1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "amdgpu_gfx.h" 27 #include "amdgpu_ucode.h" 28 #include "clearstate_si.h" 29 #include "bif/bif_3_0_d.h" 30 #include "bif/bif_3_0_sh_mask.h" 31 #include "oss/oss_1_0_d.h" 32 #include "oss/oss_1_0_sh_mask.h" 33 #include "gca/gfx_6_0_d.h" 34 #include "gca/gfx_6_0_sh_mask.h" 35 #include "gmc/gmc_6_0_d.h" 36 #include "gmc/gmc_6_0_sh_mask.h" 37 #include "dce/dce_6_0_d.h" 38 #include "dce/dce_6_0_sh_mask.h" 39 #include "gca/gfx_7_2_enum.h" 40 #include "si_enums.h" 41 #include "si.h" 42 43 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 44 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 45 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 46 47 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin"); 48 MODULE_FIRMWARE("amdgpu/tahiti_me.bin"); 49 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin"); 50 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin"); 51 52 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin"); 53 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin"); 54 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin"); 55 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin"); 56 57 MODULE_FIRMWARE("amdgpu/verde_pfp.bin"); 58 MODULE_FIRMWARE("amdgpu/verde_me.bin"); 59 MODULE_FIRMWARE("amdgpu/verde_ce.bin"); 60 MODULE_FIRMWARE("amdgpu/verde_rlc.bin"); 61 62 MODULE_FIRMWARE("amdgpu/oland_pfp.bin"); 63 MODULE_FIRMWARE("amdgpu/oland_me.bin"); 64 MODULE_FIRMWARE("amdgpu/oland_ce.bin"); 65 MODULE_FIRMWARE("amdgpu/oland_rlc.bin"); 66 67 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin"); 68 MODULE_FIRMWARE("amdgpu/hainan_me.bin"); 69 MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); 70 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); 71 72 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 73 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 74 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 75 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 76 77 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 78 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 79 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 80 #define MICRO_TILE_MODE(x) ((x) << 0) 81 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 82 #define BANK_WIDTH(x) ((x) << 14) 83 #define BANK_HEIGHT(x) ((x) << 16) 84 #define MACRO_TILE_ASPECT(x) ((x) << 18) 85 #define NUM_BANKS(x) ((x) << 20) 86 87 static const u32 verde_rlc_save_restore_register_list[] = 88 { 89 (0x8000 << 16) | (0x98f4 >> 2), 90 0x00000000, 91 (0x8040 << 16) | (0x98f4 >> 2), 92 0x00000000, 93 (0x8000 << 16) | (0xe80 >> 2), 94 0x00000000, 95 (0x8040 << 16) | (0xe80 >> 2), 96 0x00000000, 97 (0x8000 << 16) | (0x89bc >> 2), 98 0x00000000, 99 (0x8040 << 16) | (0x89bc >> 2), 100 0x00000000, 101 (0x8000 << 16) | (0x8c1c >> 2), 102 0x00000000, 103 (0x8040 << 16) | (0x8c1c >> 2), 104 0x00000000, 105 (0x9c00 << 16) | (0x98f0 >> 2), 106 0x00000000, 107 (0x9c00 << 16) | (0xe7c >> 2), 108 0x00000000, 109 (0x8000 << 16) | (0x9148 >> 2), 110 0x00000000, 111 (0x8040 << 16) | (0x9148 >> 2), 112 0x00000000, 113 (0x9c00 << 16) | (0x9150 >> 2), 114 0x00000000, 115 (0x9c00 << 16) | (0x897c >> 2), 116 0x00000000, 117 (0x9c00 << 16) | (0x8d8c >> 2), 118 0x00000000, 119 (0x9c00 << 16) | (0xac54 >> 2), 120 0X00000000, 121 0x3, 122 (0x9c00 << 16) | (0x98f8 >> 2), 123 0x00000000, 124 (0x9c00 << 16) | (0x9910 >> 2), 125 0x00000000, 126 (0x9c00 << 16) | (0x9914 >> 2), 127 0x00000000, 128 (0x9c00 << 16) | (0x9918 >> 2), 129 0x00000000, 130 (0x9c00 << 16) | (0x991c >> 2), 131 0x00000000, 132 (0x9c00 << 16) | (0x9920 >> 2), 133 0x00000000, 134 (0x9c00 << 16) | (0x9924 >> 2), 135 0x00000000, 136 (0x9c00 << 16) | (0x9928 >> 2), 137 0x00000000, 138 (0x9c00 << 16) | (0x992c >> 2), 139 0x00000000, 140 (0x9c00 << 16) | (0x9930 >> 2), 141 0x00000000, 142 (0x9c00 << 16) | (0x9934 >> 2), 143 0x00000000, 144 (0x9c00 << 16) | (0x9938 >> 2), 145 0x00000000, 146 (0x9c00 << 16) | (0x993c >> 2), 147 0x00000000, 148 (0x9c00 << 16) | (0x9940 >> 2), 149 0x00000000, 150 (0x9c00 << 16) | (0x9944 >> 2), 151 0x00000000, 152 (0x9c00 << 16) | (0x9948 >> 2), 153 0x00000000, 154 (0x9c00 << 16) | (0x994c >> 2), 155 0x00000000, 156 (0x9c00 << 16) | (0x9950 >> 2), 157 0x00000000, 158 (0x9c00 << 16) | (0x9954 >> 2), 159 0x00000000, 160 (0x9c00 << 16) | (0x9958 >> 2), 161 0x00000000, 162 (0x9c00 << 16) | (0x995c >> 2), 163 0x00000000, 164 (0x9c00 << 16) | (0x9960 >> 2), 165 0x00000000, 166 (0x9c00 << 16) | (0x9964 >> 2), 167 0x00000000, 168 (0x9c00 << 16) | (0x9968 >> 2), 169 0x00000000, 170 (0x9c00 << 16) | (0x996c >> 2), 171 0x00000000, 172 (0x9c00 << 16) | (0x9970 >> 2), 173 0x00000000, 174 (0x9c00 << 16) | (0x9974 >> 2), 175 0x00000000, 176 (0x9c00 << 16) | (0x9978 >> 2), 177 0x00000000, 178 (0x9c00 << 16) | (0x997c >> 2), 179 0x00000000, 180 (0x9c00 << 16) | (0x9980 >> 2), 181 0x00000000, 182 (0x9c00 << 16) | (0x9984 >> 2), 183 0x00000000, 184 (0x9c00 << 16) | (0x9988 >> 2), 185 0x00000000, 186 (0x9c00 << 16) | (0x998c >> 2), 187 0x00000000, 188 (0x9c00 << 16) | (0x8c00 >> 2), 189 0x00000000, 190 (0x9c00 << 16) | (0x8c14 >> 2), 191 0x00000000, 192 (0x9c00 << 16) | (0x8c04 >> 2), 193 0x00000000, 194 (0x9c00 << 16) | (0x8c08 >> 2), 195 0x00000000, 196 (0x8000 << 16) | (0x9b7c >> 2), 197 0x00000000, 198 (0x8040 << 16) | (0x9b7c >> 2), 199 0x00000000, 200 (0x8000 << 16) | (0xe84 >> 2), 201 0x00000000, 202 (0x8040 << 16) | (0xe84 >> 2), 203 0x00000000, 204 (0x8000 << 16) | (0x89c0 >> 2), 205 0x00000000, 206 (0x8040 << 16) | (0x89c0 >> 2), 207 0x00000000, 208 (0x8000 << 16) | (0x914c >> 2), 209 0x00000000, 210 (0x8040 << 16) | (0x914c >> 2), 211 0x00000000, 212 (0x8000 << 16) | (0x8c20 >> 2), 213 0x00000000, 214 (0x8040 << 16) | (0x8c20 >> 2), 215 0x00000000, 216 (0x8000 << 16) | (0x9354 >> 2), 217 0x00000000, 218 (0x8040 << 16) | (0x9354 >> 2), 219 0x00000000, 220 (0x9c00 << 16) | (0x9060 >> 2), 221 0x00000000, 222 (0x9c00 << 16) | (0x9364 >> 2), 223 0x00000000, 224 (0x9c00 << 16) | (0x9100 >> 2), 225 0x00000000, 226 (0x9c00 << 16) | (0x913c >> 2), 227 0x00000000, 228 (0x8000 << 16) | (0x90e0 >> 2), 229 0x00000000, 230 (0x8000 << 16) | (0x90e4 >> 2), 231 0x00000000, 232 (0x8000 << 16) | (0x90e8 >> 2), 233 0x00000000, 234 (0x8040 << 16) | (0x90e0 >> 2), 235 0x00000000, 236 (0x8040 << 16) | (0x90e4 >> 2), 237 0x00000000, 238 (0x8040 << 16) | (0x90e8 >> 2), 239 0x00000000, 240 (0x9c00 << 16) | (0x8bcc >> 2), 241 0x00000000, 242 (0x9c00 << 16) | (0x8b24 >> 2), 243 0x00000000, 244 (0x9c00 << 16) | (0x88c4 >> 2), 245 0x00000000, 246 (0x9c00 << 16) | (0x8e50 >> 2), 247 0x00000000, 248 (0x9c00 << 16) | (0x8c0c >> 2), 249 0x00000000, 250 (0x9c00 << 16) | (0x8e58 >> 2), 251 0x00000000, 252 (0x9c00 << 16) | (0x8e5c >> 2), 253 0x00000000, 254 (0x9c00 << 16) | (0x9508 >> 2), 255 0x00000000, 256 (0x9c00 << 16) | (0x950c >> 2), 257 0x00000000, 258 (0x9c00 << 16) | (0x9494 >> 2), 259 0x00000000, 260 (0x9c00 << 16) | (0xac0c >> 2), 261 0x00000000, 262 (0x9c00 << 16) | (0xac10 >> 2), 263 0x00000000, 264 (0x9c00 << 16) | (0xac14 >> 2), 265 0x00000000, 266 (0x9c00 << 16) | (0xae00 >> 2), 267 0x00000000, 268 (0x9c00 << 16) | (0xac08 >> 2), 269 0x00000000, 270 (0x9c00 << 16) | (0x88d4 >> 2), 271 0x00000000, 272 (0x9c00 << 16) | (0x88c8 >> 2), 273 0x00000000, 274 (0x9c00 << 16) | (0x88cc >> 2), 275 0x00000000, 276 (0x9c00 << 16) | (0x89b0 >> 2), 277 0x00000000, 278 (0x9c00 << 16) | (0x8b10 >> 2), 279 0x00000000, 280 (0x9c00 << 16) | (0x8a14 >> 2), 281 0x00000000, 282 (0x9c00 << 16) | (0x9830 >> 2), 283 0x00000000, 284 (0x9c00 << 16) | (0x9834 >> 2), 285 0x00000000, 286 (0x9c00 << 16) | (0x9838 >> 2), 287 0x00000000, 288 (0x9c00 << 16) | (0x9a10 >> 2), 289 0x00000000, 290 (0x8000 << 16) | (0x9870 >> 2), 291 0x00000000, 292 (0x8000 << 16) | (0x9874 >> 2), 293 0x00000000, 294 (0x8001 << 16) | (0x9870 >> 2), 295 0x00000000, 296 (0x8001 << 16) | (0x9874 >> 2), 297 0x00000000, 298 (0x8040 << 16) | (0x9870 >> 2), 299 0x00000000, 300 (0x8040 << 16) | (0x9874 >> 2), 301 0x00000000, 302 (0x8041 << 16) | (0x9870 >> 2), 303 0x00000000, 304 (0x8041 << 16) | (0x9874 >> 2), 305 0x00000000, 306 0x00000000 307 }; 308 309 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 310 { 311 const char *chip_name; 312 char fw_name[30]; 313 int err; 314 const struct gfx_firmware_header_v1_0 *cp_hdr; 315 const struct rlc_firmware_header_v1_0 *rlc_hdr; 316 317 DRM_DEBUG("\n"); 318 319 switch (adev->asic_type) { 320 case CHIP_TAHITI: 321 chip_name = "tahiti"; 322 break; 323 case CHIP_PITCAIRN: 324 chip_name = "pitcairn"; 325 break; 326 case CHIP_VERDE: 327 chip_name = "verde"; 328 break; 329 case CHIP_OLAND: 330 chip_name = "oland"; 331 break; 332 case CHIP_HAINAN: 333 chip_name = "hainan"; 334 break; 335 default: BUG(); 336 } 337 338 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 339 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 340 if (err) 341 goto out; 342 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 343 if (err) 344 goto out; 345 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 346 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 347 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 348 349 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 350 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 351 if (err) 352 goto out; 353 err = amdgpu_ucode_validate(adev->gfx.me_fw); 354 if (err) 355 goto out; 356 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 357 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 358 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 359 360 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 361 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 362 if (err) 363 goto out; 364 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 365 if (err) 366 goto out; 367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 368 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 369 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 370 371 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 372 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 373 if (err) 374 goto out; 375 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 376 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 377 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 378 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 379 380 out: 381 if (err) { 382 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name); 383 release_firmware(adev->gfx.pfp_fw); 384 adev->gfx.pfp_fw = NULL; 385 release_firmware(adev->gfx.me_fw); 386 adev->gfx.me_fw = NULL; 387 release_firmware(adev->gfx.ce_fw); 388 adev->gfx.ce_fw = NULL; 389 release_firmware(adev->gfx.rlc_fw); 390 adev->gfx.rlc_fw = NULL; 391 } 392 return err; 393 } 394 395 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 396 { 397 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 398 u32 reg_offset, split_equal_to_row_size, *tilemode; 399 400 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 401 tilemode = adev->gfx.config.tile_mode_array; 402 403 switch (adev->gfx.config.mem_row_size_in_kb) { 404 case 1: 405 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 406 break; 407 case 2: 408 default: 409 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 410 break; 411 case 4: 412 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 413 break; 414 } 415 416 if (adev->asic_type == CHIP_VERDE) { 417 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 418 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 419 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 421 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 424 NUM_BANKS(ADDR_SURF_16_BANK); 425 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 426 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 427 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 428 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 429 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 432 NUM_BANKS(ADDR_SURF_16_BANK); 433 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 434 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 435 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 436 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 437 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 440 NUM_BANKS(ADDR_SURF_16_BANK); 441 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 442 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 443 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 447 NUM_BANKS(ADDR_SURF_8_BANK) | 448 TILE_SPLIT(split_equal_to_row_size); 449 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 450 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 451 PIPE_CONFIG(ADDR_SURF_P4_8x16); 452 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 453 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 454 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 456 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 459 NUM_BANKS(ADDR_SURF_4_BANK); 460 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 461 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 462 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 464 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 466 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 467 NUM_BANKS(ADDR_SURF_4_BANK); 468 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 469 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 470 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 475 NUM_BANKS(ADDR_SURF_2_BANK); 476 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 477 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 478 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 479 PIPE_CONFIG(ADDR_SURF_P4_8x16); 480 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 481 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 482 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 483 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 484 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 487 NUM_BANKS(ADDR_SURF_16_BANK); 488 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 489 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 490 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 492 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 495 NUM_BANKS(ADDR_SURF_16_BANK); 496 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 497 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 498 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 499 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 500 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 501 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 502 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 503 NUM_BANKS(ADDR_SURF_16_BANK); 504 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 505 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 506 PIPE_CONFIG(ADDR_SURF_P4_8x16); 507 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 508 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 509 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 510 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 514 NUM_BANKS(ADDR_SURF_16_BANK); 515 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 516 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 517 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 519 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 522 NUM_BANKS(ADDR_SURF_16_BANK); 523 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 524 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 525 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 527 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 530 NUM_BANKS(ADDR_SURF_16_BANK); 531 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 532 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 533 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 534 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 537 NUM_BANKS(ADDR_SURF_16_BANK) | 538 TILE_SPLIT(split_equal_to_row_size); 539 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 540 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 541 PIPE_CONFIG(ADDR_SURF_P4_8x16); 542 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 543 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 544 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 545 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 548 NUM_BANKS(ADDR_SURF_16_BANK) | 549 TILE_SPLIT(split_equal_to_row_size); 550 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 551 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 552 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 556 NUM_BANKS(ADDR_SURF_16_BANK) | 557 TILE_SPLIT(split_equal_to_row_size); 558 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 559 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 560 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 562 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 563 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 564 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 565 NUM_BANKS(ADDR_SURF_8_BANK); 566 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 568 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 569 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 570 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 571 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 572 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 573 NUM_BANKS(ADDR_SURF_8_BANK); 574 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 575 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 576 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 577 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 579 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 580 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 581 NUM_BANKS(ADDR_SURF_4_BANK); 582 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 583 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 584 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 585 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 586 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 587 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 588 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 589 NUM_BANKS(ADDR_SURF_4_BANK); 590 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 591 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 592 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 593 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 597 NUM_BANKS(ADDR_SURF_2_BANK); 598 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 599 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 600 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 602 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 603 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 604 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 605 NUM_BANKS(ADDR_SURF_2_BANK); 606 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 607 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 608 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 609 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 610 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 611 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 612 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 613 NUM_BANKS(ADDR_SURF_2_BANK); 614 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 615 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 616 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 617 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 618 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 621 NUM_BANKS(ADDR_SURF_2_BANK); 622 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 623 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 624 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 625 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 626 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 629 NUM_BANKS(ADDR_SURF_2_BANK); 630 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 631 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 632 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 634 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 637 NUM_BANKS(ADDR_SURF_2_BANK); 638 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 639 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 640 } else if (adev->asic_type == CHIP_OLAND) { 641 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 643 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 645 NUM_BANKS(ADDR_SURF_16_BANK) | 646 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 649 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 650 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 651 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 652 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 653 NUM_BANKS(ADDR_SURF_16_BANK) | 654 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 657 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 658 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 659 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 660 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 661 NUM_BANKS(ADDR_SURF_16_BANK) | 662 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 665 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 666 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 667 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 668 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 669 NUM_BANKS(ADDR_SURF_16_BANK) | 670 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 673 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 674 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 675 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 676 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 677 NUM_BANKS(ADDR_SURF_16_BANK) | 678 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 681 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 683 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 684 TILE_SPLIT(split_equal_to_row_size) | 685 NUM_BANKS(ADDR_SURF_16_BANK) | 686 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 687 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 688 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 689 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 690 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 691 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 692 TILE_SPLIT(split_equal_to_row_size) | 693 NUM_BANKS(ADDR_SURF_16_BANK) | 694 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 697 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 698 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 699 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 700 TILE_SPLIT(split_equal_to_row_size) | 701 NUM_BANKS(ADDR_SURF_16_BANK) | 702 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 703 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 704 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 705 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 706 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 707 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 708 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 709 NUM_BANKS(ADDR_SURF_16_BANK) | 710 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 711 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 712 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 713 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 714 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 715 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 716 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 717 NUM_BANKS(ADDR_SURF_16_BANK) | 718 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 721 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 722 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 723 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 725 NUM_BANKS(ADDR_SURF_16_BANK) | 726 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 727 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 728 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 729 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 730 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 731 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 732 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 733 NUM_BANKS(ADDR_SURF_16_BANK) | 734 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 737 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 738 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 739 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 740 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 741 NUM_BANKS(ADDR_SURF_16_BANK) | 742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 745 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 746 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 747 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 748 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 749 NUM_BANKS(ADDR_SURF_16_BANK) | 750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 753 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 754 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 755 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 756 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 757 NUM_BANKS(ADDR_SURF_16_BANK) | 758 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 759 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 760 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 761 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 762 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 763 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 764 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 765 NUM_BANKS(ADDR_SURF_16_BANK) | 766 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 767 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 768 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 769 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 770 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 771 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 772 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 773 NUM_BANKS(ADDR_SURF_16_BANK) | 774 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 775 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 776 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 777 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 778 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 779 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 780 TILE_SPLIT(split_equal_to_row_size) | 781 NUM_BANKS(ADDR_SURF_16_BANK) | 782 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 785 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 786 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 787 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 789 NUM_BANKS(ADDR_SURF_16_BANK) | 790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 791 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 792 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 793 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 794 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 795 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 796 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 797 NUM_BANKS(ADDR_SURF_16_BANK) | 798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 801 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 802 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 803 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 804 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 805 NUM_BANKS(ADDR_SURF_16_BANK) | 806 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 807 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 808 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 809 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 810 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 811 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 812 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 813 NUM_BANKS(ADDR_SURF_16_BANK) | 814 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 815 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 816 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 817 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 818 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 819 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 820 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 821 NUM_BANKS(ADDR_SURF_8_BANK) | 822 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); 825 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 826 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 827 } else if (adev->asic_type == CHIP_HAINAN) { 828 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 829 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 830 PIPE_CONFIG(ADDR_SURF_P2) | 831 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 832 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 835 NUM_BANKS(ADDR_SURF_16_BANK); 836 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 837 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 838 PIPE_CONFIG(ADDR_SURF_P2) | 839 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 840 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 843 NUM_BANKS(ADDR_SURF_16_BANK); 844 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 845 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 846 PIPE_CONFIG(ADDR_SURF_P2) | 847 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 848 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 851 NUM_BANKS(ADDR_SURF_16_BANK); 852 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 853 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 854 PIPE_CONFIG(ADDR_SURF_P2) | 855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 858 NUM_BANKS(ADDR_SURF_8_BANK) | 859 TILE_SPLIT(split_equal_to_row_size); 860 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 861 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 862 PIPE_CONFIG(ADDR_SURF_P2); 863 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 864 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 865 PIPE_CONFIG(ADDR_SURF_P2) | 866 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 867 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 868 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 869 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 870 NUM_BANKS(ADDR_SURF_8_BANK); 871 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 872 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 873 PIPE_CONFIG(ADDR_SURF_P2) | 874 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 875 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 876 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 877 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 878 NUM_BANKS(ADDR_SURF_8_BANK); 879 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 880 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 881 PIPE_CONFIG(ADDR_SURF_P2) | 882 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 883 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 884 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 885 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 886 NUM_BANKS(ADDR_SURF_4_BANK); 887 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 888 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 889 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 890 PIPE_CONFIG(ADDR_SURF_P2); 891 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 892 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 893 PIPE_CONFIG(ADDR_SURF_P2) | 894 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 895 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 896 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 897 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 898 NUM_BANKS(ADDR_SURF_16_BANK); 899 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 900 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 901 PIPE_CONFIG(ADDR_SURF_P2) | 902 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 903 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 904 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 905 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 906 NUM_BANKS(ADDR_SURF_16_BANK); 907 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 908 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 909 PIPE_CONFIG(ADDR_SURF_P2) | 910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 911 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 912 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 913 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 914 NUM_BANKS(ADDR_SURF_16_BANK); 915 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 916 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 917 PIPE_CONFIG(ADDR_SURF_P2); 918 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 919 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 920 PIPE_CONFIG(ADDR_SURF_P2) | 921 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 922 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 925 NUM_BANKS(ADDR_SURF_16_BANK); 926 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 927 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 928 PIPE_CONFIG(ADDR_SURF_P2) | 929 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 933 NUM_BANKS(ADDR_SURF_16_BANK); 934 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 935 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 936 PIPE_CONFIG(ADDR_SURF_P2) | 937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 941 NUM_BANKS(ADDR_SURF_16_BANK); 942 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 943 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 944 PIPE_CONFIG(ADDR_SURF_P2) | 945 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 946 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 947 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 948 NUM_BANKS(ADDR_SURF_16_BANK) | 949 TILE_SPLIT(split_equal_to_row_size); 950 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 951 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 952 PIPE_CONFIG(ADDR_SURF_P2); 953 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 954 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 955 PIPE_CONFIG(ADDR_SURF_P2) | 956 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 957 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 958 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 959 NUM_BANKS(ADDR_SURF_16_BANK) | 960 TILE_SPLIT(split_equal_to_row_size); 961 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 962 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 963 PIPE_CONFIG(ADDR_SURF_P2) | 964 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 967 NUM_BANKS(ADDR_SURF_16_BANK) | 968 TILE_SPLIT(split_equal_to_row_size); 969 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 970 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 971 PIPE_CONFIG(ADDR_SURF_P2) | 972 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 973 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 974 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 975 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 976 NUM_BANKS(ADDR_SURF_8_BANK); 977 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 978 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 979 PIPE_CONFIG(ADDR_SURF_P2) | 980 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 981 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 982 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 983 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 984 NUM_BANKS(ADDR_SURF_8_BANK); 985 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 986 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 987 PIPE_CONFIG(ADDR_SURF_P2) | 988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 989 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 992 NUM_BANKS(ADDR_SURF_8_BANK); 993 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 994 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 995 PIPE_CONFIG(ADDR_SURF_P2) | 996 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 997 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 998 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 999 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1000 NUM_BANKS(ADDR_SURF_8_BANK); 1001 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1002 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1003 PIPE_CONFIG(ADDR_SURF_P2) | 1004 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1005 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1006 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1007 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1008 NUM_BANKS(ADDR_SURF_4_BANK); 1009 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1010 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1011 PIPE_CONFIG(ADDR_SURF_P2) | 1012 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1013 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1014 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1015 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1016 NUM_BANKS(ADDR_SURF_4_BANK); 1017 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1018 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1019 PIPE_CONFIG(ADDR_SURF_P2) | 1020 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1021 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1022 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1023 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1024 NUM_BANKS(ADDR_SURF_4_BANK); 1025 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1026 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1027 PIPE_CONFIG(ADDR_SURF_P2) | 1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1029 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1032 NUM_BANKS(ADDR_SURF_4_BANK); 1033 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1034 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1035 PIPE_CONFIG(ADDR_SURF_P2) | 1036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1037 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1038 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1039 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1040 NUM_BANKS(ADDR_SURF_4_BANK); 1041 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1042 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1043 PIPE_CONFIG(ADDR_SURF_P2) | 1044 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1045 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1046 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1047 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1048 NUM_BANKS(ADDR_SURF_4_BANK); 1049 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1050 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1051 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1052 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1053 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1054 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1059 NUM_BANKS(ADDR_SURF_16_BANK); 1060 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1061 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1062 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1064 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1065 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1066 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1067 NUM_BANKS(ADDR_SURF_16_BANK); 1068 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1069 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1070 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1071 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1072 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1073 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1074 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1075 NUM_BANKS(ADDR_SURF_16_BANK); 1076 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1077 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1078 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1079 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1082 NUM_BANKS(ADDR_SURF_4_BANK) | 1083 TILE_SPLIT(split_equal_to_row_size); 1084 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1085 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1086 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1087 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1088 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1089 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1091 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1092 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1093 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1094 NUM_BANKS(ADDR_SURF_2_BANK); 1095 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1096 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1099 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1100 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1101 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1102 NUM_BANKS(ADDR_SURF_2_BANK); 1103 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1104 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1105 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1107 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1108 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1109 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1110 NUM_BANKS(ADDR_SURF_2_BANK); 1111 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 1112 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1113 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1114 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1115 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1116 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1119 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1120 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1121 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1122 NUM_BANKS(ADDR_SURF_16_BANK); 1123 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1124 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1125 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1126 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1127 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1128 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1129 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1130 NUM_BANKS(ADDR_SURF_16_BANK); 1131 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1132 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1135 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1138 NUM_BANKS(ADDR_SURF_16_BANK); 1139 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1140 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1141 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1142 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1143 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1144 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1149 NUM_BANKS(ADDR_SURF_16_BANK); 1150 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1151 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1152 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1154 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1157 NUM_BANKS(ADDR_SURF_16_BANK); 1158 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1159 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1160 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1162 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1165 NUM_BANKS(ADDR_SURF_16_BANK); 1166 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1167 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1168 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1172 NUM_BANKS(ADDR_SURF_16_BANK) | 1173 TILE_SPLIT(split_equal_to_row_size); 1174 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1175 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1176 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1177 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1178 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1179 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1180 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1183 NUM_BANKS(ADDR_SURF_16_BANK) | 1184 TILE_SPLIT(split_equal_to_row_size); 1185 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1186 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1187 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1188 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1191 NUM_BANKS(ADDR_SURF_16_BANK) | 1192 TILE_SPLIT(split_equal_to_row_size); 1193 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1194 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1195 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1196 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1197 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1200 NUM_BANKS(ADDR_SURF_4_BANK); 1201 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1202 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1203 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1205 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1208 NUM_BANKS(ADDR_SURF_4_BANK); 1209 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1210 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1211 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1212 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1213 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1216 NUM_BANKS(ADDR_SURF_2_BANK); 1217 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1218 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1219 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1220 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1221 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1222 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1223 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1224 NUM_BANKS(ADDR_SURF_2_BANK); 1225 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1226 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1227 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1228 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1232 NUM_BANKS(ADDR_SURF_2_BANK); 1233 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1234 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1235 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1236 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1240 NUM_BANKS(ADDR_SURF_2_BANK); 1241 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1242 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1243 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1244 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1245 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1246 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1247 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1248 NUM_BANKS(ADDR_SURF_2_BANK); 1249 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1250 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1251 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1252 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1253 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1256 NUM_BANKS(ADDR_SURF_2_BANK); 1257 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1258 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1259 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1260 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1261 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1264 NUM_BANKS(ADDR_SURF_2_BANK); 1265 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1266 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1267 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1268 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1272 NUM_BANKS(ADDR_SURF_2_BANK); 1273 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1274 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1275 } else { 1276 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1277 } 1278 } 1279 1280 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1281 u32 sh_num, u32 instance) 1282 { 1283 u32 data; 1284 1285 if (instance == 0xffffffff) 1286 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1287 else 1288 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1289 1290 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1291 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1292 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1293 else if (se_num == 0xffffffff) 1294 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1295 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1296 else if (sh_num == 0xffffffff) 1297 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1298 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1299 else 1300 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1301 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1302 WREG32(mmGRBM_GFX_INDEX, data); 1303 } 1304 1305 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1306 { 1307 u32 data, mask; 1308 1309 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1310 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1311 1312 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1313 1314 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1315 adev->gfx.config.max_sh_per_se); 1316 1317 return ~data & mask; 1318 } 1319 1320 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1321 { 1322 switch (adev->asic_type) { 1323 case CHIP_TAHITI: 1324 case CHIP_PITCAIRN: 1325 *rconf |= 1326 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1327 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1328 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1329 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1330 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1331 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1332 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1333 break; 1334 case CHIP_VERDE: 1335 *rconf |= 1336 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1337 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1338 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1339 break; 1340 case CHIP_OLAND: 1341 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1342 break; 1343 case CHIP_HAINAN: 1344 *rconf |= 0x0; 1345 break; 1346 default: 1347 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1348 break; 1349 } 1350 } 1351 1352 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1353 u32 raster_config, unsigned rb_mask, 1354 unsigned num_rb) 1355 { 1356 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1357 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1358 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1359 unsigned rb_per_se = num_rb / num_se; 1360 unsigned se_mask[4]; 1361 unsigned se; 1362 1363 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1364 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1365 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1366 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1367 1368 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1369 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1370 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1371 1372 for (se = 0; se < num_se; se++) { 1373 unsigned raster_config_se = raster_config; 1374 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1375 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1376 int idx = (se / 2) * 2; 1377 1378 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1379 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1380 1381 if (!se_mask[idx]) 1382 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1383 else 1384 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1385 } 1386 1387 pkr0_mask &= rb_mask; 1388 pkr1_mask &= rb_mask; 1389 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1390 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1391 1392 if (!pkr0_mask) 1393 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1394 else 1395 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1396 } 1397 1398 if (rb_per_se >= 2) { 1399 unsigned rb0_mask = 1 << (se * rb_per_se); 1400 unsigned rb1_mask = rb0_mask << 1; 1401 1402 rb0_mask &= rb_mask; 1403 rb1_mask &= rb_mask; 1404 if (!rb0_mask || !rb1_mask) { 1405 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1406 1407 if (!rb0_mask) 1408 raster_config_se |= 1409 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1410 else 1411 raster_config_se |= 1412 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1413 } 1414 1415 if (rb_per_se > 2) { 1416 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1417 rb1_mask = rb0_mask << 1; 1418 rb0_mask &= rb_mask; 1419 rb1_mask &= rb_mask; 1420 if (!rb0_mask || !rb1_mask) { 1421 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1422 1423 if (!rb0_mask) 1424 raster_config_se |= 1425 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1426 else 1427 raster_config_se |= 1428 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1429 } 1430 } 1431 } 1432 1433 /* GRBM_GFX_INDEX has a different offset on SI */ 1434 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1435 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1436 } 1437 1438 /* GRBM_GFX_INDEX has a different offset on SI */ 1439 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1440 } 1441 1442 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1443 { 1444 int i, j; 1445 u32 data; 1446 u32 raster_config = 0; 1447 u32 active_rbs = 0; 1448 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1449 adev->gfx.config.max_sh_per_se; 1450 unsigned num_rb_pipes; 1451 1452 mutex_lock(&adev->grbm_idx_mutex); 1453 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1454 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1455 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1456 data = gfx_v6_0_get_rb_active_bitmap(adev); 1457 active_rbs |= data << 1458 ((i * adev->gfx.config.max_sh_per_se + j) * 1459 rb_bitmap_width_per_sh); 1460 } 1461 } 1462 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1463 1464 adev->gfx.config.backend_enable_mask = active_rbs; 1465 adev->gfx.config.num_rbs = hweight32(active_rbs); 1466 1467 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1468 adev->gfx.config.max_shader_engines, 16); 1469 1470 gfx_v6_0_raster_config(adev, &raster_config); 1471 1472 if (!adev->gfx.config.backend_enable_mask || 1473 adev->gfx.config.num_rbs >= num_rb_pipes) 1474 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1475 else 1476 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1477 adev->gfx.config.backend_enable_mask, 1478 num_rb_pipes); 1479 1480 /* cache the values for userspace */ 1481 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1482 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1483 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1484 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1485 RREG32(mmCC_RB_BACKEND_DISABLE); 1486 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1487 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1488 adev->gfx.config.rb_config[i][j].raster_config = 1489 RREG32(mmPA_SC_RASTER_CONFIG); 1490 } 1491 } 1492 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1493 mutex_unlock(&adev->grbm_idx_mutex); 1494 } 1495 1496 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1497 u32 bitmap) 1498 { 1499 u32 data; 1500 1501 if (!bitmap) 1502 return; 1503 1504 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1505 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1506 1507 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1508 } 1509 1510 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1511 { 1512 u32 data, mask; 1513 1514 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1515 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1516 1517 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1518 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1519 } 1520 1521 1522 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1523 { 1524 int i, j, k; 1525 u32 data, mask; 1526 u32 active_cu = 0; 1527 1528 mutex_lock(&adev->grbm_idx_mutex); 1529 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1530 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1531 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1532 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1533 active_cu = gfx_v6_0_get_cu_enabled(adev); 1534 1535 mask = 1; 1536 for (k = 0; k < 16; k++) { 1537 mask <<= k; 1538 if (active_cu & mask) { 1539 data &= ~mask; 1540 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1541 break; 1542 } 1543 } 1544 } 1545 } 1546 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1547 mutex_unlock(&adev->grbm_idx_mutex); 1548 } 1549 1550 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1551 { 1552 adev->gfx.config.double_offchip_lds_buf = 0; 1553 } 1554 1555 static void gfx_v6_0_constants_init(struct amdgpu_device *adev) 1556 { 1557 u32 gb_addr_config = 0; 1558 u32 mc_shared_chmap, mc_arb_ramcfg; 1559 u32 sx_debug_1; 1560 u32 hdp_host_path_cntl; 1561 u32 tmp; 1562 1563 switch (adev->asic_type) { 1564 case CHIP_TAHITI: 1565 adev->gfx.config.max_shader_engines = 2; 1566 adev->gfx.config.max_tile_pipes = 12; 1567 adev->gfx.config.max_cu_per_sh = 8; 1568 adev->gfx.config.max_sh_per_se = 2; 1569 adev->gfx.config.max_backends_per_se = 4; 1570 adev->gfx.config.max_texture_channel_caches = 12; 1571 adev->gfx.config.max_gprs = 256; 1572 adev->gfx.config.max_gs_threads = 32; 1573 adev->gfx.config.max_hw_contexts = 8; 1574 1575 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1576 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1577 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1578 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1579 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1580 break; 1581 case CHIP_PITCAIRN: 1582 adev->gfx.config.max_shader_engines = 2; 1583 adev->gfx.config.max_tile_pipes = 8; 1584 adev->gfx.config.max_cu_per_sh = 5; 1585 adev->gfx.config.max_sh_per_se = 2; 1586 adev->gfx.config.max_backends_per_se = 4; 1587 adev->gfx.config.max_texture_channel_caches = 8; 1588 adev->gfx.config.max_gprs = 256; 1589 adev->gfx.config.max_gs_threads = 32; 1590 adev->gfx.config.max_hw_contexts = 8; 1591 1592 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1593 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1594 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1595 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1596 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1597 break; 1598 case CHIP_VERDE: 1599 adev->gfx.config.max_shader_engines = 1; 1600 adev->gfx.config.max_tile_pipes = 4; 1601 adev->gfx.config.max_cu_per_sh = 5; 1602 adev->gfx.config.max_sh_per_se = 2; 1603 adev->gfx.config.max_backends_per_se = 4; 1604 adev->gfx.config.max_texture_channel_caches = 4; 1605 adev->gfx.config.max_gprs = 256; 1606 adev->gfx.config.max_gs_threads = 32; 1607 adev->gfx.config.max_hw_contexts = 8; 1608 1609 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1610 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1611 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1612 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1613 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1614 break; 1615 case CHIP_OLAND: 1616 adev->gfx.config.max_shader_engines = 1; 1617 adev->gfx.config.max_tile_pipes = 4; 1618 adev->gfx.config.max_cu_per_sh = 6; 1619 adev->gfx.config.max_sh_per_se = 1; 1620 adev->gfx.config.max_backends_per_se = 2; 1621 adev->gfx.config.max_texture_channel_caches = 4; 1622 adev->gfx.config.max_gprs = 256; 1623 adev->gfx.config.max_gs_threads = 16; 1624 adev->gfx.config.max_hw_contexts = 8; 1625 1626 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1627 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1628 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1629 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1630 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1631 break; 1632 case CHIP_HAINAN: 1633 adev->gfx.config.max_shader_engines = 1; 1634 adev->gfx.config.max_tile_pipes = 4; 1635 adev->gfx.config.max_cu_per_sh = 5; 1636 adev->gfx.config.max_sh_per_se = 1; 1637 adev->gfx.config.max_backends_per_se = 1; 1638 adev->gfx.config.max_texture_channel_caches = 2; 1639 adev->gfx.config.max_gprs = 256; 1640 adev->gfx.config.max_gs_threads = 16; 1641 adev->gfx.config.max_hw_contexts = 8; 1642 1643 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1644 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1645 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1646 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1647 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1648 break; 1649 default: 1650 BUG(); 1651 break; 1652 } 1653 1654 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1655 WREG32(mmSRBM_INT_CNTL, 1); 1656 WREG32(mmSRBM_INT_ACK, 1); 1657 1658 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1659 1660 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 1661 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1662 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1663 1664 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1665 adev->gfx.config.mem_max_burst_length_bytes = 256; 1666 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1667 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1668 if (adev->gfx.config.mem_row_size_in_kb > 4) 1669 adev->gfx.config.mem_row_size_in_kb = 4; 1670 adev->gfx.config.shader_engine_tile_size = 32; 1671 adev->gfx.config.num_gpus = 1; 1672 adev->gfx.config.multi_gpu_tile_size = 64; 1673 1674 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1675 switch (adev->gfx.config.mem_row_size_in_kb) { 1676 case 1: 1677 default: 1678 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1679 break; 1680 case 2: 1681 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1682 break; 1683 case 4: 1684 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1685 break; 1686 } 1687 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1688 if (adev->gfx.config.max_shader_engines == 2) 1689 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1690 adev->gfx.config.gb_addr_config = gb_addr_config; 1691 1692 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1693 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1694 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1695 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1696 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1697 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1698 1699 #if 0 1700 if (adev->has_uvd) { 1701 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1702 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1703 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1704 } 1705 #endif 1706 gfx_v6_0_tiling_mode_table_init(adev); 1707 1708 gfx_v6_0_setup_rb(adev); 1709 1710 gfx_v6_0_setup_spi(adev); 1711 1712 gfx_v6_0_get_cu_info(adev); 1713 gfx_v6_0_config_init(adev); 1714 1715 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1716 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1717 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1718 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1719 1720 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1721 WREG32(mmSX_DEBUG_1, sx_debug_1); 1722 1723 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1724 1725 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1726 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1727 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1728 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1729 1730 WREG32(mmVGT_NUM_INSTANCES, 1); 1731 WREG32(mmCP_PERFMON_CNTL, 0); 1732 WREG32(mmSQ_CONFIG, 0); 1733 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1734 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1735 1736 WREG32(mmVGT_CACHE_INVALIDATION, 1737 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1738 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1739 1740 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1741 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1742 1743 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1744 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1745 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1746 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1747 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1748 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1749 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1750 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1751 1752 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1753 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1754 1755 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1756 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1757 1758 udelay(50); 1759 } 1760 1761 1762 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev) 1763 { 1764 adev->gfx.scratch.num_reg = 8; 1765 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 1766 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 1767 } 1768 1769 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1770 { 1771 struct amdgpu_device *adev = ring->adev; 1772 uint32_t scratch; 1773 uint32_t tmp = 0; 1774 unsigned i; 1775 int r; 1776 1777 r = amdgpu_gfx_scratch_get(adev, &scratch); 1778 if (r) 1779 return r; 1780 1781 WREG32(scratch, 0xCAFEDEAD); 1782 1783 r = amdgpu_ring_alloc(ring, 3); 1784 if (r) 1785 goto error_free_scratch; 1786 1787 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1788 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); 1789 amdgpu_ring_write(ring, 0xDEADBEEF); 1790 amdgpu_ring_commit(ring); 1791 1792 for (i = 0; i < adev->usec_timeout; i++) { 1793 tmp = RREG32(scratch); 1794 if (tmp == 0xDEADBEEF) 1795 break; 1796 DRM_UDELAY(1); 1797 } 1798 1799 if (i >= adev->usec_timeout) 1800 r = -ETIMEDOUT; 1801 1802 error_free_scratch: 1803 amdgpu_gfx_scratch_free(adev, scratch); 1804 return r; 1805 } 1806 1807 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1808 { 1809 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1810 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1811 EVENT_INDEX(0)); 1812 } 1813 1814 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1815 u64 seq, unsigned flags) 1816 { 1817 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1818 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1819 /* flush read cache over gart */ 1820 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1821 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1822 amdgpu_ring_write(ring, 0); 1823 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1824 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1825 PACKET3_TC_ACTION_ENA | 1826 PACKET3_SH_KCACHE_ACTION_ENA | 1827 PACKET3_SH_ICACHE_ACTION_ENA); 1828 amdgpu_ring_write(ring, 0xFFFFFFFF); 1829 amdgpu_ring_write(ring, 0); 1830 amdgpu_ring_write(ring, 10); /* poll interval */ 1831 /* EVENT_WRITE_EOP - flush caches, send int */ 1832 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1833 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1834 amdgpu_ring_write(ring, addr & 0xfffffffc); 1835 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1836 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1837 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1838 amdgpu_ring_write(ring, lower_32_bits(seq)); 1839 amdgpu_ring_write(ring, upper_32_bits(seq)); 1840 } 1841 1842 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1843 struct amdgpu_job *job, 1844 struct amdgpu_ib *ib, 1845 uint32_t flags) 1846 { 1847 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1848 u32 header, control = 0; 1849 1850 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1851 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 1852 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1853 amdgpu_ring_write(ring, 0); 1854 } 1855 1856 if (ib->flags & AMDGPU_IB_FLAG_CE) 1857 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1858 else 1859 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1860 1861 control |= ib->length_dw | (vmid << 24); 1862 1863 amdgpu_ring_write(ring, header); 1864 amdgpu_ring_write(ring, 1865 #ifdef __BIG_ENDIAN 1866 (2 << 0) | 1867 #endif 1868 (ib->gpu_addr & 0xFFFFFFFC)); 1869 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1870 amdgpu_ring_write(ring, control); 1871 } 1872 1873 /** 1874 * gfx_v6_0_ring_test_ib - basic ring IB test 1875 * 1876 * @ring: amdgpu_ring structure holding ring information 1877 * 1878 * Allocate an IB and execute it on the gfx ring (SI). 1879 * Provides a basic gfx ring test to verify that IBs are working. 1880 * Returns 0 on success, error on failure. 1881 */ 1882 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1883 { 1884 struct amdgpu_device *adev = ring->adev; 1885 struct amdgpu_ib ib; 1886 struct dma_fence *f = NULL; 1887 uint32_t scratch; 1888 uint32_t tmp = 0; 1889 long r; 1890 1891 r = amdgpu_gfx_scratch_get(adev, &scratch); 1892 if (r) 1893 return r; 1894 1895 WREG32(scratch, 0xCAFEDEAD); 1896 memset(&ib, 0, sizeof(ib)); 1897 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1898 if (r) 1899 goto err1; 1900 1901 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1902 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START)); 1903 ib.ptr[2] = 0xDEADBEEF; 1904 ib.length_dw = 3; 1905 1906 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1907 if (r) 1908 goto err2; 1909 1910 r = dma_fence_wait_timeout(f, false, timeout); 1911 if (r == 0) { 1912 r = -ETIMEDOUT; 1913 goto err2; 1914 } else if (r < 0) { 1915 goto err2; 1916 } 1917 tmp = RREG32(scratch); 1918 if (tmp == 0xDEADBEEF) 1919 r = 0; 1920 else 1921 r = -EINVAL; 1922 1923 err2: 1924 amdgpu_ib_free(adev, &ib, NULL); 1925 dma_fence_put(f); 1926 err1: 1927 amdgpu_gfx_scratch_free(adev, scratch); 1928 return r; 1929 } 1930 1931 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1932 { 1933 int i; 1934 if (enable) { 1935 WREG32(mmCP_ME_CNTL, 0); 1936 } else { 1937 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 1938 CP_ME_CNTL__PFP_HALT_MASK | 1939 CP_ME_CNTL__CE_HALT_MASK)); 1940 WREG32(mmSCRATCH_UMSK, 0); 1941 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1942 adev->gfx.gfx_ring[i].sched.ready = false; 1943 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1944 adev->gfx.compute_ring[i].sched.ready = false; 1945 } 1946 udelay(50); 1947 } 1948 1949 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 1950 { 1951 unsigned i; 1952 const struct gfx_firmware_header_v1_0 *pfp_hdr; 1953 const struct gfx_firmware_header_v1_0 *ce_hdr; 1954 const struct gfx_firmware_header_v1_0 *me_hdr; 1955 const __le32 *fw_data; 1956 u32 fw_size; 1957 1958 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 1959 return -EINVAL; 1960 1961 gfx_v6_0_cp_gfx_enable(adev, false); 1962 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1963 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1964 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1965 1966 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 1967 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 1968 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 1969 1970 /* PFP */ 1971 fw_data = (const __le32 *) 1972 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1973 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1974 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1975 for (i = 0; i < fw_size; i++) 1976 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 1977 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1978 1979 /* CE */ 1980 fw_data = (const __le32 *) 1981 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 1982 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 1983 WREG32(mmCP_CE_UCODE_ADDR, 0); 1984 for (i = 0; i < fw_size; i++) 1985 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 1986 WREG32(mmCP_CE_UCODE_ADDR, 0); 1987 1988 /* ME */ 1989 fw_data = (const __be32 *) 1990 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 1991 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 1992 WREG32(mmCP_ME_RAM_WADDR, 0); 1993 for (i = 0; i < fw_size; i++) 1994 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 1995 WREG32(mmCP_ME_RAM_WADDR, 0); 1996 1997 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1998 WREG32(mmCP_CE_UCODE_ADDR, 0); 1999 WREG32(mmCP_ME_RAM_WADDR, 0); 2000 WREG32(mmCP_ME_RAM_RADDR, 0); 2001 return 0; 2002 } 2003 2004 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 2005 { 2006 const struct cs_section_def *sect = NULL; 2007 const struct cs_extent_def *ext = NULL; 2008 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2009 int r, i; 2010 2011 r = amdgpu_ring_alloc(ring, 7 + 4); 2012 if (r) { 2013 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2014 return r; 2015 } 2016 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2017 amdgpu_ring_write(ring, 0x1); 2018 amdgpu_ring_write(ring, 0x0); 2019 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 2020 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2021 amdgpu_ring_write(ring, 0); 2022 amdgpu_ring_write(ring, 0); 2023 2024 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2025 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2026 amdgpu_ring_write(ring, 0xc000); 2027 amdgpu_ring_write(ring, 0xe000); 2028 amdgpu_ring_commit(ring); 2029 2030 gfx_v6_0_cp_gfx_enable(adev, true); 2031 2032 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2033 if (r) { 2034 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2035 return r; 2036 } 2037 2038 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2039 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2040 2041 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2042 for (ext = sect->section; ext->extent != NULL; ++ext) { 2043 if (sect->id == SECT_CONTEXT) { 2044 amdgpu_ring_write(ring, 2045 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2046 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2047 for (i = 0; i < ext->reg_count; i++) 2048 amdgpu_ring_write(ring, ext->extent[i]); 2049 } 2050 } 2051 } 2052 2053 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2054 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2055 2056 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2057 amdgpu_ring_write(ring, 0); 2058 2059 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2060 amdgpu_ring_write(ring, 0x00000316); 2061 amdgpu_ring_write(ring, 0x0000000e); 2062 amdgpu_ring_write(ring, 0x00000010); 2063 2064 amdgpu_ring_commit(ring); 2065 2066 return 0; 2067 } 2068 2069 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2070 { 2071 struct amdgpu_ring *ring; 2072 u32 tmp; 2073 u32 rb_bufsz; 2074 int r; 2075 u64 rptr_addr; 2076 2077 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2078 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2079 2080 /* Set the write pointer delay */ 2081 WREG32(mmCP_RB_WPTR_DELAY, 0); 2082 2083 WREG32(mmCP_DEBUG, 0); 2084 WREG32(mmSCRATCH_ADDR, 0); 2085 2086 /* ring 0 - compute and gfx */ 2087 /* Set ring buffer size */ 2088 ring = &adev->gfx.gfx_ring[0]; 2089 rb_bufsz = order_base_2(ring->ring_size / 8); 2090 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2091 2092 #ifdef __BIG_ENDIAN 2093 tmp |= BUF_SWAP_32BIT; 2094 #endif 2095 WREG32(mmCP_RB0_CNTL, tmp); 2096 2097 /* Initialize the ring buffer's read and write pointers */ 2098 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2099 ring->wptr = 0; 2100 WREG32(mmCP_RB0_WPTR, ring->wptr); 2101 2102 /* set the wb address whether it's enabled or not */ 2103 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2104 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2105 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2106 2107 WREG32(mmSCRATCH_UMSK, 0); 2108 2109 mdelay(1); 2110 WREG32(mmCP_RB0_CNTL, tmp); 2111 2112 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2113 2114 /* start the rings */ 2115 gfx_v6_0_cp_gfx_start(adev); 2116 r = amdgpu_ring_test_helper(ring); 2117 if (r) 2118 return r; 2119 2120 return 0; 2121 } 2122 2123 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2124 { 2125 return ring->adev->wb.wb[ring->rptr_offs]; 2126 } 2127 2128 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2129 { 2130 struct amdgpu_device *adev = ring->adev; 2131 2132 if (ring == &adev->gfx.gfx_ring[0]) 2133 return RREG32(mmCP_RB0_WPTR); 2134 else if (ring == &adev->gfx.compute_ring[0]) 2135 return RREG32(mmCP_RB1_WPTR); 2136 else if (ring == &adev->gfx.compute_ring[1]) 2137 return RREG32(mmCP_RB2_WPTR); 2138 else 2139 BUG(); 2140 } 2141 2142 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2143 { 2144 struct amdgpu_device *adev = ring->adev; 2145 2146 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2147 (void)RREG32(mmCP_RB0_WPTR); 2148 } 2149 2150 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2151 { 2152 struct amdgpu_device *adev = ring->adev; 2153 2154 if (ring == &adev->gfx.compute_ring[0]) { 2155 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2156 (void)RREG32(mmCP_RB1_WPTR); 2157 } else if (ring == &adev->gfx.compute_ring[1]) { 2158 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2159 (void)RREG32(mmCP_RB2_WPTR); 2160 } else { 2161 BUG(); 2162 } 2163 2164 } 2165 2166 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 2167 { 2168 struct amdgpu_ring *ring; 2169 u32 tmp; 2170 u32 rb_bufsz; 2171 int i, r; 2172 u64 rptr_addr; 2173 2174 /* ring1 - compute only */ 2175 /* Set ring buffer size */ 2176 2177 ring = &adev->gfx.compute_ring[0]; 2178 rb_bufsz = order_base_2(ring->ring_size / 8); 2179 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2180 #ifdef __BIG_ENDIAN 2181 tmp |= BUF_SWAP_32BIT; 2182 #endif 2183 WREG32(mmCP_RB1_CNTL, tmp); 2184 2185 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2186 ring->wptr = 0; 2187 WREG32(mmCP_RB1_WPTR, ring->wptr); 2188 2189 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2190 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2191 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2192 2193 mdelay(1); 2194 WREG32(mmCP_RB1_CNTL, tmp); 2195 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2196 2197 ring = &adev->gfx.compute_ring[1]; 2198 rb_bufsz = order_base_2(ring->ring_size / 8); 2199 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2200 #ifdef __BIG_ENDIAN 2201 tmp |= BUF_SWAP_32BIT; 2202 #endif 2203 WREG32(mmCP_RB2_CNTL, tmp); 2204 2205 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2206 ring->wptr = 0; 2207 WREG32(mmCP_RB2_WPTR, ring->wptr); 2208 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2209 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2210 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2211 2212 mdelay(1); 2213 WREG32(mmCP_RB2_CNTL, tmp); 2214 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2215 2216 2217 for (i = 0; i < 2; i++) { 2218 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]); 2219 if (r) 2220 return r; 2221 } 2222 2223 return 0; 2224 } 2225 2226 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2227 { 2228 gfx_v6_0_cp_gfx_enable(adev, enable); 2229 } 2230 2231 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2232 { 2233 return gfx_v6_0_cp_gfx_load_microcode(adev); 2234 } 2235 2236 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2237 bool enable) 2238 { 2239 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2240 u32 mask; 2241 int i; 2242 2243 if (enable) 2244 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2245 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2246 else 2247 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2248 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2249 WREG32(mmCP_INT_CNTL_RING0, tmp); 2250 2251 if (!enable) { 2252 /* read a gfx register */ 2253 tmp = RREG32(mmDB_DEPTH_INFO); 2254 2255 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2256 for (i = 0; i < adev->usec_timeout; i++) { 2257 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2258 break; 2259 udelay(1); 2260 } 2261 } 2262 } 2263 2264 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2265 { 2266 int r; 2267 2268 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2269 2270 r = gfx_v6_0_cp_load_microcode(adev); 2271 if (r) 2272 return r; 2273 2274 r = gfx_v6_0_cp_gfx_resume(adev); 2275 if (r) 2276 return r; 2277 r = gfx_v6_0_cp_compute_resume(adev); 2278 if (r) 2279 return r; 2280 2281 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2282 2283 return 0; 2284 } 2285 2286 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2287 { 2288 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2289 uint32_t seq = ring->fence_drv.sync_seq; 2290 uint64_t addr = ring->fence_drv.gpu_addr; 2291 2292 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2293 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2294 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2295 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2296 amdgpu_ring_write(ring, addr & 0xfffffffc); 2297 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2298 amdgpu_ring_write(ring, seq); 2299 amdgpu_ring_write(ring, 0xffffffff); 2300 amdgpu_ring_write(ring, 4); /* poll interval */ 2301 2302 if (usepfp) { 2303 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2304 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2305 amdgpu_ring_write(ring, 0); 2306 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2307 amdgpu_ring_write(ring, 0); 2308 } 2309 } 2310 2311 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2312 unsigned vmid, uint64_t pd_addr) 2313 { 2314 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2315 2316 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2317 2318 /* wait for the invalidate to complete */ 2319 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2320 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2321 WAIT_REG_MEM_ENGINE(0))); /* me */ 2322 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2323 amdgpu_ring_write(ring, 0); 2324 amdgpu_ring_write(ring, 0); /* ref */ 2325 amdgpu_ring_write(ring, 0); /* mask */ 2326 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2327 2328 if (usepfp) { 2329 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2330 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2331 amdgpu_ring_write(ring, 0x0); 2332 2333 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2334 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2335 amdgpu_ring_write(ring, 0); 2336 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2337 amdgpu_ring_write(ring, 0); 2338 } 2339 } 2340 2341 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 2342 uint32_t reg, uint32_t val) 2343 { 2344 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2345 2346 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2347 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 2348 WRITE_DATA_DST_SEL(0))); 2349 amdgpu_ring_write(ring, reg); 2350 amdgpu_ring_write(ring, 0); 2351 amdgpu_ring_write(ring, val); 2352 } 2353 2354 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2355 { 2356 const u32 *src_ptr; 2357 volatile u32 *dst_ptr; 2358 u32 dws; 2359 u64 reg_list_mc_addr; 2360 const struct cs_section_def *cs_data; 2361 int r; 2362 2363 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2364 adev->gfx.rlc.reg_list_size = 2365 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2366 2367 adev->gfx.rlc.cs_data = si_cs_data; 2368 src_ptr = adev->gfx.rlc.reg_list; 2369 dws = adev->gfx.rlc.reg_list_size; 2370 cs_data = adev->gfx.rlc.cs_data; 2371 2372 if (src_ptr) { 2373 /* init save restore block */ 2374 r = amdgpu_gfx_rlc_init_sr(adev, dws); 2375 if (r) 2376 return r; 2377 } 2378 2379 if (cs_data) { 2380 /* clear state block */ 2381 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2382 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2383 2384 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2385 AMDGPU_GEM_DOMAIN_VRAM, 2386 &adev->gfx.rlc.clear_state_obj, 2387 &adev->gfx.rlc.clear_state_gpu_addr, 2388 (void **)&adev->gfx.rlc.cs_ptr); 2389 if (r) { 2390 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2391 amdgpu_gfx_rlc_fini(adev); 2392 return r; 2393 } 2394 2395 /* set up the cs buffer */ 2396 dst_ptr = adev->gfx.rlc.cs_ptr; 2397 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2398 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2399 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2400 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2401 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2402 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2403 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2404 } 2405 2406 return 0; 2407 } 2408 2409 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2410 { 2411 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2412 2413 if (!enable) { 2414 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2415 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2416 } 2417 } 2418 2419 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2420 { 2421 int i; 2422 2423 for (i = 0; i < adev->usec_timeout; i++) { 2424 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2425 break; 2426 udelay(1); 2427 } 2428 2429 for (i = 0; i < adev->usec_timeout; i++) { 2430 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2431 break; 2432 udelay(1); 2433 } 2434 } 2435 2436 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2437 { 2438 u32 tmp; 2439 2440 tmp = RREG32(mmRLC_CNTL); 2441 if (tmp != rlc) 2442 WREG32(mmRLC_CNTL, rlc); 2443 } 2444 2445 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2446 { 2447 u32 data, orig; 2448 2449 orig = data = RREG32(mmRLC_CNTL); 2450 2451 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2452 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2453 WREG32(mmRLC_CNTL, data); 2454 2455 gfx_v6_0_wait_for_rlc_serdes(adev); 2456 } 2457 2458 return orig; 2459 } 2460 2461 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2462 { 2463 WREG32(mmRLC_CNTL, 0); 2464 2465 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2466 gfx_v6_0_wait_for_rlc_serdes(adev); 2467 } 2468 2469 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2470 { 2471 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2472 2473 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2474 2475 udelay(50); 2476 } 2477 2478 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2479 { 2480 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2481 udelay(50); 2482 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2483 udelay(50); 2484 } 2485 2486 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2487 { 2488 u32 tmp; 2489 2490 /* Enable LBPW only for DDR3 */ 2491 tmp = RREG32(mmMC_SEQ_MISC0); 2492 if ((tmp & 0xF0000000) == 0xB0000000) 2493 return true; 2494 return false; 2495 } 2496 2497 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2498 { 2499 } 2500 2501 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2502 { 2503 u32 i; 2504 const struct rlc_firmware_header_v1_0 *hdr; 2505 const __le32 *fw_data; 2506 u32 fw_size; 2507 2508 2509 if (!adev->gfx.rlc_fw) 2510 return -EINVAL; 2511 2512 adev->gfx.rlc.funcs->stop(adev); 2513 adev->gfx.rlc.funcs->reset(adev); 2514 gfx_v6_0_init_pg(adev); 2515 gfx_v6_0_init_cg(adev); 2516 2517 WREG32(mmRLC_RL_BASE, 0); 2518 WREG32(mmRLC_RL_SIZE, 0); 2519 WREG32(mmRLC_LB_CNTL, 0); 2520 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2521 WREG32(mmRLC_LB_CNTR_INIT, 0); 2522 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2523 2524 WREG32(mmRLC_MC_CNTL, 0); 2525 WREG32(mmRLC_UCODE_CNTL, 0); 2526 2527 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2528 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2529 fw_data = (const __le32 *) 2530 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2531 2532 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2533 2534 for (i = 0; i < fw_size; i++) { 2535 WREG32(mmRLC_UCODE_ADDR, i); 2536 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2537 } 2538 WREG32(mmRLC_UCODE_ADDR, 0); 2539 2540 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2541 adev->gfx.rlc.funcs->start(adev); 2542 2543 return 0; 2544 } 2545 2546 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2547 { 2548 u32 data, orig, tmp; 2549 2550 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2551 2552 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2553 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2554 2555 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2556 2557 tmp = gfx_v6_0_halt_rlc(adev); 2558 2559 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2560 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2561 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2562 2563 gfx_v6_0_wait_for_rlc_serdes(adev); 2564 gfx_v6_0_update_rlc(adev, tmp); 2565 2566 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2567 2568 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2569 } else { 2570 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2571 2572 RREG32(mmCB_CGTT_SCLK_CTRL); 2573 RREG32(mmCB_CGTT_SCLK_CTRL); 2574 RREG32(mmCB_CGTT_SCLK_CTRL); 2575 RREG32(mmCB_CGTT_SCLK_CTRL); 2576 2577 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2578 } 2579 2580 if (orig != data) 2581 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2582 2583 } 2584 2585 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2586 { 2587 2588 u32 data, orig, tmp = 0; 2589 2590 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2591 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2592 data = 0x96940200; 2593 if (orig != data) 2594 WREG32(mmCGTS_SM_CTRL_REG, data); 2595 2596 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2597 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2598 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2599 if (orig != data) 2600 WREG32(mmCP_MEM_SLP_CNTL, data); 2601 } 2602 2603 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2604 data &= 0xffffffc0; 2605 if (orig != data) 2606 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2607 2608 tmp = gfx_v6_0_halt_rlc(adev); 2609 2610 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2611 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2612 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2613 2614 gfx_v6_0_update_rlc(adev, tmp); 2615 } else { 2616 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2617 data |= 0x00000003; 2618 if (orig != data) 2619 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2620 2621 data = RREG32(mmCP_MEM_SLP_CNTL); 2622 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2623 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2624 WREG32(mmCP_MEM_SLP_CNTL, data); 2625 } 2626 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2627 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2628 if (orig != data) 2629 WREG32(mmCGTS_SM_CTRL_REG, data); 2630 2631 tmp = gfx_v6_0_halt_rlc(adev); 2632 2633 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2634 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2635 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2636 2637 gfx_v6_0_update_rlc(adev, tmp); 2638 } 2639 } 2640 /* 2641 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2642 bool enable) 2643 { 2644 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2645 if (enable) { 2646 gfx_v6_0_enable_mgcg(adev, true); 2647 gfx_v6_0_enable_cgcg(adev, true); 2648 } else { 2649 gfx_v6_0_enable_cgcg(adev, false); 2650 gfx_v6_0_enable_mgcg(adev, false); 2651 } 2652 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2653 } 2654 */ 2655 2656 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2657 bool enable) 2658 { 2659 } 2660 2661 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2662 bool enable) 2663 { 2664 } 2665 2666 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2667 { 2668 u32 data, orig; 2669 2670 orig = data = RREG32(mmRLC_PG_CNTL); 2671 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2672 data &= ~0x8000; 2673 else 2674 data |= 0x8000; 2675 if (orig != data) 2676 WREG32(mmRLC_PG_CNTL, data); 2677 } 2678 2679 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2680 { 2681 } 2682 /* 2683 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2684 { 2685 const __le32 *fw_data; 2686 volatile u32 *dst_ptr; 2687 int me, i, max_me = 4; 2688 u32 bo_offset = 0; 2689 u32 table_offset, table_size; 2690 2691 if (adev->asic_type == CHIP_KAVERI) 2692 max_me = 5; 2693 2694 if (adev->gfx.rlc.cp_table_ptr == NULL) 2695 return; 2696 2697 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2698 for (me = 0; me < max_me; me++) { 2699 if (me == 0) { 2700 const struct gfx_firmware_header_v1_0 *hdr = 2701 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2702 fw_data = (const __le32 *) 2703 (adev->gfx.ce_fw->data + 2704 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2705 table_offset = le32_to_cpu(hdr->jt_offset); 2706 table_size = le32_to_cpu(hdr->jt_size); 2707 } else if (me == 1) { 2708 const struct gfx_firmware_header_v1_0 *hdr = 2709 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2710 fw_data = (const __le32 *) 2711 (adev->gfx.pfp_fw->data + 2712 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2713 table_offset = le32_to_cpu(hdr->jt_offset); 2714 table_size = le32_to_cpu(hdr->jt_size); 2715 } else if (me == 2) { 2716 const struct gfx_firmware_header_v1_0 *hdr = 2717 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2718 fw_data = (const __le32 *) 2719 (adev->gfx.me_fw->data + 2720 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2721 table_offset = le32_to_cpu(hdr->jt_offset); 2722 table_size = le32_to_cpu(hdr->jt_size); 2723 } else if (me == 3) { 2724 const struct gfx_firmware_header_v1_0 *hdr = 2725 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2726 fw_data = (const __le32 *) 2727 (adev->gfx.mec_fw->data + 2728 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2729 table_offset = le32_to_cpu(hdr->jt_offset); 2730 table_size = le32_to_cpu(hdr->jt_size); 2731 } else { 2732 const struct gfx_firmware_header_v1_0 *hdr = 2733 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2734 fw_data = (const __le32 *) 2735 (adev->gfx.mec2_fw->data + 2736 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2737 table_offset = le32_to_cpu(hdr->jt_offset); 2738 table_size = le32_to_cpu(hdr->jt_size); 2739 } 2740 2741 for (i = 0; i < table_size; i ++) { 2742 dst_ptr[bo_offset + i] = 2743 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2744 } 2745 2746 bo_offset += table_size; 2747 } 2748 } 2749 */ 2750 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2751 bool enable) 2752 { 2753 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2754 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2755 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2756 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2757 } else { 2758 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2759 (void)RREG32(mmDB_RENDER_CONTROL); 2760 } 2761 } 2762 2763 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2764 { 2765 u32 tmp; 2766 2767 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2768 2769 tmp = RREG32(mmRLC_MAX_PG_CU); 2770 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2771 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2772 WREG32(mmRLC_MAX_PG_CU, tmp); 2773 } 2774 2775 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2776 bool enable) 2777 { 2778 u32 data, orig; 2779 2780 orig = data = RREG32(mmRLC_PG_CNTL); 2781 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2782 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2783 else 2784 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2785 if (orig != data) 2786 WREG32(mmRLC_PG_CNTL, data); 2787 } 2788 2789 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2790 bool enable) 2791 { 2792 u32 data, orig; 2793 2794 orig = data = RREG32(mmRLC_PG_CNTL); 2795 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2796 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2797 else 2798 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2799 if (orig != data) 2800 WREG32(mmRLC_PG_CNTL, data); 2801 } 2802 2803 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2804 { 2805 u32 tmp; 2806 2807 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2808 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2809 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2810 2811 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2812 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2813 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2814 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2815 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2816 } 2817 2818 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2819 { 2820 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2821 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2822 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2823 } 2824 2825 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2826 { 2827 u32 count = 0; 2828 const struct cs_section_def *sect = NULL; 2829 const struct cs_extent_def *ext = NULL; 2830 2831 if (adev->gfx.rlc.cs_data == NULL) 2832 return 0; 2833 2834 /* begin clear state */ 2835 count += 2; 2836 /* context control state */ 2837 count += 3; 2838 2839 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2840 for (ext = sect->section; ext->extent != NULL; ++ext) { 2841 if (sect->id == SECT_CONTEXT) 2842 count += 2 + ext->reg_count; 2843 else 2844 return 0; 2845 } 2846 } 2847 /* pa_sc_raster_config */ 2848 count += 3; 2849 /* end clear state */ 2850 count += 2; 2851 /* clear state */ 2852 count += 2; 2853 2854 return count; 2855 } 2856 2857 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 2858 volatile u32 *buffer) 2859 { 2860 u32 count = 0, i; 2861 const struct cs_section_def *sect = NULL; 2862 const struct cs_extent_def *ext = NULL; 2863 2864 if (adev->gfx.rlc.cs_data == NULL) 2865 return; 2866 if (buffer == NULL) 2867 return; 2868 2869 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2870 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2871 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2872 buffer[count++] = cpu_to_le32(0x80000000); 2873 buffer[count++] = cpu_to_le32(0x80000000); 2874 2875 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2876 for (ext = sect->section; ext->extent != NULL; ++ext) { 2877 if (sect->id == SECT_CONTEXT) { 2878 buffer[count++] = 2879 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2880 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); 2881 for (i = 0; i < ext->reg_count; i++) 2882 buffer[count++] = cpu_to_le32(ext->extent[i]); 2883 } else { 2884 return; 2885 } 2886 } 2887 } 2888 2889 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2890 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2891 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 2892 2893 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2894 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 2895 2896 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 2897 buffer[count++] = cpu_to_le32(0); 2898 } 2899 2900 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2901 { 2902 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2903 AMD_PG_SUPPORT_GFX_SMG | 2904 AMD_PG_SUPPORT_GFX_DMG | 2905 AMD_PG_SUPPORT_CP | 2906 AMD_PG_SUPPORT_GDS | 2907 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2908 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2909 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2910 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2911 gfx_v6_0_init_gfx_cgpg(adev); 2912 gfx_v6_0_enable_cp_pg(adev, true); 2913 gfx_v6_0_enable_gds_pg(adev, true); 2914 } else { 2915 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2916 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2917 2918 } 2919 gfx_v6_0_init_ao_cu_mask(adev); 2920 gfx_v6_0_update_gfx_pg(adev, true); 2921 } else { 2922 2923 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2924 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2925 } 2926 } 2927 2928 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 2929 { 2930 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2931 AMD_PG_SUPPORT_GFX_SMG | 2932 AMD_PG_SUPPORT_GFX_DMG | 2933 AMD_PG_SUPPORT_CP | 2934 AMD_PG_SUPPORT_GDS | 2935 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2936 gfx_v6_0_update_gfx_pg(adev, false); 2937 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2938 gfx_v6_0_enable_cp_pg(adev, false); 2939 gfx_v6_0_enable_gds_pg(adev, false); 2940 } 2941 } 2942 } 2943 2944 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 2945 { 2946 uint64_t clock; 2947 2948 mutex_lock(&adev->gfx.gpu_clock_mutex); 2949 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2950 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 2951 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2952 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2953 return clock; 2954 } 2955 2956 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2957 { 2958 if (flags & AMDGPU_HAVE_CTX_SWITCH) 2959 gfx_v6_0_ring_emit_vgt_flush(ring); 2960 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2961 amdgpu_ring_write(ring, 0x80000000); 2962 amdgpu_ring_write(ring, 0); 2963 } 2964 2965 2966 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 2967 { 2968 WREG32(mmSQ_IND_INDEX, 2969 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2970 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2971 (address << SQ_IND_INDEX__INDEX__SHIFT) | 2972 (SQ_IND_INDEX__FORCE_READ_MASK)); 2973 return RREG32(mmSQ_IND_DATA); 2974 } 2975 2976 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 2977 uint32_t wave, uint32_t thread, 2978 uint32_t regno, uint32_t num, uint32_t *out) 2979 { 2980 WREG32(mmSQ_IND_INDEX, 2981 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2982 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2983 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 2984 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 2985 (SQ_IND_INDEX__FORCE_READ_MASK) | 2986 (SQ_IND_INDEX__AUTO_INCR_MASK)); 2987 while (num--) 2988 *(out++) = RREG32(mmSQ_IND_DATA); 2989 } 2990 2991 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 2992 { 2993 /* type 0 wave data */ 2994 dst[(*no_fields)++] = 0; 2995 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 2996 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 2997 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 2998 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 2999 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 3000 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 3001 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 3002 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 3003 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 3004 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 3005 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 3006 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 3007 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 3008 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 3009 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 3010 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 3011 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 3012 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 3013 } 3014 3015 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 3016 uint32_t wave, uint32_t start, 3017 uint32_t size, uint32_t *dst) 3018 { 3019 wave_read_regs( 3020 adev, simd, wave, 0, 3021 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3022 } 3023 3024 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, 3025 u32 me, u32 pipe, u32 q) 3026 { 3027 DRM_INFO("Not implemented\n"); 3028 } 3029 3030 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3031 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3032 .select_se_sh = &gfx_v6_0_select_se_sh, 3033 .read_wave_data = &gfx_v6_0_read_wave_data, 3034 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3035 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q 3036 }; 3037 3038 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { 3039 .init = gfx_v6_0_rlc_init, 3040 .resume = gfx_v6_0_rlc_resume, 3041 .stop = gfx_v6_0_rlc_stop, 3042 .reset = gfx_v6_0_rlc_reset, 3043 .start = gfx_v6_0_rlc_start 3044 }; 3045 3046 static int gfx_v6_0_early_init(void *handle) 3047 { 3048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3049 3050 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3051 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS; 3052 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3053 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; 3054 gfx_v6_0_set_ring_funcs(adev); 3055 gfx_v6_0_set_irq_funcs(adev); 3056 3057 return 0; 3058 } 3059 3060 static int gfx_v6_0_sw_init(void *handle) 3061 { 3062 struct amdgpu_ring *ring; 3063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3064 int i, r; 3065 3066 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3067 if (r) 3068 return r; 3069 3070 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3071 if (r) 3072 return r; 3073 3074 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3075 if (r) 3076 return r; 3077 3078 gfx_v6_0_scratch_init(adev); 3079 3080 r = gfx_v6_0_init_microcode(adev); 3081 if (r) { 3082 DRM_ERROR("Failed to load gfx firmware!\n"); 3083 return r; 3084 } 3085 3086 r = adev->gfx.rlc.funcs->init(adev); 3087 if (r) { 3088 DRM_ERROR("Failed to init rlc BOs!\n"); 3089 return r; 3090 } 3091 3092 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3093 ring = &adev->gfx.gfx_ring[i]; 3094 ring->ring_obj = NULL; 3095 sprintf(ring->name, "gfx"); 3096 r = amdgpu_ring_init(adev, ring, 1024, 3097 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 3098 if (r) 3099 return r; 3100 } 3101 3102 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3103 unsigned irq_type; 3104 3105 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3106 DRM_ERROR("Too many (%d) compute rings!\n", i); 3107 break; 3108 } 3109 ring = &adev->gfx.compute_ring[i]; 3110 ring->ring_obj = NULL; 3111 ring->use_doorbell = false; 3112 ring->doorbell_index = 0; 3113 ring->me = 1; 3114 ring->pipe = i; 3115 ring->queue = i; 3116 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3117 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3118 r = amdgpu_ring_init(adev, ring, 1024, 3119 &adev->gfx.eop_irq, irq_type); 3120 if (r) 3121 return r; 3122 } 3123 3124 return r; 3125 } 3126 3127 static int gfx_v6_0_sw_fini(void *handle) 3128 { 3129 int i; 3130 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3131 3132 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3133 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3134 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3135 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3136 3137 amdgpu_gfx_rlc_fini(adev); 3138 3139 return 0; 3140 } 3141 3142 static int gfx_v6_0_hw_init(void *handle) 3143 { 3144 int r; 3145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3146 3147 gfx_v6_0_constants_init(adev); 3148 3149 r = adev->gfx.rlc.funcs->resume(adev); 3150 if (r) 3151 return r; 3152 3153 r = gfx_v6_0_cp_resume(adev); 3154 if (r) 3155 return r; 3156 3157 adev->gfx.ce_ram_size = 0x8000; 3158 3159 return r; 3160 } 3161 3162 static int gfx_v6_0_hw_fini(void *handle) 3163 { 3164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3165 3166 gfx_v6_0_cp_enable(adev, false); 3167 adev->gfx.rlc.funcs->stop(adev); 3168 gfx_v6_0_fini_pg(adev); 3169 3170 return 0; 3171 } 3172 3173 static int gfx_v6_0_suspend(void *handle) 3174 { 3175 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3176 3177 return gfx_v6_0_hw_fini(adev); 3178 } 3179 3180 static int gfx_v6_0_resume(void *handle) 3181 { 3182 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3183 3184 return gfx_v6_0_hw_init(adev); 3185 } 3186 3187 static bool gfx_v6_0_is_idle(void *handle) 3188 { 3189 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3190 3191 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3192 return false; 3193 else 3194 return true; 3195 } 3196 3197 static int gfx_v6_0_wait_for_idle(void *handle) 3198 { 3199 unsigned i; 3200 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3201 3202 for (i = 0; i < adev->usec_timeout; i++) { 3203 if (gfx_v6_0_is_idle(handle)) 3204 return 0; 3205 udelay(1); 3206 } 3207 return -ETIMEDOUT; 3208 } 3209 3210 static int gfx_v6_0_soft_reset(void *handle) 3211 { 3212 return 0; 3213 } 3214 3215 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3216 enum amdgpu_interrupt_state state) 3217 { 3218 u32 cp_int_cntl; 3219 3220 switch (state) { 3221 case AMDGPU_IRQ_STATE_DISABLE: 3222 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3223 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3224 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3225 break; 3226 case AMDGPU_IRQ_STATE_ENABLE: 3227 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3228 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3229 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3230 break; 3231 default: 3232 break; 3233 } 3234 } 3235 3236 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3237 int ring, 3238 enum amdgpu_interrupt_state state) 3239 { 3240 u32 cp_int_cntl; 3241 switch (state){ 3242 case AMDGPU_IRQ_STATE_DISABLE: 3243 if (ring == 0) { 3244 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3245 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3246 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3247 break; 3248 } else { 3249 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3250 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3251 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3252 break; 3253 3254 } 3255 case AMDGPU_IRQ_STATE_ENABLE: 3256 if (ring == 0) { 3257 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3258 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3259 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3260 break; 3261 } else { 3262 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3263 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3264 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3265 break; 3266 3267 } 3268 3269 default: 3270 BUG(); 3271 break; 3272 3273 } 3274 } 3275 3276 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3277 struct amdgpu_irq_src *src, 3278 unsigned type, 3279 enum amdgpu_interrupt_state state) 3280 { 3281 u32 cp_int_cntl; 3282 3283 switch (state) { 3284 case AMDGPU_IRQ_STATE_DISABLE: 3285 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3286 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3287 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3288 break; 3289 case AMDGPU_IRQ_STATE_ENABLE: 3290 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3291 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3292 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3293 break; 3294 default: 3295 break; 3296 } 3297 3298 return 0; 3299 } 3300 3301 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3302 struct amdgpu_irq_src *src, 3303 unsigned type, 3304 enum amdgpu_interrupt_state state) 3305 { 3306 u32 cp_int_cntl; 3307 3308 switch (state) { 3309 case AMDGPU_IRQ_STATE_DISABLE: 3310 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3311 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3312 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3313 break; 3314 case AMDGPU_IRQ_STATE_ENABLE: 3315 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3316 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3317 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3318 break; 3319 default: 3320 break; 3321 } 3322 3323 return 0; 3324 } 3325 3326 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3327 struct amdgpu_irq_src *src, 3328 unsigned type, 3329 enum amdgpu_interrupt_state state) 3330 { 3331 switch (type) { 3332 case AMDGPU_CP_IRQ_GFX_EOP: 3333 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3334 break; 3335 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3336 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3337 break; 3338 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3339 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3340 break; 3341 default: 3342 break; 3343 } 3344 return 0; 3345 } 3346 3347 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3348 struct amdgpu_irq_src *source, 3349 struct amdgpu_iv_entry *entry) 3350 { 3351 switch (entry->ring_id) { 3352 case 0: 3353 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3354 break; 3355 case 1: 3356 case 2: 3357 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3358 break; 3359 default: 3360 break; 3361 } 3362 return 0; 3363 } 3364 3365 static void gfx_v6_0_fault(struct amdgpu_device *adev, 3366 struct amdgpu_iv_entry *entry) 3367 { 3368 struct amdgpu_ring *ring; 3369 3370 switch (entry->ring_id) { 3371 case 0: 3372 ring = &adev->gfx.gfx_ring[0]; 3373 break; 3374 case 1: 3375 case 2: 3376 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; 3377 break; 3378 default: 3379 return; 3380 } 3381 drm_sched_fault(&ring->sched); 3382 } 3383 3384 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3385 struct amdgpu_irq_src *source, 3386 struct amdgpu_iv_entry *entry) 3387 { 3388 DRM_ERROR("Illegal register access in command stream\n"); 3389 gfx_v6_0_fault(adev, entry); 3390 return 0; 3391 } 3392 3393 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3394 struct amdgpu_irq_src *source, 3395 struct amdgpu_iv_entry *entry) 3396 { 3397 DRM_ERROR("Illegal instruction in command stream\n"); 3398 gfx_v6_0_fault(adev, entry); 3399 return 0; 3400 } 3401 3402 static int gfx_v6_0_set_clockgating_state(void *handle, 3403 enum amd_clockgating_state state) 3404 { 3405 bool gate = false; 3406 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3407 3408 if (state == AMD_CG_STATE_GATE) 3409 gate = true; 3410 3411 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3412 if (gate) { 3413 gfx_v6_0_enable_mgcg(adev, true); 3414 gfx_v6_0_enable_cgcg(adev, true); 3415 } else { 3416 gfx_v6_0_enable_cgcg(adev, false); 3417 gfx_v6_0_enable_mgcg(adev, false); 3418 } 3419 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3420 3421 return 0; 3422 } 3423 3424 static int gfx_v6_0_set_powergating_state(void *handle, 3425 enum amd_powergating_state state) 3426 { 3427 bool gate = false; 3428 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3429 3430 if (state == AMD_PG_STATE_GATE) 3431 gate = true; 3432 3433 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3434 AMD_PG_SUPPORT_GFX_SMG | 3435 AMD_PG_SUPPORT_GFX_DMG | 3436 AMD_PG_SUPPORT_CP | 3437 AMD_PG_SUPPORT_GDS | 3438 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3439 gfx_v6_0_update_gfx_pg(adev, gate); 3440 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3441 gfx_v6_0_enable_cp_pg(adev, gate); 3442 gfx_v6_0_enable_gds_pg(adev, gate); 3443 } 3444 } 3445 3446 return 0; 3447 } 3448 3449 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3450 .name = "gfx_v6_0", 3451 .early_init = gfx_v6_0_early_init, 3452 .late_init = NULL, 3453 .sw_init = gfx_v6_0_sw_init, 3454 .sw_fini = gfx_v6_0_sw_fini, 3455 .hw_init = gfx_v6_0_hw_init, 3456 .hw_fini = gfx_v6_0_hw_fini, 3457 .suspend = gfx_v6_0_suspend, 3458 .resume = gfx_v6_0_resume, 3459 .is_idle = gfx_v6_0_is_idle, 3460 .wait_for_idle = gfx_v6_0_wait_for_idle, 3461 .soft_reset = gfx_v6_0_soft_reset, 3462 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3463 .set_powergating_state = gfx_v6_0_set_powergating_state, 3464 }; 3465 3466 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3467 .type = AMDGPU_RING_TYPE_GFX, 3468 .align_mask = 0xff, 3469 .nop = 0x80000000, 3470 .support_64bit_ptrs = false, 3471 .get_rptr = gfx_v6_0_ring_get_rptr, 3472 .get_wptr = gfx_v6_0_ring_get_wptr, 3473 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3474 .emit_frame_size = 3475 5 + 5 + /* hdp flush / invalidate */ 3476 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3477 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3478 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3479 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3480 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3481 .emit_ib = gfx_v6_0_ring_emit_ib, 3482 .emit_fence = gfx_v6_0_ring_emit_fence, 3483 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3484 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3485 .test_ring = gfx_v6_0_ring_test_ring, 3486 .test_ib = gfx_v6_0_ring_test_ib, 3487 .insert_nop = amdgpu_ring_insert_nop, 3488 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3489 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3490 }; 3491 3492 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3493 .type = AMDGPU_RING_TYPE_COMPUTE, 3494 .align_mask = 0xff, 3495 .nop = 0x80000000, 3496 .get_rptr = gfx_v6_0_ring_get_rptr, 3497 .get_wptr = gfx_v6_0_ring_get_wptr, 3498 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3499 .emit_frame_size = 3500 5 + 5 + /* hdp flush / invalidate */ 3501 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3502 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ 3503 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3504 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3505 .emit_ib = gfx_v6_0_ring_emit_ib, 3506 .emit_fence = gfx_v6_0_ring_emit_fence, 3507 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3508 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3509 .test_ring = gfx_v6_0_ring_test_ring, 3510 .test_ib = gfx_v6_0_ring_test_ib, 3511 .insert_nop = amdgpu_ring_insert_nop, 3512 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3513 }; 3514 3515 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3516 { 3517 int i; 3518 3519 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3520 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3521 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3522 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3523 } 3524 3525 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3526 .set = gfx_v6_0_set_eop_interrupt_state, 3527 .process = gfx_v6_0_eop_irq, 3528 }; 3529 3530 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3531 .set = gfx_v6_0_set_priv_reg_fault_state, 3532 .process = gfx_v6_0_priv_reg_irq, 3533 }; 3534 3535 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3536 .set = gfx_v6_0_set_priv_inst_fault_state, 3537 .process = gfx_v6_0_priv_inst_irq, 3538 }; 3539 3540 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3541 { 3542 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3543 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3544 3545 adev->gfx.priv_reg_irq.num_types = 1; 3546 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3547 3548 adev->gfx.priv_inst_irq.num_types = 1; 3549 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3550 } 3551 3552 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3553 { 3554 int i, j, k, counter, active_cu_number = 0; 3555 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3556 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3557 unsigned disable_masks[4 * 2]; 3558 u32 ao_cu_num; 3559 3560 if (adev->flags & AMD_IS_APU) 3561 ao_cu_num = 2; 3562 else 3563 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3564 3565 memset(cu_info, 0, sizeof(*cu_info)); 3566 3567 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 3568 3569 mutex_lock(&adev->grbm_idx_mutex); 3570 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3571 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3572 mask = 1; 3573 ao_bitmap = 0; 3574 counter = 0; 3575 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 3576 if (i < 4 && j < 2) 3577 gfx_v6_0_set_user_cu_inactive_bitmap( 3578 adev, disable_masks[i * 2 + j]); 3579 bitmap = gfx_v6_0_get_cu_enabled(adev); 3580 cu_info->bitmap[i][j] = bitmap; 3581 3582 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3583 if (bitmap & mask) { 3584 if (counter < ao_cu_num) 3585 ao_bitmap |= mask; 3586 counter ++; 3587 } 3588 mask <<= 1; 3589 } 3590 active_cu_number += counter; 3591 if (i < 2 && j < 2) 3592 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3593 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3594 } 3595 } 3596 3597 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3598 mutex_unlock(&adev->grbm_idx_mutex); 3599 3600 cu_info->number = active_cu_number; 3601 cu_info->ao_cu_mask = ao_cu_mask; 3602 } 3603 3604 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3605 { 3606 .type = AMD_IP_BLOCK_TYPE_GFX, 3607 .major = 6, 3608 .minor = 0, 3609 .rev = 0, 3610 .funcs = &gfx_v6_0_ip_funcs, 3611 }; 3612