1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "amdgpu_gfx.h" 27 #include "amdgpu_ucode.h" 28 #include "clearstate_si.h" 29 #include "bif/bif_3_0_d.h" 30 #include "bif/bif_3_0_sh_mask.h" 31 #include "oss/oss_1_0_d.h" 32 #include "oss/oss_1_0_sh_mask.h" 33 #include "gca/gfx_6_0_d.h" 34 #include "gca/gfx_6_0_sh_mask.h" 35 #include "gmc/gmc_6_0_d.h" 36 #include "gmc/gmc_6_0_sh_mask.h" 37 #include "dce/dce_6_0_d.h" 38 #include "dce/dce_6_0_sh_mask.h" 39 #include "gca/gfx_7_2_enum.h" 40 #include "si_enums.h" 41 42 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 43 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 44 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 45 46 MODULE_FIRMWARE("radeon/tahiti_pfp.bin"); 47 MODULE_FIRMWARE("radeon/tahiti_me.bin"); 48 MODULE_FIRMWARE("radeon/tahiti_ce.bin"); 49 MODULE_FIRMWARE("radeon/tahiti_rlc.bin"); 50 51 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin"); 52 MODULE_FIRMWARE("radeon/pitcairn_me.bin"); 53 MODULE_FIRMWARE("radeon/pitcairn_ce.bin"); 54 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin"); 55 56 MODULE_FIRMWARE("radeon/verde_pfp.bin"); 57 MODULE_FIRMWARE("radeon/verde_me.bin"); 58 MODULE_FIRMWARE("radeon/verde_ce.bin"); 59 MODULE_FIRMWARE("radeon/verde_rlc.bin"); 60 61 MODULE_FIRMWARE("radeon/oland_pfp.bin"); 62 MODULE_FIRMWARE("radeon/oland_me.bin"); 63 MODULE_FIRMWARE("radeon/oland_ce.bin"); 64 MODULE_FIRMWARE("radeon/oland_rlc.bin"); 65 66 MODULE_FIRMWARE("radeon/hainan_pfp.bin"); 67 MODULE_FIRMWARE("radeon/hainan_me.bin"); 68 MODULE_FIRMWARE("radeon/hainan_ce.bin"); 69 MODULE_FIRMWARE("radeon/hainan_rlc.bin"); 70 71 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 72 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 73 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 74 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 75 76 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 77 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 78 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 79 #define MICRO_TILE_MODE(x) ((x) << 0) 80 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 81 #define BANK_WIDTH(x) ((x) << 14) 82 #define BANK_HEIGHT(x) ((x) << 16) 83 #define MACRO_TILE_ASPECT(x) ((x) << 18) 84 #define NUM_BANKS(x) ((x) << 20) 85 86 static const u32 verde_rlc_save_restore_register_list[] = 87 { 88 (0x8000 << 16) | (0x98f4 >> 2), 89 0x00000000, 90 (0x8040 << 16) | (0x98f4 >> 2), 91 0x00000000, 92 (0x8000 << 16) | (0xe80 >> 2), 93 0x00000000, 94 (0x8040 << 16) | (0xe80 >> 2), 95 0x00000000, 96 (0x8000 << 16) | (0x89bc >> 2), 97 0x00000000, 98 (0x8040 << 16) | (0x89bc >> 2), 99 0x00000000, 100 (0x8000 << 16) | (0x8c1c >> 2), 101 0x00000000, 102 (0x8040 << 16) | (0x8c1c >> 2), 103 0x00000000, 104 (0x9c00 << 16) | (0x98f0 >> 2), 105 0x00000000, 106 (0x9c00 << 16) | (0xe7c >> 2), 107 0x00000000, 108 (0x8000 << 16) | (0x9148 >> 2), 109 0x00000000, 110 (0x8040 << 16) | (0x9148 >> 2), 111 0x00000000, 112 (0x9c00 << 16) | (0x9150 >> 2), 113 0x00000000, 114 (0x9c00 << 16) | (0x897c >> 2), 115 0x00000000, 116 (0x9c00 << 16) | (0x8d8c >> 2), 117 0x00000000, 118 (0x9c00 << 16) | (0xac54 >> 2), 119 0X00000000, 120 0x3, 121 (0x9c00 << 16) | (0x98f8 >> 2), 122 0x00000000, 123 (0x9c00 << 16) | (0x9910 >> 2), 124 0x00000000, 125 (0x9c00 << 16) | (0x9914 >> 2), 126 0x00000000, 127 (0x9c00 << 16) | (0x9918 >> 2), 128 0x00000000, 129 (0x9c00 << 16) | (0x991c >> 2), 130 0x00000000, 131 (0x9c00 << 16) | (0x9920 >> 2), 132 0x00000000, 133 (0x9c00 << 16) | (0x9924 >> 2), 134 0x00000000, 135 (0x9c00 << 16) | (0x9928 >> 2), 136 0x00000000, 137 (0x9c00 << 16) | (0x992c >> 2), 138 0x00000000, 139 (0x9c00 << 16) | (0x9930 >> 2), 140 0x00000000, 141 (0x9c00 << 16) | (0x9934 >> 2), 142 0x00000000, 143 (0x9c00 << 16) | (0x9938 >> 2), 144 0x00000000, 145 (0x9c00 << 16) | (0x993c >> 2), 146 0x00000000, 147 (0x9c00 << 16) | (0x9940 >> 2), 148 0x00000000, 149 (0x9c00 << 16) | (0x9944 >> 2), 150 0x00000000, 151 (0x9c00 << 16) | (0x9948 >> 2), 152 0x00000000, 153 (0x9c00 << 16) | (0x994c >> 2), 154 0x00000000, 155 (0x9c00 << 16) | (0x9950 >> 2), 156 0x00000000, 157 (0x9c00 << 16) | (0x9954 >> 2), 158 0x00000000, 159 (0x9c00 << 16) | (0x9958 >> 2), 160 0x00000000, 161 (0x9c00 << 16) | (0x995c >> 2), 162 0x00000000, 163 (0x9c00 << 16) | (0x9960 >> 2), 164 0x00000000, 165 (0x9c00 << 16) | (0x9964 >> 2), 166 0x00000000, 167 (0x9c00 << 16) | (0x9968 >> 2), 168 0x00000000, 169 (0x9c00 << 16) | (0x996c >> 2), 170 0x00000000, 171 (0x9c00 << 16) | (0x9970 >> 2), 172 0x00000000, 173 (0x9c00 << 16) | (0x9974 >> 2), 174 0x00000000, 175 (0x9c00 << 16) | (0x9978 >> 2), 176 0x00000000, 177 (0x9c00 << 16) | (0x997c >> 2), 178 0x00000000, 179 (0x9c00 << 16) | (0x9980 >> 2), 180 0x00000000, 181 (0x9c00 << 16) | (0x9984 >> 2), 182 0x00000000, 183 (0x9c00 << 16) | (0x9988 >> 2), 184 0x00000000, 185 (0x9c00 << 16) | (0x998c >> 2), 186 0x00000000, 187 (0x9c00 << 16) | (0x8c00 >> 2), 188 0x00000000, 189 (0x9c00 << 16) | (0x8c14 >> 2), 190 0x00000000, 191 (0x9c00 << 16) | (0x8c04 >> 2), 192 0x00000000, 193 (0x9c00 << 16) | (0x8c08 >> 2), 194 0x00000000, 195 (0x8000 << 16) | (0x9b7c >> 2), 196 0x00000000, 197 (0x8040 << 16) | (0x9b7c >> 2), 198 0x00000000, 199 (0x8000 << 16) | (0xe84 >> 2), 200 0x00000000, 201 (0x8040 << 16) | (0xe84 >> 2), 202 0x00000000, 203 (0x8000 << 16) | (0x89c0 >> 2), 204 0x00000000, 205 (0x8040 << 16) | (0x89c0 >> 2), 206 0x00000000, 207 (0x8000 << 16) | (0x914c >> 2), 208 0x00000000, 209 (0x8040 << 16) | (0x914c >> 2), 210 0x00000000, 211 (0x8000 << 16) | (0x8c20 >> 2), 212 0x00000000, 213 (0x8040 << 16) | (0x8c20 >> 2), 214 0x00000000, 215 (0x8000 << 16) | (0x9354 >> 2), 216 0x00000000, 217 (0x8040 << 16) | (0x9354 >> 2), 218 0x00000000, 219 (0x9c00 << 16) | (0x9060 >> 2), 220 0x00000000, 221 (0x9c00 << 16) | (0x9364 >> 2), 222 0x00000000, 223 (0x9c00 << 16) | (0x9100 >> 2), 224 0x00000000, 225 (0x9c00 << 16) | (0x913c >> 2), 226 0x00000000, 227 (0x8000 << 16) | (0x90e0 >> 2), 228 0x00000000, 229 (0x8000 << 16) | (0x90e4 >> 2), 230 0x00000000, 231 (0x8000 << 16) | (0x90e8 >> 2), 232 0x00000000, 233 (0x8040 << 16) | (0x90e0 >> 2), 234 0x00000000, 235 (0x8040 << 16) | (0x90e4 >> 2), 236 0x00000000, 237 (0x8040 << 16) | (0x90e8 >> 2), 238 0x00000000, 239 (0x9c00 << 16) | (0x8bcc >> 2), 240 0x00000000, 241 (0x9c00 << 16) | (0x8b24 >> 2), 242 0x00000000, 243 (0x9c00 << 16) | (0x88c4 >> 2), 244 0x00000000, 245 (0x9c00 << 16) | (0x8e50 >> 2), 246 0x00000000, 247 (0x9c00 << 16) | (0x8c0c >> 2), 248 0x00000000, 249 (0x9c00 << 16) | (0x8e58 >> 2), 250 0x00000000, 251 (0x9c00 << 16) | (0x8e5c >> 2), 252 0x00000000, 253 (0x9c00 << 16) | (0x9508 >> 2), 254 0x00000000, 255 (0x9c00 << 16) | (0x950c >> 2), 256 0x00000000, 257 (0x9c00 << 16) | (0x9494 >> 2), 258 0x00000000, 259 (0x9c00 << 16) | (0xac0c >> 2), 260 0x00000000, 261 (0x9c00 << 16) | (0xac10 >> 2), 262 0x00000000, 263 (0x9c00 << 16) | (0xac14 >> 2), 264 0x00000000, 265 (0x9c00 << 16) | (0xae00 >> 2), 266 0x00000000, 267 (0x9c00 << 16) | (0xac08 >> 2), 268 0x00000000, 269 (0x9c00 << 16) | (0x88d4 >> 2), 270 0x00000000, 271 (0x9c00 << 16) | (0x88c8 >> 2), 272 0x00000000, 273 (0x9c00 << 16) | (0x88cc >> 2), 274 0x00000000, 275 (0x9c00 << 16) | (0x89b0 >> 2), 276 0x00000000, 277 (0x9c00 << 16) | (0x8b10 >> 2), 278 0x00000000, 279 (0x9c00 << 16) | (0x8a14 >> 2), 280 0x00000000, 281 (0x9c00 << 16) | (0x9830 >> 2), 282 0x00000000, 283 (0x9c00 << 16) | (0x9834 >> 2), 284 0x00000000, 285 (0x9c00 << 16) | (0x9838 >> 2), 286 0x00000000, 287 (0x9c00 << 16) | (0x9a10 >> 2), 288 0x00000000, 289 (0x8000 << 16) | (0x9870 >> 2), 290 0x00000000, 291 (0x8000 << 16) | (0x9874 >> 2), 292 0x00000000, 293 (0x8001 << 16) | (0x9870 >> 2), 294 0x00000000, 295 (0x8001 << 16) | (0x9874 >> 2), 296 0x00000000, 297 (0x8040 << 16) | (0x9870 >> 2), 298 0x00000000, 299 (0x8040 << 16) | (0x9874 >> 2), 300 0x00000000, 301 (0x8041 << 16) | (0x9870 >> 2), 302 0x00000000, 303 (0x8041 << 16) | (0x9874 >> 2), 304 0x00000000, 305 0x00000000 306 }; 307 308 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 309 { 310 const char *chip_name; 311 char fw_name[30]; 312 int err; 313 const struct gfx_firmware_header_v1_0 *cp_hdr; 314 const struct rlc_firmware_header_v1_0 *rlc_hdr; 315 316 DRM_DEBUG("\n"); 317 318 switch (adev->asic_type) { 319 case CHIP_TAHITI: 320 chip_name = "tahiti"; 321 break; 322 case CHIP_PITCAIRN: 323 chip_name = "pitcairn"; 324 break; 325 case CHIP_VERDE: 326 chip_name = "verde"; 327 break; 328 case CHIP_OLAND: 329 chip_name = "oland"; 330 break; 331 case CHIP_HAINAN: 332 chip_name = "hainan"; 333 break; 334 default: BUG(); 335 } 336 337 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 338 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 339 if (err) 340 goto out; 341 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 342 if (err) 343 goto out; 344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 347 348 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 349 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 350 if (err) 351 goto out; 352 err = amdgpu_ucode_validate(adev->gfx.me_fw); 353 if (err) 354 goto out; 355 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 356 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 357 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 358 359 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); 360 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 361 if (err) 362 goto out; 363 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 364 if (err) 365 goto out; 366 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 367 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 368 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 369 370 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); 371 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 372 if (err) 373 goto out; 374 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 375 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 376 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 377 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 378 379 out: 380 if (err) { 381 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name); 382 release_firmware(adev->gfx.pfp_fw); 383 adev->gfx.pfp_fw = NULL; 384 release_firmware(adev->gfx.me_fw); 385 adev->gfx.me_fw = NULL; 386 release_firmware(adev->gfx.ce_fw); 387 adev->gfx.ce_fw = NULL; 388 release_firmware(adev->gfx.rlc_fw); 389 adev->gfx.rlc_fw = NULL; 390 } 391 return err; 392 } 393 394 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 395 { 396 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 397 u32 reg_offset, split_equal_to_row_size, *tilemode; 398 399 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 400 tilemode = adev->gfx.config.tile_mode_array; 401 402 switch (adev->gfx.config.mem_row_size_in_kb) { 403 case 1: 404 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 405 break; 406 case 2: 407 default: 408 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 409 break; 410 case 4: 411 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 412 break; 413 } 414 415 if (adev->asic_type == CHIP_VERDE) { 416 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 417 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 418 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 419 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 420 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 423 NUM_BANKS(ADDR_SURF_16_BANK); 424 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 425 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 426 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 427 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 428 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 429 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 430 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 431 NUM_BANKS(ADDR_SURF_16_BANK); 432 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 433 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 434 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 435 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 439 NUM_BANKS(ADDR_SURF_16_BANK); 440 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 442 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 446 NUM_BANKS(ADDR_SURF_8_BANK) | 447 TILE_SPLIT(split_equal_to_row_size); 448 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 449 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 450 PIPE_CONFIG(ADDR_SURF_P4_8x16); 451 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 452 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 453 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 454 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 455 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 456 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 457 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 458 NUM_BANKS(ADDR_SURF_4_BANK); 459 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 461 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 462 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 466 NUM_BANKS(ADDR_SURF_4_BANK); 467 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 469 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 470 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 473 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 474 NUM_BANKS(ADDR_SURF_2_BANK); 475 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 476 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 477 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 478 PIPE_CONFIG(ADDR_SURF_P4_8x16); 479 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 480 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 481 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 482 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 483 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 484 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 485 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 486 NUM_BANKS(ADDR_SURF_16_BANK); 487 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 488 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 489 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 490 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 491 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 492 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 493 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 494 NUM_BANKS(ADDR_SURF_16_BANK); 495 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 496 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 497 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 498 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 499 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 500 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 501 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 502 NUM_BANKS(ADDR_SURF_16_BANK); 503 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 504 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 505 PIPE_CONFIG(ADDR_SURF_P4_8x16); 506 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 507 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 508 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 510 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 513 NUM_BANKS(ADDR_SURF_16_BANK); 514 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 515 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 516 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 518 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 521 NUM_BANKS(ADDR_SURF_16_BANK); 522 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 523 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 524 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 526 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 529 NUM_BANKS(ADDR_SURF_16_BANK); 530 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 531 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 532 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 536 NUM_BANKS(ADDR_SURF_16_BANK) | 537 TILE_SPLIT(split_equal_to_row_size); 538 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 539 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 540 PIPE_CONFIG(ADDR_SURF_P4_8x16); 541 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 542 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 543 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 544 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 546 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 547 NUM_BANKS(ADDR_SURF_16_BANK) | 548 TILE_SPLIT(split_equal_to_row_size); 549 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 550 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 551 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 552 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 553 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 554 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 555 NUM_BANKS(ADDR_SURF_16_BANK) | 556 TILE_SPLIT(split_equal_to_row_size); 557 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 558 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 559 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 560 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 561 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 564 NUM_BANKS(ADDR_SURF_8_BANK); 565 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 566 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 567 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 568 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 572 NUM_BANKS(ADDR_SURF_8_BANK); 573 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 574 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 575 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 576 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 577 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 578 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 579 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 580 NUM_BANKS(ADDR_SURF_4_BANK); 581 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 582 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 583 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 584 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 585 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 588 NUM_BANKS(ADDR_SURF_4_BANK); 589 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 590 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 591 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 592 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 596 NUM_BANKS(ADDR_SURF_2_BANK); 597 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 598 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 599 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 600 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 601 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 602 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 603 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 604 NUM_BANKS(ADDR_SURF_2_BANK); 605 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 606 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 607 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 608 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 609 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 610 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 611 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 612 NUM_BANKS(ADDR_SURF_2_BANK); 613 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 614 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 615 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 616 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 617 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 618 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 619 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 620 NUM_BANKS(ADDR_SURF_2_BANK); 621 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 622 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 623 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 628 NUM_BANKS(ADDR_SURF_2_BANK); 629 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 630 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 631 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 632 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 636 NUM_BANKS(ADDR_SURF_2_BANK); 637 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 638 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 639 } else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) { 640 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 641 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 642 PIPE_CONFIG(ADDR_SURF_P2) | 643 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 644 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 645 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 646 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 647 NUM_BANKS(ADDR_SURF_16_BANK); 648 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 649 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 650 PIPE_CONFIG(ADDR_SURF_P2) | 651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 652 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 653 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 654 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 655 NUM_BANKS(ADDR_SURF_16_BANK); 656 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 657 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 658 PIPE_CONFIG(ADDR_SURF_P2) | 659 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 660 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 661 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 662 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 663 NUM_BANKS(ADDR_SURF_16_BANK); 664 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 665 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 666 PIPE_CONFIG(ADDR_SURF_P2) | 667 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 668 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 669 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 670 NUM_BANKS(ADDR_SURF_8_BANK) | 671 TILE_SPLIT(split_equal_to_row_size); 672 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 673 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 674 PIPE_CONFIG(ADDR_SURF_P2); 675 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 676 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 677 PIPE_CONFIG(ADDR_SURF_P2) | 678 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 679 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 680 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 681 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 682 NUM_BANKS(ADDR_SURF_8_BANK); 683 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 684 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 685 PIPE_CONFIG(ADDR_SURF_P2) | 686 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 687 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 688 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 689 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 690 NUM_BANKS(ADDR_SURF_8_BANK); 691 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 692 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 693 PIPE_CONFIG(ADDR_SURF_P2) | 694 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 695 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 696 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 697 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 698 NUM_BANKS(ADDR_SURF_4_BANK); 699 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 700 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 701 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 702 PIPE_CONFIG(ADDR_SURF_P2); 703 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 704 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 705 PIPE_CONFIG(ADDR_SURF_P2) | 706 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 707 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 708 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 709 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 710 NUM_BANKS(ADDR_SURF_16_BANK); 711 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 712 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 713 PIPE_CONFIG(ADDR_SURF_P2) | 714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 715 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 716 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 717 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 718 NUM_BANKS(ADDR_SURF_16_BANK); 719 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 720 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 721 PIPE_CONFIG(ADDR_SURF_P2) | 722 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 723 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 724 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 725 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 726 NUM_BANKS(ADDR_SURF_16_BANK); 727 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 728 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 729 PIPE_CONFIG(ADDR_SURF_P2); 730 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 731 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 732 PIPE_CONFIG(ADDR_SURF_P2) | 733 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 734 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 737 NUM_BANKS(ADDR_SURF_16_BANK); 738 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 739 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 740 PIPE_CONFIG(ADDR_SURF_P2) | 741 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 745 NUM_BANKS(ADDR_SURF_16_BANK); 746 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 747 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 748 PIPE_CONFIG(ADDR_SURF_P2) | 749 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 753 NUM_BANKS(ADDR_SURF_16_BANK); 754 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 755 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 756 PIPE_CONFIG(ADDR_SURF_P2) | 757 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 758 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 759 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 760 NUM_BANKS(ADDR_SURF_16_BANK) | 761 TILE_SPLIT(split_equal_to_row_size); 762 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 763 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 764 PIPE_CONFIG(ADDR_SURF_P2); 765 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 766 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 767 PIPE_CONFIG(ADDR_SURF_P2) | 768 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 769 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 770 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 771 NUM_BANKS(ADDR_SURF_16_BANK) | 772 TILE_SPLIT(split_equal_to_row_size); 773 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 774 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 775 PIPE_CONFIG(ADDR_SURF_P2) | 776 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 777 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 778 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 779 NUM_BANKS(ADDR_SURF_16_BANK) | 780 TILE_SPLIT(split_equal_to_row_size); 781 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 782 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 783 PIPE_CONFIG(ADDR_SURF_P2) | 784 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 785 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 786 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 787 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 788 NUM_BANKS(ADDR_SURF_8_BANK); 789 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 790 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 791 PIPE_CONFIG(ADDR_SURF_P2) | 792 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 793 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 795 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 796 NUM_BANKS(ADDR_SURF_8_BANK); 797 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 798 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 799 PIPE_CONFIG(ADDR_SURF_P2) | 800 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 801 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 802 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 803 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 804 NUM_BANKS(ADDR_SURF_8_BANK); 805 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 806 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 807 PIPE_CONFIG(ADDR_SURF_P2) | 808 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 809 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 810 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 811 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 812 NUM_BANKS(ADDR_SURF_8_BANK); 813 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 814 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 815 PIPE_CONFIG(ADDR_SURF_P2) | 816 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 817 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 820 NUM_BANKS(ADDR_SURF_4_BANK); 821 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 822 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 823 PIPE_CONFIG(ADDR_SURF_P2) | 824 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 825 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 828 NUM_BANKS(ADDR_SURF_4_BANK); 829 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 830 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 831 PIPE_CONFIG(ADDR_SURF_P2) | 832 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 836 NUM_BANKS(ADDR_SURF_4_BANK); 837 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 838 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 839 PIPE_CONFIG(ADDR_SURF_P2) | 840 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 841 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 842 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 843 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 844 NUM_BANKS(ADDR_SURF_4_BANK); 845 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 846 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 847 PIPE_CONFIG(ADDR_SURF_P2) | 848 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 849 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 850 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 851 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 852 NUM_BANKS(ADDR_SURF_4_BANK); 853 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 854 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 855 PIPE_CONFIG(ADDR_SURF_P2) | 856 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 857 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 858 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 859 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 860 NUM_BANKS(ADDR_SURF_4_BANK); 861 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 862 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 863 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 864 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 865 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 866 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 867 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 868 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 869 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 870 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 871 NUM_BANKS(ADDR_SURF_16_BANK); 872 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 873 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 874 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 875 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 876 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 877 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 878 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 879 NUM_BANKS(ADDR_SURF_16_BANK); 880 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 881 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 882 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 883 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 884 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 885 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 886 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 887 NUM_BANKS(ADDR_SURF_16_BANK); 888 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 889 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 890 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 891 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 892 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 893 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 894 NUM_BANKS(ADDR_SURF_4_BANK) | 895 TILE_SPLIT(split_equal_to_row_size); 896 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 897 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 898 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 899 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 900 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 901 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 902 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 903 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 904 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 905 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 906 NUM_BANKS(ADDR_SURF_2_BANK); 907 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 908 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 909 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 911 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 912 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 913 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 914 NUM_BANKS(ADDR_SURF_2_BANK); 915 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 916 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 917 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 918 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 919 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 920 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 921 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 922 NUM_BANKS(ADDR_SURF_2_BANK); 923 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 924 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 925 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 926 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 927 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 928 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 929 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 930 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 931 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 932 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 933 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 934 NUM_BANKS(ADDR_SURF_16_BANK); 935 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 936 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 937 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 938 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 939 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 940 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 941 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 942 NUM_BANKS(ADDR_SURF_16_BANK); 943 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 944 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 945 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 946 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 947 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 948 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 949 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 950 NUM_BANKS(ADDR_SURF_16_BANK); 951 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 952 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 953 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 954 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 955 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 956 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 957 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 958 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 959 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 960 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 961 NUM_BANKS(ADDR_SURF_16_BANK); 962 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 963 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 964 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 965 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 966 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 967 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 968 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 969 NUM_BANKS(ADDR_SURF_16_BANK); 970 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 971 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 972 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 973 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 974 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 975 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 976 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 977 NUM_BANKS(ADDR_SURF_16_BANK); 978 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 979 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 980 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 981 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 982 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 983 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 984 NUM_BANKS(ADDR_SURF_16_BANK) | 985 TILE_SPLIT(split_equal_to_row_size); 986 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 987 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 988 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 989 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 990 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 991 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 992 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 993 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 994 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 995 NUM_BANKS(ADDR_SURF_16_BANK) | 996 TILE_SPLIT(split_equal_to_row_size); 997 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 998 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 999 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1000 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1003 NUM_BANKS(ADDR_SURF_16_BANK) | 1004 TILE_SPLIT(split_equal_to_row_size); 1005 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1006 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1007 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1008 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1009 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1010 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1011 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1012 NUM_BANKS(ADDR_SURF_4_BANK); 1013 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1014 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1015 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1016 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1017 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1018 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1019 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1020 NUM_BANKS(ADDR_SURF_4_BANK); 1021 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1022 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1023 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1024 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1025 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1026 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1027 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1028 NUM_BANKS(ADDR_SURF_2_BANK); 1029 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1030 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1031 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1032 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1033 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1034 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1035 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1036 NUM_BANKS(ADDR_SURF_2_BANK); 1037 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1038 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1039 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1040 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1041 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1042 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1043 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1044 NUM_BANKS(ADDR_SURF_2_BANK); 1045 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1046 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1047 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1048 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1049 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1050 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1051 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1052 NUM_BANKS(ADDR_SURF_2_BANK); 1053 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1054 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1055 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1056 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1057 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1058 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1059 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1060 NUM_BANKS(ADDR_SURF_2_BANK); 1061 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1062 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1063 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1064 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1065 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1066 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1067 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1068 NUM_BANKS(ADDR_SURF_2_BANK); 1069 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1070 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1071 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1072 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1073 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1074 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1075 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1076 NUM_BANKS(ADDR_SURF_2_BANK); 1077 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1078 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1079 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1080 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1081 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1082 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1083 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1084 NUM_BANKS(ADDR_SURF_2_BANK); 1085 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1086 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1087 } else { 1088 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1089 } 1090 } 1091 1092 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1093 u32 sh_num, u32 instance) 1094 { 1095 u32 data; 1096 1097 if (instance == 0xffffffff) 1098 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1099 else 1100 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1101 1102 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1103 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1104 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1105 else if (se_num == 0xffffffff) 1106 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1107 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1108 else if (sh_num == 0xffffffff) 1109 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1110 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1111 else 1112 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1113 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1114 WREG32(mmGRBM_GFX_INDEX, data); 1115 } 1116 1117 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1118 { 1119 u32 data, mask; 1120 1121 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1122 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1123 1124 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1125 1126 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1127 adev->gfx.config.max_sh_per_se); 1128 1129 return ~data & mask; 1130 } 1131 1132 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1133 { 1134 switch (adev->asic_type) { 1135 case CHIP_TAHITI: 1136 case CHIP_PITCAIRN: 1137 *rconf |= 1138 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1139 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1140 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1141 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1142 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1143 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1144 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1145 break; 1146 case CHIP_VERDE: 1147 *rconf |= 1148 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1149 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1150 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1151 break; 1152 case CHIP_OLAND: 1153 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1154 break; 1155 case CHIP_HAINAN: 1156 *rconf |= 0x0; 1157 break; 1158 default: 1159 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1160 break; 1161 } 1162 } 1163 1164 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1165 u32 raster_config, unsigned rb_mask, 1166 unsigned num_rb) 1167 { 1168 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1169 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1170 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1171 unsigned rb_per_se = num_rb / num_se; 1172 unsigned se_mask[4]; 1173 unsigned se; 1174 1175 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1176 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1177 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1178 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1179 1180 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1181 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1182 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1183 1184 for (se = 0; se < num_se; se++) { 1185 unsigned raster_config_se = raster_config; 1186 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1187 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1188 int idx = (se / 2) * 2; 1189 1190 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1191 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1192 1193 if (!se_mask[idx]) 1194 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1195 else 1196 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1197 } 1198 1199 pkr0_mask &= rb_mask; 1200 pkr1_mask &= rb_mask; 1201 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1202 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1203 1204 if (!pkr0_mask) 1205 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1206 else 1207 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1208 } 1209 1210 if (rb_per_se >= 2) { 1211 unsigned rb0_mask = 1 << (se * rb_per_se); 1212 unsigned rb1_mask = rb0_mask << 1; 1213 1214 rb0_mask &= rb_mask; 1215 rb1_mask &= rb_mask; 1216 if (!rb0_mask || !rb1_mask) { 1217 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1218 1219 if (!rb0_mask) 1220 raster_config_se |= 1221 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1222 else 1223 raster_config_se |= 1224 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1225 } 1226 1227 if (rb_per_se > 2) { 1228 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1229 rb1_mask = rb0_mask << 1; 1230 rb0_mask &= rb_mask; 1231 rb1_mask &= rb_mask; 1232 if (!rb0_mask || !rb1_mask) { 1233 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1234 1235 if (!rb0_mask) 1236 raster_config_se |= 1237 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1238 else 1239 raster_config_se |= 1240 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1241 } 1242 } 1243 } 1244 1245 /* GRBM_GFX_INDEX has a different offset on SI */ 1246 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1247 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1248 } 1249 1250 /* GRBM_GFX_INDEX has a different offset on SI */ 1251 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1252 } 1253 1254 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1255 { 1256 int i, j; 1257 u32 data; 1258 u32 raster_config = 0; 1259 u32 active_rbs = 0; 1260 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1261 adev->gfx.config.max_sh_per_se; 1262 unsigned num_rb_pipes; 1263 1264 mutex_lock(&adev->grbm_idx_mutex); 1265 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1266 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1267 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1268 data = gfx_v6_0_get_rb_active_bitmap(adev); 1269 active_rbs |= data << 1270 ((i * adev->gfx.config.max_sh_per_se + j) * 1271 rb_bitmap_width_per_sh); 1272 } 1273 } 1274 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1275 1276 adev->gfx.config.backend_enable_mask = active_rbs; 1277 adev->gfx.config.num_rbs = hweight32(active_rbs); 1278 1279 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1280 adev->gfx.config.max_shader_engines, 16); 1281 1282 gfx_v6_0_raster_config(adev, &raster_config); 1283 1284 if (!adev->gfx.config.backend_enable_mask || 1285 adev->gfx.config.num_rbs >= num_rb_pipes) 1286 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1287 else 1288 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1289 adev->gfx.config.backend_enable_mask, 1290 num_rb_pipes); 1291 1292 /* cache the values for userspace */ 1293 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1294 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1295 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1296 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1297 RREG32(mmCC_RB_BACKEND_DISABLE); 1298 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1299 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1300 adev->gfx.config.rb_config[i][j].raster_config = 1301 RREG32(mmPA_SC_RASTER_CONFIG); 1302 } 1303 } 1304 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1305 mutex_unlock(&adev->grbm_idx_mutex); 1306 } 1307 1308 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1309 u32 bitmap) 1310 { 1311 u32 data; 1312 1313 if (!bitmap) 1314 return; 1315 1316 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1317 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1318 1319 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1320 } 1321 1322 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1323 { 1324 u32 data, mask; 1325 1326 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1327 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1328 1329 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1330 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1331 } 1332 1333 1334 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1335 { 1336 int i, j, k; 1337 u32 data, mask; 1338 u32 active_cu = 0; 1339 1340 mutex_lock(&adev->grbm_idx_mutex); 1341 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1342 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1343 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1344 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1345 active_cu = gfx_v6_0_get_cu_enabled(adev); 1346 1347 mask = 1; 1348 for (k = 0; k < 16; k++) { 1349 mask <<= k; 1350 if (active_cu & mask) { 1351 data &= ~mask; 1352 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1353 break; 1354 } 1355 } 1356 } 1357 } 1358 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1359 mutex_unlock(&adev->grbm_idx_mutex); 1360 } 1361 1362 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1363 { 1364 adev->gfx.config.double_offchip_lds_buf = 0; 1365 } 1366 1367 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) 1368 { 1369 u32 gb_addr_config = 0; 1370 u32 mc_shared_chmap, mc_arb_ramcfg; 1371 u32 sx_debug_1; 1372 u32 hdp_host_path_cntl; 1373 u32 tmp; 1374 1375 switch (adev->asic_type) { 1376 case CHIP_TAHITI: 1377 adev->gfx.config.max_shader_engines = 2; 1378 adev->gfx.config.max_tile_pipes = 12; 1379 adev->gfx.config.max_cu_per_sh = 8; 1380 adev->gfx.config.max_sh_per_se = 2; 1381 adev->gfx.config.max_backends_per_se = 4; 1382 adev->gfx.config.max_texture_channel_caches = 12; 1383 adev->gfx.config.max_gprs = 256; 1384 adev->gfx.config.max_gs_threads = 32; 1385 adev->gfx.config.max_hw_contexts = 8; 1386 1387 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1388 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1389 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1390 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1391 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1392 break; 1393 case CHIP_PITCAIRN: 1394 adev->gfx.config.max_shader_engines = 2; 1395 adev->gfx.config.max_tile_pipes = 8; 1396 adev->gfx.config.max_cu_per_sh = 5; 1397 adev->gfx.config.max_sh_per_se = 2; 1398 adev->gfx.config.max_backends_per_se = 4; 1399 adev->gfx.config.max_texture_channel_caches = 8; 1400 adev->gfx.config.max_gprs = 256; 1401 adev->gfx.config.max_gs_threads = 32; 1402 adev->gfx.config.max_hw_contexts = 8; 1403 1404 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1405 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1406 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1407 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1408 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1409 break; 1410 case CHIP_VERDE: 1411 adev->gfx.config.max_shader_engines = 1; 1412 adev->gfx.config.max_tile_pipes = 4; 1413 adev->gfx.config.max_cu_per_sh = 5; 1414 adev->gfx.config.max_sh_per_se = 2; 1415 adev->gfx.config.max_backends_per_se = 4; 1416 adev->gfx.config.max_texture_channel_caches = 4; 1417 adev->gfx.config.max_gprs = 256; 1418 adev->gfx.config.max_gs_threads = 32; 1419 adev->gfx.config.max_hw_contexts = 8; 1420 1421 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1422 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1423 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1424 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1425 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1426 break; 1427 case CHIP_OLAND: 1428 adev->gfx.config.max_shader_engines = 1; 1429 adev->gfx.config.max_tile_pipes = 4; 1430 adev->gfx.config.max_cu_per_sh = 6; 1431 adev->gfx.config.max_sh_per_se = 1; 1432 adev->gfx.config.max_backends_per_se = 2; 1433 adev->gfx.config.max_texture_channel_caches = 4; 1434 adev->gfx.config.max_gprs = 256; 1435 adev->gfx.config.max_gs_threads = 16; 1436 adev->gfx.config.max_hw_contexts = 8; 1437 1438 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1439 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1440 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1441 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1442 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1443 break; 1444 case CHIP_HAINAN: 1445 adev->gfx.config.max_shader_engines = 1; 1446 adev->gfx.config.max_tile_pipes = 4; 1447 adev->gfx.config.max_cu_per_sh = 5; 1448 adev->gfx.config.max_sh_per_se = 1; 1449 adev->gfx.config.max_backends_per_se = 1; 1450 adev->gfx.config.max_texture_channel_caches = 2; 1451 adev->gfx.config.max_gprs = 256; 1452 adev->gfx.config.max_gs_threads = 16; 1453 adev->gfx.config.max_hw_contexts = 8; 1454 1455 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1456 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1457 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1458 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1459 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1460 break; 1461 default: 1462 BUG(); 1463 break; 1464 } 1465 1466 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1467 WREG32(mmSRBM_INT_CNTL, 1); 1468 WREG32(mmSRBM_INT_ACK, 1); 1469 1470 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1471 1472 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 1473 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1474 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1475 1476 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1477 adev->gfx.config.mem_max_burst_length_bytes = 256; 1478 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1479 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1480 if (adev->gfx.config.mem_row_size_in_kb > 4) 1481 adev->gfx.config.mem_row_size_in_kb = 4; 1482 adev->gfx.config.shader_engine_tile_size = 32; 1483 adev->gfx.config.num_gpus = 1; 1484 adev->gfx.config.multi_gpu_tile_size = 64; 1485 1486 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1487 switch (adev->gfx.config.mem_row_size_in_kb) { 1488 case 1: 1489 default: 1490 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1491 break; 1492 case 2: 1493 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1494 break; 1495 case 4: 1496 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1497 break; 1498 } 1499 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1500 if (adev->gfx.config.max_shader_engines == 2) 1501 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1502 adev->gfx.config.gb_addr_config = gb_addr_config; 1503 1504 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1505 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1506 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1507 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1508 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1509 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1510 1511 #if 0 1512 if (adev->has_uvd) { 1513 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1514 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1515 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1516 } 1517 #endif 1518 gfx_v6_0_tiling_mode_table_init(adev); 1519 1520 gfx_v6_0_setup_rb(adev); 1521 1522 gfx_v6_0_setup_spi(adev); 1523 1524 gfx_v6_0_get_cu_info(adev); 1525 gfx_v6_0_config_init(adev); 1526 1527 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1528 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1529 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1530 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1531 1532 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1533 WREG32(mmSX_DEBUG_1, sx_debug_1); 1534 1535 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1536 1537 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1538 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1539 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1540 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1541 1542 WREG32(mmVGT_NUM_INSTANCES, 1); 1543 WREG32(mmCP_PERFMON_CNTL, 0); 1544 WREG32(mmSQ_CONFIG, 0); 1545 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1546 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1547 1548 WREG32(mmVGT_CACHE_INVALIDATION, 1549 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1550 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1551 1552 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1553 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1554 1555 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1556 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1557 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1558 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1559 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1560 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1561 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1562 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1563 1564 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1565 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1566 1567 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1568 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1569 1570 udelay(50); 1571 } 1572 1573 1574 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev) 1575 { 1576 adev->gfx.scratch.num_reg = 8; 1577 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 1578 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 1579 } 1580 1581 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1582 { 1583 struct amdgpu_device *adev = ring->adev; 1584 uint32_t scratch; 1585 uint32_t tmp = 0; 1586 unsigned i; 1587 int r; 1588 1589 r = amdgpu_gfx_scratch_get(adev, &scratch); 1590 if (r) { 1591 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 1592 return r; 1593 } 1594 WREG32(scratch, 0xCAFEDEAD); 1595 1596 r = amdgpu_ring_alloc(ring, 3); 1597 if (r) { 1598 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); 1599 amdgpu_gfx_scratch_free(adev, scratch); 1600 return r; 1601 } 1602 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1603 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); 1604 amdgpu_ring_write(ring, 0xDEADBEEF); 1605 amdgpu_ring_commit(ring); 1606 1607 for (i = 0; i < adev->usec_timeout; i++) { 1608 tmp = RREG32(scratch); 1609 if (tmp == 0xDEADBEEF) 1610 break; 1611 DRM_UDELAY(1); 1612 } 1613 if (i < adev->usec_timeout) { 1614 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 1615 } else { 1616 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 1617 ring->idx, scratch, tmp); 1618 r = -EINVAL; 1619 } 1620 amdgpu_gfx_scratch_free(adev, scratch); 1621 return r; 1622 } 1623 1624 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1625 { 1626 /* flush hdp cache */ 1627 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1628 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1629 WRITE_DATA_DST_SEL(0))); 1630 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1631 amdgpu_ring_write(ring, 0); 1632 amdgpu_ring_write(ring, 0x1); 1633 } 1634 1635 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1636 { 1637 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1638 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1639 EVENT_INDEX(0)); 1640 } 1641 1642 /** 1643 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 1644 * 1645 * @adev: amdgpu_device pointer 1646 * @ridx: amdgpu ring index 1647 * 1648 * Emits an hdp invalidate on the cp. 1649 */ 1650 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 1651 { 1652 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1653 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1654 WRITE_DATA_DST_SEL(0))); 1655 amdgpu_ring_write(ring, mmHDP_DEBUG0); 1656 amdgpu_ring_write(ring, 0); 1657 amdgpu_ring_write(ring, 0x1); 1658 } 1659 1660 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1661 u64 seq, unsigned flags) 1662 { 1663 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1664 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1665 /* flush read cache over gart */ 1666 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1667 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1668 amdgpu_ring_write(ring, 0); 1669 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1670 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1671 PACKET3_TC_ACTION_ENA | 1672 PACKET3_SH_KCACHE_ACTION_ENA | 1673 PACKET3_SH_ICACHE_ACTION_ENA); 1674 amdgpu_ring_write(ring, 0xFFFFFFFF); 1675 amdgpu_ring_write(ring, 0); 1676 amdgpu_ring_write(ring, 10); /* poll interval */ 1677 /* EVENT_WRITE_EOP - flush caches, send int */ 1678 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1679 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1680 amdgpu_ring_write(ring, addr & 0xfffffffc); 1681 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1682 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1683 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1684 amdgpu_ring_write(ring, lower_32_bits(seq)); 1685 amdgpu_ring_write(ring, upper_32_bits(seq)); 1686 } 1687 1688 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1689 struct amdgpu_ib *ib, 1690 unsigned vm_id, bool ctx_switch) 1691 { 1692 u32 header, control = 0; 1693 1694 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1695 if (ctx_switch) { 1696 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1697 amdgpu_ring_write(ring, 0); 1698 } 1699 1700 if (ib->flags & AMDGPU_IB_FLAG_CE) 1701 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1702 else 1703 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1704 1705 control |= ib->length_dw | (vm_id << 24); 1706 1707 amdgpu_ring_write(ring, header); 1708 amdgpu_ring_write(ring, 1709 #ifdef __BIG_ENDIAN 1710 (2 << 0) | 1711 #endif 1712 (ib->gpu_addr & 0xFFFFFFFC)); 1713 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1714 amdgpu_ring_write(ring, control); 1715 } 1716 1717 /** 1718 * gfx_v6_0_ring_test_ib - basic ring IB test 1719 * 1720 * @ring: amdgpu_ring structure holding ring information 1721 * 1722 * Allocate an IB and execute it on the gfx ring (SI). 1723 * Provides a basic gfx ring test to verify that IBs are working. 1724 * Returns 0 on success, error on failure. 1725 */ 1726 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1727 { 1728 struct amdgpu_device *adev = ring->adev; 1729 struct amdgpu_ib ib; 1730 struct dma_fence *f = NULL; 1731 uint32_t scratch; 1732 uint32_t tmp = 0; 1733 long r; 1734 1735 r = amdgpu_gfx_scratch_get(adev, &scratch); 1736 if (r) { 1737 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 1738 return r; 1739 } 1740 WREG32(scratch, 0xCAFEDEAD); 1741 memset(&ib, 0, sizeof(ib)); 1742 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1743 if (r) { 1744 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1745 goto err1; 1746 } 1747 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1748 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START)); 1749 ib.ptr[2] = 0xDEADBEEF; 1750 ib.length_dw = 3; 1751 1752 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1753 if (r) 1754 goto err2; 1755 1756 r = dma_fence_wait_timeout(f, false, timeout); 1757 if (r == 0) { 1758 DRM_ERROR("amdgpu: IB test timed out\n"); 1759 r = -ETIMEDOUT; 1760 goto err2; 1761 } else if (r < 0) { 1762 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1763 goto err2; 1764 } 1765 tmp = RREG32(scratch); 1766 if (tmp == 0xDEADBEEF) { 1767 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 1768 r = 0; 1769 } else { 1770 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 1771 scratch, tmp); 1772 r = -EINVAL; 1773 } 1774 1775 err2: 1776 amdgpu_ib_free(adev, &ib, NULL); 1777 dma_fence_put(f); 1778 err1: 1779 amdgpu_gfx_scratch_free(adev, scratch); 1780 return r; 1781 } 1782 1783 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1784 { 1785 int i; 1786 if (enable) { 1787 WREG32(mmCP_ME_CNTL, 0); 1788 } else { 1789 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 1790 CP_ME_CNTL__PFP_HALT_MASK | 1791 CP_ME_CNTL__CE_HALT_MASK)); 1792 WREG32(mmSCRATCH_UMSK, 0); 1793 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1794 adev->gfx.gfx_ring[i].ready = false; 1795 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1796 adev->gfx.compute_ring[i].ready = false; 1797 } 1798 udelay(50); 1799 } 1800 1801 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 1802 { 1803 unsigned i; 1804 const struct gfx_firmware_header_v1_0 *pfp_hdr; 1805 const struct gfx_firmware_header_v1_0 *ce_hdr; 1806 const struct gfx_firmware_header_v1_0 *me_hdr; 1807 const __le32 *fw_data; 1808 u32 fw_size; 1809 1810 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 1811 return -EINVAL; 1812 1813 gfx_v6_0_cp_gfx_enable(adev, false); 1814 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1815 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1816 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1817 1818 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 1819 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 1820 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 1821 1822 /* PFP */ 1823 fw_data = (const __le32 *) 1824 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1825 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1826 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1827 for (i = 0; i < fw_size; i++) 1828 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 1829 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1830 1831 /* CE */ 1832 fw_data = (const __le32 *) 1833 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 1834 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 1835 WREG32(mmCP_CE_UCODE_ADDR, 0); 1836 for (i = 0; i < fw_size; i++) 1837 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 1838 WREG32(mmCP_CE_UCODE_ADDR, 0); 1839 1840 /* ME */ 1841 fw_data = (const __be32 *) 1842 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 1843 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 1844 WREG32(mmCP_ME_RAM_WADDR, 0); 1845 for (i = 0; i < fw_size; i++) 1846 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 1847 WREG32(mmCP_ME_RAM_WADDR, 0); 1848 1849 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1850 WREG32(mmCP_CE_UCODE_ADDR, 0); 1851 WREG32(mmCP_ME_RAM_WADDR, 0); 1852 WREG32(mmCP_ME_RAM_RADDR, 0); 1853 return 0; 1854 } 1855 1856 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 1857 { 1858 const struct cs_section_def *sect = NULL; 1859 const struct cs_extent_def *ext = NULL; 1860 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1861 int r, i; 1862 1863 r = amdgpu_ring_alloc(ring, 7 + 4); 1864 if (r) { 1865 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 1866 return r; 1867 } 1868 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1869 amdgpu_ring_write(ring, 0x1); 1870 amdgpu_ring_write(ring, 0x0); 1871 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 1872 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1873 amdgpu_ring_write(ring, 0); 1874 amdgpu_ring_write(ring, 0); 1875 1876 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 1877 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 1878 amdgpu_ring_write(ring, 0xc000); 1879 amdgpu_ring_write(ring, 0xe000); 1880 amdgpu_ring_commit(ring); 1881 1882 gfx_v6_0_cp_gfx_enable(adev, true); 1883 1884 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 1885 if (r) { 1886 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 1887 return r; 1888 } 1889 1890 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1891 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1892 1893 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1894 for (ext = sect->section; ext->extent != NULL; ++ext) { 1895 if (sect->id == SECT_CONTEXT) { 1896 amdgpu_ring_write(ring, 1897 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1898 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 1899 for (i = 0; i < ext->reg_count; i++) 1900 amdgpu_ring_write(ring, ext->extent[i]); 1901 } 1902 } 1903 } 1904 1905 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1906 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1907 1908 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1909 amdgpu_ring_write(ring, 0); 1910 1911 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 1912 amdgpu_ring_write(ring, 0x00000316); 1913 amdgpu_ring_write(ring, 0x0000000e); 1914 amdgpu_ring_write(ring, 0x00000010); 1915 1916 amdgpu_ring_commit(ring); 1917 1918 return 0; 1919 } 1920 1921 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 1922 { 1923 struct amdgpu_ring *ring; 1924 u32 tmp; 1925 u32 rb_bufsz; 1926 int r; 1927 u64 rptr_addr; 1928 1929 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 1930 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1931 1932 /* Set the write pointer delay */ 1933 WREG32(mmCP_RB_WPTR_DELAY, 0); 1934 1935 WREG32(mmCP_DEBUG, 0); 1936 WREG32(mmSCRATCH_ADDR, 0); 1937 1938 /* ring 0 - compute and gfx */ 1939 /* Set ring buffer size */ 1940 ring = &adev->gfx.gfx_ring[0]; 1941 rb_bufsz = order_base_2(ring->ring_size / 8); 1942 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1943 1944 #ifdef __BIG_ENDIAN 1945 tmp |= BUF_SWAP_32BIT; 1946 #endif 1947 WREG32(mmCP_RB0_CNTL, tmp); 1948 1949 /* Initialize the ring buffer's read and write pointers */ 1950 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 1951 ring->wptr = 0; 1952 WREG32(mmCP_RB0_WPTR, ring->wptr); 1953 1954 /* set the wb address whether it's enabled or not */ 1955 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1956 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 1957 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 1958 1959 WREG32(mmSCRATCH_UMSK, 0); 1960 1961 mdelay(1); 1962 WREG32(mmCP_RB0_CNTL, tmp); 1963 1964 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 1965 1966 /* start the rings */ 1967 gfx_v6_0_cp_gfx_start(adev); 1968 ring->ready = true; 1969 r = amdgpu_ring_test_ring(ring); 1970 if (r) { 1971 ring->ready = false; 1972 return r; 1973 } 1974 1975 return 0; 1976 } 1977 1978 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 1979 { 1980 return ring->adev->wb.wb[ring->rptr_offs]; 1981 } 1982 1983 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 1984 { 1985 struct amdgpu_device *adev = ring->adev; 1986 1987 if (ring == &adev->gfx.gfx_ring[0]) 1988 return RREG32(mmCP_RB0_WPTR); 1989 else if (ring == &adev->gfx.compute_ring[0]) 1990 return RREG32(mmCP_RB1_WPTR); 1991 else if (ring == &adev->gfx.compute_ring[1]) 1992 return RREG32(mmCP_RB2_WPTR); 1993 else 1994 BUG(); 1995 } 1996 1997 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 1998 { 1999 struct amdgpu_device *adev = ring->adev; 2000 2001 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2002 (void)RREG32(mmCP_RB0_WPTR); 2003 } 2004 2005 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2006 { 2007 struct amdgpu_device *adev = ring->adev; 2008 2009 if (ring == &adev->gfx.compute_ring[0]) { 2010 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2011 (void)RREG32(mmCP_RB1_WPTR); 2012 } else if (ring == &adev->gfx.compute_ring[1]) { 2013 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2014 (void)RREG32(mmCP_RB2_WPTR); 2015 } else { 2016 BUG(); 2017 } 2018 2019 } 2020 2021 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 2022 { 2023 struct amdgpu_ring *ring; 2024 u32 tmp; 2025 u32 rb_bufsz; 2026 int i, r; 2027 u64 rptr_addr; 2028 2029 /* ring1 - compute only */ 2030 /* Set ring buffer size */ 2031 2032 ring = &adev->gfx.compute_ring[0]; 2033 rb_bufsz = order_base_2(ring->ring_size / 8); 2034 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2035 #ifdef __BIG_ENDIAN 2036 tmp |= BUF_SWAP_32BIT; 2037 #endif 2038 WREG32(mmCP_RB1_CNTL, tmp); 2039 2040 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2041 ring->wptr = 0; 2042 WREG32(mmCP_RB1_WPTR, ring->wptr); 2043 2044 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2045 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2046 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2047 2048 mdelay(1); 2049 WREG32(mmCP_RB1_CNTL, tmp); 2050 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2051 2052 ring = &adev->gfx.compute_ring[1]; 2053 rb_bufsz = order_base_2(ring->ring_size / 8); 2054 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2055 #ifdef __BIG_ENDIAN 2056 tmp |= BUF_SWAP_32BIT; 2057 #endif 2058 WREG32(mmCP_RB2_CNTL, tmp); 2059 2060 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2061 ring->wptr = 0; 2062 WREG32(mmCP_RB2_WPTR, ring->wptr); 2063 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2064 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2065 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2066 2067 mdelay(1); 2068 WREG32(mmCP_RB2_CNTL, tmp); 2069 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2070 2071 adev->gfx.compute_ring[0].ready = false; 2072 adev->gfx.compute_ring[1].ready = false; 2073 2074 for (i = 0; i < 2; i++) { 2075 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]); 2076 if (r) 2077 return r; 2078 adev->gfx.compute_ring[i].ready = true; 2079 } 2080 2081 return 0; 2082 } 2083 2084 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2085 { 2086 gfx_v6_0_cp_gfx_enable(adev, enable); 2087 } 2088 2089 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2090 { 2091 return gfx_v6_0_cp_gfx_load_microcode(adev); 2092 } 2093 2094 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2095 bool enable) 2096 { 2097 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2098 u32 mask; 2099 int i; 2100 2101 if (enable) 2102 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2103 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2104 else 2105 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2106 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2107 WREG32(mmCP_INT_CNTL_RING0, tmp); 2108 2109 if (!enable) { 2110 /* read a gfx register */ 2111 tmp = RREG32(mmDB_DEPTH_INFO); 2112 2113 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2114 for (i = 0; i < adev->usec_timeout; i++) { 2115 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2116 break; 2117 udelay(1); 2118 } 2119 } 2120 } 2121 2122 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2123 { 2124 int r; 2125 2126 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2127 2128 r = gfx_v6_0_cp_load_microcode(adev); 2129 if (r) 2130 return r; 2131 2132 r = gfx_v6_0_cp_gfx_resume(adev); 2133 if (r) 2134 return r; 2135 r = gfx_v6_0_cp_compute_resume(adev); 2136 if (r) 2137 return r; 2138 2139 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2140 2141 return 0; 2142 } 2143 2144 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2145 { 2146 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2147 uint32_t seq = ring->fence_drv.sync_seq; 2148 uint64_t addr = ring->fence_drv.gpu_addr; 2149 2150 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2151 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2152 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2153 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2154 amdgpu_ring_write(ring, addr & 0xfffffffc); 2155 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2156 amdgpu_ring_write(ring, seq); 2157 amdgpu_ring_write(ring, 0xffffffff); 2158 amdgpu_ring_write(ring, 4); /* poll interval */ 2159 2160 if (usepfp) { 2161 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2162 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2163 amdgpu_ring_write(ring, 0); 2164 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2165 amdgpu_ring_write(ring, 0); 2166 } 2167 } 2168 2169 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2170 unsigned vm_id, uint64_t pd_addr) 2171 { 2172 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2173 2174 /* write new base address */ 2175 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2176 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2177 WRITE_DATA_DST_SEL(0))); 2178 if (vm_id < 8) { 2179 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); 2180 } else { 2181 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); 2182 } 2183 amdgpu_ring_write(ring, 0); 2184 amdgpu_ring_write(ring, pd_addr >> 12); 2185 2186 /* bits 0-15 are the VM contexts0-15 */ 2187 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2188 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2189 WRITE_DATA_DST_SEL(0))); 2190 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2191 amdgpu_ring_write(ring, 0); 2192 amdgpu_ring_write(ring, 1 << vm_id); 2193 2194 /* wait for the invalidate to complete */ 2195 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2196 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2197 WAIT_REG_MEM_ENGINE(0))); /* me */ 2198 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2199 amdgpu_ring_write(ring, 0); 2200 amdgpu_ring_write(ring, 0); /* ref */ 2201 amdgpu_ring_write(ring, 0); /* mask */ 2202 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2203 2204 if (usepfp) { 2205 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2206 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2207 amdgpu_ring_write(ring, 0x0); 2208 2209 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2210 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2211 amdgpu_ring_write(ring, 0); 2212 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2213 amdgpu_ring_write(ring, 0); 2214 } 2215 } 2216 2217 2218 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev) 2219 { 2220 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); 2221 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); 2222 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); 2223 } 2224 2225 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2226 { 2227 const u32 *src_ptr; 2228 volatile u32 *dst_ptr; 2229 u32 dws, i; 2230 u64 reg_list_mc_addr; 2231 const struct cs_section_def *cs_data; 2232 int r; 2233 2234 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2235 adev->gfx.rlc.reg_list_size = 2236 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2237 2238 adev->gfx.rlc.cs_data = si_cs_data; 2239 src_ptr = adev->gfx.rlc.reg_list; 2240 dws = adev->gfx.rlc.reg_list_size; 2241 cs_data = adev->gfx.rlc.cs_data; 2242 2243 if (src_ptr) { 2244 /* save restore block */ 2245 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2246 AMDGPU_GEM_DOMAIN_VRAM, 2247 &adev->gfx.rlc.save_restore_obj, 2248 &adev->gfx.rlc.save_restore_gpu_addr, 2249 (void **)&adev->gfx.rlc.sr_ptr); 2250 if (r) { 2251 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", 2252 r); 2253 gfx_v6_0_rlc_fini(adev); 2254 return r; 2255 } 2256 2257 /* write the sr buffer */ 2258 dst_ptr = adev->gfx.rlc.sr_ptr; 2259 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 2260 dst_ptr[i] = cpu_to_le32(src_ptr[i]); 2261 2262 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); 2263 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 2264 } 2265 2266 if (cs_data) { 2267 /* clear state block */ 2268 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2269 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2270 2271 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2272 AMDGPU_GEM_DOMAIN_VRAM, 2273 &adev->gfx.rlc.clear_state_obj, 2274 &adev->gfx.rlc.clear_state_gpu_addr, 2275 (void **)&adev->gfx.rlc.cs_ptr); 2276 if (r) { 2277 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2278 gfx_v6_0_rlc_fini(adev); 2279 return r; 2280 } 2281 2282 /* set up the cs buffer */ 2283 dst_ptr = adev->gfx.rlc.cs_ptr; 2284 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2285 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2286 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2287 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2288 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2289 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2290 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2291 } 2292 2293 return 0; 2294 } 2295 2296 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2297 { 2298 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2299 2300 if (!enable) { 2301 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2302 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2303 } 2304 } 2305 2306 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2307 { 2308 int i; 2309 2310 for (i = 0; i < adev->usec_timeout; i++) { 2311 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2312 break; 2313 udelay(1); 2314 } 2315 2316 for (i = 0; i < adev->usec_timeout; i++) { 2317 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2318 break; 2319 udelay(1); 2320 } 2321 } 2322 2323 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2324 { 2325 u32 tmp; 2326 2327 tmp = RREG32(mmRLC_CNTL); 2328 if (tmp != rlc) 2329 WREG32(mmRLC_CNTL, rlc); 2330 } 2331 2332 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2333 { 2334 u32 data, orig; 2335 2336 orig = data = RREG32(mmRLC_CNTL); 2337 2338 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2339 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2340 WREG32(mmRLC_CNTL, data); 2341 2342 gfx_v6_0_wait_for_rlc_serdes(adev); 2343 } 2344 2345 return orig; 2346 } 2347 2348 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2349 { 2350 WREG32(mmRLC_CNTL, 0); 2351 2352 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2353 gfx_v6_0_wait_for_rlc_serdes(adev); 2354 } 2355 2356 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2357 { 2358 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2359 2360 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2361 2362 udelay(50); 2363 } 2364 2365 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2366 { 2367 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2368 udelay(50); 2369 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2370 udelay(50); 2371 } 2372 2373 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2374 { 2375 u32 tmp; 2376 2377 /* Enable LBPW only for DDR3 */ 2378 tmp = RREG32(mmMC_SEQ_MISC0); 2379 if ((tmp & 0xF0000000) == 0xB0000000) 2380 return true; 2381 return false; 2382 } 2383 2384 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2385 { 2386 } 2387 2388 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2389 { 2390 u32 i; 2391 const struct rlc_firmware_header_v1_0 *hdr; 2392 const __le32 *fw_data; 2393 u32 fw_size; 2394 2395 2396 if (!adev->gfx.rlc_fw) 2397 return -EINVAL; 2398 2399 gfx_v6_0_rlc_stop(adev); 2400 gfx_v6_0_rlc_reset(adev); 2401 gfx_v6_0_init_pg(adev); 2402 gfx_v6_0_init_cg(adev); 2403 2404 WREG32(mmRLC_RL_BASE, 0); 2405 WREG32(mmRLC_RL_SIZE, 0); 2406 WREG32(mmRLC_LB_CNTL, 0); 2407 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2408 WREG32(mmRLC_LB_CNTR_INIT, 0); 2409 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2410 2411 WREG32(mmRLC_MC_CNTL, 0); 2412 WREG32(mmRLC_UCODE_CNTL, 0); 2413 2414 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2415 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2416 fw_data = (const __le32 *) 2417 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2418 2419 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2420 2421 for (i = 0; i < fw_size; i++) { 2422 WREG32(mmRLC_UCODE_ADDR, i); 2423 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2424 } 2425 WREG32(mmRLC_UCODE_ADDR, 0); 2426 2427 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2428 gfx_v6_0_rlc_start(adev); 2429 2430 return 0; 2431 } 2432 2433 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2434 { 2435 u32 data, orig, tmp; 2436 2437 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2438 2439 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2440 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2441 2442 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2443 2444 tmp = gfx_v6_0_halt_rlc(adev); 2445 2446 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2447 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2448 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2449 2450 gfx_v6_0_wait_for_rlc_serdes(adev); 2451 gfx_v6_0_update_rlc(adev, tmp); 2452 2453 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2454 2455 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2456 } else { 2457 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2458 2459 RREG32(mmCB_CGTT_SCLK_CTRL); 2460 RREG32(mmCB_CGTT_SCLK_CTRL); 2461 RREG32(mmCB_CGTT_SCLK_CTRL); 2462 RREG32(mmCB_CGTT_SCLK_CTRL); 2463 2464 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2465 } 2466 2467 if (orig != data) 2468 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2469 2470 } 2471 2472 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2473 { 2474 2475 u32 data, orig, tmp = 0; 2476 2477 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2478 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2479 data = 0x96940200; 2480 if (orig != data) 2481 WREG32(mmCGTS_SM_CTRL_REG, data); 2482 2483 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2484 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2485 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2486 if (orig != data) 2487 WREG32(mmCP_MEM_SLP_CNTL, data); 2488 } 2489 2490 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2491 data &= 0xffffffc0; 2492 if (orig != data) 2493 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2494 2495 tmp = gfx_v6_0_halt_rlc(adev); 2496 2497 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2498 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2499 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2500 2501 gfx_v6_0_update_rlc(adev, tmp); 2502 } else { 2503 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2504 data |= 0x00000003; 2505 if (orig != data) 2506 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2507 2508 data = RREG32(mmCP_MEM_SLP_CNTL); 2509 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2510 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2511 WREG32(mmCP_MEM_SLP_CNTL, data); 2512 } 2513 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2514 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2515 if (orig != data) 2516 WREG32(mmCGTS_SM_CTRL_REG, data); 2517 2518 tmp = gfx_v6_0_halt_rlc(adev); 2519 2520 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2521 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2522 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2523 2524 gfx_v6_0_update_rlc(adev, tmp); 2525 } 2526 } 2527 /* 2528 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2529 bool enable) 2530 { 2531 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2532 if (enable) { 2533 gfx_v6_0_enable_mgcg(adev, true); 2534 gfx_v6_0_enable_cgcg(adev, true); 2535 } else { 2536 gfx_v6_0_enable_cgcg(adev, false); 2537 gfx_v6_0_enable_mgcg(adev, false); 2538 } 2539 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2540 } 2541 */ 2542 2543 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2544 bool enable) 2545 { 2546 } 2547 2548 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2549 bool enable) 2550 { 2551 } 2552 2553 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2554 { 2555 u32 data, orig; 2556 2557 orig = data = RREG32(mmRLC_PG_CNTL); 2558 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2559 data &= ~0x8000; 2560 else 2561 data |= 0x8000; 2562 if (orig != data) 2563 WREG32(mmRLC_PG_CNTL, data); 2564 } 2565 2566 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2567 { 2568 } 2569 /* 2570 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2571 { 2572 const __le32 *fw_data; 2573 volatile u32 *dst_ptr; 2574 int me, i, max_me = 4; 2575 u32 bo_offset = 0; 2576 u32 table_offset, table_size; 2577 2578 if (adev->asic_type == CHIP_KAVERI) 2579 max_me = 5; 2580 2581 if (adev->gfx.rlc.cp_table_ptr == NULL) 2582 return; 2583 2584 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2585 for (me = 0; me < max_me; me++) { 2586 if (me == 0) { 2587 const struct gfx_firmware_header_v1_0 *hdr = 2588 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2589 fw_data = (const __le32 *) 2590 (adev->gfx.ce_fw->data + 2591 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2592 table_offset = le32_to_cpu(hdr->jt_offset); 2593 table_size = le32_to_cpu(hdr->jt_size); 2594 } else if (me == 1) { 2595 const struct gfx_firmware_header_v1_0 *hdr = 2596 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2597 fw_data = (const __le32 *) 2598 (adev->gfx.pfp_fw->data + 2599 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2600 table_offset = le32_to_cpu(hdr->jt_offset); 2601 table_size = le32_to_cpu(hdr->jt_size); 2602 } else if (me == 2) { 2603 const struct gfx_firmware_header_v1_0 *hdr = 2604 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2605 fw_data = (const __le32 *) 2606 (adev->gfx.me_fw->data + 2607 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2608 table_offset = le32_to_cpu(hdr->jt_offset); 2609 table_size = le32_to_cpu(hdr->jt_size); 2610 } else if (me == 3) { 2611 const struct gfx_firmware_header_v1_0 *hdr = 2612 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2613 fw_data = (const __le32 *) 2614 (adev->gfx.mec_fw->data + 2615 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2616 table_offset = le32_to_cpu(hdr->jt_offset); 2617 table_size = le32_to_cpu(hdr->jt_size); 2618 } else { 2619 const struct gfx_firmware_header_v1_0 *hdr = 2620 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2621 fw_data = (const __le32 *) 2622 (adev->gfx.mec2_fw->data + 2623 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2624 table_offset = le32_to_cpu(hdr->jt_offset); 2625 table_size = le32_to_cpu(hdr->jt_size); 2626 } 2627 2628 for (i = 0; i < table_size; i ++) { 2629 dst_ptr[bo_offset + i] = 2630 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2631 } 2632 2633 bo_offset += table_size; 2634 } 2635 } 2636 */ 2637 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2638 bool enable) 2639 { 2640 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2641 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2642 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2643 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2644 } else { 2645 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2646 (void)RREG32(mmDB_RENDER_CONTROL); 2647 } 2648 } 2649 2650 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2651 { 2652 u32 tmp; 2653 2654 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2655 2656 tmp = RREG32(mmRLC_MAX_PG_CU); 2657 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2658 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2659 WREG32(mmRLC_MAX_PG_CU, tmp); 2660 } 2661 2662 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2663 bool enable) 2664 { 2665 u32 data, orig; 2666 2667 orig = data = RREG32(mmRLC_PG_CNTL); 2668 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2669 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2670 else 2671 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2672 if (orig != data) 2673 WREG32(mmRLC_PG_CNTL, data); 2674 } 2675 2676 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2677 bool enable) 2678 { 2679 u32 data, orig; 2680 2681 orig = data = RREG32(mmRLC_PG_CNTL); 2682 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2683 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2684 else 2685 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2686 if (orig != data) 2687 WREG32(mmRLC_PG_CNTL, data); 2688 } 2689 2690 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2691 { 2692 u32 tmp; 2693 2694 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2695 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2696 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2697 2698 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2699 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2700 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2701 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2702 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2703 } 2704 2705 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2706 { 2707 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2708 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2709 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2710 } 2711 2712 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2713 { 2714 u32 count = 0; 2715 const struct cs_section_def *sect = NULL; 2716 const struct cs_extent_def *ext = NULL; 2717 2718 if (adev->gfx.rlc.cs_data == NULL) 2719 return 0; 2720 2721 /* begin clear state */ 2722 count += 2; 2723 /* context control state */ 2724 count += 3; 2725 2726 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2727 for (ext = sect->section; ext->extent != NULL; ++ext) { 2728 if (sect->id == SECT_CONTEXT) 2729 count += 2 + ext->reg_count; 2730 else 2731 return 0; 2732 } 2733 } 2734 /* pa_sc_raster_config */ 2735 count += 3; 2736 /* end clear state */ 2737 count += 2; 2738 /* clear state */ 2739 count += 2; 2740 2741 return count; 2742 } 2743 2744 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 2745 volatile u32 *buffer) 2746 { 2747 u32 count = 0, i; 2748 const struct cs_section_def *sect = NULL; 2749 const struct cs_extent_def *ext = NULL; 2750 2751 if (adev->gfx.rlc.cs_data == NULL) 2752 return; 2753 if (buffer == NULL) 2754 return; 2755 2756 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2757 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2758 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2759 buffer[count++] = cpu_to_le32(0x80000000); 2760 buffer[count++] = cpu_to_le32(0x80000000); 2761 2762 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2763 for (ext = sect->section; ext->extent != NULL; ++ext) { 2764 if (sect->id == SECT_CONTEXT) { 2765 buffer[count++] = 2766 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2767 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); 2768 for (i = 0; i < ext->reg_count; i++) 2769 buffer[count++] = cpu_to_le32(ext->extent[i]); 2770 } else { 2771 return; 2772 } 2773 } 2774 } 2775 2776 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2777 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2778 2779 switch (adev->asic_type) { 2780 case CHIP_TAHITI: 2781 case CHIP_PITCAIRN: 2782 buffer[count++] = cpu_to_le32(0x2a00126a); 2783 break; 2784 case CHIP_VERDE: 2785 buffer[count++] = cpu_to_le32(0x0000124a); 2786 break; 2787 case CHIP_OLAND: 2788 buffer[count++] = cpu_to_le32(0x00000082); 2789 break; 2790 case CHIP_HAINAN: 2791 buffer[count++] = cpu_to_le32(0x00000000); 2792 break; 2793 default: 2794 buffer[count++] = cpu_to_le32(0x00000000); 2795 break; 2796 } 2797 2798 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2799 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 2800 2801 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 2802 buffer[count++] = cpu_to_le32(0); 2803 } 2804 2805 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2806 { 2807 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2808 AMD_PG_SUPPORT_GFX_SMG | 2809 AMD_PG_SUPPORT_GFX_DMG | 2810 AMD_PG_SUPPORT_CP | 2811 AMD_PG_SUPPORT_GDS | 2812 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2813 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2814 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2815 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2816 gfx_v6_0_init_gfx_cgpg(adev); 2817 gfx_v6_0_enable_cp_pg(adev, true); 2818 gfx_v6_0_enable_gds_pg(adev, true); 2819 } else { 2820 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2821 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2822 2823 } 2824 gfx_v6_0_init_ao_cu_mask(adev); 2825 gfx_v6_0_update_gfx_pg(adev, true); 2826 } else { 2827 2828 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2829 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2830 } 2831 } 2832 2833 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 2834 { 2835 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2836 AMD_PG_SUPPORT_GFX_SMG | 2837 AMD_PG_SUPPORT_GFX_DMG | 2838 AMD_PG_SUPPORT_CP | 2839 AMD_PG_SUPPORT_GDS | 2840 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2841 gfx_v6_0_update_gfx_pg(adev, false); 2842 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2843 gfx_v6_0_enable_cp_pg(adev, false); 2844 gfx_v6_0_enable_gds_pg(adev, false); 2845 } 2846 } 2847 } 2848 2849 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 2850 { 2851 uint64_t clock; 2852 2853 mutex_lock(&adev->gfx.gpu_clock_mutex); 2854 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2855 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 2856 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2857 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2858 return clock; 2859 } 2860 2861 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2862 { 2863 if (flags & AMDGPU_HAVE_CTX_SWITCH) 2864 gfx_v6_0_ring_emit_vgt_flush(ring); 2865 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2866 amdgpu_ring_write(ring, 0x80000000); 2867 amdgpu_ring_write(ring, 0); 2868 } 2869 2870 2871 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 2872 { 2873 WREG32(mmSQ_IND_INDEX, 2874 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2875 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2876 (address << SQ_IND_INDEX__INDEX__SHIFT) | 2877 (SQ_IND_INDEX__FORCE_READ_MASK)); 2878 return RREG32(mmSQ_IND_DATA); 2879 } 2880 2881 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 2882 uint32_t wave, uint32_t thread, 2883 uint32_t regno, uint32_t num, uint32_t *out) 2884 { 2885 WREG32(mmSQ_IND_INDEX, 2886 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2887 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2888 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 2889 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 2890 (SQ_IND_INDEX__FORCE_READ_MASK) | 2891 (SQ_IND_INDEX__AUTO_INCR_MASK)); 2892 while (num--) 2893 *(out++) = RREG32(mmSQ_IND_DATA); 2894 } 2895 2896 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 2897 { 2898 /* type 0 wave data */ 2899 dst[(*no_fields)++] = 0; 2900 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 2901 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 2902 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 2903 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 2904 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 2905 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 2906 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 2907 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 2908 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 2909 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 2910 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 2911 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 2912 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 2913 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 2914 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 2915 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 2916 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 2917 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 2918 } 2919 2920 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 2921 uint32_t wave, uint32_t start, 2922 uint32_t size, uint32_t *dst) 2923 { 2924 wave_read_regs( 2925 adev, simd, wave, 0, 2926 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 2927 } 2928 2929 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 2930 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 2931 .select_se_sh = &gfx_v6_0_select_se_sh, 2932 .read_wave_data = &gfx_v6_0_read_wave_data, 2933 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 2934 }; 2935 2936 static int gfx_v6_0_early_init(void *handle) 2937 { 2938 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2939 2940 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 2941 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS; 2942 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 2943 gfx_v6_0_set_ring_funcs(adev); 2944 gfx_v6_0_set_irq_funcs(adev); 2945 2946 return 0; 2947 } 2948 2949 static int gfx_v6_0_sw_init(void *handle) 2950 { 2951 struct amdgpu_ring *ring; 2952 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2953 int i, r; 2954 2955 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 2956 if (r) 2957 return r; 2958 2959 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 2960 if (r) 2961 return r; 2962 2963 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 2964 if (r) 2965 return r; 2966 2967 gfx_v6_0_scratch_init(adev); 2968 2969 r = gfx_v6_0_init_microcode(adev); 2970 if (r) { 2971 DRM_ERROR("Failed to load gfx firmware!\n"); 2972 return r; 2973 } 2974 2975 r = gfx_v6_0_rlc_init(adev); 2976 if (r) { 2977 DRM_ERROR("Failed to init rlc BOs!\n"); 2978 return r; 2979 } 2980 2981 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2982 ring = &adev->gfx.gfx_ring[i]; 2983 ring->ring_obj = NULL; 2984 sprintf(ring->name, "gfx"); 2985 r = amdgpu_ring_init(adev, ring, 1024, 2986 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 2987 if (r) 2988 return r; 2989 } 2990 2991 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2992 unsigned irq_type; 2993 2994 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 2995 DRM_ERROR("Too many (%d) compute rings!\n", i); 2996 break; 2997 } 2998 ring = &adev->gfx.compute_ring[i]; 2999 ring->ring_obj = NULL; 3000 ring->use_doorbell = false; 3001 ring->doorbell_index = 0; 3002 ring->me = 1; 3003 ring->pipe = i; 3004 ring->queue = i; 3005 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3006 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3007 r = amdgpu_ring_init(adev, ring, 1024, 3008 &adev->gfx.eop_irq, irq_type); 3009 if (r) 3010 return r; 3011 } 3012 3013 return r; 3014 } 3015 3016 static int gfx_v6_0_sw_fini(void *handle) 3017 { 3018 int i; 3019 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3020 3021 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3022 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3023 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3024 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3025 3026 gfx_v6_0_rlc_fini(adev); 3027 3028 return 0; 3029 } 3030 3031 static int gfx_v6_0_hw_init(void *handle) 3032 { 3033 int r; 3034 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3035 3036 gfx_v6_0_gpu_init(adev); 3037 3038 r = gfx_v6_0_rlc_resume(adev); 3039 if (r) 3040 return r; 3041 3042 r = gfx_v6_0_cp_resume(adev); 3043 if (r) 3044 return r; 3045 3046 adev->gfx.ce_ram_size = 0x8000; 3047 3048 return r; 3049 } 3050 3051 static int gfx_v6_0_hw_fini(void *handle) 3052 { 3053 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3054 3055 gfx_v6_0_cp_enable(adev, false); 3056 gfx_v6_0_rlc_stop(adev); 3057 gfx_v6_0_fini_pg(adev); 3058 3059 return 0; 3060 } 3061 3062 static int gfx_v6_0_suspend(void *handle) 3063 { 3064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3065 3066 return gfx_v6_0_hw_fini(adev); 3067 } 3068 3069 static int gfx_v6_0_resume(void *handle) 3070 { 3071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3072 3073 return gfx_v6_0_hw_init(adev); 3074 } 3075 3076 static bool gfx_v6_0_is_idle(void *handle) 3077 { 3078 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3079 3080 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3081 return false; 3082 else 3083 return true; 3084 } 3085 3086 static int gfx_v6_0_wait_for_idle(void *handle) 3087 { 3088 unsigned i; 3089 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3090 3091 for (i = 0; i < adev->usec_timeout; i++) { 3092 if (gfx_v6_0_is_idle(handle)) 3093 return 0; 3094 udelay(1); 3095 } 3096 return -ETIMEDOUT; 3097 } 3098 3099 static int gfx_v6_0_soft_reset(void *handle) 3100 { 3101 return 0; 3102 } 3103 3104 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3105 enum amdgpu_interrupt_state state) 3106 { 3107 u32 cp_int_cntl; 3108 3109 switch (state) { 3110 case AMDGPU_IRQ_STATE_DISABLE: 3111 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3112 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3113 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3114 break; 3115 case AMDGPU_IRQ_STATE_ENABLE: 3116 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3117 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3118 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3119 break; 3120 default: 3121 break; 3122 } 3123 } 3124 3125 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3126 int ring, 3127 enum amdgpu_interrupt_state state) 3128 { 3129 u32 cp_int_cntl; 3130 switch (state){ 3131 case AMDGPU_IRQ_STATE_DISABLE: 3132 if (ring == 0) { 3133 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3134 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3135 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3136 break; 3137 } else { 3138 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3139 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3140 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3141 break; 3142 3143 } 3144 case AMDGPU_IRQ_STATE_ENABLE: 3145 if (ring == 0) { 3146 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3147 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3148 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3149 break; 3150 } else { 3151 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3152 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3153 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3154 break; 3155 3156 } 3157 3158 default: 3159 BUG(); 3160 break; 3161 3162 } 3163 } 3164 3165 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3166 struct amdgpu_irq_src *src, 3167 unsigned type, 3168 enum amdgpu_interrupt_state state) 3169 { 3170 u32 cp_int_cntl; 3171 3172 switch (state) { 3173 case AMDGPU_IRQ_STATE_DISABLE: 3174 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3175 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3176 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3177 break; 3178 case AMDGPU_IRQ_STATE_ENABLE: 3179 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3180 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3181 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3182 break; 3183 default: 3184 break; 3185 } 3186 3187 return 0; 3188 } 3189 3190 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3191 struct amdgpu_irq_src *src, 3192 unsigned type, 3193 enum amdgpu_interrupt_state state) 3194 { 3195 u32 cp_int_cntl; 3196 3197 switch (state) { 3198 case AMDGPU_IRQ_STATE_DISABLE: 3199 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3200 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3201 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3202 break; 3203 case AMDGPU_IRQ_STATE_ENABLE: 3204 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3205 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3206 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3207 break; 3208 default: 3209 break; 3210 } 3211 3212 return 0; 3213 } 3214 3215 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3216 struct amdgpu_irq_src *src, 3217 unsigned type, 3218 enum amdgpu_interrupt_state state) 3219 { 3220 switch (type) { 3221 case AMDGPU_CP_IRQ_GFX_EOP: 3222 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3223 break; 3224 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3225 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3226 break; 3227 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3228 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3229 break; 3230 default: 3231 break; 3232 } 3233 return 0; 3234 } 3235 3236 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3237 struct amdgpu_irq_src *source, 3238 struct amdgpu_iv_entry *entry) 3239 { 3240 switch (entry->ring_id) { 3241 case 0: 3242 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3243 break; 3244 case 1: 3245 case 2: 3246 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3247 break; 3248 default: 3249 break; 3250 } 3251 return 0; 3252 } 3253 3254 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3255 struct amdgpu_irq_src *source, 3256 struct amdgpu_iv_entry *entry) 3257 { 3258 DRM_ERROR("Illegal register access in command stream\n"); 3259 schedule_work(&adev->reset_work); 3260 return 0; 3261 } 3262 3263 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3264 struct amdgpu_irq_src *source, 3265 struct amdgpu_iv_entry *entry) 3266 { 3267 DRM_ERROR("Illegal instruction in command stream\n"); 3268 schedule_work(&adev->reset_work); 3269 return 0; 3270 } 3271 3272 static int gfx_v6_0_set_clockgating_state(void *handle, 3273 enum amd_clockgating_state state) 3274 { 3275 bool gate = false; 3276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3277 3278 if (state == AMD_CG_STATE_GATE) 3279 gate = true; 3280 3281 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3282 if (gate) { 3283 gfx_v6_0_enable_mgcg(adev, true); 3284 gfx_v6_0_enable_cgcg(adev, true); 3285 } else { 3286 gfx_v6_0_enable_cgcg(adev, false); 3287 gfx_v6_0_enable_mgcg(adev, false); 3288 } 3289 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3290 3291 return 0; 3292 } 3293 3294 static int gfx_v6_0_set_powergating_state(void *handle, 3295 enum amd_powergating_state state) 3296 { 3297 bool gate = false; 3298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3299 3300 if (state == AMD_PG_STATE_GATE) 3301 gate = true; 3302 3303 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3304 AMD_PG_SUPPORT_GFX_SMG | 3305 AMD_PG_SUPPORT_GFX_DMG | 3306 AMD_PG_SUPPORT_CP | 3307 AMD_PG_SUPPORT_GDS | 3308 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3309 gfx_v6_0_update_gfx_pg(adev, gate); 3310 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3311 gfx_v6_0_enable_cp_pg(adev, gate); 3312 gfx_v6_0_enable_gds_pg(adev, gate); 3313 } 3314 } 3315 3316 return 0; 3317 } 3318 3319 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3320 .name = "gfx_v6_0", 3321 .early_init = gfx_v6_0_early_init, 3322 .late_init = NULL, 3323 .sw_init = gfx_v6_0_sw_init, 3324 .sw_fini = gfx_v6_0_sw_fini, 3325 .hw_init = gfx_v6_0_hw_init, 3326 .hw_fini = gfx_v6_0_hw_fini, 3327 .suspend = gfx_v6_0_suspend, 3328 .resume = gfx_v6_0_resume, 3329 .is_idle = gfx_v6_0_is_idle, 3330 .wait_for_idle = gfx_v6_0_wait_for_idle, 3331 .soft_reset = gfx_v6_0_soft_reset, 3332 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3333 .set_powergating_state = gfx_v6_0_set_powergating_state, 3334 }; 3335 3336 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3337 .type = AMDGPU_RING_TYPE_GFX, 3338 .align_mask = 0xff, 3339 .nop = 0x80000000, 3340 .support_64bit_ptrs = false, 3341 .get_rptr = gfx_v6_0_ring_get_rptr, 3342 .get_wptr = gfx_v6_0_ring_get_wptr, 3343 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3344 .emit_frame_size = 3345 5 + /* gfx_v6_0_ring_emit_hdp_flush */ 3346 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ 3347 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3348 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3349 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3350 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3351 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3352 .emit_ib = gfx_v6_0_ring_emit_ib, 3353 .emit_fence = gfx_v6_0_ring_emit_fence, 3354 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3355 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3356 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, 3357 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, 3358 .test_ring = gfx_v6_0_ring_test_ring, 3359 .test_ib = gfx_v6_0_ring_test_ib, 3360 .insert_nop = amdgpu_ring_insert_nop, 3361 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3362 }; 3363 3364 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3365 .type = AMDGPU_RING_TYPE_COMPUTE, 3366 .align_mask = 0xff, 3367 .nop = 0x80000000, 3368 .get_rptr = gfx_v6_0_ring_get_rptr, 3369 .get_wptr = gfx_v6_0_ring_get_wptr, 3370 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3371 .emit_frame_size = 3372 5 + /* gfx_v6_0_ring_emit_hdp_flush */ 3373 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ 3374 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3375 17 + /* gfx_v6_0_ring_emit_vm_flush */ 3376 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3377 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3378 .emit_ib = gfx_v6_0_ring_emit_ib, 3379 .emit_fence = gfx_v6_0_ring_emit_fence, 3380 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3381 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3382 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, 3383 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, 3384 .test_ring = gfx_v6_0_ring_test_ring, 3385 .test_ib = gfx_v6_0_ring_test_ib, 3386 .insert_nop = amdgpu_ring_insert_nop, 3387 }; 3388 3389 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3390 { 3391 int i; 3392 3393 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3394 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3395 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3396 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3397 } 3398 3399 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3400 .set = gfx_v6_0_set_eop_interrupt_state, 3401 .process = gfx_v6_0_eop_irq, 3402 }; 3403 3404 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3405 .set = gfx_v6_0_set_priv_reg_fault_state, 3406 .process = gfx_v6_0_priv_reg_irq, 3407 }; 3408 3409 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3410 .set = gfx_v6_0_set_priv_inst_fault_state, 3411 .process = gfx_v6_0_priv_inst_irq, 3412 }; 3413 3414 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3415 { 3416 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3417 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3418 3419 adev->gfx.priv_reg_irq.num_types = 1; 3420 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3421 3422 adev->gfx.priv_inst_irq.num_types = 1; 3423 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3424 } 3425 3426 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3427 { 3428 int i, j, k, counter, active_cu_number = 0; 3429 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3430 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3431 unsigned disable_masks[4 * 2]; 3432 u32 ao_cu_num; 3433 3434 if (adev->flags & AMD_IS_APU) 3435 ao_cu_num = 2; 3436 else 3437 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3438 3439 memset(cu_info, 0, sizeof(*cu_info)); 3440 3441 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 3442 3443 mutex_lock(&adev->grbm_idx_mutex); 3444 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3445 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3446 mask = 1; 3447 ao_bitmap = 0; 3448 counter = 0; 3449 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 3450 if (i < 4 && j < 2) 3451 gfx_v6_0_set_user_cu_inactive_bitmap( 3452 adev, disable_masks[i * 2 + j]); 3453 bitmap = gfx_v6_0_get_cu_enabled(adev); 3454 cu_info->bitmap[i][j] = bitmap; 3455 3456 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3457 if (bitmap & mask) { 3458 if (counter < ao_cu_num) 3459 ao_bitmap |= mask; 3460 counter ++; 3461 } 3462 mask <<= 1; 3463 } 3464 active_cu_number += counter; 3465 if (i < 2 && j < 2) 3466 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3467 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3468 } 3469 } 3470 3471 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3472 mutex_unlock(&adev->grbm_idx_mutex); 3473 3474 cu_info->number = active_cu_number; 3475 cu_info->ao_cu_mask = ao_cu_mask; 3476 } 3477 3478 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3479 { 3480 .type = AMD_IP_BLOCK_TYPE_GFX, 3481 .major = 6, 3482 .minor = 0, 3483 .rev = 0, 3484 .funcs = &gfx_v6_0_ip_funcs, 3485 }; 3486