1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "amdgpu_gfx.h" 27 #include "amdgpu_ucode.h" 28 #include "clearstate_si.h" 29 #include "bif/bif_3_0_d.h" 30 #include "bif/bif_3_0_sh_mask.h" 31 #include "oss/oss_1_0_d.h" 32 #include "oss/oss_1_0_sh_mask.h" 33 #include "gca/gfx_6_0_d.h" 34 #include "gca/gfx_6_0_sh_mask.h" 35 #include "gmc/gmc_6_0_d.h" 36 #include "gmc/gmc_6_0_sh_mask.h" 37 #include "dce/dce_6_0_d.h" 38 #include "dce/dce_6_0_sh_mask.h" 39 #include "gca/gfx_7_2_enum.h" 40 #include "si_enums.h" 41 #include "si.h" 42 43 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 44 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 45 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 46 47 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin"); 48 MODULE_FIRMWARE("amdgpu/tahiti_me.bin"); 49 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin"); 50 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin"); 51 52 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin"); 53 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin"); 54 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin"); 55 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin"); 56 57 MODULE_FIRMWARE("amdgpu/verde_pfp.bin"); 58 MODULE_FIRMWARE("amdgpu/verde_me.bin"); 59 MODULE_FIRMWARE("amdgpu/verde_ce.bin"); 60 MODULE_FIRMWARE("amdgpu/verde_rlc.bin"); 61 62 MODULE_FIRMWARE("amdgpu/oland_pfp.bin"); 63 MODULE_FIRMWARE("amdgpu/oland_me.bin"); 64 MODULE_FIRMWARE("amdgpu/oland_ce.bin"); 65 MODULE_FIRMWARE("amdgpu/oland_rlc.bin"); 66 67 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin"); 68 MODULE_FIRMWARE("amdgpu/hainan_me.bin"); 69 MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); 70 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); 71 72 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 73 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 74 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 75 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 76 77 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 78 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 79 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 80 #define MICRO_TILE_MODE(x) ((x) << 0) 81 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 82 #define BANK_WIDTH(x) ((x) << 14) 83 #define BANK_HEIGHT(x) ((x) << 16) 84 #define MACRO_TILE_ASPECT(x) ((x) << 18) 85 #define NUM_BANKS(x) ((x) << 20) 86 87 static const u32 verde_rlc_save_restore_register_list[] = 88 { 89 (0x8000 << 16) | (0x98f4 >> 2), 90 0x00000000, 91 (0x8040 << 16) | (0x98f4 >> 2), 92 0x00000000, 93 (0x8000 << 16) | (0xe80 >> 2), 94 0x00000000, 95 (0x8040 << 16) | (0xe80 >> 2), 96 0x00000000, 97 (0x8000 << 16) | (0x89bc >> 2), 98 0x00000000, 99 (0x8040 << 16) | (0x89bc >> 2), 100 0x00000000, 101 (0x8000 << 16) | (0x8c1c >> 2), 102 0x00000000, 103 (0x8040 << 16) | (0x8c1c >> 2), 104 0x00000000, 105 (0x9c00 << 16) | (0x98f0 >> 2), 106 0x00000000, 107 (0x9c00 << 16) | (0xe7c >> 2), 108 0x00000000, 109 (0x8000 << 16) | (0x9148 >> 2), 110 0x00000000, 111 (0x8040 << 16) | (0x9148 >> 2), 112 0x00000000, 113 (0x9c00 << 16) | (0x9150 >> 2), 114 0x00000000, 115 (0x9c00 << 16) | (0x897c >> 2), 116 0x00000000, 117 (0x9c00 << 16) | (0x8d8c >> 2), 118 0x00000000, 119 (0x9c00 << 16) | (0xac54 >> 2), 120 0X00000000, 121 0x3, 122 (0x9c00 << 16) | (0x98f8 >> 2), 123 0x00000000, 124 (0x9c00 << 16) | (0x9910 >> 2), 125 0x00000000, 126 (0x9c00 << 16) | (0x9914 >> 2), 127 0x00000000, 128 (0x9c00 << 16) | (0x9918 >> 2), 129 0x00000000, 130 (0x9c00 << 16) | (0x991c >> 2), 131 0x00000000, 132 (0x9c00 << 16) | (0x9920 >> 2), 133 0x00000000, 134 (0x9c00 << 16) | (0x9924 >> 2), 135 0x00000000, 136 (0x9c00 << 16) | (0x9928 >> 2), 137 0x00000000, 138 (0x9c00 << 16) | (0x992c >> 2), 139 0x00000000, 140 (0x9c00 << 16) | (0x9930 >> 2), 141 0x00000000, 142 (0x9c00 << 16) | (0x9934 >> 2), 143 0x00000000, 144 (0x9c00 << 16) | (0x9938 >> 2), 145 0x00000000, 146 (0x9c00 << 16) | (0x993c >> 2), 147 0x00000000, 148 (0x9c00 << 16) | (0x9940 >> 2), 149 0x00000000, 150 (0x9c00 << 16) | (0x9944 >> 2), 151 0x00000000, 152 (0x9c00 << 16) | (0x9948 >> 2), 153 0x00000000, 154 (0x9c00 << 16) | (0x994c >> 2), 155 0x00000000, 156 (0x9c00 << 16) | (0x9950 >> 2), 157 0x00000000, 158 (0x9c00 << 16) | (0x9954 >> 2), 159 0x00000000, 160 (0x9c00 << 16) | (0x9958 >> 2), 161 0x00000000, 162 (0x9c00 << 16) | (0x995c >> 2), 163 0x00000000, 164 (0x9c00 << 16) | (0x9960 >> 2), 165 0x00000000, 166 (0x9c00 << 16) | (0x9964 >> 2), 167 0x00000000, 168 (0x9c00 << 16) | (0x9968 >> 2), 169 0x00000000, 170 (0x9c00 << 16) | (0x996c >> 2), 171 0x00000000, 172 (0x9c00 << 16) | (0x9970 >> 2), 173 0x00000000, 174 (0x9c00 << 16) | (0x9974 >> 2), 175 0x00000000, 176 (0x9c00 << 16) | (0x9978 >> 2), 177 0x00000000, 178 (0x9c00 << 16) | (0x997c >> 2), 179 0x00000000, 180 (0x9c00 << 16) | (0x9980 >> 2), 181 0x00000000, 182 (0x9c00 << 16) | (0x9984 >> 2), 183 0x00000000, 184 (0x9c00 << 16) | (0x9988 >> 2), 185 0x00000000, 186 (0x9c00 << 16) | (0x998c >> 2), 187 0x00000000, 188 (0x9c00 << 16) | (0x8c00 >> 2), 189 0x00000000, 190 (0x9c00 << 16) | (0x8c14 >> 2), 191 0x00000000, 192 (0x9c00 << 16) | (0x8c04 >> 2), 193 0x00000000, 194 (0x9c00 << 16) | (0x8c08 >> 2), 195 0x00000000, 196 (0x8000 << 16) | (0x9b7c >> 2), 197 0x00000000, 198 (0x8040 << 16) | (0x9b7c >> 2), 199 0x00000000, 200 (0x8000 << 16) | (0xe84 >> 2), 201 0x00000000, 202 (0x8040 << 16) | (0xe84 >> 2), 203 0x00000000, 204 (0x8000 << 16) | (0x89c0 >> 2), 205 0x00000000, 206 (0x8040 << 16) | (0x89c0 >> 2), 207 0x00000000, 208 (0x8000 << 16) | (0x914c >> 2), 209 0x00000000, 210 (0x8040 << 16) | (0x914c >> 2), 211 0x00000000, 212 (0x8000 << 16) | (0x8c20 >> 2), 213 0x00000000, 214 (0x8040 << 16) | (0x8c20 >> 2), 215 0x00000000, 216 (0x8000 << 16) | (0x9354 >> 2), 217 0x00000000, 218 (0x8040 << 16) | (0x9354 >> 2), 219 0x00000000, 220 (0x9c00 << 16) | (0x9060 >> 2), 221 0x00000000, 222 (0x9c00 << 16) | (0x9364 >> 2), 223 0x00000000, 224 (0x9c00 << 16) | (0x9100 >> 2), 225 0x00000000, 226 (0x9c00 << 16) | (0x913c >> 2), 227 0x00000000, 228 (0x8000 << 16) | (0x90e0 >> 2), 229 0x00000000, 230 (0x8000 << 16) | (0x90e4 >> 2), 231 0x00000000, 232 (0x8000 << 16) | (0x90e8 >> 2), 233 0x00000000, 234 (0x8040 << 16) | (0x90e0 >> 2), 235 0x00000000, 236 (0x8040 << 16) | (0x90e4 >> 2), 237 0x00000000, 238 (0x8040 << 16) | (0x90e8 >> 2), 239 0x00000000, 240 (0x9c00 << 16) | (0x8bcc >> 2), 241 0x00000000, 242 (0x9c00 << 16) | (0x8b24 >> 2), 243 0x00000000, 244 (0x9c00 << 16) | (0x88c4 >> 2), 245 0x00000000, 246 (0x9c00 << 16) | (0x8e50 >> 2), 247 0x00000000, 248 (0x9c00 << 16) | (0x8c0c >> 2), 249 0x00000000, 250 (0x9c00 << 16) | (0x8e58 >> 2), 251 0x00000000, 252 (0x9c00 << 16) | (0x8e5c >> 2), 253 0x00000000, 254 (0x9c00 << 16) | (0x9508 >> 2), 255 0x00000000, 256 (0x9c00 << 16) | (0x950c >> 2), 257 0x00000000, 258 (0x9c00 << 16) | (0x9494 >> 2), 259 0x00000000, 260 (0x9c00 << 16) | (0xac0c >> 2), 261 0x00000000, 262 (0x9c00 << 16) | (0xac10 >> 2), 263 0x00000000, 264 (0x9c00 << 16) | (0xac14 >> 2), 265 0x00000000, 266 (0x9c00 << 16) | (0xae00 >> 2), 267 0x00000000, 268 (0x9c00 << 16) | (0xac08 >> 2), 269 0x00000000, 270 (0x9c00 << 16) | (0x88d4 >> 2), 271 0x00000000, 272 (0x9c00 << 16) | (0x88c8 >> 2), 273 0x00000000, 274 (0x9c00 << 16) | (0x88cc >> 2), 275 0x00000000, 276 (0x9c00 << 16) | (0x89b0 >> 2), 277 0x00000000, 278 (0x9c00 << 16) | (0x8b10 >> 2), 279 0x00000000, 280 (0x9c00 << 16) | (0x8a14 >> 2), 281 0x00000000, 282 (0x9c00 << 16) | (0x9830 >> 2), 283 0x00000000, 284 (0x9c00 << 16) | (0x9834 >> 2), 285 0x00000000, 286 (0x9c00 << 16) | (0x9838 >> 2), 287 0x00000000, 288 (0x9c00 << 16) | (0x9a10 >> 2), 289 0x00000000, 290 (0x8000 << 16) | (0x9870 >> 2), 291 0x00000000, 292 (0x8000 << 16) | (0x9874 >> 2), 293 0x00000000, 294 (0x8001 << 16) | (0x9870 >> 2), 295 0x00000000, 296 (0x8001 << 16) | (0x9874 >> 2), 297 0x00000000, 298 (0x8040 << 16) | (0x9870 >> 2), 299 0x00000000, 300 (0x8040 << 16) | (0x9874 >> 2), 301 0x00000000, 302 (0x8041 << 16) | (0x9870 >> 2), 303 0x00000000, 304 (0x8041 << 16) | (0x9874 >> 2), 305 0x00000000, 306 0x00000000 307 }; 308 309 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 310 { 311 const char *chip_name; 312 char fw_name[30]; 313 int err; 314 const struct gfx_firmware_header_v1_0 *cp_hdr; 315 const struct rlc_firmware_header_v1_0 *rlc_hdr; 316 317 DRM_DEBUG("\n"); 318 319 switch (adev->asic_type) { 320 case CHIP_TAHITI: 321 chip_name = "tahiti"; 322 break; 323 case CHIP_PITCAIRN: 324 chip_name = "pitcairn"; 325 break; 326 case CHIP_VERDE: 327 chip_name = "verde"; 328 break; 329 case CHIP_OLAND: 330 chip_name = "oland"; 331 break; 332 case CHIP_HAINAN: 333 chip_name = "hainan"; 334 break; 335 default: BUG(); 336 } 337 338 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 339 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 340 if (err) 341 goto out; 342 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 343 if (err) 344 goto out; 345 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 346 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 347 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 348 349 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 350 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 351 if (err) 352 goto out; 353 err = amdgpu_ucode_validate(adev->gfx.me_fw); 354 if (err) 355 goto out; 356 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 357 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 358 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 359 360 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 361 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 362 if (err) 363 goto out; 364 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 365 if (err) 366 goto out; 367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 368 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 369 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 370 371 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 372 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 373 if (err) 374 goto out; 375 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 376 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 377 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 378 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 379 380 out: 381 if (err) { 382 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name); 383 release_firmware(adev->gfx.pfp_fw); 384 adev->gfx.pfp_fw = NULL; 385 release_firmware(adev->gfx.me_fw); 386 adev->gfx.me_fw = NULL; 387 release_firmware(adev->gfx.ce_fw); 388 adev->gfx.ce_fw = NULL; 389 release_firmware(adev->gfx.rlc_fw); 390 adev->gfx.rlc_fw = NULL; 391 } 392 return err; 393 } 394 395 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 396 { 397 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 398 u32 reg_offset, split_equal_to_row_size, *tilemode; 399 400 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 401 tilemode = adev->gfx.config.tile_mode_array; 402 403 switch (adev->gfx.config.mem_row_size_in_kb) { 404 case 1: 405 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 406 break; 407 case 2: 408 default: 409 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 410 break; 411 case 4: 412 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 413 break; 414 } 415 416 if (adev->asic_type == CHIP_VERDE) { 417 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 418 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 419 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 421 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 424 NUM_BANKS(ADDR_SURF_16_BANK); 425 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 426 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 427 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 428 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 429 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 432 NUM_BANKS(ADDR_SURF_16_BANK); 433 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 434 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 435 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 436 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 437 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 440 NUM_BANKS(ADDR_SURF_16_BANK); 441 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 442 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 443 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 447 NUM_BANKS(ADDR_SURF_8_BANK) | 448 TILE_SPLIT(split_equal_to_row_size); 449 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 450 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 451 PIPE_CONFIG(ADDR_SURF_P4_8x16); 452 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 453 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 454 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 456 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 459 NUM_BANKS(ADDR_SURF_4_BANK); 460 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 461 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 462 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 464 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 466 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 467 NUM_BANKS(ADDR_SURF_4_BANK); 468 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 469 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 470 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 475 NUM_BANKS(ADDR_SURF_2_BANK); 476 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 477 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 478 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 479 PIPE_CONFIG(ADDR_SURF_P4_8x16); 480 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 481 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 482 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 483 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 484 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 487 NUM_BANKS(ADDR_SURF_16_BANK); 488 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 489 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 490 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 492 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 495 NUM_BANKS(ADDR_SURF_16_BANK); 496 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 497 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 498 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 499 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 500 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 501 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 502 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 503 NUM_BANKS(ADDR_SURF_16_BANK); 504 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 505 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 506 PIPE_CONFIG(ADDR_SURF_P4_8x16); 507 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 508 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 509 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 510 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 514 NUM_BANKS(ADDR_SURF_16_BANK); 515 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 516 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 517 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 519 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 522 NUM_BANKS(ADDR_SURF_16_BANK); 523 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 524 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 525 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 527 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 530 NUM_BANKS(ADDR_SURF_16_BANK); 531 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 532 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 533 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 534 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 537 NUM_BANKS(ADDR_SURF_16_BANK) | 538 TILE_SPLIT(split_equal_to_row_size); 539 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 540 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 541 PIPE_CONFIG(ADDR_SURF_P4_8x16); 542 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 543 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 544 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 545 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 548 NUM_BANKS(ADDR_SURF_16_BANK) | 549 TILE_SPLIT(split_equal_to_row_size); 550 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 551 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 552 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 556 NUM_BANKS(ADDR_SURF_16_BANK) | 557 TILE_SPLIT(split_equal_to_row_size); 558 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 559 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 560 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 562 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 563 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 564 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 565 NUM_BANKS(ADDR_SURF_8_BANK); 566 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 568 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 569 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 570 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 571 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 572 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 573 NUM_BANKS(ADDR_SURF_8_BANK); 574 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 575 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 576 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 577 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 579 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 580 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 581 NUM_BANKS(ADDR_SURF_4_BANK); 582 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 583 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 584 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 585 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 586 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 587 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 588 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 589 NUM_BANKS(ADDR_SURF_4_BANK); 590 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 591 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 592 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 593 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 597 NUM_BANKS(ADDR_SURF_2_BANK); 598 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 599 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 600 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 602 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 603 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 604 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 605 NUM_BANKS(ADDR_SURF_2_BANK); 606 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 607 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 608 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 609 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 610 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 611 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 612 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 613 NUM_BANKS(ADDR_SURF_2_BANK); 614 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 615 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 616 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 617 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 618 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 621 NUM_BANKS(ADDR_SURF_2_BANK); 622 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 623 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 624 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 625 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 626 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 629 NUM_BANKS(ADDR_SURF_2_BANK); 630 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 631 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 632 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 634 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 637 NUM_BANKS(ADDR_SURF_2_BANK); 638 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 639 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 640 } else if (adev->asic_type == CHIP_OLAND) { 641 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 643 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 645 NUM_BANKS(ADDR_SURF_16_BANK) | 646 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 649 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 650 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 651 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 652 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 653 NUM_BANKS(ADDR_SURF_16_BANK) | 654 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 657 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 658 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 659 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 660 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 661 NUM_BANKS(ADDR_SURF_16_BANK) | 662 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 665 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 666 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 667 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 668 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 669 NUM_BANKS(ADDR_SURF_16_BANK) | 670 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 673 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 674 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 675 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 676 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 677 NUM_BANKS(ADDR_SURF_16_BANK) | 678 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 681 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 683 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 684 TILE_SPLIT(split_equal_to_row_size) | 685 NUM_BANKS(ADDR_SURF_16_BANK) | 686 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 687 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 688 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 689 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 690 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 691 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 692 TILE_SPLIT(split_equal_to_row_size) | 693 NUM_BANKS(ADDR_SURF_16_BANK) | 694 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 697 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 698 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 699 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 700 TILE_SPLIT(split_equal_to_row_size) | 701 NUM_BANKS(ADDR_SURF_16_BANK) | 702 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 703 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 704 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 705 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 706 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 707 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 708 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 709 NUM_BANKS(ADDR_SURF_16_BANK) | 710 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 711 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 712 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 713 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 714 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 715 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 716 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 717 NUM_BANKS(ADDR_SURF_16_BANK) | 718 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 721 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 722 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 723 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 725 NUM_BANKS(ADDR_SURF_16_BANK) | 726 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 727 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 728 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 729 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 730 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 731 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 732 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 733 NUM_BANKS(ADDR_SURF_16_BANK) | 734 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 737 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 738 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 739 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 740 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 741 NUM_BANKS(ADDR_SURF_16_BANK) | 742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 745 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 746 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 747 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 748 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 749 NUM_BANKS(ADDR_SURF_16_BANK) | 750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 753 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 754 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 755 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 756 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 757 NUM_BANKS(ADDR_SURF_16_BANK) | 758 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 759 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 760 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 761 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 762 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 763 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 764 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 765 NUM_BANKS(ADDR_SURF_16_BANK) | 766 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 767 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 768 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 769 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 770 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 771 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 772 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 773 NUM_BANKS(ADDR_SURF_16_BANK) | 774 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 775 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 776 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 777 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 778 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 779 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 780 TILE_SPLIT(split_equal_to_row_size) | 781 NUM_BANKS(ADDR_SURF_16_BANK) | 782 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 785 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 786 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 787 PIPE_CONFIG(ADDR_SURF_P4_8x16); 788 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 789 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 790 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 791 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 792 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 793 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 794 NUM_BANKS(ADDR_SURF_16_BANK) | 795 TILE_SPLIT(split_equal_to_row_size); 796 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 797 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 798 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 799 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 800 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 801 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 802 NUM_BANKS(ADDR_SURF_16_BANK) | 803 TILE_SPLIT(split_equal_to_row_size); 804 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 805 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 806 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 807 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 808 NUM_BANKS(ADDR_SURF_16_BANK) | 809 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 810 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 811 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 812 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 813 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 814 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 815 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 816 NUM_BANKS(ADDR_SURF_16_BANK) | 817 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 820 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 821 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 822 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 823 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 824 NUM_BANKS(ADDR_SURF_16_BANK) | 825 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 828 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 829 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 830 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 831 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 832 NUM_BANKS(ADDR_SURF_16_BANK) | 833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 836 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 837 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 838 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 839 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 840 NUM_BANKS(ADDR_SURF_8_BANK) | 841 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 842 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 843 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); 844 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 845 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 846 } else if (adev->asic_type == CHIP_HAINAN) { 847 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 848 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 849 PIPE_CONFIG(ADDR_SURF_P2) | 850 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 851 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 852 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 853 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 854 NUM_BANKS(ADDR_SURF_16_BANK); 855 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 856 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 857 PIPE_CONFIG(ADDR_SURF_P2) | 858 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 859 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 860 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 861 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 862 NUM_BANKS(ADDR_SURF_16_BANK); 863 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 864 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 865 PIPE_CONFIG(ADDR_SURF_P2) | 866 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 867 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 868 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 869 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 870 NUM_BANKS(ADDR_SURF_16_BANK); 871 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 872 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 873 PIPE_CONFIG(ADDR_SURF_P2) | 874 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 875 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 876 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 877 NUM_BANKS(ADDR_SURF_8_BANK) | 878 TILE_SPLIT(split_equal_to_row_size); 879 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 880 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 881 PIPE_CONFIG(ADDR_SURF_P2); 882 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 883 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 884 PIPE_CONFIG(ADDR_SURF_P2) | 885 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 886 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 887 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 888 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 889 NUM_BANKS(ADDR_SURF_8_BANK); 890 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 891 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 892 PIPE_CONFIG(ADDR_SURF_P2) | 893 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 894 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 895 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 896 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 897 NUM_BANKS(ADDR_SURF_8_BANK); 898 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 899 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 900 PIPE_CONFIG(ADDR_SURF_P2) | 901 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 902 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 903 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 904 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 905 NUM_BANKS(ADDR_SURF_4_BANK); 906 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 907 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 908 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 909 PIPE_CONFIG(ADDR_SURF_P2); 910 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 911 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 912 PIPE_CONFIG(ADDR_SURF_P2) | 913 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 914 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 915 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 916 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 917 NUM_BANKS(ADDR_SURF_16_BANK); 918 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 919 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 920 PIPE_CONFIG(ADDR_SURF_P2) | 921 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 922 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 925 NUM_BANKS(ADDR_SURF_16_BANK); 926 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 927 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 928 PIPE_CONFIG(ADDR_SURF_P2) | 929 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 933 NUM_BANKS(ADDR_SURF_16_BANK); 934 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 935 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 936 PIPE_CONFIG(ADDR_SURF_P2); 937 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 938 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 939 PIPE_CONFIG(ADDR_SURF_P2) | 940 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 941 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 942 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 943 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 944 NUM_BANKS(ADDR_SURF_16_BANK); 945 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 946 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 947 PIPE_CONFIG(ADDR_SURF_P2) | 948 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 949 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 950 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 951 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 952 NUM_BANKS(ADDR_SURF_16_BANK); 953 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 954 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 955 PIPE_CONFIG(ADDR_SURF_P2) | 956 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 957 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 958 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 959 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 960 NUM_BANKS(ADDR_SURF_16_BANK); 961 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 962 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 963 PIPE_CONFIG(ADDR_SURF_P2) | 964 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 967 NUM_BANKS(ADDR_SURF_16_BANK) | 968 TILE_SPLIT(split_equal_to_row_size); 969 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 970 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 971 PIPE_CONFIG(ADDR_SURF_P2); 972 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 973 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 974 PIPE_CONFIG(ADDR_SURF_P2) | 975 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 976 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 977 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 978 NUM_BANKS(ADDR_SURF_16_BANK) | 979 TILE_SPLIT(split_equal_to_row_size); 980 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 981 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 982 PIPE_CONFIG(ADDR_SURF_P2) | 983 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 984 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 985 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 986 NUM_BANKS(ADDR_SURF_16_BANK) | 987 TILE_SPLIT(split_equal_to_row_size); 988 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 989 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 990 PIPE_CONFIG(ADDR_SURF_P2) | 991 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 992 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 993 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 994 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 995 NUM_BANKS(ADDR_SURF_8_BANK); 996 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 997 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 998 PIPE_CONFIG(ADDR_SURF_P2) | 999 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1000 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1003 NUM_BANKS(ADDR_SURF_8_BANK); 1004 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1005 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1006 PIPE_CONFIG(ADDR_SURF_P2) | 1007 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1008 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1009 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1010 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1011 NUM_BANKS(ADDR_SURF_8_BANK); 1012 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1013 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1014 PIPE_CONFIG(ADDR_SURF_P2) | 1015 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1016 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1017 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1018 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1019 NUM_BANKS(ADDR_SURF_8_BANK); 1020 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1021 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1022 PIPE_CONFIG(ADDR_SURF_P2) | 1023 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1024 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1025 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1026 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1027 NUM_BANKS(ADDR_SURF_4_BANK); 1028 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1029 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1030 PIPE_CONFIG(ADDR_SURF_P2) | 1031 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1032 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1033 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1034 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1035 NUM_BANKS(ADDR_SURF_4_BANK); 1036 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1037 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1038 PIPE_CONFIG(ADDR_SURF_P2) | 1039 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1040 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1041 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1042 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1043 NUM_BANKS(ADDR_SURF_4_BANK); 1044 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1045 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1046 PIPE_CONFIG(ADDR_SURF_P2) | 1047 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1048 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1049 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1050 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1051 NUM_BANKS(ADDR_SURF_4_BANK); 1052 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1053 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1054 PIPE_CONFIG(ADDR_SURF_P2) | 1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1059 NUM_BANKS(ADDR_SURF_4_BANK); 1060 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1061 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1062 PIPE_CONFIG(ADDR_SURF_P2) | 1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1064 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1065 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1066 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1067 NUM_BANKS(ADDR_SURF_4_BANK); 1068 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1069 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1070 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1071 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1072 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1073 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1074 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1075 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1076 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1077 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1078 NUM_BANKS(ADDR_SURF_16_BANK); 1079 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1080 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1081 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1082 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1083 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1084 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1085 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1086 NUM_BANKS(ADDR_SURF_16_BANK); 1087 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1088 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1089 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1091 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1092 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1093 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1094 NUM_BANKS(ADDR_SURF_16_BANK); 1095 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1096 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1098 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1101 NUM_BANKS(ADDR_SURF_4_BANK) | 1102 TILE_SPLIT(split_equal_to_row_size); 1103 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1104 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1105 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1106 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1107 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1108 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1109 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1110 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1113 NUM_BANKS(ADDR_SURF_2_BANK); 1114 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1115 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1116 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1117 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1118 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1119 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1120 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1121 NUM_BANKS(ADDR_SURF_2_BANK); 1122 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1123 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1124 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1125 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1126 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1127 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1128 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1129 NUM_BANKS(ADDR_SURF_2_BANK); 1130 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 1131 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1132 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1134 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1135 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1136 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1137 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1138 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1139 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1140 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1141 NUM_BANKS(ADDR_SURF_16_BANK); 1142 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1143 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1144 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1149 NUM_BANKS(ADDR_SURF_16_BANK); 1150 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1151 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1152 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1154 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1157 NUM_BANKS(ADDR_SURF_16_BANK); 1158 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1159 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1160 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1161 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1162 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1163 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1164 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1165 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1166 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1167 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1168 NUM_BANKS(ADDR_SURF_16_BANK); 1169 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1170 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1171 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1172 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1173 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1174 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1175 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1176 NUM_BANKS(ADDR_SURF_16_BANK); 1177 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1178 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1179 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1180 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1181 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1182 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1183 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1184 NUM_BANKS(ADDR_SURF_16_BANK); 1185 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1186 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1187 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1188 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1191 NUM_BANKS(ADDR_SURF_16_BANK) | 1192 TILE_SPLIT(split_equal_to_row_size); 1193 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1194 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1195 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1196 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1197 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1198 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1199 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1202 NUM_BANKS(ADDR_SURF_16_BANK) | 1203 TILE_SPLIT(split_equal_to_row_size); 1204 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1205 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1206 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1207 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1210 NUM_BANKS(ADDR_SURF_16_BANK) | 1211 TILE_SPLIT(split_equal_to_row_size); 1212 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1213 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1214 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1215 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1216 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1217 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1218 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1219 NUM_BANKS(ADDR_SURF_4_BANK); 1220 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1221 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1222 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1223 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1224 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1225 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1226 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1227 NUM_BANKS(ADDR_SURF_4_BANK); 1228 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1229 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1230 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1231 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1232 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1233 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1234 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1235 NUM_BANKS(ADDR_SURF_2_BANK); 1236 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1237 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1238 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1239 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1240 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1241 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1242 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1243 NUM_BANKS(ADDR_SURF_2_BANK); 1244 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1245 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1246 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1247 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1248 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1249 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1250 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1251 NUM_BANKS(ADDR_SURF_2_BANK); 1252 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1253 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1254 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1255 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1256 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1257 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1258 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1259 NUM_BANKS(ADDR_SURF_2_BANK); 1260 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1261 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1262 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1263 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1264 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1265 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1266 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1267 NUM_BANKS(ADDR_SURF_2_BANK); 1268 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1269 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1270 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1271 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1272 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1273 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1274 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1275 NUM_BANKS(ADDR_SURF_2_BANK); 1276 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1277 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1278 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1279 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1280 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1281 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1282 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1283 NUM_BANKS(ADDR_SURF_2_BANK); 1284 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1285 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1286 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1287 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1288 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1289 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1290 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1291 NUM_BANKS(ADDR_SURF_2_BANK); 1292 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1293 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1294 } else { 1295 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1296 } 1297 } 1298 1299 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1300 u32 sh_num, u32 instance) 1301 { 1302 u32 data; 1303 1304 if (instance == 0xffffffff) 1305 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1306 else 1307 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1308 1309 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1310 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1311 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1312 else if (se_num == 0xffffffff) 1313 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1314 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1315 else if (sh_num == 0xffffffff) 1316 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1317 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1318 else 1319 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1320 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1321 WREG32(mmGRBM_GFX_INDEX, data); 1322 } 1323 1324 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1325 { 1326 u32 data, mask; 1327 1328 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1329 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1330 1331 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1332 1333 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1334 adev->gfx.config.max_sh_per_se); 1335 1336 return ~data & mask; 1337 } 1338 1339 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1340 { 1341 switch (adev->asic_type) { 1342 case CHIP_TAHITI: 1343 case CHIP_PITCAIRN: 1344 *rconf |= 1345 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1346 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1347 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1348 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1349 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1350 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1351 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1352 break; 1353 case CHIP_VERDE: 1354 *rconf |= 1355 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1356 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1357 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1358 break; 1359 case CHIP_OLAND: 1360 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1361 break; 1362 case CHIP_HAINAN: 1363 *rconf |= 0x0; 1364 break; 1365 default: 1366 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1367 break; 1368 } 1369 } 1370 1371 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1372 u32 raster_config, unsigned rb_mask, 1373 unsigned num_rb) 1374 { 1375 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1376 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1377 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1378 unsigned rb_per_se = num_rb / num_se; 1379 unsigned se_mask[4]; 1380 unsigned se; 1381 1382 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1383 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1384 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1385 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1386 1387 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1388 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1389 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1390 1391 for (se = 0; se < num_se; se++) { 1392 unsigned raster_config_se = raster_config; 1393 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1394 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1395 int idx = (se / 2) * 2; 1396 1397 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1398 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1399 1400 if (!se_mask[idx]) 1401 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1402 else 1403 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1404 } 1405 1406 pkr0_mask &= rb_mask; 1407 pkr1_mask &= rb_mask; 1408 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1409 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1410 1411 if (!pkr0_mask) 1412 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1413 else 1414 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1415 } 1416 1417 if (rb_per_se >= 2) { 1418 unsigned rb0_mask = 1 << (se * rb_per_se); 1419 unsigned rb1_mask = rb0_mask << 1; 1420 1421 rb0_mask &= rb_mask; 1422 rb1_mask &= rb_mask; 1423 if (!rb0_mask || !rb1_mask) { 1424 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1425 1426 if (!rb0_mask) 1427 raster_config_se |= 1428 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1429 else 1430 raster_config_se |= 1431 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1432 } 1433 1434 if (rb_per_se > 2) { 1435 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1436 rb1_mask = rb0_mask << 1; 1437 rb0_mask &= rb_mask; 1438 rb1_mask &= rb_mask; 1439 if (!rb0_mask || !rb1_mask) { 1440 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1441 1442 if (!rb0_mask) 1443 raster_config_se |= 1444 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1445 else 1446 raster_config_se |= 1447 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1448 } 1449 } 1450 } 1451 1452 /* GRBM_GFX_INDEX has a different offset on SI */ 1453 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1454 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1455 } 1456 1457 /* GRBM_GFX_INDEX has a different offset on SI */ 1458 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1459 } 1460 1461 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1462 { 1463 int i, j; 1464 u32 data; 1465 u32 raster_config = 0; 1466 u32 active_rbs = 0; 1467 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1468 adev->gfx.config.max_sh_per_se; 1469 unsigned num_rb_pipes; 1470 1471 mutex_lock(&adev->grbm_idx_mutex); 1472 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1473 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1474 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1475 data = gfx_v6_0_get_rb_active_bitmap(adev); 1476 active_rbs |= data << 1477 ((i * adev->gfx.config.max_sh_per_se + j) * 1478 rb_bitmap_width_per_sh); 1479 } 1480 } 1481 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1482 1483 adev->gfx.config.backend_enable_mask = active_rbs; 1484 adev->gfx.config.num_rbs = hweight32(active_rbs); 1485 1486 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1487 adev->gfx.config.max_shader_engines, 16); 1488 1489 gfx_v6_0_raster_config(adev, &raster_config); 1490 1491 if (!adev->gfx.config.backend_enable_mask || 1492 adev->gfx.config.num_rbs >= num_rb_pipes) 1493 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1494 else 1495 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1496 adev->gfx.config.backend_enable_mask, 1497 num_rb_pipes); 1498 1499 /* cache the values for userspace */ 1500 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1501 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1502 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1503 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1504 RREG32(mmCC_RB_BACKEND_DISABLE); 1505 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1506 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1507 adev->gfx.config.rb_config[i][j].raster_config = 1508 RREG32(mmPA_SC_RASTER_CONFIG); 1509 } 1510 } 1511 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1512 mutex_unlock(&adev->grbm_idx_mutex); 1513 } 1514 1515 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1516 u32 bitmap) 1517 { 1518 u32 data; 1519 1520 if (!bitmap) 1521 return; 1522 1523 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1524 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1525 1526 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1527 } 1528 1529 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1530 { 1531 u32 data, mask; 1532 1533 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1534 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1535 1536 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1537 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1538 } 1539 1540 1541 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1542 { 1543 int i, j, k; 1544 u32 data, mask; 1545 u32 active_cu = 0; 1546 1547 mutex_lock(&adev->grbm_idx_mutex); 1548 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1549 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1550 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1551 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1552 active_cu = gfx_v6_0_get_cu_enabled(adev); 1553 1554 mask = 1; 1555 for (k = 0; k < 16; k++) { 1556 mask <<= k; 1557 if (active_cu & mask) { 1558 data &= ~mask; 1559 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1560 break; 1561 } 1562 } 1563 } 1564 } 1565 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1566 mutex_unlock(&adev->grbm_idx_mutex); 1567 } 1568 1569 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1570 { 1571 adev->gfx.config.double_offchip_lds_buf = 0; 1572 } 1573 1574 static void gfx_v6_0_constants_init(struct amdgpu_device *adev) 1575 { 1576 u32 gb_addr_config = 0; 1577 u32 mc_shared_chmap, mc_arb_ramcfg; 1578 u32 sx_debug_1; 1579 u32 hdp_host_path_cntl; 1580 u32 tmp; 1581 1582 switch (adev->asic_type) { 1583 case CHIP_TAHITI: 1584 adev->gfx.config.max_shader_engines = 2; 1585 adev->gfx.config.max_tile_pipes = 12; 1586 adev->gfx.config.max_cu_per_sh = 8; 1587 adev->gfx.config.max_sh_per_se = 2; 1588 adev->gfx.config.max_backends_per_se = 4; 1589 adev->gfx.config.max_texture_channel_caches = 12; 1590 adev->gfx.config.max_gprs = 256; 1591 adev->gfx.config.max_gs_threads = 32; 1592 adev->gfx.config.max_hw_contexts = 8; 1593 1594 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1595 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1596 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1597 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1598 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1599 break; 1600 case CHIP_PITCAIRN: 1601 adev->gfx.config.max_shader_engines = 2; 1602 adev->gfx.config.max_tile_pipes = 8; 1603 adev->gfx.config.max_cu_per_sh = 5; 1604 adev->gfx.config.max_sh_per_se = 2; 1605 adev->gfx.config.max_backends_per_se = 4; 1606 adev->gfx.config.max_texture_channel_caches = 8; 1607 adev->gfx.config.max_gprs = 256; 1608 adev->gfx.config.max_gs_threads = 32; 1609 adev->gfx.config.max_hw_contexts = 8; 1610 1611 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1612 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1613 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1614 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1615 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1616 break; 1617 case CHIP_VERDE: 1618 adev->gfx.config.max_shader_engines = 1; 1619 adev->gfx.config.max_tile_pipes = 4; 1620 adev->gfx.config.max_cu_per_sh = 5; 1621 adev->gfx.config.max_sh_per_se = 2; 1622 adev->gfx.config.max_backends_per_se = 4; 1623 adev->gfx.config.max_texture_channel_caches = 4; 1624 adev->gfx.config.max_gprs = 256; 1625 adev->gfx.config.max_gs_threads = 32; 1626 adev->gfx.config.max_hw_contexts = 8; 1627 1628 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1629 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1630 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1631 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1632 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1633 break; 1634 case CHIP_OLAND: 1635 adev->gfx.config.max_shader_engines = 1; 1636 adev->gfx.config.max_tile_pipes = 4; 1637 adev->gfx.config.max_cu_per_sh = 6; 1638 adev->gfx.config.max_sh_per_se = 1; 1639 adev->gfx.config.max_backends_per_se = 2; 1640 adev->gfx.config.max_texture_channel_caches = 4; 1641 adev->gfx.config.max_gprs = 256; 1642 adev->gfx.config.max_gs_threads = 16; 1643 adev->gfx.config.max_hw_contexts = 8; 1644 1645 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1646 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1647 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1648 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1649 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1650 break; 1651 case CHIP_HAINAN: 1652 adev->gfx.config.max_shader_engines = 1; 1653 adev->gfx.config.max_tile_pipes = 4; 1654 adev->gfx.config.max_cu_per_sh = 5; 1655 adev->gfx.config.max_sh_per_se = 1; 1656 adev->gfx.config.max_backends_per_se = 1; 1657 adev->gfx.config.max_texture_channel_caches = 2; 1658 adev->gfx.config.max_gprs = 256; 1659 adev->gfx.config.max_gs_threads = 16; 1660 adev->gfx.config.max_hw_contexts = 8; 1661 1662 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1663 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1664 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1665 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1666 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1667 break; 1668 default: 1669 BUG(); 1670 break; 1671 } 1672 1673 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1674 WREG32(mmSRBM_INT_CNTL, 1); 1675 WREG32(mmSRBM_INT_ACK, 1); 1676 1677 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1678 1679 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 1680 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1681 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1682 1683 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1684 adev->gfx.config.mem_max_burst_length_bytes = 256; 1685 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1686 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1687 if (adev->gfx.config.mem_row_size_in_kb > 4) 1688 adev->gfx.config.mem_row_size_in_kb = 4; 1689 adev->gfx.config.shader_engine_tile_size = 32; 1690 adev->gfx.config.num_gpus = 1; 1691 adev->gfx.config.multi_gpu_tile_size = 64; 1692 1693 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1694 switch (adev->gfx.config.mem_row_size_in_kb) { 1695 case 1: 1696 default: 1697 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1698 break; 1699 case 2: 1700 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1701 break; 1702 case 4: 1703 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1704 break; 1705 } 1706 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1707 if (adev->gfx.config.max_shader_engines == 2) 1708 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1709 adev->gfx.config.gb_addr_config = gb_addr_config; 1710 1711 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1712 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1713 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1714 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1715 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1716 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1717 1718 #if 0 1719 if (adev->has_uvd) { 1720 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1721 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1722 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1723 } 1724 #endif 1725 gfx_v6_0_tiling_mode_table_init(adev); 1726 1727 gfx_v6_0_setup_rb(adev); 1728 1729 gfx_v6_0_setup_spi(adev); 1730 1731 gfx_v6_0_get_cu_info(adev); 1732 gfx_v6_0_config_init(adev); 1733 1734 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1735 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1736 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1737 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1738 1739 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1740 WREG32(mmSX_DEBUG_1, sx_debug_1); 1741 1742 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1743 1744 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1745 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1746 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1747 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1748 1749 WREG32(mmVGT_NUM_INSTANCES, 1); 1750 WREG32(mmCP_PERFMON_CNTL, 0); 1751 WREG32(mmSQ_CONFIG, 0); 1752 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1753 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1754 1755 WREG32(mmVGT_CACHE_INVALIDATION, 1756 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1757 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1758 1759 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1760 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1761 1762 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1763 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1764 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1765 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1766 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1767 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1768 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1769 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1770 1771 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1772 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1773 1774 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1775 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1776 1777 udelay(50); 1778 } 1779 1780 1781 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev) 1782 { 1783 adev->gfx.scratch.num_reg = 8; 1784 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 1785 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 1786 } 1787 1788 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1789 { 1790 struct amdgpu_device *adev = ring->adev; 1791 uint32_t scratch; 1792 uint32_t tmp = 0; 1793 unsigned i; 1794 int r; 1795 1796 r = amdgpu_gfx_scratch_get(adev, &scratch); 1797 if (r) 1798 return r; 1799 1800 WREG32(scratch, 0xCAFEDEAD); 1801 1802 r = amdgpu_ring_alloc(ring, 3); 1803 if (r) 1804 goto error_free_scratch; 1805 1806 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1807 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); 1808 amdgpu_ring_write(ring, 0xDEADBEEF); 1809 amdgpu_ring_commit(ring); 1810 1811 for (i = 0; i < adev->usec_timeout; i++) { 1812 tmp = RREG32(scratch); 1813 if (tmp == 0xDEADBEEF) 1814 break; 1815 udelay(1); 1816 } 1817 1818 if (i >= adev->usec_timeout) 1819 r = -ETIMEDOUT; 1820 1821 error_free_scratch: 1822 amdgpu_gfx_scratch_free(adev, scratch); 1823 return r; 1824 } 1825 1826 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1827 { 1828 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1829 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1830 EVENT_INDEX(0)); 1831 } 1832 1833 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1834 u64 seq, unsigned flags) 1835 { 1836 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1837 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1838 /* flush read cache over gart */ 1839 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1840 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1841 amdgpu_ring_write(ring, 0); 1842 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1843 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1844 PACKET3_TC_ACTION_ENA | 1845 PACKET3_SH_KCACHE_ACTION_ENA | 1846 PACKET3_SH_ICACHE_ACTION_ENA); 1847 amdgpu_ring_write(ring, 0xFFFFFFFF); 1848 amdgpu_ring_write(ring, 0); 1849 amdgpu_ring_write(ring, 10); /* poll interval */ 1850 /* EVENT_WRITE_EOP - flush caches, send int */ 1851 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1852 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1853 amdgpu_ring_write(ring, addr & 0xfffffffc); 1854 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1855 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1856 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1857 amdgpu_ring_write(ring, lower_32_bits(seq)); 1858 amdgpu_ring_write(ring, upper_32_bits(seq)); 1859 } 1860 1861 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1862 struct amdgpu_job *job, 1863 struct amdgpu_ib *ib, 1864 uint32_t flags) 1865 { 1866 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1867 u32 header, control = 0; 1868 1869 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1870 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 1871 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1872 amdgpu_ring_write(ring, 0); 1873 } 1874 1875 if (ib->flags & AMDGPU_IB_FLAG_CE) 1876 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1877 else 1878 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1879 1880 control |= ib->length_dw | (vmid << 24); 1881 1882 amdgpu_ring_write(ring, header); 1883 amdgpu_ring_write(ring, 1884 #ifdef __BIG_ENDIAN 1885 (2 << 0) | 1886 #endif 1887 (ib->gpu_addr & 0xFFFFFFFC)); 1888 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1889 amdgpu_ring_write(ring, control); 1890 } 1891 1892 /** 1893 * gfx_v6_0_ring_test_ib - basic ring IB test 1894 * 1895 * @ring: amdgpu_ring structure holding ring information 1896 * 1897 * Allocate an IB and execute it on the gfx ring (SI). 1898 * Provides a basic gfx ring test to verify that IBs are working. 1899 * Returns 0 on success, error on failure. 1900 */ 1901 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1902 { 1903 struct amdgpu_device *adev = ring->adev; 1904 struct amdgpu_ib ib; 1905 struct dma_fence *f = NULL; 1906 uint32_t scratch; 1907 uint32_t tmp = 0; 1908 long r; 1909 1910 r = amdgpu_gfx_scratch_get(adev, &scratch); 1911 if (r) 1912 return r; 1913 1914 WREG32(scratch, 0xCAFEDEAD); 1915 memset(&ib, 0, sizeof(ib)); 1916 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1917 if (r) 1918 goto err1; 1919 1920 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1921 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START)); 1922 ib.ptr[2] = 0xDEADBEEF; 1923 ib.length_dw = 3; 1924 1925 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1926 if (r) 1927 goto err2; 1928 1929 r = dma_fence_wait_timeout(f, false, timeout); 1930 if (r == 0) { 1931 r = -ETIMEDOUT; 1932 goto err2; 1933 } else if (r < 0) { 1934 goto err2; 1935 } 1936 tmp = RREG32(scratch); 1937 if (tmp == 0xDEADBEEF) 1938 r = 0; 1939 else 1940 r = -EINVAL; 1941 1942 err2: 1943 amdgpu_ib_free(adev, &ib, NULL); 1944 dma_fence_put(f); 1945 err1: 1946 amdgpu_gfx_scratch_free(adev, scratch); 1947 return r; 1948 } 1949 1950 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1951 { 1952 int i; 1953 if (enable) { 1954 WREG32(mmCP_ME_CNTL, 0); 1955 } else { 1956 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 1957 CP_ME_CNTL__PFP_HALT_MASK | 1958 CP_ME_CNTL__CE_HALT_MASK)); 1959 WREG32(mmSCRATCH_UMSK, 0); 1960 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1961 adev->gfx.gfx_ring[i].sched.ready = false; 1962 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1963 adev->gfx.compute_ring[i].sched.ready = false; 1964 } 1965 udelay(50); 1966 } 1967 1968 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 1969 { 1970 unsigned i; 1971 const struct gfx_firmware_header_v1_0 *pfp_hdr; 1972 const struct gfx_firmware_header_v1_0 *ce_hdr; 1973 const struct gfx_firmware_header_v1_0 *me_hdr; 1974 const __le32 *fw_data; 1975 u32 fw_size; 1976 1977 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 1978 return -EINVAL; 1979 1980 gfx_v6_0_cp_gfx_enable(adev, false); 1981 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1982 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1983 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1984 1985 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 1986 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 1987 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 1988 1989 /* PFP */ 1990 fw_data = (const __le32 *) 1991 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1992 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1993 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1994 for (i = 0; i < fw_size; i++) 1995 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 1996 WREG32(mmCP_PFP_UCODE_ADDR, 0); 1997 1998 /* CE */ 1999 fw_data = (const __le32 *) 2000 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2001 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2002 WREG32(mmCP_CE_UCODE_ADDR, 0); 2003 for (i = 0; i < fw_size; i++) 2004 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2005 WREG32(mmCP_CE_UCODE_ADDR, 0); 2006 2007 /* ME */ 2008 fw_data = (const __be32 *) 2009 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2010 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2011 WREG32(mmCP_ME_RAM_WADDR, 0); 2012 for (i = 0; i < fw_size; i++) 2013 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2014 WREG32(mmCP_ME_RAM_WADDR, 0); 2015 2016 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2017 WREG32(mmCP_CE_UCODE_ADDR, 0); 2018 WREG32(mmCP_ME_RAM_WADDR, 0); 2019 WREG32(mmCP_ME_RAM_RADDR, 0); 2020 return 0; 2021 } 2022 2023 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 2024 { 2025 const struct cs_section_def *sect = NULL; 2026 const struct cs_extent_def *ext = NULL; 2027 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2028 int r, i; 2029 2030 r = amdgpu_ring_alloc(ring, 7 + 4); 2031 if (r) { 2032 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2033 return r; 2034 } 2035 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2036 amdgpu_ring_write(ring, 0x1); 2037 amdgpu_ring_write(ring, 0x0); 2038 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 2039 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2040 amdgpu_ring_write(ring, 0); 2041 amdgpu_ring_write(ring, 0); 2042 2043 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2044 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2045 amdgpu_ring_write(ring, 0xc000); 2046 amdgpu_ring_write(ring, 0xe000); 2047 amdgpu_ring_commit(ring); 2048 2049 gfx_v6_0_cp_gfx_enable(adev, true); 2050 2051 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2052 if (r) { 2053 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2054 return r; 2055 } 2056 2057 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2058 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2059 2060 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2061 for (ext = sect->section; ext->extent != NULL; ++ext) { 2062 if (sect->id == SECT_CONTEXT) { 2063 amdgpu_ring_write(ring, 2064 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2065 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2066 for (i = 0; i < ext->reg_count; i++) 2067 amdgpu_ring_write(ring, ext->extent[i]); 2068 } 2069 } 2070 } 2071 2072 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2073 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2074 2075 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2076 amdgpu_ring_write(ring, 0); 2077 2078 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2079 amdgpu_ring_write(ring, 0x00000316); 2080 amdgpu_ring_write(ring, 0x0000000e); 2081 amdgpu_ring_write(ring, 0x00000010); 2082 2083 amdgpu_ring_commit(ring); 2084 2085 return 0; 2086 } 2087 2088 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2089 { 2090 struct amdgpu_ring *ring; 2091 u32 tmp; 2092 u32 rb_bufsz; 2093 int r; 2094 u64 rptr_addr; 2095 2096 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2097 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2098 2099 /* Set the write pointer delay */ 2100 WREG32(mmCP_RB_WPTR_DELAY, 0); 2101 2102 WREG32(mmCP_DEBUG, 0); 2103 WREG32(mmSCRATCH_ADDR, 0); 2104 2105 /* ring 0 - compute and gfx */ 2106 /* Set ring buffer size */ 2107 ring = &adev->gfx.gfx_ring[0]; 2108 rb_bufsz = order_base_2(ring->ring_size / 8); 2109 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2110 2111 #ifdef __BIG_ENDIAN 2112 tmp |= BUF_SWAP_32BIT; 2113 #endif 2114 WREG32(mmCP_RB0_CNTL, tmp); 2115 2116 /* Initialize the ring buffer's read and write pointers */ 2117 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2118 ring->wptr = 0; 2119 WREG32(mmCP_RB0_WPTR, ring->wptr); 2120 2121 /* set the wb address whether it's enabled or not */ 2122 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2123 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2124 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2125 2126 WREG32(mmSCRATCH_UMSK, 0); 2127 2128 mdelay(1); 2129 WREG32(mmCP_RB0_CNTL, tmp); 2130 2131 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2132 2133 /* start the rings */ 2134 gfx_v6_0_cp_gfx_start(adev); 2135 r = amdgpu_ring_test_helper(ring); 2136 if (r) 2137 return r; 2138 2139 return 0; 2140 } 2141 2142 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2143 { 2144 return ring->adev->wb.wb[ring->rptr_offs]; 2145 } 2146 2147 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2148 { 2149 struct amdgpu_device *adev = ring->adev; 2150 2151 if (ring == &adev->gfx.gfx_ring[0]) 2152 return RREG32(mmCP_RB0_WPTR); 2153 else if (ring == &adev->gfx.compute_ring[0]) 2154 return RREG32(mmCP_RB1_WPTR); 2155 else if (ring == &adev->gfx.compute_ring[1]) 2156 return RREG32(mmCP_RB2_WPTR); 2157 else 2158 BUG(); 2159 } 2160 2161 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2162 { 2163 struct amdgpu_device *adev = ring->adev; 2164 2165 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2166 (void)RREG32(mmCP_RB0_WPTR); 2167 } 2168 2169 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2170 { 2171 struct amdgpu_device *adev = ring->adev; 2172 2173 if (ring == &adev->gfx.compute_ring[0]) { 2174 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2175 (void)RREG32(mmCP_RB1_WPTR); 2176 } else if (ring == &adev->gfx.compute_ring[1]) { 2177 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2178 (void)RREG32(mmCP_RB2_WPTR); 2179 } else { 2180 BUG(); 2181 } 2182 2183 } 2184 2185 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 2186 { 2187 struct amdgpu_ring *ring; 2188 u32 tmp; 2189 u32 rb_bufsz; 2190 int i, r; 2191 u64 rptr_addr; 2192 2193 /* ring1 - compute only */ 2194 /* Set ring buffer size */ 2195 2196 ring = &adev->gfx.compute_ring[0]; 2197 rb_bufsz = order_base_2(ring->ring_size / 8); 2198 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2199 #ifdef __BIG_ENDIAN 2200 tmp |= BUF_SWAP_32BIT; 2201 #endif 2202 WREG32(mmCP_RB1_CNTL, tmp); 2203 2204 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2205 ring->wptr = 0; 2206 WREG32(mmCP_RB1_WPTR, ring->wptr); 2207 2208 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2209 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2210 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2211 2212 mdelay(1); 2213 WREG32(mmCP_RB1_CNTL, tmp); 2214 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2215 2216 ring = &adev->gfx.compute_ring[1]; 2217 rb_bufsz = order_base_2(ring->ring_size / 8); 2218 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2219 #ifdef __BIG_ENDIAN 2220 tmp |= BUF_SWAP_32BIT; 2221 #endif 2222 WREG32(mmCP_RB2_CNTL, tmp); 2223 2224 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2225 ring->wptr = 0; 2226 WREG32(mmCP_RB2_WPTR, ring->wptr); 2227 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2228 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2229 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2230 2231 mdelay(1); 2232 WREG32(mmCP_RB2_CNTL, tmp); 2233 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2234 2235 2236 for (i = 0; i < 2; i++) { 2237 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]); 2238 if (r) 2239 return r; 2240 } 2241 2242 return 0; 2243 } 2244 2245 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2246 { 2247 gfx_v6_0_cp_gfx_enable(adev, enable); 2248 } 2249 2250 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2251 { 2252 return gfx_v6_0_cp_gfx_load_microcode(adev); 2253 } 2254 2255 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2256 bool enable) 2257 { 2258 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2259 u32 mask; 2260 int i; 2261 2262 if (enable) 2263 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2264 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2265 else 2266 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2267 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2268 WREG32(mmCP_INT_CNTL_RING0, tmp); 2269 2270 if (!enable) { 2271 /* read a gfx register */ 2272 tmp = RREG32(mmDB_DEPTH_INFO); 2273 2274 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2275 for (i = 0; i < adev->usec_timeout; i++) { 2276 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2277 break; 2278 udelay(1); 2279 } 2280 } 2281 } 2282 2283 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2284 { 2285 int r; 2286 2287 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2288 2289 r = gfx_v6_0_cp_load_microcode(adev); 2290 if (r) 2291 return r; 2292 2293 r = gfx_v6_0_cp_gfx_resume(adev); 2294 if (r) 2295 return r; 2296 r = gfx_v6_0_cp_compute_resume(adev); 2297 if (r) 2298 return r; 2299 2300 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2301 2302 return 0; 2303 } 2304 2305 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2306 { 2307 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2308 uint32_t seq = ring->fence_drv.sync_seq; 2309 uint64_t addr = ring->fence_drv.gpu_addr; 2310 2311 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2312 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2313 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2314 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2315 amdgpu_ring_write(ring, addr & 0xfffffffc); 2316 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2317 amdgpu_ring_write(ring, seq); 2318 amdgpu_ring_write(ring, 0xffffffff); 2319 amdgpu_ring_write(ring, 4); /* poll interval */ 2320 2321 if (usepfp) { 2322 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2323 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2324 amdgpu_ring_write(ring, 0); 2325 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2326 amdgpu_ring_write(ring, 0); 2327 } 2328 } 2329 2330 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2331 unsigned vmid, uint64_t pd_addr) 2332 { 2333 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2334 2335 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2336 2337 /* wait for the invalidate to complete */ 2338 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2339 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2340 WAIT_REG_MEM_ENGINE(0))); /* me */ 2341 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2342 amdgpu_ring_write(ring, 0); 2343 amdgpu_ring_write(ring, 0); /* ref */ 2344 amdgpu_ring_write(ring, 0); /* mask */ 2345 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2346 2347 if (usepfp) { 2348 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2349 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2350 amdgpu_ring_write(ring, 0x0); 2351 2352 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2353 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2354 amdgpu_ring_write(ring, 0); 2355 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2356 amdgpu_ring_write(ring, 0); 2357 } 2358 } 2359 2360 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 2361 uint32_t reg, uint32_t val) 2362 { 2363 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2364 2365 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2366 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 2367 WRITE_DATA_DST_SEL(0))); 2368 amdgpu_ring_write(ring, reg); 2369 amdgpu_ring_write(ring, 0); 2370 amdgpu_ring_write(ring, val); 2371 } 2372 2373 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2374 { 2375 const u32 *src_ptr; 2376 volatile u32 *dst_ptr; 2377 u32 dws; 2378 u64 reg_list_mc_addr; 2379 const struct cs_section_def *cs_data; 2380 int r; 2381 2382 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2383 adev->gfx.rlc.reg_list_size = 2384 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2385 2386 adev->gfx.rlc.cs_data = si_cs_data; 2387 src_ptr = adev->gfx.rlc.reg_list; 2388 dws = adev->gfx.rlc.reg_list_size; 2389 cs_data = adev->gfx.rlc.cs_data; 2390 2391 if (src_ptr) { 2392 /* init save restore block */ 2393 r = amdgpu_gfx_rlc_init_sr(adev, dws); 2394 if (r) 2395 return r; 2396 } 2397 2398 if (cs_data) { 2399 /* clear state block */ 2400 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2401 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2402 2403 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2404 AMDGPU_GEM_DOMAIN_VRAM, 2405 &adev->gfx.rlc.clear_state_obj, 2406 &adev->gfx.rlc.clear_state_gpu_addr, 2407 (void **)&adev->gfx.rlc.cs_ptr); 2408 if (r) { 2409 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2410 amdgpu_gfx_rlc_fini(adev); 2411 return r; 2412 } 2413 2414 /* set up the cs buffer */ 2415 dst_ptr = adev->gfx.rlc.cs_ptr; 2416 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2417 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2418 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2419 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2420 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2421 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2422 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2423 } 2424 2425 return 0; 2426 } 2427 2428 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2429 { 2430 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2431 2432 if (!enable) { 2433 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2434 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2435 } 2436 } 2437 2438 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2439 { 2440 int i; 2441 2442 for (i = 0; i < adev->usec_timeout; i++) { 2443 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2444 break; 2445 udelay(1); 2446 } 2447 2448 for (i = 0; i < adev->usec_timeout; i++) { 2449 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2450 break; 2451 udelay(1); 2452 } 2453 } 2454 2455 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2456 { 2457 u32 tmp; 2458 2459 tmp = RREG32(mmRLC_CNTL); 2460 if (tmp != rlc) 2461 WREG32(mmRLC_CNTL, rlc); 2462 } 2463 2464 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2465 { 2466 u32 data, orig; 2467 2468 orig = data = RREG32(mmRLC_CNTL); 2469 2470 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2471 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2472 WREG32(mmRLC_CNTL, data); 2473 2474 gfx_v6_0_wait_for_rlc_serdes(adev); 2475 } 2476 2477 return orig; 2478 } 2479 2480 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2481 { 2482 WREG32(mmRLC_CNTL, 0); 2483 2484 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2485 gfx_v6_0_wait_for_rlc_serdes(adev); 2486 } 2487 2488 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2489 { 2490 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2491 2492 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2493 2494 udelay(50); 2495 } 2496 2497 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2498 { 2499 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2500 udelay(50); 2501 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2502 udelay(50); 2503 } 2504 2505 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2506 { 2507 u32 tmp; 2508 2509 /* Enable LBPW only for DDR3 */ 2510 tmp = RREG32(mmMC_SEQ_MISC0); 2511 if ((tmp & 0xF0000000) == 0xB0000000) 2512 return true; 2513 return false; 2514 } 2515 2516 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2517 { 2518 } 2519 2520 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2521 { 2522 u32 i; 2523 const struct rlc_firmware_header_v1_0 *hdr; 2524 const __le32 *fw_data; 2525 u32 fw_size; 2526 2527 2528 if (!adev->gfx.rlc_fw) 2529 return -EINVAL; 2530 2531 adev->gfx.rlc.funcs->stop(adev); 2532 adev->gfx.rlc.funcs->reset(adev); 2533 gfx_v6_0_init_pg(adev); 2534 gfx_v6_0_init_cg(adev); 2535 2536 WREG32(mmRLC_RL_BASE, 0); 2537 WREG32(mmRLC_RL_SIZE, 0); 2538 WREG32(mmRLC_LB_CNTL, 0); 2539 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2540 WREG32(mmRLC_LB_CNTR_INIT, 0); 2541 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2542 2543 WREG32(mmRLC_MC_CNTL, 0); 2544 WREG32(mmRLC_UCODE_CNTL, 0); 2545 2546 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2547 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2548 fw_data = (const __le32 *) 2549 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2550 2551 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2552 2553 for (i = 0; i < fw_size; i++) { 2554 WREG32(mmRLC_UCODE_ADDR, i); 2555 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2556 } 2557 WREG32(mmRLC_UCODE_ADDR, 0); 2558 2559 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2560 adev->gfx.rlc.funcs->start(adev); 2561 2562 return 0; 2563 } 2564 2565 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2566 { 2567 u32 data, orig, tmp; 2568 2569 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2570 2571 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2572 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2573 2574 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2575 2576 tmp = gfx_v6_0_halt_rlc(adev); 2577 2578 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2579 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2580 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2581 2582 gfx_v6_0_wait_for_rlc_serdes(adev); 2583 gfx_v6_0_update_rlc(adev, tmp); 2584 2585 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2586 2587 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2588 } else { 2589 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2590 2591 RREG32(mmCB_CGTT_SCLK_CTRL); 2592 RREG32(mmCB_CGTT_SCLK_CTRL); 2593 RREG32(mmCB_CGTT_SCLK_CTRL); 2594 RREG32(mmCB_CGTT_SCLK_CTRL); 2595 2596 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2597 } 2598 2599 if (orig != data) 2600 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2601 2602 } 2603 2604 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2605 { 2606 2607 u32 data, orig, tmp = 0; 2608 2609 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2610 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2611 data = 0x96940200; 2612 if (orig != data) 2613 WREG32(mmCGTS_SM_CTRL_REG, data); 2614 2615 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2616 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2617 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2618 if (orig != data) 2619 WREG32(mmCP_MEM_SLP_CNTL, data); 2620 } 2621 2622 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2623 data &= 0xffffffc0; 2624 if (orig != data) 2625 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2626 2627 tmp = gfx_v6_0_halt_rlc(adev); 2628 2629 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2630 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2631 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2632 2633 gfx_v6_0_update_rlc(adev, tmp); 2634 } else { 2635 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2636 data |= 0x00000003; 2637 if (orig != data) 2638 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2639 2640 data = RREG32(mmCP_MEM_SLP_CNTL); 2641 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2642 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2643 WREG32(mmCP_MEM_SLP_CNTL, data); 2644 } 2645 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2646 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2647 if (orig != data) 2648 WREG32(mmCGTS_SM_CTRL_REG, data); 2649 2650 tmp = gfx_v6_0_halt_rlc(adev); 2651 2652 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2653 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2654 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2655 2656 gfx_v6_0_update_rlc(adev, tmp); 2657 } 2658 } 2659 /* 2660 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2661 bool enable) 2662 { 2663 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2664 if (enable) { 2665 gfx_v6_0_enable_mgcg(adev, true); 2666 gfx_v6_0_enable_cgcg(adev, true); 2667 } else { 2668 gfx_v6_0_enable_cgcg(adev, false); 2669 gfx_v6_0_enable_mgcg(adev, false); 2670 } 2671 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2672 } 2673 */ 2674 2675 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2676 bool enable) 2677 { 2678 } 2679 2680 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2681 bool enable) 2682 { 2683 } 2684 2685 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2686 { 2687 u32 data, orig; 2688 2689 orig = data = RREG32(mmRLC_PG_CNTL); 2690 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2691 data &= ~0x8000; 2692 else 2693 data |= 0x8000; 2694 if (orig != data) 2695 WREG32(mmRLC_PG_CNTL, data); 2696 } 2697 2698 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2699 { 2700 } 2701 /* 2702 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2703 { 2704 const __le32 *fw_data; 2705 volatile u32 *dst_ptr; 2706 int me, i, max_me = 4; 2707 u32 bo_offset = 0; 2708 u32 table_offset, table_size; 2709 2710 if (adev->asic_type == CHIP_KAVERI) 2711 max_me = 5; 2712 2713 if (adev->gfx.rlc.cp_table_ptr == NULL) 2714 return; 2715 2716 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2717 for (me = 0; me < max_me; me++) { 2718 if (me == 0) { 2719 const struct gfx_firmware_header_v1_0 *hdr = 2720 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2721 fw_data = (const __le32 *) 2722 (adev->gfx.ce_fw->data + 2723 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2724 table_offset = le32_to_cpu(hdr->jt_offset); 2725 table_size = le32_to_cpu(hdr->jt_size); 2726 } else if (me == 1) { 2727 const struct gfx_firmware_header_v1_0 *hdr = 2728 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2729 fw_data = (const __le32 *) 2730 (adev->gfx.pfp_fw->data + 2731 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2732 table_offset = le32_to_cpu(hdr->jt_offset); 2733 table_size = le32_to_cpu(hdr->jt_size); 2734 } else if (me == 2) { 2735 const struct gfx_firmware_header_v1_0 *hdr = 2736 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2737 fw_data = (const __le32 *) 2738 (adev->gfx.me_fw->data + 2739 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2740 table_offset = le32_to_cpu(hdr->jt_offset); 2741 table_size = le32_to_cpu(hdr->jt_size); 2742 } else if (me == 3) { 2743 const struct gfx_firmware_header_v1_0 *hdr = 2744 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2745 fw_data = (const __le32 *) 2746 (adev->gfx.mec_fw->data + 2747 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2748 table_offset = le32_to_cpu(hdr->jt_offset); 2749 table_size = le32_to_cpu(hdr->jt_size); 2750 } else { 2751 const struct gfx_firmware_header_v1_0 *hdr = 2752 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2753 fw_data = (const __le32 *) 2754 (adev->gfx.mec2_fw->data + 2755 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2756 table_offset = le32_to_cpu(hdr->jt_offset); 2757 table_size = le32_to_cpu(hdr->jt_size); 2758 } 2759 2760 for (i = 0; i < table_size; i ++) { 2761 dst_ptr[bo_offset + i] = 2762 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2763 } 2764 2765 bo_offset += table_size; 2766 } 2767 } 2768 */ 2769 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2770 bool enable) 2771 { 2772 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2773 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2774 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2775 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2776 } else { 2777 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2778 (void)RREG32(mmDB_RENDER_CONTROL); 2779 } 2780 } 2781 2782 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2783 { 2784 u32 tmp; 2785 2786 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2787 2788 tmp = RREG32(mmRLC_MAX_PG_CU); 2789 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2790 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2791 WREG32(mmRLC_MAX_PG_CU, tmp); 2792 } 2793 2794 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2795 bool enable) 2796 { 2797 u32 data, orig; 2798 2799 orig = data = RREG32(mmRLC_PG_CNTL); 2800 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2801 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2802 else 2803 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2804 if (orig != data) 2805 WREG32(mmRLC_PG_CNTL, data); 2806 } 2807 2808 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2809 bool enable) 2810 { 2811 u32 data, orig; 2812 2813 orig = data = RREG32(mmRLC_PG_CNTL); 2814 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2815 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2816 else 2817 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2818 if (orig != data) 2819 WREG32(mmRLC_PG_CNTL, data); 2820 } 2821 2822 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2823 { 2824 u32 tmp; 2825 2826 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2827 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2828 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2829 2830 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2831 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2832 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2833 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2834 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2835 } 2836 2837 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2838 { 2839 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2840 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2841 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2842 } 2843 2844 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2845 { 2846 u32 count = 0; 2847 const struct cs_section_def *sect = NULL; 2848 const struct cs_extent_def *ext = NULL; 2849 2850 if (adev->gfx.rlc.cs_data == NULL) 2851 return 0; 2852 2853 /* begin clear state */ 2854 count += 2; 2855 /* context control state */ 2856 count += 3; 2857 2858 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2859 for (ext = sect->section; ext->extent != NULL; ++ext) { 2860 if (sect->id == SECT_CONTEXT) 2861 count += 2 + ext->reg_count; 2862 else 2863 return 0; 2864 } 2865 } 2866 /* pa_sc_raster_config */ 2867 count += 3; 2868 /* end clear state */ 2869 count += 2; 2870 /* clear state */ 2871 count += 2; 2872 2873 return count; 2874 } 2875 2876 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 2877 volatile u32 *buffer) 2878 { 2879 u32 count = 0, i; 2880 const struct cs_section_def *sect = NULL; 2881 const struct cs_extent_def *ext = NULL; 2882 2883 if (adev->gfx.rlc.cs_data == NULL) 2884 return; 2885 if (buffer == NULL) 2886 return; 2887 2888 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2889 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2890 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2891 buffer[count++] = cpu_to_le32(0x80000000); 2892 buffer[count++] = cpu_to_le32(0x80000000); 2893 2894 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2895 for (ext = sect->section; ext->extent != NULL; ++ext) { 2896 if (sect->id == SECT_CONTEXT) { 2897 buffer[count++] = 2898 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2899 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); 2900 for (i = 0; i < ext->reg_count; i++) 2901 buffer[count++] = cpu_to_le32(ext->extent[i]); 2902 } else { 2903 return; 2904 } 2905 } 2906 } 2907 2908 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2909 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2910 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 2911 2912 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2913 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 2914 2915 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 2916 buffer[count++] = cpu_to_le32(0); 2917 } 2918 2919 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2920 { 2921 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2922 AMD_PG_SUPPORT_GFX_SMG | 2923 AMD_PG_SUPPORT_GFX_DMG | 2924 AMD_PG_SUPPORT_CP | 2925 AMD_PG_SUPPORT_GDS | 2926 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2927 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2928 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2929 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2930 gfx_v6_0_init_gfx_cgpg(adev); 2931 gfx_v6_0_enable_cp_pg(adev, true); 2932 gfx_v6_0_enable_gds_pg(adev, true); 2933 } else { 2934 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2935 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2936 2937 } 2938 gfx_v6_0_init_ao_cu_mask(adev); 2939 gfx_v6_0_update_gfx_pg(adev, true); 2940 } else { 2941 2942 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2943 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2944 } 2945 } 2946 2947 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 2948 { 2949 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2950 AMD_PG_SUPPORT_GFX_SMG | 2951 AMD_PG_SUPPORT_GFX_DMG | 2952 AMD_PG_SUPPORT_CP | 2953 AMD_PG_SUPPORT_GDS | 2954 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2955 gfx_v6_0_update_gfx_pg(adev, false); 2956 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2957 gfx_v6_0_enable_cp_pg(adev, false); 2958 gfx_v6_0_enable_gds_pg(adev, false); 2959 } 2960 } 2961 } 2962 2963 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 2964 { 2965 uint64_t clock; 2966 2967 mutex_lock(&adev->gfx.gpu_clock_mutex); 2968 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2969 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 2970 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2971 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2972 return clock; 2973 } 2974 2975 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2976 { 2977 if (flags & AMDGPU_HAVE_CTX_SWITCH) 2978 gfx_v6_0_ring_emit_vgt_flush(ring); 2979 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2980 amdgpu_ring_write(ring, 0x80000000); 2981 amdgpu_ring_write(ring, 0); 2982 } 2983 2984 2985 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 2986 { 2987 WREG32(mmSQ_IND_INDEX, 2988 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2989 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2990 (address << SQ_IND_INDEX__INDEX__SHIFT) | 2991 (SQ_IND_INDEX__FORCE_READ_MASK)); 2992 return RREG32(mmSQ_IND_DATA); 2993 } 2994 2995 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 2996 uint32_t wave, uint32_t thread, 2997 uint32_t regno, uint32_t num, uint32_t *out) 2998 { 2999 WREG32(mmSQ_IND_INDEX, 3000 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3001 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3002 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 3003 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 3004 (SQ_IND_INDEX__FORCE_READ_MASK) | 3005 (SQ_IND_INDEX__AUTO_INCR_MASK)); 3006 while (num--) 3007 *(out++) = RREG32(mmSQ_IND_DATA); 3008 } 3009 3010 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 3011 { 3012 /* type 0 wave data */ 3013 dst[(*no_fields)++] = 0; 3014 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 3015 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 3016 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 3017 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 3018 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 3019 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 3020 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 3021 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 3022 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 3023 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 3024 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 3025 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 3026 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 3027 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 3028 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 3029 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 3030 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 3031 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 3032 } 3033 3034 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 3035 uint32_t wave, uint32_t start, 3036 uint32_t size, uint32_t *dst) 3037 { 3038 wave_read_regs( 3039 adev, simd, wave, 0, 3040 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3041 } 3042 3043 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, 3044 u32 me, u32 pipe, u32 q) 3045 { 3046 DRM_INFO("Not implemented\n"); 3047 } 3048 3049 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3050 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3051 .select_se_sh = &gfx_v6_0_select_se_sh, 3052 .read_wave_data = &gfx_v6_0_read_wave_data, 3053 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3054 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q 3055 }; 3056 3057 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { 3058 .init = gfx_v6_0_rlc_init, 3059 .resume = gfx_v6_0_rlc_resume, 3060 .stop = gfx_v6_0_rlc_stop, 3061 .reset = gfx_v6_0_rlc_reset, 3062 .start = gfx_v6_0_rlc_start 3063 }; 3064 3065 static int gfx_v6_0_early_init(void *handle) 3066 { 3067 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3068 3069 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3070 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS; 3071 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3072 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; 3073 gfx_v6_0_set_ring_funcs(adev); 3074 gfx_v6_0_set_irq_funcs(adev); 3075 3076 return 0; 3077 } 3078 3079 static int gfx_v6_0_sw_init(void *handle) 3080 { 3081 struct amdgpu_ring *ring; 3082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3083 int i, r; 3084 3085 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3086 if (r) 3087 return r; 3088 3089 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3090 if (r) 3091 return r; 3092 3093 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3094 if (r) 3095 return r; 3096 3097 gfx_v6_0_scratch_init(adev); 3098 3099 r = gfx_v6_0_init_microcode(adev); 3100 if (r) { 3101 DRM_ERROR("Failed to load gfx firmware!\n"); 3102 return r; 3103 } 3104 3105 r = adev->gfx.rlc.funcs->init(adev); 3106 if (r) { 3107 DRM_ERROR("Failed to init rlc BOs!\n"); 3108 return r; 3109 } 3110 3111 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3112 ring = &adev->gfx.gfx_ring[i]; 3113 ring->ring_obj = NULL; 3114 sprintf(ring->name, "gfx"); 3115 r = amdgpu_ring_init(adev, ring, 1024, 3116 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 3117 if (r) 3118 return r; 3119 } 3120 3121 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3122 unsigned irq_type; 3123 3124 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3125 DRM_ERROR("Too many (%d) compute rings!\n", i); 3126 break; 3127 } 3128 ring = &adev->gfx.compute_ring[i]; 3129 ring->ring_obj = NULL; 3130 ring->use_doorbell = false; 3131 ring->doorbell_index = 0; 3132 ring->me = 1; 3133 ring->pipe = i; 3134 ring->queue = i; 3135 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3136 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3137 r = amdgpu_ring_init(adev, ring, 1024, 3138 &adev->gfx.eop_irq, irq_type); 3139 if (r) 3140 return r; 3141 } 3142 3143 return r; 3144 } 3145 3146 static int gfx_v6_0_sw_fini(void *handle) 3147 { 3148 int i; 3149 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3150 3151 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3152 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3153 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3154 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3155 3156 amdgpu_gfx_rlc_fini(adev); 3157 3158 return 0; 3159 } 3160 3161 static int gfx_v6_0_hw_init(void *handle) 3162 { 3163 int r; 3164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3165 3166 gfx_v6_0_constants_init(adev); 3167 3168 r = adev->gfx.rlc.funcs->resume(adev); 3169 if (r) 3170 return r; 3171 3172 r = gfx_v6_0_cp_resume(adev); 3173 if (r) 3174 return r; 3175 3176 adev->gfx.ce_ram_size = 0x8000; 3177 3178 return r; 3179 } 3180 3181 static int gfx_v6_0_hw_fini(void *handle) 3182 { 3183 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3184 3185 gfx_v6_0_cp_enable(adev, false); 3186 adev->gfx.rlc.funcs->stop(adev); 3187 gfx_v6_0_fini_pg(adev); 3188 3189 return 0; 3190 } 3191 3192 static int gfx_v6_0_suspend(void *handle) 3193 { 3194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3195 3196 return gfx_v6_0_hw_fini(adev); 3197 } 3198 3199 static int gfx_v6_0_resume(void *handle) 3200 { 3201 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3202 3203 return gfx_v6_0_hw_init(adev); 3204 } 3205 3206 static bool gfx_v6_0_is_idle(void *handle) 3207 { 3208 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3209 3210 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3211 return false; 3212 else 3213 return true; 3214 } 3215 3216 static int gfx_v6_0_wait_for_idle(void *handle) 3217 { 3218 unsigned i; 3219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3220 3221 for (i = 0; i < adev->usec_timeout; i++) { 3222 if (gfx_v6_0_is_idle(handle)) 3223 return 0; 3224 udelay(1); 3225 } 3226 return -ETIMEDOUT; 3227 } 3228 3229 static int gfx_v6_0_soft_reset(void *handle) 3230 { 3231 return 0; 3232 } 3233 3234 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3235 enum amdgpu_interrupt_state state) 3236 { 3237 u32 cp_int_cntl; 3238 3239 switch (state) { 3240 case AMDGPU_IRQ_STATE_DISABLE: 3241 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3242 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3243 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3244 break; 3245 case AMDGPU_IRQ_STATE_ENABLE: 3246 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3247 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3248 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3249 break; 3250 default: 3251 break; 3252 } 3253 } 3254 3255 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3256 int ring, 3257 enum amdgpu_interrupt_state state) 3258 { 3259 u32 cp_int_cntl; 3260 switch (state){ 3261 case AMDGPU_IRQ_STATE_DISABLE: 3262 if (ring == 0) { 3263 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3264 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3265 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3266 break; 3267 } else { 3268 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3269 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3270 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3271 break; 3272 3273 } 3274 case AMDGPU_IRQ_STATE_ENABLE: 3275 if (ring == 0) { 3276 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3277 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3278 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3279 break; 3280 } else { 3281 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3282 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3283 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3284 break; 3285 3286 } 3287 3288 default: 3289 BUG(); 3290 break; 3291 3292 } 3293 } 3294 3295 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3296 struct amdgpu_irq_src *src, 3297 unsigned type, 3298 enum amdgpu_interrupt_state state) 3299 { 3300 u32 cp_int_cntl; 3301 3302 switch (state) { 3303 case AMDGPU_IRQ_STATE_DISABLE: 3304 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3305 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3306 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3307 break; 3308 case AMDGPU_IRQ_STATE_ENABLE: 3309 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3310 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3311 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3312 break; 3313 default: 3314 break; 3315 } 3316 3317 return 0; 3318 } 3319 3320 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3321 struct amdgpu_irq_src *src, 3322 unsigned type, 3323 enum amdgpu_interrupt_state state) 3324 { 3325 u32 cp_int_cntl; 3326 3327 switch (state) { 3328 case AMDGPU_IRQ_STATE_DISABLE: 3329 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3330 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3331 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3332 break; 3333 case AMDGPU_IRQ_STATE_ENABLE: 3334 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3335 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3336 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3337 break; 3338 default: 3339 break; 3340 } 3341 3342 return 0; 3343 } 3344 3345 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3346 struct amdgpu_irq_src *src, 3347 unsigned type, 3348 enum amdgpu_interrupt_state state) 3349 { 3350 switch (type) { 3351 case AMDGPU_CP_IRQ_GFX_EOP: 3352 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3353 break; 3354 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3355 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3356 break; 3357 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3358 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3359 break; 3360 default: 3361 break; 3362 } 3363 return 0; 3364 } 3365 3366 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3367 struct amdgpu_irq_src *source, 3368 struct amdgpu_iv_entry *entry) 3369 { 3370 switch (entry->ring_id) { 3371 case 0: 3372 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3373 break; 3374 case 1: 3375 case 2: 3376 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3377 break; 3378 default: 3379 break; 3380 } 3381 return 0; 3382 } 3383 3384 static void gfx_v6_0_fault(struct amdgpu_device *adev, 3385 struct amdgpu_iv_entry *entry) 3386 { 3387 struct amdgpu_ring *ring; 3388 3389 switch (entry->ring_id) { 3390 case 0: 3391 ring = &adev->gfx.gfx_ring[0]; 3392 break; 3393 case 1: 3394 case 2: 3395 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; 3396 break; 3397 default: 3398 return; 3399 } 3400 drm_sched_fault(&ring->sched); 3401 } 3402 3403 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3404 struct amdgpu_irq_src *source, 3405 struct amdgpu_iv_entry *entry) 3406 { 3407 DRM_ERROR("Illegal register access in command stream\n"); 3408 gfx_v6_0_fault(adev, entry); 3409 return 0; 3410 } 3411 3412 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3413 struct amdgpu_irq_src *source, 3414 struct amdgpu_iv_entry *entry) 3415 { 3416 DRM_ERROR("Illegal instruction in command stream\n"); 3417 gfx_v6_0_fault(adev, entry); 3418 return 0; 3419 } 3420 3421 static int gfx_v6_0_set_clockgating_state(void *handle, 3422 enum amd_clockgating_state state) 3423 { 3424 bool gate = false; 3425 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3426 3427 if (state == AMD_CG_STATE_GATE) 3428 gate = true; 3429 3430 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3431 if (gate) { 3432 gfx_v6_0_enable_mgcg(adev, true); 3433 gfx_v6_0_enable_cgcg(adev, true); 3434 } else { 3435 gfx_v6_0_enable_cgcg(adev, false); 3436 gfx_v6_0_enable_mgcg(adev, false); 3437 } 3438 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3439 3440 return 0; 3441 } 3442 3443 static int gfx_v6_0_set_powergating_state(void *handle, 3444 enum amd_powergating_state state) 3445 { 3446 bool gate = false; 3447 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3448 3449 if (state == AMD_PG_STATE_GATE) 3450 gate = true; 3451 3452 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3453 AMD_PG_SUPPORT_GFX_SMG | 3454 AMD_PG_SUPPORT_GFX_DMG | 3455 AMD_PG_SUPPORT_CP | 3456 AMD_PG_SUPPORT_GDS | 3457 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3458 gfx_v6_0_update_gfx_pg(adev, gate); 3459 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3460 gfx_v6_0_enable_cp_pg(adev, gate); 3461 gfx_v6_0_enable_gds_pg(adev, gate); 3462 } 3463 } 3464 3465 return 0; 3466 } 3467 3468 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3469 .name = "gfx_v6_0", 3470 .early_init = gfx_v6_0_early_init, 3471 .late_init = NULL, 3472 .sw_init = gfx_v6_0_sw_init, 3473 .sw_fini = gfx_v6_0_sw_fini, 3474 .hw_init = gfx_v6_0_hw_init, 3475 .hw_fini = gfx_v6_0_hw_fini, 3476 .suspend = gfx_v6_0_suspend, 3477 .resume = gfx_v6_0_resume, 3478 .is_idle = gfx_v6_0_is_idle, 3479 .wait_for_idle = gfx_v6_0_wait_for_idle, 3480 .soft_reset = gfx_v6_0_soft_reset, 3481 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3482 .set_powergating_state = gfx_v6_0_set_powergating_state, 3483 }; 3484 3485 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3486 .type = AMDGPU_RING_TYPE_GFX, 3487 .align_mask = 0xff, 3488 .nop = 0x80000000, 3489 .support_64bit_ptrs = false, 3490 .get_rptr = gfx_v6_0_ring_get_rptr, 3491 .get_wptr = gfx_v6_0_ring_get_wptr, 3492 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3493 .emit_frame_size = 3494 5 + 5 + /* hdp flush / invalidate */ 3495 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3496 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3497 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3498 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3499 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3500 .emit_ib = gfx_v6_0_ring_emit_ib, 3501 .emit_fence = gfx_v6_0_ring_emit_fence, 3502 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3503 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3504 .test_ring = gfx_v6_0_ring_test_ring, 3505 .test_ib = gfx_v6_0_ring_test_ib, 3506 .insert_nop = amdgpu_ring_insert_nop, 3507 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3508 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3509 }; 3510 3511 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3512 .type = AMDGPU_RING_TYPE_COMPUTE, 3513 .align_mask = 0xff, 3514 .nop = 0x80000000, 3515 .get_rptr = gfx_v6_0_ring_get_rptr, 3516 .get_wptr = gfx_v6_0_ring_get_wptr, 3517 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3518 .emit_frame_size = 3519 5 + 5 + /* hdp flush / invalidate */ 3520 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3521 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ 3522 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3523 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3524 .emit_ib = gfx_v6_0_ring_emit_ib, 3525 .emit_fence = gfx_v6_0_ring_emit_fence, 3526 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3527 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3528 .test_ring = gfx_v6_0_ring_test_ring, 3529 .test_ib = gfx_v6_0_ring_test_ib, 3530 .insert_nop = amdgpu_ring_insert_nop, 3531 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3532 }; 3533 3534 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3535 { 3536 int i; 3537 3538 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3539 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3540 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3541 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3542 } 3543 3544 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3545 .set = gfx_v6_0_set_eop_interrupt_state, 3546 .process = gfx_v6_0_eop_irq, 3547 }; 3548 3549 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3550 .set = gfx_v6_0_set_priv_reg_fault_state, 3551 .process = gfx_v6_0_priv_reg_irq, 3552 }; 3553 3554 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3555 .set = gfx_v6_0_set_priv_inst_fault_state, 3556 .process = gfx_v6_0_priv_inst_irq, 3557 }; 3558 3559 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3560 { 3561 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3562 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3563 3564 adev->gfx.priv_reg_irq.num_types = 1; 3565 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3566 3567 adev->gfx.priv_inst_irq.num_types = 1; 3568 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3569 } 3570 3571 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3572 { 3573 int i, j, k, counter, active_cu_number = 0; 3574 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3575 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3576 unsigned disable_masks[4 * 2]; 3577 u32 ao_cu_num; 3578 3579 if (adev->flags & AMD_IS_APU) 3580 ao_cu_num = 2; 3581 else 3582 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3583 3584 memset(cu_info, 0, sizeof(*cu_info)); 3585 3586 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 3587 3588 mutex_lock(&adev->grbm_idx_mutex); 3589 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3590 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3591 mask = 1; 3592 ao_bitmap = 0; 3593 counter = 0; 3594 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 3595 if (i < 4 && j < 2) 3596 gfx_v6_0_set_user_cu_inactive_bitmap( 3597 adev, disable_masks[i * 2 + j]); 3598 bitmap = gfx_v6_0_get_cu_enabled(adev); 3599 cu_info->bitmap[i][j] = bitmap; 3600 3601 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3602 if (bitmap & mask) { 3603 if (counter < ao_cu_num) 3604 ao_bitmap |= mask; 3605 counter ++; 3606 } 3607 mask <<= 1; 3608 } 3609 active_cu_number += counter; 3610 if (i < 2 && j < 2) 3611 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3612 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3613 } 3614 } 3615 3616 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3617 mutex_unlock(&adev->grbm_idx_mutex); 3618 3619 cu_info->number = active_cu_number; 3620 cu_info->ao_cu_mask = ao_cu_mask; 3621 } 3622 3623 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3624 { 3625 .type = AMD_IP_BLOCK_TYPE_GFX, 3626 .major = 6, 3627 .minor = 0, 3628 .rev = 0, 3629 .funcs = &gfx_v6_0_ip_funcs, 3630 }; 3631