1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "amdgpu_gfx.h" 27 #include "amdgpu_ucode.h" 28 #include "clearstate_si.h" 29 #include "bif/bif_3_0_d.h" 30 #include "bif/bif_3_0_sh_mask.h" 31 #include "oss/oss_1_0_d.h" 32 #include "oss/oss_1_0_sh_mask.h" 33 #include "gca/gfx_6_0_d.h" 34 #include "gca/gfx_6_0_sh_mask.h" 35 #include "gmc/gmc_6_0_d.h" 36 #include "gmc/gmc_6_0_sh_mask.h" 37 #include "dce/dce_6_0_d.h" 38 #include "dce/dce_6_0_sh_mask.h" 39 #include "gca/gfx_7_2_enum.h" 40 #include "si_enums.h" 41 #include "si.h" 42 43 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 44 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 45 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 46 47 MODULE_FIRMWARE("radeon/tahiti_pfp.bin"); 48 MODULE_FIRMWARE("radeon/tahiti_me.bin"); 49 MODULE_FIRMWARE("radeon/tahiti_ce.bin"); 50 MODULE_FIRMWARE("radeon/tahiti_rlc.bin"); 51 52 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin"); 53 MODULE_FIRMWARE("radeon/pitcairn_me.bin"); 54 MODULE_FIRMWARE("radeon/pitcairn_ce.bin"); 55 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin"); 56 57 MODULE_FIRMWARE("radeon/verde_pfp.bin"); 58 MODULE_FIRMWARE("radeon/verde_me.bin"); 59 MODULE_FIRMWARE("radeon/verde_ce.bin"); 60 MODULE_FIRMWARE("radeon/verde_rlc.bin"); 61 62 MODULE_FIRMWARE("radeon/oland_pfp.bin"); 63 MODULE_FIRMWARE("radeon/oland_me.bin"); 64 MODULE_FIRMWARE("radeon/oland_ce.bin"); 65 MODULE_FIRMWARE("radeon/oland_rlc.bin"); 66 67 MODULE_FIRMWARE("radeon/hainan_pfp.bin"); 68 MODULE_FIRMWARE("radeon/hainan_me.bin"); 69 MODULE_FIRMWARE("radeon/hainan_ce.bin"); 70 MODULE_FIRMWARE("radeon/hainan_rlc.bin"); 71 72 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 73 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 74 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 75 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 76 77 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 78 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 79 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 80 #define MICRO_TILE_MODE(x) ((x) << 0) 81 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 82 #define BANK_WIDTH(x) ((x) << 14) 83 #define BANK_HEIGHT(x) ((x) << 16) 84 #define MACRO_TILE_ASPECT(x) ((x) << 18) 85 #define NUM_BANKS(x) ((x) << 20) 86 87 static const u32 verde_rlc_save_restore_register_list[] = 88 { 89 (0x8000 << 16) | (0x98f4 >> 2), 90 0x00000000, 91 (0x8040 << 16) | (0x98f4 >> 2), 92 0x00000000, 93 (0x8000 << 16) | (0xe80 >> 2), 94 0x00000000, 95 (0x8040 << 16) | (0xe80 >> 2), 96 0x00000000, 97 (0x8000 << 16) | (0x89bc >> 2), 98 0x00000000, 99 (0x8040 << 16) | (0x89bc >> 2), 100 0x00000000, 101 (0x8000 << 16) | (0x8c1c >> 2), 102 0x00000000, 103 (0x8040 << 16) | (0x8c1c >> 2), 104 0x00000000, 105 (0x9c00 << 16) | (0x98f0 >> 2), 106 0x00000000, 107 (0x9c00 << 16) | (0xe7c >> 2), 108 0x00000000, 109 (0x8000 << 16) | (0x9148 >> 2), 110 0x00000000, 111 (0x8040 << 16) | (0x9148 >> 2), 112 0x00000000, 113 (0x9c00 << 16) | (0x9150 >> 2), 114 0x00000000, 115 (0x9c00 << 16) | (0x897c >> 2), 116 0x00000000, 117 (0x9c00 << 16) | (0x8d8c >> 2), 118 0x00000000, 119 (0x9c00 << 16) | (0xac54 >> 2), 120 0X00000000, 121 0x3, 122 (0x9c00 << 16) | (0x98f8 >> 2), 123 0x00000000, 124 (0x9c00 << 16) | (0x9910 >> 2), 125 0x00000000, 126 (0x9c00 << 16) | (0x9914 >> 2), 127 0x00000000, 128 (0x9c00 << 16) | (0x9918 >> 2), 129 0x00000000, 130 (0x9c00 << 16) | (0x991c >> 2), 131 0x00000000, 132 (0x9c00 << 16) | (0x9920 >> 2), 133 0x00000000, 134 (0x9c00 << 16) | (0x9924 >> 2), 135 0x00000000, 136 (0x9c00 << 16) | (0x9928 >> 2), 137 0x00000000, 138 (0x9c00 << 16) | (0x992c >> 2), 139 0x00000000, 140 (0x9c00 << 16) | (0x9930 >> 2), 141 0x00000000, 142 (0x9c00 << 16) | (0x9934 >> 2), 143 0x00000000, 144 (0x9c00 << 16) | (0x9938 >> 2), 145 0x00000000, 146 (0x9c00 << 16) | (0x993c >> 2), 147 0x00000000, 148 (0x9c00 << 16) | (0x9940 >> 2), 149 0x00000000, 150 (0x9c00 << 16) | (0x9944 >> 2), 151 0x00000000, 152 (0x9c00 << 16) | (0x9948 >> 2), 153 0x00000000, 154 (0x9c00 << 16) | (0x994c >> 2), 155 0x00000000, 156 (0x9c00 << 16) | (0x9950 >> 2), 157 0x00000000, 158 (0x9c00 << 16) | (0x9954 >> 2), 159 0x00000000, 160 (0x9c00 << 16) | (0x9958 >> 2), 161 0x00000000, 162 (0x9c00 << 16) | (0x995c >> 2), 163 0x00000000, 164 (0x9c00 << 16) | (0x9960 >> 2), 165 0x00000000, 166 (0x9c00 << 16) | (0x9964 >> 2), 167 0x00000000, 168 (0x9c00 << 16) | (0x9968 >> 2), 169 0x00000000, 170 (0x9c00 << 16) | (0x996c >> 2), 171 0x00000000, 172 (0x9c00 << 16) | (0x9970 >> 2), 173 0x00000000, 174 (0x9c00 << 16) | (0x9974 >> 2), 175 0x00000000, 176 (0x9c00 << 16) | (0x9978 >> 2), 177 0x00000000, 178 (0x9c00 << 16) | (0x997c >> 2), 179 0x00000000, 180 (0x9c00 << 16) | (0x9980 >> 2), 181 0x00000000, 182 (0x9c00 << 16) | (0x9984 >> 2), 183 0x00000000, 184 (0x9c00 << 16) | (0x9988 >> 2), 185 0x00000000, 186 (0x9c00 << 16) | (0x998c >> 2), 187 0x00000000, 188 (0x9c00 << 16) | (0x8c00 >> 2), 189 0x00000000, 190 (0x9c00 << 16) | (0x8c14 >> 2), 191 0x00000000, 192 (0x9c00 << 16) | (0x8c04 >> 2), 193 0x00000000, 194 (0x9c00 << 16) | (0x8c08 >> 2), 195 0x00000000, 196 (0x8000 << 16) | (0x9b7c >> 2), 197 0x00000000, 198 (0x8040 << 16) | (0x9b7c >> 2), 199 0x00000000, 200 (0x8000 << 16) | (0xe84 >> 2), 201 0x00000000, 202 (0x8040 << 16) | (0xe84 >> 2), 203 0x00000000, 204 (0x8000 << 16) | (0x89c0 >> 2), 205 0x00000000, 206 (0x8040 << 16) | (0x89c0 >> 2), 207 0x00000000, 208 (0x8000 << 16) | (0x914c >> 2), 209 0x00000000, 210 (0x8040 << 16) | (0x914c >> 2), 211 0x00000000, 212 (0x8000 << 16) | (0x8c20 >> 2), 213 0x00000000, 214 (0x8040 << 16) | (0x8c20 >> 2), 215 0x00000000, 216 (0x8000 << 16) | (0x9354 >> 2), 217 0x00000000, 218 (0x8040 << 16) | (0x9354 >> 2), 219 0x00000000, 220 (0x9c00 << 16) | (0x9060 >> 2), 221 0x00000000, 222 (0x9c00 << 16) | (0x9364 >> 2), 223 0x00000000, 224 (0x9c00 << 16) | (0x9100 >> 2), 225 0x00000000, 226 (0x9c00 << 16) | (0x913c >> 2), 227 0x00000000, 228 (0x8000 << 16) | (0x90e0 >> 2), 229 0x00000000, 230 (0x8000 << 16) | (0x90e4 >> 2), 231 0x00000000, 232 (0x8000 << 16) | (0x90e8 >> 2), 233 0x00000000, 234 (0x8040 << 16) | (0x90e0 >> 2), 235 0x00000000, 236 (0x8040 << 16) | (0x90e4 >> 2), 237 0x00000000, 238 (0x8040 << 16) | (0x90e8 >> 2), 239 0x00000000, 240 (0x9c00 << 16) | (0x8bcc >> 2), 241 0x00000000, 242 (0x9c00 << 16) | (0x8b24 >> 2), 243 0x00000000, 244 (0x9c00 << 16) | (0x88c4 >> 2), 245 0x00000000, 246 (0x9c00 << 16) | (0x8e50 >> 2), 247 0x00000000, 248 (0x9c00 << 16) | (0x8c0c >> 2), 249 0x00000000, 250 (0x9c00 << 16) | (0x8e58 >> 2), 251 0x00000000, 252 (0x9c00 << 16) | (0x8e5c >> 2), 253 0x00000000, 254 (0x9c00 << 16) | (0x9508 >> 2), 255 0x00000000, 256 (0x9c00 << 16) | (0x950c >> 2), 257 0x00000000, 258 (0x9c00 << 16) | (0x9494 >> 2), 259 0x00000000, 260 (0x9c00 << 16) | (0xac0c >> 2), 261 0x00000000, 262 (0x9c00 << 16) | (0xac10 >> 2), 263 0x00000000, 264 (0x9c00 << 16) | (0xac14 >> 2), 265 0x00000000, 266 (0x9c00 << 16) | (0xae00 >> 2), 267 0x00000000, 268 (0x9c00 << 16) | (0xac08 >> 2), 269 0x00000000, 270 (0x9c00 << 16) | (0x88d4 >> 2), 271 0x00000000, 272 (0x9c00 << 16) | (0x88c8 >> 2), 273 0x00000000, 274 (0x9c00 << 16) | (0x88cc >> 2), 275 0x00000000, 276 (0x9c00 << 16) | (0x89b0 >> 2), 277 0x00000000, 278 (0x9c00 << 16) | (0x8b10 >> 2), 279 0x00000000, 280 (0x9c00 << 16) | (0x8a14 >> 2), 281 0x00000000, 282 (0x9c00 << 16) | (0x9830 >> 2), 283 0x00000000, 284 (0x9c00 << 16) | (0x9834 >> 2), 285 0x00000000, 286 (0x9c00 << 16) | (0x9838 >> 2), 287 0x00000000, 288 (0x9c00 << 16) | (0x9a10 >> 2), 289 0x00000000, 290 (0x8000 << 16) | (0x9870 >> 2), 291 0x00000000, 292 (0x8000 << 16) | (0x9874 >> 2), 293 0x00000000, 294 (0x8001 << 16) | (0x9870 >> 2), 295 0x00000000, 296 (0x8001 << 16) | (0x9874 >> 2), 297 0x00000000, 298 (0x8040 << 16) | (0x9870 >> 2), 299 0x00000000, 300 (0x8040 << 16) | (0x9874 >> 2), 301 0x00000000, 302 (0x8041 << 16) | (0x9870 >> 2), 303 0x00000000, 304 (0x8041 << 16) | (0x9874 >> 2), 305 0x00000000, 306 0x00000000 307 }; 308 309 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 310 { 311 const char *chip_name; 312 char fw_name[30]; 313 int err; 314 const struct gfx_firmware_header_v1_0 *cp_hdr; 315 const struct rlc_firmware_header_v1_0 *rlc_hdr; 316 317 DRM_DEBUG("\n"); 318 319 switch (adev->asic_type) { 320 case CHIP_TAHITI: 321 chip_name = "tahiti"; 322 break; 323 case CHIP_PITCAIRN: 324 chip_name = "pitcairn"; 325 break; 326 case CHIP_VERDE: 327 chip_name = "verde"; 328 break; 329 case CHIP_OLAND: 330 chip_name = "oland"; 331 break; 332 case CHIP_HAINAN: 333 chip_name = "hainan"; 334 break; 335 default: BUG(); 336 } 337 338 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 339 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 340 if (err) 341 goto out; 342 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 343 if (err) 344 goto out; 345 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 346 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 347 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 348 349 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 350 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 351 if (err) 352 goto out; 353 err = amdgpu_ucode_validate(adev->gfx.me_fw); 354 if (err) 355 goto out; 356 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 357 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 358 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 359 360 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); 361 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 362 if (err) 363 goto out; 364 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 365 if (err) 366 goto out; 367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 368 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 369 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 370 371 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); 372 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 373 if (err) 374 goto out; 375 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 376 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 377 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 378 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 379 380 out: 381 if (err) { 382 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name); 383 release_firmware(adev->gfx.pfp_fw); 384 adev->gfx.pfp_fw = NULL; 385 release_firmware(adev->gfx.me_fw); 386 adev->gfx.me_fw = NULL; 387 release_firmware(adev->gfx.ce_fw); 388 adev->gfx.ce_fw = NULL; 389 release_firmware(adev->gfx.rlc_fw); 390 adev->gfx.rlc_fw = NULL; 391 } 392 return err; 393 } 394 395 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 396 { 397 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 398 u32 reg_offset, split_equal_to_row_size, *tilemode; 399 400 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 401 tilemode = adev->gfx.config.tile_mode_array; 402 403 switch (adev->gfx.config.mem_row_size_in_kb) { 404 case 1: 405 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 406 break; 407 case 2: 408 default: 409 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 410 break; 411 case 4: 412 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 413 break; 414 } 415 416 if (adev->asic_type == CHIP_VERDE) { 417 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 418 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 419 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 421 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 424 NUM_BANKS(ADDR_SURF_16_BANK); 425 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 426 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 427 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 428 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 429 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 432 NUM_BANKS(ADDR_SURF_16_BANK); 433 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 434 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 435 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 436 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 437 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 440 NUM_BANKS(ADDR_SURF_16_BANK); 441 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 442 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 443 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 447 NUM_BANKS(ADDR_SURF_8_BANK) | 448 TILE_SPLIT(split_equal_to_row_size); 449 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 450 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 451 PIPE_CONFIG(ADDR_SURF_P4_8x16); 452 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 453 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 454 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 456 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 459 NUM_BANKS(ADDR_SURF_4_BANK); 460 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 461 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 462 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 464 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 466 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 467 NUM_BANKS(ADDR_SURF_4_BANK); 468 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 469 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 470 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 475 NUM_BANKS(ADDR_SURF_2_BANK); 476 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 477 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 478 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 479 PIPE_CONFIG(ADDR_SURF_P4_8x16); 480 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 481 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 482 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 483 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 484 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 487 NUM_BANKS(ADDR_SURF_16_BANK); 488 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 489 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 490 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 492 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 495 NUM_BANKS(ADDR_SURF_16_BANK); 496 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 497 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 498 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 499 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 500 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 501 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 502 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 503 NUM_BANKS(ADDR_SURF_16_BANK); 504 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 505 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 506 PIPE_CONFIG(ADDR_SURF_P4_8x16); 507 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 508 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 509 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 510 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 514 NUM_BANKS(ADDR_SURF_16_BANK); 515 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 516 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 517 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 519 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 522 NUM_BANKS(ADDR_SURF_16_BANK); 523 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 524 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 525 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 527 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 530 NUM_BANKS(ADDR_SURF_16_BANK); 531 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 532 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 533 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 534 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 537 NUM_BANKS(ADDR_SURF_16_BANK) | 538 TILE_SPLIT(split_equal_to_row_size); 539 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 540 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 541 PIPE_CONFIG(ADDR_SURF_P4_8x16); 542 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 543 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 544 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 545 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 548 NUM_BANKS(ADDR_SURF_16_BANK) | 549 TILE_SPLIT(split_equal_to_row_size); 550 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 551 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 552 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 556 NUM_BANKS(ADDR_SURF_16_BANK) | 557 TILE_SPLIT(split_equal_to_row_size); 558 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 559 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 560 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 562 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 563 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 564 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 565 NUM_BANKS(ADDR_SURF_8_BANK); 566 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 568 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 569 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 570 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 571 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 572 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 573 NUM_BANKS(ADDR_SURF_8_BANK); 574 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 575 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 576 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 577 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 579 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 580 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 581 NUM_BANKS(ADDR_SURF_4_BANK); 582 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 583 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 584 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 585 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 586 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 587 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 588 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 589 NUM_BANKS(ADDR_SURF_4_BANK); 590 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 591 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 592 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 593 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 597 NUM_BANKS(ADDR_SURF_2_BANK); 598 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 599 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 600 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 602 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 603 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 604 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 605 NUM_BANKS(ADDR_SURF_2_BANK); 606 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 607 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 608 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 609 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 610 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 611 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 612 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 613 NUM_BANKS(ADDR_SURF_2_BANK); 614 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 615 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 616 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 617 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 618 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 621 NUM_BANKS(ADDR_SURF_2_BANK); 622 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 623 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 624 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 625 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 626 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 629 NUM_BANKS(ADDR_SURF_2_BANK); 630 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 631 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 632 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 634 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 637 NUM_BANKS(ADDR_SURF_2_BANK); 638 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 639 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 640 } else if (adev->asic_type == CHIP_OLAND) { 641 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 643 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 645 NUM_BANKS(ADDR_SURF_16_BANK) | 646 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 649 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 650 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 651 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 652 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 653 NUM_BANKS(ADDR_SURF_16_BANK) | 654 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 657 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 658 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 659 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 660 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 661 NUM_BANKS(ADDR_SURF_16_BANK) | 662 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 665 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 666 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 667 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 668 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 669 NUM_BANKS(ADDR_SURF_16_BANK) | 670 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 673 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 674 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 675 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 676 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 677 NUM_BANKS(ADDR_SURF_16_BANK) | 678 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 681 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 683 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 684 TILE_SPLIT(split_equal_to_row_size) | 685 NUM_BANKS(ADDR_SURF_16_BANK) | 686 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 687 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 688 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 689 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 690 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 691 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 692 TILE_SPLIT(split_equal_to_row_size) | 693 NUM_BANKS(ADDR_SURF_16_BANK) | 694 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 697 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 698 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 699 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 700 TILE_SPLIT(split_equal_to_row_size) | 701 NUM_BANKS(ADDR_SURF_16_BANK) | 702 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 703 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 704 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 705 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 706 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 707 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 708 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 709 NUM_BANKS(ADDR_SURF_16_BANK) | 710 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 711 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 712 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 713 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 714 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 715 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 716 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 717 NUM_BANKS(ADDR_SURF_16_BANK) | 718 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 721 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 722 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 723 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 725 NUM_BANKS(ADDR_SURF_16_BANK) | 726 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 727 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 728 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 729 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 730 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 731 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 732 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 733 NUM_BANKS(ADDR_SURF_16_BANK) | 734 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 737 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 738 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 739 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 740 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 741 NUM_BANKS(ADDR_SURF_16_BANK) | 742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 745 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 746 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 747 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 748 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 749 NUM_BANKS(ADDR_SURF_16_BANK) | 750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 753 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 754 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 755 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 756 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 757 NUM_BANKS(ADDR_SURF_16_BANK) | 758 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 759 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 760 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 761 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 762 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 763 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 764 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 765 NUM_BANKS(ADDR_SURF_16_BANK) | 766 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 767 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 768 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 769 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 770 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 771 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 772 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 773 NUM_BANKS(ADDR_SURF_16_BANK) | 774 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 775 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 776 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 777 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 778 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 779 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 780 TILE_SPLIT(split_equal_to_row_size) | 781 NUM_BANKS(ADDR_SURF_16_BANK) | 782 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 785 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 786 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 787 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 789 NUM_BANKS(ADDR_SURF_16_BANK) | 790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 791 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 792 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 793 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 794 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 795 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 796 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 797 NUM_BANKS(ADDR_SURF_16_BANK) | 798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 801 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 802 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 803 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 804 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 805 NUM_BANKS(ADDR_SURF_16_BANK) | 806 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 807 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 808 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 809 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 810 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 811 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 812 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 813 NUM_BANKS(ADDR_SURF_16_BANK) | 814 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 815 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 816 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 817 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 818 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 819 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 820 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 821 NUM_BANKS(ADDR_SURF_8_BANK) | 822 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); 825 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 826 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 827 } else if (adev->asic_type == CHIP_HAINAN) { 828 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 829 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 830 PIPE_CONFIG(ADDR_SURF_P2) | 831 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 832 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 835 NUM_BANKS(ADDR_SURF_16_BANK); 836 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 837 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 838 PIPE_CONFIG(ADDR_SURF_P2) | 839 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 840 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 843 NUM_BANKS(ADDR_SURF_16_BANK); 844 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 845 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 846 PIPE_CONFIG(ADDR_SURF_P2) | 847 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 848 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 851 NUM_BANKS(ADDR_SURF_16_BANK); 852 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 853 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 854 PIPE_CONFIG(ADDR_SURF_P2) | 855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 858 NUM_BANKS(ADDR_SURF_8_BANK) | 859 TILE_SPLIT(split_equal_to_row_size); 860 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 861 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 862 PIPE_CONFIG(ADDR_SURF_P2); 863 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 864 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 865 PIPE_CONFIG(ADDR_SURF_P2) | 866 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 867 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 868 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 869 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 870 NUM_BANKS(ADDR_SURF_8_BANK); 871 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 872 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 873 PIPE_CONFIG(ADDR_SURF_P2) | 874 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 875 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 876 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 877 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 878 NUM_BANKS(ADDR_SURF_8_BANK); 879 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 880 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 881 PIPE_CONFIG(ADDR_SURF_P2) | 882 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 883 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 884 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 885 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 886 NUM_BANKS(ADDR_SURF_4_BANK); 887 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 888 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 889 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 890 PIPE_CONFIG(ADDR_SURF_P2); 891 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 892 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 893 PIPE_CONFIG(ADDR_SURF_P2) | 894 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 895 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 896 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 897 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 898 NUM_BANKS(ADDR_SURF_16_BANK); 899 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 900 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 901 PIPE_CONFIG(ADDR_SURF_P2) | 902 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 903 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 904 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 905 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 906 NUM_BANKS(ADDR_SURF_16_BANK); 907 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 908 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 909 PIPE_CONFIG(ADDR_SURF_P2) | 910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 911 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 912 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 913 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 914 NUM_BANKS(ADDR_SURF_16_BANK); 915 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 916 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 917 PIPE_CONFIG(ADDR_SURF_P2); 918 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 919 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 920 PIPE_CONFIG(ADDR_SURF_P2) | 921 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 922 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 925 NUM_BANKS(ADDR_SURF_16_BANK); 926 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 927 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 928 PIPE_CONFIG(ADDR_SURF_P2) | 929 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 933 NUM_BANKS(ADDR_SURF_16_BANK); 934 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 935 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 936 PIPE_CONFIG(ADDR_SURF_P2) | 937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 941 NUM_BANKS(ADDR_SURF_16_BANK); 942 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 943 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 944 PIPE_CONFIG(ADDR_SURF_P2) | 945 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 946 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 947 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 948 NUM_BANKS(ADDR_SURF_16_BANK) | 949 TILE_SPLIT(split_equal_to_row_size); 950 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 951 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 952 PIPE_CONFIG(ADDR_SURF_P2); 953 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 954 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 955 PIPE_CONFIG(ADDR_SURF_P2) | 956 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 957 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 958 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 959 NUM_BANKS(ADDR_SURF_16_BANK) | 960 TILE_SPLIT(split_equal_to_row_size); 961 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 962 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 963 PIPE_CONFIG(ADDR_SURF_P2) | 964 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 967 NUM_BANKS(ADDR_SURF_16_BANK) | 968 TILE_SPLIT(split_equal_to_row_size); 969 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 970 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 971 PIPE_CONFIG(ADDR_SURF_P2) | 972 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 973 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 974 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 975 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 976 NUM_BANKS(ADDR_SURF_8_BANK); 977 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 978 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 979 PIPE_CONFIG(ADDR_SURF_P2) | 980 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 981 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 982 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 983 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 984 NUM_BANKS(ADDR_SURF_8_BANK); 985 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 986 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 987 PIPE_CONFIG(ADDR_SURF_P2) | 988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 989 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 992 NUM_BANKS(ADDR_SURF_8_BANK); 993 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 994 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 995 PIPE_CONFIG(ADDR_SURF_P2) | 996 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 997 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 998 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 999 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1000 NUM_BANKS(ADDR_SURF_8_BANK); 1001 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1002 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1003 PIPE_CONFIG(ADDR_SURF_P2) | 1004 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1005 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1006 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1007 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1008 NUM_BANKS(ADDR_SURF_4_BANK); 1009 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1010 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1011 PIPE_CONFIG(ADDR_SURF_P2) | 1012 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1013 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1014 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1015 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1016 NUM_BANKS(ADDR_SURF_4_BANK); 1017 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1018 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1019 PIPE_CONFIG(ADDR_SURF_P2) | 1020 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1021 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1022 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1023 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1024 NUM_BANKS(ADDR_SURF_4_BANK); 1025 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1026 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1027 PIPE_CONFIG(ADDR_SURF_P2) | 1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1029 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1032 NUM_BANKS(ADDR_SURF_4_BANK); 1033 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1034 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1035 PIPE_CONFIG(ADDR_SURF_P2) | 1036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1037 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1038 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1039 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1040 NUM_BANKS(ADDR_SURF_4_BANK); 1041 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1042 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1043 PIPE_CONFIG(ADDR_SURF_P2) | 1044 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1045 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1046 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1047 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1048 NUM_BANKS(ADDR_SURF_4_BANK); 1049 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1050 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1051 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1052 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1053 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1054 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1059 NUM_BANKS(ADDR_SURF_16_BANK); 1060 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1061 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1062 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1064 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1065 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1066 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1067 NUM_BANKS(ADDR_SURF_16_BANK); 1068 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1069 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1070 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1071 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1072 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1073 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1074 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1075 NUM_BANKS(ADDR_SURF_16_BANK); 1076 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1077 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1078 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1079 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1082 NUM_BANKS(ADDR_SURF_4_BANK) | 1083 TILE_SPLIT(split_equal_to_row_size); 1084 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1085 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1086 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1087 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1088 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1089 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1091 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1092 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1093 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1094 NUM_BANKS(ADDR_SURF_2_BANK); 1095 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1096 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1099 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1100 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1101 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1102 NUM_BANKS(ADDR_SURF_2_BANK); 1103 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1104 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1105 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1107 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1108 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1109 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1110 NUM_BANKS(ADDR_SURF_2_BANK); 1111 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 1112 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1113 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1114 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1115 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1116 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1119 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1120 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1121 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1122 NUM_BANKS(ADDR_SURF_16_BANK); 1123 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1124 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1125 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1126 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1127 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1128 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1129 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1130 NUM_BANKS(ADDR_SURF_16_BANK); 1131 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1132 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1135 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1138 NUM_BANKS(ADDR_SURF_16_BANK); 1139 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1140 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1141 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1142 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1143 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1144 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1149 NUM_BANKS(ADDR_SURF_16_BANK); 1150 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1151 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1152 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1154 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1157 NUM_BANKS(ADDR_SURF_16_BANK); 1158 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1159 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1160 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1162 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1165 NUM_BANKS(ADDR_SURF_16_BANK); 1166 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1167 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1168 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1172 NUM_BANKS(ADDR_SURF_16_BANK) | 1173 TILE_SPLIT(split_equal_to_row_size); 1174 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1175 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1176 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1177 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1178 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1179 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1180 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1183 NUM_BANKS(ADDR_SURF_16_BANK) | 1184 TILE_SPLIT(split_equal_to_row_size); 1185 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1186 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1187 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1188 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1191 NUM_BANKS(ADDR_SURF_16_BANK) | 1192 TILE_SPLIT(split_equal_to_row_size); 1193 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1194 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1195 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1196 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1197 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1200 NUM_BANKS(ADDR_SURF_4_BANK); 1201 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1202 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1203 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1205 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1208 NUM_BANKS(ADDR_SURF_4_BANK); 1209 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1210 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1211 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1212 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1213 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1216 NUM_BANKS(ADDR_SURF_2_BANK); 1217 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1218 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1219 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1220 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1221 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1222 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1223 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1224 NUM_BANKS(ADDR_SURF_2_BANK); 1225 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1226 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1227 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1228 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1232 NUM_BANKS(ADDR_SURF_2_BANK); 1233 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1234 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1235 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1236 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1240 NUM_BANKS(ADDR_SURF_2_BANK); 1241 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1242 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1243 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1244 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1245 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1246 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1247 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1248 NUM_BANKS(ADDR_SURF_2_BANK); 1249 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1250 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1251 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1252 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1253 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1256 NUM_BANKS(ADDR_SURF_2_BANK); 1257 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1258 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1259 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1260 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1261 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1264 NUM_BANKS(ADDR_SURF_2_BANK); 1265 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1266 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1267 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1268 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1272 NUM_BANKS(ADDR_SURF_2_BANK); 1273 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1274 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1275 } else { 1276 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1277 } 1278 } 1279 1280 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1281 u32 sh_num, u32 instance) 1282 { 1283 u32 data; 1284 1285 if (instance == 0xffffffff) 1286 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1287 else 1288 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1289 1290 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1291 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1292 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1293 else if (se_num == 0xffffffff) 1294 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1295 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1296 else if (sh_num == 0xffffffff) 1297 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1298 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1299 else 1300 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1301 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1302 WREG32(mmGRBM_GFX_INDEX, data); 1303 } 1304 1305 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1306 { 1307 u32 data, mask; 1308 1309 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1310 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1311 1312 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1313 1314 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1315 adev->gfx.config.max_sh_per_se); 1316 1317 return ~data & mask; 1318 } 1319 1320 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1321 { 1322 switch (adev->asic_type) { 1323 case CHIP_TAHITI: 1324 case CHIP_PITCAIRN: 1325 *rconf |= 1326 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1327 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1328 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1329 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1330 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1331 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1332 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1333 break; 1334 case CHIP_VERDE: 1335 *rconf |= 1336 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1337 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1338 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1339 break; 1340 case CHIP_OLAND: 1341 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1342 break; 1343 case CHIP_HAINAN: 1344 *rconf |= 0x0; 1345 break; 1346 default: 1347 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1348 break; 1349 } 1350 } 1351 1352 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1353 u32 raster_config, unsigned rb_mask, 1354 unsigned num_rb) 1355 { 1356 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1357 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1358 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1359 unsigned rb_per_se = num_rb / num_se; 1360 unsigned se_mask[4]; 1361 unsigned se; 1362 1363 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1364 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1365 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1366 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1367 1368 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1369 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1370 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1371 1372 for (se = 0; se < num_se; se++) { 1373 unsigned raster_config_se = raster_config; 1374 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1375 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1376 int idx = (se / 2) * 2; 1377 1378 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1379 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1380 1381 if (!se_mask[idx]) 1382 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1383 else 1384 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1385 } 1386 1387 pkr0_mask &= rb_mask; 1388 pkr1_mask &= rb_mask; 1389 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1390 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1391 1392 if (!pkr0_mask) 1393 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1394 else 1395 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1396 } 1397 1398 if (rb_per_se >= 2) { 1399 unsigned rb0_mask = 1 << (se * rb_per_se); 1400 unsigned rb1_mask = rb0_mask << 1; 1401 1402 rb0_mask &= rb_mask; 1403 rb1_mask &= rb_mask; 1404 if (!rb0_mask || !rb1_mask) { 1405 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1406 1407 if (!rb0_mask) 1408 raster_config_se |= 1409 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1410 else 1411 raster_config_se |= 1412 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1413 } 1414 1415 if (rb_per_se > 2) { 1416 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1417 rb1_mask = rb0_mask << 1; 1418 rb0_mask &= rb_mask; 1419 rb1_mask &= rb_mask; 1420 if (!rb0_mask || !rb1_mask) { 1421 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1422 1423 if (!rb0_mask) 1424 raster_config_se |= 1425 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1426 else 1427 raster_config_se |= 1428 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1429 } 1430 } 1431 } 1432 1433 /* GRBM_GFX_INDEX has a different offset on SI */ 1434 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1435 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1436 } 1437 1438 /* GRBM_GFX_INDEX has a different offset on SI */ 1439 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1440 } 1441 1442 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1443 { 1444 int i, j; 1445 u32 data; 1446 u32 raster_config = 0; 1447 u32 active_rbs = 0; 1448 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1449 adev->gfx.config.max_sh_per_se; 1450 unsigned num_rb_pipes; 1451 1452 mutex_lock(&adev->grbm_idx_mutex); 1453 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1454 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1455 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1456 data = gfx_v6_0_get_rb_active_bitmap(adev); 1457 active_rbs |= data << 1458 ((i * adev->gfx.config.max_sh_per_se + j) * 1459 rb_bitmap_width_per_sh); 1460 } 1461 } 1462 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1463 1464 adev->gfx.config.backend_enable_mask = active_rbs; 1465 adev->gfx.config.num_rbs = hweight32(active_rbs); 1466 1467 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1468 adev->gfx.config.max_shader_engines, 16); 1469 1470 gfx_v6_0_raster_config(adev, &raster_config); 1471 1472 if (!adev->gfx.config.backend_enable_mask || 1473 adev->gfx.config.num_rbs >= num_rb_pipes) 1474 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1475 else 1476 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1477 adev->gfx.config.backend_enable_mask, 1478 num_rb_pipes); 1479 1480 /* cache the values for userspace */ 1481 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1482 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1483 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1484 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1485 RREG32(mmCC_RB_BACKEND_DISABLE); 1486 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1487 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1488 adev->gfx.config.rb_config[i][j].raster_config = 1489 RREG32(mmPA_SC_RASTER_CONFIG); 1490 } 1491 } 1492 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1493 mutex_unlock(&adev->grbm_idx_mutex); 1494 } 1495 1496 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1497 u32 bitmap) 1498 { 1499 u32 data; 1500 1501 if (!bitmap) 1502 return; 1503 1504 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1505 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1506 1507 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1508 } 1509 1510 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1511 { 1512 u32 data, mask; 1513 1514 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1515 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1516 1517 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1518 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1519 } 1520 1521 1522 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1523 { 1524 int i, j, k; 1525 u32 data, mask; 1526 u32 active_cu = 0; 1527 1528 mutex_lock(&adev->grbm_idx_mutex); 1529 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1530 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1531 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1532 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1533 active_cu = gfx_v6_0_get_cu_enabled(adev); 1534 1535 mask = 1; 1536 for (k = 0; k < 16; k++) { 1537 mask <<= k; 1538 if (active_cu & mask) { 1539 data &= ~mask; 1540 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1541 break; 1542 } 1543 } 1544 } 1545 } 1546 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1547 mutex_unlock(&adev->grbm_idx_mutex); 1548 } 1549 1550 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1551 { 1552 adev->gfx.config.double_offchip_lds_buf = 0; 1553 } 1554 1555 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) 1556 { 1557 u32 gb_addr_config = 0; 1558 u32 mc_shared_chmap, mc_arb_ramcfg; 1559 u32 sx_debug_1; 1560 u32 hdp_host_path_cntl; 1561 u32 tmp; 1562 1563 switch (adev->asic_type) { 1564 case CHIP_TAHITI: 1565 adev->gfx.config.max_shader_engines = 2; 1566 adev->gfx.config.max_tile_pipes = 12; 1567 adev->gfx.config.max_cu_per_sh = 8; 1568 adev->gfx.config.max_sh_per_se = 2; 1569 adev->gfx.config.max_backends_per_se = 4; 1570 adev->gfx.config.max_texture_channel_caches = 12; 1571 adev->gfx.config.max_gprs = 256; 1572 adev->gfx.config.max_gs_threads = 32; 1573 adev->gfx.config.max_hw_contexts = 8; 1574 1575 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1576 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1577 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1578 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1579 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1580 break; 1581 case CHIP_PITCAIRN: 1582 adev->gfx.config.max_shader_engines = 2; 1583 adev->gfx.config.max_tile_pipes = 8; 1584 adev->gfx.config.max_cu_per_sh = 5; 1585 adev->gfx.config.max_sh_per_se = 2; 1586 adev->gfx.config.max_backends_per_se = 4; 1587 adev->gfx.config.max_texture_channel_caches = 8; 1588 adev->gfx.config.max_gprs = 256; 1589 adev->gfx.config.max_gs_threads = 32; 1590 adev->gfx.config.max_hw_contexts = 8; 1591 1592 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1593 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1594 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1595 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1596 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1597 break; 1598 case CHIP_VERDE: 1599 adev->gfx.config.max_shader_engines = 1; 1600 adev->gfx.config.max_tile_pipes = 4; 1601 adev->gfx.config.max_cu_per_sh = 5; 1602 adev->gfx.config.max_sh_per_se = 2; 1603 adev->gfx.config.max_backends_per_se = 4; 1604 adev->gfx.config.max_texture_channel_caches = 4; 1605 adev->gfx.config.max_gprs = 256; 1606 adev->gfx.config.max_gs_threads = 32; 1607 adev->gfx.config.max_hw_contexts = 8; 1608 1609 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1610 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1611 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1612 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1613 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1614 break; 1615 case CHIP_OLAND: 1616 adev->gfx.config.max_shader_engines = 1; 1617 adev->gfx.config.max_tile_pipes = 4; 1618 adev->gfx.config.max_cu_per_sh = 6; 1619 adev->gfx.config.max_sh_per_se = 1; 1620 adev->gfx.config.max_backends_per_se = 2; 1621 adev->gfx.config.max_texture_channel_caches = 4; 1622 adev->gfx.config.max_gprs = 256; 1623 adev->gfx.config.max_gs_threads = 16; 1624 adev->gfx.config.max_hw_contexts = 8; 1625 1626 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1627 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1628 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1629 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1630 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1631 break; 1632 case CHIP_HAINAN: 1633 adev->gfx.config.max_shader_engines = 1; 1634 adev->gfx.config.max_tile_pipes = 4; 1635 adev->gfx.config.max_cu_per_sh = 5; 1636 adev->gfx.config.max_sh_per_se = 1; 1637 adev->gfx.config.max_backends_per_se = 1; 1638 adev->gfx.config.max_texture_channel_caches = 2; 1639 adev->gfx.config.max_gprs = 256; 1640 adev->gfx.config.max_gs_threads = 16; 1641 adev->gfx.config.max_hw_contexts = 8; 1642 1643 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1644 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1645 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1646 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1647 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1648 break; 1649 default: 1650 BUG(); 1651 break; 1652 } 1653 1654 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1655 WREG32(mmSRBM_INT_CNTL, 1); 1656 WREG32(mmSRBM_INT_ACK, 1); 1657 1658 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1659 1660 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 1661 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1662 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1663 1664 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1665 adev->gfx.config.mem_max_burst_length_bytes = 256; 1666 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1667 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1668 if (adev->gfx.config.mem_row_size_in_kb > 4) 1669 adev->gfx.config.mem_row_size_in_kb = 4; 1670 adev->gfx.config.shader_engine_tile_size = 32; 1671 adev->gfx.config.num_gpus = 1; 1672 adev->gfx.config.multi_gpu_tile_size = 64; 1673 1674 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1675 switch (adev->gfx.config.mem_row_size_in_kb) { 1676 case 1: 1677 default: 1678 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1679 break; 1680 case 2: 1681 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1682 break; 1683 case 4: 1684 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1685 break; 1686 } 1687 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1688 if (adev->gfx.config.max_shader_engines == 2) 1689 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1690 adev->gfx.config.gb_addr_config = gb_addr_config; 1691 1692 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1693 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1694 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1695 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1696 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1697 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1698 1699 #if 0 1700 if (adev->has_uvd) { 1701 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1702 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1703 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1704 } 1705 #endif 1706 gfx_v6_0_tiling_mode_table_init(adev); 1707 1708 gfx_v6_0_setup_rb(adev); 1709 1710 gfx_v6_0_setup_spi(adev); 1711 1712 gfx_v6_0_get_cu_info(adev); 1713 gfx_v6_0_config_init(adev); 1714 1715 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1716 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1717 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1718 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1719 1720 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1721 WREG32(mmSX_DEBUG_1, sx_debug_1); 1722 1723 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1724 1725 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1726 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1727 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1728 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1729 1730 WREG32(mmVGT_NUM_INSTANCES, 1); 1731 WREG32(mmCP_PERFMON_CNTL, 0); 1732 WREG32(mmSQ_CONFIG, 0); 1733 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1734 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1735 1736 WREG32(mmVGT_CACHE_INVALIDATION, 1737 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1738 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1739 1740 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1741 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1742 1743 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1744 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1745 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1746 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1747 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1748 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1749 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1750 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1751 1752 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1753 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1754 1755 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1756 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1757 1758 udelay(50); 1759 } 1760 1761 1762 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev) 1763 { 1764 adev->gfx.scratch.num_reg = 8; 1765 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 1766 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 1767 } 1768 1769 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1770 { 1771 struct amdgpu_device *adev = ring->adev; 1772 uint32_t scratch; 1773 uint32_t tmp = 0; 1774 unsigned i; 1775 int r; 1776 1777 r = amdgpu_gfx_scratch_get(adev, &scratch); 1778 if (r) { 1779 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 1780 return r; 1781 } 1782 WREG32(scratch, 0xCAFEDEAD); 1783 1784 r = amdgpu_ring_alloc(ring, 3); 1785 if (r) { 1786 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); 1787 amdgpu_gfx_scratch_free(adev, scratch); 1788 return r; 1789 } 1790 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1791 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); 1792 amdgpu_ring_write(ring, 0xDEADBEEF); 1793 amdgpu_ring_commit(ring); 1794 1795 for (i = 0; i < adev->usec_timeout; i++) { 1796 tmp = RREG32(scratch); 1797 if (tmp == 0xDEADBEEF) 1798 break; 1799 DRM_UDELAY(1); 1800 } 1801 if (i < adev->usec_timeout) { 1802 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 1803 } else { 1804 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 1805 ring->idx, scratch, tmp); 1806 r = -EINVAL; 1807 } 1808 amdgpu_gfx_scratch_free(adev, scratch); 1809 return r; 1810 } 1811 1812 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1813 { 1814 /* flush hdp cache */ 1815 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1816 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1817 WRITE_DATA_DST_SEL(0))); 1818 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1819 amdgpu_ring_write(ring, 0); 1820 amdgpu_ring_write(ring, 0x1); 1821 } 1822 1823 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1824 { 1825 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1826 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1827 EVENT_INDEX(0)); 1828 } 1829 1830 /** 1831 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 1832 * 1833 * @adev: amdgpu_device pointer 1834 * @ridx: amdgpu ring index 1835 * 1836 * Emits an hdp invalidate on the cp. 1837 */ 1838 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 1839 { 1840 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1841 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1842 WRITE_DATA_DST_SEL(0))); 1843 amdgpu_ring_write(ring, mmHDP_DEBUG0); 1844 amdgpu_ring_write(ring, 0); 1845 amdgpu_ring_write(ring, 0x1); 1846 } 1847 1848 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1849 u64 seq, unsigned flags) 1850 { 1851 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1852 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1853 /* flush read cache over gart */ 1854 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1855 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1856 amdgpu_ring_write(ring, 0); 1857 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1858 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1859 PACKET3_TC_ACTION_ENA | 1860 PACKET3_SH_KCACHE_ACTION_ENA | 1861 PACKET3_SH_ICACHE_ACTION_ENA); 1862 amdgpu_ring_write(ring, 0xFFFFFFFF); 1863 amdgpu_ring_write(ring, 0); 1864 amdgpu_ring_write(ring, 10); /* poll interval */ 1865 /* EVENT_WRITE_EOP - flush caches, send int */ 1866 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1867 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1868 amdgpu_ring_write(ring, addr & 0xfffffffc); 1869 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1870 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1871 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1872 amdgpu_ring_write(ring, lower_32_bits(seq)); 1873 amdgpu_ring_write(ring, upper_32_bits(seq)); 1874 } 1875 1876 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1877 struct amdgpu_ib *ib, 1878 unsigned vmid, bool ctx_switch) 1879 { 1880 u32 header, control = 0; 1881 1882 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1883 if (ctx_switch) { 1884 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1885 amdgpu_ring_write(ring, 0); 1886 } 1887 1888 if (ib->flags & AMDGPU_IB_FLAG_CE) 1889 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1890 else 1891 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1892 1893 control |= ib->length_dw | (vmid << 24); 1894 1895 amdgpu_ring_write(ring, header); 1896 amdgpu_ring_write(ring, 1897 #ifdef __BIG_ENDIAN 1898 (2 << 0) | 1899 #endif 1900 (ib->gpu_addr & 0xFFFFFFFC)); 1901 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1902 amdgpu_ring_write(ring, control); 1903 } 1904 1905 /** 1906 * gfx_v6_0_ring_test_ib - basic ring IB test 1907 * 1908 * @ring: amdgpu_ring structure holding ring information 1909 * 1910 * Allocate an IB and execute it on the gfx ring (SI). 1911 * Provides a basic gfx ring test to verify that IBs are working. 1912 * Returns 0 on success, error on failure. 1913 */ 1914 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1915 { 1916 struct amdgpu_device *adev = ring->adev; 1917 struct amdgpu_ib ib; 1918 struct dma_fence *f = NULL; 1919 uint32_t scratch; 1920 uint32_t tmp = 0; 1921 long r; 1922 1923 r = amdgpu_gfx_scratch_get(adev, &scratch); 1924 if (r) { 1925 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 1926 return r; 1927 } 1928 WREG32(scratch, 0xCAFEDEAD); 1929 memset(&ib, 0, sizeof(ib)); 1930 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1931 if (r) { 1932 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1933 goto err1; 1934 } 1935 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1936 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START)); 1937 ib.ptr[2] = 0xDEADBEEF; 1938 ib.length_dw = 3; 1939 1940 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1941 if (r) 1942 goto err2; 1943 1944 r = dma_fence_wait_timeout(f, false, timeout); 1945 if (r == 0) { 1946 DRM_ERROR("amdgpu: IB test timed out\n"); 1947 r = -ETIMEDOUT; 1948 goto err2; 1949 } else if (r < 0) { 1950 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1951 goto err2; 1952 } 1953 tmp = RREG32(scratch); 1954 if (tmp == 0xDEADBEEF) { 1955 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 1956 r = 0; 1957 } else { 1958 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 1959 scratch, tmp); 1960 r = -EINVAL; 1961 } 1962 1963 err2: 1964 amdgpu_ib_free(adev, &ib, NULL); 1965 dma_fence_put(f); 1966 err1: 1967 amdgpu_gfx_scratch_free(adev, scratch); 1968 return r; 1969 } 1970 1971 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1972 { 1973 int i; 1974 if (enable) { 1975 WREG32(mmCP_ME_CNTL, 0); 1976 } else { 1977 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 1978 CP_ME_CNTL__PFP_HALT_MASK | 1979 CP_ME_CNTL__CE_HALT_MASK)); 1980 WREG32(mmSCRATCH_UMSK, 0); 1981 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1982 adev->gfx.gfx_ring[i].ready = false; 1983 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1984 adev->gfx.compute_ring[i].ready = false; 1985 } 1986 udelay(50); 1987 } 1988 1989 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 1990 { 1991 unsigned i; 1992 const struct gfx_firmware_header_v1_0 *pfp_hdr; 1993 const struct gfx_firmware_header_v1_0 *ce_hdr; 1994 const struct gfx_firmware_header_v1_0 *me_hdr; 1995 const __le32 *fw_data; 1996 u32 fw_size; 1997 1998 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 1999 return -EINVAL; 2000 2001 gfx_v6_0_cp_gfx_enable(adev, false); 2002 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2003 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2004 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2005 2006 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2007 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2008 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2009 2010 /* PFP */ 2011 fw_data = (const __le32 *) 2012 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2013 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2014 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2015 for (i = 0; i < fw_size; i++) 2016 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2017 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2018 2019 /* CE */ 2020 fw_data = (const __le32 *) 2021 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2022 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2023 WREG32(mmCP_CE_UCODE_ADDR, 0); 2024 for (i = 0; i < fw_size; i++) 2025 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2026 WREG32(mmCP_CE_UCODE_ADDR, 0); 2027 2028 /* ME */ 2029 fw_data = (const __be32 *) 2030 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2031 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2032 WREG32(mmCP_ME_RAM_WADDR, 0); 2033 for (i = 0; i < fw_size; i++) 2034 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2035 WREG32(mmCP_ME_RAM_WADDR, 0); 2036 2037 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2038 WREG32(mmCP_CE_UCODE_ADDR, 0); 2039 WREG32(mmCP_ME_RAM_WADDR, 0); 2040 WREG32(mmCP_ME_RAM_RADDR, 0); 2041 return 0; 2042 } 2043 2044 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 2045 { 2046 const struct cs_section_def *sect = NULL; 2047 const struct cs_extent_def *ext = NULL; 2048 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2049 int r, i; 2050 2051 r = amdgpu_ring_alloc(ring, 7 + 4); 2052 if (r) { 2053 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2054 return r; 2055 } 2056 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2057 amdgpu_ring_write(ring, 0x1); 2058 amdgpu_ring_write(ring, 0x0); 2059 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 2060 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2061 amdgpu_ring_write(ring, 0); 2062 amdgpu_ring_write(ring, 0); 2063 2064 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2065 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2066 amdgpu_ring_write(ring, 0xc000); 2067 amdgpu_ring_write(ring, 0xe000); 2068 amdgpu_ring_commit(ring); 2069 2070 gfx_v6_0_cp_gfx_enable(adev, true); 2071 2072 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2073 if (r) { 2074 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2075 return r; 2076 } 2077 2078 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2079 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2080 2081 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2082 for (ext = sect->section; ext->extent != NULL; ++ext) { 2083 if (sect->id == SECT_CONTEXT) { 2084 amdgpu_ring_write(ring, 2085 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2086 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2087 for (i = 0; i < ext->reg_count; i++) 2088 amdgpu_ring_write(ring, ext->extent[i]); 2089 } 2090 } 2091 } 2092 2093 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2094 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2095 2096 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2097 amdgpu_ring_write(ring, 0); 2098 2099 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2100 amdgpu_ring_write(ring, 0x00000316); 2101 amdgpu_ring_write(ring, 0x0000000e); 2102 amdgpu_ring_write(ring, 0x00000010); 2103 2104 amdgpu_ring_commit(ring); 2105 2106 return 0; 2107 } 2108 2109 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2110 { 2111 struct amdgpu_ring *ring; 2112 u32 tmp; 2113 u32 rb_bufsz; 2114 int r; 2115 u64 rptr_addr; 2116 2117 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2118 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2119 2120 /* Set the write pointer delay */ 2121 WREG32(mmCP_RB_WPTR_DELAY, 0); 2122 2123 WREG32(mmCP_DEBUG, 0); 2124 WREG32(mmSCRATCH_ADDR, 0); 2125 2126 /* ring 0 - compute and gfx */ 2127 /* Set ring buffer size */ 2128 ring = &adev->gfx.gfx_ring[0]; 2129 rb_bufsz = order_base_2(ring->ring_size / 8); 2130 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2131 2132 #ifdef __BIG_ENDIAN 2133 tmp |= BUF_SWAP_32BIT; 2134 #endif 2135 WREG32(mmCP_RB0_CNTL, tmp); 2136 2137 /* Initialize the ring buffer's read and write pointers */ 2138 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2139 ring->wptr = 0; 2140 WREG32(mmCP_RB0_WPTR, ring->wptr); 2141 2142 /* set the wb address whether it's enabled or not */ 2143 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2144 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2145 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2146 2147 WREG32(mmSCRATCH_UMSK, 0); 2148 2149 mdelay(1); 2150 WREG32(mmCP_RB0_CNTL, tmp); 2151 2152 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2153 2154 /* start the rings */ 2155 gfx_v6_0_cp_gfx_start(adev); 2156 ring->ready = true; 2157 r = amdgpu_ring_test_ring(ring); 2158 if (r) { 2159 ring->ready = false; 2160 return r; 2161 } 2162 2163 return 0; 2164 } 2165 2166 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2167 { 2168 return ring->adev->wb.wb[ring->rptr_offs]; 2169 } 2170 2171 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2172 { 2173 struct amdgpu_device *adev = ring->adev; 2174 2175 if (ring == &adev->gfx.gfx_ring[0]) 2176 return RREG32(mmCP_RB0_WPTR); 2177 else if (ring == &adev->gfx.compute_ring[0]) 2178 return RREG32(mmCP_RB1_WPTR); 2179 else if (ring == &adev->gfx.compute_ring[1]) 2180 return RREG32(mmCP_RB2_WPTR); 2181 else 2182 BUG(); 2183 } 2184 2185 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2186 { 2187 struct amdgpu_device *adev = ring->adev; 2188 2189 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2190 (void)RREG32(mmCP_RB0_WPTR); 2191 } 2192 2193 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2194 { 2195 struct amdgpu_device *adev = ring->adev; 2196 2197 if (ring == &adev->gfx.compute_ring[0]) { 2198 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2199 (void)RREG32(mmCP_RB1_WPTR); 2200 } else if (ring == &adev->gfx.compute_ring[1]) { 2201 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2202 (void)RREG32(mmCP_RB2_WPTR); 2203 } else { 2204 BUG(); 2205 } 2206 2207 } 2208 2209 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 2210 { 2211 struct amdgpu_ring *ring; 2212 u32 tmp; 2213 u32 rb_bufsz; 2214 int i, r; 2215 u64 rptr_addr; 2216 2217 /* ring1 - compute only */ 2218 /* Set ring buffer size */ 2219 2220 ring = &adev->gfx.compute_ring[0]; 2221 rb_bufsz = order_base_2(ring->ring_size / 8); 2222 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2223 #ifdef __BIG_ENDIAN 2224 tmp |= BUF_SWAP_32BIT; 2225 #endif 2226 WREG32(mmCP_RB1_CNTL, tmp); 2227 2228 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2229 ring->wptr = 0; 2230 WREG32(mmCP_RB1_WPTR, ring->wptr); 2231 2232 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2233 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2234 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2235 2236 mdelay(1); 2237 WREG32(mmCP_RB1_CNTL, tmp); 2238 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2239 2240 ring = &adev->gfx.compute_ring[1]; 2241 rb_bufsz = order_base_2(ring->ring_size / 8); 2242 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2243 #ifdef __BIG_ENDIAN 2244 tmp |= BUF_SWAP_32BIT; 2245 #endif 2246 WREG32(mmCP_RB2_CNTL, tmp); 2247 2248 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2249 ring->wptr = 0; 2250 WREG32(mmCP_RB2_WPTR, ring->wptr); 2251 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2252 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2253 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2254 2255 mdelay(1); 2256 WREG32(mmCP_RB2_CNTL, tmp); 2257 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2258 2259 adev->gfx.compute_ring[0].ready = false; 2260 adev->gfx.compute_ring[1].ready = false; 2261 2262 for (i = 0; i < 2; i++) { 2263 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]); 2264 if (r) 2265 return r; 2266 adev->gfx.compute_ring[i].ready = true; 2267 } 2268 2269 return 0; 2270 } 2271 2272 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2273 { 2274 gfx_v6_0_cp_gfx_enable(adev, enable); 2275 } 2276 2277 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2278 { 2279 return gfx_v6_0_cp_gfx_load_microcode(adev); 2280 } 2281 2282 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2283 bool enable) 2284 { 2285 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2286 u32 mask; 2287 int i; 2288 2289 if (enable) 2290 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2291 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2292 else 2293 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2294 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2295 WREG32(mmCP_INT_CNTL_RING0, tmp); 2296 2297 if (!enable) { 2298 /* read a gfx register */ 2299 tmp = RREG32(mmDB_DEPTH_INFO); 2300 2301 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2302 for (i = 0; i < adev->usec_timeout; i++) { 2303 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2304 break; 2305 udelay(1); 2306 } 2307 } 2308 } 2309 2310 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2311 { 2312 int r; 2313 2314 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2315 2316 r = gfx_v6_0_cp_load_microcode(adev); 2317 if (r) 2318 return r; 2319 2320 r = gfx_v6_0_cp_gfx_resume(adev); 2321 if (r) 2322 return r; 2323 r = gfx_v6_0_cp_compute_resume(adev); 2324 if (r) 2325 return r; 2326 2327 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2328 2329 return 0; 2330 } 2331 2332 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2333 { 2334 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2335 uint32_t seq = ring->fence_drv.sync_seq; 2336 uint64_t addr = ring->fence_drv.gpu_addr; 2337 2338 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2339 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2340 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2341 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2342 amdgpu_ring_write(ring, addr & 0xfffffffc); 2343 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2344 amdgpu_ring_write(ring, seq); 2345 amdgpu_ring_write(ring, 0xffffffff); 2346 amdgpu_ring_write(ring, 4); /* poll interval */ 2347 2348 if (usepfp) { 2349 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2350 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2351 amdgpu_ring_write(ring, 0); 2352 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2353 amdgpu_ring_write(ring, 0); 2354 } 2355 } 2356 2357 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2358 unsigned vmid, unsigned pasid, 2359 uint64_t pd_addr) 2360 { 2361 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2362 2363 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr); 2364 2365 /* wait for the invalidate to complete */ 2366 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2367 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2368 WAIT_REG_MEM_ENGINE(0))); /* me */ 2369 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2370 amdgpu_ring_write(ring, 0); 2371 amdgpu_ring_write(ring, 0); /* ref */ 2372 amdgpu_ring_write(ring, 0); /* mask */ 2373 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2374 2375 if (usepfp) { 2376 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2377 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2378 amdgpu_ring_write(ring, 0x0); 2379 2380 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2381 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2382 amdgpu_ring_write(ring, 0); 2383 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2384 amdgpu_ring_write(ring, 0); 2385 } 2386 } 2387 2388 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 2389 uint32_t reg, uint32_t val) 2390 { 2391 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2392 2393 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2394 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 2395 WRITE_DATA_DST_SEL(0))); 2396 amdgpu_ring_write(ring, reg); 2397 amdgpu_ring_write(ring, 0); 2398 amdgpu_ring_write(ring, val); 2399 } 2400 2401 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev) 2402 { 2403 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); 2404 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); 2405 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); 2406 } 2407 2408 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2409 { 2410 const u32 *src_ptr; 2411 volatile u32 *dst_ptr; 2412 u32 dws, i; 2413 u64 reg_list_mc_addr; 2414 const struct cs_section_def *cs_data; 2415 int r; 2416 2417 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2418 adev->gfx.rlc.reg_list_size = 2419 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2420 2421 adev->gfx.rlc.cs_data = si_cs_data; 2422 src_ptr = adev->gfx.rlc.reg_list; 2423 dws = adev->gfx.rlc.reg_list_size; 2424 cs_data = adev->gfx.rlc.cs_data; 2425 2426 if (src_ptr) { 2427 /* save restore block */ 2428 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2429 AMDGPU_GEM_DOMAIN_VRAM, 2430 &adev->gfx.rlc.save_restore_obj, 2431 &adev->gfx.rlc.save_restore_gpu_addr, 2432 (void **)&adev->gfx.rlc.sr_ptr); 2433 if (r) { 2434 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", 2435 r); 2436 gfx_v6_0_rlc_fini(adev); 2437 return r; 2438 } 2439 2440 /* write the sr buffer */ 2441 dst_ptr = adev->gfx.rlc.sr_ptr; 2442 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 2443 dst_ptr[i] = cpu_to_le32(src_ptr[i]); 2444 2445 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); 2446 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 2447 } 2448 2449 if (cs_data) { 2450 /* clear state block */ 2451 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2452 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2453 2454 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2455 AMDGPU_GEM_DOMAIN_VRAM, 2456 &adev->gfx.rlc.clear_state_obj, 2457 &adev->gfx.rlc.clear_state_gpu_addr, 2458 (void **)&adev->gfx.rlc.cs_ptr); 2459 if (r) { 2460 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2461 gfx_v6_0_rlc_fini(adev); 2462 return r; 2463 } 2464 2465 /* set up the cs buffer */ 2466 dst_ptr = adev->gfx.rlc.cs_ptr; 2467 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2468 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2469 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2470 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2471 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2472 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2473 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2474 } 2475 2476 return 0; 2477 } 2478 2479 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2480 { 2481 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2482 2483 if (!enable) { 2484 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2485 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2486 } 2487 } 2488 2489 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2490 { 2491 int i; 2492 2493 for (i = 0; i < adev->usec_timeout; i++) { 2494 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2495 break; 2496 udelay(1); 2497 } 2498 2499 for (i = 0; i < adev->usec_timeout; i++) { 2500 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2501 break; 2502 udelay(1); 2503 } 2504 } 2505 2506 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2507 { 2508 u32 tmp; 2509 2510 tmp = RREG32(mmRLC_CNTL); 2511 if (tmp != rlc) 2512 WREG32(mmRLC_CNTL, rlc); 2513 } 2514 2515 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2516 { 2517 u32 data, orig; 2518 2519 orig = data = RREG32(mmRLC_CNTL); 2520 2521 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2522 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2523 WREG32(mmRLC_CNTL, data); 2524 2525 gfx_v6_0_wait_for_rlc_serdes(adev); 2526 } 2527 2528 return orig; 2529 } 2530 2531 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2532 { 2533 WREG32(mmRLC_CNTL, 0); 2534 2535 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2536 gfx_v6_0_wait_for_rlc_serdes(adev); 2537 } 2538 2539 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2540 { 2541 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2542 2543 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2544 2545 udelay(50); 2546 } 2547 2548 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2549 { 2550 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2551 udelay(50); 2552 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2553 udelay(50); 2554 } 2555 2556 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2557 { 2558 u32 tmp; 2559 2560 /* Enable LBPW only for DDR3 */ 2561 tmp = RREG32(mmMC_SEQ_MISC0); 2562 if ((tmp & 0xF0000000) == 0xB0000000) 2563 return true; 2564 return false; 2565 } 2566 2567 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2568 { 2569 } 2570 2571 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2572 { 2573 u32 i; 2574 const struct rlc_firmware_header_v1_0 *hdr; 2575 const __le32 *fw_data; 2576 u32 fw_size; 2577 2578 2579 if (!adev->gfx.rlc_fw) 2580 return -EINVAL; 2581 2582 gfx_v6_0_rlc_stop(adev); 2583 gfx_v6_0_rlc_reset(adev); 2584 gfx_v6_0_init_pg(adev); 2585 gfx_v6_0_init_cg(adev); 2586 2587 WREG32(mmRLC_RL_BASE, 0); 2588 WREG32(mmRLC_RL_SIZE, 0); 2589 WREG32(mmRLC_LB_CNTL, 0); 2590 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2591 WREG32(mmRLC_LB_CNTR_INIT, 0); 2592 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2593 2594 WREG32(mmRLC_MC_CNTL, 0); 2595 WREG32(mmRLC_UCODE_CNTL, 0); 2596 2597 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2598 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2599 fw_data = (const __le32 *) 2600 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2601 2602 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2603 2604 for (i = 0; i < fw_size; i++) { 2605 WREG32(mmRLC_UCODE_ADDR, i); 2606 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2607 } 2608 WREG32(mmRLC_UCODE_ADDR, 0); 2609 2610 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2611 gfx_v6_0_rlc_start(adev); 2612 2613 return 0; 2614 } 2615 2616 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2617 { 2618 u32 data, orig, tmp; 2619 2620 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2621 2622 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2623 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2624 2625 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2626 2627 tmp = gfx_v6_0_halt_rlc(adev); 2628 2629 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2630 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2631 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2632 2633 gfx_v6_0_wait_for_rlc_serdes(adev); 2634 gfx_v6_0_update_rlc(adev, tmp); 2635 2636 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2637 2638 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2639 } else { 2640 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2641 2642 RREG32(mmCB_CGTT_SCLK_CTRL); 2643 RREG32(mmCB_CGTT_SCLK_CTRL); 2644 RREG32(mmCB_CGTT_SCLK_CTRL); 2645 RREG32(mmCB_CGTT_SCLK_CTRL); 2646 2647 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2648 } 2649 2650 if (orig != data) 2651 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2652 2653 } 2654 2655 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2656 { 2657 2658 u32 data, orig, tmp = 0; 2659 2660 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2661 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2662 data = 0x96940200; 2663 if (orig != data) 2664 WREG32(mmCGTS_SM_CTRL_REG, data); 2665 2666 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2667 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2668 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2669 if (orig != data) 2670 WREG32(mmCP_MEM_SLP_CNTL, data); 2671 } 2672 2673 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2674 data &= 0xffffffc0; 2675 if (orig != data) 2676 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2677 2678 tmp = gfx_v6_0_halt_rlc(adev); 2679 2680 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2681 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2682 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2683 2684 gfx_v6_0_update_rlc(adev, tmp); 2685 } else { 2686 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2687 data |= 0x00000003; 2688 if (orig != data) 2689 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2690 2691 data = RREG32(mmCP_MEM_SLP_CNTL); 2692 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2693 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2694 WREG32(mmCP_MEM_SLP_CNTL, data); 2695 } 2696 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2697 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2698 if (orig != data) 2699 WREG32(mmCGTS_SM_CTRL_REG, data); 2700 2701 tmp = gfx_v6_0_halt_rlc(adev); 2702 2703 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2704 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2705 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2706 2707 gfx_v6_0_update_rlc(adev, tmp); 2708 } 2709 } 2710 /* 2711 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2712 bool enable) 2713 { 2714 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2715 if (enable) { 2716 gfx_v6_0_enable_mgcg(adev, true); 2717 gfx_v6_0_enable_cgcg(adev, true); 2718 } else { 2719 gfx_v6_0_enable_cgcg(adev, false); 2720 gfx_v6_0_enable_mgcg(adev, false); 2721 } 2722 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2723 } 2724 */ 2725 2726 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2727 bool enable) 2728 { 2729 } 2730 2731 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2732 bool enable) 2733 { 2734 } 2735 2736 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2737 { 2738 u32 data, orig; 2739 2740 orig = data = RREG32(mmRLC_PG_CNTL); 2741 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2742 data &= ~0x8000; 2743 else 2744 data |= 0x8000; 2745 if (orig != data) 2746 WREG32(mmRLC_PG_CNTL, data); 2747 } 2748 2749 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2750 { 2751 } 2752 /* 2753 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2754 { 2755 const __le32 *fw_data; 2756 volatile u32 *dst_ptr; 2757 int me, i, max_me = 4; 2758 u32 bo_offset = 0; 2759 u32 table_offset, table_size; 2760 2761 if (adev->asic_type == CHIP_KAVERI) 2762 max_me = 5; 2763 2764 if (adev->gfx.rlc.cp_table_ptr == NULL) 2765 return; 2766 2767 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2768 for (me = 0; me < max_me; me++) { 2769 if (me == 0) { 2770 const struct gfx_firmware_header_v1_0 *hdr = 2771 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2772 fw_data = (const __le32 *) 2773 (adev->gfx.ce_fw->data + 2774 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2775 table_offset = le32_to_cpu(hdr->jt_offset); 2776 table_size = le32_to_cpu(hdr->jt_size); 2777 } else if (me == 1) { 2778 const struct gfx_firmware_header_v1_0 *hdr = 2779 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2780 fw_data = (const __le32 *) 2781 (adev->gfx.pfp_fw->data + 2782 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2783 table_offset = le32_to_cpu(hdr->jt_offset); 2784 table_size = le32_to_cpu(hdr->jt_size); 2785 } else if (me == 2) { 2786 const struct gfx_firmware_header_v1_0 *hdr = 2787 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2788 fw_data = (const __le32 *) 2789 (adev->gfx.me_fw->data + 2790 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2791 table_offset = le32_to_cpu(hdr->jt_offset); 2792 table_size = le32_to_cpu(hdr->jt_size); 2793 } else if (me == 3) { 2794 const struct gfx_firmware_header_v1_0 *hdr = 2795 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2796 fw_data = (const __le32 *) 2797 (adev->gfx.mec_fw->data + 2798 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2799 table_offset = le32_to_cpu(hdr->jt_offset); 2800 table_size = le32_to_cpu(hdr->jt_size); 2801 } else { 2802 const struct gfx_firmware_header_v1_0 *hdr = 2803 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2804 fw_data = (const __le32 *) 2805 (adev->gfx.mec2_fw->data + 2806 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2807 table_offset = le32_to_cpu(hdr->jt_offset); 2808 table_size = le32_to_cpu(hdr->jt_size); 2809 } 2810 2811 for (i = 0; i < table_size; i ++) { 2812 dst_ptr[bo_offset + i] = 2813 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2814 } 2815 2816 bo_offset += table_size; 2817 } 2818 } 2819 */ 2820 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2821 bool enable) 2822 { 2823 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2824 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2825 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2826 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2827 } else { 2828 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2829 (void)RREG32(mmDB_RENDER_CONTROL); 2830 } 2831 } 2832 2833 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2834 { 2835 u32 tmp; 2836 2837 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2838 2839 tmp = RREG32(mmRLC_MAX_PG_CU); 2840 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2841 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2842 WREG32(mmRLC_MAX_PG_CU, tmp); 2843 } 2844 2845 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2846 bool enable) 2847 { 2848 u32 data, orig; 2849 2850 orig = data = RREG32(mmRLC_PG_CNTL); 2851 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2852 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2853 else 2854 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2855 if (orig != data) 2856 WREG32(mmRLC_PG_CNTL, data); 2857 } 2858 2859 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2860 bool enable) 2861 { 2862 u32 data, orig; 2863 2864 orig = data = RREG32(mmRLC_PG_CNTL); 2865 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2866 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2867 else 2868 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2869 if (orig != data) 2870 WREG32(mmRLC_PG_CNTL, data); 2871 } 2872 2873 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2874 { 2875 u32 tmp; 2876 2877 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2878 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2879 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2880 2881 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2882 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2883 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2884 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2885 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2886 } 2887 2888 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2889 { 2890 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2891 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2892 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2893 } 2894 2895 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2896 { 2897 u32 count = 0; 2898 const struct cs_section_def *sect = NULL; 2899 const struct cs_extent_def *ext = NULL; 2900 2901 if (adev->gfx.rlc.cs_data == NULL) 2902 return 0; 2903 2904 /* begin clear state */ 2905 count += 2; 2906 /* context control state */ 2907 count += 3; 2908 2909 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2910 for (ext = sect->section; ext->extent != NULL; ++ext) { 2911 if (sect->id == SECT_CONTEXT) 2912 count += 2 + ext->reg_count; 2913 else 2914 return 0; 2915 } 2916 } 2917 /* pa_sc_raster_config */ 2918 count += 3; 2919 /* end clear state */ 2920 count += 2; 2921 /* clear state */ 2922 count += 2; 2923 2924 return count; 2925 } 2926 2927 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 2928 volatile u32 *buffer) 2929 { 2930 u32 count = 0, i; 2931 const struct cs_section_def *sect = NULL; 2932 const struct cs_extent_def *ext = NULL; 2933 2934 if (adev->gfx.rlc.cs_data == NULL) 2935 return; 2936 if (buffer == NULL) 2937 return; 2938 2939 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2940 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2941 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2942 buffer[count++] = cpu_to_le32(0x80000000); 2943 buffer[count++] = cpu_to_le32(0x80000000); 2944 2945 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2946 for (ext = sect->section; ext->extent != NULL; ++ext) { 2947 if (sect->id == SECT_CONTEXT) { 2948 buffer[count++] = 2949 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2950 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); 2951 for (i = 0; i < ext->reg_count; i++) 2952 buffer[count++] = cpu_to_le32(ext->extent[i]); 2953 } else { 2954 return; 2955 } 2956 } 2957 } 2958 2959 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2960 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2961 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 2962 2963 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2964 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 2965 2966 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 2967 buffer[count++] = cpu_to_le32(0); 2968 } 2969 2970 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2971 { 2972 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2973 AMD_PG_SUPPORT_GFX_SMG | 2974 AMD_PG_SUPPORT_GFX_DMG | 2975 AMD_PG_SUPPORT_CP | 2976 AMD_PG_SUPPORT_GDS | 2977 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2978 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2979 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2980 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2981 gfx_v6_0_init_gfx_cgpg(adev); 2982 gfx_v6_0_enable_cp_pg(adev, true); 2983 gfx_v6_0_enable_gds_pg(adev, true); 2984 } else { 2985 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2986 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2987 2988 } 2989 gfx_v6_0_init_ao_cu_mask(adev); 2990 gfx_v6_0_update_gfx_pg(adev, true); 2991 } else { 2992 2993 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2994 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2995 } 2996 } 2997 2998 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 2999 { 3000 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3001 AMD_PG_SUPPORT_GFX_SMG | 3002 AMD_PG_SUPPORT_GFX_DMG | 3003 AMD_PG_SUPPORT_CP | 3004 AMD_PG_SUPPORT_GDS | 3005 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3006 gfx_v6_0_update_gfx_pg(adev, false); 3007 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3008 gfx_v6_0_enable_cp_pg(adev, false); 3009 gfx_v6_0_enable_gds_pg(adev, false); 3010 } 3011 } 3012 } 3013 3014 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3015 { 3016 uint64_t clock; 3017 3018 mutex_lock(&adev->gfx.gpu_clock_mutex); 3019 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3020 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 3021 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3022 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3023 return clock; 3024 } 3025 3026 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 3027 { 3028 if (flags & AMDGPU_HAVE_CTX_SWITCH) 3029 gfx_v6_0_ring_emit_vgt_flush(ring); 3030 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3031 amdgpu_ring_write(ring, 0x80000000); 3032 amdgpu_ring_write(ring, 0); 3033 } 3034 3035 3036 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 3037 { 3038 WREG32(mmSQ_IND_INDEX, 3039 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3040 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3041 (address << SQ_IND_INDEX__INDEX__SHIFT) | 3042 (SQ_IND_INDEX__FORCE_READ_MASK)); 3043 return RREG32(mmSQ_IND_DATA); 3044 } 3045 3046 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 3047 uint32_t wave, uint32_t thread, 3048 uint32_t regno, uint32_t num, uint32_t *out) 3049 { 3050 WREG32(mmSQ_IND_INDEX, 3051 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3052 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3053 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 3054 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 3055 (SQ_IND_INDEX__FORCE_READ_MASK) | 3056 (SQ_IND_INDEX__AUTO_INCR_MASK)); 3057 while (num--) 3058 *(out++) = RREG32(mmSQ_IND_DATA); 3059 } 3060 3061 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 3062 { 3063 /* type 0 wave data */ 3064 dst[(*no_fields)++] = 0; 3065 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 3066 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 3067 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 3068 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 3069 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 3070 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 3071 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 3072 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 3073 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 3074 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 3075 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 3076 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 3077 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 3078 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 3079 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 3080 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 3081 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 3082 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 3083 } 3084 3085 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 3086 uint32_t wave, uint32_t start, 3087 uint32_t size, uint32_t *dst) 3088 { 3089 wave_read_regs( 3090 adev, simd, wave, 0, 3091 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3092 } 3093 3094 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3095 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3096 .select_se_sh = &gfx_v6_0_select_se_sh, 3097 .read_wave_data = &gfx_v6_0_read_wave_data, 3098 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3099 }; 3100 3101 static int gfx_v6_0_early_init(void *handle) 3102 { 3103 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3104 3105 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3106 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS; 3107 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3108 gfx_v6_0_set_ring_funcs(adev); 3109 gfx_v6_0_set_irq_funcs(adev); 3110 3111 return 0; 3112 } 3113 3114 static int gfx_v6_0_sw_init(void *handle) 3115 { 3116 struct amdgpu_ring *ring; 3117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3118 int i, r; 3119 3120 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3121 if (r) 3122 return r; 3123 3124 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3125 if (r) 3126 return r; 3127 3128 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3129 if (r) 3130 return r; 3131 3132 gfx_v6_0_scratch_init(adev); 3133 3134 r = gfx_v6_0_init_microcode(adev); 3135 if (r) { 3136 DRM_ERROR("Failed to load gfx firmware!\n"); 3137 return r; 3138 } 3139 3140 r = gfx_v6_0_rlc_init(adev); 3141 if (r) { 3142 DRM_ERROR("Failed to init rlc BOs!\n"); 3143 return r; 3144 } 3145 3146 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3147 ring = &adev->gfx.gfx_ring[i]; 3148 ring->ring_obj = NULL; 3149 sprintf(ring->name, "gfx"); 3150 r = amdgpu_ring_init(adev, ring, 1024, 3151 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 3152 if (r) 3153 return r; 3154 } 3155 3156 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3157 unsigned irq_type; 3158 3159 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3160 DRM_ERROR("Too many (%d) compute rings!\n", i); 3161 break; 3162 } 3163 ring = &adev->gfx.compute_ring[i]; 3164 ring->ring_obj = NULL; 3165 ring->use_doorbell = false; 3166 ring->doorbell_index = 0; 3167 ring->me = 1; 3168 ring->pipe = i; 3169 ring->queue = i; 3170 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3171 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3172 r = amdgpu_ring_init(adev, ring, 1024, 3173 &adev->gfx.eop_irq, irq_type); 3174 if (r) 3175 return r; 3176 } 3177 3178 return r; 3179 } 3180 3181 static int gfx_v6_0_sw_fini(void *handle) 3182 { 3183 int i; 3184 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3185 3186 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3187 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3188 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3189 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3190 3191 gfx_v6_0_rlc_fini(adev); 3192 3193 return 0; 3194 } 3195 3196 static int gfx_v6_0_hw_init(void *handle) 3197 { 3198 int r; 3199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3200 3201 gfx_v6_0_gpu_init(adev); 3202 3203 r = gfx_v6_0_rlc_resume(adev); 3204 if (r) 3205 return r; 3206 3207 r = gfx_v6_0_cp_resume(adev); 3208 if (r) 3209 return r; 3210 3211 adev->gfx.ce_ram_size = 0x8000; 3212 3213 return r; 3214 } 3215 3216 static int gfx_v6_0_hw_fini(void *handle) 3217 { 3218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3219 3220 gfx_v6_0_cp_enable(adev, false); 3221 gfx_v6_0_rlc_stop(adev); 3222 gfx_v6_0_fini_pg(adev); 3223 3224 return 0; 3225 } 3226 3227 static int gfx_v6_0_suspend(void *handle) 3228 { 3229 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3230 3231 return gfx_v6_0_hw_fini(adev); 3232 } 3233 3234 static int gfx_v6_0_resume(void *handle) 3235 { 3236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3237 3238 return gfx_v6_0_hw_init(adev); 3239 } 3240 3241 static bool gfx_v6_0_is_idle(void *handle) 3242 { 3243 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3244 3245 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3246 return false; 3247 else 3248 return true; 3249 } 3250 3251 static int gfx_v6_0_wait_for_idle(void *handle) 3252 { 3253 unsigned i; 3254 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3255 3256 for (i = 0; i < adev->usec_timeout; i++) { 3257 if (gfx_v6_0_is_idle(handle)) 3258 return 0; 3259 udelay(1); 3260 } 3261 return -ETIMEDOUT; 3262 } 3263 3264 static int gfx_v6_0_soft_reset(void *handle) 3265 { 3266 return 0; 3267 } 3268 3269 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3270 enum amdgpu_interrupt_state state) 3271 { 3272 u32 cp_int_cntl; 3273 3274 switch (state) { 3275 case AMDGPU_IRQ_STATE_DISABLE: 3276 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3277 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3278 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3279 break; 3280 case AMDGPU_IRQ_STATE_ENABLE: 3281 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3282 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3283 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3284 break; 3285 default: 3286 break; 3287 } 3288 } 3289 3290 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3291 int ring, 3292 enum amdgpu_interrupt_state state) 3293 { 3294 u32 cp_int_cntl; 3295 switch (state){ 3296 case AMDGPU_IRQ_STATE_DISABLE: 3297 if (ring == 0) { 3298 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3299 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3300 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3301 break; 3302 } else { 3303 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3304 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3305 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3306 break; 3307 3308 } 3309 case AMDGPU_IRQ_STATE_ENABLE: 3310 if (ring == 0) { 3311 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3312 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3313 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3314 break; 3315 } else { 3316 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3317 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3318 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3319 break; 3320 3321 } 3322 3323 default: 3324 BUG(); 3325 break; 3326 3327 } 3328 } 3329 3330 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3331 struct amdgpu_irq_src *src, 3332 unsigned type, 3333 enum amdgpu_interrupt_state state) 3334 { 3335 u32 cp_int_cntl; 3336 3337 switch (state) { 3338 case AMDGPU_IRQ_STATE_DISABLE: 3339 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3340 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3341 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3342 break; 3343 case AMDGPU_IRQ_STATE_ENABLE: 3344 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3345 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3346 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3347 break; 3348 default: 3349 break; 3350 } 3351 3352 return 0; 3353 } 3354 3355 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3356 struct amdgpu_irq_src *src, 3357 unsigned type, 3358 enum amdgpu_interrupt_state state) 3359 { 3360 u32 cp_int_cntl; 3361 3362 switch (state) { 3363 case AMDGPU_IRQ_STATE_DISABLE: 3364 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3365 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3366 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3367 break; 3368 case AMDGPU_IRQ_STATE_ENABLE: 3369 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3370 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3371 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3372 break; 3373 default: 3374 break; 3375 } 3376 3377 return 0; 3378 } 3379 3380 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3381 struct amdgpu_irq_src *src, 3382 unsigned type, 3383 enum amdgpu_interrupt_state state) 3384 { 3385 switch (type) { 3386 case AMDGPU_CP_IRQ_GFX_EOP: 3387 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3388 break; 3389 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3390 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3391 break; 3392 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3393 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3394 break; 3395 default: 3396 break; 3397 } 3398 return 0; 3399 } 3400 3401 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3402 struct amdgpu_irq_src *source, 3403 struct amdgpu_iv_entry *entry) 3404 { 3405 switch (entry->ring_id) { 3406 case 0: 3407 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3408 break; 3409 case 1: 3410 case 2: 3411 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3412 break; 3413 default: 3414 break; 3415 } 3416 return 0; 3417 } 3418 3419 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3420 struct amdgpu_irq_src *source, 3421 struct amdgpu_iv_entry *entry) 3422 { 3423 DRM_ERROR("Illegal register access in command stream\n"); 3424 schedule_work(&adev->reset_work); 3425 return 0; 3426 } 3427 3428 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3429 struct amdgpu_irq_src *source, 3430 struct amdgpu_iv_entry *entry) 3431 { 3432 DRM_ERROR("Illegal instruction in command stream\n"); 3433 schedule_work(&adev->reset_work); 3434 return 0; 3435 } 3436 3437 static int gfx_v6_0_set_clockgating_state(void *handle, 3438 enum amd_clockgating_state state) 3439 { 3440 bool gate = false; 3441 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3442 3443 if (state == AMD_CG_STATE_GATE) 3444 gate = true; 3445 3446 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3447 if (gate) { 3448 gfx_v6_0_enable_mgcg(adev, true); 3449 gfx_v6_0_enable_cgcg(adev, true); 3450 } else { 3451 gfx_v6_0_enable_cgcg(adev, false); 3452 gfx_v6_0_enable_mgcg(adev, false); 3453 } 3454 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3455 3456 return 0; 3457 } 3458 3459 static int gfx_v6_0_set_powergating_state(void *handle, 3460 enum amd_powergating_state state) 3461 { 3462 bool gate = false; 3463 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3464 3465 if (state == AMD_PG_STATE_GATE) 3466 gate = true; 3467 3468 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3469 AMD_PG_SUPPORT_GFX_SMG | 3470 AMD_PG_SUPPORT_GFX_DMG | 3471 AMD_PG_SUPPORT_CP | 3472 AMD_PG_SUPPORT_GDS | 3473 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3474 gfx_v6_0_update_gfx_pg(adev, gate); 3475 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3476 gfx_v6_0_enable_cp_pg(adev, gate); 3477 gfx_v6_0_enable_gds_pg(adev, gate); 3478 } 3479 } 3480 3481 return 0; 3482 } 3483 3484 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3485 .name = "gfx_v6_0", 3486 .early_init = gfx_v6_0_early_init, 3487 .late_init = NULL, 3488 .sw_init = gfx_v6_0_sw_init, 3489 .sw_fini = gfx_v6_0_sw_fini, 3490 .hw_init = gfx_v6_0_hw_init, 3491 .hw_fini = gfx_v6_0_hw_fini, 3492 .suspend = gfx_v6_0_suspend, 3493 .resume = gfx_v6_0_resume, 3494 .is_idle = gfx_v6_0_is_idle, 3495 .wait_for_idle = gfx_v6_0_wait_for_idle, 3496 .soft_reset = gfx_v6_0_soft_reset, 3497 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3498 .set_powergating_state = gfx_v6_0_set_powergating_state, 3499 }; 3500 3501 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3502 .type = AMDGPU_RING_TYPE_GFX, 3503 .align_mask = 0xff, 3504 .nop = 0x80000000, 3505 .support_64bit_ptrs = false, 3506 .get_rptr = gfx_v6_0_ring_get_rptr, 3507 .get_wptr = gfx_v6_0_ring_get_wptr, 3508 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3509 .emit_frame_size = 3510 5 + /* gfx_v6_0_ring_emit_hdp_flush */ 3511 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ 3512 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3513 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3514 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3515 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3516 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3517 .emit_ib = gfx_v6_0_ring_emit_ib, 3518 .emit_fence = gfx_v6_0_ring_emit_fence, 3519 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3520 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3521 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, 3522 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, 3523 .test_ring = gfx_v6_0_ring_test_ring, 3524 .test_ib = gfx_v6_0_ring_test_ib, 3525 .insert_nop = amdgpu_ring_insert_nop, 3526 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3527 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3528 }; 3529 3530 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3531 .type = AMDGPU_RING_TYPE_COMPUTE, 3532 .align_mask = 0xff, 3533 .nop = 0x80000000, 3534 .get_rptr = gfx_v6_0_ring_get_rptr, 3535 .get_wptr = gfx_v6_0_ring_get_wptr, 3536 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3537 .emit_frame_size = 3538 5 + /* gfx_v6_0_ring_emit_hdp_flush */ 3539 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ 3540 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3541 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ 3542 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3543 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3544 .emit_ib = gfx_v6_0_ring_emit_ib, 3545 .emit_fence = gfx_v6_0_ring_emit_fence, 3546 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3547 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3548 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, 3549 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, 3550 .test_ring = gfx_v6_0_ring_test_ring, 3551 .test_ib = gfx_v6_0_ring_test_ib, 3552 .insert_nop = amdgpu_ring_insert_nop, 3553 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3554 }; 3555 3556 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3557 { 3558 int i; 3559 3560 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3561 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3562 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3563 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3564 } 3565 3566 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3567 .set = gfx_v6_0_set_eop_interrupt_state, 3568 .process = gfx_v6_0_eop_irq, 3569 }; 3570 3571 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3572 .set = gfx_v6_0_set_priv_reg_fault_state, 3573 .process = gfx_v6_0_priv_reg_irq, 3574 }; 3575 3576 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3577 .set = gfx_v6_0_set_priv_inst_fault_state, 3578 .process = gfx_v6_0_priv_inst_irq, 3579 }; 3580 3581 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3582 { 3583 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3584 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3585 3586 adev->gfx.priv_reg_irq.num_types = 1; 3587 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3588 3589 adev->gfx.priv_inst_irq.num_types = 1; 3590 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3591 } 3592 3593 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3594 { 3595 int i, j, k, counter, active_cu_number = 0; 3596 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3597 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3598 unsigned disable_masks[4 * 2]; 3599 u32 ao_cu_num; 3600 3601 if (adev->flags & AMD_IS_APU) 3602 ao_cu_num = 2; 3603 else 3604 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3605 3606 memset(cu_info, 0, sizeof(*cu_info)); 3607 3608 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 3609 3610 mutex_lock(&adev->grbm_idx_mutex); 3611 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3612 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3613 mask = 1; 3614 ao_bitmap = 0; 3615 counter = 0; 3616 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 3617 if (i < 4 && j < 2) 3618 gfx_v6_0_set_user_cu_inactive_bitmap( 3619 adev, disable_masks[i * 2 + j]); 3620 bitmap = gfx_v6_0_get_cu_enabled(adev); 3621 cu_info->bitmap[i][j] = bitmap; 3622 3623 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3624 if (bitmap & mask) { 3625 if (counter < ao_cu_num) 3626 ao_bitmap |= mask; 3627 counter ++; 3628 } 3629 mask <<= 1; 3630 } 3631 active_cu_number += counter; 3632 if (i < 2 && j < 2) 3633 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3634 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3635 } 3636 } 3637 3638 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3639 mutex_unlock(&adev->grbm_idx_mutex); 3640 3641 cu_info->number = active_cu_number; 3642 cu_info->ao_cu_mask = ao_cu_mask; 3643 } 3644 3645 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3646 { 3647 .type = AMD_IP_BLOCK_TYPE_GFX, 3648 .major = 6, 3649 .minor = 0, 3650 .rev = 0, 3651 .funcs = &gfx_v6_0_ip_funcs, 3652 }; 3653