1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 52 #define GFX11_NUM_GFX_RINGS 1 53 #define GFX11_MEC_HPD_SIZE 2048 54 55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 56 57 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 62 63 static const struct soc15_reg_golden golden_settings_gc_11_0[] = 64 { 65 /* Pending on emulation bring up */ 66 }; 67 68 static const struct soc15_reg_golden golden_settings_gc_11_0_0[] = 69 { 70 /* Pending on emulation bring up */ 71 }; 72 73 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_11_0[] = 74 { 75 /* Pending on emulation bring up */ 76 }; 77 78 #define DEFAULT_SH_MEM_CONFIG \ 79 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 80 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 81 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 82 83 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 84 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 85 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 86 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 87 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 88 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 89 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 90 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 91 struct amdgpu_cu_info *cu_info); 92 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 93 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 94 u32 sh_num, u32 instance); 95 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 96 97 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 98 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 99 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 100 uint32_t val); 101 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 102 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 103 uint16_t pasid, uint32_t flush_type, 104 bool all_hub, uint8_t dst_sel); 105 106 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 107 { 108 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 109 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 110 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 111 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 112 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 113 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 114 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 115 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 116 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 117 } 118 119 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 120 struct amdgpu_ring *ring) 121 { 122 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 123 uint64_t wptr_addr = ring->wptr_gpu_addr; 124 uint32_t eng_sel = 0; 125 126 switch (ring->funcs->type) { 127 case AMDGPU_RING_TYPE_COMPUTE: 128 eng_sel = 0; 129 break; 130 case AMDGPU_RING_TYPE_GFX: 131 eng_sel = 4; 132 break; 133 case AMDGPU_RING_TYPE_MES: 134 eng_sel = 5; 135 break; 136 default: 137 WARN_ON(1); 138 } 139 140 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 141 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 142 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 143 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 144 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 145 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 146 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 147 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 148 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 149 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 150 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 151 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 152 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 153 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 154 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 155 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 156 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 157 } 158 159 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 160 struct amdgpu_ring *ring, 161 enum amdgpu_unmap_queues_action action, 162 u64 gpu_addr, u64 seq) 163 { 164 struct amdgpu_device *adev = kiq_ring->adev; 165 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 166 167 if (!adev->gfx.kiq.ring.sched.ready) { 168 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 169 return; 170 } 171 172 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 173 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 174 PACKET3_UNMAP_QUEUES_ACTION(action) | 175 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 176 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 177 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 178 amdgpu_ring_write(kiq_ring, 179 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 180 181 if (action == PREEMPT_QUEUES_NO_UNMAP) { 182 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 183 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 184 amdgpu_ring_write(kiq_ring, seq); 185 } else { 186 amdgpu_ring_write(kiq_ring, 0); 187 amdgpu_ring_write(kiq_ring, 0); 188 amdgpu_ring_write(kiq_ring, 0); 189 } 190 } 191 192 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 193 struct amdgpu_ring *ring, 194 u64 addr, 195 u64 seq) 196 { 197 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 198 199 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 200 amdgpu_ring_write(kiq_ring, 201 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 202 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 203 PACKET3_QUERY_STATUS_COMMAND(2)); 204 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 205 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 206 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 207 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 208 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 209 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 210 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 211 } 212 213 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 214 uint16_t pasid, uint32_t flush_type, 215 bool all_hub) 216 { 217 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 218 } 219 220 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 221 .kiq_set_resources = gfx11_kiq_set_resources, 222 .kiq_map_queues = gfx11_kiq_map_queues, 223 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 224 .kiq_query_status = gfx11_kiq_query_status, 225 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 226 .set_resources_size = 8, 227 .map_queues_size = 7, 228 .unmap_queues_size = 6, 229 .query_status_size = 7, 230 .invalidate_tlbs_size = 2, 231 }; 232 233 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 234 { 235 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; 236 } 237 238 static void gfx_v11_0_init_spm_golden_registers(struct amdgpu_device *adev) 239 { 240 switch (adev->ip_versions[GC_HWIP][0]) { 241 case IP_VERSION(11, 0, 0): 242 soc15_program_register_sequence(adev, 243 golden_settings_gc_rlc_spm_11_0, 244 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_11_0)); 245 break; 246 default: 247 break; 248 } 249 } 250 251 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 252 { 253 switch (adev->ip_versions[GC_HWIP][0]) { 254 case IP_VERSION(11, 0, 0): 255 soc15_program_register_sequence(adev, 256 golden_settings_gc_11_0, 257 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 258 soc15_program_register_sequence(adev, 259 golden_settings_gc_11_0_0, 260 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_0)); 261 break; 262 default: 263 break; 264 } 265 gfx_v11_0_init_spm_golden_registers(adev); 266 } 267 268 static void gfx_v11_0_scratch_init(struct amdgpu_device *adev) 269 { 270 adev->gfx.scratch.num_reg = 8; 271 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 272 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 273 } 274 275 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 276 bool wc, uint32_t reg, uint32_t val) 277 { 278 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 279 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 280 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 281 amdgpu_ring_write(ring, reg); 282 amdgpu_ring_write(ring, 0); 283 amdgpu_ring_write(ring, val); 284 } 285 286 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 287 int mem_space, int opt, uint32_t addr0, 288 uint32_t addr1, uint32_t ref, uint32_t mask, 289 uint32_t inv) 290 { 291 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 292 amdgpu_ring_write(ring, 293 /* memory (1) or register (0) */ 294 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 295 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 296 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 297 WAIT_REG_MEM_ENGINE(eng_sel))); 298 299 if (mem_space) 300 BUG_ON(addr0 & 0x3); /* Dword align */ 301 amdgpu_ring_write(ring, addr0); 302 amdgpu_ring_write(ring, addr1); 303 amdgpu_ring_write(ring, ref); 304 amdgpu_ring_write(ring, mask); 305 amdgpu_ring_write(ring, inv); /* poll interval */ 306 } 307 308 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 309 { 310 struct amdgpu_device *adev = ring->adev; 311 uint32_t scratch; 312 uint32_t tmp = 0; 313 unsigned i; 314 int r; 315 316 r = amdgpu_gfx_scratch_get(adev, &scratch); 317 if (r) { 318 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 319 return r; 320 } 321 322 WREG32(scratch, 0xCAFEDEAD); 323 324 r = amdgpu_ring_alloc(ring, 5); 325 if (r) { 326 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 327 ring->idx, r); 328 amdgpu_gfx_scratch_free(adev, scratch); 329 return r; 330 } 331 332 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 333 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 334 } else { 335 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 336 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 337 amdgpu_ring_write(ring, 0xDEADBEEF); 338 } 339 amdgpu_ring_commit(ring); 340 341 for (i = 0; i < adev->usec_timeout; i++) { 342 tmp = RREG32(scratch); 343 if (tmp == 0xDEADBEEF) 344 break; 345 if (amdgpu_emu_mode == 1) 346 msleep(1); 347 else 348 udelay(1); 349 } 350 351 if (i >= adev->usec_timeout) 352 r = -ETIMEDOUT; 353 354 amdgpu_gfx_scratch_free(adev, scratch); 355 356 return r; 357 } 358 359 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 360 { 361 struct amdgpu_device *adev = ring->adev; 362 struct amdgpu_ib ib; 363 struct dma_fence *f = NULL; 364 unsigned index; 365 uint64_t gpu_addr; 366 volatile uint32_t *cpu_ptr; 367 long r; 368 369 /* MES KIQ fw hasn't indirect buffer support for now */ 370 if (adev->enable_mes_kiq && 371 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 372 return 0; 373 374 memset(&ib, 0, sizeof(ib)); 375 376 if (ring->is_mes_queue) { 377 uint32_t padding, offset; 378 379 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 380 padding = amdgpu_mes_ctx_get_offs(ring, 381 AMDGPU_MES_CTX_PADDING_OFFS); 382 383 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 384 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 385 386 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 387 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 388 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 389 } else { 390 r = amdgpu_device_wb_get(adev, &index); 391 if (r) 392 return r; 393 394 gpu_addr = adev->wb.gpu_addr + (index * 4); 395 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 396 cpu_ptr = &adev->wb.wb[index]; 397 398 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 399 if (r) { 400 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 401 goto err1; 402 } 403 } 404 405 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 406 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 407 ib.ptr[2] = lower_32_bits(gpu_addr); 408 ib.ptr[3] = upper_32_bits(gpu_addr); 409 ib.ptr[4] = 0xDEADBEEF; 410 ib.length_dw = 5; 411 412 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 413 if (r) 414 goto err2; 415 416 r = dma_fence_wait_timeout(f, false, timeout); 417 if (r == 0) { 418 r = -ETIMEDOUT; 419 goto err2; 420 } else if (r < 0) { 421 goto err2; 422 } 423 424 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 425 r = 0; 426 else 427 r = -EINVAL; 428 err2: 429 if (!ring->is_mes_queue) 430 amdgpu_ib_free(adev, &ib, NULL); 431 dma_fence_put(f); 432 err1: 433 if (!ring->is_mes_queue) 434 amdgpu_device_wb_free(adev, index); 435 return r; 436 } 437 438 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 439 { 440 release_firmware(adev->gfx.pfp_fw); 441 adev->gfx.pfp_fw = NULL; 442 release_firmware(adev->gfx.me_fw); 443 adev->gfx.me_fw = NULL; 444 release_firmware(adev->gfx.rlc_fw); 445 adev->gfx.rlc_fw = NULL; 446 release_firmware(adev->gfx.mec_fw); 447 adev->gfx.mec_fw = NULL; 448 449 kfree(adev->gfx.rlc.register_list_format); 450 } 451 452 static void gfx_v11_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 453 { 454 const struct rlc_firmware_header_v2_1 *rlc_hdr; 455 456 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 457 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 458 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 459 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 460 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 461 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 462 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 463 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 464 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 465 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 466 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 467 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 468 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 469 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 470 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 471 } 472 473 static void gfx_v11_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 474 { 475 const struct rlc_firmware_header_v2_2 *rlc_hdr; 476 477 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 478 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 479 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 480 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 481 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 482 } 483 484 static void gfx_v11_0_init_rlcp_rlcv_microcode(struct amdgpu_device *adev) 485 { 486 const struct rlc_firmware_header_v2_3 *rlc_hdr; 487 488 rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 489 adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes); 490 adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); 491 adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes); 492 adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); 493 } 494 495 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 496 { 497 char fw_name[40]; 498 char ucode_prefix[30]; 499 int err; 500 struct amdgpu_firmware_info *info = NULL; 501 const struct common_firmware_header *header = NULL; 502 const struct gfx_firmware_header_v1_0 *cp_hdr; 503 const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0; 504 const struct rlc_firmware_header_v2_0 *rlc_hdr; 505 unsigned int *tmp = NULL; 506 unsigned int i = 0; 507 uint16_t version_major; 508 uint16_t version_minor; 509 510 DRM_DEBUG("\n"); 511 512 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 513 514 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 515 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 516 if (err) 517 goto out; 518 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 519 if (err) 520 goto out; 521 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 522 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 523 (union amdgpu_firmware_header *) 524 adev->gfx.pfp_fw->data, 2, 0); 525 if (adev->gfx.rs64_enable) { 526 dev_info(adev->dev, "CP RS64 enable\n"); 527 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; 528 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 529 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 530 531 } else { 532 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 533 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 534 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 535 } 536 537 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 538 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 539 if (err) 540 goto out; 541 err = amdgpu_ucode_validate(adev->gfx.me_fw); 542 if (err) 543 goto out; 544 if (adev->gfx.rs64_enable) { 545 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; 546 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 547 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 548 549 } else { 550 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 551 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 552 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 553 } 554 555 if (!amdgpu_sriov_vf(adev)) { 556 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 557 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 558 if (err) 559 goto out; 560 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 561 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 562 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 563 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 564 565 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 566 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 567 adev->gfx.rlc.save_and_restore_offset = 568 le32_to_cpu(rlc_hdr->save_and_restore_offset); 569 adev->gfx.rlc.clear_state_descriptor_offset = 570 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 571 adev->gfx.rlc.avail_scratch_ram_locations = 572 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 573 adev->gfx.rlc.reg_restore_list_size = 574 le32_to_cpu(rlc_hdr->reg_restore_list_size); 575 adev->gfx.rlc.reg_list_format_start = 576 le32_to_cpu(rlc_hdr->reg_list_format_start); 577 adev->gfx.rlc.reg_list_format_separate_start = 578 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 579 adev->gfx.rlc.starting_offsets_start = 580 le32_to_cpu(rlc_hdr->starting_offsets_start); 581 adev->gfx.rlc.reg_list_format_size_bytes = 582 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 583 adev->gfx.rlc.reg_list_size_bytes = 584 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 585 adev->gfx.rlc.register_list_format = 586 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 587 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 588 if (!adev->gfx.rlc.register_list_format) { 589 err = -ENOMEM; 590 goto out; 591 } 592 593 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 594 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 595 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 596 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 597 598 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 599 600 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 601 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 602 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 603 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 604 605 if (version_major == 2) { 606 if (version_minor >= 1) 607 gfx_v11_0_init_rlc_ext_microcode(adev); 608 if (version_minor >= 2) 609 gfx_v11_0_init_rlc_iram_dram_microcode(adev); 610 if (version_minor == 3) 611 gfx_v11_0_init_rlcp_rlcv_microcode(adev); 612 } 613 } 614 615 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 616 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 617 if (err) 618 goto out; 619 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 620 if (err) 621 goto out; 622 if (adev->gfx.rs64_enable) { 623 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 624 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 625 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 626 627 } else { 628 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 629 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 630 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 631 } 632 633 /* only one MEC for gfx 11.0.0. */ 634 adev->gfx.mec2_fw = NULL; 635 636 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 637 if (adev->gfx.rs64_enable) { 638 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; 639 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP]; 640 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP; 641 info->fw = adev->gfx.pfp_fw; 642 header = (const struct common_firmware_header *)info->fw->data; 643 adev->firmware.fw_size += 644 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 645 646 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK]; 647 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK; 648 info->fw = adev->gfx.pfp_fw; 649 header = (const struct common_firmware_header *)info->fw->data; 650 adev->firmware.fw_size += 651 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 652 653 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK]; 654 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK; 655 info->fw = adev->gfx.pfp_fw; 656 header = (const struct common_firmware_header *)info->fw->data; 657 adev->firmware.fw_size += 658 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 659 660 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; 661 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME]; 662 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME; 663 info->fw = adev->gfx.me_fw; 664 header = (const struct common_firmware_header *)info->fw->data; 665 adev->firmware.fw_size += 666 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 667 668 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK]; 669 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK; 670 info->fw = adev->gfx.me_fw; 671 header = (const struct common_firmware_header *)info->fw->data; 672 adev->firmware.fw_size += 673 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 674 675 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK]; 676 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK; 677 info->fw = adev->gfx.me_fw; 678 header = (const struct common_firmware_header *)info->fw->data; 679 adev->firmware.fw_size += 680 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 681 682 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 683 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC]; 684 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC; 685 info->fw = adev->gfx.mec_fw; 686 header = (const struct common_firmware_header *)info->fw->data; 687 adev->firmware.fw_size += 688 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 689 690 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK]; 691 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK; 692 info->fw = adev->gfx.mec_fw; 693 header = (const struct common_firmware_header *)info->fw->data; 694 adev->firmware.fw_size += 695 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 696 697 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK]; 698 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK; 699 info->fw = adev->gfx.mec_fw; 700 header = (const struct common_firmware_header *)info->fw->data; 701 adev->firmware.fw_size += 702 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 703 704 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK]; 705 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK; 706 info->fw = adev->gfx.mec_fw; 707 header = (const struct common_firmware_header *)info->fw->data; 708 adev->firmware.fw_size += 709 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 710 711 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK]; 712 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK; 713 info->fw = adev->gfx.mec_fw; 714 header = (const struct common_firmware_header *)info->fw->data; 715 adev->firmware.fw_size += 716 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 717 } else { 718 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 719 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 720 info->fw = adev->gfx.pfp_fw; 721 header = (const struct common_firmware_header *)info->fw->data; 722 adev->firmware.fw_size += 723 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 724 725 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 726 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 727 info->fw = adev->gfx.me_fw; 728 header = (const struct common_firmware_header *)info->fw->data; 729 adev->firmware.fw_size += 730 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 731 732 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 733 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 734 info->fw = adev->gfx.mec_fw; 735 header = (const struct common_firmware_header *)info->fw->data; 736 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 737 adev->firmware.fw_size += 738 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 739 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 740 741 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 742 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 743 info->fw = adev->gfx.mec_fw; 744 adev->firmware.fw_size += 745 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 746 } 747 748 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 749 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 750 info->fw = adev->gfx.rlc_fw; 751 if (info->fw) { 752 header = (const struct common_firmware_header *)info->fw->data; 753 adev->firmware.fw_size += 754 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 755 } 756 if (adev->gfx.rlc.save_restore_list_gpm_size_bytes && 757 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 758 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 759 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 760 info->fw = adev->gfx.rlc_fw; 761 adev->firmware.fw_size += 762 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 763 764 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 765 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 766 info->fw = adev->gfx.rlc_fw; 767 adev->firmware.fw_size += 768 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 769 } 770 771 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 772 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 773 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 774 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 775 info->fw = adev->gfx.rlc_fw; 776 adev->firmware.fw_size += 777 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 778 779 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 780 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 781 info->fw = adev->gfx.rlc_fw; 782 adev->firmware.fw_size += 783 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 784 } 785 786 if (adev->gfx.rlc.rlcp_ucode_size_bytes) { 787 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; 788 info->ucode_id = AMDGPU_UCODE_ID_RLC_P; 789 info->fw = adev->gfx.rlc_fw; 790 adev->firmware.fw_size += 791 ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE); 792 } 793 794 if (adev->gfx.rlc.rlcv_ucode_size_bytes) { 795 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; 796 info->ucode_id = AMDGPU_UCODE_ID_RLC_V; 797 info->fw = adev->gfx.rlc_fw; 798 adev->firmware.fw_size += 799 ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE); 800 } 801 } 802 803 out: 804 if (err) { 805 dev_err(adev->dev, 806 "gfx11: Failed to load firmware \"%s\"\n", 807 fw_name); 808 release_firmware(adev->gfx.pfp_fw); 809 adev->gfx.pfp_fw = NULL; 810 release_firmware(adev->gfx.me_fw); 811 adev->gfx.me_fw = NULL; 812 release_firmware(adev->gfx.rlc_fw); 813 adev->gfx.rlc_fw = NULL; 814 release_firmware(adev->gfx.mec_fw); 815 adev->gfx.mec_fw = NULL; 816 } 817 818 return err; 819 } 820 821 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) 822 { 823 const struct psp_firmware_header_v1_0 *toc_hdr; 824 int err = 0; 825 char fw_name[40]; 826 char ucode_prefix[30]; 827 828 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 829 830 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 831 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 832 if (err) 833 goto out; 834 835 err = amdgpu_ucode_validate(adev->psp.toc_fw); 836 if (err) 837 goto out; 838 839 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 840 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 841 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 842 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 843 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 844 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 845 return 0; 846 out: 847 dev_err(adev->dev, "Failed to load TOC microcode\n"); 848 release_firmware(adev->psp.toc_fw); 849 adev->psp.toc_fw = NULL; 850 return err; 851 } 852 853 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 854 { 855 u32 count = 0; 856 const struct cs_section_def *sect = NULL; 857 const struct cs_extent_def *ext = NULL; 858 859 /* begin clear state */ 860 count += 2; 861 /* context control state */ 862 count += 3; 863 864 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 865 for (ext = sect->section; ext->extent != NULL; ++ext) { 866 if (sect->id == SECT_CONTEXT) 867 count += 2 + ext->reg_count; 868 else 869 return 0; 870 } 871 } 872 873 /* set PA_SC_TILE_STEERING_OVERRIDE */ 874 count += 3; 875 /* end clear state */ 876 count += 2; 877 /* clear state */ 878 count += 2; 879 880 return count; 881 } 882 883 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 884 volatile u32 *buffer) 885 { 886 u32 count = 0, i; 887 const struct cs_section_def *sect = NULL; 888 const struct cs_extent_def *ext = NULL; 889 int ctx_reg_offset; 890 891 if (adev->gfx.rlc.cs_data == NULL) 892 return; 893 if (buffer == NULL) 894 return; 895 896 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 897 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 898 899 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 900 buffer[count++] = cpu_to_le32(0x80000000); 901 buffer[count++] = cpu_to_le32(0x80000000); 902 903 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 904 for (ext = sect->section; ext->extent != NULL; ++ext) { 905 if (sect->id == SECT_CONTEXT) { 906 buffer[count++] = 907 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 908 buffer[count++] = cpu_to_le32(ext->reg_index - 909 PACKET3_SET_CONTEXT_REG_START); 910 for (i = 0; i < ext->reg_count; i++) 911 buffer[count++] = cpu_to_le32(ext->extent[i]); 912 } else { 913 return; 914 } 915 } 916 } 917 918 ctx_reg_offset = 919 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 920 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 921 buffer[count++] = cpu_to_le32(ctx_reg_offset); 922 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 923 924 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 925 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 926 927 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 928 buffer[count++] = cpu_to_le32(0); 929 } 930 931 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 932 { 933 /* clear state block */ 934 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 935 &adev->gfx.rlc.clear_state_gpu_addr, 936 (void **)&adev->gfx.rlc.cs_ptr); 937 938 /* jump table block */ 939 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 940 &adev->gfx.rlc.cp_table_gpu_addr, 941 (void **)&adev->gfx.rlc.cp_table_ptr); 942 } 943 944 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 945 { 946 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 947 948 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 949 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 950 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 951 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 952 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 953 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 954 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 955 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 956 adev->gfx.rlc.rlcg_reg_access_supported = true; 957 } 958 959 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 960 { 961 const struct cs_section_def *cs_data; 962 int r; 963 964 adev->gfx.rlc.cs_data = gfx11_cs_data; 965 966 cs_data = adev->gfx.rlc.cs_data; 967 968 if (cs_data) { 969 /* init clear state block */ 970 r = amdgpu_gfx_rlc_init_csb(adev); 971 if (r) 972 return r; 973 } 974 975 /* init spm vmid with 0xf */ 976 if (adev->gfx.rlc.funcs->update_spm_vmid) 977 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 978 979 return 0; 980 } 981 982 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 983 { 984 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 985 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 986 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 987 } 988 989 static int gfx_v11_0_me_init(struct amdgpu_device *adev) 990 { 991 int r; 992 993 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 994 995 amdgpu_gfx_graphics_queue_acquire(adev); 996 997 r = gfx_v11_0_init_microcode(adev); 998 if (r) 999 DRM_ERROR("Failed to load gfx firmware!\n"); 1000 1001 return r; 1002 } 1003 1004 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 1005 { 1006 int r; 1007 u32 *hpd; 1008 size_t mec_hpd_size; 1009 1010 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1011 1012 /* take ownership of the relevant compute queues */ 1013 amdgpu_gfx_compute_queue_acquire(adev); 1014 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 1015 1016 if (mec_hpd_size) { 1017 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1018 AMDGPU_GEM_DOMAIN_GTT, 1019 &adev->gfx.mec.hpd_eop_obj, 1020 &adev->gfx.mec.hpd_eop_gpu_addr, 1021 (void **)&hpd); 1022 if (r) { 1023 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1024 gfx_v11_0_mec_fini(adev); 1025 return r; 1026 } 1027 1028 memset(hpd, 0, mec_hpd_size); 1029 1030 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1031 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1032 } 1033 1034 return 0; 1035 } 1036 1037 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1038 { 1039 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1040 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1041 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1042 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1043 } 1044 1045 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1046 uint32_t thread, uint32_t regno, 1047 uint32_t num, uint32_t *out) 1048 { 1049 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1050 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1051 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1052 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1053 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1054 while (num--) 1055 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1056 } 1057 1058 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1059 { 1060 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 1061 * field when performing a select_se_sh so it should be 1062 * zero here */ 1063 WARN_ON(simd != 0); 1064 1065 /* type 2 wave data */ 1066 dst[(*no_fields)++] = 2; 1067 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1068 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1069 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1070 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1071 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1072 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1073 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1074 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1075 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1076 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1077 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1078 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1079 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1080 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1081 } 1082 1083 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1084 uint32_t wave, uint32_t start, 1085 uint32_t size, uint32_t *dst) 1086 { 1087 WARN_ON(simd != 0); 1088 1089 wave_read_regs( 1090 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1091 dst); 1092 } 1093 1094 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1095 uint32_t wave, uint32_t thread, 1096 uint32_t start, uint32_t size, 1097 uint32_t *dst) 1098 { 1099 wave_read_regs( 1100 adev, wave, thread, 1101 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1102 } 1103 1104 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1105 u32 me, u32 pipe, u32 q, u32 vm) 1106 { 1107 soc21_grbm_select(adev, me, pipe, q, vm); 1108 } 1109 1110 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1111 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1112 .select_se_sh = &gfx_v11_0_select_se_sh, 1113 .read_wave_data = &gfx_v11_0_read_wave_data, 1114 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1115 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1116 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1117 .init_spm_golden = &gfx_v11_0_init_spm_golden_registers, 1118 }; 1119 1120 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1121 { 1122 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 1123 1124 switch (adev->ip_versions[GC_HWIP][0]) { 1125 case IP_VERSION(11, 0, 0): 1126 adev->gfx.config.max_hw_contexts = 8; 1127 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1128 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1129 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1130 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1131 break; 1132 default: 1133 BUG(); 1134 break; 1135 } 1136 1137 return 0; 1138 } 1139 1140 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1141 int me, int pipe, int queue) 1142 { 1143 int r; 1144 struct amdgpu_ring *ring; 1145 unsigned int irq_type; 1146 1147 ring = &adev->gfx.gfx_ring[ring_id]; 1148 1149 ring->me = me; 1150 ring->pipe = pipe; 1151 ring->queue = queue; 1152 1153 ring->ring_obj = NULL; 1154 ring->use_doorbell = true; 1155 1156 if (!ring_id) 1157 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1158 else 1159 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1160 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1161 1162 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1163 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1164 AMDGPU_RING_PRIO_DEFAULT, NULL); 1165 if (r) 1166 return r; 1167 return 0; 1168 } 1169 1170 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1171 int mec, int pipe, int queue) 1172 { 1173 int r; 1174 unsigned irq_type; 1175 struct amdgpu_ring *ring; 1176 unsigned int hw_prio; 1177 1178 ring = &adev->gfx.compute_ring[ring_id]; 1179 1180 /* mec0 is me1 */ 1181 ring->me = mec + 1; 1182 ring->pipe = pipe; 1183 ring->queue = queue; 1184 1185 ring->ring_obj = NULL; 1186 ring->use_doorbell = true; 1187 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1188 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1189 + (ring_id * GFX11_MEC_HPD_SIZE); 1190 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1191 1192 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1193 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1194 + ring->pipe; 1195 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1196 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1197 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1198 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1199 hw_prio, NULL); 1200 if (r) 1201 return r; 1202 1203 return 0; 1204 } 1205 1206 static struct { 1207 SOC21_FIRMWARE_ID id; 1208 unsigned int offset; 1209 unsigned int size; 1210 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1211 1212 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1213 { 1214 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1215 1216 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1217 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1218 rlc_autoload_info[ucode->id].id = ucode->id; 1219 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1220 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1221 1222 ucode++; 1223 }; 1224 } 1225 1226 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1227 { 1228 uint32_t total_size = 0; 1229 SOC21_FIRMWARE_ID id; 1230 1231 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1232 1233 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1234 total_size += rlc_autoload_info[id].size; 1235 1236 /* In case the offset in rlc toc ucode is aligned */ 1237 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1238 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1239 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1240 1241 return total_size; 1242 } 1243 1244 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1245 { 1246 int r; 1247 uint32_t total_size; 1248 1249 total_size = gfx_v11_0_calc_toc_total_size(adev); 1250 1251 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1252 AMDGPU_GEM_DOMAIN_VRAM, 1253 &adev->gfx.rlc.rlc_autoload_bo, 1254 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1255 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1256 1257 if (r) { 1258 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1259 return r; 1260 } 1261 1262 return 0; 1263 } 1264 1265 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1266 SOC21_FIRMWARE_ID id, 1267 const void *fw_data, 1268 uint32_t fw_size, 1269 uint32_t *fw_autoload_mask) 1270 { 1271 uint32_t toc_offset; 1272 uint32_t toc_fw_size; 1273 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1274 1275 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1276 return; 1277 1278 toc_offset = rlc_autoload_info[id].offset; 1279 toc_fw_size = rlc_autoload_info[id].size; 1280 1281 if (fw_size == 0) 1282 fw_size = toc_fw_size; 1283 1284 if (fw_size > toc_fw_size) 1285 fw_size = toc_fw_size; 1286 1287 memcpy(ptr + toc_offset, fw_data, fw_size); 1288 1289 if (fw_size < toc_fw_size) 1290 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1291 1292 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1293 *(uint64_t *)fw_autoload_mask |= 1 << id; 1294 } 1295 1296 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1297 uint32_t *fw_autoload_mask) 1298 { 1299 void *data; 1300 uint32_t size; 1301 uint64_t *toc_ptr; 1302 1303 *(uint64_t *)fw_autoload_mask |= 0x1; 1304 1305 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1306 1307 data = adev->psp.toc.start_addr; 1308 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1309 1310 toc_ptr = (uint64_t *)data + size / 8 - 1; 1311 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1312 1313 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1314 data, size, fw_autoload_mask); 1315 } 1316 1317 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1318 uint32_t *fw_autoload_mask) 1319 { 1320 const __le32 *fw_data; 1321 uint32_t fw_size; 1322 const struct gfx_firmware_header_v1_0 *cp_hdr; 1323 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1324 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1325 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1326 uint16_t version_major, version_minor; 1327 1328 if (adev->gfx.rs64_enable) { 1329 /* pfp ucode */ 1330 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1331 adev->gfx.pfp_fw->data; 1332 /* instruction */ 1333 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1334 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1335 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1336 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1337 fw_data, fw_size, fw_autoload_mask); 1338 /* data */ 1339 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1340 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1341 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1342 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1343 fw_data, fw_size, fw_autoload_mask); 1344 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1345 fw_data, fw_size, fw_autoload_mask); 1346 /* me ucode */ 1347 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1348 adev->gfx.me_fw->data; 1349 /* instruction */ 1350 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1351 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1352 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1353 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1354 fw_data, fw_size, fw_autoload_mask); 1355 /* data */ 1356 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1357 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1358 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1359 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1360 fw_data, fw_size, fw_autoload_mask); 1361 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1362 fw_data, fw_size, fw_autoload_mask); 1363 /* mec ucode */ 1364 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1365 adev->gfx.mec_fw->data; 1366 /* instruction */ 1367 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1368 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1369 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1370 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1371 fw_data, fw_size, fw_autoload_mask); 1372 /* data */ 1373 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1374 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1375 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1376 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1377 fw_data, fw_size, fw_autoload_mask); 1378 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1379 fw_data, fw_size, fw_autoload_mask); 1380 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1381 fw_data, fw_size, fw_autoload_mask); 1382 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1383 fw_data, fw_size, fw_autoload_mask); 1384 } else { 1385 /* pfp ucode */ 1386 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1387 adev->gfx.pfp_fw->data; 1388 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1389 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1390 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1391 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1392 fw_data, fw_size, fw_autoload_mask); 1393 1394 /* me ucode */ 1395 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1396 adev->gfx.me_fw->data; 1397 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1398 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1399 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1400 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1401 fw_data, fw_size, fw_autoload_mask); 1402 1403 /* mec ucode */ 1404 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1405 adev->gfx.mec_fw->data; 1406 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1407 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1408 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1409 cp_hdr->jt_size * 4; 1410 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1411 fw_data, fw_size, fw_autoload_mask); 1412 } 1413 1414 /* rlc ucode */ 1415 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1416 adev->gfx.rlc_fw->data; 1417 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1418 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1419 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1420 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1421 fw_data, fw_size, fw_autoload_mask); 1422 1423 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1424 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1425 if (version_major == 2) { 1426 if (version_minor >= 2) { 1427 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1428 1429 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1430 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1431 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1432 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1433 fw_data, fw_size, fw_autoload_mask); 1434 1435 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1436 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1437 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1438 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1439 fw_data, fw_size, fw_autoload_mask); 1440 } 1441 } 1442 } 1443 1444 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1445 uint32_t *fw_autoload_mask) 1446 { 1447 const __le32 *fw_data; 1448 uint32_t fw_size; 1449 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1450 1451 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1452 adev->sdma.instance[0].fw->data; 1453 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1454 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1455 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1456 1457 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1458 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1459 1460 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1461 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1462 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1463 1464 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1465 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1466 } 1467 1468 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1469 uint32_t *fw_autoload_mask) 1470 { 1471 const __le32 *fw_data; 1472 unsigned fw_size; 1473 const struct mes_firmware_header_v1_0 *mes_hdr; 1474 int pipe, ucode_id, data_id; 1475 1476 for (pipe = 0; pipe < 2; pipe++) { 1477 if (pipe==0) { 1478 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1479 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1480 } else { 1481 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1482 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1483 } 1484 1485 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1486 adev->mes.fw[pipe]->data; 1487 1488 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1489 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1490 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1491 1492 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1493 ucode_id, fw_data, fw_size, fw_autoload_mask); 1494 1495 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1496 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1497 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1498 1499 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1500 data_id, fw_data, fw_size, fw_autoload_mask); 1501 } 1502 } 1503 1504 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1505 { 1506 uint32_t rlc_g_offset, rlc_g_size; 1507 uint64_t gpu_addr; 1508 uint32_t autoload_fw_id[2]; 1509 1510 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1511 1512 /* RLC autoload sequence 2: copy ucode */ 1513 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1514 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1515 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1516 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1517 1518 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1519 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1520 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1521 1522 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1523 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1524 1525 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1526 1527 /* RLC autoload sequence 3: load IMU fw */ 1528 if (adev->gfx.imu.funcs->load_microcode) 1529 adev->gfx.imu.funcs->load_microcode(adev); 1530 /* RLC autoload sequence 4 init IMU fw */ 1531 if (adev->gfx.imu.funcs->setup_imu) 1532 adev->gfx.imu.funcs->setup_imu(adev); 1533 if (adev->gfx.imu.funcs->start_imu) 1534 adev->gfx.imu.funcs->start_imu(adev); 1535 1536 /* RLC autoload sequence 5 disable gpa mode */ 1537 gfx_v11_0_disable_gpa_mode(adev); 1538 1539 return 0; 1540 } 1541 1542 static int gfx_v11_0_sw_init(void *handle) 1543 { 1544 int i, j, k, r, ring_id = 0; 1545 struct amdgpu_kiq *kiq; 1546 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1547 1548 adev->gfxhub.funcs->init(adev); 1549 1550 switch (adev->ip_versions[GC_HWIP][0]) { 1551 case IP_VERSION(11, 0, 0): 1552 adev->gfx.me.num_me = 1; 1553 adev->gfx.me.num_pipe_per_me = 1; 1554 adev->gfx.me.num_queue_per_pipe = 1; 1555 adev->gfx.mec.num_mec = 2; 1556 adev->gfx.mec.num_pipe_per_mec = 4; 1557 adev->gfx.mec.num_queue_per_pipe = 4; 1558 break; 1559 default: 1560 adev->gfx.me.num_me = 1; 1561 adev->gfx.me.num_pipe_per_me = 1; 1562 adev->gfx.me.num_queue_per_pipe = 1; 1563 adev->gfx.mec.num_mec = 1; 1564 adev->gfx.mec.num_pipe_per_mec = 4; 1565 adev->gfx.mec.num_queue_per_pipe = 8; 1566 break; 1567 } 1568 1569 /* EOP Event */ 1570 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1571 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1572 &adev->gfx.eop_irq); 1573 if (r) 1574 return r; 1575 1576 /* Privileged reg */ 1577 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1578 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1579 &adev->gfx.priv_reg_irq); 1580 if (r) 1581 return r; 1582 1583 /* Privileged inst */ 1584 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1585 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1586 &adev->gfx.priv_inst_irq); 1587 if (r) 1588 return r; 1589 1590 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1591 1592 gfx_v11_0_scratch_init(adev); 1593 1594 if (adev->gfx.imu.funcs) { 1595 if (adev->gfx.imu.funcs->init_microcode) { 1596 r = adev->gfx.imu.funcs->init_microcode(adev); 1597 if (r) 1598 DRM_ERROR("Failed to load imu firmware!\n"); 1599 } 1600 } 1601 1602 r = gfx_v11_0_me_init(adev); 1603 if (r) 1604 return r; 1605 1606 r = gfx_v11_0_rlc_init(adev); 1607 if (r) { 1608 DRM_ERROR("Failed to init rlc BOs!\n"); 1609 return r; 1610 } 1611 1612 r = gfx_v11_0_mec_init(adev); 1613 if (r) { 1614 DRM_ERROR("Failed to init MEC BOs!\n"); 1615 return r; 1616 } 1617 1618 /* set up the gfx ring */ 1619 for (i = 0; i < adev->gfx.me.num_me; i++) { 1620 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1621 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1622 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1623 continue; 1624 1625 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1626 i, k, j); 1627 if (r) 1628 return r; 1629 ring_id++; 1630 } 1631 } 1632 } 1633 1634 ring_id = 0; 1635 /* set up the compute queues - allocate horizontally across pipes */ 1636 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1637 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1638 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1639 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1640 j)) 1641 continue; 1642 1643 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1644 i, k, j); 1645 if (r) 1646 return r; 1647 1648 ring_id++; 1649 } 1650 } 1651 } 1652 1653 if (!adev->enable_mes_kiq) { 1654 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE); 1655 if (r) { 1656 DRM_ERROR("Failed to init KIQ BOs!\n"); 1657 return r; 1658 } 1659 1660 kiq = &adev->gfx.kiq; 1661 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1662 if (r) 1663 return r; 1664 } 1665 1666 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd)); 1667 if (r) 1668 return r; 1669 1670 /* allocate visible FB for rlc auto-loading fw */ 1671 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1672 r = gfx_v11_0_init_toc_microcode(adev); 1673 if (r) 1674 dev_err(adev->dev, "Failed to load toc firmware!\n"); 1675 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1676 if (r) 1677 return r; 1678 } 1679 1680 r = gfx_v11_0_gpu_early_init(adev); 1681 if (r) 1682 return r; 1683 1684 return 0; 1685 } 1686 1687 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1688 { 1689 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1690 &adev->gfx.pfp.pfp_fw_gpu_addr, 1691 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1692 1693 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1694 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1695 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1696 } 1697 1698 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1699 { 1700 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1701 &adev->gfx.me.me_fw_gpu_addr, 1702 (void **)&adev->gfx.me.me_fw_ptr); 1703 1704 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1705 &adev->gfx.me.me_fw_data_gpu_addr, 1706 (void **)&adev->gfx.me.me_fw_data_ptr); 1707 } 1708 1709 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1710 { 1711 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1712 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1713 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1714 } 1715 1716 static int gfx_v11_0_sw_fini(void *handle) 1717 { 1718 int i; 1719 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1720 1721 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1722 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1723 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1724 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1725 1726 amdgpu_gfx_mqd_sw_fini(adev); 1727 1728 if (!adev->enable_mes_kiq) { 1729 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1730 amdgpu_gfx_kiq_fini(adev); 1731 } 1732 1733 gfx_v11_0_pfp_fini(adev); 1734 gfx_v11_0_me_fini(adev); 1735 gfx_v11_0_rlc_fini(adev); 1736 gfx_v11_0_mec_fini(adev); 1737 1738 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1739 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1740 1741 gfx_v11_0_free_microcode(adev); 1742 1743 return 0; 1744 } 1745 1746 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1747 u32 sh_num, u32 instance) 1748 { 1749 u32 data; 1750 1751 if (instance == 0xffffffff) 1752 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1753 INSTANCE_BROADCAST_WRITES, 1); 1754 else 1755 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1756 instance); 1757 1758 if (se_num == 0xffffffff) 1759 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1760 1); 1761 else 1762 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1763 1764 if (sh_num == 0xffffffff) 1765 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1766 1); 1767 else 1768 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1769 1770 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1771 } 1772 1773 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1774 { 1775 u32 data, mask; 1776 1777 data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1778 data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1779 1780 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1781 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1782 1783 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1784 adev->gfx.config.max_sh_per_se); 1785 1786 return (~data) & mask; 1787 } 1788 1789 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1790 { 1791 int i, j; 1792 u32 data; 1793 u32 active_rbs = 0; 1794 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1795 adev->gfx.config.max_sh_per_se; 1796 1797 mutex_lock(&adev->grbm_idx_mutex); 1798 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1799 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1800 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 1801 data = gfx_v11_0_get_rb_active_bitmap(adev); 1802 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1803 rb_bitmap_width_per_sh); 1804 } 1805 } 1806 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1807 mutex_unlock(&adev->grbm_idx_mutex); 1808 1809 adev->gfx.config.backend_enable_mask = active_rbs; 1810 adev->gfx.config.num_rbs = hweight32(active_rbs); 1811 } 1812 1813 #define DEFAULT_SH_MEM_BASES (0x6000) 1814 #define LDS_APP_BASE 0x1 1815 #define SCRATCH_APP_BASE 0x2 1816 1817 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1818 { 1819 int i; 1820 uint32_t sh_mem_bases; 1821 uint32_t data; 1822 1823 /* 1824 * Configure apertures: 1825 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1826 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1827 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1828 */ 1829 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1830 SCRATCH_APP_BASE; 1831 1832 mutex_lock(&adev->srbm_mutex); 1833 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1834 soc21_grbm_select(adev, 0, 0, 0, i); 1835 /* CP and shaders */ 1836 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1837 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1838 1839 /* Enable trap for each kfd vmid. */ 1840 data = RREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL)); 1841 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1842 } 1843 soc21_grbm_select(adev, 0, 0, 0, 0); 1844 mutex_unlock(&adev->srbm_mutex); 1845 1846 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1847 acccess. These should be enabled by FW for target VMIDs. */ 1848 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1849 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1850 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1851 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1852 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1853 } 1854 } 1855 1856 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1857 { 1858 int vmid; 1859 1860 /* 1861 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1862 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1863 * the driver can enable them for graphics. VMID0 should maintain 1864 * access so that HWS firmware can save/restore entries. 1865 */ 1866 for (vmid = 1; vmid < 16; vmid++) { 1867 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1868 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1869 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1870 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1871 } 1872 } 1873 1874 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1875 { 1876 /* TODO: harvest feature to be added later. */ 1877 } 1878 1879 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1880 { 1881 /* TCCs are global (not instanced). */ 1882 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1883 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1884 1885 adev->gfx.config.tcc_disabled_mask = 1886 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1887 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1888 } 1889 1890 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1891 { 1892 u32 tmp; 1893 int i; 1894 1895 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1896 1897 gfx_v11_0_setup_rb(adev); 1898 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1899 gfx_v11_0_get_tcc_info(adev); 1900 adev->gfx.config.pa_sc_tile_steering_override = 0; 1901 1902 /* XXX SH_MEM regs */ 1903 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1904 mutex_lock(&adev->srbm_mutex); 1905 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1906 soc21_grbm_select(adev, 0, 0, 0, i); 1907 /* CP and shaders */ 1908 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1909 if (i != 0) { 1910 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1911 (adev->gmc.private_aperture_start >> 48)); 1912 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1913 (adev->gmc.shared_aperture_start >> 48)); 1914 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1915 } 1916 } 1917 soc21_grbm_select(adev, 0, 0, 0, 0); 1918 1919 mutex_unlock(&adev->srbm_mutex); 1920 1921 gfx_v11_0_init_compute_vmid(adev); 1922 gfx_v11_0_init_gds_vmid(adev); 1923 } 1924 1925 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1926 bool enable) 1927 { 1928 u32 tmp; 1929 1930 if (amdgpu_sriov_vf(adev)) 1931 return; 1932 1933 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1934 1935 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1936 enable ? 1 : 0); 1937 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1938 enable ? 1 : 0); 1939 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1940 enable ? 1 : 0); 1941 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1942 enable ? 1 : 0); 1943 1944 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1945 } 1946 1947 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1948 { 1949 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1950 1951 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1952 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1953 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1954 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1955 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1956 1957 return 0; 1958 } 1959 1960 void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1961 { 1962 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1963 1964 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1965 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1966 } 1967 1968 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1969 { 1970 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1971 udelay(50); 1972 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1973 udelay(50); 1974 } 1975 1976 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1977 bool enable) 1978 { 1979 uint32_t rlc_pg_cntl; 1980 1981 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1982 1983 if (!enable) { 1984 /* RLC_PG_CNTL[23] = 0 (default) 1985 * RLC will wait for handshake acks with SMU 1986 * GFXOFF will be enabled 1987 * RLC_PG_CNTL[23] = 1 1988 * RLC will not issue any message to SMU 1989 * hence no handshake between SMU & RLC 1990 * GFXOFF will be disabled 1991 */ 1992 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1993 } else 1994 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1995 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1996 } 1997 1998 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 1999 { 2000 /* TODO: enable rlc & smu handshake until smu 2001 * and gfxoff feature works as expected */ 2002 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2003 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2004 2005 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2006 udelay(50); 2007 } 2008 2009 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2010 { 2011 uint32_t tmp; 2012 2013 /* enable Save Restore Machine */ 2014 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2015 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2016 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2017 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2018 } 2019 2020 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2021 { 2022 const struct rlc_firmware_header_v2_0 *hdr; 2023 const __le32 *fw_data; 2024 unsigned i, fw_size; 2025 2026 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2027 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2028 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2029 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2030 2031 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2032 RLCG_UCODE_LOADING_START_ADDRESS); 2033 2034 for (i = 0; i < fw_size; i++) 2035 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2036 le32_to_cpup(fw_data++)); 2037 2038 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2039 } 2040 2041 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2042 { 2043 const struct rlc_firmware_header_v2_2 *hdr; 2044 const __le32 *fw_data; 2045 unsigned i, fw_size; 2046 u32 tmp; 2047 2048 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2049 2050 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2051 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2052 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2053 2054 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2055 2056 for (i = 0; i < fw_size; i++) { 2057 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2058 msleep(1); 2059 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2060 le32_to_cpup(fw_data++)); 2061 } 2062 2063 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2064 2065 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2066 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2067 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2068 2069 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2070 for (i = 0; i < fw_size; i++) { 2071 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2072 msleep(1); 2073 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2074 le32_to_cpup(fw_data++)); 2075 } 2076 2077 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2078 2079 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2080 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2081 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2082 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2083 } 2084 2085 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2086 { 2087 const struct rlc_firmware_header_v2_3 *hdr; 2088 const __le32 *fw_data; 2089 unsigned i, fw_size; 2090 u32 tmp; 2091 2092 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2093 2094 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2095 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2096 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2097 2098 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2099 2100 for (i = 0; i < fw_size; i++) { 2101 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2102 msleep(1); 2103 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2104 le32_to_cpup(fw_data++)); 2105 } 2106 2107 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2108 2109 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2110 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2111 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2112 2113 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2114 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2115 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2116 2117 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2118 2119 for (i = 0; i < fw_size; i++) { 2120 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2121 msleep(1); 2122 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2123 le32_to_cpup(fw_data++)); 2124 } 2125 2126 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2127 2128 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2129 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2130 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2131 } 2132 2133 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2134 { 2135 const struct rlc_firmware_header_v2_0 *hdr; 2136 uint16_t version_major; 2137 uint16_t version_minor; 2138 2139 if (!adev->gfx.rlc_fw) 2140 return -EINVAL; 2141 2142 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2143 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2144 2145 version_major = le16_to_cpu(hdr->header.header_version_major); 2146 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2147 2148 if (version_major == 2) { 2149 gfx_v11_0_load_rlcg_microcode(adev); 2150 if (amdgpu_dpm == 1) { 2151 if (version_minor >= 2) 2152 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2153 if (version_minor == 3) 2154 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2155 } 2156 2157 return 0; 2158 } 2159 2160 return -EINVAL; 2161 } 2162 2163 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2164 { 2165 int r; 2166 2167 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2168 gfx_v11_0_init_csb(adev); 2169 2170 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2171 gfx_v11_0_rlc_enable_srm(adev); 2172 } else { 2173 if (amdgpu_sriov_vf(adev)) { 2174 gfx_v11_0_init_csb(adev); 2175 return 0; 2176 } 2177 2178 adev->gfx.rlc.funcs->stop(adev); 2179 2180 /* disable CG */ 2181 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2182 2183 /* disable PG */ 2184 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2185 2186 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2187 /* legacy rlc firmware loading */ 2188 r = gfx_v11_0_rlc_load_microcode(adev); 2189 if (r) 2190 return r; 2191 } 2192 2193 gfx_v11_0_init_csb(adev); 2194 2195 adev->gfx.rlc.funcs->start(adev); 2196 } 2197 return 0; 2198 } 2199 2200 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2201 { 2202 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2203 uint32_t tmp; 2204 int i; 2205 2206 /* Trigger an invalidation of the L1 instruction caches */ 2207 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2208 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2209 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2210 2211 /* Wait for invalidation complete */ 2212 for (i = 0; i < usec_timeout; i++) { 2213 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2214 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2215 INVALIDATE_CACHE_COMPLETE)) 2216 break; 2217 udelay(1); 2218 } 2219 2220 if (i >= usec_timeout) { 2221 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2222 return -EINVAL; 2223 } 2224 2225 if (amdgpu_emu_mode == 1) 2226 adev->hdp.funcs->flush_hdp(adev, NULL); 2227 2228 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2229 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2230 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2231 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2232 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2233 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2234 2235 /* Program me ucode address into intruction cache address register */ 2236 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2237 lower_32_bits(addr) & 0xFFFFF000); 2238 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2239 upper_32_bits(addr)); 2240 2241 return 0; 2242 } 2243 2244 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2245 { 2246 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2247 uint32_t tmp; 2248 int i; 2249 2250 /* Trigger an invalidation of the L1 instruction caches */ 2251 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2252 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2253 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2254 2255 /* Wait for invalidation complete */ 2256 for (i = 0; i < usec_timeout; i++) { 2257 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2258 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2259 INVALIDATE_CACHE_COMPLETE)) 2260 break; 2261 udelay(1); 2262 } 2263 2264 if (i >= usec_timeout) { 2265 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2266 return -EINVAL; 2267 } 2268 2269 if (amdgpu_emu_mode == 1) 2270 adev->hdp.funcs->flush_hdp(adev, NULL); 2271 2272 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2273 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2274 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2275 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2276 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2277 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2278 2279 /* Program pfp ucode address into intruction cache address register */ 2280 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2281 lower_32_bits(addr) & 0xFFFFF000); 2282 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2283 upper_32_bits(addr)); 2284 2285 return 0; 2286 } 2287 2288 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2289 { 2290 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2291 uint32_t tmp; 2292 int i; 2293 2294 /* Trigger an invalidation of the L1 instruction caches */ 2295 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2296 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2297 2298 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2299 2300 /* Wait for invalidation complete */ 2301 for (i = 0; i < usec_timeout; i++) { 2302 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2303 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2304 INVALIDATE_CACHE_COMPLETE)) 2305 break; 2306 udelay(1); 2307 } 2308 2309 if (i >= usec_timeout) { 2310 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2311 return -EINVAL; 2312 } 2313 2314 if (amdgpu_emu_mode == 1) 2315 adev->hdp.funcs->flush_hdp(adev, NULL); 2316 2317 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2318 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2319 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2320 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2321 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2322 2323 /* Program mec1 ucode address into intruction cache address register */ 2324 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2325 lower_32_bits(addr) & 0xFFFFF000); 2326 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2327 upper_32_bits(addr)); 2328 2329 return 0; 2330 } 2331 2332 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2333 { 2334 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2335 uint32_t tmp; 2336 unsigned i, pipe_id; 2337 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2338 2339 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2340 adev->gfx.pfp_fw->data; 2341 2342 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2343 lower_32_bits(addr)); 2344 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2345 upper_32_bits(addr)); 2346 2347 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2348 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2349 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2350 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2351 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2352 2353 /* 2354 * Programming any of the CP_PFP_IC_BASE registers 2355 * forces invalidation of the ME L1 I$. Wait for the 2356 * invalidation complete 2357 */ 2358 for (i = 0; i < usec_timeout; i++) { 2359 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2360 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2361 INVALIDATE_CACHE_COMPLETE)) 2362 break; 2363 udelay(1); 2364 } 2365 2366 if (i >= usec_timeout) { 2367 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2368 return -EINVAL; 2369 } 2370 2371 /* Prime the L1 instruction caches */ 2372 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2373 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2374 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2375 /* Waiting for cache primed*/ 2376 for (i = 0; i < usec_timeout; i++) { 2377 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2378 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2379 ICACHE_PRIMED)) 2380 break; 2381 udelay(1); 2382 } 2383 2384 if (i >= usec_timeout) { 2385 dev_err(adev->dev, "failed to prime instruction cache\n"); 2386 return -EINVAL; 2387 } 2388 2389 mutex_lock(&adev->srbm_mutex); 2390 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2391 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2392 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2393 (pfp_hdr->ucode_start_addr_hi << 30) | 2394 (pfp_hdr->ucode_start_addr_lo >> 2)); 2395 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2396 pfp_hdr->ucode_start_addr_hi >> 2); 2397 2398 /* 2399 * Program CP_ME_CNTL to reset given PIPE to take 2400 * effect of CP_PFP_PRGRM_CNTR_START. 2401 */ 2402 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2403 if (pipe_id == 0) 2404 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2405 PFP_PIPE0_RESET, 1); 2406 else 2407 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2408 PFP_PIPE1_RESET, 1); 2409 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2410 2411 /* Clear pfp pipe0 reset bit. */ 2412 if (pipe_id == 0) 2413 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2414 PFP_PIPE0_RESET, 0); 2415 else 2416 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2417 PFP_PIPE1_RESET, 0); 2418 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2419 2420 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2421 lower_32_bits(addr2)); 2422 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2423 upper_32_bits(addr2)); 2424 } 2425 soc21_grbm_select(adev, 0, 0, 0, 0); 2426 mutex_unlock(&adev->srbm_mutex); 2427 2428 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2429 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2430 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2431 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2432 2433 /* Invalidate the data caches */ 2434 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2435 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2436 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2437 2438 for (i = 0; i < usec_timeout; i++) { 2439 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2440 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2441 INVALIDATE_DCACHE_COMPLETE)) 2442 break; 2443 udelay(1); 2444 } 2445 2446 if (i >= usec_timeout) { 2447 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2448 return -EINVAL; 2449 } 2450 2451 return 0; 2452 } 2453 2454 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2455 { 2456 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2457 uint32_t tmp; 2458 unsigned i, pipe_id; 2459 const struct gfx_firmware_header_v2_0 *me_hdr; 2460 2461 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2462 adev->gfx.me_fw->data; 2463 2464 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2465 lower_32_bits(addr)); 2466 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2467 upper_32_bits(addr)); 2468 2469 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2470 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2471 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2472 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2473 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2474 2475 /* 2476 * Programming any of the CP_ME_IC_BASE registers 2477 * forces invalidation of the ME L1 I$. Wait for the 2478 * invalidation complete 2479 */ 2480 for (i = 0; i < usec_timeout; i++) { 2481 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2482 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2483 INVALIDATE_CACHE_COMPLETE)) 2484 break; 2485 udelay(1); 2486 } 2487 2488 if (i >= usec_timeout) { 2489 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2490 return -EINVAL; 2491 } 2492 2493 /* Prime the instruction caches */ 2494 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2495 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2496 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2497 2498 /* Waiting for instruction cache primed*/ 2499 for (i = 0; i < usec_timeout; i++) { 2500 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2501 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2502 ICACHE_PRIMED)) 2503 break; 2504 udelay(1); 2505 } 2506 2507 if (i >= usec_timeout) { 2508 dev_err(adev->dev, "failed to prime instruction cache\n"); 2509 return -EINVAL; 2510 } 2511 2512 mutex_lock(&adev->srbm_mutex); 2513 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2514 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2515 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2516 (me_hdr->ucode_start_addr_hi << 30) | 2517 (me_hdr->ucode_start_addr_lo >> 2) ); 2518 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2519 me_hdr->ucode_start_addr_hi>>2); 2520 2521 /* 2522 * Program CP_ME_CNTL to reset given PIPE to take 2523 * effect of CP_PFP_PRGRM_CNTR_START. 2524 */ 2525 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2526 if (pipe_id == 0) 2527 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2528 ME_PIPE0_RESET, 1); 2529 else 2530 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2531 ME_PIPE1_RESET, 1); 2532 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2533 2534 /* Clear pfp pipe0 reset bit. */ 2535 if (pipe_id == 0) 2536 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2537 ME_PIPE0_RESET, 0); 2538 else 2539 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2540 ME_PIPE1_RESET, 0); 2541 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2542 2543 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2544 lower_32_bits(addr2)); 2545 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2546 upper_32_bits(addr2)); 2547 } 2548 soc21_grbm_select(adev, 0, 0, 0, 0); 2549 mutex_unlock(&adev->srbm_mutex); 2550 2551 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2552 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2553 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2554 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2555 2556 /* Invalidate the data caches */ 2557 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2558 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2559 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2560 2561 for (i = 0; i < usec_timeout; i++) { 2562 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2563 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2564 INVALIDATE_DCACHE_COMPLETE)) 2565 break; 2566 udelay(1); 2567 } 2568 2569 if (i >= usec_timeout) { 2570 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2571 return -EINVAL; 2572 } 2573 2574 return 0; 2575 } 2576 2577 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2578 { 2579 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2580 uint32_t tmp; 2581 unsigned i; 2582 const struct gfx_firmware_header_v2_0 *mec_hdr; 2583 2584 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2585 adev->gfx.mec_fw->data; 2586 2587 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2588 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2589 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2590 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2591 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2592 2593 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2594 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2595 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2596 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2597 2598 mutex_lock(&adev->srbm_mutex); 2599 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2600 soc21_grbm_select(adev, 1, i, 0, 0); 2601 2602 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2603 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2604 upper_32_bits(addr2)); 2605 2606 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2607 mec_hdr->ucode_start_addr_lo >> 2 | 2608 mec_hdr->ucode_start_addr_hi << 30); 2609 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2610 mec_hdr->ucode_start_addr_hi >> 2); 2611 2612 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2613 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2614 upper_32_bits(addr)); 2615 } 2616 mutex_unlock(&adev->srbm_mutex); 2617 soc21_grbm_select(adev, 0, 0, 0, 0); 2618 2619 /* Trigger an invalidation of the L1 instruction caches */ 2620 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2621 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2622 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2623 2624 /* Wait for invalidation complete */ 2625 for (i = 0; i < usec_timeout; i++) { 2626 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2627 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2628 INVALIDATE_DCACHE_COMPLETE)) 2629 break; 2630 udelay(1); 2631 } 2632 2633 if (i >= usec_timeout) { 2634 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2635 return -EINVAL; 2636 } 2637 2638 /* Trigger an invalidation of the L1 instruction caches */ 2639 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2640 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2641 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2642 2643 /* Wait for invalidation complete */ 2644 for (i = 0; i < usec_timeout; i++) { 2645 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2646 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2647 INVALIDATE_CACHE_COMPLETE)) 2648 break; 2649 udelay(1); 2650 } 2651 2652 if (i >= usec_timeout) { 2653 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2654 return -EINVAL; 2655 } 2656 2657 return 0; 2658 } 2659 2660 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2661 { 2662 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2663 const struct gfx_firmware_header_v2_0 *me_hdr; 2664 const struct gfx_firmware_header_v2_0 *mec_hdr; 2665 uint32_t pipe_id, tmp; 2666 2667 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2668 adev->gfx.mec_fw->data; 2669 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2670 adev->gfx.me_fw->data; 2671 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2672 adev->gfx.pfp_fw->data; 2673 2674 /* config pfp program start addr */ 2675 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2676 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2677 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2678 (pfp_hdr->ucode_start_addr_hi << 30) | 2679 (pfp_hdr->ucode_start_addr_lo >> 2)); 2680 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2681 pfp_hdr->ucode_start_addr_hi >> 2); 2682 } 2683 soc21_grbm_select(adev, 0, 0, 0, 0); 2684 2685 /* reset pfp pipe */ 2686 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2687 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2688 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2689 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2690 2691 /* clear pfp pipe reset */ 2692 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2693 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2694 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2695 2696 /* config me program start addr */ 2697 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2698 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2699 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2700 (me_hdr->ucode_start_addr_hi << 30) | 2701 (me_hdr->ucode_start_addr_lo >> 2) ); 2702 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2703 me_hdr->ucode_start_addr_hi>>2); 2704 } 2705 soc21_grbm_select(adev, 0, 0, 0, 0); 2706 2707 /* reset me pipe */ 2708 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2709 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2710 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2711 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2712 2713 /* clear me pipe reset */ 2714 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2715 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2716 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2717 2718 /* config mec program start addr */ 2719 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2720 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2721 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2722 mec_hdr->ucode_start_addr_lo >> 2 | 2723 mec_hdr->ucode_start_addr_hi << 30); 2724 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2725 mec_hdr->ucode_start_addr_hi >> 2); 2726 } 2727 soc21_grbm_select(adev, 0, 0, 0, 0); 2728 } 2729 2730 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2731 { 2732 uint32_t cp_status; 2733 uint32_t bootload_status; 2734 int i, r; 2735 uint64_t addr, addr2; 2736 2737 for (i = 0; i < adev->usec_timeout; i++) { 2738 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2739 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2740 if ((cp_status == 0) && 2741 (REG_GET_FIELD(bootload_status, 2742 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2743 break; 2744 } 2745 udelay(1); 2746 } 2747 2748 if (i >= adev->usec_timeout) { 2749 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2750 return -ETIMEDOUT; 2751 } 2752 2753 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2754 if (adev->gfx.rs64_enable) { 2755 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2756 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2757 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2758 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2759 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2760 if (r) 2761 return r; 2762 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2763 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2764 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2765 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2766 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2767 if (r) 2768 return r; 2769 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2770 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2771 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2772 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2773 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2774 if (r) 2775 return r; 2776 } else { 2777 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2778 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2779 r = gfx_v11_0_config_me_cache(adev, addr); 2780 if (r) 2781 return r; 2782 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2783 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2784 r = gfx_v11_0_config_pfp_cache(adev, addr); 2785 if (r) 2786 return r; 2787 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2788 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2789 r = gfx_v11_0_config_mec_cache(adev, addr); 2790 if (r) 2791 return r; 2792 } 2793 } 2794 2795 return 0; 2796 } 2797 2798 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2799 { 2800 int i; 2801 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2802 2803 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2804 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2805 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2806 2807 for (i = 0; i < adev->usec_timeout; i++) { 2808 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2809 break; 2810 udelay(1); 2811 } 2812 2813 if (i >= adev->usec_timeout) 2814 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2815 2816 return 0; 2817 } 2818 2819 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2820 { 2821 int r; 2822 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2823 const __le32 *fw_data; 2824 unsigned i, fw_size; 2825 2826 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2827 adev->gfx.pfp_fw->data; 2828 2829 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2830 2831 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2832 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2833 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2834 2835 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2836 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2837 &adev->gfx.pfp.pfp_fw_obj, 2838 &adev->gfx.pfp.pfp_fw_gpu_addr, 2839 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2840 if (r) { 2841 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2842 gfx_v11_0_pfp_fini(adev); 2843 return r; 2844 } 2845 2846 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2847 2848 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2849 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2850 2851 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2852 2853 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2854 2855 for (i = 0; i < pfp_hdr->jt_size; i++) 2856 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2857 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2858 2859 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2860 2861 return 0; 2862 } 2863 2864 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2865 { 2866 int r; 2867 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2868 const __le32 *fw_ucode, *fw_data; 2869 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2870 uint32_t tmp; 2871 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2872 2873 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2874 adev->gfx.pfp_fw->data; 2875 2876 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2877 2878 /* instruction */ 2879 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2880 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2881 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2882 /* data */ 2883 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2884 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2885 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2886 2887 /* 64kb align */ 2888 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2889 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2890 &adev->gfx.pfp.pfp_fw_obj, 2891 &adev->gfx.pfp.pfp_fw_gpu_addr, 2892 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2893 if (r) { 2894 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2895 gfx_v11_0_pfp_fini(adev); 2896 return r; 2897 } 2898 2899 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2900 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2901 &adev->gfx.pfp.pfp_fw_data_obj, 2902 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2903 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2904 if (r) { 2905 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2906 gfx_v11_0_pfp_fini(adev); 2907 return r; 2908 } 2909 2910 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2911 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2912 2913 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2914 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2915 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2916 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2917 2918 if (amdgpu_emu_mode == 1) 2919 adev->hdp.funcs->flush_hdp(adev, NULL); 2920 2921 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2922 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2923 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2924 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2925 2926 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2927 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2928 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2929 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2930 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2931 2932 /* 2933 * Programming any of the CP_PFP_IC_BASE registers 2934 * forces invalidation of the ME L1 I$. Wait for the 2935 * invalidation complete 2936 */ 2937 for (i = 0; i < usec_timeout; i++) { 2938 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2939 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2940 INVALIDATE_CACHE_COMPLETE)) 2941 break; 2942 udelay(1); 2943 } 2944 2945 if (i >= usec_timeout) { 2946 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2947 return -EINVAL; 2948 } 2949 2950 /* Prime the L1 instruction caches */ 2951 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2952 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2953 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2954 /* Waiting for cache primed*/ 2955 for (i = 0; i < usec_timeout; i++) { 2956 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2957 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2958 ICACHE_PRIMED)) 2959 break; 2960 udelay(1); 2961 } 2962 2963 if (i >= usec_timeout) { 2964 dev_err(adev->dev, "failed to prime instruction cache\n"); 2965 return -EINVAL; 2966 } 2967 2968 mutex_lock(&adev->srbm_mutex); 2969 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2970 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2971 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2972 (pfp_hdr->ucode_start_addr_hi << 30) | 2973 (pfp_hdr->ucode_start_addr_lo >> 2) ); 2974 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2975 pfp_hdr->ucode_start_addr_hi>>2); 2976 2977 /* 2978 * Program CP_ME_CNTL to reset given PIPE to take 2979 * effect of CP_PFP_PRGRM_CNTR_START. 2980 */ 2981 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2982 if (pipe_id == 0) 2983 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2984 PFP_PIPE0_RESET, 1); 2985 else 2986 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2987 PFP_PIPE1_RESET, 1); 2988 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2989 2990 /* Clear pfp pipe0 reset bit. */ 2991 if (pipe_id == 0) 2992 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2993 PFP_PIPE0_RESET, 0); 2994 else 2995 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2996 PFP_PIPE1_RESET, 0); 2997 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2998 2999 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3000 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3001 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3002 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3003 } 3004 soc21_grbm_select(adev, 0, 0, 0, 0); 3005 mutex_unlock(&adev->srbm_mutex); 3006 3007 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3008 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3009 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3010 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3011 3012 /* Invalidate the data caches */ 3013 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3014 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3015 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3016 3017 for (i = 0; i < usec_timeout; i++) { 3018 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3019 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3020 INVALIDATE_DCACHE_COMPLETE)) 3021 break; 3022 udelay(1); 3023 } 3024 3025 if (i >= usec_timeout) { 3026 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3027 return -EINVAL; 3028 } 3029 3030 return 0; 3031 } 3032 3033 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3034 { 3035 int r; 3036 const struct gfx_firmware_header_v1_0 *me_hdr; 3037 const __le32 *fw_data; 3038 unsigned i, fw_size; 3039 3040 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3041 adev->gfx.me_fw->data; 3042 3043 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3044 3045 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3046 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3047 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3048 3049 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3050 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3051 &adev->gfx.me.me_fw_obj, 3052 &adev->gfx.me.me_fw_gpu_addr, 3053 (void **)&adev->gfx.me.me_fw_ptr); 3054 if (r) { 3055 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3056 gfx_v11_0_me_fini(adev); 3057 return r; 3058 } 3059 3060 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3061 3062 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3063 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3064 3065 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3066 3067 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3068 3069 for (i = 0; i < me_hdr->jt_size; i++) 3070 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3071 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3072 3073 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3074 3075 return 0; 3076 } 3077 3078 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3079 { 3080 int r; 3081 const struct gfx_firmware_header_v2_0 *me_hdr; 3082 const __le32 *fw_ucode, *fw_data; 3083 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3084 uint32_t tmp; 3085 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3086 3087 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3088 adev->gfx.me_fw->data; 3089 3090 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3091 3092 /* instruction */ 3093 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3094 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3095 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3096 /* data */ 3097 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3098 le32_to_cpu(me_hdr->data_offset_bytes)); 3099 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3100 3101 /* 64kb align*/ 3102 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3103 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3104 &adev->gfx.me.me_fw_obj, 3105 &adev->gfx.me.me_fw_gpu_addr, 3106 (void **)&adev->gfx.me.me_fw_ptr); 3107 if (r) { 3108 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3109 gfx_v11_0_me_fini(adev); 3110 return r; 3111 } 3112 3113 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3114 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3115 &adev->gfx.me.me_fw_data_obj, 3116 &adev->gfx.me.me_fw_data_gpu_addr, 3117 (void **)&adev->gfx.me.me_fw_data_ptr); 3118 if (r) { 3119 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3120 gfx_v11_0_pfp_fini(adev); 3121 return r; 3122 } 3123 3124 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3125 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3126 3127 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3128 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3129 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3130 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3131 3132 if (amdgpu_emu_mode == 1) 3133 adev->hdp.funcs->flush_hdp(adev, NULL); 3134 3135 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3136 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3137 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3138 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3139 3140 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3141 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3142 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3143 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3144 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3145 3146 /* 3147 * Programming any of the CP_ME_IC_BASE registers 3148 * forces invalidation of the ME L1 I$. Wait for the 3149 * invalidation complete 3150 */ 3151 for (i = 0; i < usec_timeout; i++) { 3152 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3153 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3154 INVALIDATE_CACHE_COMPLETE)) 3155 break; 3156 udelay(1); 3157 } 3158 3159 if (i >= usec_timeout) { 3160 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3161 return -EINVAL; 3162 } 3163 3164 /* Prime the instruction caches */ 3165 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3166 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3167 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3168 3169 /* Waiting for instruction cache primed*/ 3170 for (i = 0; i < usec_timeout; i++) { 3171 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3172 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3173 ICACHE_PRIMED)) 3174 break; 3175 udelay(1); 3176 } 3177 3178 if (i >= usec_timeout) { 3179 dev_err(adev->dev, "failed to prime instruction cache\n"); 3180 return -EINVAL; 3181 } 3182 3183 mutex_lock(&adev->srbm_mutex); 3184 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3185 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3186 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3187 (me_hdr->ucode_start_addr_hi << 30) | 3188 (me_hdr->ucode_start_addr_lo >> 2) ); 3189 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3190 me_hdr->ucode_start_addr_hi>>2); 3191 3192 /* 3193 * Program CP_ME_CNTL to reset given PIPE to take 3194 * effect of CP_PFP_PRGRM_CNTR_START. 3195 */ 3196 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3197 if (pipe_id == 0) 3198 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3199 ME_PIPE0_RESET, 1); 3200 else 3201 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3202 ME_PIPE1_RESET, 1); 3203 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3204 3205 /* Clear pfp pipe0 reset bit. */ 3206 if (pipe_id == 0) 3207 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3208 ME_PIPE0_RESET, 0); 3209 else 3210 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3211 ME_PIPE1_RESET, 0); 3212 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3213 3214 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3215 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3216 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3217 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3218 } 3219 soc21_grbm_select(adev, 0, 0, 0, 0); 3220 mutex_unlock(&adev->srbm_mutex); 3221 3222 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3223 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3224 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3225 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3226 3227 /* Invalidate the data caches */ 3228 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3229 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3230 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3231 3232 for (i = 0; i < usec_timeout; i++) { 3233 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3234 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3235 INVALIDATE_DCACHE_COMPLETE)) 3236 break; 3237 udelay(1); 3238 } 3239 3240 if (i >= usec_timeout) { 3241 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3242 return -EINVAL; 3243 } 3244 3245 return 0; 3246 } 3247 3248 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3249 { 3250 int r; 3251 3252 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3253 return -EINVAL; 3254 3255 gfx_v11_0_cp_gfx_enable(adev, false); 3256 3257 if (adev->gfx.rs64_enable) 3258 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3259 else 3260 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3261 if (r) { 3262 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3263 return r; 3264 } 3265 3266 if (adev->gfx.rs64_enable) 3267 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3268 else 3269 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3270 if (r) { 3271 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3272 return r; 3273 } 3274 3275 return 0; 3276 } 3277 3278 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3279 { 3280 struct amdgpu_ring *ring; 3281 const struct cs_section_def *sect = NULL; 3282 const struct cs_extent_def *ext = NULL; 3283 int r, i; 3284 int ctx_reg_offset; 3285 3286 /* init the CP */ 3287 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3288 adev->gfx.config.max_hw_contexts - 1); 3289 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3290 3291 if (!amdgpu_async_gfx_ring) 3292 gfx_v11_0_cp_gfx_enable(adev, true); 3293 3294 ring = &adev->gfx.gfx_ring[0]; 3295 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3296 if (r) { 3297 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3298 return r; 3299 } 3300 3301 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3302 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3303 3304 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3305 amdgpu_ring_write(ring, 0x80000000); 3306 amdgpu_ring_write(ring, 0x80000000); 3307 3308 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3309 for (ext = sect->section; ext->extent != NULL; ++ext) { 3310 if (sect->id == SECT_CONTEXT) { 3311 amdgpu_ring_write(ring, 3312 PACKET3(PACKET3_SET_CONTEXT_REG, 3313 ext->reg_count)); 3314 amdgpu_ring_write(ring, ext->reg_index - 3315 PACKET3_SET_CONTEXT_REG_START); 3316 for (i = 0; i < ext->reg_count; i++) 3317 amdgpu_ring_write(ring, ext->extent[i]); 3318 } 3319 } 3320 } 3321 3322 ctx_reg_offset = 3323 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3324 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3325 amdgpu_ring_write(ring, ctx_reg_offset); 3326 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3327 3328 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3329 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3330 3331 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3332 amdgpu_ring_write(ring, 0); 3333 3334 amdgpu_ring_commit(ring); 3335 3336 /* submit cs packet to copy state 0 to next available state */ 3337 if (adev->gfx.num_gfx_rings > 1) { 3338 /* maximum supported gfx ring is 2 */ 3339 ring = &adev->gfx.gfx_ring[1]; 3340 r = amdgpu_ring_alloc(ring, 2); 3341 if (r) { 3342 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3343 return r; 3344 } 3345 3346 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3347 amdgpu_ring_write(ring, 0); 3348 3349 amdgpu_ring_commit(ring); 3350 } 3351 return 0; 3352 } 3353 3354 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3355 CP_PIPE_ID pipe) 3356 { 3357 u32 tmp; 3358 3359 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3360 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3361 3362 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3363 } 3364 3365 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3366 struct amdgpu_ring *ring) 3367 { 3368 u32 tmp; 3369 3370 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3371 if (ring->use_doorbell) { 3372 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3373 DOORBELL_OFFSET, ring->doorbell_index); 3374 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3375 DOORBELL_EN, 1); 3376 } else { 3377 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3378 DOORBELL_EN, 0); 3379 } 3380 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3381 3382 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3383 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3384 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3385 3386 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3387 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3388 } 3389 3390 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3391 { 3392 struct amdgpu_ring *ring; 3393 u32 tmp; 3394 u32 rb_bufsz; 3395 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3396 u32 i; 3397 3398 /* Set the write pointer delay */ 3399 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3400 3401 /* set the RB to use vmid 0 */ 3402 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3403 3404 /* Init gfx ring 0 for pipe 0 */ 3405 mutex_lock(&adev->srbm_mutex); 3406 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3407 3408 /* Set ring buffer size */ 3409 ring = &adev->gfx.gfx_ring[0]; 3410 rb_bufsz = order_base_2(ring->ring_size / 8); 3411 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3412 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3413 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3414 3415 /* Initialize the ring buffer's write pointers */ 3416 ring->wptr = 0; 3417 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3418 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3419 3420 /* set the wb address wether it's enabled or not */ 3421 rptr_addr = ring->rptr_gpu_addr; 3422 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3423 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3424 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3425 3426 wptr_gpu_addr = ring->wptr_gpu_addr; 3427 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3428 lower_32_bits(wptr_gpu_addr)); 3429 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3430 upper_32_bits(wptr_gpu_addr)); 3431 3432 mdelay(1); 3433 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3434 3435 rb_addr = ring->gpu_addr >> 8; 3436 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3437 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3438 3439 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3440 3441 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3442 mutex_unlock(&adev->srbm_mutex); 3443 3444 /* Init gfx ring 1 for pipe 1 */ 3445 if (adev->gfx.num_gfx_rings > 1) { 3446 mutex_lock(&adev->srbm_mutex); 3447 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3448 /* maximum supported gfx ring is 2 */ 3449 ring = &adev->gfx.gfx_ring[1]; 3450 rb_bufsz = order_base_2(ring->ring_size / 8); 3451 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3452 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3453 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3454 /* Initialize the ring buffer's write pointers */ 3455 ring->wptr = 0; 3456 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3457 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3458 /* Set the wb address wether it's enabled or not */ 3459 rptr_addr = ring->rptr_gpu_addr; 3460 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3461 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3462 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3463 wptr_gpu_addr = ring->wptr_gpu_addr; 3464 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3465 lower_32_bits(wptr_gpu_addr)); 3466 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3467 upper_32_bits(wptr_gpu_addr)); 3468 3469 mdelay(1); 3470 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3471 3472 rb_addr = ring->gpu_addr >> 8; 3473 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3474 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3475 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3476 3477 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3478 mutex_unlock(&adev->srbm_mutex); 3479 } 3480 /* Switch to pipe 0 */ 3481 mutex_lock(&adev->srbm_mutex); 3482 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3483 mutex_unlock(&adev->srbm_mutex); 3484 3485 /* start the ring */ 3486 gfx_v11_0_cp_gfx_start(adev); 3487 3488 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3489 ring = &adev->gfx.gfx_ring[i]; 3490 ring->sched.ready = true; 3491 } 3492 3493 return 0; 3494 } 3495 3496 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3497 { 3498 u32 data; 3499 3500 if (adev->gfx.rs64_enable) { 3501 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3502 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3503 enable ? 0 : 1); 3504 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3505 enable ? 0 : 1); 3506 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3507 enable ? 0 : 1); 3508 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3509 enable ? 0 : 1); 3510 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3511 enable ? 0 : 1); 3512 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3513 enable ? 1 : 0); 3514 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3515 enable ? 1 : 0); 3516 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3517 enable ? 1 : 0); 3518 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3519 enable ? 1 : 0); 3520 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3521 enable ? 0 : 1); 3522 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3523 } else { 3524 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3525 3526 if (enable) { 3527 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3528 if (!adev->enable_mes_kiq) 3529 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3530 MEC_ME2_HALT, 0); 3531 } else { 3532 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3533 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3534 } 3535 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3536 } 3537 3538 adev->gfx.kiq.ring.sched.ready = enable; 3539 3540 udelay(50); 3541 } 3542 3543 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3544 { 3545 const struct gfx_firmware_header_v1_0 *mec_hdr; 3546 const __le32 *fw_data; 3547 unsigned i, fw_size; 3548 u32 *fw = NULL; 3549 int r; 3550 3551 if (!adev->gfx.mec_fw) 3552 return -EINVAL; 3553 3554 gfx_v11_0_cp_compute_enable(adev, false); 3555 3556 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3557 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3558 3559 fw_data = (const __le32 *) 3560 (adev->gfx.mec_fw->data + 3561 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3562 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3563 3564 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3565 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3566 &adev->gfx.mec.mec_fw_obj, 3567 &adev->gfx.mec.mec_fw_gpu_addr, 3568 (void **)&fw); 3569 if (r) { 3570 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3571 gfx_v11_0_mec_fini(adev); 3572 return r; 3573 } 3574 3575 memcpy(fw, fw_data, fw_size); 3576 3577 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3578 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3579 3580 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3581 3582 /* MEC1 */ 3583 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3584 3585 for (i = 0; i < mec_hdr->jt_size; i++) 3586 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3587 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3588 3589 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3590 3591 return 0; 3592 } 3593 3594 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3595 { 3596 const struct gfx_firmware_header_v2_0 *mec_hdr; 3597 const __le32 *fw_ucode, *fw_data; 3598 u32 tmp, fw_ucode_size, fw_data_size; 3599 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3600 u32 *fw_ucode_ptr, *fw_data_ptr; 3601 int r; 3602 3603 if (!adev->gfx.mec_fw) 3604 return -EINVAL; 3605 3606 gfx_v11_0_cp_compute_enable(adev, false); 3607 3608 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3609 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3610 3611 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3612 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3613 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3614 3615 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3616 le32_to_cpu(mec_hdr->data_offset_bytes)); 3617 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3618 3619 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3620 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3621 &adev->gfx.mec.mec_fw_obj, 3622 &adev->gfx.mec.mec_fw_gpu_addr, 3623 (void **)&fw_ucode_ptr); 3624 if (r) { 3625 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3626 gfx_v11_0_mec_fini(adev); 3627 return r; 3628 } 3629 3630 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3631 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3632 &adev->gfx.mec.mec_fw_data_obj, 3633 &adev->gfx.mec.mec_fw_data_gpu_addr, 3634 (void **)&fw_data_ptr); 3635 if (r) { 3636 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3637 gfx_v11_0_mec_fini(adev); 3638 return r; 3639 } 3640 3641 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3642 memcpy(fw_data_ptr, fw_data, fw_data_size); 3643 3644 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3645 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3646 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3647 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3648 3649 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3650 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3651 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3652 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3653 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3654 3655 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3656 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3657 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3658 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3659 3660 mutex_lock(&adev->srbm_mutex); 3661 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3662 soc21_grbm_select(adev, 1, i, 0, 0); 3663 3664 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3665 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3666 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3667 3668 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3669 mec_hdr->ucode_start_addr_lo >> 2 | 3670 mec_hdr->ucode_start_addr_hi << 30); 3671 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3672 mec_hdr->ucode_start_addr_hi >> 2); 3673 3674 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3675 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3676 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3677 } 3678 mutex_unlock(&adev->srbm_mutex); 3679 soc21_grbm_select(adev, 0, 0, 0, 0); 3680 3681 /* Trigger an invalidation of the L1 instruction caches */ 3682 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3683 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3684 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3685 3686 /* Wait for invalidation complete */ 3687 for (i = 0; i < usec_timeout; i++) { 3688 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3689 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3690 INVALIDATE_DCACHE_COMPLETE)) 3691 break; 3692 udelay(1); 3693 } 3694 3695 if (i >= usec_timeout) { 3696 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3697 return -EINVAL; 3698 } 3699 3700 /* Trigger an invalidation of the L1 instruction caches */ 3701 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3702 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3703 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3704 3705 /* Wait for invalidation complete */ 3706 for (i = 0; i < usec_timeout; i++) { 3707 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3708 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3709 INVALIDATE_CACHE_COMPLETE)) 3710 break; 3711 udelay(1); 3712 } 3713 3714 if (i >= usec_timeout) { 3715 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3716 return -EINVAL; 3717 } 3718 3719 return 0; 3720 } 3721 3722 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3723 { 3724 uint32_t tmp; 3725 struct amdgpu_device *adev = ring->adev; 3726 3727 /* tell RLC which is KIQ queue */ 3728 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3729 tmp &= 0xffffff00; 3730 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3731 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3732 tmp |= 0x80; 3733 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3734 } 3735 3736 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3737 { 3738 /* set graphics engine doorbell range */ 3739 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3740 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3741 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3742 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3743 3744 /* set compute engine doorbell range */ 3745 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3746 (adev->doorbell_index.kiq * 2) << 2); 3747 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3748 (adev->doorbell_index.userqueue_end * 2) << 2); 3749 } 3750 3751 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3752 struct amdgpu_mqd_prop *prop) 3753 { 3754 struct v11_gfx_mqd *mqd = m; 3755 uint64_t hqd_gpu_addr, wb_gpu_addr; 3756 uint32_t tmp; 3757 uint32_t rb_bufsz; 3758 3759 /* set up gfx hqd wptr */ 3760 mqd->cp_gfx_hqd_wptr = 0; 3761 mqd->cp_gfx_hqd_wptr_hi = 0; 3762 3763 /* set the pointer to the MQD */ 3764 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3765 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3766 3767 /* set up mqd control */ 3768 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3769 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3770 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3771 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3772 mqd->cp_gfx_mqd_control = tmp; 3773 3774 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3775 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3776 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3777 mqd->cp_gfx_hqd_vmid = 0; 3778 3779 /* set up default queue priority level 3780 * 0x0 = low priority, 0x1 = high priority */ 3781 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3782 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3783 mqd->cp_gfx_hqd_queue_priority = tmp; 3784 3785 /* set up time quantum */ 3786 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3787 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3788 mqd->cp_gfx_hqd_quantum = tmp; 3789 3790 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3791 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3792 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3793 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3794 3795 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3796 wb_gpu_addr = prop->rptr_gpu_addr; 3797 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3798 mqd->cp_gfx_hqd_rptr_addr_hi = 3799 upper_32_bits(wb_gpu_addr) & 0xffff; 3800 3801 /* set up rb_wptr_poll addr */ 3802 wb_gpu_addr = prop->wptr_gpu_addr; 3803 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3804 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3805 3806 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3807 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3808 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3809 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3810 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3811 #ifdef __BIG_ENDIAN 3812 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3813 #endif 3814 mqd->cp_gfx_hqd_cntl = tmp; 3815 3816 /* set up cp_doorbell_control */ 3817 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3818 if (prop->use_doorbell) { 3819 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3820 DOORBELL_OFFSET, prop->doorbell_index); 3821 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3822 DOORBELL_EN, 1); 3823 } else 3824 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3825 DOORBELL_EN, 0); 3826 mqd->cp_rb_doorbell_control = tmp; 3827 3828 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3829 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3830 3831 /* active the queue */ 3832 mqd->cp_gfx_hqd_active = 1; 3833 3834 return 0; 3835 } 3836 3837 #ifdef BRING_UP_DEBUG 3838 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3839 { 3840 struct amdgpu_device *adev = ring->adev; 3841 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3842 3843 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3844 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3845 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3846 3847 /* set GFX_MQD_BASE */ 3848 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3849 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3850 3851 /* set GFX_MQD_CONTROL */ 3852 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3853 3854 /* set GFX_HQD_VMID to 0 */ 3855 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3856 3857 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY, 3858 mqd->cp_gfx_hqd_queue_priority); 3859 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3860 3861 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3862 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3863 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3864 3865 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3866 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3867 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3868 3869 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3870 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3871 3872 /* set RB_WPTR_POLL_ADDR */ 3873 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3874 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3875 3876 /* set RB_DOORBELL_CONTROL */ 3877 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3878 3879 /* active the queue */ 3880 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3881 3882 return 0; 3883 } 3884 #endif 3885 3886 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3887 { 3888 struct amdgpu_device *adev = ring->adev; 3889 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3890 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3891 3892 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3893 memset((void *)mqd, 0, sizeof(*mqd)); 3894 mutex_lock(&adev->srbm_mutex); 3895 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3896 amdgpu_ring_init_mqd(ring); 3897 #ifdef BRING_UP_DEBUG 3898 gfx_v11_0_gfx_queue_init_register(ring); 3899 #endif 3900 soc21_grbm_select(adev, 0, 0, 0, 0); 3901 mutex_unlock(&adev->srbm_mutex); 3902 if (adev->gfx.me.mqd_backup[mqd_idx]) 3903 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3904 } else if (amdgpu_in_reset(adev)) { 3905 /* reset mqd with the backup copy */ 3906 if (adev->gfx.me.mqd_backup[mqd_idx]) 3907 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3908 /* reset the ring */ 3909 ring->wptr = 0; 3910 *ring->wptr_cpu_addr = 0; 3911 amdgpu_ring_clear_ring(ring); 3912 #ifdef BRING_UP_DEBUG 3913 mutex_lock(&adev->srbm_mutex); 3914 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3915 gfx_v11_0_gfx_queue_init_register(ring); 3916 soc21_grbm_select(adev, 0, 0, 0, 0); 3917 mutex_unlock(&adev->srbm_mutex); 3918 #endif 3919 } else { 3920 amdgpu_ring_clear_ring(ring); 3921 } 3922 3923 return 0; 3924 } 3925 3926 #ifndef BRING_UP_DEBUG 3927 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev) 3928 { 3929 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3930 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3931 int r, i; 3932 3933 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3934 return -EINVAL; 3935 3936 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3937 adev->gfx.num_gfx_rings); 3938 if (r) { 3939 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3940 return r; 3941 } 3942 3943 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3944 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3945 3946 return amdgpu_ring_test_helper(kiq_ring); 3947 } 3948 #endif 3949 3950 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3951 { 3952 int r, i; 3953 struct amdgpu_ring *ring; 3954 3955 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3956 ring = &adev->gfx.gfx_ring[i]; 3957 3958 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3959 if (unlikely(r != 0)) 3960 goto done; 3961 3962 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3963 if (!r) { 3964 r = gfx_v11_0_gfx_init_queue(ring); 3965 amdgpu_bo_kunmap(ring->mqd_obj); 3966 ring->mqd_ptr = NULL; 3967 } 3968 amdgpu_bo_unreserve(ring->mqd_obj); 3969 if (r) 3970 goto done; 3971 } 3972 #ifndef BRING_UP_DEBUG 3973 r = gfx_v11_0_kiq_enable_kgq(adev); 3974 if (r) 3975 goto done; 3976 #endif 3977 r = gfx_v11_0_cp_gfx_start(adev); 3978 if (r) 3979 goto done; 3980 3981 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3982 ring = &adev->gfx.gfx_ring[i]; 3983 ring->sched.ready = true; 3984 } 3985 done: 3986 return r; 3987 } 3988 3989 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3990 struct amdgpu_mqd_prop *prop) 3991 { 3992 struct v11_compute_mqd *mqd = m; 3993 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3994 uint32_t tmp; 3995 3996 mqd->header = 0xC0310800; 3997 mqd->compute_pipelinestat_enable = 0x00000001; 3998 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3999 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4000 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4001 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4002 mqd->compute_misc_reserved = 0x00000007; 4003 4004 eop_base_addr = prop->eop_gpu_addr >> 8; 4005 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4006 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4007 4008 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4009 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 4010 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4011 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4012 4013 mqd->cp_hqd_eop_control = tmp; 4014 4015 /* enable doorbell? */ 4016 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4017 4018 if (prop->use_doorbell) { 4019 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4020 DOORBELL_OFFSET, prop->doorbell_index); 4021 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4022 DOORBELL_EN, 1); 4023 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4024 DOORBELL_SOURCE, 0); 4025 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4026 DOORBELL_HIT, 0); 4027 } else { 4028 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4029 DOORBELL_EN, 0); 4030 } 4031 4032 mqd->cp_hqd_pq_doorbell_control = tmp; 4033 4034 /* disable the queue if it's active */ 4035 mqd->cp_hqd_dequeue_request = 0; 4036 mqd->cp_hqd_pq_rptr = 0; 4037 mqd->cp_hqd_pq_wptr_lo = 0; 4038 mqd->cp_hqd_pq_wptr_hi = 0; 4039 4040 /* set the pointer to the MQD */ 4041 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4042 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4043 4044 /* set MQD vmid to 0 */ 4045 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 4046 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4047 mqd->cp_mqd_control = tmp; 4048 4049 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4050 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4051 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4052 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4053 4054 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4055 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 4056 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4057 (order_base_2(prop->queue_size / 4) - 1)); 4058 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4059 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 4060 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 4061 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 4062 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4063 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4064 mqd->cp_hqd_pq_control = tmp; 4065 4066 /* set the wb address whether it's enabled or not */ 4067 wb_gpu_addr = prop->rptr_gpu_addr; 4068 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4069 mqd->cp_hqd_pq_rptr_report_addr_hi = 4070 upper_32_bits(wb_gpu_addr) & 0xffff; 4071 4072 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4073 wb_gpu_addr = prop->wptr_gpu_addr; 4074 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4075 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4076 4077 tmp = 0; 4078 /* enable the doorbell if requested */ 4079 if (prop->use_doorbell) { 4080 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4081 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4082 DOORBELL_OFFSET, prop->doorbell_index); 4083 4084 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4085 DOORBELL_EN, 1); 4086 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4087 DOORBELL_SOURCE, 0); 4088 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4089 DOORBELL_HIT, 0); 4090 } 4091 4092 mqd->cp_hqd_pq_doorbell_control = tmp; 4093 4094 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4095 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 4096 4097 /* set the vmid for the queue */ 4098 mqd->cp_hqd_vmid = 0; 4099 4100 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 4101 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4102 mqd->cp_hqd_persistent_state = tmp; 4103 4104 /* set MIN_IB_AVAIL_SIZE */ 4105 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 4106 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4107 mqd->cp_hqd_ib_control = tmp; 4108 4109 /* set static priority for a compute queue/ring */ 4110 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4111 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4112 4113 mqd->cp_hqd_active = prop->hqd_active; 4114 4115 return 0; 4116 } 4117 4118 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4119 { 4120 struct amdgpu_device *adev = ring->adev; 4121 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4122 int j; 4123 4124 /* inactivate the queue */ 4125 if (amdgpu_sriov_vf(adev)) 4126 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4127 4128 /* disable wptr polling */ 4129 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4130 4131 /* write the EOP addr */ 4132 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4133 mqd->cp_hqd_eop_base_addr_lo); 4134 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4135 mqd->cp_hqd_eop_base_addr_hi); 4136 4137 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4138 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4139 mqd->cp_hqd_eop_control); 4140 4141 /* enable doorbell? */ 4142 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4143 mqd->cp_hqd_pq_doorbell_control); 4144 4145 /* disable the queue if it's active */ 4146 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4147 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4148 for (j = 0; j < adev->usec_timeout; j++) { 4149 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4150 break; 4151 udelay(1); 4152 } 4153 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4154 mqd->cp_hqd_dequeue_request); 4155 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4156 mqd->cp_hqd_pq_rptr); 4157 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4158 mqd->cp_hqd_pq_wptr_lo); 4159 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4160 mqd->cp_hqd_pq_wptr_hi); 4161 } 4162 4163 /* set the pointer to the MQD */ 4164 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4165 mqd->cp_mqd_base_addr_lo); 4166 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4167 mqd->cp_mqd_base_addr_hi); 4168 4169 /* set MQD vmid to 0 */ 4170 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4171 mqd->cp_mqd_control); 4172 4173 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4174 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4175 mqd->cp_hqd_pq_base_lo); 4176 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4177 mqd->cp_hqd_pq_base_hi); 4178 4179 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4180 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4181 mqd->cp_hqd_pq_control); 4182 4183 /* set the wb address whether it's enabled or not */ 4184 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4185 mqd->cp_hqd_pq_rptr_report_addr_lo); 4186 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4187 mqd->cp_hqd_pq_rptr_report_addr_hi); 4188 4189 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4190 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4191 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4192 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4193 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4194 4195 /* enable the doorbell if requested */ 4196 if (ring->use_doorbell) { 4197 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4198 (adev->doorbell_index.kiq * 2) << 2); 4199 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4200 (adev->doorbell_index.userqueue_end * 2) << 2); 4201 } 4202 4203 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4204 mqd->cp_hqd_pq_doorbell_control); 4205 4206 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4207 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4208 mqd->cp_hqd_pq_wptr_lo); 4209 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4210 mqd->cp_hqd_pq_wptr_hi); 4211 4212 /* set the vmid for the queue */ 4213 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4214 4215 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4216 mqd->cp_hqd_persistent_state); 4217 4218 /* activate the queue */ 4219 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4220 mqd->cp_hqd_active); 4221 4222 if (ring->use_doorbell) 4223 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4224 4225 return 0; 4226 } 4227 4228 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4229 { 4230 struct amdgpu_device *adev = ring->adev; 4231 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4232 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 4233 4234 gfx_v11_0_kiq_setting(ring); 4235 4236 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4237 /* reset MQD to a clean status */ 4238 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4239 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4240 4241 /* reset ring buffer */ 4242 ring->wptr = 0; 4243 amdgpu_ring_clear_ring(ring); 4244 4245 mutex_lock(&adev->srbm_mutex); 4246 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4247 gfx_v11_0_kiq_init_register(ring); 4248 soc21_grbm_select(adev, 0, 0, 0, 0); 4249 mutex_unlock(&adev->srbm_mutex); 4250 } else { 4251 memset((void *)mqd, 0, sizeof(*mqd)); 4252 mutex_lock(&adev->srbm_mutex); 4253 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4254 amdgpu_ring_init_mqd(ring); 4255 gfx_v11_0_kiq_init_register(ring); 4256 soc21_grbm_select(adev, 0, 0, 0, 0); 4257 mutex_unlock(&adev->srbm_mutex); 4258 4259 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4260 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4261 } 4262 4263 return 0; 4264 } 4265 4266 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4267 { 4268 struct amdgpu_device *adev = ring->adev; 4269 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4270 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4271 4272 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4273 memset((void *)mqd, 0, sizeof(*mqd)); 4274 mutex_lock(&adev->srbm_mutex); 4275 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4276 amdgpu_ring_init_mqd(ring); 4277 soc21_grbm_select(adev, 0, 0, 0, 0); 4278 mutex_unlock(&adev->srbm_mutex); 4279 4280 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4281 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4282 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4283 /* reset MQD to a clean status */ 4284 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4285 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4286 4287 /* reset ring buffer */ 4288 ring->wptr = 0; 4289 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4290 amdgpu_ring_clear_ring(ring); 4291 } else { 4292 amdgpu_ring_clear_ring(ring); 4293 } 4294 4295 return 0; 4296 } 4297 4298 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4299 { 4300 struct amdgpu_ring *ring; 4301 int r; 4302 4303 ring = &adev->gfx.kiq.ring; 4304 4305 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4306 if (unlikely(r != 0)) 4307 return r; 4308 4309 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4310 if (unlikely(r != 0)) 4311 return r; 4312 4313 gfx_v11_0_kiq_init_queue(ring); 4314 amdgpu_bo_kunmap(ring->mqd_obj); 4315 ring->mqd_ptr = NULL; 4316 amdgpu_bo_unreserve(ring->mqd_obj); 4317 ring->sched.ready = true; 4318 return 0; 4319 } 4320 4321 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4322 { 4323 struct amdgpu_ring *ring = NULL; 4324 int r = 0, i; 4325 4326 if (!amdgpu_async_gfx_ring) 4327 gfx_v11_0_cp_compute_enable(adev, true); 4328 4329 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4330 ring = &adev->gfx.compute_ring[i]; 4331 4332 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4333 if (unlikely(r != 0)) 4334 goto done; 4335 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4336 if (!r) { 4337 r = gfx_v11_0_kcq_init_queue(ring); 4338 amdgpu_bo_kunmap(ring->mqd_obj); 4339 ring->mqd_ptr = NULL; 4340 } 4341 amdgpu_bo_unreserve(ring->mqd_obj); 4342 if (r) 4343 goto done; 4344 } 4345 4346 r = amdgpu_gfx_enable_kcq(adev); 4347 done: 4348 return r; 4349 } 4350 4351 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4352 { 4353 int r, i; 4354 struct amdgpu_ring *ring; 4355 4356 if (!(adev->flags & AMD_IS_APU)) 4357 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4358 4359 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4360 /* legacy firmware loading */ 4361 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4362 if (r) 4363 return r; 4364 4365 if (adev->gfx.rs64_enable) 4366 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4367 else 4368 r = gfx_v11_0_cp_compute_load_microcode(adev); 4369 if (r) 4370 return r; 4371 } 4372 4373 gfx_v11_0_cp_set_doorbell_range(adev); 4374 4375 if (amdgpu_async_gfx_ring) { 4376 gfx_v11_0_cp_compute_enable(adev, true); 4377 gfx_v11_0_cp_gfx_enable(adev, true); 4378 } 4379 4380 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4381 r = amdgpu_mes_kiq_hw_init(adev); 4382 else 4383 r = gfx_v11_0_kiq_resume(adev); 4384 if (r) 4385 return r; 4386 4387 r = gfx_v11_0_kcq_resume(adev); 4388 if (r) 4389 return r; 4390 4391 if (!amdgpu_async_gfx_ring) { 4392 r = gfx_v11_0_cp_gfx_resume(adev); 4393 if (r) 4394 return r; 4395 } else { 4396 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4397 if (r) 4398 return r; 4399 } 4400 4401 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4402 ring = &adev->gfx.gfx_ring[i]; 4403 r = amdgpu_ring_test_helper(ring); 4404 if (r) 4405 return r; 4406 } 4407 4408 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4409 ring = &adev->gfx.compute_ring[i]; 4410 r = amdgpu_ring_test_helper(ring); 4411 if (r) 4412 return r; 4413 } 4414 4415 return 0; 4416 } 4417 4418 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4419 { 4420 gfx_v11_0_cp_gfx_enable(adev, enable); 4421 gfx_v11_0_cp_compute_enable(adev, enable); 4422 } 4423 4424 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4425 { 4426 int r; 4427 bool value; 4428 4429 r = adev->gfxhub.funcs->gart_enable(adev); 4430 if (r) 4431 return r; 4432 4433 adev->hdp.funcs->flush_hdp(adev, NULL); 4434 4435 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4436 false : true; 4437 4438 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4439 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 4440 4441 return 0; 4442 } 4443 4444 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4445 { 4446 u32 tmp; 4447 4448 /* select RS64 */ 4449 if (adev->gfx.rs64_enable) { 4450 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4451 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4452 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4453 4454 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4455 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4456 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4457 } 4458 4459 if (amdgpu_emu_mode == 1) 4460 msleep(100); 4461 } 4462 4463 static int get_gb_addr_config(struct amdgpu_device * adev) 4464 { 4465 u32 gb_addr_config; 4466 4467 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4468 if (gb_addr_config == 0) 4469 return -EINVAL; 4470 4471 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4472 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4473 4474 adev->gfx.config.gb_addr_config = gb_addr_config; 4475 4476 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4477 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4478 GB_ADDR_CONFIG, NUM_PIPES); 4479 4480 adev->gfx.config.max_tile_pipes = 4481 adev->gfx.config.gb_addr_config_fields.num_pipes; 4482 4483 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4484 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4485 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4486 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4487 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4488 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4489 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4490 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4491 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4492 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4493 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4494 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4495 4496 return 0; 4497 } 4498 4499 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4500 { 4501 uint32_t data; 4502 4503 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4504 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4505 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4506 4507 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4508 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4509 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4510 } 4511 4512 static int gfx_v11_0_hw_init(void *handle) 4513 { 4514 int r; 4515 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4516 4517 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4518 if (adev->gfx.imu.funcs) { 4519 /* RLC autoload sequence 1: Program rlc ram */ 4520 if (adev->gfx.imu.funcs->program_rlc_ram) 4521 adev->gfx.imu.funcs->program_rlc_ram(adev); 4522 } 4523 /* rlc autoload firmware */ 4524 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4525 if (r) 4526 return r; 4527 } else { 4528 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4529 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4530 if (adev->gfx.imu.funcs->load_microcode) 4531 adev->gfx.imu.funcs->load_microcode(adev); 4532 if (adev->gfx.imu.funcs->setup_imu) 4533 adev->gfx.imu.funcs->setup_imu(adev); 4534 if (adev->gfx.imu.funcs->start_imu) 4535 adev->gfx.imu.funcs->start_imu(adev); 4536 } 4537 } 4538 } 4539 4540 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4541 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4542 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4543 if (r) { 4544 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4545 return r; 4546 } 4547 } 4548 4549 adev->gfx.is_poweron = true; 4550 4551 if(get_gb_addr_config(adev)) 4552 DRM_WARN("Invalid gb_addr_config !\n"); 4553 4554 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4555 adev->gfx.rs64_enable) 4556 gfx_v11_0_config_gfx_rs64(adev); 4557 4558 r = gfx_v11_0_gfxhub_enable(adev); 4559 if (r) 4560 return r; 4561 4562 if (!amdgpu_emu_mode) 4563 gfx_v11_0_init_golden_registers(adev); 4564 4565 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4566 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4567 /** 4568 * For gfx 11, rlc firmware loading relies on smu firmware is 4569 * loaded firstly, so in direct type, it has to load smc ucode 4570 * here before rlc. 4571 */ 4572 if (!(adev->flags & AMD_IS_APU)) { 4573 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4574 if (r) 4575 return r; 4576 } 4577 } 4578 4579 gfx_v11_0_constants_init(adev); 4580 4581 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4582 gfx_v11_0_select_cp_fw_arch(adev); 4583 4584 adev->nbio.funcs->gc_doorbell_init(adev); 4585 4586 r = gfx_v11_0_rlc_resume(adev); 4587 if (r) 4588 return r; 4589 4590 /* 4591 * init golden registers and rlc resume may override some registers, 4592 * reconfig them here 4593 */ 4594 gfx_v11_0_tcp_harvest(adev); 4595 4596 r = gfx_v11_0_cp_resume(adev); 4597 if (r) 4598 return r; 4599 4600 return r; 4601 } 4602 4603 #ifndef BRING_UP_DEBUG 4604 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev) 4605 { 4606 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4607 struct amdgpu_ring *kiq_ring = &kiq->ring; 4608 int i, r = 0; 4609 4610 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4611 return -EINVAL; 4612 4613 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 4614 adev->gfx.num_gfx_rings)) 4615 return -ENOMEM; 4616 4617 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4618 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 4619 PREEMPT_QUEUES, 0, 0); 4620 4621 if (adev->gfx.kiq.ring.sched.ready) 4622 r = amdgpu_ring_test_helper(kiq_ring); 4623 4624 return r; 4625 } 4626 #endif 4627 4628 static int gfx_v11_0_hw_fini(void *handle) 4629 { 4630 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4631 int r; 4632 uint32_t tmp; 4633 4634 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4635 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4636 4637 if (!adev->no_hw_access) { 4638 #ifndef BRING_UP_DEBUG 4639 if (amdgpu_async_gfx_ring) { 4640 r = gfx_v11_0_kiq_disable_kgq(adev); 4641 if (r) 4642 DRM_ERROR("KGQ disable failed\n"); 4643 } 4644 #endif 4645 if (amdgpu_gfx_disable_kcq(adev)) 4646 DRM_ERROR("KCQ disable failed\n"); 4647 4648 amdgpu_mes_kiq_hw_fini(adev); 4649 } 4650 4651 if (amdgpu_sriov_vf(adev)) { 4652 gfx_v11_0_cp_gfx_enable(adev, false); 4653 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 4654 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 4655 tmp &= 0xffffff00; 4656 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 4657 4658 return 0; 4659 } 4660 gfx_v11_0_cp_enable(adev, false); 4661 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4662 4663 adev->gfxhub.funcs->gart_disable(adev); 4664 4665 adev->gfx.is_poweron = false; 4666 4667 return 0; 4668 } 4669 4670 static int gfx_v11_0_suspend(void *handle) 4671 { 4672 return gfx_v11_0_hw_fini(handle); 4673 } 4674 4675 static int gfx_v11_0_resume(void *handle) 4676 { 4677 return gfx_v11_0_hw_init(handle); 4678 } 4679 4680 static bool gfx_v11_0_is_idle(void *handle) 4681 { 4682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4683 4684 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4685 GRBM_STATUS, GUI_ACTIVE)) 4686 return false; 4687 else 4688 return true; 4689 } 4690 4691 static int gfx_v11_0_wait_for_idle(void *handle) 4692 { 4693 unsigned i; 4694 u32 tmp; 4695 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4696 4697 for (i = 0; i < adev->usec_timeout; i++) { 4698 /* read MC_STATUS */ 4699 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4700 GRBM_STATUS__GUI_ACTIVE_MASK; 4701 4702 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4703 return 0; 4704 udelay(1); 4705 } 4706 return -ETIMEDOUT; 4707 } 4708 4709 static int gfx_v11_0_soft_reset(void *handle) 4710 { 4711 u32 grbm_soft_reset = 0; 4712 u32 tmp; 4713 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4714 4715 /* GRBM_STATUS */ 4716 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS); 4717 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4718 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4719 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 4720 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 4721 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 4722 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4723 GRBM_SOFT_RESET, SOFT_RESET_CP, 4724 1); 4725 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4726 GRBM_SOFT_RESET, SOFT_RESET_GFX, 4727 1); 4728 } 4729 4730 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4731 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4732 GRBM_SOFT_RESET, SOFT_RESET_CP, 4733 1); 4734 } 4735 4736 /* GRBM_STATUS2 */ 4737 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS2); 4738 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 4739 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4740 GRBM_SOFT_RESET, 4741 SOFT_RESET_RLC, 4742 1); 4743 4744 if (grbm_soft_reset) { 4745 /* stop the rlc */ 4746 gfx_v11_0_rlc_stop(adev); 4747 4748 /* Disable GFX parsing/prefetching */ 4749 gfx_v11_0_cp_gfx_enable(adev, false); 4750 4751 /* Disable MEC parsing/prefetching */ 4752 gfx_v11_0_cp_compute_enable(adev, false); 4753 4754 if (grbm_soft_reset) { 4755 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4756 tmp |= grbm_soft_reset; 4757 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4758 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 4759 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4760 4761 udelay(50); 4762 4763 tmp &= ~grbm_soft_reset; 4764 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 4765 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4766 } 4767 4768 /* Wait a little for things to settle down */ 4769 udelay(50); 4770 } 4771 return 0; 4772 } 4773 4774 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4775 { 4776 uint64_t clock; 4777 4778 amdgpu_gfx_off_ctrl(adev, false); 4779 mutex_lock(&adev->gfx.gpu_clock_mutex); 4780 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) | 4781 ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL); 4782 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4783 amdgpu_gfx_off_ctrl(adev, true); 4784 return clock; 4785 } 4786 4787 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4788 uint32_t vmid, 4789 uint32_t gds_base, uint32_t gds_size, 4790 uint32_t gws_base, uint32_t gws_size, 4791 uint32_t oa_base, uint32_t oa_size) 4792 { 4793 struct amdgpu_device *adev = ring->adev; 4794 4795 /* GDS Base */ 4796 gfx_v11_0_write_data_to_reg(ring, 0, false, 4797 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4798 gds_base); 4799 4800 /* GDS Size */ 4801 gfx_v11_0_write_data_to_reg(ring, 0, false, 4802 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4803 gds_size); 4804 4805 /* GWS */ 4806 gfx_v11_0_write_data_to_reg(ring, 0, false, 4807 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4808 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4809 4810 /* OA */ 4811 gfx_v11_0_write_data_to_reg(ring, 0, false, 4812 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4813 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4814 } 4815 4816 static int gfx_v11_0_early_init(void *handle) 4817 { 4818 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4819 4820 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4821 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4822 AMDGPU_MAX_COMPUTE_RINGS); 4823 4824 gfx_v11_0_set_kiq_pm4_funcs(adev); 4825 gfx_v11_0_set_ring_funcs(adev); 4826 gfx_v11_0_set_irq_funcs(adev); 4827 gfx_v11_0_set_gds_init(adev); 4828 gfx_v11_0_set_rlc_funcs(adev); 4829 gfx_v11_0_set_mqd_funcs(adev); 4830 gfx_v11_0_set_imu_funcs(adev); 4831 4832 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4833 4834 return 0; 4835 } 4836 4837 static int gfx_v11_0_late_init(void *handle) 4838 { 4839 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4840 int r; 4841 4842 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4843 if (r) 4844 return r; 4845 4846 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4847 if (r) 4848 return r; 4849 4850 return 0; 4851 } 4852 4853 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4854 { 4855 uint32_t rlc_cntl; 4856 4857 /* if RLC is not enabled, do nothing */ 4858 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4859 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4860 } 4861 4862 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev) 4863 { 4864 uint32_t data; 4865 unsigned i; 4866 4867 data = RLC_SAFE_MODE__CMD_MASK; 4868 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4869 4870 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4871 4872 /* wait for RLC_SAFE_MODE */ 4873 for (i = 0; i < adev->usec_timeout; i++) { 4874 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4875 RLC_SAFE_MODE, CMD)) 4876 break; 4877 udelay(1); 4878 } 4879 } 4880 4881 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev) 4882 { 4883 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4884 } 4885 4886 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 4887 bool enable) 4888 { 4889 uint32_t def, data; 4890 4891 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4892 return; 4893 4894 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4895 4896 if (enable) 4897 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4898 else 4899 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4900 4901 if (def != data) 4902 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4903 } 4904 4905 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 4906 bool enable) 4907 { 4908 uint32_t def, data; 4909 4910 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4911 return; 4912 4913 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4914 4915 if (enable) 4916 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4917 else 4918 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4919 4920 if (def != data) 4921 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4922 } 4923 4924 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 4925 bool enable) 4926 { 4927 uint32_t def, data; 4928 4929 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4930 return; 4931 4932 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4933 4934 if (enable) 4935 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4936 else 4937 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4938 4939 if (def != data) 4940 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4941 } 4942 4943 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4944 bool enable) 4945 { 4946 uint32_t data, def; 4947 4948 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4949 return; 4950 4951 /* It is disabled by HW by default */ 4952 if (enable) { 4953 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4954 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4955 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4956 4957 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4958 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4959 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4960 4961 if (def != data) 4962 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4963 } 4964 } else { 4965 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4966 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4967 4968 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4969 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4970 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4971 4972 if (def != data) 4973 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4974 } 4975 } 4976 } 4977 4978 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4979 bool enable) 4980 { 4981 uint32_t def, data; 4982 4983 if (!(adev->cg_flags & 4984 (AMD_CG_SUPPORT_GFX_CGCG | 4985 AMD_CG_SUPPORT_GFX_CGLS | 4986 AMD_CG_SUPPORT_GFX_3D_CGCG | 4987 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4988 return; 4989 4990 if (enable) { 4991 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4992 4993 /* unset CGCG override */ 4994 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4995 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4996 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4997 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4998 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4999 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5000 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5001 5002 /* update CGCG override bits */ 5003 if (def != data) 5004 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5005 5006 /* enable cgcg FSM(0x0000363F) */ 5007 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5008 5009 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5010 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5011 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5012 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5013 } 5014 5015 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5016 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5017 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5018 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5019 } 5020 5021 if (def != data) 5022 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5023 5024 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5025 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5026 5027 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5028 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5029 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5030 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5031 } 5032 5033 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5034 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5035 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5036 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5037 } 5038 5039 if (def != data) 5040 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5041 5042 /* set IDLE_POLL_COUNT(0x00900100) */ 5043 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5044 5045 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5046 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5047 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5048 5049 if (def != data) 5050 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5051 5052 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5053 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5054 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5055 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5056 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5057 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5058 5059 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5060 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5061 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5062 5063 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5064 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5065 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5066 } else { 5067 /* Program RLC_CGCG_CGLS_CTRL */ 5068 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5069 5070 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5071 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5072 5073 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5074 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5075 5076 if (def != data) 5077 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5078 5079 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5080 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5081 5082 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5083 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5084 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5085 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5086 5087 if (def != data) 5088 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5089 5090 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5091 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5092 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5093 5094 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5095 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5096 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5097 } 5098 } 5099 5100 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5101 bool enable) 5102 { 5103 amdgpu_gfx_rlc_enter_safe_mode(adev); 5104 5105 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5106 5107 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5108 5109 gfx_v11_0_update_repeater_fgcg(adev, enable); 5110 5111 gfx_v11_0_update_sram_fgcg(adev, enable); 5112 5113 gfx_v11_0_update_perf_clk(adev, enable); 5114 5115 if (adev->cg_flags & 5116 (AMD_CG_SUPPORT_GFX_MGCG | 5117 AMD_CG_SUPPORT_GFX_CGLS | 5118 AMD_CG_SUPPORT_GFX_CGCG | 5119 AMD_CG_SUPPORT_GFX_3D_CGCG | 5120 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5121 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5122 5123 amdgpu_gfx_rlc_exit_safe_mode(adev); 5124 5125 return 0; 5126 } 5127 5128 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 5129 { 5130 u32 reg, data; 5131 5132 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5133 if (amdgpu_sriov_is_pp_one_vf(adev)) 5134 data = RREG32_NO_KIQ(reg); 5135 else 5136 data = RREG32(reg); 5137 5138 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5139 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5140 5141 if (amdgpu_sriov_is_pp_one_vf(adev)) 5142 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5143 else 5144 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5145 } 5146 5147 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5148 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5149 .set_safe_mode = gfx_v11_0_set_safe_mode, 5150 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5151 .init = gfx_v11_0_rlc_init, 5152 .get_csb_size = gfx_v11_0_get_csb_size, 5153 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5154 .resume = gfx_v11_0_rlc_resume, 5155 .stop = gfx_v11_0_rlc_stop, 5156 .reset = gfx_v11_0_rlc_reset, 5157 .start = gfx_v11_0_rlc_start, 5158 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5159 }; 5160 5161 static int gfx_v11_0_set_powergating_state(void *handle, 5162 enum amd_powergating_state state) 5163 { 5164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5165 bool enable = (state == AMD_PG_STATE_GATE); 5166 5167 if (amdgpu_sriov_vf(adev)) 5168 return 0; 5169 5170 switch (adev->ip_versions[GC_HWIP][0]) { 5171 case IP_VERSION(11, 0, 0): 5172 amdgpu_gfx_off_ctrl(adev, enable); 5173 break; 5174 default: 5175 break; 5176 } 5177 5178 return 0; 5179 } 5180 5181 static int gfx_v11_0_set_clockgating_state(void *handle, 5182 enum amd_clockgating_state state) 5183 { 5184 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5185 5186 if (amdgpu_sriov_vf(adev)) 5187 return 0; 5188 5189 switch (adev->ip_versions[GC_HWIP][0]) { 5190 case IP_VERSION(11, 0, 0): 5191 case IP_VERSION(11, 0, 2): 5192 gfx_v11_0_update_gfx_clock_gating(adev, 5193 state == AMD_CG_STATE_GATE); 5194 break; 5195 default: 5196 break; 5197 } 5198 5199 return 0; 5200 } 5201 5202 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5203 { 5204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5205 int data; 5206 5207 /* AMD_CG_SUPPORT_GFX_MGCG */ 5208 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5209 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5210 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5211 5212 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5213 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5214 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5215 5216 /* AMD_CG_SUPPORT_GFX_FGCG */ 5217 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5218 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5219 5220 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5221 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5222 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5223 5224 /* AMD_CG_SUPPORT_GFX_CGCG */ 5225 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5226 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5227 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5228 5229 /* AMD_CG_SUPPORT_GFX_CGLS */ 5230 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5231 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5232 5233 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5234 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5235 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5236 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5237 5238 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5239 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5240 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5241 } 5242 5243 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5244 { 5245 /* gfx11 is 32bit rptr*/ 5246 return *(uint32_t *)ring->rptr_cpu_addr; 5247 } 5248 5249 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5250 { 5251 struct amdgpu_device *adev = ring->adev; 5252 u64 wptr; 5253 5254 /* XXX check if swapping is necessary on BE */ 5255 if (ring->use_doorbell) { 5256 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5257 } else { 5258 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5259 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5260 } 5261 5262 return wptr; 5263 } 5264 5265 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5266 { 5267 struct amdgpu_device *adev = ring->adev; 5268 5269 if (ring->use_doorbell) { 5270 /* XXX check if swapping is necessary on BE */ 5271 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5272 WDOORBELL64(ring->doorbell_index, ring->wptr); 5273 } else { 5274 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5275 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5276 } 5277 } 5278 5279 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5280 { 5281 /* gfx11 hardware is 32bit rptr */ 5282 return *(uint32_t *)ring->rptr_cpu_addr; 5283 } 5284 5285 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5286 { 5287 u64 wptr; 5288 5289 /* XXX check if swapping is necessary on BE */ 5290 if (ring->use_doorbell) 5291 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5292 else 5293 BUG(); 5294 return wptr; 5295 } 5296 5297 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5298 { 5299 struct amdgpu_device *adev = ring->adev; 5300 5301 /* XXX check if swapping is necessary on BE */ 5302 if (ring->use_doorbell) { 5303 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5304 WDOORBELL64(ring->doorbell_index, ring->wptr); 5305 } else { 5306 BUG(); /* only DOORBELL method supported on gfx11 now */ 5307 } 5308 } 5309 5310 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5311 { 5312 struct amdgpu_device *adev = ring->adev; 5313 u32 ref_and_mask, reg_mem_engine; 5314 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5315 5316 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5317 switch (ring->me) { 5318 case 1: 5319 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5320 break; 5321 case 2: 5322 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5323 break; 5324 default: 5325 return; 5326 } 5327 reg_mem_engine = 0; 5328 } else { 5329 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5330 reg_mem_engine = 1; /* pfp */ 5331 } 5332 5333 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5334 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5335 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5336 ref_and_mask, ref_and_mask, 0x20); 5337 } 5338 5339 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5340 struct amdgpu_job *job, 5341 struct amdgpu_ib *ib, 5342 uint32_t flags) 5343 { 5344 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5345 u32 header, control = 0; 5346 5347 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5348 5349 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5350 5351 control |= ib->length_dw | (vmid << 24); 5352 5353 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5354 control |= INDIRECT_BUFFER_PRE_ENB(1); 5355 5356 if (flags & AMDGPU_IB_PREEMPTED) 5357 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5358 5359 if (vmid) 5360 gfx_v11_0_ring_emit_de_meta(ring, 5361 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5362 } 5363 5364 if (ring->is_mes_queue) 5365 /* inherit vmid from mqd */ 5366 control |= 0x400000; 5367 5368 amdgpu_ring_write(ring, header); 5369 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5370 amdgpu_ring_write(ring, 5371 #ifdef __BIG_ENDIAN 5372 (2 << 0) | 5373 #endif 5374 lower_32_bits(ib->gpu_addr)); 5375 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5376 amdgpu_ring_write(ring, control); 5377 } 5378 5379 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5380 struct amdgpu_job *job, 5381 struct amdgpu_ib *ib, 5382 uint32_t flags) 5383 { 5384 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5385 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5386 5387 if (ring->is_mes_queue) 5388 /* inherit vmid from mqd */ 5389 control |= 0x40000000; 5390 5391 /* Currently, there is a high possibility to get wave ID mismatch 5392 * between ME and GDS, leading to a hw deadlock, because ME generates 5393 * different wave IDs than the GDS expects. This situation happens 5394 * randomly when at least 5 compute pipes use GDS ordered append. 5395 * The wave IDs generated by ME are also wrong after suspend/resume. 5396 * Those are probably bugs somewhere else in the kernel driver. 5397 * 5398 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5399 * GDS to 0 for this ring (me/pipe). 5400 */ 5401 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5402 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5403 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5404 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5405 } 5406 5407 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5408 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5409 amdgpu_ring_write(ring, 5410 #ifdef __BIG_ENDIAN 5411 (2 << 0) | 5412 #endif 5413 lower_32_bits(ib->gpu_addr)); 5414 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5415 amdgpu_ring_write(ring, control); 5416 } 5417 5418 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5419 u64 seq, unsigned flags) 5420 { 5421 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5422 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5423 5424 /* RELEASE_MEM - flush caches, send int */ 5425 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5426 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5427 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5428 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5429 PACKET3_RELEASE_MEM_GCR_GL2_US | 5430 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5431 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5432 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5433 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5434 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5435 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5436 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5437 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5438 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5439 5440 /* 5441 * the address should be Qword aligned if 64bit write, Dword 5442 * aligned if only send 32bit data low (discard data high) 5443 */ 5444 if (write64bit) 5445 BUG_ON(addr & 0x7); 5446 else 5447 BUG_ON(addr & 0x3); 5448 amdgpu_ring_write(ring, lower_32_bits(addr)); 5449 amdgpu_ring_write(ring, upper_32_bits(addr)); 5450 amdgpu_ring_write(ring, lower_32_bits(seq)); 5451 amdgpu_ring_write(ring, upper_32_bits(seq)); 5452 amdgpu_ring_write(ring, ring->is_mes_queue ? 5453 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5454 } 5455 5456 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5457 { 5458 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5459 uint32_t seq = ring->fence_drv.sync_seq; 5460 uint64_t addr = ring->fence_drv.gpu_addr; 5461 5462 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5463 upper_32_bits(addr), seq, 0xffffffff, 4); 5464 } 5465 5466 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5467 uint16_t pasid, uint32_t flush_type, 5468 bool all_hub, uint8_t dst_sel) 5469 { 5470 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5471 amdgpu_ring_write(ring, 5472 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5473 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5474 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5475 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5476 } 5477 5478 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5479 unsigned vmid, uint64_t pd_addr) 5480 { 5481 if (ring->is_mes_queue) 5482 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5483 else 5484 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5485 5486 /* compute doesn't have PFP */ 5487 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5488 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5489 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5490 amdgpu_ring_write(ring, 0x0); 5491 } 5492 } 5493 5494 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5495 u64 seq, unsigned int flags) 5496 { 5497 struct amdgpu_device *adev = ring->adev; 5498 5499 /* we only allocate 32bit for each seq wb address */ 5500 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5501 5502 /* write fence seq to the "addr" */ 5503 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5504 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5505 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5506 amdgpu_ring_write(ring, lower_32_bits(addr)); 5507 amdgpu_ring_write(ring, upper_32_bits(addr)); 5508 amdgpu_ring_write(ring, lower_32_bits(seq)); 5509 5510 if (flags & AMDGPU_FENCE_FLAG_INT) { 5511 /* set register to trigger INT */ 5512 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5513 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5514 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5515 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5516 amdgpu_ring_write(ring, 0); 5517 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5518 } 5519 } 5520 5521 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5522 uint32_t flags) 5523 { 5524 uint32_t dw2 = 0; 5525 5526 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5527 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5528 /* set load_global_config & load_global_uconfig */ 5529 dw2 |= 0x8001; 5530 /* set load_cs_sh_regs */ 5531 dw2 |= 0x01000000; 5532 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5533 dw2 |= 0x10002; 5534 } 5535 5536 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5537 amdgpu_ring_write(ring, dw2); 5538 amdgpu_ring_write(ring, 0); 5539 } 5540 5541 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5542 { 5543 unsigned ret; 5544 5545 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5546 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5547 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5548 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5549 ret = ring->wptr & ring->buf_mask; 5550 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5551 5552 return ret; 5553 } 5554 5555 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5556 { 5557 unsigned cur; 5558 BUG_ON(offset > ring->buf_mask); 5559 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5560 5561 cur = (ring->wptr - 1) & ring->buf_mask; 5562 if (likely(cur > offset)) 5563 ring->ring[offset] = cur - offset; 5564 else 5565 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5566 } 5567 5568 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5569 { 5570 int i, r = 0; 5571 struct amdgpu_device *adev = ring->adev; 5572 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5573 struct amdgpu_ring *kiq_ring = &kiq->ring; 5574 unsigned long flags; 5575 5576 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5577 return -EINVAL; 5578 5579 spin_lock_irqsave(&kiq->ring_lock, flags); 5580 5581 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5582 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5583 return -ENOMEM; 5584 } 5585 5586 /* assert preemption condition */ 5587 amdgpu_ring_set_preempt_cond_exec(ring, false); 5588 5589 /* assert IB preemption, emit the trailing fence */ 5590 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5591 ring->trail_fence_gpu_addr, 5592 ++ring->trail_seq); 5593 amdgpu_ring_commit(kiq_ring); 5594 5595 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5596 5597 /* poll the trailing fence */ 5598 for (i = 0; i < adev->usec_timeout; i++) { 5599 if (ring->trail_seq == 5600 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5601 break; 5602 udelay(1); 5603 } 5604 5605 if (i >= adev->usec_timeout) { 5606 r = -EINVAL; 5607 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5608 } 5609 5610 /* deassert preemption condition */ 5611 amdgpu_ring_set_preempt_cond_exec(ring, true); 5612 return r; 5613 } 5614 5615 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5616 { 5617 struct amdgpu_device *adev = ring->adev; 5618 struct v10_de_ib_state de_payload = {0}; 5619 uint64_t offset, gds_addr, de_payload_gpu_addr; 5620 void *de_payload_cpu_addr; 5621 int cnt; 5622 5623 if (ring->is_mes_queue) { 5624 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5625 gfx[0].gfx_meta_data) + 5626 offsetof(struct v10_gfx_meta_data, de_payload); 5627 de_payload_gpu_addr = 5628 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5629 de_payload_cpu_addr = 5630 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5631 5632 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5633 gfx[0].gds_backup) + 5634 offsetof(struct v10_gfx_meta_data, de_payload); 5635 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5636 } else { 5637 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5638 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5639 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5640 5641 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5642 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5643 PAGE_SIZE); 5644 } 5645 5646 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5647 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5648 5649 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5650 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5651 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5652 WRITE_DATA_DST_SEL(8) | 5653 WR_CONFIRM) | 5654 WRITE_DATA_CACHE_POLICY(0)); 5655 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5656 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5657 5658 if (resume) 5659 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5660 sizeof(de_payload) >> 2); 5661 else 5662 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5663 sizeof(de_payload) >> 2); 5664 } 5665 5666 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5667 bool secure) 5668 { 5669 uint32_t v = secure ? FRAME_TMZ : 0; 5670 5671 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5672 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5673 } 5674 5675 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5676 uint32_t reg_val_offs) 5677 { 5678 struct amdgpu_device *adev = ring->adev; 5679 5680 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5681 amdgpu_ring_write(ring, 0 | /* src: register*/ 5682 (5 << 8) | /* dst: memory */ 5683 (1 << 20)); /* write confirm */ 5684 amdgpu_ring_write(ring, reg); 5685 amdgpu_ring_write(ring, 0); 5686 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5687 reg_val_offs * 4)); 5688 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5689 reg_val_offs * 4)); 5690 } 5691 5692 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5693 uint32_t val) 5694 { 5695 uint32_t cmd = 0; 5696 5697 switch (ring->funcs->type) { 5698 case AMDGPU_RING_TYPE_GFX: 5699 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5700 break; 5701 case AMDGPU_RING_TYPE_KIQ: 5702 cmd = (1 << 16); /* no inc addr */ 5703 break; 5704 default: 5705 cmd = WR_CONFIRM; 5706 break; 5707 } 5708 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5709 amdgpu_ring_write(ring, cmd); 5710 amdgpu_ring_write(ring, reg); 5711 amdgpu_ring_write(ring, 0); 5712 amdgpu_ring_write(ring, val); 5713 } 5714 5715 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5716 uint32_t val, uint32_t mask) 5717 { 5718 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5719 } 5720 5721 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5722 uint32_t reg0, uint32_t reg1, 5723 uint32_t ref, uint32_t mask) 5724 { 5725 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5726 5727 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5728 ref, mask, 0x20); 5729 } 5730 5731 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5732 unsigned vmid) 5733 { 5734 struct amdgpu_device *adev = ring->adev; 5735 uint32_t value = 0; 5736 5737 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5738 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5739 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5740 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5741 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5742 } 5743 5744 static void 5745 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5746 uint32_t me, uint32_t pipe, 5747 enum amdgpu_interrupt_state state) 5748 { 5749 uint32_t cp_int_cntl, cp_int_cntl_reg; 5750 5751 if (!me) { 5752 switch (pipe) { 5753 case 0: 5754 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5755 break; 5756 case 1: 5757 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5758 break; 5759 default: 5760 DRM_DEBUG("invalid pipe %d\n", pipe); 5761 return; 5762 } 5763 } else { 5764 DRM_DEBUG("invalid me %d\n", me); 5765 return; 5766 } 5767 5768 switch (state) { 5769 case AMDGPU_IRQ_STATE_DISABLE: 5770 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5771 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5772 TIME_STAMP_INT_ENABLE, 0); 5773 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5774 GENERIC0_INT_ENABLE, 0); 5775 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5776 break; 5777 case AMDGPU_IRQ_STATE_ENABLE: 5778 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5779 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5780 TIME_STAMP_INT_ENABLE, 1); 5781 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5782 GENERIC0_INT_ENABLE, 1); 5783 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5784 break; 5785 default: 5786 break; 5787 } 5788 } 5789 5790 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5791 int me, int pipe, 5792 enum amdgpu_interrupt_state state) 5793 { 5794 u32 mec_int_cntl, mec_int_cntl_reg; 5795 5796 /* 5797 * amdgpu controls only the first MEC. That's why this function only 5798 * handles the setting of interrupts for this specific MEC. All other 5799 * pipes' interrupts are set by amdkfd. 5800 */ 5801 5802 if (me == 1) { 5803 switch (pipe) { 5804 case 0: 5805 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5806 break; 5807 case 1: 5808 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5809 break; 5810 case 2: 5811 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5812 break; 5813 case 3: 5814 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5815 break; 5816 default: 5817 DRM_DEBUG("invalid pipe %d\n", pipe); 5818 return; 5819 } 5820 } else { 5821 DRM_DEBUG("invalid me %d\n", me); 5822 return; 5823 } 5824 5825 switch (state) { 5826 case AMDGPU_IRQ_STATE_DISABLE: 5827 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5828 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5829 TIME_STAMP_INT_ENABLE, 0); 5830 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5831 GENERIC0_INT_ENABLE, 0); 5832 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5833 break; 5834 case AMDGPU_IRQ_STATE_ENABLE: 5835 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5836 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5837 TIME_STAMP_INT_ENABLE, 1); 5838 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5839 GENERIC0_INT_ENABLE, 1); 5840 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5841 break; 5842 default: 5843 break; 5844 } 5845 } 5846 5847 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5848 struct amdgpu_irq_src *src, 5849 unsigned type, 5850 enum amdgpu_interrupt_state state) 5851 { 5852 switch (type) { 5853 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5854 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 5855 break; 5856 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 5857 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 5858 break; 5859 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5860 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5861 break; 5862 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5863 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5864 break; 5865 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5866 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5867 break; 5868 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5869 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5870 break; 5871 default: 5872 break; 5873 } 5874 return 0; 5875 } 5876 5877 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 5878 struct amdgpu_irq_src *source, 5879 struct amdgpu_iv_entry *entry) 5880 { 5881 int i; 5882 u8 me_id, pipe_id, queue_id; 5883 struct amdgpu_ring *ring; 5884 uint32_t mes_queue_id = entry->src_data[0]; 5885 5886 DRM_DEBUG("IH: CP EOP\n"); 5887 5888 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 5889 struct amdgpu_mes_queue *queue; 5890 5891 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 5892 5893 spin_lock(&adev->mes.queue_id_lock); 5894 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 5895 if (queue) { 5896 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 5897 amdgpu_fence_process(queue->ring); 5898 } 5899 spin_unlock(&adev->mes.queue_id_lock); 5900 } else { 5901 me_id = (entry->ring_id & 0x0c) >> 2; 5902 pipe_id = (entry->ring_id & 0x03) >> 0; 5903 queue_id = (entry->ring_id & 0x70) >> 4; 5904 5905 switch (me_id) { 5906 case 0: 5907 if (pipe_id == 0) 5908 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5909 else 5910 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5911 break; 5912 case 1: 5913 case 2: 5914 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5915 ring = &adev->gfx.compute_ring[i]; 5916 /* Per-queue interrupt is supported for MEC starting from VI. 5917 * The interrupt can only be enabled/disabled per pipe instead 5918 * of per queue. 5919 */ 5920 if ((ring->me == me_id) && 5921 (ring->pipe == pipe_id) && 5922 (ring->queue == queue_id)) 5923 amdgpu_fence_process(ring); 5924 } 5925 break; 5926 } 5927 } 5928 5929 return 0; 5930 } 5931 5932 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5933 struct amdgpu_irq_src *source, 5934 unsigned type, 5935 enum amdgpu_interrupt_state state) 5936 { 5937 switch (state) { 5938 case AMDGPU_IRQ_STATE_DISABLE: 5939 case AMDGPU_IRQ_STATE_ENABLE: 5940 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5941 PRIV_REG_INT_ENABLE, 5942 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5943 break; 5944 default: 5945 break; 5946 } 5947 5948 return 0; 5949 } 5950 5951 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5952 struct amdgpu_irq_src *source, 5953 unsigned type, 5954 enum amdgpu_interrupt_state state) 5955 { 5956 switch (state) { 5957 case AMDGPU_IRQ_STATE_DISABLE: 5958 case AMDGPU_IRQ_STATE_ENABLE: 5959 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5960 PRIV_INSTR_INT_ENABLE, 5961 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5962 break; 5963 default: 5964 break; 5965 } 5966 5967 return 0; 5968 } 5969 5970 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 5971 struct amdgpu_iv_entry *entry) 5972 { 5973 u8 me_id, pipe_id, queue_id; 5974 struct amdgpu_ring *ring; 5975 int i; 5976 5977 me_id = (entry->ring_id & 0x0c) >> 2; 5978 pipe_id = (entry->ring_id & 0x03) >> 0; 5979 queue_id = (entry->ring_id & 0x70) >> 4; 5980 5981 switch (me_id) { 5982 case 0: 5983 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5984 ring = &adev->gfx.gfx_ring[i]; 5985 /* we only enabled 1 gfx queue per pipe for now */ 5986 if (ring->me == me_id && ring->pipe == pipe_id) 5987 drm_sched_fault(&ring->sched); 5988 } 5989 break; 5990 case 1: 5991 case 2: 5992 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5993 ring = &adev->gfx.compute_ring[i]; 5994 if (ring->me == me_id && ring->pipe == pipe_id && 5995 ring->queue == queue_id) 5996 drm_sched_fault(&ring->sched); 5997 } 5998 break; 5999 default: 6000 BUG(); 6001 } 6002 } 6003 6004 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6005 struct amdgpu_irq_src *source, 6006 struct amdgpu_iv_entry *entry) 6007 { 6008 DRM_ERROR("Illegal register access in command stream\n"); 6009 gfx_v11_0_handle_priv_fault(adev, entry); 6010 return 0; 6011 } 6012 6013 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6014 struct amdgpu_irq_src *source, 6015 struct amdgpu_iv_entry *entry) 6016 { 6017 DRM_ERROR("Illegal instruction in command stream\n"); 6018 gfx_v11_0_handle_priv_fault(adev, entry); 6019 return 0; 6020 } 6021 6022 #if 0 6023 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6024 struct amdgpu_irq_src *src, 6025 unsigned int type, 6026 enum amdgpu_interrupt_state state) 6027 { 6028 uint32_t tmp, target; 6029 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 6030 6031 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6032 target += ring->pipe; 6033 6034 switch (type) { 6035 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6036 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6037 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6038 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6039 GENERIC2_INT_ENABLE, 0); 6040 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6041 6042 tmp = RREG32_SOC15_IP(GC, target); 6043 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6044 GENERIC2_INT_ENABLE, 0); 6045 WREG32_SOC15_IP(GC, target, tmp); 6046 } else { 6047 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6048 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6049 GENERIC2_INT_ENABLE, 1); 6050 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6051 6052 tmp = RREG32_SOC15_IP(GC, target); 6053 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6054 GENERIC2_INT_ENABLE, 1); 6055 WREG32_SOC15_IP(GC, target, tmp); 6056 } 6057 break; 6058 default: 6059 BUG(); /* kiq only support GENERIC2_INT now */ 6060 break; 6061 } 6062 return 0; 6063 } 6064 #endif 6065 6066 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6067 { 6068 const unsigned int gcr_cntl = 6069 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6070 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6071 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6072 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6073 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6074 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6075 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6076 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6077 6078 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6079 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6080 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6081 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6082 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6083 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6084 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6085 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6086 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6087 } 6088 6089 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6090 .name = "gfx_v11_0", 6091 .early_init = gfx_v11_0_early_init, 6092 .late_init = gfx_v11_0_late_init, 6093 .sw_init = gfx_v11_0_sw_init, 6094 .sw_fini = gfx_v11_0_sw_fini, 6095 .hw_init = gfx_v11_0_hw_init, 6096 .hw_fini = gfx_v11_0_hw_fini, 6097 .suspend = gfx_v11_0_suspend, 6098 .resume = gfx_v11_0_resume, 6099 .is_idle = gfx_v11_0_is_idle, 6100 .wait_for_idle = gfx_v11_0_wait_for_idle, 6101 .soft_reset = gfx_v11_0_soft_reset, 6102 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6103 .set_powergating_state = gfx_v11_0_set_powergating_state, 6104 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6105 }; 6106 6107 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6108 .type = AMDGPU_RING_TYPE_GFX, 6109 .align_mask = 0xff, 6110 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6111 .support_64bit_ptrs = true, 6112 .vmhub = AMDGPU_GFXHUB_0, 6113 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6114 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6115 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6116 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6117 5 + /* COND_EXEC */ 6118 7 + /* PIPELINE_SYNC */ 6119 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6120 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6121 2 + /* VM_FLUSH */ 6122 8 + /* FENCE for VM_FLUSH */ 6123 20 + /* GDS switch */ 6124 5 + /* COND_EXEC */ 6125 7 + /* HDP_flush */ 6126 4 + /* VGT_flush */ 6127 31 + /* DE_META */ 6128 3 + /* CNTX_CTRL */ 6129 5 + /* HDP_INVL */ 6130 8 + 8 + /* FENCE x2 */ 6131 8, /* gfx_v11_0_emit_mem_sync */ 6132 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6133 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6134 .emit_fence = gfx_v11_0_ring_emit_fence, 6135 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6136 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6137 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6138 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6139 .test_ring = gfx_v11_0_ring_test_ring, 6140 .test_ib = gfx_v11_0_ring_test_ib, 6141 .insert_nop = amdgpu_ring_insert_nop, 6142 .pad_ib = amdgpu_ring_generic_pad_ib, 6143 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6144 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6145 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6146 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6147 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6148 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6149 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6150 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6151 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6152 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6153 }; 6154 6155 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6156 .type = AMDGPU_RING_TYPE_COMPUTE, 6157 .align_mask = 0xff, 6158 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6159 .support_64bit_ptrs = true, 6160 .vmhub = AMDGPU_GFXHUB_0, 6161 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6162 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6163 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6164 .emit_frame_size = 6165 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6166 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6167 5 + /* hdp invalidate */ 6168 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6169 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6170 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6171 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6172 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6173 8, /* gfx_v11_0_emit_mem_sync */ 6174 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6175 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6176 .emit_fence = gfx_v11_0_ring_emit_fence, 6177 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6178 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6179 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6180 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6181 .test_ring = gfx_v11_0_ring_test_ring, 6182 .test_ib = gfx_v11_0_ring_test_ib, 6183 .insert_nop = amdgpu_ring_insert_nop, 6184 .pad_ib = amdgpu_ring_generic_pad_ib, 6185 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6186 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6187 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6188 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6189 }; 6190 6191 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6192 .type = AMDGPU_RING_TYPE_KIQ, 6193 .align_mask = 0xff, 6194 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6195 .support_64bit_ptrs = true, 6196 .vmhub = AMDGPU_GFXHUB_0, 6197 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6198 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6199 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6200 .emit_frame_size = 6201 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6202 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6203 5 + /*hdp invalidate */ 6204 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6205 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6206 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6207 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6208 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6209 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6210 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6211 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6212 .test_ring = gfx_v11_0_ring_test_ring, 6213 .test_ib = gfx_v11_0_ring_test_ib, 6214 .insert_nop = amdgpu_ring_insert_nop, 6215 .pad_ib = amdgpu_ring_generic_pad_ib, 6216 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6217 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6218 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6219 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6220 }; 6221 6222 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6223 { 6224 int i; 6225 6226 adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6227 6228 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6229 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6230 6231 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6232 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6233 } 6234 6235 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6236 .set = gfx_v11_0_set_eop_interrupt_state, 6237 .process = gfx_v11_0_eop_irq, 6238 }; 6239 6240 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6241 .set = gfx_v11_0_set_priv_reg_fault_state, 6242 .process = gfx_v11_0_priv_reg_irq, 6243 }; 6244 6245 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6246 .set = gfx_v11_0_set_priv_inst_fault_state, 6247 .process = gfx_v11_0_priv_inst_irq, 6248 }; 6249 6250 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6251 { 6252 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6253 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6254 6255 adev->gfx.priv_reg_irq.num_types = 1; 6256 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6257 6258 adev->gfx.priv_inst_irq.num_types = 1; 6259 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6260 } 6261 6262 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6263 { 6264 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6265 } 6266 6267 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6268 { 6269 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6270 } 6271 6272 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6273 { 6274 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6275 adev->gfx.config.max_sh_per_se * 6276 adev->gfx.config.max_shader_engines; 6277 6278 adev->gds.gds_size = 0x1000; 6279 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6280 adev->gds.gws_size = 64; 6281 adev->gds.oa_size = 16; 6282 } 6283 6284 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6285 { 6286 /* set gfx eng mqd */ 6287 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6288 sizeof(struct v11_gfx_mqd); 6289 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6290 gfx_v11_0_gfx_mqd_init; 6291 /* set compute eng mqd */ 6292 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6293 sizeof(struct v11_compute_mqd); 6294 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6295 gfx_v11_0_compute_mqd_init; 6296 } 6297 6298 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6299 u32 bitmap) 6300 { 6301 u32 data; 6302 6303 if (!bitmap) 6304 return; 6305 6306 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6307 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6308 6309 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6310 } 6311 6312 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6313 { 6314 u32 data, wgp_bitmask; 6315 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6316 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6317 6318 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6319 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6320 6321 wgp_bitmask = 6322 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6323 6324 return (~data) & wgp_bitmask; 6325 } 6326 6327 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6328 { 6329 u32 wgp_idx, wgp_active_bitmap; 6330 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6331 6332 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6333 cu_active_bitmap = 0; 6334 6335 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6336 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6337 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6338 if (wgp_active_bitmap & (1 << wgp_idx)) 6339 cu_active_bitmap |= cu_bitmap_per_wgp; 6340 } 6341 6342 return cu_active_bitmap; 6343 } 6344 6345 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6346 struct amdgpu_cu_info *cu_info) 6347 { 6348 int i, j, k, counter, active_cu_number = 0; 6349 u32 mask, bitmap; 6350 unsigned disable_masks[8 * 2]; 6351 6352 if (!adev || !cu_info) 6353 return -EINVAL; 6354 6355 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6356 6357 mutex_lock(&adev->grbm_idx_mutex); 6358 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6359 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6360 mask = 1; 6361 counter = 0; 6362 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 6363 if (i < 8 && j < 2) 6364 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6365 adev, disable_masks[i * 2 + j]); 6366 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6367 6368 /** 6369 * GFX11 could support more than 4 SEs, while the bitmap 6370 * in cu_info struct is 4x4 and ioctl interface struct 6371 * drm_amdgpu_info_device should keep stable. 6372 * So we use last two columns of bitmap to store cu mask for 6373 * SEs 4 to 7, the layout of the bitmap is as below: 6374 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6375 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6376 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6377 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6378 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6379 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6380 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6381 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6382 */ 6383 cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; 6384 6385 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6386 if (bitmap & mask) 6387 counter++; 6388 6389 mask <<= 1; 6390 } 6391 active_cu_number += counter; 6392 } 6393 } 6394 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6395 mutex_unlock(&adev->grbm_idx_mutex); 6396 6397 cu_info->number = active_cu_number; 6398 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6399 6400 return 0; 6401 } 6402 6403 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6404 { 6405 .type = AMD_IP_BLOCK_TYPE_GFX, 6406 .major = 11, 6407 .minor = 0, 6408 .rev = 0, 6409 .funcs = &gfx_v11_0_ip_funcs, 6410 }; 6411