1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "gfx_v11_0_3.h" 50 #include "nbio_v4_3.h" 51 #include "mes_v11_0.h" 52 53 #define GFX11_NUM_GFX_RINGS 1 54 #define GFX11_MEC_HPD_SIZE 2048 55 56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 58 59 #define regCGTT_WD_CLK_CTRL 0x5086 60 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 63 64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 85 86 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 87 { 88 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 89 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 90 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 91 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 97 }; 98 99 #define DEFAULT_SH_MEM_CONFIG \ 100 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 101 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 102 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 103 104 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 105 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 106 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 107 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 108 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 109 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 110 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 111 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 112 struct amdgpu_cu_info *cu_info); 113 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 114 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 115 u32 sh_num, u32 instance, int xcc_id); 116 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 117 118 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 119 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 120 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 121 uint32_t val); 122 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 123 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 124 uint16_t pasid, uint32_t flush_type, 125 bool all_hub, uint8_t dst_sel); 126 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 127 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 128 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 129 bool enable); 130 131 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 132 { 133 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 134 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 135 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 136 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 137 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 138 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 139 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 140 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 141 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 142 } 143 144 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 145 struct amdgpu_ring *ring) 146 { 147 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 148 uint64_t wptr_addr = ring->wptr_gpu_addr; 149 uint32_t me = 0, eng_sel = 0; 150 151 switch (ring->funcs->type) { 152 case AMDGPU_RING_TYPE_COMPUTE: 153 me = 1; 154 eng_sel = 0; 155 break; 156 case AMDGPU_RING_TYPE_GFX: 157 me = 0; 158 eng_sel = 4; 159 break; 160 case AMDGPU_RING_TYPE_MES: 161 me = 2; 162 eng_sel = 5; 163 break; 164 default: 165 WARN_ON(1); 166 } 167 168 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 169 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 170 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 171 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 172 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 173 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 174 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 175 PACKET3_MAP_QUEUES_ME((me)) | 176 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 177 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 178 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 179 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 180 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 181 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 182 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 183 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 184 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 185 } 186 187 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 188 struct amdgpu_ring *ring, 189 enum amdgpu_unmap_queues_action action, 190 u64 gpu_addr, u64 seq) 191 { 192 struct amdgpu_device *adev = kiq_ring->adev; 193 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 194 195 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 196 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 197 return; 198 } 199 200 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 201 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 202 PACKET3_UNMAP_QUEUES_ACTION(action) | 203 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 204 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 205 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 206 amdgpu_ring_write(kiq_ring, 207 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 208 209 if (action == PREEMPT_QUEUES_NO_UNMAP) { 210 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 211 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 212 amdgpu_ring_write(kiq_ring, seq); 213 } else { 214 amdgpu_ring_write(kiq_ring, 0); 215 amdgpu_ring_write(kiq_ring, 0); 216 amdgpu_ring_write(kiq_ring, 0); 217 } 218 } 219 220 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 221 struct amdgpu_ring *ring, 222 u64 addr, 223 u64 seq) 224 { 225 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 226 227 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 228 amdgpu_ring_write(kiq_ring, 229 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 230 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 231 PACKET3_QUERY_STATUS_COMMAND(2)); 232 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 233 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 234 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 235 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 236 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 237 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 238 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 239 } 240 241 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 242 uint16_t pasid, uint32_t flush_type, 243 bool all_hub) 244 { 245 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 246 } 247 248 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 249 .kiq_set_resources = gfx11_kiq_set_resources, 250 .kiq_map_queues = gfx11_kiq_map_queues, 251 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 252 .kiq_query_status = gfx11_kiq_query_status, 253 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 254 .set_resources_size = 8, 255 .map_queues_size = 7, 256 .unmap_queues_size = 6, 257 .query_status_size = 7, 258 .invalidate_tlbs_size = 2, 259 }; 260 261 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 262 { 263 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 264 } 265 266 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 267 { 268 switch (adev->ip_versions[GC_HWIP][0]) { 269 case IP_VERSION(11, 0, 1): 270 case IP_VERSION(11, 0, 4): 271 soc15_program_register_sequence(adev, 272 golden_settings_gc_11_0_1, 273 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 274 break; 275 default: 276 break; 277 } 278 } 279 280 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 281 bool wc, uint32_t reg, uint32_t val) 282 { 283 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 284 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 285 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 286 amdgpu_ring_write(ring, reg); 287 amdgpu_ring_write(ring, 0); 288 amdgpu_ring_write(ring, val); 289 } 290 291 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 292 int mem_space, int opt, uint32_t addr0, 293 uint32_t addr1, uint32_t ref, uint32_t mask, 294 uint32_t inv) 295 { 296 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 297 amdgpu_ring_write(ring, 298 /* memory (1) or register (0) */ 299 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 300 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 301 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 302 WAIT_REG_MEM_ENGINE(eng_sel))); 303 304 if (mem_space) 305 BUG_ON(addr0 & 0x3); /* Dword align */ 306 amdgpu_ring_write(ring, addr0); 307 amdgpu_ring_write(ring, addr1); 308 amdgpu_ring_write(ring, ref); 309 amdgpu_ring_write(ring, mask); 310 amdgpu_ring_write(ring, inv); /* poll interval */ 311 } 312 313 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 314 { 315 struct amdgpu_device *adev = ring->adev; 316 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 317 uint32_t tmp = 0; 318 unsigned i; 319 int r; 320 321 WREG32(scratch, 0xCAFEDEAD); 322 r = amdgpu_ring_alloc(ring, 5); 323 if (r) { 324 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 325 ring->idx, r); 326 return r; 327 } 328 329 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 330 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 331 } else { 332 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 333 amdgpu_ring_write(ring, scratch - 334 PACKET3_SET_UCONFIG_REG_START); 335 amdgpu_ring_write(ring, 0xDEADBEEF); 336 } 337 amdgpu_ring_commit(ring); 338 339 for (i = 0; i < adev->usec_timeout; i++) { 340 tmp = RREG32(scratch); 341 if (tmp == 0xDEADBEEF) 342 break; 343 if (amdgpu_emu_mode == 1) 344 msleep(1); 345 else 346 udelay(1); 347 } 348 349 if (i >= adev->usec_timeout) 350 r = -ETIMEDOUT; 351 return r; 352 } 353 354 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 355 { 356 struct amdgpu_device *adev = ring->adev; 357 struct amdgpu_ib ib; 358 struct dma_fence *f = NULL; 359 unsigned index; 360 uint64_t gpu_addr; 361 volatile uint32_t *cpu_ptr; 362 long r; 363 364 /* MES KIQ fw hasn't indirect buffer support for now */ 365 if (adev->enable_mes_kiq && 366 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 367 return 0; 368 369 memset(&ib, 0, sizeof(ib)); 370 371 if (ring->is_mes_queue) { 372 uint32_t padding, offset; 373 374 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 375 padding = amdgpu_mes_ctx_get_offs(ring, 376 AMDGPU_MES_CTX_PADDING_OFFS); 377 378 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 379 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 380 381 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 382 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 383 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 384 } else { 385 r = amdgpu_device_wb_get(adev, &index); 386 if (r) 387 return r; 388 389 gpu_addr = adev->wb.gpu_addr + (index * 4); 390 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 391 cpu_ptr = &adev->wb.wb[index]; 392 393 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 394 if (r) { 395 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 396 goto err1; 397 } 398 } 399 400 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 401 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 402 ib.ptr[2] = lower_32_bits(gpu_addr); 403 ib.ptr[3] = upper_32_bits(gpu_addr); 404 ib.ptr[4] = 0xDEADBEEF; 405 ib.length_dw = 5; 406 407 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 408 if (r) 409 goto err2; 410 411 r = dma_fence_wait_timeout(f, false, timeout); 412 if (r == 0) { 413 r = -ETIMEDOUT; 414 goto err2; 415 } else if (r < 0) { 416 goto err2; 417 } 418 419 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 420 r = 0; 421 else 422 r = -EINVAL; 423 err2: 424 if (!ring->is_mes_queue) 425 amdgpu_ib_free(adev, &ib, NULL); 426 dma_fence_put(f); 427 err1: 428 if (!ring->is_mes_queue) 429 amdgpu_device_wb_free(adev, index); 430 return r; 431 } 432 433 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 434 { 435 amdgpu_ucode_release(&adev->gfx.pfp_fw); 436 amdgpu_ucode_release(&adev->gfx.me_fw); 437 amdgpu_ucode_release(&adev->gfx.rlc_fw); 438 amdgpu_ucode_release(&adev->gfx.mec_fw); 439 440 kfree(adev->gfx.rlc.register_list_format); 441 } 442 443 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 444 { 445 const struct psp_firmware_header_v1_0 *toc_hdr; 446 int err = 0; 447 char fw_name[40]; 448 449 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 450 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 451 if (err) 452 goto out; 453 454 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 455 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 456 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 457 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 458 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 459 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 460 return 0; 461 out: 462 amdgpu_ucode_release(&adev->psp.toc_fw); 463 return err; 464 } 465 466 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 467 { 468 switch (adev->ip_versions[GC_HWIP][0]) { 469 case IP_VERSION(11, 0, 0): 470 case IP_VERSION(11, 0, 2): 471 case IP_VERSION(11, 0, 3): 472 if ((adev->gfx.me_fw_version >= 1505) && 473 (adev->gfx.pfp_fw_version >= 1600) && 474 (adev->gfx.mec_fw_version >= 512)) 475 adev->gfx.cp_gfx_shadow = true; 476 break; 477 default: 478 adev->gfx.cp_gfx_shadow = false; 479 break; 480 } 481 } 482 483 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 484 { 485 char fw_name[40]; 486 char ucode_prefix[30]; 487 int err; 488 const struct rlc_firmware_header_v2_0 *rlc_hdr; 489 uint16_t version_major; 490 uint16_t version_minor; 491 492 DRM_DEBUG("\n"); 493 494 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 495 496 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 497 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 498 if (err) 499 goto out; 500 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 501 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 502 (union amdgpu_firmware_header *) 503 adev->gfx.pfp_fw->data, 2, 0); 504 if (adev->gfx.rs64_enable) { 505 dev_info(adev->dev, "CP RS64 enable\n"); 506 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 507 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 508 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 509 } else { 510 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 511 } 512 513 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 514 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 515 if (err) 516 goto out; 517 if (adev->gfx.rs64_enable) { 518 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 519 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 520 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 521 } else { 522 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 523 } 524 525 if (!amdgpu_sriov_vf(adev)) { 526 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 527 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 528 if (err) 529 goto out; 530 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 531 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 532 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 533 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 534 if (err) 535 goto out; 536 } 537 538 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 539 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 540 if (err) 541 goto out; 542 if (adev->gfx.rs64_enable) { 543 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 544 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 545 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 546 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 547 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 548 } else { 549 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 550 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 551 } 552 553 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 554 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 555 556 /* only one MEC for gfx 11.0.0. */ 557 adev->gfx.mec2_fw = NULL; 558 559 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 560 out: 561 if (err) { 562 amdgpu_ucode_release(&adev->gfx.pfp_fw); 563 amdgpu_ucode_release(&adev->gfx.me_fw); 564 amdgpu_ucode_release(&adev->gfx.rlc_fw); 565 amdgpu_ucode_release(&adev->gfx.mec_fw); 566 } 567 568 return err; 569 } 570 571 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 572 { 573 u32 count = 0; 574 const struct cs_section_def *sect = NULL; 575 const struct cs_extent_def *ext = NULL; 576 577 /* begin clear state */ 578 count += 2; 579 /* context control state */ 580 count += 3; 581 582 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 583 for (ext = sect->section; ext->extent != NULL; ++ext) { 584 if (sect->id == SECT_CONTEXT) 585 count += 2 + ext->reg_count; 586 else 587 return 0; 588 } 589 } 590 591 /* set PA_SC_TILE_STEERING_OVERRIDE */ 592 count += 3; 593 /* end clear state */ 594 count += 2; 595 /* clear state */ 596 count += 2; 597 598 return count; 599 } 600 601 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 602 volatile u32 *buffer) 603 { 604 u32 count = 0, i; 605 const struct cs_section_def *sect = NULL; 606 const struct cs_extent_def *ext = NULL; 607 int ctx_reg_offset; 608 609 if (adev->gfx.rlc.cs_data == NULL) 610 return; 611 if (buffer == NULL) 612 return; 613 614 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 615 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 616 617 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 618 buffer[count++] = cpu_to_le32(0x80000000); 619 buffer[count++] = cpu_to_le32(0x80000000); 620 621 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 622 for (ext = sect->section; ext->extent != NULL; ++ext) { 623 if (sect->id == SECT_CONTEXT) { 624 buffer[count++] = 625 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 626 buffer[count++] = cpu_to_le32(ext->reg_index - 627 PACKET3_SET_CONTEXT_REG_START); 628 for (i = 0; i < ext->reg_count; i++) 629 buffer[count++] = cpu_to_le32(ext->extent[i]); 630 } else { 631 return; 632 } 633 } 634 } 635 636 ctx_reg_offset = 637 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 638 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 639 buffer[count++] = cpu_to_le32(ctx_reg_offset); 640 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 641 642 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 643 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 644 645 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 646 buffer[count++] = cpu_to_le32(0); 647 } 648 649 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 650 { 651 /* clear state block */ 652 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 653 &adev->gfx.rlc.clear_state_gpu_addr, 654 (void **)&adev->gfx.rlc.cs_ptr); 655 656 /* jump table block */ 657 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 658 &adev->gfx.rlc.cp_table_gpu_addr, 659 (void **)&adev->gfx.rlc.cp_table_ptr); 660 } 661 662 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 663 { 664 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 665 666 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 667 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 668 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 669 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 670 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 671 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 672 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 673 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 674 adev->gfx.rlc.rlcg_reg_access_supported = true; 675 } 676 677 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 678 { 679 const struct cs_section_def *cs_data; 680 int r; 681 682 adev->gfx.rlc.cs_data = gfx11_cs_data; 683 684 cs_data = adev->gfx.rlc.cs_data; 685 686 if (cs_data) { 687 /* init clear state block */ 688 r = amdgpu_gfx_rlc_init_csb(adev); 689 if (r) 690 return r; 691 } 692 693 /* init spm vmid with 0xf */ 694 if (adev->gfx.rlc.funcs->update_spm_vmid) 695 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 696 697 return 0; 698 } 699 700 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 701 { 702 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 703 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 704 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 705 } 706 707 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 708 { 709 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 710 711 amdgpu_gfx_graphics_queue_acquire(adev); 712 } 713 714 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 715 { 716 int r; 717 u32 *hpd; 718 size_t mec_hpd_size; 719 720 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 721 722 /* take ownership of the relevant compute queues */ 723 amdgpu_gfx_compute_queue_acquire(adev); 724 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 725 726 if (mec_hpd_size) { 727 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 728 AMDGPU_GEM_DOMAIN_GTT, 729 &adev->gfx.mec.hpd_eop_obj, 730 &adev->gfx.mec.hpd_eop_gpu_addr, 731 (void **)&hpd); 732 if (r) { 733 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 734 gfx_v11_0_mec_fini(adev); 735 return r; 736 } 737 738 memset(hpd, 0, mec_hpd_size); 739 740 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 741 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 742 } 743 744 return 0; 745 } 746 747 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 748 { 749 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 750 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 751 (address << SQ_IND_INDEX__INDEX__SHIFT)); 752 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 753 } 754 755 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 756 uint32_t thread, uint32_t regno, 757 uint32_t num, uint32_t *out) 758 { 759 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 760 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 761 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 762 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 763 (SQ_IND_INDEX__AUTO_INCR_MASK)); 764 while (num--) 765 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 766 } 767 768 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 769 { 770 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 771 * field when performing a select_se_sh so it should be 772 * zero here */ 773 WARN_ON(simd != 0); 774 775 /* type 3 wave data */ 776 dst[(*no_fields)++] = 3; 777 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 778 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 779 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 780 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 781 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 782 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 783 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 784 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 785 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 786 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 787 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 788 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 789 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 790 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 791 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 792 } 793 794 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 795 uint32_t wave, uint32_t start, 796 uint32_t size, uint32_t *dst) 797 { 798 WARN_ON(simd != 0); 799 800 wave_read_regs( 801 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 802 dst); 803 } 804 805 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 806 uint32_t wave, uint32_t thread, 807 uint32_t start, uint32_t size, 808 uint32_t *dst) 809 { 810 wave_read_regs( 811 adev, wave, thread, 812 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 813 } 814 815 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 816 u32 me, u32 pipe, u32 q, u32 vm) 817 { 818 soc21_grbm_select(adev, me, pipe, q, vm); 819 } 820 821 /* all sizes are in bytes */ 822 #define MQD_SHADOW_BASE_SIZE 73728 823 #define MQD_SHADOW_BASE_ALIGNMENT 256 824 #define MQD_FWWORKAREA_SIZE 484 825 #define MQD_FWWORKAREA_ALIGNMENT 256 826 827 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 828 struct amdgpu_gfx_shadow_info *shadow_info) 829 { 830 if (adev->gfx.cp_gfx_shadow) { 831 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 832 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 833 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 834 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 835 return 0; 836 } else { 837 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 838 return -ENOTSUPP; 839 } 840 } 841 842 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 843 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 844 .select_se_sh = &gfx_v11_0_select_se_sh, 845 .read_wave_data = &gfx_v11_0_read_wave_data, 846 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 847 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 848 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 849 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 850 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 851 }; 852 853 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 854 { 855 856 switch (adev->ip_versions[GC_HWIP][0]) { 857 case IP_VERSION(11, 0, 0): 858 case IP_VERSION(11, 0, 2): 859 adev->gfx.config.max_hw_contexts = 8; 860 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 861 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 862 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 863 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 864 break; 865 case IP_VERSION(11, 0, 3): 866 adev->gfx.ras = &gfx_v11_0_3_ras; 867 adev->gfx.config.max_hw_contexts = 8; 868 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 869 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 870 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 871 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 872 break; 873 case IP_VERSION(11, 0, 1): 874 case IP_VERSION(11, 0, 4): 875 adev->gfx.config.max_hw_contexts = 8; 876 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 877 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 878 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 879 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 880 break; 881 default: 882 BUG(); 883 break; 884 } 885 886 return 0; 887 } 888 889 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 890 int me, int pipe, int queue) 891 { 892 int r; 893 struct amdgpu_ring *ring; 894 unsigned int irq_type; 895 896 ring = &adev->gfx.gfx_ring[ring_id]; 897 898 ring->me = me; 899 ring->pipe = pipe; 900 ring->queue = queue; 901 902 ring->ring_obj = NULL; 903 ring->use_doorbell = true; 904 905 if (!ring_id) 906 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 907 else 908 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 909 ring->vm_hub = AMDGPU_GFXHUB_0; 910 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 911 912 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 913 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 914 AMDGPU_RING_PRIO_DEFAULT, NULL); 915 if (r) 916 return r; 917 return 0; 918 } 919 920 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 921 int mec, int pipe, int queue) 922 { 923 int r; 924 unsigned irq_type; 925 struct amdgpu_ring *ring; 926 unsigned int hw_prio; 927 928 ring = &adev->gfx.compute_ring[ring_id]; 929 930 /* mec0 is me1 */ 931 ring->me = mec + 1; 932 ring->pipe = pipe; 933 ring->queue = queue; 934 935 ring->ring_obj = NULL; 936 ring->use_doorbell = true; 937 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 938 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 939 + (ring_id * GFX11_MEC_HPD_SIZE); 940 ring->vm_hub = AMDGPU_GFXHUB_0; 941 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 942 943 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 944 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 945 + ring->pipe; 946 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 947 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 948 /* type-2 packets are deprecated on MEC, use type-3 instead */ 949 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 950 hw_prio, NULL); 951 if (r) 952 return r; 953 954 return 0; 955 } 956 957 static struct { 958 SOC21_FIRMWARE_ID id; 959 unsigned int offset; 960 unsigned int size; 961 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 962 963 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 964 { 965 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 966 967 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 968 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 969 rlc_autoload_info[ucode->id].id = ucode->id; 970 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 971 rlc_autoload_info[ucode->id].size = ucode->size * 4; 972 973 ucode++; 974 } 975 } 976 977 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 978 { 979 uint32_t total_size = 0; 980 SOC21_FIRMWARE_ID id; 981 982 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 983 984 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 985 total_size += rlc_autoload_info[id].size; 986 987 /* In case the offset in rlc toc ucode is aligned */ 988 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 989 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 990 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 991 992 return total_size; 993 } 994 995 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 996 { 997 int r; 998 uint32_t total_size; 999 1000 total_size = gfx_v11_0_calc_toc_total_size(adev); 1001 1002 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1003 AMDGPU_GEM_DOMAIN_VRAM | 1004 AMDGPU_GEM_DOMAIN_GTT, 1005 &adev->gfx.rlc.rlc_autoload_bo, 1006 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1007 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1008 1009 if (r) { 1010 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1011 return r; 1012 } 1013 1014 return 0; 1015 } 1016 1017 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1018 SOC21_FIRMWARE_ID id, 1019 const void *fw_data, 1020 uint32_t fw_size, 1021 uint32_t *fw_autoload_mask) 1022 { 1023 uint32_t toc_offset; 1024 uint32_t toc_fw_size; 1025 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1026 1027 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1028 return; 1029 1030 toc_offset = rlc_autoload_info[id].offset; 1031 toc_fw_size = rlc_autoload_info[id].size; 1032 1033 if (fw_size == 0) 1034 fw_size = toc_fw_size; 1035 1036 if (fw_size > toc_fw_size) 1037 fw_size = toc_fw_size; 1038 1039 memcpy(ptr + toc_offset, fw_data, fw_size); 1040 1041 if (fw_size < toc_fw_size) 1042 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1043 1044 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1045 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1046 } 1047 1048 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1049 uint32_t *fw_autoload_mask) 1050 { 1051 void *data; 1052 uint32_t size; 1053 uint64_t *toc_ptr; 1054 1055 *(uint64_t *)fw_autoload_mask |= 0x1; 1056 1057 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1058 1059 data = adev->psp.toc.start_addr; 1060 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1061 1062 toc_ptr = (uint64_t *)data + size / 8 - 1; 1063 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1064 1065 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1066 data, size, fw_autoload_mask); 1067 } 1068 1069 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1070 uint32_t *fw_autoload_mask) 1071 { 1072 const __le32 *fw_data; 1073 uint32_t fw_size; 1074 const struct gfx_firmware_header_v1_0 *cp_hdr; 1075 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1076 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1077 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1078 uint16_t version_major, version_minor; 1079 1080 if (adev->gfx.rs64_enable) { 1081 /* pfp ucode */ 1082 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1083 adev->gfx.pfp_fw->data; 1084 /* instruction */ 1085 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1086 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1087 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1088 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1089 fw_data, fw_size, fw_autoload_mask); 1090 /* data */ 1091 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1092 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1093 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1094 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1095 fw_data, fw_size, fw_autoload_mask); 1096 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1097 fw_data, fw_size, fw_autoload_mask); 1098 /* me ucode */ 1099 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1100 adev->gfx.me_fw->data; 1101 /* instruction */ 1102 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1103 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1104 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1105 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1106 fw_data, fw_size, fw_autoload_mask); 1107 /* data */ 1108 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1109 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1110 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1111 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1112 fw_data, fw_size, fw_autoload_mask); 1113 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1114 fw_data, fw_size, fw_autoload_mask); 1115 /* mec ucode */ 1116 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1117 adev->gfx.mec_fw->data; 1118 /* instruction */ 1119 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1120 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1121 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1122 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1123 fw_data, fw_size, fw_autoload_mask); 1124 /* data */ 1125 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1126 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1127 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1128 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1129 fw_data, fw_size, fw_autoload_mask); 1130 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1131 fw_data, fw_size, fw_autoload_mask); 1132 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1133 fw_data, fw_size, fw_autoload_mask); 1134 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1135 fw_data, fw_size, fw_autoload_mask); 1136 } else { 1137 /* pfp ucode */ 1138 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1139 adev->gfx.pfp_fw->data; 1140 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1141 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1142 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1143 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1144 fw_data, fw_size, fw_autoload_mask); 1145 1146 /* me ucode */ 1147 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1148 adev->gfx.me_fw->data; 1149 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1150 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1151 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1152 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1153 fw_data, fw_size, fw_autoload_mask); 1154 1155 /* mec ucode */ 1156 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1157 adev->gfx.mec_fw->data; 1158 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1159 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1160 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1161 cp_hdr->jt_size * 4; 1162 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1163 fw_data, fw_size, fw_autoload_mask); 1164 } 1165 1166 /* rlc ucode */ 1167 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1168 adev->gfx.rlc_fw->data; 1169 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1170 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1171 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1172 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1173 fw_data, fw_size, fw_autoload_mask); 1174 1175 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1176 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1177 if (version_major == 2) { 1178 if (version_minor >= 2) { 1179 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1180 1181 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1182 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1183 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1184 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1185 fw_data, fw_size, fw_autoload_mask); 1186 1187 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1188 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1189 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1190 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1191 fw_data, fw_size, fw_autoload_mask); 1192 } 1193 } 1194 } 1195 1196 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1197 uint32_t *fw_autoload_mask) 1198 { 1199 const __le32 *fw_data; 1200 uint32_t fw_size; 1201 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1202 1203 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1204 adev->sdma.instance[0].fw->data; 1205 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1206 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1207 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1208 1209 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1210 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1211 1212 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1213 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1214 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1215 1216 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1217 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1218 } 1219 1220 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1221 uint32_t *fw_autoload_mask) 1222 { 1223 const __le32 *fw_data; 1224 unsigned fw_size; 1225 const struct mes_firmware_header_v1_0 *mes_hdr; 1226 int pipe, ucode_id, data_id; 1227 1228 for (pipe = 0; pipe < 2; pipe++) { 1229 if (pipe==0) { 1230 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1231 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1232 } else { 1233 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1234 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1235 } 1236 1237 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1238 adev->mes.fw[pipe]->data; 1239 1240 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1241 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1242 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1243 1244 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1245 ucode_id, fw_data, fw_size, fw_autoload_mask); 1246 1247 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1248 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1249 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1250 1251 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1252 data_id, fw_data, fw_size, fw_autoload_mask); 1253 } 1254 } 1255 1256 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1257 { 1258 uint32_t rlc_g_offset, rlc_g_size; 1259 uint64_t gpu_addr; 1260 uint32_t autoload_fw_id[2]; 1261 1262 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1263 1264 /* RLC autoload sequence 2: copy ucode */ 1265 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1266 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1267 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1268 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1269 1270 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1271 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1272 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1273 1274 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1275 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1276 1277 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1278 1279 /* RLC autoload sequence 3: load IMU fw */ 1280 if (adev->gfx.imu.funcs->load_microcode) 1281 adev->gfx.imu.funcs->load_microcode(adev); 1282 /* RLC autoload sequence 4 init IMU fw */ 1283 if (adev->gfx.imu.funcs->setup_imu) 1284 adev->gfx.imu.funcs->setup_imu(adev); 1285 if (adev->gfx.imu.funcs->start_imu) 1286 adev->gfx.imu.funcs->start_imu(adev); 1287 1288 /* RLC autoload sequence 5 disable gpa mode */ 1289 gfx_v11_0_disable_gpa_mode(adev); 1290 1291 return 0; 1292 } 1293 1294 static int gfx_v11_0_sw_init(void *handle) 1295 { 1296 int i, j, k, r, ring_id = 0; 1297 struct amdgpu_kiq *kiq; 1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1299 1300 adev->gfxhub.funcs->init(adev); 1301 1302 switch (adev->ip_versions[GC_HWIP][0]) { 1303 case IP_VERSION(11, 0, 0): 1304 case IP_VERSION(11, 0, 2): 1305 case IP_VERSION(11, 0, 3): 1306 adev->gfx.me.num_me = 1; 1307 adev->gfx.me.num_pipe_per_me = 1; 1308 adev->gfx.me.num_queue_per_pipe = 1; 1309 adev->gfx.mec.num_mec = 2; 1310 adev->gfx.mec.num_pipe_per_mec = 4; 1311 adev->gfx.mec.num_queue_per_pipe = 4; 1312 break; 1313 case IP_VERSION(11, 0, 1): 1314 case IP_VERSION(11, 0, 4): 1315 adev->gfx.me.num_me = 1; 1316 adev->gfx.me.num_pipe_per_me = 1; 1317 adev->gfx.me.num_queue_per_pipe = 1; 1318 adev->gfx.mec.num_mec = 1; 1319 adev->gfx.mec.num_pipe_per_mec = 4; 1320 adev->gfx.mec.num_queue_per_pipe = 4; 1321 break; 1322 default: 1323 adev->gfx.me.num_me = 1; 1324 adev->gfx.me.num_pipe_per_me = 1; 1325 adev->gfx.me.num_queue_per_pipe = 1; 1326 adev->gfx.mec.num_mec = 1; 1327 adev->gfx.mec.num_pipe_per_mec = 4; 1328 adev->gfx.mec.num_queue_per_pipe = 8; 1329 break; 1330 } 1331 1332 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1333 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3) && 1334 amdgpu_sriov_is_pp_one_vf(adev)) 1335 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1336 1337 /* EOP Event */ 1338 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1339 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1340 &adev->gfx.eop_irq); 1341 if (r) 1342 return r; 1343 1344 /* Privileged reg */ 1345 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1346 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1347 &adev->gfx.priv_reg_irq); 1348 if (r) 1349 return r; 1350 1351 /* Privileged inst */ 1352 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1353 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1354 &adev->gfx.priv_inst_irq); 1355 if (r) 1356 return r; 1357 1358 /* ECC error */ 1359 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1360 GFX_11_0_0__SRCID__CP_ECC_ERROR, 1361 &adev->gfx.cp_ecc_error_irq); 1362 if (r) 1363 return r; 1364 1365 /* FED error */ 1366 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1367 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1368 &adev->gfx.rlc_gc_fed_irq); 1369 if (r) 1370 return r; 1371 1372 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1373 1374 if (adev->gfx.imu.funcs) { 1375 if (adev->gfx.imu.funcs->init_microcode) { 1376 r = adev->gfx.imu.funcs->init_microcode(adev); 1377 if (r) 1378 DRM_ERROR("Failed to load imu firmware!\n"); 1379 } 1380 } 1381 1382 gfx_v11_0_me_init(adev); 1383 1384 r = gfx_v11_0_rlc_init(adev); 1385 if (r) { 1386 DRM_ERROR("Failed to init rlc BOs!\n"); 1387 return r; 1388 } 1389 1390 r = gfx_v11_0_mec_init(adev); 1391 if (r) { 1392 DRM_ERROR("Failed to init MEC BOs!\n"); 1393 return r; 1394 } 1395 1396 /* set up the gfx ring */ 1397 for (i = 0; i < adev->gfx.me.num_me; i++) { 1398 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1399 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1400 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1401 continue; 1402 1403 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1404 i, k, j); 1405 if (r) 1406 return r; 1407 ring_id++; 1408 } 1409 } 1410 } 1411 1412 ring_id = 0; 1413 /* set up the compute queues - allocate horizontally across pipes */ 1414 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1415 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1416 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1417 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1418 k, j)) 1419 continue; 1420 1421 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1422 i, k, j); 1423 if (r) 1424 return r; 1425 1426 ring_id++; 1427 } 1428 } 1429 } 1430 1431 if (!adev->enable_mes_kiq) { 1432 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1433 if (r) { 1434 DRM_ERROR("Failed to init KIQ BOs!\n"); 1435 return r; 1436 } 1437 1438 kiq = &adev->gfx.kiq[0]; 1439 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 1440 if (r) 1441 return r; 1442 } 1443 1444 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1445 if (r) 1446 return r; 1447 1448 /* allocate visible FB for rlc auto-loading fw */ 1449 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1450 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1451 if (r) 1452 return r; 1453 } 1454 1455 r = gfx_v11_0_gpu_early_init(adev); 1456 if (r) 1457 return r; 1458 1459 if (amdgpu_gfx_ras_sw_init(adev)) { 1460 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1461 return -EINVAL; 1462 } 1463 1464 return 0; 1465 } 1466 1467 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1468 { 1469 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1470 &adev->gfx.pfp.pfp_fw_gpu_addr, 1471 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1472 1473 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1474 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1475 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1476 } 1477 1478 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1479 { 1480 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1481 &adev->gfx.me.me_fw_gpu_addr, 1482 (void **)&adev->gfx.me.me_fw_ptr); 1483 1484 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1485 &adev->gfx.me.me_fw_data_gpu_addr, 1486 (void **)&adev->gfx.me.me_fw_data_ptr); 1487 } 1488 1489 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1490 { 1491 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1492 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1493 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1494 } 1495 1496 static int gfx_v11_0_sw_fini(void *handle) 1497 { 1498 int i; 1499 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1500 1501 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1502 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1503 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1504 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1505 1506 amdgpu_gfx_mqd_sw_fini(adev, 0); 1507 1508 if (!adev->enable_mes_kiq) { 1509 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1510 amdgpu_gfx_kiq_fini(adev, 0); 1511 } 1512 1513 gfx_v11_0_pfp_fini(adev); 1514 gfx_v11_0_me_fini(adev); 1515 gfx_v11_0_rlc_fini(adev); 1516 gfx_v11_0_mec_fini(adev); 1517 1518 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1519 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1520 1521 gfx_v11_0_free_microcode(adev); 1522 1523 return 0; 1524 } 1525 1526 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1527 u32 sh_num, u32 instance, int xcc_id) 1528 { 1529 u32 data; 1530 1531 if (instance == 0xffffffff) 1532 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1533 INSTANCE_BROADCAST_WRITES, 1); 1534 else 1535 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1536 instance); 1537 1538 if (se_num == 0xffffffff) 1539 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1540 1); 1541 else 1542 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1543 1544 if (sh_num == 0xffffffff) 1545 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1546 1); 1547 else 1548 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1549 1550 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1551 } 1552 1553 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1554 { 1555 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1556 1557 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1558 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1559 CC_GC_SA_UNIT_DISABLE, 1560 SA_DISABLE); 1561 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1562 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1563 GC_USER_SA_UNIT_DISABLE, 1564 SA_DISABLE); 1565 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1566 adev->gfx.config.max_shader_engines); 1567 1568 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1569 } 1570 1571 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1572 { 1573 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1574 u32 rb_mask; 1575 1576 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1577 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1578 CC_RB_BACKEND_DISABLE, 1579 BACKEND_DISABLE); 1580 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1581 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1582 GC_USER_RB_BACKEND_DISABLE, 1583 BACKEND_DISABLE); 1584 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1585 adev->gfx.config.max_shader_engines); 1586 1587 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1588 } 1589 1590 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1591 { 1592 u32 rb_bitmap_width_per_sa; 1593 u32 max_sa; 1594 u32 active_sa_bitmap; 1595 u32 global_active_rb_bitmap; 1596 u32 active_rb_bitmap = 0; 1597 u32 i; 1598 1599 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1600 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 1601 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1602 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 1603 1604 /* generate active rb bitmap according to active sa bitmap */ 1605 max_sa = adev->gfx.config.max_shader_engines * 1606 adev->gfx.config.max_sh_per_se; 1607 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1608 adev->gfx.config.max_sh_per_se; 1609 for (i = 0; i < max_sa; i++) { 1610 if (active_sa_bitmap & (1 << i)) 1611 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1612 } 1613 1614 active_rb_bitmap |= global_active_rb_bitmap; 1615 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1616 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1617 } 1618 1619 #define DEFAULT_SH_MEM_BASES (0x6000) 1620 #define LDS_APP_BASE 0x1 1621 #define SCRATCH_APP_BASE 0x2 1622 1623 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1624 { 1625 int i; 1626 uint32_t sh_mem_bases; 1627 uint32_t data; 1628 1629 /* 1630 * Configure apertures: 1631 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1632 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1633 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1634 */ 1635 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1636 SCRATCH_APP_BASE; 1637 1638 mutex_lock(&adev->srbm_mutex); 1639 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1640 soc21_grbm_select(adev, 0, 0, 0, i); 1641 /* CP and shaders */ 1642 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1643 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1644 1645 /* Enable trap for each kfd vmid. */ 1646 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1647 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1648 } 1649 soc21_grbm_select(adev, 0, 0, 0, 0); 1650 mutex_unlock(&adev->srbm_mutex); 1651 1652 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1653 acccess. These should be enabled by FW for target VMIDs. */ 1654 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1655 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1656 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1657 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1658 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1659 } 1660 } 1661 1662 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1663 { 1664 int vmid; 1665 1666 /* 1667 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1668 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1669 * the driver can enable them for graphics. VMID0 should maintain 1670 * access so that HWS firmware can save/restore entries. 1671 */ 1672 for (vmid = 1; vmid < 16; vmid++) { 1673 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1674 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1675 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1676 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1677 } 1678 } 1679 1680 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1681 { 1682 /* TODO: harvest feature to be added later. */ 1683 } 1684 1685 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1686 { 1687 /* TCCs are global (not instanced). */ 1688 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1689 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1690 1691 adev->gfx.config.tcc_disabled_mask = 1692 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1693 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1694 } 1695 1696 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1697 { 1698 u32 tmp; 1699 int i; 1700 1701 if (!amdgpu_sriov_vf(adev)) 1702 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1703 1704 gfx_v11_0_setup_rb(adev); 1705 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1706 gfx_v11_0_get_tcc_info(adev); 1707 adev->gfx.config.pa_sc_tile_steering_override = 0; 1708 1709 /* Set whether texture coordinate truncation is conformant. */ 1710 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 1711 adev->gfx.config.ta_cntl2_truncate_coord_mode = 1712 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 1713 1714 /* XXX SH_MEM regs */ 1715 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1716 mutex_lock(&adev->srbm_mutex); 1717 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1718 soc21_grbm_select(adev, 0, 0, 0, i); 1719 /* CP and shaders */ 1720 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1721 if (i != 0) { 1722 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1723 (adev->gmc.private_aperture_start >> 48)); 1724 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1725 (adev->gmc.shared_aperture_start >> 48)); 1726 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1727 } 1728 } 1729 soc21_grbm_select(adev, 0, 0, 0, 0); 1730 1731 mutex_unlock(&adev->srbm_mutex); 1732 1733 gfx_v11_0_init_compute_vmid(adev); 1734 gfx_v11_0_init_gds_vmid(adev); 1735 } 1736 1737 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1738 bool enable) 1739 { 1740 u32 tmp; 1741 1742 if (amdgpu_sriov_vf(adev)) 1743 return; 1744 1745 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1746 1747 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1748 enable ? 1 : 0); 1749 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1750 enable ? 1 : 0); 1751 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1752 enable ? 1 : 0); 1753 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1754 enable ? 1 : 0); 1755 1756 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1757 } 1758 1759 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1760 { 1761 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1762 1763 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1764 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1765 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1766 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1767 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1768 1769 return 0; 1770 } 1771 1772 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1773 { 1774 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1775 1776 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1777 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1778 } 1779 1780 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1781 { 1782 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1783 udelay(50); 1784 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1785 udelay(50); 1786 } 1787 1788 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1789 bool enable) 1790 { 1791 uint32_t rlc_pg_cntl; 1792 1793 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1794 1795 if (!enable) { 1796 /* RLC_PG_CNTL[23] = 0 (default) 1797 * RLC will wait for handshake acks with SMU 1798 * GFXOFF will be enabled 1799 * RLC_PG_CNTL[23] = 1 1800 * RLC will not issue any message to SMU 1801 * hence no handshake between SMU & RLC 1802 * GFXOFF will be disabled 1803 */ 1804 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1805 } else 1806 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1807 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1808 } 1809 1810 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 1811 { 1812 /* TODO: enable rlc & smu handshake until smu 1813 * and gfxoff feature works as expected */ 1814 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1815 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 1816 1817 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1818 udelay(50); 1819 } 1820 1821 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 1822 { 1823 uint32_t tmp; 1824 1825 /* enable Save Restore Machine */ 1826 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1827 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1828 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1829 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1830 } 1831 1832 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 1833 { 1834 const struct rlc_firmware_header_v2_0 *hdr; 1835 const __le32 *fw_data; 1836 unsigned i, fw_size; 1837 1838 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1839 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1840 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1841 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1842 1843 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1844 RLCG_UCODE_LOADING_START_ADDRESS); 1845 1846 for (i = 0; i < fw_size; i++) 1847 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1848 le32_to_cpup(fw_data++)); 1849 1850 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1851 } 1852 1853 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1854 { 1855 const struct rlc_firmware_header_v2_2 *hdr; 1856 const __le32 *fw_data; 1857 unsigned i, fw_size; 1858 u32 tmp; 1859 1860 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1861 1862 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1863 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1864 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1865 1866 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1867 1868 for (i = 0; i < fw_size; i++) { 1869 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1870 msleep(1); 1871 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1872 le32_to_cpup(fw_data++)); 1873 } 1874 1875 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1876 1877 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1878 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1879 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1880 1881 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1882 for (i = 0; i < fw_size; i++) { 1883 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1884 msleep(1); 1885 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1886 le32_to_cpup(fw_data++)); 1887 } 1888 1889 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1890 1891 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1892 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1893 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1894 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1895 } 1896 1897 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 1898 { 1899 const struct rlc_firmware_header_v2_3 *hdr; 1900 const __le32 *fw_data; 1901 unsigned i, fw_size; 1902 u32 tmp; 1903 1904 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 1905 1906 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1907 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 1908 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 1909 1910 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 1911 1912 for (i = 0; i < fw_size; i++) { 1913 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1914 msleep(1); 1915 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 1916 le32_to_cpup(fw_data++)); 1917 } 1918 1919 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 1920 1921 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1922 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1923 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 1924 1925 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1926 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 1927 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 1928 1929 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 1930 1931 for (i = 0; i < fw_size; i++) { 1932 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1933 msleep(1); 1934 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 1935 le32_to_cpup(fw_data++)); 1936 } 1937 1938 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 1939 1940 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 1941 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 1942 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 1943 } 1944 1945 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 1946 { 1947 const struct rlc_firmware_header_v2_0 *hdr; 1948 uint16_t version_major; 1949 uint16_t version_minor; 1950 1951 if (!adev->gfx.rlc_fw) 1952 return -EINVAL; 1953 1954 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1955 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1956 1957 version_major = le16_to_cpu(hdr->header.header_version_major); 1958 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1959 1960 if (version_major == 2) { 1961 gfx_v11_0_load_rlcg_microcode(adev); 1962 if (amdgpu_dpm == 1) { 1963 if (version_minor >= 2) 1964 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 1965 if (version_minor == 3) 1966 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 1967 } 1968 1969 return 0; 1970 } 1971 1972 return -EINVAL; 1973 } 1974 1975 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 1976 { 1977 int r; 1978 1979 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1980 gfx_v11_0_init_csb(adev); 1981 1982 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1983 gfx_v11_0_rlc_enable_srm(adev); 1984 } else { 1985 if (amdgpu_sriov_vf(adev)) { 1986 gfx_v11_0_init_csb(adev); 1987 return 0; 1988 } 1989 1990 adev->gfx.rlc.funcs->stop(adev); 1991 1992 /* disable CG */ 1993 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1994 1995 /* disable PG */ 1996 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1997 1998 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1999 /* legacy rlc firmware loading */ 2000 r = gfx_v11_0_rlc_load_microcode(adev); 2001 if (r) 2002 return r; 2003 } 2004 2005 gfx_v11_0_init_csb(adev); 2006 2007 adev->gfx.rlc.funcs->start(adev); 2008 } 2009 return 0; 2010 } 2011 2012 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2013 { 2014 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2015 uint32_t tmp; 2016 int i; 2017 2018 /* Trigger an invalidation of the L1 instruction caches */ 2019 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2020 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2021 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2022 2023 /* Wait for invalidation complete */ 2024 for (i = 0; i < usec_timeout; i++) { 2025 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2026 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2027 INVALIDATE_CACHE_COMPLETE)) 2028 break; 2029 udelay(1); 2030 } 2031 2032 if (i >= usec_timeout) { 2033 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2034 return -EINVAL; 2035 } 2036 2037 if (amdgpu_emu_mode == 1) 2038 adev->hdp.funcs->flush_hdp(adev, NULL); 2039 2040 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2041 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2042 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2043 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2044 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2045 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2046 2047 /* Program me ucode address into intruction cache address register */ 2048 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2049 lower_32_bits(addr) & 0xFFFFF000); 2050 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2051 upper_32_bits(addr)); 2052 2053 return 0; 2054 } 2055 2056 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2057 { 2058 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2059 uint32_t tmp; 2060 int i; 2061 2062 /* Trigger an invalidation of the L1 instruction caches */ 2063 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2064 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2065 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2066 2067 /* Wait for invalidation complete */ 2068 for (i = 0; i < usec_timeout; i++) { 2069 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2070 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2071 INVALIDATE_CACHE_COMPLETE)) 2072 break; 2073 udelay(1); 2074 } 2075 2076 if (i >= usec_timeout) { 2077 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2078 return -EINVAL; 2079 } 2080 2081 if (amdgpu_emu_mode == 1) 2082 adev->hdp.funcs->flush_hdp(adev, NULL); 2083 2084 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2085 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2086 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2087 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2088 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2089 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2090 2091 /* Program pfp ucode address into intruction cache address register */ 2092 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2093 lower_32_bits(addr) & 0xFFFFF000); 2094 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2095 upper_32_bits(addr)); 2096 2097 return 0; 2098 } 2099 2100 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2101 { 2102 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2103 uint32_t tmp; 2104 int i; 2105 2106 /* Trigger an invalidation of the L1 instruction caches */ 2107 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2108 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2109 2110 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2111 2112 /* Wait for invalidation complete */ 2113 for (i = 0; i < usec_timeout; i++) { 2114 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2115 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2116 INVALIDATE_CACHE_COMPLETE)) 2117 break; 2118 udelay(1); 2119 } 2120 2121 if (i >= usec_timeout) { 2122 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2123 return -EINVAL; 2124 } 2125 2126 if (amdgpu_emu_mode == 1) 2127 adev->hdp.funcs->flush_hdp(adev, NULL); 2128 2129 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2130 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2131 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2132 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2133 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2134 2135 /* Program mec1 ucode address into intruction cache address register */ 2136 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2137 lower_32_bits(addr) & 0xFFFFF000); 2138 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2139 upper_32_bits(addr)); 2140 2141 return 0; 2142 } 2143 2144 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2145 { 2146 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2147 uint32_t tmp; 2148 unsigned i, pipe_id; 2149 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2150 2151 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2152 adev->gfx.pfp_fw->data; 2153 2154 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2155 lower_32_bits(addr)); 2156 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2157 upper_32_bits(addr)); 2158 2159 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2160 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2161 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2162 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2163 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2164 2165 /* 2166 * Programming any of the CP_PFP_IC_BASE registers 2167 * forces invalidation of the ME L1 I$. Wait for the 2168 * invalidation complete 2169 */ 2170 for (i = 0; i < usec_timeout; i++) { 2171 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2172 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2173 INVALIDATE_CACHE_COMPLETE)) 2174 break; 2175 udelay(1); 2176 } 2177 2178 if (i >= usec_timeout) { 2179 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2180 return -EINVAL; 2181 } 2182 2183 /* Prime the L1 instruction caches */ 2184 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2185 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2186 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2187 /* Waiting for cache primed*/ 2188 for (i = 0; i < usec_timeout; i++) { 2189 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2190 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2191 ICACHE_PRIMED)) 2192 break; 2193 udelay(1); 2194 } 2195 2196 if (i >= usec_timeout) { 2197 dev_err(adev->dev, "failed to prime instruction cache\n"); 2198 return -EINVAL; 2199 } 2200 2201 mutex_lock(&adev->srbm_mutex); 2202 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2203 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2204 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2205 (pfp_hdr->ucode_start_addr_hi << 30) | 2206 (pfp_hdr->ucode_start_addr_lo >> 2)); 2207 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2208 pfp_hdr->ucode_start_addr_hi >> 2); 2209 2210 /* 2211 * Program CP_ME_CNTL to reset given PIPE to take 2212 * effect of CP_PFP_PRGRM_CNTR_START. 2213 */ 2214 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2215 if (pipe_id == 0) 2216 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2217 PFP_PIPE0_RESET, 1); 2218 else 2219 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2220 PFP_PIPE1_RESET, 1); 2221 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2222 2223 /* Clear pfp pipe0 reset bit. */ 2224 if (pipe_id == 0) 2225 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2226 PFP_PIPE0_RESET, 0); 2227 else 2228 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2229 PFP_PIPE1_RESET, 0); 2230 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2231 2232 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2233 lower_32_bits(addr2)); 2234 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2235 upper_32_bits(addr2)); 2236 } 2237 soc21_grbm_select(adev, 0, 0, 0, 0); 2238 mutex_unlock(&adev->srbm_mutex); 2239 2240 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2241 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2242 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2243 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2244 2245 /* Invalidate the data caches */ 2246 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2247 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2248 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2249 2250 for (i = 0; i < usec_timeout; i++) { 2251 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2252 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2253 INVALIDATE_DCACHE_COMPLETE)) 2254 break; 2255 udelay(1); 2256 } 2257 2258 if (i >= usec_timeout) { 2259 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2260 return -EINVAL; 2261 } 2262 2263 return 0; 2264 } 2265 2266 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2267 { 2268 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2269 uint32_t tmp; 2270 unsigned i, pipe_id; 2271 const struct gfx_firmware_header_v2_0 *me_hdr; 2272 2273 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2274 adev->gfx.me_fw->data; 2275 2276 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2277 lower_32_bits(addr)); 2278 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2279 upper_32_bits(addr)); 2280 2281 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2282 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2283 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2284 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2285 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2286 2287 /* 2288 * Programming any of the CP_ME_IC_BASE registers 2289 * forces invalidation of the ME L1 I$. Wait for the 2290 * invalidation complete 2291 */ 2292 for (i = 0; i < usec_timeout; i++) { 2293 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2294 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2295 INVALIDATE_CACHE_COMPLETE)) 2296 break; 2297 udelay(1); 2298 } 2299 2300 if (i >= usec_timeout) { 2301 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2302 return -EINVAL; 2303 } 2304 2305 /* Prime the instruction caches */ 2306 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2307 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2308 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2309 2310 /* Waiting for instruction cache primed*/ 2311 for (i = 0; i < usec_timeout; i++) { 2312 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2313 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2314 ICACHE_PRIMED)) 2315 break; 2316 udelay(1); 2317 } 2318 2319 if (i >= usec_timeout) { 2320 dev_err(adev->dev, "failed to prime instruction cache\n"); 2321 return -EINVAL; 2322 } 2323 2324 mutex_lock(&adev->srbm_mutex); 2325 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2326 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2327 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2328 (me_hdr->ucode_start_addr_hi << 30) | 2329 (me_hdr->ucode_start_addr_lo >> 2) ); 2330 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2331 me_hdr->ucode_start_addr_hi>>2); 2332 2333 /* 2334 * Program CP_ME_CNTL to reset given PIPE to take 2335 * effect of CP_PFP_PRGRM_CNTR_START. 2336 */ 2337 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2338 if (pipe_id == 0) 2339 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2340 ME_PIPE0_RESET, 1); 2341 else 2342 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2343 ME_PIPE1_RESET, 1); 2344 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2345 2346 /* Clear pfp pipe0 reset bit. */ 2347 if (pipe_id == 0) 2348 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2349 ME_PIPE0_RESET, 0); 2350 else 2351 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2352 ME_PIPE1_RESET, 0); 2353 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2354 2355 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2356 lower_32_bits(addr2)); 2357 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2358 upper_32_bits(addr2)); 2359 } 2360 soc21_grbm_select(adev, 0, 0, 0, 0); 2361 mutex_unlock(&adev->srbm_mutex); 2362 2363 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2364 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2365 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2366 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2367 2368 /* Invalidate the data caches */ 2369 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2370 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2371 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2372 2373 for (i = 0; i < usec_timeout; i++) { 2374 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2375 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2376 INVALIDATE_DCACHE_COMPLETE)) 2377 break; 2378 udelay(1); 2379 } 2380 2381 if (i >= usec_timeout) { 2382 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2383 return -EINVAL; 2384 } 2385 2386 return 0; 2387 } 2388 2389 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2390 { 2391 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2392 uint32_t tmp; 2393 unsigned i; 2394 const struct gfx_firmware_header_v2_0 *mec_hdr; 2395 2396 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2397 adev->gfx.mec_fw->data; 2398 2399 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2400 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2401 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2402 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2403 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2404 2405 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2406 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2407 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2408 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2409 2410 mutex_lock(&adev->srbm_mutex); 2411 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2412 soc21_grbm_select(adev, 1, i, 0, 0); 2413 2414 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2415 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2416 upper_32_bits(addr2)); 2417 2418 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2419 mec_hdr->ucode_start_addr_lo >> 2 | 2420 mec_hdr->ucode_start_addr_hi << 30); 2421 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2422 mec_hdr->ucode_start_addr_hi >> 2); 2423 2424 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2425 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2426 upper_32_bits(addr)); 2427 } 2428 mutex_unlock(&adev->srbm_mutex); 2429 soc21_grbm_select(adev, 0, 0, 0, 0); 2430 2431 /* Trigger an invalidation of the L1 instruction caches */ 2432 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2433 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2434 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2435 2436 /* Wait for invalidation complete */ 2437 for (i = 0; i < usec_timeout; i++) { 2438 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2439 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2440 INVALIDATE_DCACHE_COMPLETE)) 2441 break; 2442 udelay(1); 2443 } 2444 2445 if (i >= usec_timeout) { 2446 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2447 return -EINVAL; 2448 } 2449 2450 /* Trigger an invalidation of the L1 instruction caches */ 2451 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2452 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2453 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2454 2455 /* Wait for invalidation complete */ 2456 for (i = 0; i < usec_timeout; i++) { 2457 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2458 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2459 INVALIDATE_CACHE_COMPLETE)) 2460 break; 2461 udelay(1); 2462 } 2463 2464 if (i >= usec_timeout) { 2465 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2466 return -EINVAL; 2467 } 2468 2469 return 0; 2470 } 2471 2472 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2473 { 2474 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2475 const struct gfx_firmware_header_v2_0 *me_hdr; 2476 const struct gfx_firmware_header_v2_0 *mec_hdr; 2477 uint32_t pipe_id, tmp; 2478 2479 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2480 adev->gfx.mec_fw->data; 2481 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2482 adev->gfx.me_fw->data; 2483 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2484 adev->gfx.pfp_fw->data; 2485 2486 /* config pfp program start addr */ 2487 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2488 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2489 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2490 (pfp_hdr->ucode_start_addr_hi << 30) | 2491 (pfp_hdr->ucode_start_addr_lo >> 2)); 2492 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2493 pfp_hdr->ucode_start_addr_hi >> 2); 2494 } 2495 soc21_grbm_select(adev, 0, 0, 0, 0); 2496 2497 /* reset pfp pipe */ 2498 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2499 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2500 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2501 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2502 2503 /* clear pfp pipe reset */ 2504 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2505 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2506 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2507 2508 /* config me program start addr */ 2509 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2510 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2511 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2512 (me_hdr->ucode_start_addr_hi << 30) | 2513 (me_hdr->ucode_start_addr_lo >> 2) ); 2514 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2515 me_hdr->ucode_start_addr_hi>>2); 2516 } 2517 soc21_grbm_select(adev, 0, 0, 0, 0); 2518 2519 /* reset me pipe */ 2520 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2521 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2522 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2523 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2524 2525 /* clear me pipe reset */ 2526 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2527 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2528 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2529 2530 /* config mec program start addr */ 2531 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2532 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2533 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2534 mec_hdr->ucode_start_addr_lo >> 2 | 2535 mec_hdr->ucode_start_addr_hi << 30); 2536 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2537 mec_hdr->ucode_start_addr_hi >> 2); 2538 } 2539 soc21_grbm_select(adev, 0, 0, 0, 0); 2540 2541 /* reset mec pipe */ 2542 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2543 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2544 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2545 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2546 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2547 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2548 2549 /* clear mec pipe reset */ 2550 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2551 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2552 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2553 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2554 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2555 } 2556 2557 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2558 { 2559 uint32_t cp_status; 2560 uint32_t bootload_status; 2561 int i, r; 2562 uint64_t addr, addr2; 2563 2564 for (i = 0; i < adev->usec_timeout; i++) { 2565 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2566 2567 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) || 2568 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4)) 2569 bootload_status = RREG32_SOC15(GC, 0, 2570 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2571 else 2572 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2573 2574 if ((cp_status == 0) && 2575 (REG_GET_FIELD(bootload_status, 2576 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2577 break; 2578 } 2579 udelay(1); 2580 } 2581 2582 if (i >= adev->usec_timeout) { 2583 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2584 return -ETIMEDOUT; 2585 } 2586 2587 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2588 if (adev->gfx.rs64_enable) { 2589 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2590 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2591 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2592 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2593 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2594 if (r) 2595 return r; 2596 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2597 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2598 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2599 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2600 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2601 if (r) 2602 return r; 2603 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2604 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2605 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2606 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2607 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2608 if (r) 2609 return r; 2610 } else { 2611 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2612 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2613 r = gfx_v11_0_config_me_cache(adev, addr); 2614 if (r) 2615 return r; 2616 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2617 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2618 r = gfx_v11_0_config_pfp_cache(adev, addr); 2619 if (r) 2620 return r; 2621 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2622 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2623 r = gfx_v11_0_config_mec_cache(adev, addr); 2624 if (r) 2625 return r; 2626 } 2627 } 2628 2629 return 0; 2630 } 2631 2632 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2633 { 2634 int i; 2635 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2636 2637 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2638 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2639 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2640 2641 for (i = 0; i < adev->usec_timeout; i++) { 2642 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2643 break; 2644 udelay(1); 2645 } 2646 2647 if (i >= adev->usec_timeout) 2648 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2649 2650 return 0; 2651 } 2652 2653 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2654 { 2655 int r; 2656 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2657 const __le32 *fw_data; 2658 unsigned i, fw_size; 2659 2660 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2661 adev->gfx.pfp_fw->data; 2662 2663 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2664 2665 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2666 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2667 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2668 2669 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2670 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2671 &adev->gfx.pfp.pfp_fw_obj, 2672 &adev->gfx.pfp.pfp_fw_gpu_addr, 2673 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2674 if (r) { 2675 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2676 gfx_v11_0_pfp_fini(adev); 2677 return r; 2678 } 2679 2680 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2681 2682 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2683 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2684 2685 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2686 2687 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2688 2689 for (i = 0; i < pfp_hdr->jt_size; i++) 2690 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2691 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2692 2693 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2694 2695 return 0; 2696 } 2697 2698 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2699 { 2700 int r; 2701 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2702 const __le32 *fw_ucode, *fw_data; 2703 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2704 uint32_t tmp; 2705 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2706 2707 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2708 adev->gfx.pfp_fw->data; 2709 2710 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2711 2712 /* instruction */ 2713 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2714 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2715 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2716 /* data */ 2717 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2718 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2719 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2720 2721 /* 64kb align */ 2722 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2723 64 * 1024, 2724 AMDGPU_GEM_DOMAIN_VRAM | 2725 AMDGPU_GEM_DOMAIN_GTT, 2726 &adev->gfx.pfp.pfp_fw_obj, 2727 &adev->gfx.pfp.pfp_fw_gpu_addr, 2728 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2729 if (r) { 2730 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2731 gfx_v11_0_pfp_fini(adev); 2732 return r; 2733 } 2734 2735 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2736 64 * 1024, 2737 AMDGPU_GEM_DOMAIN_VRAM | 2738 AMDGPU_GEM_DOMAIN_GTT, 2739 &adev->gfx.pfp.pfp_fw_data_obj, 2740 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2741 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2742 if (r) { 2743 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2744 gfx_v11_0_pfp_fini(adev); 2745 return r; 2746 } 2747 2748 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2749 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2750 2751 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2752 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2753 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2754 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2755 2756 if (amdgpu_emu_mode == 1) 2757 adev->hdp.funcs->flush_hdp(adev, NULL); 2758 2759 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2760 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2761 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2762 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2763 2764 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2765 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2766 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2767 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2768 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2769 2770 /* 2771 * Programming any of the CP_PFP_IC_BASE registers 2772 * forces invalidation of the ME L1 I$. Wait for the 2773 * invalidation complete 2774 */ 2775 for (i = 0; i < usec_timeout; i++) { 2776 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2777 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2778 INVALIDATE_CACHE_COMPLETE)) 2779 break; 2780 udelay(1); 2781 } 2782 2783 if (i >= usec_timeout) { 2784 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2785 return -EINVAL; 2786 } 2787 2788 /* Prime the L1 instruction caches */ 2789 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2790 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2791 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2792 /* Waiting for cache primed*/ 2793 for (i = 0; i < usec_timeout; i++) { 2794 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2795 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2796 ICACHE_PRIMED)) 2797 break; 2798 udelay(1); 2799 } 2800 2801 if (i >= usec_timeout) { 2802 dev_err(adev->dev, "failed to prime instruction cache\n"); 2803 return -EINVAL; 2804 } 2805 2806 mutex_lock(&adev->srbm_mutex); 2807 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2808 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2809 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2810 (pfp_hdr->ucode_start_addr_hi << 30) | 2811 (pfp_hdr->ucode_start_addr_lo >> 2) ); 2812 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2813 pfp_hdr->ucode_start_addr_hi>>2); 2814 2815 /* 2816 * Program CP_ME_CNTL to reset given PIPE to take 2817 * effect of CP_PFP_PRGRM_CNTR_START. 2818 */ 2819 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2820 if (pipe_id == 0) 2821 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2822 PFP_PIPE0_RESET, 1); 2823 else 2824 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2825 PFP_PIPE1_RESET, 1); 2826 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2827 2828 /* Clear pfp pipe0 reset bit. */ 2829 if (pipe_id == 0) 2830 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2831 PFP_PIPE0_RESET, 0); 2832 else 2833 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2834 PFP_PIPE1_RESET, 0); 2835 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2836 2837 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2838 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2839 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2840 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2841 } 2842 soc21_grbm_select(adev, 0, 0, 0, 0); 2843 mutex_unlock(&adev->srbm_mutex); 2844 2845 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2846 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2847 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2848 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2849 2850 /* Invalidate the data caches */ 2851 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2852 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2853 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2854 2855 for (i = 0; i < usec_timeout; i++) { 2856 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2857 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2858 INVALIDATE_DCACHE_COMPLETE)) 2859 break; 2860 udelay(1); 2861 } 2862 2863 if (i >= usec_timeout) { 2864 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2865 return -EINVAL; 2866 } 2867 2868 return 0; 2869 } 2870 2871 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2872 { 2873 int r; 2874 const struct gfx_firmware_header_v1_0 *me_hdr; 2875 const __le32 *fw_data; 2876 unsigned i, fw_size; 2877 2878 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2879 adev->gfx.me_fw->data; 2880 2881 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2882 2883 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2884 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2885 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2886 2887 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2888 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2889 &adev->gfx.me.me_fw_obj, 2890 &adev->gfx.me.me_fw_gpu_addr, 2891 (void **)&adev->gfx.me.me_fw_ptr); 2892 if (r) { 2893 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2894 gfx_v11_0_me_fini(adev); 2895 return r; 2896 } 2897 2898 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2899 2900 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2901 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2902 2903 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 2904 2905 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 2906 2907 for (i = 0; i < me_hdr->jt_size; i++) 2908 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 2909 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 2910 2911 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 2912 2913 return 0; 2914 } 2915 2916 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2917 { 2918 int r; 2919 const struct gfx_firmware_header_v2_0 *me_hdr; 2920 const __le32 *fw_ucode, *fw_data; 2921 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2922 uint32_t tmp; 2923 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2924 2925 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2926 adev->gfx.me_fw->data; 2927 2928 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2929 2930 /* instruction */ 2931 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2932 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2933 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2934 /* data */ 2935 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2936 le32_to_cpu(me_hdr->data_offset_bytes)); 2937 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2938 2939 /* 64kb align*/ 2940 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2941 64 * 1024, 2942 AMDGPU_GEM_DOMAIN_VRAM | 2943 AMDGPU_GEM_DOMAIN_GTT, 2944 &adev->gfx.me.me_fw_obj, 2945 &adev->gfx.me.me_fw_gpu_addr, 2946 (void **)&adev->gfx.me.me_fw_ptr); 2947 if (r) { 2948 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2949 gfx_v11_0_me_fini(adev); 2950 return r; 2951 } 2952 2953 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2954 64 * 1024, 2955 AMDGPU_GEM_DOMAIN_VRAM | 2956 AMDGPU_GEM_DOMAIN_GTT, 2957 &adev->gfx.me.me_fw_data_obj, 2958 &adev->gfx.me.me_fw_data_gpu_addr, 2959 (void **)&adev->gfx.me.me_fw_data_ptr); 2960 if (r) { 2961 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2962 gfx_v11_0_pfp_fini(adev); 2963 return r; 2964 } 2965 2966 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2967 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2968 2969 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2970 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2971 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2972 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2973 2974 if (amdgpu_emu_mode == 1) 2975 adev->hdp.funcs->flush_hdp(adev, NULL); 2976 2977 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2978 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2979 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2980 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2981 2982 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2983 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2984 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2985 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2986 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2987 2988 /* 2989 * Programming any of the CP_ME_IC_BASE registers 2990 * forces invalidation of the ME L1 I$. Wait for the 2991 * invalidation complete 2992 */ 2993 for (i = 0; i < usec_timeout; i++) { 2994 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2995 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2996 INVALIDATE_CACHE_COMPLETE)) 2997 break; 2998 udelay(1); 2999 } 3000 3001 if (i >= usec_timeout) { 3002 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3003 return -EINVAL; 3004 } 3005 3006 /* Prime the instruction caches */ 3007 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3008 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3009 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3010 3011 /* Waiting for instruction cache primed*/ 3012 for (i = 0; i < usec_timeout; i++) { 3013 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3014 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3015 ICACHE_PRIMED)) 3016 break; 3017 udelay(1); 3018 } 3019 3020 if (i >= usec_timeout) { 3021 dev_err(adev->dev, "failed to prime instruction cache\n"); 3022 return -EINVAL; 3023 } 3024 3025 mutex_lock(&adev->srbm_mutex); 3026 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3027 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3028 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3029 (me_hdr->ucode_start_addr_hi << 30) | 3030 (me_hdr->ucode_start_addr_lo >> 2) ); 3031 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3032 me_hdr->ucode_start_addr_hi>>2); 3033 3034 /* 3035 * Program CP_ME_CNTL to reset given PIPE to take 3036 * effect of CP_PFP_PRGRM_CNTR_START. 3037 */ 3038 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3039 if (pipe_id == 0) 3040 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3041 ME_PIPE0_RESET, 1); 3042 else 3043 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3044 ME_PIPE1_RESET, 1); 3045 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3046 3047 /* Clear pfp pipe0 reset bit. */ 3048 if (pipe_id == 0) 3049 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3050 ME_PIPE0_RESET, 0); 3051 else 3052 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3053 ME_PIPE1_RESET, 0); 3054 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3055 3056 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3057 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3058 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3059 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3060 } 3061 soc21_grbm_select(adev, 0, 0, 0, 0); 3062 mutex_unlock(&adev->srbm_mutex); 3063 3064 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3065 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3066 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3067 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3068 3069 /* Invalidate the data caches */ 3070 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3071 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3072 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3073 3074 for (i = 0; i < usec_timeout; i++) { 3075 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3076 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3077 INVALIDATE_DCACHE_COMPLETE)) 3078 break; 3079 udelay(1); 3080 } 3081 3082 if (i >= usec_timeout) { 3083 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3084 return -EINVAL; 3085 } 3086 3087 return 0; 3088 } 3089 3090 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3091 { 3092 int r; 3093 3094 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3095 return -EINVAL; 3096 3097 gfx_v11_0_cp_gfx_enable(adev, false); 3098 3099 if (adev->gfx.rs64_enable) 3100 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3101 else 3102 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3103 if (r) { 3104 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3105 return r; 3106 } 3107 3108 if (adev->gfx.rs64_enable) 3109 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3110 else 3111 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3112 if (r) { 3113 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3114 return r; 3115 } 3116 3117 return 0; 3118 } 3119 3120 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3121 { 3122 struct amdgpu_ring *ring; 3123 const struct cs_section_def *sect = NULL; 3124 const struct cs_extent_def *ext = NULL; 3125 int r, i; 3126 int ctx_reg_offset; 3127 3128 /* init the CP */ 3129 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3130 adev->gfx.config.max_hw_contexts - 1); 3131 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3132 3133 if (!amdgpu_async_gfx_ring) 3134 gfx_v11_0_cp_gfx_enable(adev, true); 3135 3136 ring = &adev->gfx.gfx_ring[0]; 3137 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3138 if (r) { 3139 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3140 return r; 3141 } 3142 3143 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3144 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3145 3146 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3147 amdgpu_ring_write(ring, 0x80000000); 3148 amdgpu_ring_write(ring, 0x80000000); 3149 3150 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3151 for (ext = sect->section; ext->extent != NULL; ++ext) { 3152 if (sect->id == SECT_CONTEXT) { 3153 amdgpu_ring_write(ring, 3154 PACKET3(PACKET3_SET_CONTEXT_REG, 3155 ext->reg_count)); 3156 amdgpu_ring_write(ring, ext->reg_index - 3157 PACKET3_SET_CONTEXT_REG_START); 3158 for (i = 0; i < ext->reg_count; i++) 3159 amdgpu_ring_write(ring, ext->extent[i]); 3160 } 3161 } 3162 } 3163 3164 ctx_reg_offset = 3165 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3166 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3167 amdgpu_ring_write(ring, ctx_reg_offset); 3168 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3169 3170 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3171 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3172 3173 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3174 amdgpu_ring_write(ring, 0); 3175 3176 amdgpu_ring_commit(ring); 3177 3178 /* submit cs packet to copy state 0 to next available state */ 3179 if (adev->gfx.num_gfx_rings > 1) { 3180 /* maximum supported gfx ring is 2 */ 3181 ring = &adev->gfx.gfx_ring[1]; 3182 r = amdgpu_ring_alloc(ring, 2); 3183 if (r) { 3184 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3185 return r; 3186 } 3187 3188 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3189 amdgpu_ring_write(ring, 0); 3190 3191 amdgpu_ring_commit(ring); 3192 } 3193 return 0; 3194 } 3195 3196 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3197 CP_PIPE_ID pipe) 3198 { 3199 u32 tmp; 3200 3201 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3202 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3203 3204 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3205 } 3206 3207 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3208 struct amdgpu_ring *ring) 3209 { 3210 u32 tmp; 3211 3212 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3213 if (ring->use_doorbell) { 3214 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3215 DOORBELL_OFFSET, ring->doorbell_index); 3216 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3217 DOORBELL_EN, 1); 3218 } else { 3219 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3220 DOORBELL_EN, 0); 3221 } 3222 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3223 3224 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3225 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3226 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3227 3228 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3229 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3230 } 3231 3232 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3233 { 3234 struct amdgpu_ring *ring; 3235 u32 tmp; 3236 u32 rb_bufsz; 3237 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3238 u32 i; 3239 3240 /* Set the write pointer delay */ 3241 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3242 3243 /* set the RB to use vmid 0 */ 3244 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3245 3246 /* Init gfx ring 0 for pipe 0 */ 3247 mutex_lock(&adev->srbm_mutex); 3248 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3249 3250 /* Set ring buffer size */ 3251 ring = &adev->gfx.gfx_ring[0]; 3252 rb_bufsz = order_base_2(ring->ring_size / 8); 3253 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3254 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3255 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3256 3257 /* Initialize the ring buffer's write pointers */ 3258 ring->wptr = 0; 3259 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3260 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3261 3262 /* set the wb address wether it's enabled or not */ 3263 rptr_addr = ring->rptr_gpu_addr; 3264 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3265 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3266 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3267 3268 wptr_gpu_addr = ring->wptr_gpu_addr; 3269 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3270 lower_32_bits(wptr_gpu_addr)); 3271 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3272 upper_32_bits(wptr_gpu_addr)); 3273 3274 mdelay(1); 3275 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3276 3277 rb_addr = ring->gpu_addr >> 8; 3278 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3279 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3280 3281 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3282 3283 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3284 mutex_unlock(&adev->srbm_mutex); 3285 3286 /* Init gfx ring 1 for pipe 1 */ 3287 if (adev->gfx.num_gfx_rings > 1) { 3288 mutex_lock(&adev->srbm_mutex); 3289 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3290 /* maximum supported gfx ring is 2 */ 3291 ring = &adev->gfx.gfx_ring[1]; 3292 rb_bufsz = order_base_2(ring->ring_size / 8); 3293 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3294 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3295 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3296 /* Initialize the ring buffer's write pointers */ 3297 ring->wptr = 0; 3298 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3299 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3300 /* Set the wb address wether it's enabled or not */ 3301 rptr_addr = ring->rptr_gpu_addr; 3302 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3303 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3304 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3305 wptr_gpu_addr = ring->wptr_gpu_addr; 3306 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3307 lower_32_bits(wptr_gpu_addr)); 3308 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3309 upper_32_bits(wptr_gpu_addr)); 3310 3311 mdelay(1); 3312 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3313 3314 rb_addr = ring->gpu_addr >> 8; 3315 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3316 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3317 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3318 3319 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3320 mutex_unlock(&adev->srbm_mutex); 3321 } 3322 /* Switch to pipe 0 */ 3323 mutex_lock(&adev->srbm_mutex); 3324 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3325 mutex_unlock(&adev->srbm_mutex); 3326 3327 /* start the ring */ 3328 gfx_v11_0_cp_gfx_start(adev); 3329 3330 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3331 ring = &adev->gfx.gfx_ring[i]; 3332 ring->sched.ready = true; 3333 } 3334 3335 return 0; 3336 } 3337 3338 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3339 { 3340 u32 data; 3341 3342 if (adev->gfx.rs64_enable) { 3343 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3344 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3345 enable ? 0 : 1); 3346 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3347 enable ? 0 : 1); 3348 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3349 enable ? 0 : 1); 3350 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3351 enable ? 0 : 1); 3352 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3353 enable ? 0 : 1); 3354 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3355 enable ? 1 : 0); 3356 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3357 enable ? 1 : 0); 3358 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3359 enable ? 1 : 0); 3360 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3361 enable ? 1 : 0); 3362 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3363 enable ? 0 : 1); 3364 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3365 } else { 3366 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3367 3368 if (enable) { 3369 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3370 if (!adev->enable_mes_kiq) 3371 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3372 MEC_ME2_HALT, 0); 3373 } else { 3374 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3375 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3376 } 3377 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3378 } 3379 3380 adev->gfx.kiq[0].ring.sched.ready = enable; 3381 3382 udelay(50); 3383 } 3384 3385 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3386 { 3387 const struct gfx_firmware_header_v1_0 *mec_hdr; 3388 const __le32 *fw_data; 3389 unsigned i, fw_size; 3390 u32 *fw = NULL; 3391 int r; 3392 3393 if (!adev->gfx.mec_fw) 3394 return -EINVAL; 3395 3396 gfx_v11_0_cp_compute_enable(adev, false); 3397 3398 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3399 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3400 3401 fw_data = (const __le32 *) 3402 (adev->gfx.mec_fw->data + 3403 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3404 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3405 3406 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3407 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3408 &adev->gfx.mec.mec_fw_obj, 3409 &adev->gfx.mec.mec_fw_gpu_addr, 3410 (void **)&fw); 3411 if (r) { 3412 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3413 gfx_v11_0_mec_fini(adev); 3414 return r; 3415 } 3416 3417 memcpy(fw, fw_data, fw_size); 3418 3419 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3420 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3421 3422 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3423 3424 /* MEC1 */ 3425 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3426 3427 for (i = 0; i < mec_hdr->jt_size; i++) 3428 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3429 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3430 3431 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3432 3433 return 0; 3434 } 3435 3436 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3437 { 3438 const struct gfx_firmware_header_v2_0 *mec_hdr; 3439 const __le32 *fw_ucode, *fw_data; 3440 u32 tmp, fw_ucode_size, fw_data_size; 3441 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3442 u32 *fw_ucode_ptr, *fw_data_ptr; 3443 int r; 3444 3445 if (!adev->gfx.mec_fw) 3446 return -EINVAL; 3447 3448 gfx_v11_0_cp_compute_enable(adev, false); 3449 3450 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3451 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3452 3453 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3454 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3455 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3456 3457 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3458 le32_to_cpu(mec_hdr->data_offset_bytes)); 3459 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3460 3461 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3462 64 * 1024, 3463 AMDGPU_GEM_DOMAIN_VRAM | 3464 AMDGPU_GEM_DOMAIN_GTT, 3465 &adev->gfx.mec.mec_fw_obj, 3466 &adev->gfx.mec.mec_fw_gpu_addr, 3467 (void **)&fw_ucode_ptr); 3468 if (r) { 3469 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3470 gfx_v11_0_mec_fini(adev); 3471 return r; 3472 } 3473 3474 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3475 64 * 1024, 3476 AMDGPU_GEM_DOMAIN_VRAM | 3477 AMDGPU_GEM_DOMAIN_GTT, 3478 &adev->gfx.mec.mec_fw_data_obj, 3479 &adev->gfx.mec.mec_fw_data_gpu_addr, 3480 (void **)&fw_data_ptr); 3481 if (r) { 3482 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3483 gfx_v11_0_mec_fini(adev); 3484 return r; 3485 } 3486 3487 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3488 memcpy(fw_data_ptr, fw_data, fw_data_size); 3489 3490 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3491 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3492 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3493 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3494 3495 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3496 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3497 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3498 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3499 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3500 3501 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3502 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3503 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3504 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3505 3506 mutex_lock(&adev->srbm_mutex); 3507 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3508 soc21_grbm_select(adev, 1, i, 0, 0); 3509 3510 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3511 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3512 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3513 3514 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3515 mec_hdr->ucode_start_addr_lo >> 2 | 3516 mec_hdr->ucode_start_addr_hi << 30); 3517 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3518 mec_hdr->ucode_start_addr_hi >> 2); 3519 3520 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3521 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3522 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3523 } 3524 mutex_unlock(&adev->srbm_mutex); 3525 soc21_grbm_select(adev, 0, 0, 0, 0); 3526 3527 /* Trigger an invalidation of the L1 instruction caches */ 3528 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3529 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3530 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3531 3532 /* Wait for invalidation complete */ 3533 for (i = 0; i < usec_timeout; i++) { 3534 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3535 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3536 INVALIDATE_DCACHE_COMPLETE)) 3537 break; 3538 udelay(1); 3539 } 3540 3541 if (i >= usec_timeout) { 3542 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3543 return -EINVAL; 3544 } 3545 3546 /* Trigger an invalidation of the L1 instruction caches */ 3547 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3548 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3549 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3550 3551 /* Wait for invalidation complete */ 3552 for (i = 0; i < usec_timeout; i++) { 3553 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3554 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3555 INVALIDATE_CACHE_COMPLETE)) 3556 break; 3557 udelay(1); 3558 } 3559 3560 if (i >= usec_timeout) { 3561 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3562 return -EINVAL; 3563 } 3564 3565 return 0; 3566 } 3567 3568 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3569 { 3570 uint32_t tmp; 3571 struct amdgpu_device *adev = ring->adev; 3572 3573 /* tell RLC which is KIQ queue */ 3574 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3575 tmp &= 0xffffff00; 3576 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3577 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3578 tmp |= 0x80; 3579 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3580 } 3581 3582 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3583 { 3584 /* set graphics engine doorbell range */ 3585 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3586 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3587 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3588 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3589 3590 /* set compute engine doorbell range */ 3591 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3592 (adev->doorbell_index.kiq * 2) << 2); 3593 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3594 (adev->doorbell_index.userqueue_end * 2) << 2); 3595 } 3596 3597 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3598 struct amdgpu_mqd_prop *prop) 3599 { 3600 struct v11_gfx_mqd *mqd = m; 3601 uint64_t hqd_gpu_addr, wb_gpu_addr; 3602 uint32_t tmp; 3603 uint32_t rb_bufsz; 3604 3605 /* set up gfx hqd wptr */ 3606 mqd->cp_gfx_hqd_wptr = 0; 3607 mqd->cp_gfx_hqd_wptr_hi = 0; 3608 3609 /* set the pointer to the MQD */ 3610 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3611 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3612 3613 /* set up mqd control */ 3614 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3615 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3616 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3617 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3618 mqd->cp_gfx_mqd_control = tmp; 3619 3620 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3621 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3622 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3623 mqd->cp_gfx_hqd_vmid = 0; 3624 3625 /* set up default queue priority level 3626 * 0x0 = low priority, 0x1 = high priority */ 3627 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3628 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3629 mqd->cp_gfx_hqd_queue_priority = tmp; 3630 3631 /* set up time quantum */ 3632 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3633 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3634 mqd->cp_gfx_hqd_quantum = tmp; 3635 3636 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3637 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3638 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3639 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3640 3641 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3642 wb_gpu_addr = prop->rptr_gpu_addr; 3643 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3644 mqd->cp_gfx_hqd_rptr_addr_hi = 3645 upper_32_bits(wb_gpu_addr) & 0xffff; 3646 3647 /* set up rb_wptr_poll addr */ 3648 wb_gpu_addr = prop->wptr_gpu_addr; 3649 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3650 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3651 3652 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3653 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3654 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3655 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3656 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3657 #ifdef __BIG_ENDIAN 3658 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3659 #endif 3660 mqd->cp_gfx_hqd_cntl = tmp; 3661 3662 /* set up cp_doorbell_control */ 3663 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3664 if (prop->use_doorbell) { 3665 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3666 DOORBELL_OFFSET, prop->doorbell_index); 3667 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3668 DOORBELL_EN, 1); 3669 } else 3670 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3671 DOORBELL_EN, 0); 3672 mqd->cp_rb_doorbell_control = tmp; 3673 3674 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3675 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3676 3677 /* active the queue */ 3678 mqd->cp_gfx_hqd_active = 1; 3679 3680 return 0; 3681 } 3682 3683 #ifdef BRING_UP_DEBUG 3684 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3685 { 3686 struct amdgpu_device *adev = ring->adev; 3687 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3688 3689 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3690 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3691 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3692 3693 /* set GFX_MQD_BASE */ 3694 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3695 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3696 3697 /* set GFX_MQD_CONTROL */ 3698 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3699 3700 /* set GFX_HQD_VMID to 0 */ 3701 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3702 3703 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY, 3704 mqd->cp_gfx_hqd_queue_priority); 3705 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3706 3707 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3708 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3709 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3710 3711 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3712 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3713 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3714 3715 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3716 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3717 3718 /* set RB_WPTR_POLL_ADDR */ 3719 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3720 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3721 3722 /* set RB_DOORBELL_CONTROL */ 3723 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3724 3725 /* active the queue */ 3726 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3727 3728 return 0; 3729 } 3730 #endif 3731 3732 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3733 { 3734 struct amdgpu_device *adev = ring->adev; 3735 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3736 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3737 3738 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3739 memset((void *)mqd, 0, sizeof(*mqd)); 3740 mutex_lock(&adev->srbm_mutex); 3741 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3742 amdgpu_ring_init_mqd(ring); 3743 #ifdef BRING_UP_DEBUG 3744 gfx_v11_0_gfx_queue_init_register(ring); 3745 #endif 3746 soc21_grbm_select(adev, 0, 0, 0, 0); 3747 mutex_unlock(&adev->srbm_mutex); 3748 if (adev->gfx.me.mqd_backup[mqd_idx]) 3749 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3750 } else if (amdgpu_in_reset(adev)) { 3751 /* reset mqd with the backup copy */ 3752 if (adev->gfx.me.mqd_backup[mqd_idx]) 3753 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3754 /* reset the ring */ 3755 ring->wptr = 0; 3756 *ring->wptr_cpu_addr = 0; 3757 amdgpu_ring_clear_ring(ring); 3758 #ifdef BRING_UP_DEBUG 3759 mutex_lock(&adev->srbm_mutex); 3760 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3761 gfx_v11_0_gfx_queue_init_register(ring); 3762 soc21_grbm_select(adev, 0, 0, 0, 0); 3763 mutex_unlock(&adev->srbm_mutex); 3764 #endif 3765 } else { 3766 amdgpu_ring_clear_ring(ring); 3767 } 3768 3769 return 0; 3770 } 3771 3772 #ifndef BRING_UP_DEBUG 3773 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev) 3774 { 3775 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 3776 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 3777 int r, i; 3778 3779 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3780 return -EINVAL; 3781 3782 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3783 adev->gfx.num_gfx_rings); 3784 if (r) { 3785 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3786 return r; 3787 } 3788 3789 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3790 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3791 3792 return amdgpu_ring_test_helper(kiq_ring); 3793 } 3794 #endif 3795 3796 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3797 { 3798 int r, i; 3799 struct amdgpu_ring *ring; 3800 3801 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3802 ring = &adev->gfx.gfx_ring[i]; 3803 3804 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3805 if (unlikely(r != 0)) 3806 goto done; 3807 3808 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3809 if (!r) { 3810 r = gfx_v11_0_gfx_init_queue(ring); 3811 amdgpu_bo_kunmap(ring->mqd_obj); 3812 ring->mqd_ptr = NULL; 3813 } 3814 amdgpu_bo_unreserve(ring->mqd_obj); 3815 if (r) 3816 goto done; 3817 } 3818 #ifndef BRING_UP_DEBUG 3819 r = gfx_v11_0_kiq_enable_kgq(adev); 3820 if (r) 3821 goto done; 3822 #endif 3823 r = gfx_v11_0_cp_gfx_start(adev); 3824 if (r) 3825 goto done; 3826 3827 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3828 ring = &adev->gfx.gfx_ring[i]; 3829 ring->sched.ready = true; 3830 } 3831 done: 3832 return r; 3833 } 3834 3835 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3836 struct amdgpu_mqd_prop *prop) 3837 { 3838 struct v11_compute_mqd *mqd = m; 3839 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3840 uint32_t tmp; 3841 3842 mqd->header = 0xC0310800; 3843 mqd->compute_pipelinestat_enable = 0x00000001; 3844 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3845 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3846 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3847 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3848 mqd->compute_misc_reserved = 0x00000007; 3849 3850 eop_base_addr = prop->eop_gpu_addr >> 8; 3851 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3852 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3853 3854 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3855 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3856 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3857 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 3858 3859 mqd->cp_hqd_eop_control = tmp; 3860 3861 /* enable doorbell? */ 3862 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3863 3864 if (prop->use_doorbell) { 3865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3866 DOORBELL_OFFSET, prop->doorbell_index); 3867 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3868 DOORBELL_EN, 1); 3869 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3870 DOORBELL_SOURCE, 0); 3871 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3872 DOORBELL_HIT, 0); 3873 } else { 3874 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3875 DOORBELL_EN, 0); 3876 } 3877 3878 mqd->cp_hqd_pq_doorbell_control = tmp; 3879 3880 /* disable the queue if it's active */ 3881 mqd->cp_hqd_dequeue_request = 0; 3882 mqd->cp_hqd_pq_rptr = 0; 3883 mqd->cp_hqd_pq_wptr_lo = 0; 3884 mqd->cp_hqd_pq_wptr_hi = 0; 3885 3886 /* set the pointer to the MQD */ 3887 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3888 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3889 3890 /* set MQD vmid to 0 */ 3891 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3892 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3893 mqd->cp_mqd_control = tmp; 3894 3895 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3896 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3897 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3898 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3899 3900 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3901 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3902 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3903 (order_base_2(prop->queue_size / 4) - 1)); 3904 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3905 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3906 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3907 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3908 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3909 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3910 mqd->cp_hqd_pq_control = tmp; 3911 3912 /* set the wb address whether it's enabled or not */ 3913 wb_gpu_addr = prop->rptr_gpu_addr; 3914 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3915 mqd->cp_hqd_pq_rptr_report_addr_hi = 3916 upper_32_bits(wb_gpu_addr) & 0xffff; 3917 3918 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3919 wb_gpu_addr = prop->wptr_gpu_addr; 3920 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3921 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3922 3923 tmp = 0; 3924 /* enable the doorbell if requested */ 3925 if (prop->use_doorbell) { 3926 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3927 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3928 DOORBELL_OFFSET, prop->doorbell_index); 3929 3930 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3931 DOORBELL_EN, 1); 3932 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3933 DOORBELL_SOURCE, 0); 3934 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3935 DOORBELL_HIT, 0); 3936 } 3937 3938 mqd->cp_hqd_pq_doorbell_control = tmp; 3939 3940 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3941 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3942 3943 /* set the vmid for the queue */ 3944 mqd->cp_hqd_vmid = 0; 3945 3946 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3947 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3948 mqd->cp_hqd_persistent_state = tmp; 3949 3950 /* set MIN_IB_AVAIL_SIZE */ 3951 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3952 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3953 mqd->cp_hqd_ib_control = tmp; 3954 3955 /* set static priority for a compute queue/ring */ 3956 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3957 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3958 3959 mqd->cp_hqd_active = prop->hqd_active; 3960 3961 return 0; 3962 } 3963 3964 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 3965 { 3966 struct amdgpu_device *adev = ring->adev; 3967 struct v11_compute_mqd *mqd = ring->mqd_ptr; 3968 int j; 3969 3970 /* inactivate the queue */ 3971 if (amdgpu_sriov_vf(adev)) 3972 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3973 3974 /* disable wptr polling */ 3975 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3976 3977 /* write the EOP addr */ 3978 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3979 mqd->cp_hqd_eop_base_addr_lo); 3980 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3981 mqd->cp_hqd_eop_base_addr_hi); 3982 3983 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3984 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3985 mqd->cp_hqd_eop_control); 3986 3987 /* enable doorbell? */ 3988 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3989 mqd->cp_hqd_pq_doorbell_control); 3990 3991 /* disable the queue if it's active */ 3992 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3993 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3994 for (j = 0; j < adev->usec_timeout; j++) { 3995 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3996 break; 3997 udelay(1); 3998 } 3999 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4000 mqd->cp_hqd_dequeue_request); 4001 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4002 mqd->cp_hqd_pq_rptr); 4003 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4004 mqd->cp_hqd_pq_wptr_lo); 4005 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4006 mqd->cp_hqd_pq_wptr_hi); 4007 } 4008 4009 /* set the pointer to the MQD */ 4010 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4011 mqd->cp_mqd_base_addr_lo); 4012 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4013 mqd->cp_mqd_base_addr_hi); 4014 4015 /* set MQD vmid to 0 */ 4016 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4017 mqd->cp_mqd_control); 4018 4019 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4020 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4021 mqd->cp_hqd_pq_base_lo); 4022 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4023 mqd->cp_hqd_pq_base_hi); 4024 4025 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4026 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4027 mqd->cp_hqd_pq_control); 4028 4029 /* set the wb address whether it's enabled or not */ 4030 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4031 mqd->cp_hqd_pq_rptr_report_addr_lo); 4032 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4033 mqd->cp_hqd_pq_rptr_report_addr_hi); 4034 4035 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4036 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4037 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4038 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4039 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4040 4041 /* enable the doorbell if requested */ 4042 if (ring->use_doorbell) { 4043 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4044 (adev->doorbell_index.kiq * 2) << 2); 4045 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4046 (adev->doorbell_index.userqueue_end * 2) << 2); 4047 } 4048 4049 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4050 mqd->cp_hqd_pq_doorbell_control); 4051 4052 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4053 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4054 mqd->cp_hqd_pq_wptr_lo); 4055 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4056 mqd->cp_hqd_pq_wptr_hi); 4057 4058 /* set the vmid for the queue */ 4059 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4060 4061 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4062 mqd->cp_hqd_persistent_state); 4063 4064 /* activate the queue */ 4065 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4066 mqd->cp_hqd_active); 4067 4068 if (ring->use_doorbell) 4069 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4070 4071 return 0; 4072 } 4073 4074 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4075 { 4076 struct amdgpu_device *adev = ring->adev; 4077 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4078 4079 gfx_v11_0_kiq_setting(ring); 4080 4081 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4082 /* reset MQD to a clean status */ 4083 if (adev->gfx.kiq[0].mqd_backup) 4084 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 4085 4086 /* reset ring buffer */ 4087 ring->wptr = 0; 4088 amdgpu_ring_clear_ring(ring); 4089 4090 mutex_lock(&adev->srbm_mutex); 4091 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4092 gfx_v11_0_kiq_init_register(ring); 4093 soc21_grbm_select(adev, 0, 0, 0, 0); 4094 mutex_unlock(&adev->srbm_mutex); 4095 } else { 4096 memset((void *)mqd, 0, sizeof(*mqd)); 4097 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4098 amdgpu_ring_clear_ring(ring); 4099 mutex_lock(&adev->srbm_mutex); 4100 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4101 amdgpu_ring_init_mqd(ring); 4102 gfx_v11_0_kiq_init_register(ring); 4103 soc21_grbm_select(adev, 0, 0, 0, 0); 4104 mutex_unlock(&adev->srbm_mutex); 4105 4106 if (adev->gfx.kiq[0].mqd_backup) 4107 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4108 } 4109 4110 return 0; 4111 } 4112 4113 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4114 { 4115 struct amdgpu_device *adev = ring->adev; 4116 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4117 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4118 4119 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4120 memset((void *)mqd, 0, sizeof(*mqd)); 4121 mutex_lock(&adev->srbm_mutex); 4122 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4123 amdgpu_ring_init_mqd(ring); 4124 soc21_grbm_select(adev, 0, 0, 0, 0); 4125 mutex_unlock(&adev->srbm_mutex); 4126 4127 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4128 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4129 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4130 /* reset MQD to a clean status */ 4131 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4132 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4133 4134 /* reset ring buffer */ 4135 ring->wptr = 0; 4136 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4137 amdgpu_ring_clear_ring(ring); 4138 } else { 4139 amdgpu_ring_clear_ring(ring); 4140 } 4141 4142 return 0; 4143 } 4144 4145 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4146 { 4147 struct amdgpu_ring *ring; 4148 int r; 4149 4150 ring = &adev->gfx.kiq[0].ring; 4151 4152 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4153 if (unlikely(r != 0)) 4154 return r; 4155 4156 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4157 if (unlikely(r != 0)) { 4158 amdgpu_bo_unreserve(ring->mqd_obj); 4159 return r; 4160 } 4161 4162 gfx_v11_0_kiq_init_queue(ring); 4163 amdgpu_bo_kunmap(ring->mqd_obj); 4164 ring->mqd_ptr = NULL; 4165 amdgpu_bo_unreserve(ring->mqd_obj); 4166 ring->sched.ready = true; 4167 return 0; 4168 } 4169 4170 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4171 { 4172 struct amdgpu_ring *ring = NULL; 4173 int r = 0, i; 4174 4175 if (!amdgpu_async_gfx_ring) 4176 gfx_v11_0_cp_compute_enable(adev, true); 4177 4178 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4179 ring = &adev->gfx.compute_ring[i]; 4180 4181 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4182 if (unlikely(r != 0)) 4183 goto done; 4184 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4185 if (!r) { 4186 r = gfx_v11_0_kcq_init_queue(ring); 4187 amdgpu_bo_kunmap(ring->mqd_obj); 4188 ring->mqd_ptr = NULL; 4189 } 4190 amdgpu_bo_unreserve(ring->mqd_obj); 4191 if (r) 4192 goto done; 4193 } 4194 4195 r = amdgpu_gfx_enable_kcq(adev, 0); 4196 done: 4197 return r; 4198 } 4199 4200 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4201 { 4202 int r, i; 4203 struct amdgpu_ring *ring; 4204 4205 if (!(adev->flags & AMD_IS_APU)) 4206 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4207 4208 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4209 /* legacy firmware loading */ 4210 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4211 if (r) 4212 return r; 4213 4214 if (adev->gfx.rs64_enable) 4215 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4216 else 4217 r = gfx_v11_0_cp_compute_load_microcode(adev); 4218 if (r) 4219 return r; 4220 } 4221 4222 gfx_v11_0_cp_set_doorbell_range(adev); 4223 4224 if (amdgpu_async_gfx_ring) { 4225 gfx_v11_0_cp_compute_enable(adev, true); 4226 gfx_v11_0_cp_gfx_enable(adev, true); 4227 } 4228 4229 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4230 r = amdgpu_mes_kiq_hw_init(adev); 4231 else 4232 r = gfx_v11_0_kiq_resume(adev); 4233 if (r) 4234 return r; 4235 4236 r = gfx_v11_0_kcq_resume(adev); 4237 if (r) 4238 return r; 4239 4240 if (!amdgpu_async_gfx_ring) { 4241 r = gfx_v11_0_cp_gfx_resume(adev); 4242 if (r) 4243 return r; 4244 } else { 4245 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4246 if (r) 4247 return r; 4248 } 4249 4250 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4251 ring = &adev->gfx.gfx_ring[i]; 4252 r = amdgpu_ring_test_helper(ring); 4253 if (r) 4254 return r; 4255 } 4256 4257 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4258 ring = &adev->gfx.compute_ring[i]; 4259 r = amdgpu_ring_test_helper(ring); 4260 if (r) 4261 return r; 4262 } 4263 4264 return 0; 4265 } 4266 4267 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4268 { 4269 gfx_v11_0_cp_gfx_enable(adev, enable); 4270 gfx_v11_0_cp_compute_enable(adev, enable); 4271 } 4272 4273 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4274 { 4275 int r; 4276 bool value; 4277 4278 r = adev->gfxhub.funcs->gart_enable(adev); 4279 if (r) 4280 return r; 4281 4282 adev->hdp.funcs->flush_hdp(adev, NULL); 4283 4284 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4285 false : true; 4286 4287 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4288 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 4289 4290 return 0; 4291 } 4292 4293 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4294 { 4295 u32 tmp; 4296 4297 /* select RS64 */ 4298 if (adev->gfx.rs64_enable) { 4299 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4300 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4301 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4302 4303 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4304 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4305 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4306 } 4307 4308 if (amdgpu_emu_mode == 1) 4309 msleep(100); 4310 } 4311 4312 static int get_gb_addr_config(struct amdgpu_device * adev) 4313 { 4314 u32 gb_addr_config; 4315 4316 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4317 if (gb_addr_config == 0) 4318 return -EINVAL; 4319 4320 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4321 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4322 4323 adev->gfx.config.gb_addr_config = gb_addr_config; 4324 4325 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4326 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4327 GB_ADDR_CONFIG, NUM_PIPES); 4328 4329 adev->gfx.config.max_tile_pipes = 4330 adev->gfx.config.gb_addr_config_fields.num_pipes; 4331 4332 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4333 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4334 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4335 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4336 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4337 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4338 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4339 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4340 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4341 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4342 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4343 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4344 4345 return 0; 4346 } 4347 4348 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4349 { 4350 uint32_t data; 4351 4352 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4353 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4354 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4355 4356 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4357 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4358 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4359 } 4360 4361 static int gfx_v11_0_hw_init(void *handle) 4362 { 4363 int r; 4364 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4365 4366 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4367 if (adev->gfx.imu.funcs) { 4368 /* RLC autoload sequence 1: Program rlc ram */ 4369 if (adev->gfx.imu.funcs->program_rlc_ram) 4370 adev->gfx.imu.funcs->program_rlc_ram(adev); 4371 } 4372 /* rlc autoload firmware */ 4373 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4374 if (r) 4375 return r; 4376 } else { 4377 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4378 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4379 if (adev->gfx.imu.funcs->load_microcode) 4380 adev->gfx.imu.funcs->load_microcode(adev); 4381 if (adev->gfx.imu.funcs->setup_imu) 4382 adev->gfx.imu.funcs->setup_imu(adev); 4383 if (adev->gfx.imu.funcs->start_imu) 4384 adev->gfx.imu.funcs->start_imu(adev); 4385 } 4386 4387 /* disable gpa mode in backdoor loading */ 4388 gfx_v11_0_disable_gpa_mode(adev); 4389 } 4390 } 4391 4392 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4393 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4394 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4395 if (r) { 4396 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4397 return r; 4398 } 4399 } 4400 4401 adev->gfx.is_poweron = true; 4402 4403 if(get_gb_addr_config(adev)) 4404 DRM_WARN("Invalid gb_addr_config !\n"); 4405 4406 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4407 adev->gfx.rs64_enable) 4408 gfx_v11_0_config_gfx_rs64(adev); 4409 4410 r = gfx_v11_0_gfxhub_enable(adev); 4411 if (r) 4412 return r; 4413 4414 if (!amdgpu_emu_mode) 4415 gfx_v11_0_init_golden_registers(adev); 4416 4417 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4418 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4419 /** 4420 * For gfx 11, rlc firmware loading relies on smu firmware is 4421 * loaded firstly, so in direct type, it has to load smc ucode 4422 * here before rlc. 4423 */ 4424 if (!(adev->flags & AMD_IS_APU)) { 4425 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4426 if (r) 4427 return r; 4428 } 4429 } 4430 4431 gfx_v11_0_constants_init(adev); 4432 4433 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4434 gfx_v11_0_select_cp_fw_arch(adev); 4435 4436 if (adev->nbio.funcs->gc_doorbell_init) 4437 adev->nbio.funcs->gc_doorbell_init(adev); 4438 4439 r = gfx_v11_0_rlc_resume(adev); 4440 if (r) 4441 return r; 4442 4443 /* 4444 * init golden registers and rlc resume may override some registers, 4445 * reconfig them here 4446 */ 4447 gfx_v11_0_tcp_harvest(adev); 4448 4449 r = gfx_v11_0_cp_resume(adev); 4450 if (r) 4451 return r; 4452 4453 return r; 4454 } 4455 4456 #ifndef BRING_UP_DEBUG 4457 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev) 4458 { 4459 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 4460 struct amdgpu_ring *kiq_ring = &kiq->ring; 4461 int i, r = 0; 4462 4463 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4464 return -EINVAL; 4465 4466 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 4467 adev->gfx.num_gfx_rings)) 4468 return -ENOMEM; 4469 4470 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4471 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 4472 PREEMPT_QUEUES, 0, 0); 4473 4474 if (adev->gfx.kiq[0].ring.sched.ready) 4475 r = amdgpu_ring_test_helper(kiq_ring); 4476 4477 return r; 4478 } 4479 #endif 4480 4481 static int gfx_v11_0_hw_fini(void *handle) 4482 { 4483 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4484 int r; 4485 4486 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 4487 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4488 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4489 4490 if (!adev->no_hw_access) { 4491 #ifndef BRING_UP_DEBUG 4492 if (amdgpu_async_gfx_ring) { 4493 r = gfx_v11_0_kiq_disable_kgq(adev); 4494 if (r) 4495 DRM_ERROR("KGQ disable failed\n"); 4496 } 4497 #endif 4498 if (amdgpu_gfx_disable_kcq(adev, 0)) 4499 DRM_ERROR("KCQ disable failed\n"); 4500 4501 amdgpu_mes_kiq_hw_fini(adev); 4502 } 4503 4504 if (amdgpu_sriov_vf(adev)) 4505 /* Remove the steps disabling CPG and clearing KIQ position, 4506 * so that CP could perform IDLE-SAVE during switch. Those 4507 * steps are necessary to avoid a DMAR error in gfx9 but it is 4508 * not reproduced on gfx11. 4509 */ 4510 return 0; 4511 4512 gfx_v11_0_cp_enable(adev, false); 4513 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4514 4515 adev->gfxhub.funcs->gart_disable(adev); 4516 4517 adev->gfx.is_poweron = false; 4518 4519 return 0; 4520 } 4521 4522 static int gfx_v11_0_suspend(void *handle) 4523 { 4524 return gfx_v11_0_hw_fini(handle); 4525 } 4526 4527 static int gfx_v11_0_resume(void *handle) 4528 { 4529 return gfx_v11_0_hw_init(handle); 4530 } 4531 4532 static bool gfx_v11_0_is_idle(void *handle) 4533 { 4534 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4535 4536 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4537 GRBM_STATUS, GUI_ACTIVE)) 4538 return false; 4539 else 4540 return true; 4541 } 4542 4543 static int gfx_v11_0_wait_for_idle(void *handle) 4544 { 4545 unsigned i; 4546 u32 tmp; 4547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4548 4549 for (i = 0; i < adev->usec_timeout; i++) { 4550 /* read MC_STATUS */ 4551 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4552 GRBM_STATUS__GUI_ACTIVE_MASK; 4553 4554 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4555 return 0; 4556 udelay(1); 4557 } 4558 return -ETIMEDOUT; 4559 } 4560 4561 static int gfx_v11_0_soft_reset(void *handle) 4562 { 4563 u32 grbm_soft_reset = 0; 4564 u32 tmp; 4565 int i, j, k; 4566 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4567 4568 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4569 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4570 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4571 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4572 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4573 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4574 4575 gfx_v11_0_set_safe_mode(adev, 0); 4576 4577 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4578 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4579 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4580 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4581 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4582 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4583 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4584 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4585 4586 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4587 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4588 } 4589 } 4590 } 4591 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4592 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4593 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4594 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4595 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4596 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4597 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4598 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4599 4600 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4601 } 4602 } 4603 } 4604 4605 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4606 4607 // Read CP_VMID_RESET register three times. 4608 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4609 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4610 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4611 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4612 4613 for (i = 0; i < adev->usec_timeout; i++) { 4614 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4615 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4616 break; 4617 udelay(1); 4618 } 4619 if (i >= adev->usec_timeout) { 4620 printk("Failed to wait all pipes clean\n"); 4621 return -EINVAL; 4622 } 4623 4624 /********** trigger soft reset ***********/ 4625 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4626 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4627 SOFT_RESET_CP, 1); 4628 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4629 SOFT_RESET_GFX, 1); 4630 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4631 SOFT_RESET_CPF, 1); 4632 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4633 SOFT_RESET_CPC, 1); 4634 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4635 SOFT_RESET_CPG, 1); 4636 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4637 /********** exit soft reset ***********/ 4638 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4639 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4640 SOFT_RESET_CP, 0); 4641 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4642 SOFT_RESET_GFX, 0); 4643 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4644 SOFT_RESET_CPF, 0); 4645 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4646 SOFT_RESET_CPC, 0); 4647 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4648 SOFT_RESET_CPG, 0); 4649 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4650 4651 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4652 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4653 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4654 4655 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4656 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4657 4658 for (i = 0; i < adev->usec_timeout; i++) { 4659 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4660 break; 4661 udelay(1); 4662 } 4663 if (i >= adev->usec_timeout) { 4664 printk("Failed to wait CP_VMID_RESET to 0\n"); 4665 return -EINVAL; 4666 } 4667 4668 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4669 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4670 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4671 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4672 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4673 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4674 4675 gfx_v11_0_unset_safe_mode(adev, 0); 4676 4677 return gfx_v11_0_cp_resume(adev); 4678 } 4679 4680 static bool gfx_v11_0_check_soft_reset(void *handle) 4681 { 4682 int i, r; 4683 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4684 struct amdgpu_ring *ring; 4685 long tmo = msecs_to_jiffies(1000); 4686 4687 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4688 ring = &adev->gfx.gfx_ring[i]; 4689 r = amdgpu_ring_test_ib(ring, tmo); 4690 if (r) 4691 return true; 4692 } 4693 4694 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4695 ring = &adev->gfx.compute_ring[i]; 4696 r = amdgpu_ring_test_ib(ring, tmo); 4697 if (r) 4698 return true; 4699 } 4700 4701 return false; 4702 } 4703 4704 static int gfx_v11_0_post_soft_reset(void *handle) 4705 { 4706 /** 4707 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 4708 */ 4709 return amdgpu_mes_resume((struct amdgpu_device *)handle); 4710 } 4711 4712 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4713 { 4714 uint64_t clock; 4715 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 4716 4717 amdgpu_gfx_off_ctrl(adev, false); 4718 mutex_lock(&adev->gfx.gpu_clock_mutex); 4719 if (amdgpu_sriov_vf(adev)) { 4720 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4721 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4722 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4723 if (clock_counter_hi_pre != clock_counter_hi_after) 4724 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4725 } else { 4726 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4727 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4728 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4729 if (clock_counter_hi_pre != clock_counter_hi_after) 4730 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4731 } 4732 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 4733 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4734 amdgpu_gfx_off_ctrl(adev, true); 4735 return clock; 4736 } 4737 4738 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4739 uint32_t vmid, 4740 uint32_t gds_base, uint32_t gds_size, 4741 uint32_t gws_base, uint32_t gws_size, 4742 uint32_t oa_base, uint32_t oa_size) 4743 { 4744 struct amdgpu_device *adev = ring->adev; 4745 4746 /* GDS Base */ 4747 gfx_v11_0_write_data_to_reg(ring, 0, false, 4748 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4749 gds_base); 4750 4751 /* GDS Size */ 4752 gfx_v11_0_write_data_to_reg(ring, 0, false, 4753 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4754 gds_size); 4755 4756 /* GWS */ 4757 gfx_v11_0_write_data_to_reg(ring, 0, false, 4758 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4759 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4760 4761 /* OA */ 4762 gfx_v11_0_write_data_to_reg(ring, 0, false, 4763 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4764 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4765 } 4766 4767 static int gfx_v11_0_early_init(void *handle) 4768 { 4769 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4770 4771 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 4772 4773 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4774 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4775 AMDGPU_MAX_COMPUTE_RINGS); 4776 4777 gfx_v11_0_set_kiq_pm4_funcs(adev); 4778 gfx_v11_0_set_ring_funcs(adev); 4779 gfx_v11_0_set_irq_funcs(adev); 4780 gfx_v11_0_set_gds_init(adev); 4781 gfx_v11_0_set_rlc_funcs(adev); 4782 gfx_v11_0_set_mqd_funcs(adev); 4783 gfx_v11_0_set_imu_funcs(adev); 4784 4785 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4786 4787 return gfx_v11_0_init_microcode(adev); 4788 } 4789 4790 static int gfx_v11_0_ras_late_init(void *handle) 4791 { 4792 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4793 struct ras_common_if *gfx_common_if; 4794 int ret; 4795 4796 gfx_common_if = kzalloc(sizeof(struct ras_common_if), GFP_KERNEL); 4797 if (!gfx_common_if) 4798 return -ENOMEM; 4799 4800 gfx_common_if->block = AMDGPU_RAS_BLOCK__GFX; 4801 4802 ret = amdgpu_ras_feature_enable(adev, gfx_common_if, true); 4803 if (ret) 4804 dev_warn(adev->dev, "Failed to enable gfx11 ras feature\n"); 4805 4806 kfree(gfx_common_if); 4807 return 0; 4808 } 4809 4810 static int gfx_v11_0_late_init(void *handle) 4811 { 4812 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4813 int r; 4814 4815 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4816 if (r) 4817 return r; 4818 4819 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4820 if (r) 4821 return r; 4822 4823 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) { 4824 r = gfx_v11_0_ras_late_init(handle); 4825 if (r) 4826 return r; 4827 } 4828 4829 return 0; 4830 } 4831 4832 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4833 { 4834 uint32_t rlc_cntl; 4835 4836 /* if RLC is not enabled, do nothing */ 4837 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4838 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4839 } 4840 4841 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 4842 { 4843 uint32_t data; 4844 unsigned i; 4845 4846 data = RLC_SAFE_MODE__CMD_MASK; 4847 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4848 4849 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4850 4851 /* wait for RLC_SAFE_MODE */ 4852 for (i = 0; i < adev->usec_timeout; i++) { 4853 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4854 RLC_SAFE_MODE, CMD)) 4855 break; 4856 udelay(1); 4857 } 4858 } 4859 4860 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 4861 { 4862 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4863 } 4864 4865 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 4866 bool enable) 4867 { 4868 uint32_t def, data; 4869 4870 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4871 return; 4872 4873 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4874 4875 if (enable) 4876 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4877 else 4878 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4879 4880 if (def != data) 4881 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4882 } 4883 4884 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 4885 bool enable) 4886 { 4887 uint32_t def, data; 4888 4889 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4890 return; 4891 4892 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4893 4894 if (enable) 4895 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4896 else 4897 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4898 4899 if (def != data) 4900 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4901 } 4902 4903 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 4904 bool enable) 4905 { 4906 uint32_t def, data; 4907 4908 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4909 return; 4910 4911 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4912 4913 if (enable) 4914 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4915 else 4916 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4917 4918 if (def != data) 4919 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4920 } 4921 4922 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4923 bool enable) 4924 { 4925 uint32_t data, def; 4926 4927 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4928 return; 4929 4930 /* It is disabled by HW by default */ 4931 if (enable) { 4932 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4933 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4934 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4935 4936 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4937 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4938 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4939 4940 if (def != data) 4941 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4942 } 4943 } else { 4944 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4945 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4946 4947 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4948 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4949 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4950 4951 if (def != data) 4952 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4953 } 4954 } 4955 } 4956 4957 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4958 bool enable) 4959 { 4960 uint32_t def, data; 4961 4962 if (!(adev->cg_flags & 4963 (AMD_CG_SUPPORT_GFX_CGCG | 4964 AMD_CG_SUPPORT_GFX_CGLS | 4965 AMD_CG_SUPPORT_GFX_3D_CGCG | 4966 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4967 return; 4968 4969 if (enable) { 4970 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4971 4972 /* unset CGCG override */ 4973 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4974 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4975 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4976 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4977 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4978 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4979 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4980 4981 /* update CGCG override bits */ 4982 if (def != data) 4983 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4984 4985 /* enable cgcg FSM(0x0000363F) */ 4986 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4987 4988 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4989 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4990 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4991 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4992 } 4993 4994 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4995 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4996 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4997 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4998 } 4999 5000 if (def != data) 5001 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5002 5003 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5004 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5005 5006 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5007 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5008 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5009 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5010 } 5011 5012 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5013 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5014 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5015 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5016 } 5017 5018 if (def != data) 5019 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5020 5021 /* set IDLE_POLL_COUNT(0x00900100) */ 5022 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5023 5024 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5025 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5026 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5027 5028 if (def != data) 5029 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5030 5031 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5032 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5033 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5034 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5035 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5036 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5037 5038 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5039 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5040 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5041 5042 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5043 if (adev->sdma.num_instances > 1) { 5044 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5045 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5046 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5047 } 5048 } else { 5049 /* Program RLC_CGCG_CGLS_CTRL */ 5050 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5051 5052 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5053 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5054 5055 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5056 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5057 5058 if (def != data) 5059 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5060 5061 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5062 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5063 5064 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5065 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5066 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5067 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5068 5069 if (def != data) 5070 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5071 5072 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5073 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5074 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5075 5076 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5077 if (adev->sdma.num_instances > 1) { 5078 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5079 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5080 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5081 } 5082 } 5083 } 5084 5085 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5086 bool enable) 5087 { 5088 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5089 5090 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5091 5092 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5093 5094 gfx_v11_0_update_repeater_fgcg(adev, enable); 5095 5096 gfx_v11_0_update_sram_fgcg(adev, enable); 5097 5098 gfx_v11_0_update_perf_clk(adev, enable); 5099 5100 if (adev->cg_flags & 5101 (AMD_CG_SUPPORT_GFX_MGCG | 5102 AMD_CG_SUPPORT_GFX_CGLS | 5103 AMD_CG_SUPPORT_GFX_CGCG | 5104 AMD_CG_SUPPORT_GFX_3D_CGCG | 5105 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5106 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5107 5108 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5109 5110 return 0; 5111 } 5112 5113 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 5114 { 5115 u32 reg, data; 5116 5117 amdgpu_gfx_off_ctrl(adev, false); 5118 5119 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5120 if (amdgpu_sriov_is_pp_one_vf(adev)) 5121 data = RREG32_NO_KIQ(reg); 5122 else 5123 data = RREG32(reg); 5124 5125 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5126 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5127 5128 if (amdgpu_sriov_is_pp_one_vf(adev)) 5129 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5130 else 5131 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5132 5133 amdgpu_gfx_off_ctrl(adev, true); 5134 } 5135 5136 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5137 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5138 .set_safe_mode = gfx_v11_0_set_safe_mode, 5139 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5140 .init = gfx_v11_0_rlc_init, 5141 .get_csb_size = gfx_v11_0_get_csb_size, 5142 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5143 .resume = gfx_v11_0_rlc_resume, 5144 .stop = gfx_v11_0_rlc_stop, 5145 .reset = gfx_v11_0_rlc_reset, 5146 .start = gfx_v11_0_rlc_start, 5147 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5148 }; 5149 5150 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5151 { 5152 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5153 5154 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5155 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5156 else 5157 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5158 5159 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5160 5161 // Program RLC_PG_DELAY3 for CGPG hysteresis 5162 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5163 switch (adev->ip_versions[GC_HWIP][0]) { 5164 case IP_VERSION(11, 0, 1): 5165 case IP_VERSION(11, 0, 4): 5166 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5167 break; 5168 default: 5169 break; 5170 } 5171 } 5172 } 5173 5174 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5175 { 5176 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5177 5178 gfx_v11_cntl_power_gating(adev, enable); 5179 5180 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5181 } 5182 5183 static int gfx_v11_0_set_powergating_state(void *handle, 5184 enum amd_powergating_state state) 5185 { 5186 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5187 bool enable = (state == AMD_PG_STATE_GATE); 5188 5189 if (amdgpu_sriov_vf(adev)) 5190 return 0; 5191 5192 switch (adev->ip_versions[GC_HWIP][0]) { 5193 case IP_VERSION(11, 0, 0): 5194 case IP_VERSION(11, 0, 2): 5195 case IP_VERSION(11, 0, 3): 5196 amdgpu_gfx_off_ctrl(adev, enable); 5197 break; 5198 case IP_VERSION(11, 0, 1): 5199 case IP_VERSION(11, 0, 4): 5200 gfx_v11_cntl_pg(adev, enable); 5201 amdgpu_gfx_off_ctrl(adev, enable); 5202 break; 5203 default: 5204 break; 5205 } 5206 5207 return 0; 5208 } 5209 5210 static int gfx_v11_0_set_clockgating_state(void *handle, 5211 enum amd_clockgating_state state) 5212 { 5213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5214 5215 if (amdgpu_sriov_vf(adev)) 5216 return 0; 5217 5218 switch (adev->ip_versions[GC_HWIP][0]) { 5219 case IP_VERSION(11, 0, 0): 5220 case IP_VERSION(11, 0, 1): 5221 case IP_VERSION(11, 0, 2): 5222 case IP_VERSION(11, 0, 3): 5223 case IP_VERSION(11, 0, 4): 5224 gfx_v11_0_update_gfx_clock_gating(adev, 5225 state == AMD_CG_STATE_GATE); 5226 break; 5227 default: 5228 break; 5229 } 5230 5231 return 0; 5232 } 5233 5234 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5235 { 5236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5237 int data; 5238 5239 /* AMD_CG_SUPPORT_GFX_MGCG */ 5240 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5241 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5242 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5243 5244 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5245 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5246 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5247 5248 /* AMD_CG_SUPPORT_GFX_FGCG */ 5249 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5250 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5251 5252 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5253 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5254 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5255 5256 /* AMD_CG_SUPPORT_GFX_CGCG */ 5257 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5258 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5259 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5260 5261 /* AMD_CG_SUPPORT_GFX_CGLS */ 5262 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5263 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5264 5265 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5266 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5267 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5268 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5269 5270 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5271 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5272 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5273 } 5274 5275 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5276 { 5277 /* gfx11 is 32bit rptr*/ 5278 return *(uint32_t *)ring->rptr_cpu_addr; 5279 } 5280 5281 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5282 { 5283 struct amdgpu_device *adev = ring->adev; 5284 u64 wptr; 5285 5286 /* XXX check if swapping is necessary on BE */ 5287 if (ring->use_doorbell) { 5288 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5289 } else { 5290 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5291 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5292 } 5293 5294 return wptr; 5295 } 5296 5297 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5298 { 5299 struct amdgpu_device *adev = ring->adev; 5300 uint32_t *wptr_saved; 5301 uint32_t *is_queue_unmap; 5302 uint64_t aggregated_db_index; 5303 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 5304 uint64_t wptr_tmp; 5305 5306 if (ring->is_mes_queue) { 5307 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5308 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5309 sizeof(uint32_t)); 5310 aggregated_db_index = 5311 amdgpu_mes_get_aggregated_doorbell_index(adev, 5312 ring->hw_prio); 5313 5314 wptr_tmp = ring->wptr & ring->buf_mask; 5315 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5316 *wptr_saved = wptr_tmp; 5317 /* assume doorbell always being used by mes mapped queue */ 5318 if (*is_queue_unmap) { 5319 WDOORBELL64(aggregated_db_index, wptr_tmp); 5320 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5321 } else { 5322 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5323 5324 if (*is_queue_unmap) 5325 WDOORBELL64(aggregated_db_index, wptr_tmp); 5326 } 5327 } else { 5328 if (ring->use_doorbell) { 5329 /* XXX check if swapping is necessary on BE */ 5330 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5331 ring->wptr); 5332 WDOORBELL64(ring->doorbell_index, ring->wptr); 5333 } else { 5334 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5335 lower_32_bits(ring->wptr)); 5336 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5337 upper_32_bits(ring->wptr)); 5338 } 5339 } 5340 } 5341 5342 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5343 { 5344 /* gfx11 hardware is 32bit rptr */ 5345 return *(uint32_t *)ring->rptr_cpu_addr; 5346 } 5347 5348 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5349 { 5350 u64 wptr; 5351 5352 /* XXX check if swapping is necessary on BE */ 5353 if (ring->use_doorbell) 5354 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5355 else 5356 BUG(); 5357 return wptr; 5358 } 5359 5360 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5361 { 5362 struct amdgpu_device *adev = ring->adev; 5363 uint32_t *wptr_saved; 5364 uint32_t *is_queue_unmap; 5365 uint64_t aggregated_db_index; 5366 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 5367 uint64_t wptr_tmp; 5368 5369 if (ring->is_mes_queue) { 5370 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5371 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5372 sizeof(uint32_t)); 5373 aggregated_db_index = 5374 amdgpu_mes_get_aggregated_doorbell_index(adev, 5375 ring->hw_prio); 5376 5377 wptr_tmp = ring->wptr & ring->buf_mask; 5378 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5379 *wptr_saved = wptr_tmp; 5380 /* assume doorbell always used by mes mapped queue */ 5381 if (*is_queue_unmap) { 5382 WDOORBELL64(aggregated_db_index, wptr_tmp); 5383 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5384 } else { 5385 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5386 5387 if (*is_queue_unmap) 5388 WDOORBELL64(aggregated_db_index, wptr_tmp); 5389 } 5390 } else { 5391 /* XXX check if swapping is necessary on BE */ 5392 if (ring->use_doorbell) { 5393 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5394 ring->wptr); 5395 WDOORBELL64(ring->doorbell_index, ring->wptr); 5396 } else { 5397 BUG(); /* only DOORBELL method supported on gfx11 now */ 5398 } 5399 } 5400 } 5401 5402 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5403 { 5404 struct amdgpu_device *adev = ring->adev; 5405 u32 ref_and_mask, reg_mem_engine; 5406 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5407 5408 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5409 switch (ring->me) { 5410 case 1: 5411 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5412 break; 5413 case 2: 5414 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5415 break; 5416 default: 5417 return; 5418 } 5419 reg_mem_engine = 0; 5420 } else { 5421 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5422 reg_mem_engine = 1; /* pfp */ 5423 } 5424 5425 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5426 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5427 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5428 ref_and_mask, ref_and_mask, 0x20); 5429 } 5430 5431 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5432 struct amdgpu_job *job, 5433 struct amdgpu_ib *ib, 5434 uint32_t flags) 5435 { 5436 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5437 u32 header, control = 0; 5438 5439 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5440 5441 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5442 5443 control |= ib->length_dw | (vmid << 24); 5444 5445 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5446 control |= INDIRECT_BUFFER_PRE_ENB(1); 5447 5448 if (flags & AMDGPU_IB_PREEMPTED) 5449 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5450 5451 if (vmid) 5452 gfx_v11_0_ring_emit_de_meta(ring, 5453 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5454 } 5455 5456 if (ring->is_mes_queue) 5457 /* inherit vmid from mqd */ 5458 control |= 0x400000; 5459 5460 amdgpu_ring_write(ring, header); 5461 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5462 amdgpu_ring_write(ring, 5463 #ifdef __BIG_ENDIAN 5464 (2 << 0) | 5465 #endif 5466 lower_32_bits(ib->gpu_addr)); 5467 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5468 amdgpu_ring_write(ring, control); 5469 } 5470 5471 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5472 struct amdgpu_job *job, 5473 struct amdgpu_ib *ib, 5474 uint32_t flags) 5475 { 5476 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5477 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5478 5479 if (ring->is_mes_queue) 5480 /* inherit vmid from mqd */ 5481 control |= 0x40000000; 5482 5483 /* Currently, there is a high possibility to get wave ID mismatch 5484 * between ME and GDS, leading to a hw deadlock, because ME generates 5485 * different wave IDs than the GDS expects. This situation happens 5486 * randomly when at least 5 compute pipes use GDS ordered append. 5487 * The wave IDs generated by ME are also wrong after suspend/resume. 5488 * Those are probably bugs somewhere else in the kernel driver. 5489 * 5490 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5491 * GDS to 0 for this ring (me/pipe). 5492 */ 5493 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5494 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5495 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5496 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5497 } 5498 5499 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5500 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5501 amdgpu_ring_write(ring, 5502 #ifdef __BIG_ENDIAN 5503 (2 << 0) | 5504 #endif 5505 lower_32_bits(ib->gpu_addr)); 5506 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5507 amdgpu_ring_write(ring, control); 5508 } 5509 5510 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5511 u64 seq, unsigned flags) 5512 { 5513 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5514 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5515 5516 /* RELEASE_MEM - flush caches, send int */ 5517 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5518 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5519 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5520 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5521 PACKET3_RELEASE_MEM_GCR_GL2_US | 5522 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5523 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5524 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5525 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5526 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5527 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5528 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5529 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5530 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5531 5532 /* 5533 * the address should be Qword aligned if 64bit write, Dword 5534 * aligned if only send 32bit data low (discard data high) 5535 */ 5536 if (write64bit) 5537 BUG_ON(addr & 0x7); 5538 else 5539 BUG_ON(addr & 0x3); 5540 amdgpu_ring_write(ring, lower_32_bits(addr)); 5541 amdgpu_ring_write(ring, upper_32_bits(addr)); 5542 amdgpu_ring_write(ring, lower_32_bits(seq)); 5543 amdgpu_ring_write(ring, upper_32_bits(seq)); 5544 amdgpu_ring_write(ring, ring->is_mes_queue ? 5545 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5546 } 5547 5548 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5549 { 5550 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5551 uint32_t seq = ring->fence_drv.sync_seq; 5552 uint64_t addr = ring->fence_drv.gpu_addr; 5553 5554 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5555 upper_32_bits(addr), seq, 0xffffffff, 4); 5556 } 5557 5558 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5559 uint16_t pasid, uint32_t flush_type, 5560 bool all_hub, uint8_t dst_sel) 5561 { 5562 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5563 amdgpu_ring_write(ring, 5564 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5565 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5566 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5567 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5568 } 5569 5570 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5571 unsigned vmid, uint64_t pd_addr) 5572 { 5573 if (ring->is_mes_queue) 5574 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5575 else 5576 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5577 5578 /* compute doesn't have PFP */ 5579 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5580 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5581 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5582 amdgpu_ring_write(ring, 0x0); 5583 } 5584 } 5585 5586 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5587 u64 seq, unsigned int flags) 5588 { 5589 struct amdgpu_device *adev = ring->adev; 5590 5591 /* we only allocate 32bit for each seq wb address */ 5592 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5593 5594 /* write fence seq to the "addr" */ 5595 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5596 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5597 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5598 amdgpu_ring_write(ring, lower_32_bits(addr)); 5599 amdgpu_ring_write(ring, upper_32_bits(addr)); 5600 amdgpu_ring_write(ring, lower_32_bits(seq)); 5601 5602 if (flags & AMDGPU_FENCE_FLAG_INT) { 5603 /* set register to trigger INT */ 5604 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5605 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5606 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5607 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5608 amdgpu_ring_write(ring, 0); 5609 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5610 } 5611 } 5612 5613 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5614 uint32_t flags) 5615 { 5616 uint32_t dw2 = 0; 5617 5618 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5619 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5620 /* set load_global_config & load_global_uconfig */ 5621 dw2 |= 0x8001; 5622 /* set load_cs_sh_regs */ 5623 dw2 |= 0x01000000; 5624 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5625 dw2 |= 0x10002; 5626 } 5627 5628 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5629 amdgpu_ring_write(ring, dw2); 5630 amdgpu_ring_write(ring, 0); 5631 } 5632 5633 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 5634 u64 shadow_va, u64 csa_va, 5635 u64 gds_va, bool init_shadow, 5636 int vmid) 5637 { 5638 struct amdgpu_device *adev = ring->adev; 5639 5640 if (!adev->gfx.cp_gfx_shadow) 5641 return; 5642 5643 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 5644 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 5645 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 5646 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 5647 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 5648 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 5649 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 5650 amdgpu_ring_write(ring, shadow_va ? 5651 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 5652 amdgpu_ring_write(ring, init_shadow ? 5653 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 5654 } 5655 5656 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5657 { 5658 unsigned ret; 5659 5660 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5661 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5662 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5663 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5664 ret = ring->wptr & ring->buf_mask; 5665 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5666 5667 return ret; 5668 } 5669 5670 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5671 { 5672 unsigned cur; 5673 BUG_ON(offset > ring->buf_mask); 5674 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5675 5676 cur = (ring->wptr - 1) & ring->buf_mask; 5677 if (likely(cur > offset)) 5678 ring->ring[offset] = cur - offset; 5679 else 5680 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5681 } 5682 5683 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5684 { 5685 int i, r = 0; 5686 struct amdgpu_device *adev = ring->adev; 5687 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 5688 struct amdgpu_ring *kiq_ring = &kiq->ring; 5689 unsigned long flags; 5690 5691 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5692 return -EINVAL; 5693 5694 spin_lock_irqsave(&kiq->ring_lock, flags); 5695 5696 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5697 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5698 return -ENOMEM; 5699 } 5700 5701 /* assert preemption condition */ 5702 amdgpu_ring_set_preempt_cond_exec(ring, false); 5703 5704 /* assert IB preemption, emit the trailing fence */ 5705 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5706 ring->trail_fence_gpu_addr, 5707 ++ring->trail_seq); 5708 amdgpu_ring_commit(kiq_ring); 5709 5710 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5711 5712 /* poll the trailing fence */ 5713 for (i = 0; i < adev->usec_timeout; i++) { 5714 if (ring->trail_seq == 5715 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5716 break; 5717 udelay(1); 5718 } 5719 5720 if (i >= adev->usec_timeout) { 5721 r = -EINVAL; 5722 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5723 } 5724 5725 /* deassert preemption condition */ 5726 amdgpu_ring_set_preempt_cond_exec(ring, true); 5727 return r; 5728 } 5729 5730 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5731 { 5732 struct amdgpu_device *adev = ring->adev; 5733 struct v10_de_ib_state de_payload = {0}; 5734 uint64_t offset, gds_addr, de_payload_gpu_addr; 5735 void *de_payload_cpu_addr; 5736 int cnt; 5737 5738 if (ring->is_mes_queue) { 5739 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5740 gfx[0].gfx_meta_data) + 5741 offsetof(struct v10_gfx_meta_data, de_payload); 5742 de_payload_gpu_addr = 5743 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5744 de_payload_cpu_addr = 5745 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5746 5747 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5748 gfx[0].gds_backup) + 5749 offsetof(struct v10_gfx_meta_data, de_payload); 5750 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5751 } else { 5752 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5753 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5754 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5755 5756 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5757 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5758 PAGE_SIZE); 5759 } 5760 5761 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5762 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5763 5764 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5765 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5766 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5767 WRITE_DATA_DST_SEL(8) | 5768 WR_CONFIRM) | 5769 WRITE_DATA_CACHE_POLICY(0)); 5770 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5771 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5772 5773 if (resume) 5774 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5775 sizeof(de_payload) >> 2); 5776 else 5777 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5778 sizeof(de_payload) >> 2); 5779 } 5780 5781 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5782 bool secure) 5783 { 5784 uint32_t v = secure ? FRAME_TMZ : 0; 5785 5786 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5787 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5788 } 5789 5790 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5791 uint32_t reg_val_offs) 5792 { 5793 struct amdgpu_device *adev = ring->adev; 5794 5795 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5796 amdgpu_ring_write(ring, 0 | /* src: register*/ 5797 (5 << 8) | /* dst: memory */ 5798 (1 << 20)); /* write confirm */ 5799 amdgpu_ring_write(ring, reg); 5800 amdgpu_ring_write(ring, 0); 5801 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5802 reg_val_offs * 4)); 5803 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5804 reg_val_offs * 4)); 5805 } 5806 5807 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5808 uint32_t val) 5809 { 5810 uint32_t cmd = 0; 5811 5812 switch (ring->funcs->type) { 5813 case AMDGPU_RING_TYPE_GFX: 5814 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5815 break; 5816 case AMDGPU_RING_TYPE_KIQ: 5817 cmd = (1 << 16); /* no inc addr */ 5818 break; 5819 default: 5820 cmd = WR_CONFIRM; 5821 break; 5822 } 5823 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5824 amdgpu_ring_write(ring, cmd); 5825 amdgpu_ring_write(ring, reg); 5826 amdgpu_ring_write(ring, 0); 5827 amdgpu_ring_write(ring, val); 5828 } 5829 5830 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5831 uint32_t val, uint32_t mask) 5832 { 5833 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5834 } 5835 5836 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5837 uint32_t reg0, uint32_t reg1, 5838 uint32_t ref, uint32_t mask) 5839 { 5840 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5841 5842 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5843 ref, mask, 0x20); 5844 } 5845 5846 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5847 unsigned vmid) 5848 { 5849 struct amdgpu_device *adev = ring->adev; 5850 uint32_t value = 0; 5851 5852 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5853 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5854 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5855 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5856 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5857 } 5858 5859 static void 5860 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5861 uint32_t me, uint32_t pipe, 5862 enum amdgpu_interrupt_state state) 5863 { 5864 uint32_t cp_int_cntl, cp_int_cntl_reg; 5865 5866 if (!me) { 5867 switch (pipe) { 5868 case 0: 5869 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5870 break; 5871 case 1: 5872 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5873 break; 5874 default: 5875 DRM_DEBUG("invalid pipe %d\n", pipe); 5876 return; 5877 } 5878 } else { 5879 DRM_DEBUG("invalid me %d\n", me); 5880 return; 5881 } 5882 5883 switch (state) { 5884 case AMDGPU_IRQ_STATE_DISABLE: 5885 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5886 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5887 TIME_STAMP_INT_ENABLE, 0); 5888 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5889 GENERIC0_INT_ENABLE, 0); 5890 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5891 break; 5892 case AMDGPU_IRQ_STATE_ENABLE: 5893 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5894 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5895 TIME_STAMP_INT_ENABLE, 1); 5896 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5897 GENERIC0_INT_ENABLE, 1); 5898 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5899 break; 5900 default: 5901 break; 5902 } 5903 } 5904 5905 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5906 int me, int pipe, 5907 enum amdgpu_interrupt_state state) 5908 { 5909 u32 mec_int_cntl, mec_int_cntl_reg; 5910 5911 /* 5912 * amdgpu controls only the first MEC. That's why this function only 5913 * handles the setting of interrupts for this specific MEC. All other 5914 * pipes' interrupts are set by amdkfd. 5915 */ 5916 5917 if (me == 1) { 5918 switch (pipe) { 5919 case 0: 5920 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5921 break; 5922 case 1: 5923 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5924 break; 5925 case 2: 5926 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5927 break; 5928 case 3: 5929 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5930 break; 5931 default: 5932 DRM_DEBUG("invalid pipe %d\n", pipe); 5933 return; 5934 } 5935 } else { 5936 DRM_DEBUG("invalid me %d\n", me); 5937 return; 5938 } 5939 5940 switch (state) { 5941 case AMDGPU_IRQ_STATE_DISABLE: 5942 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5943 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5944 TIME_STAMP_INT_ENABLE, 0); 5945 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5946 GENERIC0_INT_ENABLE, 0); 5947 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5948 break; 5949 case AMDGPU_IRQ_STATE_ENABLE: 5950 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5951 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5952 TIME_STAMP_INT_ENABLE, 1); 5953 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5954 GENERIC0_INT_ENABLE, 1); 5955 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5956 break; 5957 default: 5958 break; 5959 } 5960 } 5961 5962 #define CP_ME1_PIPE_INST_ADDR_INTERVAL 0x1 5963 #define SET_ECC_ME_PIPE_STATE(reg_addr, state) \ 5964 do { \ 5965 uint32_t tmp = RREG32_SOC15_IP(GC, reg_addr); \ 5966 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, state); \ 5967 WREG32_SOC15_IP(GC, reg_addr, tmp); \ 5968 } while (0) 5969 5970 static int gfx_v11_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5971 struct amdgpu_irq_src *source, 5972 unsigned type, 5973 enum amdgpu_interrupt_state state) 5974 { 5975 uint32_t ecc_irq_state = 0; 5976 uint32_t pipe0_int_cntl_addr = 0; 5977 int i = 0; 5978 5979 ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0; 5980 5981 pipe0_int_cntl_addr = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5982 5983 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, ecc_irq_state); 5984 5985 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) 5986 SET_ECC_ME_PIPE_STATE(pipe0_int_cntl_addr + i * CP_ME1_PIPE_INST_ADDR_INTERVAL, 5987 ecc_irq_state); 5988 5989 return 0; 5990 } 5991 5992 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5993 struct amdgpu_irq_src *src, 5994 unsigned type, 5995 enum amdgpu_interrupt_state state) 5996 { 5997 switch (type) { 5998 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5999 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6000 break; 6001 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6002 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6003 break; 6004 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6005 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6006 break; 6007 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6008 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6009 break; 6010 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6011 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6012 break; 6013 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6014 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6015 break; 6016 default: 6017 break; 6018 } 6019 return 0; 6020 } 6021 6022 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6023 struct amdgpu_irq_src *source, 6024 struct amdgpu_iv_entry *entry) 6025 { 6026 int i; 6027 u8 me_id, pipe_id, queue_id; 6028 struct amdgpu_ring *ring; 6029 uint32_t mes_queue_id = entry->src_data[0]; 6030 6031 DRM_DEBUG("IH: CP EOP\n"); 6032 6033 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 6034 struct amdgpu_mes_queue *queue; 6035 6036 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 6037 6038 spin_lock(&adev->mes.queue_id_lock); 6039 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 6040 if (queue) { 6041 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 6042 amdgpu_fence_process(queue->ring); 6043 } 6044 spin_unlock(&adev->mes.queue_id_lock); 6045 } else { 6046 me_id = (entry->ring_id & 0x0c) >> 2; 6047 pipe_id = (entry->ring_id & 0x03) >> 0; 6048 queue_id = (entry->ring_id & 0x70) >> 4; 6049 6050 switch (me_id) { 6051 case 0: 6052 if (pipe_id == 0) 6053 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6054 else 6055 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 6056 break; 6057 case 1: 6058 case 2: 6059 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6060 ring = &adev->gfx.compute_ring[i]; 6061 /* Per-queue interrupt is supported for MEC starting from VI. 6062 * The interrupt can only be enabled/disabled per pipe instead 6063 * of per queue. 6064 */ 6065 if ((ring->me == me_id) && 6066 (ring->pipe == pipe_id) && 6067 (ring->queue == queue_id)) 6068 amdgpu_fence_process(ring); 6069 } 6070 break; 6071 } 6072 } 6073 6074 return 0; 6075 } 6076 6077 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6078 struct amdgpu_irq_src *source, 6079 unsigned type, 6080 enum amdgpu_interrupt_state state) 6081 { 6082 switch (state) { 6083 case AMDGPU_IRQ_STATE_DISABLE: 6084 case AMDGPU_IRQ_STATE_ENABLE: 6085 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 6086 PRIV_REG_INT_ENABLE, 6087 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6088 break; 6089 default: 6090 break; 6091 } 6092 6093 return 0; 6094 } 6095 6096 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6097 struct amdgpu_irq_src *source, 6098 unsigned type, 6099 enum amdgpu_interrupt_state state) 6100 { 6101 switch (state) { 6102 case AMDGPU_IRQ_STATE_DISABLE: 6103 case AMDGPU_IRQ_STATE_ENABLE: 6104 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 6105 PRIV_INSTR_INT_ENABLE, 6106 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6107 break; 6108 default: 6109 break; 6110 } 6111 6112 return 0; 6113 } 6114 6115 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6116 struct amdgpu_iv_entry *entry) 6117 { 6118 u8 me_id, pipe_id, queue_id; 6119 struct amdgpu_ring *ring; 6120 int i; 6121 6122 me_id = (entry->ring_id & 0x0c) >> 2; 6123 pipe_id = (entry->ring_id & 0x03) >> 0; 6124 queue_id = (entry->ring_id & 0x70) >> 4; 6125 6126 switch (me_id) { 6127 case 0: 6128 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6129 ring = &adev->gfx.gfx_ring[i]; 6130 /* we only enabled 1 gfx queue per pipe for now */ 6131 if (ring->me == me_id && ring->pipe == pipe_id) 6132 drm_sched_fault(&ring->sched); 6133 } 6134 break; 6135 case 1: 6136 case 2: 6137 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6138 ring = &adev->gfx.compute_ring[i]; 6139 if (ring->me == me_id && ring->pipe == pipe_id && 6140 ring->queue == queue_id) 6141 drm_sched_fault(&ring->sched); 6142 } 6143 break; 6144 default: 6145 BUG(); 6146 break; 6147 } 6148 } 6149 6150 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6151 struct amdgpu_irq_src *source, 6152 struct amdgpu_iv_entry *entry) 6153 { 6154 DRM_ERROR("Illegal register access in command stream\n"); 6155 gfx_v11_0_handle_priv_fault(adev, entry); 6156 return 0; 6157 } 6158 6159 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6160 struct amdgpu_irq_src *source, 6161 struct amdgpu_iv_entry *entry) 6162 { 6163 DRM_ERROR("Illegal instruction in command stream\n"); 6164 gfx_v11_0_handle_priv_fault(adev, entry); 6165 return 0; 6166 } 6167 6168 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6169 struct amdgpu_irq_src *source, 6170 struct amdgpu_iv_entry *entry) 6171 { 6172 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6173 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6174 6175 return 0; 6176 } 6177 6178 #if 0 6179 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6180 struct amdgpu_irq_src *src, 6181 unsigned int type, 6182 enum amdgpu_interrupt_state state) 6183 { 6184 uint32_t tmp, target; 6185 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6186 6187 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6188 target += ring->pipe; 6189 6190 switch (type) { 6191 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6192 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6193 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6194 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6195 GENERIC2_INT_ENABLE, 0); 6196 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6197 6198 tmp = RREG32_SOC15_IP(GC, target); 6199 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6200 GENERIC2_INT_ENABLE, 0); 6201 WREG32_SOC15_IP(GC, target, tmp); 6202 } else { 6203 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6204 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6205 GENERIC2_INT_ENABLE, 1); 6206 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6207 6208 tmp = RREG32_SOC15_IP(GC, target); 6209 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6210 GENERIC2_INT_ENABLE, 1); 6211 WREG32_SOC15_IP(GC, target, tmp); 6212 } 6213 break; 6214 default: 6215 BUG(); /* kiq only support GENERIC2_INT now */ 6216 break; 6217 } 6218 return 0; 6219 } 6220 #endif 6221 6222 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6223 { 6224 const unsigned int gcr_cntl = 6225 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6226 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6227 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6228 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6229 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6230 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6231 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6232 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6233 6234 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6235 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6236 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6237 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6238 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6239 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6240 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6241 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6242 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6243 } 6244 6245 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6246 .name = "gfx_v11_0", 6247 .early_init = gfx_v11_0_early_init, 6248 .late_init = gfx_v11_0_late_init, 6249 .sw_init = gfx_v11_0_sw_init, 6250 .sw_fini = gfx_v11_0_sw_fini, 6251 .hw_init = gfx_v11_0_hw_init, 6252 .hw_fini = gfx_v11_0_hw_fini, 6253 .suspend = gfx_v11_0_suspend, 6254 .resume = gfx_v11_0_resume, 6255 .is_idle = gfx_v11_0_is_idle, 6256 .wait_for_idle = gfx_v11_0_wait_for_idle, 6257 .soft_reset = gfx_v11_0_soft_reset, 6258 .check_soft_reset = gfx_v11_0_check_soft_reset, 6259 .post_soft_reset = gfx_v11_0_post_soft_reset, 6260 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6261 .set_powergating_state = gfx_v11_0_set_powergating_state, 6262 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6263 }; 6264 6265 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6266 .type = AMDGPU_RING_TYPE_GFX, 6267 .align_mask = 0xff, 6268 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6269 .support_64bit_ptrs = true, 6270 .secure_submission_supported = true, 6271 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6272 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6273 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6274 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6275 5 + /* COND_EXEC */ 6276 9 + /* SET_Q_PREEMPTION_MODE */ 6277 7 + /* PIPELINE_SYNC */ 6278 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6279 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6280 2 + /* VM_FLUSH */ 6281 8 + /* FENCE for VM_FLUSH */ 6282 20 + /* GDS switch */ 6283 5 + /* COND_EXEC */ 6284 7 + /* HDP_flush */ 6285 4 + /* VGT_flush */ 6286 31 + /* DE_META */ 6287 3 + /* CNTX_CTRL */ 6288 5 + /* HDP_INVL */ 6289 8 + 8 + /* FENCE x2 */ 6290 8, /* gfx_v11_0_emit_mem_sync */ 6291 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6292 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6293 .emit_fence = gfx_v11_0_ring_emit_fence, 6294 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6295 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6296 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6297 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6298 .test_ring = gfx_v11_0_ring_test_ring, 6299 .test_ib = gfx_v11_0_ring_test_ib, 6300 .insert_nop = amdgpu_ring_insert_nop, 6301 .pad_ib = amdgpu_ring_generic_pad_ib, 6302 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6303 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 6304 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6305 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6306 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6307 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6308 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6309 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6310 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6311 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6312 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6313 }; 6314 6315 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6316 .type = AMDGPU_RING_TYPE_COMPUTE, 6317 .align_mask = 0xff, 6318 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6319 .support_64bit_ptrs = true, 6320 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6321 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6322 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6323 .emit_frame_size = 6324 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6325 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6326 5 + /* hdp invalidate */ 6327 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6328 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6329 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6330 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6331 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6332 8, /* gfx_v11_0_emit_mem_sync */ 6333 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6334 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6335 .emit_fence = gfx_v11_0_ring_emit_fence, 6336 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6337 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6338 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6339 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6340 .test_ring = gfx_v11_0_ring_test_ring, 6341 .test_ib = gfx_v11_0_ring_test_ib, 6342 .insert_nop = amdgpu_ring_insert_nop, 6343 .pad_ib = amdgpu_ring_generic_pad_ib, 6344 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6345 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6346 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6347 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6348 }; 6349 6350 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6351 .type = AMDGPU_RING_TYPE_KIQ, 6352 .align_mask = 0xff, 6353 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6354 .support_64bit_ptrs = true, 6355 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6356 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6357 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6358 .emit_frame_size = 6359 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6360 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6361 5 + /*hdp invalidate */ 6362 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6363 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6364 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6365 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6366 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6367 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6368 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6369 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6370 .test_ring = gfx_v11_0_ring_test_ring, 6371 .test_ib = gfx_v11_0_ring_test_ib, 6372 .insert_nop = amdgpu_ring_insert_nop, 6373 .pad_ib = amdgpu_ring_generic_pad_ib, 6374 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6375 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6376 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6377 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6378 }; 6379 6380 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6381 { 6382 int i; 6383 6384 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6385 6386 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6387 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6388 6389 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6390 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6391 } 6392 6393 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6394 .set = gfx_v11_0_set_eop_interrupt_state, 6395 .process = gfx_v11_0_eop_irq, 6396 }; 6397 6398 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6399 .set = gfx_v11_0_set_priv_reg_fault_state, 6400 .process = gfx_v11_0_priv_reg_irq, 6401 }; 6402 6403 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6404 .set = gfx_v11_0_set_priv_inst_fault_state, 6405 .process = gfx_v11_0_priv_inst_irq, 6406 }; 6407 6408 static const struct amdgpu_irq_src_funcs gfx_v11_0_cp_ecc_error_irq_funcs = { 6409 .set = gfx_v11_0_set_cp_ecc_error_state, 6410 .process = amdgpu_gfx_cp_ecc_error_irq, 6411 }; 6412 6413 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 6414 .process = gfx_v11_0_rlc_gc_fed_irq, 6415 }; 6416 6417 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6418 { 6419 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6420 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6421 6422 adev->gfx.priv_reg_irq.num_types = 1; 6423 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6424 6425 adev->gfx.priv_inst_irq.num_types = 1; 6426 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6427 6428 adev->gfx.cp_ecc_error_irq.num_types = 1; /* CP ECC error */ 6429 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v11_0_cp_ecc_error_irq_funcs; 6430 6431 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 6432 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 6433 6434 } 6435 6436 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6437 { 6438 if (adev->flags & AMD_IS_APU) 6439 adev->gfx.imu.mode = MISSION_MODE; 6440 else 6441 adev->gfx.imu.mode = DEBUG_MODE; 6442 6443 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6444 } 6445 6446 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6447 { 6448 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6449 } 6450 6451 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6452 { 6453 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6454 adev->gfx.config.max_sh_per_se * 6455 adev->gfx.config.max_shader_engines; 6456 6457 adev->gds.gds_size = 0x1000; 6458 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6459 adev->gds.gws_size = 64; 6460 adev->gds.oa_size = 16; 6461 } 6462 6463 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6464 { 6465 /* set gfx eng mqd */ 6466 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6467 sizeof(struct v11_gfx_mqd); 6468 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6469 gfx_v11_0_gfx_mqd_init; 6470 /* set compute eng mqd */ 6471 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6472 sizeof(struct v11_compute_mqd); 6473 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6474 gfx_v11_0_compute_mqd_init; 6475 } 6476 6477 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6478 u32 bitmap) 6479 { 6480 u32 data; 6481 6482 if (!bitmap) 6483 return; 6484 6485 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6486 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6487 6488 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6489 } 6490 6491 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6492 { 6493 u32 data, wgp_bitmask; 6494 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6495 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6496 6497 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6498 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6499 6500 wgp_bitmask = 6501 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6502 6503 return (~data) & wgp_bitmask; 6504 } 6505 6506 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6507 { 6508 u32 wgp_idx, wgp_active_bitmap; 6509 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6510 6511 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6512 cu_active_bitmap = 0; 6513 6514 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6515 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6516 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6517 if (wgp_active_bitmap & (1 << wgp_idx)) 6518 cu_active_bitmap |= cu_bitmap_per_wgp; 6519 } 6520 6521 return cu_active_bitmap; 6522 } 6523 6524 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6525 struct amdgpu_cu_info *cu_info) 6526 { 6527 int i, j, k, counter, active_cu_number = 0; 6528 u32 mask, bitmap; 6529 unsigned disable_masks[8 * 2]; 6530 6531 if (!adev || !cu_info) 6532 return -EINVAL; 6533 6534 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6535 6536 mutex_lock(&adev->grbm_idx_mutex); 6537 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6538 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6539 mask = 1; 6540 counter = 0; 6541 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 6542 if (i < 8 && j < 2) 6543 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6544 adev, disable_masks[i * 2 + j]); 6545 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6546 6547 /** 6548 * GFX11 could support more than 4 SEs, while the bitmap 6549 * in cu_info struct is 4x4 and ioctl interface struct 6550 * drm_amdgpu_info_device should keep stable. 6551 * So we use last two columns of bitmap to store cu mask for 6552 * SEs 4 to 7, the layout of the bitmap is as below: 6553 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6554 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6555 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6556 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6557 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6558 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6559 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6560 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6561 */ 6562 cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; 6563 6564 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6565 if (bitmap & mask) 6566 counter++; 6567 6568 mask <<= 1; 6569 } 6570 active_cu_number += counter; 6571 } 6572 } 6573 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6574 mutex_unlock(&adev->grbm_idx_mutex); 6575 6576 cu_info->number = active_cu_number; 6577 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6578 6579 return 0; 6580 } 6581 6582 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6583 { 6584 .type = AMD_IP_BLOCK_TYPE_GFX, 6585 .major = 11, 6586 .minor = 0, 6587 .rev = 0, 6588 .funcs = &gfx_v11_0_ip_funcs, 6589 }; 6590