1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "gfx_v11_0_3.h" 50 #include "nbio_v4_3.h" 51 #include "mes_v11_0.h" 52 53 #define GFX11_NUM_GFX_RINGS 1 54 #define GFX11_MEC_HPD_SIZE 2048 55 56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 58 59 #define regCGTT_WD_CLK_CTRL 0x5086 60 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 63 64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 85 86 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 87 { 88 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 89 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 90 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 91 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 97 }; 98 99 #define DEFAULT_SH_MEM_CONFIG \ 100 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 101 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 102 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 103 104 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 105 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 106 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 107 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 108 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 109 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 110 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 111 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 112 struct amdgpu_cu_info *cu_info); 113 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 114 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 115 u32 sh_num, u32 instance); 116 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 117 118 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 119 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 120 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 121 uint32_t val); 122 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 123 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 124 uint16_t pasid, uint32_t flush_type, 125 bool all_hub, uint8_t dst_sel); 126 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev); 127 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev); 128 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 129 bool enable); 130 131 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 132 { 133 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 134 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 135 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 136 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 137 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 138 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 139 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 140 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 141 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 142 } 143 144 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 145 struct amdgpu_ring *ring) 146 { 147 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 148 uint64_t wptr_addr = ring->wptr_gpu_addr; 149 uint32_t me = 0, eng_sel = 0; 150 151 switch (ring->funcs->type) { 152 case AMDGPU_RING_TYPE_COMPUTE: 153 me = 1; 154 eng_sel = 0; 155 break; 156 case AMDGPU_RING_TYPE_GFX: 157 me = 0; 158 eng_sel = 4; 159 break; 160 case AMDGPU_RING_TYPE_MES: 161 me = 2; 162 eng_sel = 5; 163 break; 164 default: 165 WARN_ON(1); 166 } 167 168 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 169 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 170 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 171 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 172 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 173 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 174 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 175 PACKET3_MAP_QUEUES_ME((me)) | 176 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 177 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 178 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 179 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 180 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 181 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 182 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 183 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 184 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 185 } 186 187 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 188 struct amdgpu_ring *ring, 189 enum amdgpu_unmap_queues_action action, 190 u64 gpu_addr, u64 seq) 191 { 192 struct amdgpu_device *adev = kiq_ring->adev; 193 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 194 195 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { 196 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 197 return; 198 } 199 200 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 201 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 202 PACKET3_UNMAP_QUEUES_ACTION(action) | 203 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 204 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 205 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 206 amdgpu_ring_write(kiq_ring, 207 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 208 209 if (action == PREEMPT_QUEUES_NO_UNMAP) { 210 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 211 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 212 amdgpu_ring_write(kiq_ring, seq); 213 } else { 214 amdgpu_ring_write(kiq_ring, 0); 215 amdgpu_ring_write(kiq_ring, 0); 216 amdgpu_ring_write(kiq_ring, 0); 217 } 218 } 219 220 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 221 struct amdgpu_ring *ring, 222 u64 addr, 223 u64 seq) 224 { 225 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 226 227 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 228 amdgpu_ring_write(kiq_ring, 229 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 230 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 231 PACKET3_QUERY_STATUS_COMMAND(2)); 232 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 233 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 234 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 235 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 236 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 237 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 238 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 239 } 240 241 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 242 uint16_t pasid, uint32_t flush_type, 243 bool all_hub) 244 { 245 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 246 } 247 248 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 249 .kiq_set_resources = gfx11_kiq_set_resources, 250 .kiq_map_queues = gfx11_kiq_map_queues, 251 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 252 .kiq_query_status = gfx11_kiq_query_status, 253 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 254 .set_resources_size = 8, 255 .map_queues_size = 7, 256 .unmap_queues_size = 6, 257 .query_status_size = 7, 258 .invalidate_tlbs_size = 2, 259 }; 260 261 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 262 { 263 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; 264 } 265 266 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 267 { 268 switch (adev->ip_versions[GC_HWIP][0]) { 269 case IP_VERSION(11, 0, 1): 270 case IP_VERSION(11, 0, 4): 271 soc15_program_register_sequence(adev, 272 golden_settings_gc_11_0_1, 273 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 274 break; 275 default: 276 break; 277 } 278 } 279 280 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 281 bool wc, uint32_t reg, uint32_t val) 282 { 283 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 284 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 285 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 286 amdgpu_ring_write(ring, reg); 287 amdgpu_ring_write(ring, 0); 288 amdgpu_ring_write(ring, val); 289 } 290 291 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 292 int mem_space, int opt, uint32_t addr0, 293 uint32_t addr1, uint32_t ref, uint32_t mask, 294 uint32_t inv) 295 { 296 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 297 amdgpu_ring_write(ring, 298 /* memory (1) or register (0) */ 299 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 300 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 301 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 302 WAIT_REG_MEM_ENGINE(eng_sel))); 303 304 if (mem_space) 305 BUG_ON(addr0 & 0x3); /* Dword align */ 306 amdgpu_ring_write(ring, addr0); 307 amdgpu_ring_write(ring, addr1); 308 amdgpu_ring_write(ring, ref); 309 amdgpu_ring_write(ring, mask); 310 amdgpu_ring_write(ring, inv); /* poll interval */ 311 } 312 313 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 314 { 315 struct amdgpu_device *adev = ring->adev; 316 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 317 uint32_t tmp = 0; 318 unsigned i; 319 int r; 320 321 WREG32(scratch, 0xCAFEDEAD); 322 r = amdgpu_ring_alloc(ring, 5); 323 if (r) { 324 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 325 ring->idx, r); 326 return r; 327 } 328 329 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 330 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 331 } else { 332 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 333 amdgpu_ring_write(ring, scratch - 334 PACKET3_SET_UCONFIG_REG_START); 335 amdgpu_ring_write(ring, 0xDEADBEEF); 336 } 337 amdgpu_ring_commit(ring); 338 339 for (i = 0; i < adev->usec_timeout; i++) { 340 tmp = RREG32(scratch); 341 if (tmp == 0xDEADBEEF) 342 break; 343 if (amdgpu_emu_mode == 1) 344 msleep(1); 345 else 346 udelay(1); 347 } 348 349 if (i >= adev->usec_timeout) 350 r = -ETIMEDOUT; 351 return r; 352 } 353 354 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 355 { 356 struct amdgpu_device *adev = ring->adev; 357 struct amdgpu_ib ib; 358 struct dma_fence *f = NULL; 359 unsigned index; 360 uint64_t gpu_addr; 361 volatile uint32_t *cpu_ptr; 362 long r; 363 364 /* MES KIQ fw hasn't indirect buffer support for now */ 365 if (adev->enable_mes_kiq && 366 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 367 return 0; 368 369 memset(&ib, 0, sizeof(ib)); 370 371 if (ring->is_mes_queue) { 372 uint32_t padding, offset; 373 374 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 375 padding = amdgpu_mes_ctx_get_offs(ring, 376 AMDGPU_MES_CTX_PADDING_OFFS); 377 378 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 379 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 380 381 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 382 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 383 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 384 } else { 385 r = amdgpu_device_wb_get(adev, &index); 386 if (r) 387 return r; 388 389 gpu_addr = adev->wb.gpu_addr + (index * 4); 390 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 391 cpu_ptr = &adev->wb.wb[index]; 392 393 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 394 if (r) { 395 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 396 goto err1; 397 } 398 } 399 400 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 401 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 402 ib.ptr[2] = lower_32_bits(gpu_addr); 403 ib.ptr[3] = upper_32_bits(gpu_addr); 404 ib.ptr[4] = 0xDEADBEEF; 405 ib.length_dw = 5; 406 407 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 408 if (r) 409 goto err2; 410 411 r = dma_fence_wait_timeout(f, false, timeout); 412 if (r == 0) { 413 r = -ETIMEDOUT; 414 goto err2; 415 } else if (r < 0) { 416 goto err2; 417 } 418 419 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 420 r = 0; 421 else 422 r = -EINVAL; 423 err2: 424 if (!ring->is_mes_queue) 425 amdgpu_ib_free(adev, &ib, NULL); 426 dma_fence_put(f); 427 err1: 428 if (!ring->is_mes_queue) 429 amdgpu_device_wb_free(adev, index); 430 return r; 431 } 432 433 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 434 { 435 amdgpu_ucode_release(&adev->gfx.pfp_fw); 436 amdgpu_ucode_release(&adev->gfx.me_fw); 437 amdgpu_ucode_release(&adev->gfx.rlc_fw); 438 amdgpu_ucode_release(&adev->gfx.mec_fw); 439 440 kfree(adev->gfx.rlc.register_list_format); 441 } 442 443 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 444 { 445 const struct psp_firmware_header_v1_0 *toc_hdr; 446 int err = 0; 447 char fw_name[40]; 448 449 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 450 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 451 if (err) 452 goto out; 453 454 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 455 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 456 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 457 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 458 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 459 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 460 return 0; 461 out: 462 amdgpu_ucode_release(&adev->psp.toc_fw); 463 return err; 464 } 465 466 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 467 { 468 char fw_name[40]; 469 char ucode_prefix[30]; 470 int err; 471 const struct rlc_firmware_header_v2_0 *rlc_hdr; 472 uint16_t version_major; 473 uint16_t version_minor; 474 475 DRM_DEBUG("\n"); 476 477 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 478 479 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 480 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 481 if (err) 482 goto out; 483 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 484 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 485 (union amdgpu_firmware_header *) 486 adev->gfx.pfp_fw->data, 2, 0); 487 if (adev->gfx.rs64_enable) { 488 dev_info(adev->dev, "CP RS64 enable\n"); 489 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 490 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 491 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 492 } else { 493 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 494 } 495 496 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 497 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 498 if (err) 499 goto out; 500 if (adev->gfx.rs64_enable) { 501 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 502 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 503 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 504 } else { 505 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 506 } 507 508 if (!amdgpu_sriov_vf(adev)) { 509 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 510 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 511 if (err) 512 goto out; 513 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 514 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 515 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 516 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 517 if (err) 518 goto out; 519 } 520 521 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 522 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 523 if (err) 524 goto out; 525 if (adev->gfx.rs64_enable) { 526 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 527 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 528 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 529 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 530 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 531 } else { 532 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 533 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 534 } 535 536 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 537 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 538 539 /* only one MEC for gfx 11.0.0. */ 540 adev->gfx.mec2_fw = NULL; 541 542 out: 543 if (err) { 544 amdgpu_ucode_release(&adev->gfx.pfp_fw); 545 amdgpu_ucode_release(&adev->gfx.me_fw); 546 amdgpu_ucode_release(&adev->gfx.rlc_fw); 547 amdgpu_ucode_release(&adev->gfx.mec_fw); 548 } 549 550 return err; 551 } 552 553 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 554 { 555 u32 count = 0; 556 const struct cs_section_def *sect = NULL; 557 const struct cs_extent_def *ext = NULL; 558 559 /* begin clear state */ 560 count += 2; 561 /* context control state */ 562 count += 3; 563 564 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 565 for (ext = sect->section; ext->extent != NULL; ++ext) { 566 if (sect->id == SECT_CONTEXT) 567 count += 2 + ext->reg_count; 568 else 569 return 0; 570 } 571 } 572 573 /* set PA_SC_TILE_STEERING_OVERRIDE */ 574 count += 3; 575 /* end clear state */ 576 count += 2; 577 /* clear state */ 578 count += 2; 579 580 return count; 581 } 582 583 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 584 volatile u32 *buffer) 585 { 586 u32 count = 0, i; 587 const struct cs_section_def *sect = NULL; 588 const struct cs_extent_def *ext = NULL; 589 int ctx_reg_offset; 590 591 if (adev->gfx.rlc.cs_data == NULL) 592 return; 593 if (buffer == NULL) 594 return; 595 596 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 597 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 598 599 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 600 buffer[count++] = cpu_to_le32(0x80000000); 601 buffer[count++] = cpu_to_le32(0x80000000); 602 603 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 604 for (ext = sect->section; ext->extent != NULL; ++ext) { 605 if (sect->id == SECT_CONTEXT) { 606 buffer[count++] = 607 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 608 buffer[count++] = cpu_to_le32(ext->reg_index - 609 PACKET3_SET_CONTEXT_REG_START); 610 for (i = 0; i < ext->reg_count; i++) 611 buffer[count++] = cpu_to_le32(ext->extent[i]); 612 } else { 613 return; 614 } 615 } 616 } 617 618 ctx_reg_offset = 619 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 620 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 621 buffer[count++] = cpu_to_le32(ctx_reg_offset); 622 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 623 624 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 625 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 626 627 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 628 buffer[count++] = cpu_to_le32(0); 629 } 630 631 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 632 { 633 /* clear state block */ 634 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 635 &adev->gfx.rlc.clear_state_gpu_addr, 636 (void **)&adev->gfx.rlc.cs_ptr); 637 638 /* jump table block */ 639 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 640 &adev->gfx.rlc.cp_table_gpu_addr, 641 (void **)&adev->gfx.rlc.cp_table_ptr); 642 } 643 644 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 645 { 646 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 647 648 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 649 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 650 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 651 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 652 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 653 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 654 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 655 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 656 adev->gfx.rlc.rlcg_reg_access_supported = true; 657 } 658 659 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 660 { 661 const struct cs_section_def *cs_data; 662 int r; 663 664 adev->gfx.rlc.cs_data = gfx11_cs_data; 665 666 cs_data = adev->gfx.rlc.cs_data; 667 668 if (cs_data) { 669 /* init clear state block */ 670 r = amdgpu_gfx_rlc_init_csb(adev); 671 if (r) 672 return r; 673 } 674 675 /* init spm vmid with 0xf */ 676 if (adev->gfx.rlc.funcs->update_spm_vmid) 677 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 678 679 return 0; 680 } 681 682 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 683 { 684 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 685 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 686 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 687 } 688 689 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 690 { 691 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 692 693 amdgpu_gfx_graphics_queue_acquire(adev); 694 } 695 696 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 697 { 698 int r; 699 u32 *hpd; 700 size_t mec_hpd_size; 701 702 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 703 704 /* take ownership of the relevant compute queues */ 705 amdgpu_gfx_compute_queue_acquire(adev); 706 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 707 708 if (mec_hpd_size) { 709 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 710 AMDGPU_GEM_DOMAIN_GTT, 711 &adev->gfx.mec.hpd_eop_obj, 712 &adev->gfx.mec.hpd_eop_gpu_addr, 713 (void **)&hpd); 714 if (r) { 715 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 716 gfx_v11_0_mec_fini(adev); 717 return r; 718 } 719 720 memset(hpd, 0, mec_hpd_size); 721 722 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 723 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 724 } 725 726 return 0; 727 } 728 729 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 730 { 731 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 732 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 733 (address << SQ_IND_INDEX__INDEX__SHIFT)); 734 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 735 } 736 737 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 738 uint32_t thread, uint32_t regno, 739 uint32_t num, uint32_t *out) 740 { 741 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 742 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 743 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 744 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 745 (SQ_IND_INDEX__AUTO_INCR_MASK)); 746 while (num--) 747 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 748 } 749 750 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 751 { 752 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 753 * field when performing a select_se_sh so it should be 754 * zero here */ 755 WARN_ON(simd != 0); 756 757 /* type 2 wave data */ 758 dst[(*no_fields)++] = 2; 759 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 760 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 761 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 762 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 763 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 764 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 765 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 766 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 767 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 768 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 769 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 770 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 771 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 772 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 773 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 774 } 775 776 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 777 uint32_t wave, uint32_t start, 778 uint32_t size, uint32_t *dst) 779 { 780 WARN_ON(simd != 0); 781 782 wave_read_regs( 783 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 784 dst); 785 } 786 787 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 788 uint32_t wave, uint32_t thread, 789 uint32_t start, uint32_t size, 790 uint32_t *dst) 791 { 792 wave_read_regs( 793 adev, wave, thread, 794 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 795 } 796 797 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 798 u32 me, u32 pipe, u32 q, u32 vm) 799 { 800 soc21_grbm_select(adev, me, pipe, q, vm); 801 } 802 803 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 804 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 805 .select_se_sh = &gfx_v11_0_select_se_sh, 806 .read_wave_data = &gfx_v11_0_read_wave_data, 807 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 808 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 809 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 810 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 811 }; 812 813 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 814 { 815 816 switch (adev->ip_versions[GC_HWIP][0]) { 817 case IP_VERSION(11, 0, 0): 818 case IP_VERSION(11, 0, 2): 819 adev->gfx.config.max_hw_contexts = 8; 820 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 821 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 822 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 823 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 824 break; 825 case IP_VERSION(11, 0, 3): 826 adev->gfx.ras = &gfx_v11_0_3_ras; 827 adev->gfx.config.max_hw_contexts = 8; 828 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 829 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 830 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 831 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 832 break; 833 case IP_VERSION(11, 0, 1): 834 case IP_VERSION(11, 0, 4): 835 adev->gfx.config.max_hw_contexts = 8; 836 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 837 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 838 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 839 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 840 break; 841 default: 842 BUG(); 843 break; 844 } 845 846 return 0; 847 } 848 849 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 850 int me, int pipe, int queue) 851 { 852 int r; 853 struct amdgpu_ring *ring; 854 unsigned int irq_type; 855 856 ring = &adev->gfx.gfx_ring[ring_id]; 857 858 ring->me = me; 859 ring->pipe = pipe; 860 ring->queue = queue; 861 862 ring->ring_obj = NULL; 863 ring->use_doorbell = true; 864 865 if (!ring_id) 866 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 867 else 868 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 869 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 870 871 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 872 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 873 AMDGPU_RING_PRIO_DEFAULT, NULL); 874 if (r) 875 return r; 876 return 0; 877 } 878 879 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 880 int mec, int pipe, int queue) 881 { 882 int r; 883 unsigned irq_type; 884 struct amdgpu_ring *ring; 885 unsigned int hw_prio; 886 887 ring = &adev->gfx.compute_ring[ring_id]; 888 889 /* mec0 is me1 */ 890 ring->me = mec + 1; 891 ring->pipe = pipe; 892 ring->queue = queue; 893 894 ring->ring_obj = NULL; 895 ring->use_doorbell = true; 896 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 897 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 898 + (ring_id * GFX11_MEC_HPD_SIZE); 899 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 900 901 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 902 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 903 + ring->pipe; 904 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 905 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 906 /* type-2 packets are deprecated on MEC, use type-3 instead */ 907 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 908 hw_prio, NULL); 909 if (r) 910 return r; 911 912 return 0; 913 } 914 915 static struct { 916 SOC21_FIRMWARE_ID id; 917 unsigned int offset; 918 unsigned int size; 919 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 920 921 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 922 { 923 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 924 925 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 926 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 927 rlc_autoload_info[ucode->id].id = ucode->id; 928 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 929 rlc_autoload_info[ucode->id].size = ucode->size * 4; 930 931 ucode++; 932 } 933 } 934 935 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 936 { 937 uint32_t total_size = 0; 938 SOC21_FIRMWARE_ID id; 939 940 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 941 942 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 943 total_size += rlc_autoload_info[id].size; 944 945 /* In case the offset in rlc toc ucode is aligned */ 946 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 947 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 948 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 949 950 return total_size; 951 } 952 953 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 954 { 955 int r; 956 uint32_t total_size; 957 958 total_size = gfx_v11_0_calc_toc_total_size(adev); 959 960 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 961 AMDGPU_GEM_DOMAIN_VRAM | 962 AMDGPU_GEM_DOMAIN_GTT, 963 &adev->gfx.rlc.rlc_autoload_bo, 964 &adev->gfx.rlc.rlc_autoload_gpu_addr, 965 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 966 967 if (r) { 968 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 969 return r; 970 } 971 972 return 0; 973 } 974 975 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 976 SOC21_FIRMWARE_ID id, 977 const void *fw_data, 978 uint32_t fw_size, 979 uint32_t *fw_autoload_mask) 980 { 981 uint32_t toc_offset; 982 uint32_t toc_fw_size; 983 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 984 985 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 986 return; 987 988 toc_offset = rlc_autoload_info[id].offset; 989 toc_fw_size = rlc_autoload_info[id].size; 990 991 if (fw_size == 0) 992 fw_size = toc_fw_size; 993 994 if (fw_size > toc_fw_size) 995 fw_size = toc_fw_size; 996 997 memcpy(ptr + toc_offset, fw_data, fw_size); 998 999 if (fw_size < toc_fw_size) 1000 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1001 1002 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1003 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1004 } 1005 1006 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1007 uint32_t *fw_autoload_mask) 1008 { 1009 void *data; 1010 uint32_t size; 1011 uint64_t *toc_ptr; 1012 1013 *(uint64_t *)fw_autoload_mask |= 0x1; 1014 1015 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1016 1017 data = adev->psp.toc.start_addr; 1018 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1019 1020 toc_ptr = (uint64_t *)data + size / 8 - 1; 1021 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1022 1023 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1024 data, size, fw_autoload_mask); 1025 } 1026 1027 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1028 uint32_t *fw_autoload_mask) 1029 { 1030 const __le32 *fw_data; 1031 uint32_t fw_size; 1032 const struct gfx_firmware_header_v1_0 *cp_hdr; 1033 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1034 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1035 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1036 uint16_t version_major, version_minor; 1037 1038 if (adev->gfx.rs64_enable) { 1039 /* pfp ucode */ 1040 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1041 adev->gfx.pfp_fw->data; 1042 /* instruction */ 1043 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1044 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1045 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1046 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1047 fw_data, fw_size, fw_autoload_mask); 1048 /* data */ 1049 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1050 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1051 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1052 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1053 fw_data, fw_size, fw_autoload_mask); 1054 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1055 fw_data, fw_size, fw_autoload_mask); 1056 /* me ucode */ 1057 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1058 adev->gfx.me_fw->data; 1059 /* instruction */ 1060 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1061 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1062 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1063 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1064 fw_data, fw_size, fw_autoload_mask); 1065 /* data */ 1066 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1067 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1068 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1069 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1070 fw_data, fw_size, fw_autoload_mask); 1071 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1072 fw_data, fw_size, fw_autoload_mask); 1073 /* mec ucode */ 1074 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1075 adev->gfx.mec_fw->data; 1076 /* instruction */ 1077 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1078 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1079 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1080 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1081 fw_data, fw_size, fw_autoload_mask); 1082 /* data */ 1083 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1084 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1085 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1086 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1087 fw_data, fw_size, fw_autoload_mask); 1088 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1089 fw_data, fw_size, fw_autoload_mask); 1090 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1091 fw_data, fw_size, fw_autoload_mask); 1092 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1093 fw_data, fw_size, fw_autoload_mask); 1094 } else { 1095 /* pfp ucode */ 1096 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1097 adev->gfx.pfp_fw->data; 1098 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1099 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1100 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1101 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1102 fw_data, fw_size, fw_autoload_mask); 1103 1104 /* me ucode */ 1105 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1106 adev->gfx.me_fw->data; 1107 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1108 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1109 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1110 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1111 fw_data, fw_size, fw_autoload_mask); 1112 1113 /* mec ucode */ 1114 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1115 adev->gfx.mec_fw->data; 1116 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1117 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1118 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1119 cp_hdr->jt_size * 4; 1120 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1121 fw_data, fw_size, fw_autoload_mask); 1122 } 1123 1124 /* rlc ucode */ 1125 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1126 adev->gfx.rlc_fw->data; 1127 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1128 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1129 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1130 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1131 fw_data, fw_size, fw_autoload_mask); 1132 1133 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1134 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1135 if (version_major == 2) { 1136 if (version_minor >= 2) { 1137 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1138 1139 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1140 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1141 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1142 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1143 fw_data, fw_size, fw_autoload_mask); 1144 1145 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1146 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1147 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1148 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1149 fw_data, fw_size, fw_autoload_mask); 1150 } 1151 } 1152 } 1153 1154 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1155 uint32_t *fw_autoload_mask) 1156 { 1157 const __le32 *fw_data; 1158 uint32_t fw_size; 1159 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1160 1161 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1162 adev->sdma.instance[0].fw->data; 1163 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1164 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1165 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1166 1167 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1168 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1169 1170 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1171 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1172 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1173 1174 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1175 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1176 } 1177 1178 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1179 uint32_t *fw_autoload_mask) 1180 { 1181 const __le32 *fw_data; 1182 unsigned fw_size; 1183 const struct mes_firmware_header_v1_0 *mes_hdr; 1184 int pipe, ucode_id, data_id; 1185 1186 for (pipe = 0; pipe < 2; pipe++) { 1187 if (pipe==0) { 1188 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1189 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1190 } else { 1191 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1192 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1193 } 1194 1195 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1196 adev->mes.fw[pipe]->data; 1197 1198 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1199 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1200 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1201 1202 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1203 ucode_id, fw_data, fw_size, fw_autoload_mask); 1204 1205 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1206 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1207 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1208 1209 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1210 data_id, fw_data, fw_size, fw_autoload_mask); 1211 } 1212 } 1213 1214 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1215 { 1216 uint32_t rlc_g_offset, rlc_g_size; 1217 uint64_t gpu_addr; 1218 uint32_t autoload_fw_id[2]; 1219 1220 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1221 1222 /* RLC autoload sequence 2: copy ucode */ 1223 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1224 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1225 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1226 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1227 1228 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1229 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1230 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1231 1232 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1233 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1234 1235 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1236 1237 /* RLC autoload sequence 3: load IMU fw */ 1238 if (adev->gfx.imu.funcs->load_microcode) 1239 adev->gfx.imu.funcs->load_microcode(adev); 1240 /* RLC autoload sequence 4 init IMU fw */ 1241 if (adev->gfx.imu.funcs->setup_imu) 1242 adev->gfx.imu.funcs->setup_imu(adev); 1243 if (adev->gfx.imu.funcs->start_imu) 1244 adev->gfx.imu.funcs->start_imu(adev); 1245 1246 /* RLC autoload sequence 5 disable gpa mode */ 1247 gfx_v11_0_disable_gpa_mode(adev); 1248 1249 return 0; 1250 } 1251 1252 static int gfx_v11_0_sw_init(void *handle) 1253 { 1254 int i, j, k, r, ring_id = 0; 1255 struct amdgpu_kiq *kiq; 1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1257 1258 adev->gfxhub.funcs->init(adev); 1259 1260 switch (adev->ip_versions[GC_HWIP][0]) { 1261 case IP_VERSION(11, 0, 0): 1262 case IP_VERSION(11, 0, 1): 1263 case IP_VERSION(11, 0, 2): 1264 case IP_VERSION(11, 0, 3): 1265 case IP_VERSION(11, 0, 4): 1266 adev->gfx.me.num_me = 1; 1267 adev->gfx.me.num_pipe_per_me = 1; 1268 adev->gfx.me.num_queue_per_pipe = 1; 1269 adev->gfx.mec.num_mec = 2; 1270 adev->gfx.mec.num_pipe_per_mec = 4; 1271 adev->gfx.mec.num_queue_per_pipe = 4; 1272 break; 1273 default: 1274 adev->gfx.me.num_me = 1; 1275 adev->gfx.me.num_pipe_per_me = 1; 1276 adev->gfx.me.num_queue_per_pipe = 1; 1277 adev->gfx.mec.num_mec = 1; 1278 adev->gfx.mec.num_pipe_per_mec = 4; 1279 adev->gfx.mec.num_queue_per_pipe = 8; 1280 break; 1281 } 1282 1283 /* EOP Event */ 1284 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1285 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1286 &adev->gfx.eop_irq); 1287 if (r) 1288 return r; 1289 1290 /* Privileged reg */ 1291 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1292 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1293 &adev->gfx.priv_reg_irq); 1294 if (r) 1295 return r; 1296 1297 /* Privileged inst */ 1298 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1299 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1300 &adev->gfx.priv_inst_irq); 1301 if (r) 1302 return r; 1303 1304 /* FED error */ 1305 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1306 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1307 &adev->gfx.rlc_gc_fed_irq); 1308 if (r) 1309 return r; 1310 1311 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1312 1313 if (adev->gfx.imu.funcs) { 1314 if (adev->gfx.imu.funcs->init_microcode) { 1315 r = adev->gfx.imu.funcs->init_microcode(adev); 1316 if (r) 1317 DRM_ERROR("Failed to load imu firmware!\n"); 1318 } 1319 } 1320 1321 gfx_v11_0_me_init(adev); 1322 1323 r = gfx_v11_0_rlc_init(adev); 1324 if (r) { 1325 DRM_ERROR("Failed to init rlc BOs!\n"); 1326 return r; 1327 } 1328 1329 r = gfx_v11_0_mec_init(adev); 1330 if (r) { 1331 DRM_ERROR("Failed to init MEC BOs!\n"); 1332 return r; 1333 } 1334 1335 /* set up the gfx ring */ 1336 for (i = 0; i < adev->gfx.me.num_me; i++) { 1337 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1338 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1339 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1340 continue; 1341 1342 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1343 i, k, j); 1344 if (r) 1345 return r; 1346 ring_id++; 1347 } 1348 } 1349 } 1350 1351 ring_id = 0; 1352 /* set up the compute queues - allocate horizontally across pipes */ 1353 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1354 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1355 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1356 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1357 j)) 1358 continue; 1359 1360 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1361 i, k, j); 1362 if (r) 1363 return r; 1364 1365 ring_id++; 1366 } 1367 } 1368 } 1369 1370 if (!adev->enable_mes_kiq) { 1371 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE); 1372 if (r) { 1373 DRM_ERROR("Failed to init KIQ BOs!\n"); 1374 return r; 1375 } 1376 1377 kiq = &adev->gfx.kiq; 1378 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1379 if (r) 1380 return r; 1381 } 1382 1383 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd)); 1384 if (r) 1385 return r; 1386 1387 /* allocate visible FB for rlc auto-loading fw */ 1388 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1389 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1390 if (r) 1391 return r; 1392 } 1393 1394 r = gfx_v11_0_gpu_early_init(adev); 1395 if (r) 1396 return r; 1397 1398 if (amdgpu_gfx_ras_sw_init(adev)) { 1399 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1400 return -EINVAL; 1401 } 1402 1403 return 0; 1404 } 1405 1406 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1407 { 1408 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1409 &adev->gfx.pfp.pfp_fw_gpu_addr, 1410 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1411 1412 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1413 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1414 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1415 } 1416 1417 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1418 { 1419 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1420 &adev->gfx.me.me_fw_gpu_addr, 1421 (void **)&adev->gfx.me.me_fw_ptr); 1422 1423 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1424 &adev->gfx.me.me_fw_data_gpu_addr, 1425 (void **)&adev->gfx.me.me_fw_data_ptr); 1426 } 1427 1428 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1429 { 1430 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1431 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1432 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1433 } 1434 1435 static int gfx_v11_0_sw_fini(void *handle) 1436 { 1437 int i; 1438 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1439 1440 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1441 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1442 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1443 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1444 1445 amdgpu_gfx_mqd_sw_fini(adev); 1446 1447 if (!adev->enable_mes_kiq) { 1448 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1449 amdgpu_gfx_kiq_fini(adev); 1450 } 1451 1452 gfx_v11_0_pfp_fini(adev); 1453 gfx_v11_0_me_fini(adev); 1454 gfx_v11_0_rlc_fini(adev); 1455 gfx_v11_0_mec_fini(adev); 1456 1457 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1458 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1459 1460 gfx_v11_0_free_microcode(adev); 1461 1462 return 0; 1463 } 1464 1465 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1466 u32 sh_num, u32 instance) 1467 { 1468 u32 data; 1469 1470 if (instance == 0xffffffff) 1471 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1472 INSTANCE_BROADCAST_WRITES, 1); 1473 else 1474 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1475 instance); 1476 1477 if (se_num == 0xffffffff) 1478 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1479 1); 1480 else 1481 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1482 1483 if (sh_num == 0xffffffff) 1484 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1485 1); 1486 else 1487 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1488 1489 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1490 } 1491 1492 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1493 { 1494 u32 data, mask; 1495 1496 data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1497 data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1498 1499 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1500 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1501 1502 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1503 adev->gfx.config.max_sh_per_se); 1504 1505 return (~data) & mask; 1506 } 1507 1508 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1509 { 1510 int i, j; 1511 u32 data; 1512 u32 active_rbs = 0; 1513 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1514 adev->gfx.config.max_sh_per_se; 1515 1516 mutex_lock(&adev->grbm_idx_mutex); 1517 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1518 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1519 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 1520 data = gfx_v11_0_get_rb_active_bitmap(adev); 1521 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1522 rb_bitmap_width_per_sh); 1523 } 1524 } 1525 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1526 mutex_unlock(&adev->grbm_idx_mutex); 1527 1528 adev->gfx.config.backend_enable_mask = active_rbs; 1529 adev->gfx.config.num_rbs = hweight32(active_rbs); 1530 } 1531 1532 #define DEFAULT_SH_MEM_BASES (0x6000) 1533 #define LDS_APP_BASE 0x1 1534 #define SCRATCH_APP_BASE 0x2 1535 1536 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1537 { 1538 int i; 1539 uint32_t sh_mem_bases; 1540 uint32_t data; 1541 1542 /* 1543 * Configure apertures: 1544 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1545 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1546 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1547 */ 1548 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1549 SCRATCH_APP_BASE; 1550 1551 mutex_lock(&adev->srbm_mutex); 1552 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1553 soc21_grbm_select(adev, 0, 0, 0, i); 1554 /* CP and shaders */ 1555 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1556 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1557 1558 /* Enable trap for each kfd vmid. */ 1559 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1560 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1561 } 1562 soc21_grbm_select(adev, 0, 0, 0, 0); 1563 mutex_unlock(&adev->srbm_mutex); 1564 1565 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1566 acccess. These should be enabled by FW for target VMIDs. */ 1567 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1568 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1569 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1570 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1571 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1572 } 1573 } 1574 1575 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1576 { 1577 int vmid; 1578 1579 /* 1580 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1581 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1582 * the driver can enable them for graphics. VMID0 should maintain 1583 * access so that HWS firmware can save/restore entries. 1584 */ 1585 for (vmid = 1; vmid < 16; vmid++) { 1586 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1587 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1588 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1589 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1590 } 1591 } 1592 1593 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1594 { 1595 /* TODO: harvest feature to be added later. */ 1596 } 1597 1598 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1599 { 1600 /* TCCs are global (not instanced). */ 1601 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1602 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1603 1604 adev->gfx.config.tcc_disabled_mask = 1605 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1606 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1607 } 1608 1609 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1610 { 1611 u32 tmp; 1612 int i; 1613 1614 if (!amdgpu_sriov_vf(adev)) 1615 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1616 1617 gfx_v11_0_setup_rb(adev); 1618 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1619 gfx_v11_0_get_tcc_info(adev); 1620 adev->gfx.config.pa_sc_tile_steering_override = 0; 1621 1622 /* XXX SH_MEM regs */ 1623 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1624 mutex_lock(&adev->srbm_mutex); 1625 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1626 soc21_grbm_select(adev, 0, 0, 0, i); 1627 /* CP and shaders */ 1628 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1629 if (i != 0) { 1630 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1631 (adev->gmc.private_aperture_start >> 48)); 1632 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1633 (adev->gmc.shared_aperture_start >> 48)); 1634 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1635 } 1636 } 1637 soc21_grbm_select(adev, 0, 0, 0, 0); 1638 1639 mutex_unlock(&adev->srbm_mutex); 1640 1641 gfx_v11_0_init_compute_vmid(adev); 1642 gfx_v11_0_init_gds_vmid(adev); 1643 } 1644 1645 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1646 bool enable) 1647 { 1648 u32 tmp; 1649 1650 if (amdgpu_sriov_vf(adev)) 1651 return; 1652 1653 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1654 1655 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1656 enable ? 1 : 0); 1657 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1658 enable ? 1 : 0); 1659 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1660 enable ? 1 : 0); 1661 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1662 enable ? 1 : 0); 1663 1664 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1665 } 1666 1667 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1668 { 1669 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1670 1671 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1672 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1673 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1674 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1675 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1676 1677 return 0; 1678 } 1679 1680 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1681 { 1682 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1683 1684 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1685 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1686 } 1687 1688 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1689 { 1690 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1691 udelay(50); 1692 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1693 udelay(50); 1694 } 1695 1696 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1697 bool enable) 1698 { 1699 uint32_t rlc_pg_cntl; 1700 1701 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1702 1703 if (!enable) { 1704 /* RLC_PG_CNTL[23] = 0 (default) 1705 * RLC will wait for handshake acks with SMU 1706 * GFXOFF will be enabled 1707 * RLC_PG_CNTL[23] = 1 1708 * RLC will not issue any message to SMU 1709 * hence no handshake between SMU & RLC 1710 * GFXOFF will be disabled 1711 */ 1712 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1713 } else 1714 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1715 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1716 } 1717 1718 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 1719 { 1720 /* TODO: enable rlc & smu handshake until smu 1721 * and gfxoff feature works as expected */ 1722 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1723 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 1724 1725 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1726 udelay(50); 1727 } 1728 1729 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 1730 { 1731 uint32_t tmp; 1732 1733 /* enable Save Restore Machine */ 1734 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1735 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1736 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1737 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1738 } 1739 1740 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 1741 { 1742 const struct rlc_firmware_header_v2_0 *hdr; 1743 const __le32 *fw_data; 1744 unsigned i, fw_size; 1745 1746 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1747 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1748 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1749 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1750 1751 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1752 RLCG_UCODE_LOADING_START_ADDRESS); 1753 1754 for (i = 0; i < fw_size; i++) 1755 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1756 le32_to_cpup(fw_data++)); 1757 1758 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1759 } 1760 1761 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1762 { 1763 const struct rlc_firmware_header_v2_2 *hdr; 1764 const __le32 *fw_data; 1765 unsigned i, fw_size; 1766 u32 tmp; 1767 1768 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1769 1770 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1771 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1772 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1773 1774 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1775 1776 for (i = 0; i < fw_size; i++) { 1777 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1778 msleep(1); 1779 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1780 le32_to_cpup(fw_data++)); 1781 } 1782 1783 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1784 1785 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1786 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1787 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1788 1789 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1790 for (i = 0; i < fw_size; i++) { 1791 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1792 msleep(1); 1793 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1794 le32_to_cpup(fw_data++)); 1795 } 1796 1797 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1798 1799 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1800 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1801 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1802 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1803 } 1804 1805 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 1806 { 1807 const struct rlc_firmware_header_v2_3 *hdr; 1808 const __le32 *fw_data; 1809 unsigned i, fw_size; 1810 u32 tmp; 1811 1812 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 1813 1814 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1815 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 1816 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 1817 1818 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 1819 1820 for (i = 0; i < fw_size; i++) { 1821 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1822 msleep(1); 1823 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 1824 le32_to_cpup(fw_data++)); 1825 } 1826 1827 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 1828 1829 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1830 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1831 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 1832 1833 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1834 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 1835 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 1836 1837 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 1838 1839 for (i = 0; i < fw_size; i++) { 1840 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1841 msleep(1); 1842 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 1843 le32_to_cpup(fw_data++)); 1844 } 1845 1846 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 1847 1848 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 1849 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 1850 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 1851 } 1852 1853 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 1854 { 1855 const struct rlc_firmware_header_v2_0 *hdr; 1856 uint16_t version_major; 1857 uint16_t version_minor; 1858 1859 if (!adev->gfx.rlc_fw) 1860 return -EINVAL; 1861 1862 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1863 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1864 1865 version_major = le16_to_cpu(hdr->header.header_version_major); 1866 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1867 1868 if (version_major == 2) { 1869 gfx_v11_0_load_rlcg_microcode(adev); 1870 if (amdgpu_dpm == 1) { 1871 if (version_minor >= 2) 1872 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 1873 if (version_minor == 3) 1874 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 1875 } 1876 1877 return 0; 1878 } 1879 1880 return -EINVAL; 1881 } 1882 1883 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 1884 { 1885 int r; 1886 1887 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1888 gfx_v11_0_init_csb(adev); 1889 1890 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1891 gfx_v11_0_rlc_enable_srm(adev); 1892 } else { 1893 if (amdgpu_sriov_vf(adev)) { 1894 gfx_v11_0_init_csb(adev); 1895 return 0; 1896 } 1897 1898 adev->gfx.rlc.funcs->stop(adev); 1899 1900 /* disable CG */ 1901 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1902 1903 /* disable PG */ 1904 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1905 1906 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1907 /* legacy rlc firmware loading */ 1908 r = gfx_v11_0_rlc_load_microcode(adev); 1909 if (r) 1910 return r; 1911 } 1912 1913 gfx_v11_0_init_csb(adev); 1914 1915 adev->gfx.rlc.funcs->start(adev); 1916 } 1917 return 0; 1918 } 1919 1920 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 1921 { 1922 uint32_t usec_timeout = 50000; /* wait for 50ms */ 1923 uint32_t tmp; 1924 int i; 1925 1926 /* Trigger an invalidation of the L1 instruction caches */ 1927 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 1928 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1929 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 1930 1931 /* Wait for invalidation complete */ 1932 for (i = 0; i < usec_timeout; i++) { 1933 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 1934 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 1935 INVALIDATE_CACHE_COMPLETE)) 1936 break; 1937 udelay(1); 1938 } 1939 1940 if (i >= usec_timeout) { 1941 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 1942 return -EINVAL; 1943 } 1944 1945 if (amdgpu_emu_mode == 1) 1946 adev->hdp.funcs->flush_hdp(adev, NULL); 1947 1948 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 1949 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 1950 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 1951 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 1952 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 1953 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 1954 1955 /* Program me ucode address into intruction cache address register */ 1956 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 1957 lower_32_bits(addr) & 0xFFFFF000); 1958 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 1959 upper_32_bits(addr)); 1960 1961 return 0; 1962 } 1963 1964 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 1965 { 1966 uint32_t usec_timeout = 50000; /* wait for 50ms */ 1967 uint32_t tmp; 1968 int i; 1969 1970 /* Trigger an invalidation of the L1 instruction caches */ 1971 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 1972 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1973 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 1974 1975 /* Wait for invalidation complete */ 1976 for (i = 0; i < usec_timeout; i++) { 1977 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 1978 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 1979 INVALIDATE_CACHE_COMPLETE)) 1980 break; 1981 udelay(1); 1982 } 1983 1984 if (i >= usec_timeout) { 1985 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 1986 return -EINVAL; 1987 } 1988 1989 if (amdgpu_emu_mode == 1) 1990 adev->hdp.funcs->flush_hdp(adev, NULL); 1991 1992 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 1993 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 1994 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 1995 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 1996 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 1997 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 1998 1999 /* Program pfp ucode address into intruction cache address register */ 2000 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2001 lower_32_bits(addr) & 0xFFFFF000); 2002 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2003 upper_32_bits(addr)); 2004 2005 return 0; 2006 } 2007 2008 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2009 { 2010 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2011 uint32_t tmp; 2012 int i; 2013 2014 /* Trigger an invalidation of the L1 instruction caches */ 2015 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2016 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2017 2018 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2019 2020 /* Wait for invalidation complete */ 2021 for (i = 0; i < usec_timeout; i++) { 2022 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2023 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2024 INVALIDATE_CACHE_COMPLETE)) 2025 break; 2026 udelay(1); 2027 } 2028 2029 if (i >= usec_timeout) { 2030 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2031 return -EINVAL; 2032 } 2033 2034 if (amdgpu_emu_mode == 1) 2035 adev->hdp.funcs->flush_hdp(adev, NULL); 2036 2037 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2038 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2039 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2040 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2041 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2042 2043 /* Program mec1 ucode address into intruction cache address register */ 2044 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2045 lower_32_bits(addr) & 0xFFFFF000); 2046 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2047 upper_32_bits(addr)); 2048 2049 return 0; 2050 } 2051 2052 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2053 { 2054 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2055 uint32_t tmp; 2056 unsigned i, pipe_id; 2057 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2058 2059 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2060 adev->gfx.pfp_fw->data; 2061 2062 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2063 lower_32_bits(addr)); 2064 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2065 upper_32_bits(addr)); 2066 2067 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2068 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2069 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2070 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2071 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2072 2073 /* 2074 * Programming any of the CP_PFP_IC_BASE registers 2075 * forces invalidation of the ME L1 I$. Wait for the 2076 * invalidation complete 2077 */ 2078 for (i = 0; i < usec_timeout; i++) { 2079 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2080 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2081 INVALIDATE_CACHE_COMPLETE)) 2082 break; 2083 udelay(1); 2084 } 2085 2086 if (i >= usec_timeout) { 2087 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2088 return -EINVAL; 2089 } 2090 2091 /* Prime the L1 instruction caches */ 2092 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2093 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2094 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2095 /* Waiting for cache primed*/ 2096 for (i = 0; i < usec_timeout; i++) { 2097 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2098 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2099 ICACHE_PRIMED)) 2100 break; 2101 udelay(1); 2102 } 2103 2104 if (i >= usec_timeout) { 2105 dev_err(adev->dev, "failed to prime instruction cache\n"); 2106 return -EINVAL; 2107 } 2108 2109 mutex_lock(&adev->srbm_mutex); 2110 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2111 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2112 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2113 (pfp_hdr->ucode_start_addr_hi << 30) | 2114 (pfp_hdr->ucode_start_addr_lo >> 2)); 2115 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2116 pfp_hdr->ucode_start_addr_hi >> 2); 2117 2118 /* 2119 * Program CP_ME_CNTL to reset given PIPE to take 2120 * effect of CP_PFP_PRGRM_CNTR_START. 2121 */ 2122 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2123 if (pipe_id == 0) 2124 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2125 PFP_PIPE0_RESET, 1); 2126 else 2127 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2128 PFP_PIPE1_RESET, 1); 2129 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2130 2131 /* Clear pfp pipe0 reset bit. */ 2132 if (pipe_id == 0) 2133 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2134 PFP_PIPE0_RESET, 0); 2135 else 2136 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2137 PFP_PIPE1_RESET, 0); 2138 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2139 2140 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2141 lower_32_bits(addr2)); 2142 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2143 upper_32_bits(addr2)); 2144 } 2145 soc21_grbm_select(adev, 0, 0, 0, 0); 2146 mutex_unlock(&adev->srbm_mutex); 2147 2148 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2149 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2150 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2151 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2152 2153 /* Invalidate the data caches */ 2154 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2155 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2156 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2157 2158 for (i = 0; i < usec_timeout; i++) { 2159 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2160 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2161 INVALIDATE_DCACHE_COMPLETE)) 2162 break; 2163 udelay(1); 2164 } 2165 2166 if (i >= usec_timeout) { 2167 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2168 return -EINVAL; 2169 } 2170 2171 return 0; 2172 } 2173 2174 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2175 { 2176 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2177 uint32_t tmp; 2178 unsigned i, pipe_id; 2179 const struct gfx_firmware_header_v2_0 *me_hdr; 2180 2181 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2182 adev->gfx.me_fw->data; 2183 2184 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2185 lower_32_bits(addr)); 2186 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2187 upper_32_bits(addr)); 2188 2189 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2190 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2191 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2192 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2193 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2194 2195 /* 2196 * Programming any of the CP_ME_IC_BASE registers 2197 * forces invalidation of the ME L1 I$. Wait for the 2198 * invalidation complete 2199 */ 2200 for (i = 0; i < usec_timeout; i++) { 2201 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2202 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2203 INVALIDATE_CACHE_COMPLETE)) 2204 break; 2205 udelay(1); 2206 } 2207 2208 if (i >= usec_timeout) { 2209 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2210 return -EINVAL; 2211 } 2212 2213 /* Prime the instruction caches */ 2214 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2215 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2216 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2217 2218 /* Waiting for instruction cache primed*/ 2219 for (i = 0; i < usec_timeout; i++) { 2220 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2221 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2222 ICACHE_PRIMED)) 2223 break; 2224 udelay(1); 2225 } 2226 2227 if (i >= usec_timeout) { 2228 dev_err(adev->dev, "failed to prime instruction cache\n"); 2229 return -EINVAL; 2230 } 2231 2232 mutex_lock(&adev->srbm_mutex); 2233 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2234 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2235 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2236 (me_hdr->ucode_start_addr_hi << 30) | 2237 (me_hdr->ucode_start_addr_lo >> 2) ); 2238 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2239 me_hdr->ucode_start_addr_hi>>2); 2240 2241 /* 2242 * Program CP_ME_CNTL to reset given PIPE to take 2243 * effect of CP_PFP_PRGRM_CNTR_START. 2244 */ 2245 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2246 if (pipe_id == 0) 2247 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2248 ME_PIPE0_RESET, 1); 2249 else 2250 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2251 ME_PIPE1_RESET, 1); 2252 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2253 2254 /* Clear pfp pipe0 reset bit. */ 2255 if (pipe_id == 0) 2256 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2257 ME_PIPE0_RESET, 0); 2258 else 2259 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2260 ME_PIPE1_RESET, 0); 2261 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2262 2263 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2264 lower_32_bits(addr2)); 2265 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2266 upper_32_bits(addr2)); 2267 } 2268 soc21_grbm_select(adev, 0, 0, 0, 0); 2269 mutex_unlock(&adev->srbm_mutex); 2270 2271 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2272 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2273 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2274 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2275 2276 /* Invalidate the data caches */ 2277 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2278 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2279 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2280 2281 for (i = 0; i < usec_timeout; i++) { 2282 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2283 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2284 INVALIDATE_DCACHE_COMPLETE)) 2285 break; 2286 udelay(1); 2287 } 2288 2289 if (i >= usec_timeout) { 2290 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2291 return -EINVAL; 2292 } 2293 2294 return 0; 2295 } 2296 2297 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2298 { 2299 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2300 uint32_t tmp; 2301 unsigned i; 2302 const struct gfx_firmware_header_v2_0 *mec_hdr; 2303 2304 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2305 adev->gfx.mec_fw->data; 2306 2307 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2308 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2309 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2310 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2311 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2312 2313 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2314 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2315 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2316 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2317 2318 mutex_lock(&adev->srbm_mutex); 2319 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2320 soc21_grbm_select(adev, 1, i, 0, 0); 2321 2322 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2323 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2324 upper_32_bits(addr2)); 2325 2326 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2327 mec_hdr->ucode_start_addr_lo >> 2 | 2328 mec_hdr->ucode_start_addr_hi << 30); 2329 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2330 mec_hdr->ucode_start_addr_hi >> 2); 2331 2332 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2333 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2334 upper_32_bits(addr)); 2335 } 2336 mutex_unlock(&adev->srbm_mutex); 2337 soc21_grbm_select(adev, 0, 0, 0, 0); 2338 2339 /* Trigger an invalidation of the L1 instruction caches */ 2340 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2341 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2342 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2343 2344 /* Wait for invalidation complete */ 2345 for (i = 0; i < usec_timeout; i++) { 2346 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2347 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2348 INVALIDATE_DCACHE_COMPLETE)) 2349 break; 2350 udelay(1); 2351 } 2352 2353 if (i >= usec_timeout) { 2354 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2355 return -EINVAL; 2356 } 2357 2358 /* Trigger an invalidation of the L1 instruction caches */ 2359 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2360 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2361 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2362 2363 /* Wait for invalidation complete */ 2364 for (i = 0; i < usec_timeout; i++) { 2365 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2366 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2367 INVALIDATE_CACHE_COMPLETE)) 2368 break; 2369 udelay(1); 2370 } 2371 2372 if (i >= usec_timeout) { 2373 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2374 return -EINVAL; 2375 } 2376 2377 return 0; 2378 } 2379 2380 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2381 { 2382 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2383 const struct gfx_firmware_header_v2_0 *me_hdr; 2384 const struct gfx_firmware_header_v2_0 *mec_hdr; 2385 uint32_t pipe_id, tmp; 2386 2387 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2388 adev->gfx.mec_fw->data; 2389 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2390 adev->gfx.me_fw->data; 2391 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2392 adev->gfx.pfp_fw->data; 2393 2394 /* config pfp program start addr */ 2395 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2396 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2397 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2398 (pfp_hdr->ucode_start_addr_hi << 30) | 2399 (pfp_hdr->ucode_start_addr_lo >> 2)); 2400 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2401 pfp_hdr->ucode_start_addr_hi >> 2); 2402 } 2403 soc21_grbm_select(adev, 0, 0, 0, 0); 2404 2405 /* reset pfp pipe */ 2406 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2407 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2408 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2409 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2410 2411 /* clear pfp pipe reset */ 2412 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2413 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2414 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2415 2416 /* config me program start addr */ 2417 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2418 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2419 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2420 (me_hdr->ucode_start_addr_hi << 30) | 2421 (me_hdr->ucode_start_addr_lo >> 2) ); 2422 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2423 me_hdr->ucode_start_addr_hi>>2); 2424 } 2425 soc21_grbm_select(adev, 0, 0, 0, 0); 2426 2427 /* reset me pipe */ 2428 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2429 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2430 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2431 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2432 2433 /* clear me pipe reset */ 2434 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2435 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2436 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2437 2438 /* config mec program start addr */ 2439 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2440 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2441 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2442 mec_hdr->ucode_start_addr_lo >> 2 | 2443 mec_hdr->ucode_start_addr_hi << 30); 2444 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2445 mec_hdr->ucode_start_addr_hi >> 2); 2446 } 2447 soc21_grbm_select(adev, 0, 0, 0, 0); 2448 2449 /* reset mec pipe */ 2450 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2451 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2452 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2453 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2454 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2455 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2456 2457 /* clear mec pipe reset */ 2458 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2459 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2460 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2461 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2462 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2463 } 2464 2465 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2466 { 2467 uint32_t cp_status; 2468 uint32_t bootload_status; 2469 int i, r; 2470 uint64_t addr, addr2; 2471 2472 for (i = 0; i < adev->usec_timeout; i++) { 2473 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2474 2475 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) || 2476 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4)) 2477 bootload_status = RREG32_SOC15(GC, 0, 2478 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2479 else 2480 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2481 2482 if ((cp_status == 0) && 2483 (REG_GET_FIELD(bootload_status, 2484 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2485 break; 2486 } 2487 udelay(1); 2488 } 2489 2490 if (i >= adev->usec_timeout) { 2491 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2492 return -ETIMEDOUT; 2493 } 2494 2495 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2496 if (adev->gfx.rs64_enable) { 2497 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2498 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2499 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2500 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2501 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2502 if (r) 2503 return r; 2504 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2505 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2506 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2507 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2508 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2509 if (r) 2510 return r; 2511 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2512 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2513 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2514 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2515 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2516 if (r) 2517 return r; 2518 } else { 2519 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2520 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2521 r = gfx_v11_0_config_me_cache(adev, addr); 2522 if (r) 2523 return r; 2524 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2525 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2526 r = gfx_v11_0_config_pfp_cache(adev, addr); 2527 if (r) 2528 return r; 2529 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2530 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2531 r = gfx_v11_0_config_mec_cache(adev, addr); 2532 if (r) 2533 return r; 2534 } 2535 } 2536 2537 return 0; 2538 } 2539 2540 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2541 { 2542 int i; 2543 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2544 2545 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2546 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2547 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2548 2549 for (i = 0; i < adev->usec_timeout; i++) { 2550 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2551 break; 2552 udelay(1); 2553 } 2554 2555 if (i >= adev->usec_timeout) 2556 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2557 2558 return 0; 2559 } 2560 2561 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2562 { 2563 int r; 2564 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2565 const __le32 *fw_data; 2566 unsigned i, fw_size; 2567 2568 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2569 adev->gfx.pfp_fw->data; 2570 2571 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2572 2573 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2574 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2575 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2576 2577 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2578 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2579 &adev->gfx.pfp.pfp_fw_obj, 2580 &adev->gfx.pfp.pfp_fw_gpu_addr, 2581 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2582 if (r) { 2583 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2584 gfx_v11_0_pfp_fini(adev); 2585 return r; 2586 } 2587 2588 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2589 2590 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2591 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2592 2593 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2594 2595 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2596 2597 for (i = 0; i < pfp_hdr->jt_size; i++) 2598 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2599 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2600 2601 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2602 2603 return 0; 2604 } 2605 2606 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2607 { 2608 int r; 2609 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2610 const __le32 *fw_ucode, *fw_data; 2611 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2612 uint32_t tmp; 2613 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2614 2615 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2616 adev->gfx.pfp_fw->data; 2617 2618 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2619 2620 /* instruction */ 2621 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2622 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2623 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2624 /* data */ 2625 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2626 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2627 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2628 2629 /* 64kb align */ 2630 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2631 64 * 1024, 2632 AMDGPU_GEM_DOMAIN_VRAM | 2633 AMDGPU_GEM_DOMAIN_GTT, 2634 &adev->gfx.pfp.pfp_fw_obj, 2635 &adev->gfx.pfp.pfp_fw_gpu_addr, 2636 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2637 if (r) { 2638 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2639 gfx_v11_0_pfp_fini(adev); 2640 return r; 2641 } 2642 2643 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2644 64 * 1024, 2645 AMDGPU_GEM_DOMAIN_VRAM | 2646 AMDGPU_GEM_DOMAIN_GTT, 2647 &adev->gfx.pfp.pfp_fw_data_obj, 2648 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2649 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2650 if (r) { 2651 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2652 gfx_v11_0_pfp_fini(adev); 2653 return r; 2654 } 2655 2656 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2657 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2658 2659 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2660 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2661 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2662 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2663 2664 if (amdgpu_emu_mode == 1) 2665 adev->hdp.funcs->flush_hdp(adev, NULL); 2666 2667 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2668 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2669 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2670 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2671 2672 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2673 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2674 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2675 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2676 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2677 2678 /* 2679 * Programming any of the CP_PFP_IC_BASE registers 2680 * forces invalidation of the ME L1 I$. Wait for the 2681 * invalidation complete 2682 */ 2683 for (i = 0; i < usec_timeout; i++) { 2684 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2685 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2686 INVALIDATE_CACHE_COMPLETE)) 2687 break; 2688 udelay(1); 2689 } 2690 2691 if (i >= usec_timeout) { 2692 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2693 return -EINVAL; 2694 } 2695 2696 /* Prime the L1 instruction caches */ 2697 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2698 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2699 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2700 /* Waiting for cache primed*/ 2701 for (i = 0; i < usec_timeout; i++) { 2702 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2703 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2704 ICACHE_PRIMED)) 2705 break; 2706 udelay(1); 2707 } 2708 2709 if (i >= usec_timeout) { 2710 dev_err(adev->dev, "failed to prime instruction cache\n"); 2711 return -EINVAL; 2712 } 2713 2714 mutex_lock(&adev->srbm_mutex); 2715 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2716 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2717 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2718 (pfp_hdr->ucode_start_addr_hi << 30) | 2719 (pfp_hdr->ucode_start_addr_lo >> 2) ); 2720 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2721 pfp_hdr->ucode_start_addr_hi>>2); 2722 2723 /* 2724 * Program CP_ME_CNTL to reset given PIPE to take 2725 * effect of CP_PFP_PRGRM_CNTR_START. 2726 */ 2727 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2728 if (pipe_id == 0) 2729 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2730 PFP_PIPE0_RESET, 1); 2731 else 2732 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2733 PFP_PIPE1_RESET, 1); 2734 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2735 2736 /* Clear pfp pipe0 reset bit. */ 2737 if (pipe_id == 0) 2738 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2739 PFP_PIPE0_RESET, 0); 2740 else 2741 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2742 PFP_PIPE1_RESET, 0); 2743 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2744 2745 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2746 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2747 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2748 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2749 } 2750 soc21_grbm_select(adev, 0, 0, 0, 0); 2751 mutex_unlock(&adev->srbm_mutex); 2752 2753 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2754 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2755 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2756 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2757 2758 /* Invalidate the data caches */ 2759 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2760 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2761 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2762 2763 for (i = 0; i < usec_timeout; i++) { 2764 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2765 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2766 INVALIDATE_DCACHE_COMPLETE)) 2767 break; 2768 udelay(1); 2769 } 2770 2771 if (i >= usec_timeout) { 2772 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2773 return -EINVAL; 2774 } 2775 2776 return 0; 2777 } 2778 2779 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2780 { 2781 int r; 2782 const struct gfx_firmware_header_v1_0 *me_hdr; 2783 const __le32 *fw_data; 2784 unsigned i, fw_size; 2785 2786 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2787 adev->gfx.me_fw->data; 2788 2789 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2790 2791 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2792 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2793 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2794 2795 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2796 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2797 &adev->gfx.me.me_fw_obj, 2798 &adev->gfx.me.me_fw_gpu_addr, 2799 (void **)&adev->gfx.me.me_fw_ptr); 2800 if (r) { 2801 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2802 gfx_v11_0_me_fini(adev); 2803 return r; 2804 } 2805 2806 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2807 2808 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2809 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2810 2811 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 2812 2813 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 2814 2815 for (i = 0; i < me_hdr->jt_size; i++) 2816 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 2817 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 2818 2819 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 2820 2821 return 0; 2822 } 2823 2824 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2825 { 2826 int r; 2827 const struct gfx_firmware_header_v2_0 *me_hdr; 2828 const __le32 *fw_ucode, *fw_data; 2829 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2830 uint32_t tmp; 2831 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2832 2833 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2834 adev->gfx.me_fw->data; 2835 2836 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2837 2838 /* instruction */ 2839 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2840 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2841 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2842 /* data */ 2843 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2844 le32_to_cpu(me_hdr->data_offset_bytes)); 2845 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2846 2847 /* 64kb align*/ 2848 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2849 64 * 1024, 2850 AMDGPU_GEM_DOMAIN_VRAM | 2851 AMDGPU_GEM_DOMAIN_GTT, 2852 &adev->gfx.me.me_fw_obj, 2853 &adev->gfx.me.me_fw_gpu_addr, 2854 (void **)&adev->gfx.me.me_fw_ptr); 2855 if (r) { 2856 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2857 gfx_v11_0_me_fini(adev); 2858 return r; 2859 } 2860 2861 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2862 64 * 1024, 2863 AMDGPU_GEM_DOMAIN_VRAM | 2864 AMDGPU_GEM_DOMAIN_GTT, 2865 &adev->gfx.me.me_fw_data_obj, 2866 &adev->gfx.me.me_fw_data_gpu_addr, 2867 (void **)&adev->gfx.me.me_fw_data_ptr); 2868 if (r) { 2869 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2870 gfx_v11_0_pfp_fini(adev); 2871 return r; 2872 } 2873 2874 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2875 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2876 2877 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2878 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2879 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2880 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2881 2882 if (amdgpu_emu_mode == 1) 2883 adev->hdp.funcs->flush_hdp(adev, NULL); 2884 2885 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2886 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2887 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2888 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2889 2890 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2891 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2892 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2893 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2894 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2895 2896 /* 2897 * Programming any of the CP_ME_IC_BASE registers 2898 * forces invalidation of the ME L1 I$. Wait for the 2899 * invalidation complete 2900 */ 2901 for (i = 0; i < usec_timeout; i++) { 2902 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2903 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2904 INVALIDATE_CACHE_COMPLETE)) 2905 break; 2906 udelay(1); 2907 } 2908 2909 if (i >= usec_timeout) { 2910 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2911 return -EINVAL; 2912 } 2913 2914 /* Prime the instruction caches */ 2915 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2916 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2917 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2918 2919 /* Waiting for instruction cache primed*/ 2920 for (i = 0; i < usec_timeout; i++) { 2921 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2922 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2923 ICACHE_PRIMED)) 2924 break; 2925 udelay(1); 2926 } 2927 2928 if (i >= usec_timeout) { 2929 dev_err(adev->dev, "failed to prime instruction cache\n"); 2930 return -EINVAL; 2931 } 2932 2933 mutex_lock(&adev->srbm_mutex); 2934 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2935 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2936 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2937 (me_hdr->ucode_start_addr_hi << 30) | 2938 (me_hdr->ucode_start_addr_lo >> 2) ); 2939 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2940 me_hdr->ucode_start_addr_hi>>2); 2941 2942 /* 2943 * Program CP_ME_CNTL to reset given PIPE to take 2944 * effect of CP_PFP_PRGRM_CNTR_START. 2945 */ 2946 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2947 if (pipe_id == 0) 2948 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2949 ME_PIPE0_RESET, 1); 2950 else 2951 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2952 ME_PIPE1_RESET, 1); 2953 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2954 2955 /* Clear pfp pipe0 reset bit. */ 2956 if (pipe_id == 0) 2957 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2958 ME_PIPE0_RESET, 0); 2959 else 2960 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2961 ME_PIPE1_RESET, 0); 2962 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2963 2964 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2965 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2966 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2967 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 2968 } 2969 soc21_grbm_select(adev, 0, 0, 0, 0); 2970 mutex_unlock(&adev->srbm_mutex); 2971 2972 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2973 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2974 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2975 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2976 2977 /* Invalidate the data caches */ 2978 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2979 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2980 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2981 2982 for (i = 0; i < usec_timeout; i++) { 2983 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2984 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2985 INVALIDATE_DCACHE_COMPLETE)) 2986 break; 2987 udelay(1); 2988 } 2989 2990 if (i >= usec_timeout) { 2991 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2992 return -EINVAL; 2993 } 2994 2995 return 0; 2996 } 2997 2998 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2999 { 3000 int r; 3001 3002 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3003 return -EINVAL; 3004 3005 gfx_v11_0_cp_gfx_enable(adev, false); 3006 3007 if (adev->gfx.rs64_enable) 3008 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3009 else 3010 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3011 if (r) { 3012 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3013 return r; 3014 } 3015 3016 if (adev->gfx.rs64_enable) 3017 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3018 else 3019 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3020 if (r) { 3021 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3022 return r; 3023 } 3024 3025 return 0; 3026 } 3027 3028 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3029 { 3030 struct amdgpu_ring *ring; 3031 const struct cs_section_def *sect = NULL; 3032 const struct cs_extent_def *ext = NULL; 3033 int r, i; 3034 int ctx_reg_offset; 3035 3036 /* init the CP */ 3037 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3038 adev->gfx.config.max_hw_contexts - 1); 3039 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3040 3041 if (!amdgpu_async_gfx_ring) 3042 gfx_v11_0_cp_gfx_enable(adev, true); 3043 3044 ring = &adev->gfx.gfx_ring[0]; 3045 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3046 if (r) { 3047 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3048 return r; 3049 } 3050 3051 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3052 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3053 3054 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3055 amdgpu_ring_write(ring, 0x80000000); 3056 amdgpu_ring_write(ring, 0x80000000); 3057 3058 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3059 for (ext = sect->section; ext->extent != NULL; ++ext) { 3060 if (sect->id == SECT_CONTEXT) { 3061 amdgpu_ring_write(ring, 3062 PACKET3(PACKET3_SET_CONTEXT_REG, 3063 ext->reg_count)); 3064 amdgpu_ring_write(ring, ext->reg_index - 3065 PACKET3_SET_CONTEXT_REG_START); 3066 for (i = 0; i < ext->reg_count; i++) 3067 amdgpu_ring_write(ring, ext->extent[i]); 3068 } 3069 } 3070 } 3071 3072 ctx_reg_offset = 3073 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3074 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3075 amdgpu_ring_write(ring, ctx_reg_offset); 3076 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3077 3078 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3079 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3080 3081 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3082 amdgpu_ring_write(ring, 0); 3083 3084 amdgpu_ring_commit(ring); 3085 3086 /* submit cs packet to copy state 0 to next available state */ 3087 if (adev->gfx.num_gfx_rings > 1) { 3088 /* maximum supported gfx ring is 2 */ 3089 ring = &adev->gfx.gfx_ring[1]; 3090 r = amdgpu_ring_alloc(ring, 2); 3091 if (r) { 3092 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3093 return r; 3094 } 3095 3096 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3097 amdgpu_ring_write(ring, 0); 3098 3099 amdgpu_ring_commit(ring); 3100 } 3101 return 0; 3102 } 3103 3104 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3105 CP_PIPE_ID pipe) 3106 { 3107 u32 tmp; 3108 3109 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3110 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3111 3112 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3113 } 3114 3115 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3116 struct amdgpu_ring *ring) 3117 { 3118 u32 tmp; 3119 3120 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3121 if (ring->use_doorbell) { 3122 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3123 DOORBELL_OFFSET, ring->doorbell_index); 3124 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3125 DOORBELL_EN, 1); 3126 } else { 3127 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3128 DOORBELL_EN, 0); 3129 } 3130 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3131 3132 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3133 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3134 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3135 3136 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3137 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3138 } 3139 3140 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3141 { 3142 struct amdgpu_ring *ring; 3143 u32 tmp; 3144 u32 rb_bufsz; 3145 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3146 u32 i; 3147 3148 /* Set the write pointer delay */ 3149 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3150 3151 /* set the RB to use vmid 0 */ 3152 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3153 3154 /* Init gfx ring 0 for pipe 0 */ 3155 mutex_lock(&adev->srbm_mutex); 3156 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3157 3158 /* Set ring buffer size */ 3159 ring = &adev->gfx.gfx_ring[0]; 3160 rb_bufsz = order_base_2(ring->ring_size / 8); 3161 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3162 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3163 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3164 3165 /* Initialize the ring buffer's write pointers */ 3166 ring->wptr = 0; 3167 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3168 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3169 3170 /* set the wb address wether it's enabled or not */ 3171 rptr_addr = ring->rptr_gpu_addr; 3172 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3173 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3174 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3175 3176 wptr_gpu_addr = ring->wptr_gpu_addr; 3177 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3178 lower_32_bits(wptr_gpu_addr)); 3179 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3180 upper_32_bits(wptr_gpu_addr)); 3181 3182 mdelay(1); 3183 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3184 3185 rb_addr = ring->gpu_addr >> 8; 3186 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3187 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3188 3189 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3190 3191 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3192 mutex_unlock(&adev->srbm_mutex); 3193 3194 /* Init gfx ring 1 for pipe 1 */ 3195 if (adev->gfx.num_gfx_rings > 1) { 3196 mutex_lock(&adev->srbm_mutex); 3197 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3198 /* maximum supported gfx ring is 2 */ 3199 ring = &adev->gfx.gfx_ring[1]; 3200 rb_bufsz = order_base_2(ring->ring_size / 8); 3201 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3202 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3203 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3204 /* Initialize the ring buffer's write pointers */ 3205 ring->wptr = 0; 3206 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3207 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3208 /* Set the wb address wether it's enabled or not */ 3209 rptr_addr = ring->rptr_gpu_addr; 3210 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3211 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3212 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3213 wptr_gpu_addr = ring->wptr_gpu_addr; 3214 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3215 lower_32_bits(wptr_gpu_addr)); 3216 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3217 upper_32_bits(wptr_gpu_addr)); 3218 3219 mdelay(1); 3220 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3221 3222 rb_addr = ring->gpu_addr >> 8; 3223 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3224 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3225 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3226 3227 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3228 mutex_unlock(&adev->srbm_mutex); 3229 } 3230 /* Switch to pipe 0 */ 3231 mutex_lock(&adev->srbm_mutex); 3232 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3233 mutex_unlock(&adev->srbm_mutex); 3234 3235 /* start the ring */ 3236 gfx_v11_0_cp_gfx_start(adev); 3237 3238 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3239 ring = &adev->gfx.gfx_ring[i]; 3240 ring->sched.ready = true; 3241 } 3242 3243 return 0; 3244 } 3245 3246 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3247 { 3248 u32 data; 3249 3250 if (adev->gfx.rs64_enable) { 3251 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3252 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3253 enable ? 0 : 1); 3254 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3255 enable ? 0 : 1); 3256 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3257 enable ? 0 : 1); 3258 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3259 enable ? 0 : 1); 3260 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3261 enable ? 0 : 1); 3262 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3263 enable ? 1 : 0); 3264 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3265 enable ? 1 : 0); 3266 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3267 enable ? 1 : 0); 3268 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3269 enable ? 1 : 0); 3270 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3271 enable ? 0 : 1); 3272 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3273 } else { 3274 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3275 3276 if (enable) { 3277 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3278 if (!adev->enable_mes_kiq) 3279 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3280 MEC_ME2_HALT, 0); 3281 } else { 3282 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3283 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3284 } 3285 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3286 } 3287 3288 adev->gfx.kiq.ring.sched.ready = enable; 3289 3290 udelay(50); 3291 } 3292 3293 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3294 { 3295 const struct gfx_firmware_header_v1_0 *mec_hdr; 3296 const __le32 *fw_data; 3297 unsigned i, fw_size; 3298 u32 *fw = NULL; 3299 int r; 3300 3301 if (!adev->gfx.mec_fw) 3302 return -EINVAL; 3303 3304 gfx_v11_0_cp_compute_enable(adev, false); 3305 3306 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3307 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3308 3309 fw_data = (const __le32 *) 3310 (adev->gfx.mec_fw->data + 3311 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3312 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3313 3314 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3315 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3316 &adev->gfx.mec.mec_fw_obj, 3317 &adev->gfx.mec.mec_fw_gpu_addr, 3318 (void **)&fw); 3319 if (r) { 3320 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3321 gfx_v11_0_mec_fini(adev); 3322 return r; 3323 } 3324 3325 memcpy(fw, fw_data, fw_size); 3326 3327 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3328 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3329 3330 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3331 3332 /* MEC1 */ 3333 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3334 3335 for (i = 0; i < mec_hdr->jt_size; i++) 3336 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3337 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3338 3339 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3340 3341 return 0; 3342 } 3343 3344 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3345 { 3346 const struct gfx_firmware_header_v2_0 *mec_hdr; 3347 const __le32 *fw_ucode, *fw_data; 3348 u32 tmp, fw_ucode_size, fw_data_size; 3349 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3350 u32 *fw_ucode_ptr, *fw_data_ptr; 3351 int r; 3352 3353 if (!adev->gfx.mec_fw) 3354 return -EINVAL; 3355 3356 gfx_v11_0_cp_compute_enable(adev, false); 3357 3358 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3359 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3360 3361 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3362 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3363 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3364 3365 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3366 le32_to_cpu(mec_hdr->data_offset_bytes)); 3367 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3368 3369 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3370 64 * 1024, 3371 AMDGPU_GEM_DOMAIN_VRAM | 3372 AMDGPU_GEM_DOMAIN_GTT, 3373 &adev->gfx.mec.mec_fw_obj, 3374 &adev->gfx.mec.mec_fw_gpu_addr, 3375 (void **)&fw_ucode_ptr); 3376 if (r) { 3377 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3378 gfx_v11_0_mec_fini(adev); 3379 return r; 3380 } 3381 3382 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3383 64 * 1024, 3384 AMDGPU_GEM_DOMAIN_VRAM | 3385 AMDGPU_GEM_DOMAIN_GTT, 3386 &adev->gfx.mec.mec_fw_data_obj, 3387 &adev->gfx.mec.mec_fw_data_gpu_addr, 3388 (void **)&fw_data_ptr); 3389 if (r) { 3390 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3391 gfx_v11_0_mec_fini(adev); 3392 return r; 3393 } 3394 3395 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3396 memcpy(fw_data_ptr, fw_data, fw_data_size); 3397 3398 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3399 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3400 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3401 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3402 3403 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3404 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3405 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3406 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3407 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3408 3409 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3410 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3411 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3412 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3413 3414 mutex_lock(&adev->srbm_mutex); 3415 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3416 soc21_grbm_select(adev, 1, i, 0, 0); 3417 3418 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3419 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3420 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3421 3422 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3423 mec_hdr->ucode_start_addr_lo >> 2 | 3424 mec_hdr->ucode_start_addr_hi << 30); 3425 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3426 mec_hdr->ucode_start_addr_hi >> 2); 3427 3428 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3429 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3430 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3431 } 3432 mutex_unlock(&adev->srbm_mutex); 3433 soc21_grbm_select(adev, 0, 0, 0, 0); 3434 3435 /* Trigger an invalidation of the L1 instruction caches */ 3436 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3437 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3438 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3439 3440 /* Wait for invalidation complete */ 3441 for (i = 0; i < usec_timeout; i++) { 3442 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3443 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3444 INVALIDATE_DCACHE_COMPLETE)) 3445 break; 3446 udelay(1); 3447 } 3448 3449 if (i >= usec_timeout) { 3450 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3451 return -EINVAL; 3452 } 3453 3454 /* Trigger an invalidation of the L1 instruction caches */ 3455 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3456 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3457 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3458 3459 /* Wait for invalidation complete */ 3460 for (i = 0; i < usec_timeout; i++) { 3461 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3462 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3463 INVALIDATE_CACHE_COMPLETE)) 3464 break; 3465 udelay(1); 3466 } 3467 3468 if (i >= usec_timeout) { 3469 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3470 return -EINVAL; 3471 } 3472 3473 return 0; 3474 } 3475 3476 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3477 { 3478 uint32_t tmp; 3479 struct amdgpu_device *adev = ring->adev; 3480 3481 /* tell RLC which is KIQ queue */ 3482 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3483 tmp &= 0xffffff00; 3484 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3485 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3486 tmp |= 0x80; 3487 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3488 } 3489 3490 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3491 { 3492 /* set graphics engine doorbell range */ 3493 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3494 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3495 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3496 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3497 3498 /* set compute engine doorbell range */ 3499 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3500 (adev->doorbell_index.kiq * 2) << 2); 3501 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3502 (adev->doorbell_index.userqueue_end * 2) << 2); 3503 } 3504 3505 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3506 struct amdgpu_mqd_prop *prop) 3507 { 3508 struct v11_gfx_mqd *mqd = m; 3509 uint64_t hqd_gpu_addr, wb_gpu_addr; 3510 uint32_t tmp; 3511 uint32_t rb_bufsz; 3512 3513 /* set up gfx hqd wptr */ 3514 mqd->cp_gfx_hqd_wptr = 0; 3515 mqd->cp_gfx_hqd_wptr_hi = 0; 3516 3517 /* set the pointer to the MQD */ 3518 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3519 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3520 3521 /* set up mqd control */ 3522 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3523 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3524 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3525 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3526 mqd->cp_gfx_mqd_control = tmp; 3527 3528 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3529 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3530 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3531 mqd->cp_gfx_hqd_vmid = 0; 3532 3533 /* set up default queue priority level 3534 * 0x0 = low priority, 0x1 = high priority */ 3535 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3536 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3537 mqd->cp_gfx_hqd_queue_priority = tmp; 3538 3539 /* set up time quantum */ 3540 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3541 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3542 mqd->cp_gfx_hqd_quantum = tmp; 3543 3544 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3545 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3546 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3547 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3548 3549 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3550 wb_gpu_addr = prop->rptr_gpu_addr; 3551 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3552 mqd->cp_gfx_hqd_rptr_addr_hi = 3553 upper_32_bits(wb_gpu_addr) & 0xffff; 3554 3555 /* set up rb_wptr_poll addr */ 3556 wb_gpu_addr = prop->wptr_gpu_addr; 3557 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3558 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3559 3560 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3561 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3562 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3563 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3564 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3565 #ifdef __BIG_ENDIAN 3566 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3567 #endif 3568 mqd->cp_gfx_hqd_cntl = tmp; 3569 3570 /* set up cp_doorbell_control */ 3571 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3572 if (prop->use_doorbell) { 3573 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3574 DOORBELL_OFFSET, prop->doorbell_index); 3575 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3576 DOORBELL_EN, 1); 3577 } else 3578 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3579 DOORBELL_EN, 0); 3580 mqd->cp_rb_doorbell_control = tmp; 3581 3582 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3583 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3584 3585 /* active the queue */ 3586 mqd->cp_gfx_hqd_active = 1; 3587 3588 return 0; 3589 } 3590 3591 #ifdef BRING_UP_DEBUG 3592 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3593 { 3594 struct amdgpu_device *adev = ring->adev; 3595 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3596 3597 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3598 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3599 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3600 3601 /* set GFX_MQD_BASE */ 3602 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3603 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3604 3605 /* set GFX_MQD_CONTROL */ 3606 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3607 3608 /* set GFX_HQD_VMID to 0 */ 3609 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3610 3611 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY, 3612 mqd->cp_gfx_hqd_queue_priority); 3613 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3614 3615 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3616 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3617 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3618 3619 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3620 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3621 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3622 3623 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3624 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3625 3626 /* set RB_WPTR_POLL_ADDR */ 3627 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3628 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3629 3630 /* set RB_DOORBELL_CONTROL */ 3631 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3632 3633 /* active the queue */ 3634 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3635 3636 return 0; 3637 } 3638 #endif 3639 3640 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3641 { 3642 struct amdgpu_device *adev = ring->adev; 3643 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3644 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3645 3646 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3647 memset((void *)mqd, 0, sizeof(*mqd)); 3648 mutex_lock(&adev->srbm_mutex); 3649 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3650 amdgpu_ring_init_mqd(ring); 3651 #ifdef BRING_UP_DEBUG 3652 gfx_v11_0_gfx_queue_init_register(ring); 3653 #endif 3654 soc21_grbm_select(adev, 0, 0, 0, 0); 3655 mutex_unlock(&adev->srbm_mutex); 3656 if (adev->gfx.me.mqd_backup[mqd_idx]) 3657 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3658 } else if (amdgpu_in_reset(adev)) { 3659 /* reset mqd with the backup copy */ 3660 if (adev->gfx.me.mqd_backup[mqd_idx]) 3661 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3662 /* reset the ring */ 3663 ring->wptr = 0; 3664 *ring->wptr_cpu_addr = 0; 3665 amdgpu_ring_clear_ring(ring); 3666 #ifdef BRING_UP_DEBUG 3667 mutex_lock(&adev->srbm_mutex); 3668 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3669 gfx_v11_0_gfx_queue_init_register(ring); 3670 soc21_grbm_select(adev, 0, 0, 0, 0); 3671 mutex_unlock(&adev->srbm_mutex); 3672 #endif 3673 } else { 3674 amdgpu_ring_clear_ring(ring); 3675 } 3676 3677 return 0; 3678 } 3679 3680 #ifndef BRING_UP_DEBUG 3681 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev) 3682 { 3683 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3684 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3685 int r, i; 3686 3687 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3688 return -EINVAL; 3689 3690 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3691 adev->gfx.num_gfx_rings); 3692 if (r) { 3693 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3694 return r; 3695 } 3696 3697 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3698 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3699 3700 return amdgpu_ring_test_helper(kiq_ring); 3701 } 3702 #endif 3703 3704 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3705 { 3706 int r, i; 3707 struct amdgpu_ring *ring; 3708 3709 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3710 ring = &adev->gfx.gfx_ring[i]; 3711 3712 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3713 if (unlikely(r != 0)) 3714 goto done; 3715 3716 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3717 if (!r) { 3718 r = gfx_v11_0_gfx_init_queue(ring); 3719 amdgpu_bo_kunmap(ring->mqd_obj); 3720 ring->mqd_ptr = NULL; 3721 } 3722 amdgpu_bo_unreserve(ring->mqd_obj); 3723 if (r) 3724 goto done; 3725 } 3726 #ifndef BRING_UP_DEBUG 3727 r = gfx_v11_0_kiq_enable_kgq(adev); 3728 if (r) 3729 goto done; 3730 #endif 3731 r = gfx_v11_0_cp_gfx_start(adev); 3732 if (r) 3733 goto done; 3734 3735 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3736 ring = &adev->gfx.gfx_ring[i]; 3737 ring->sched.ready = true; 3738 } 3739 done: 3740 return r; 3741 } 3742 3743 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3744 struct amdgpu_mqd_prop *prop) 3745 { 3746 struct v11_compute_mqd *mqd = m; 3747 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3748 uint32_t tmp; 3749 3750 mqd->header = 0xC0310800; 3751 mqd->compute_pipelinestat_enable = 0x00000001; 3752 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3753 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3754 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3755 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3756 mqd->compute_misc_reserved = 0x00000007; 3757 3758 eop_base_addr = prop->eop_gpu_addr >> 8; 3759 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3760 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3761 3762 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3763 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3764 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3765 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 3766 3767 mqd->cp_hqd_eop_control = tmp; 3768 3769 /* enable doorbell? */ 3770 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3771 3772 if (prop->use_doorbell) { 3773 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3774 DOORBELL_OFFSET, prop->doorbell_index); 3775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3776 DOORBELL_EN, 1); 3777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3778 DOORBELL_SOURCE, 0); 3779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3780 DOORBELL_HIT, 0); 3781 } else { 3782 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3783 DOORBELL_EN, 0); 3784 } 3785 3786 mqd->cp_hqd_pq_doorbell_control = tmp; 3787 3788 /* disable the queue if it's active */ 3789 mqd->cp_hqd_dequeue_request = 0; 3790 mqd->cp_hqd_pq_rptr = 0; 3791 mqd->cp_hqd_pq_wptr_lo = 0; 3792 mqd->cp_hqd_pq_wptr_hi = 0; 3793 3794 /* set the pointer to the MQD */ 3795 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3796 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3797 3798 /* set MQD vmid to 0 */ 3799 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3800 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3801 mqd->cp_mqd_control = tmp; 3802 3803 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3804 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3805 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3806 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3807 3808 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3809 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3810 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3811 (order_base_2(prop->queue_size / 4) - 1)); 3812 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3813 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3814 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3815 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3816 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3817 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3818 mqd->cp_hqd_pq_control = tmp; 3819 3820 /* set the wb address whether it's enabled or not */ 3821 wb_gpu_addr = prop->rptr_gpu_addr; 3822 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3823 mqd->cp_hqd_pq_rptr_report_addr_hi = 3824 upper_32_bits(wb_gpu_addr) & 0xffff; 3825 3826 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3827 wb_gpu_addr = prop->wptr_gpu_addr; 3828 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3829 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3830 3831 tmp = 0; 3832 /* enable the doorbell if requested */ 3833 if (prop->use_doorbell) { 3834 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3835 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3836 DOORBELL_OFFSET, prop->doorbell_index); 3837 3838 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3839 DOORBELL_EN, 1); 3840 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3841 DOORBELL_SOURCE, 0); 3842 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3843 DOORBELL_HIT, 0); 3844 } 3845 3846 mqd->cp_hqd_pq_doorbell_control = tmp; 3847 3848 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3849 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3850 3851 /* set the vmid for the queue */ 3852 mqd->cp_hqd_vmid = 0; 3853 3854 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3855 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3856 mqd->cp_hqd_persistent_state = tmp; 3857 3858 /* set MIN_IB_AVAIL_SIZE */ 3859 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3860 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3861 mqd->cp_hqd_ib_control = tmp; 3862 3863 /* set static priority for a compute queue/ring */ 3864 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3865 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3866 3867 mqd->cp_hqd_active = prop->hqd_active; 3868 3869 return 0; 3870 } 3871 3872 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 3873 { 3874 struct amdgpu_device *adev = ring->adev; 3875 struct v11_compute_mqd *mqd = ring->mqd_ptr; 3876 int j; 3877 3878 /* inactivate the queue */ 3879 if (amdgpu_sriov_vf(adev)) 3880 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3881 3882 /* disable wptr polling */ 3883 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3884 3885 /* write the EOP addr */ 3886 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3887 mqd->cp_hqd_eop_base_addr_lo); 3888 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3889 mqd->cp_hqd_eop_base_addr_hi); 3890 3891 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3892 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3893 mqd->cp_hqd_eop_control); 3894 3895 /* enable doorbell? */ 3896 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3897 mqd->cp_hqd_pq_doorbell_control); 3898 3899 /* disable the queue if it's active */ 3900 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3901 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3902 for (j = 0; j < adev->usec_timeout; j++) { 3903 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3904 break; 3905 udelay(1); 3906 } 3907 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3908 mqd->cp_hqd_dequeue_request); 3909 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3910 mqd->cp_hqd_pq_rptr); 3911 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3912 mqd->cp_hqd_pq_wptr_lo); 3913 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3914 mqd->cp_hqd_pq_wptr_hi); 3915 } 3916 3917 /* set the pointer to the MQD */ 3918 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3919 mqd->cp_mqd_base_addr_lo); 3920 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3921 mqd->cp_mqd_base_addr_hi); 3922 3923 /* set MQD vmid to 0 */ 3924 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3925 mqd->cp_mqd_control); 3926 3927 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3928 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3929 mqd->cp_hqd_pq_base_lo); 3930 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3931 mqd->cp_hqd_pq_base_hi); 3932 3933 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3934 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3935 mqd->cp_hqd_pq_control); 3936 3937 /* set the wb address whether it's enabled or not */ 3938 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3939 mqd->cp_hqd_pq_rptr_report_addr_lo); 3940 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3941 mqd->cp_hqd_pq_rptr_report_addr_hi); 3942 3943 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3944 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3945 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3946 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3947 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3948 3949 /* enable the doorbell if requested */ 3950 if (ring->use_doorbell) { 3951 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3952 (adev->doorbell_index.kiq * 2) << 2); 3953 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3954 (adev->doorbell_index.userqueue_end * 2) << 2); 3955 } 3956 3957 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3958 mqd->cp_hqd_pq_doorbell_control); 3959 3960 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3961 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3962 mqd->cp_hqd_pq_wptr_lo); 3963 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3964 mqd->cp_hqd_pq_wptr_hi); 3965 3966 /* set the vmid for the queue */ 3967 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3968 3969 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3970 mqd->cp_hqd_persistent_state); 3971 3972 /* activate the queue */ 3973 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3974 mqd->cp_hqd_active); 3975 3976 if (ring->use_doorbell) 3977 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3978 3979 return 0; 3980 } 3981 3982 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 3983 { 3984 struct amdgpu_device *adev = ring->adev; 3985 struct v11_compute_mqd *mqd = ring->mqd_ptr; 3986 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3987 3988 gfx_v11_0_kiq_setting(ring); 3989 3990 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3991 /* reset MQD to a clean status */ 3992 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3993 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3994 3995 /* reset ring buffer */ 3996 ring->wptr = 0; 3997 amdgpu_ring_clear_ring(ring); 3998 3999 mutex_lock(&adev->srbm_mutex); 4000 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4001 gfx_v11_0_kiq_init_register(ring); 4002 soc21_grbm_select(adev, 0, 0, 0, 0); 4003 mutex_unlock(&adev->srbm_mutex); 4004 } else { 4005 memset((void *)mqd, 0, sizeof(*mqd)); 4006 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4007 amdgpu_ring_clear_ring(ring); 4008 mutex_lock(&adev->srbm_mutex); 4009 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4010 amdgpu_ring_init_mqd(ring); 4011 gfx_v11_0_kiq_init_register(ring); 4012 soc21_grbm_select(adev, 0, 0, 0, 0); 4013 mutex_unlock(&adev->srbm_mutex); 4014 4015 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4016 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4017 } 4018 4019 return 0; 4020 } 4021 4022 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4023 { 4024 struct amdgpu_device *adev = ring->adev; 4025 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4026 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4027 4028 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4029 memset((void *)mqd, 0, sizeof(*mqd)); 4030 mutex_lock(&adev->srbm_mutex); 4031 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4032 amdgpu_ring_init_mqd(ring); 4033 soc21_grbm_select(adev, 0, 0, 0, 0); 4034 mutex_unlock(&adev->srbm_mutex); 4035 4036 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4037 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4038 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4039 /* reset MQD to a clean status */ 4040 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4041 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4042 4043 /* reset ring buffer */ 4044 ring->wptr = 0; 4045 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4046 amdgpu_ring_clear_ring(ring); 4047 } else { 4048 amdgpu_ring_clear_ring(ring); 4049 } 4050 4051 return 0; 4052 } 4053 4054 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4055 { 4056 struct amdgpu_ring *ring; 4057 int r; 4058 4059 ring = &adev->gfx.kiq.ring; 4060 4061 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4062 if (unlikely(r != 0)) 4063 return r; 4064 4065 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4066 if (unlikely(r != 0)) { 4067 amdgpu_bo_unreserve(ring->mqd_obj); 4068 return r; 4069 } 4070 4071 gfx_v11_0_kiq_init_queue(ring); 4072 amdgpu_bo_kunmap(ring->mqd_obj); 4073 ring->mqd_ptr = NULL; 4074 amdgpu_bo_unreserve(ring->mqd_obj); 4075 ring->sched.ready = true; 4076 return 0; 4077 } 4078 4079 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4080 { 4081 struct amdgpu_ring *ring = NULL; 4082 int r = 0, i; 4083 4084 if (!amdgpu_async_gfx_ring) 4085 gfx_v11_0_cp_compute_enable(adev, true); 4086 4087 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4088 ring = &adev->gfx.compute_ring[i]; 4089 4090 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4091 if (unlikely(r != 0)) 4092 goto done; 4093 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4094 if (!r) { 4095 r = gfx_v11_0_kcq_init_queue(ring); 4096 amdgpu_bo_kunmap(ring->mqd_obj); 4097 ring->mqd_ptr = NULL; 4098 } 4099 amdgpu_bo_unreserve(ring->mqd_obj); 4100 if (r) 4101 goto done; 4102 } 4103 4104 r = amdgpu_gfx_enable_kcq(adev); 4105 done: 4106 return r; 4107 } 4108 4109 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4110 { 4111 int r, i; 4112 struct amdgpu_ring *ring; 4113 4114 if (!(adev->flags & AMD_IS_APU)) 4115 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4116 4117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4118 /* legacy firmware loading */ 4119 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4120 if (r) 4121 return r; 4122 4123 if (adev->gfx.rs64_enable) 4124 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4125 else 4126 r = gfx_v11_0_cp_compute_load_microcode(adev); 4127 if (r) 4128 return r; 4129 } 4130 4131 gfx_v11_0_cp_set_doorbell_range(adev); 4132 4133 if (amdgpu_async_gfx_ring) { 4134 gfx_v11_0_cp_compute_enable(adev, true); 4135 gfx_v11_0_cp_gfx_enable(adev, true); 4136 } 4137 4138 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4139 r = amdgpu_mes_kiq_hw_init(adev); 4140 else 4141 r = gfx_v11_0_kiq_resume(adev); 4142 if (r) 4143 return r; 4144 4145 r = gfx_v11_0_kcq_resume(adev); 4146 if (r) 4147 return r; 4148 4149 if (!amdgpu_async_gfx_ring) { 4150 r = gfx_v11_0_cp_gfx_resume(adev); 4151 if (r) 4152 return r; 4153 } else { 4154 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4155 if (r) 4156 return r; 4157 } 4158 4159 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4160 ring = &adev->gfx.gfx_ring[i]; 4161 r = amdgpu_ring_test_helper(ring); 4162 if (r) 4163 return r; 4164 } 4165 4166 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4167 ring = &adev->gfx.compute_ring[i]; 4168 r = amdgpu_ring_test_helper(ring); 4169 if (r) 4170 return r; 4171 } 4172 4173 return 0; 4174 } 4175 4176 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4177 { 4178 gfx_v11_0_cp_gfx_enable(adev, enable); 4179 gfx_v11_0_cp_compute_enable(adev, enable); 4180 } 4181 4182 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4183 { 4184 int r; 4185 bool value; 4186 4187 r = adev->gfxhub.funcs->gart_enable(adev); 4188 if (r) 4189 return r; 4190 4191 adev->hdp.funcs->flush_hdp(adev, NULL); 4192 4193 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4194 false : true; 4195 4196 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4197 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 4198 4199 return 0; 4200 } 4201 4202 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4203 { 4204 u32 tmp; 4205 4206 /* select RS64 */ 4207 if (adev->gfx.rs64_enable) { 4208 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4209 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4210 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4211 4212 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4213 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4214 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4215 } 4216 4217 if (amdgpu_emu_mode == 1) 4218 msleep(100); 4219 } 4220 4221 static int get_gb_addr_config(struct amdgpu_device * adev) 4222 { 4223 u32 gb_addr_config; 4224 4225 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4226 if (gb_addr_config == 0) 4227 return -EINVAL; 4228 4229 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4230 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4231 4232 adev->gfx.config.gb_addr_config = gb_addr_config; 4233 4234 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4235 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4236 GB_ADDR_CONFIG, NUM_PIPES); 4237 4238 adev->gfx.config.max_tile_pipes = 4239 adev->gfx.config.gb_addr_config_fields.num_pipes; 4240 4241 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4242 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4243 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4244 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4245 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4246 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4247 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4248 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4249 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4250 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4251 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4252 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4253 4254 return 0; 4255 } 4256 4257 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4258 { 4259 uint32_t data; 4260 4261 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4262 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4263 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4264 4265 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4266 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4267 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4268 } 4269 4270 static int gfx_v11_0_hw_init(void *handle) 4271 { 4272 int r; 4273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4274 4275 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4276 if (adev->gfx.imu.funcs) { 4277 /* RLC autoload sequence 1: Program rlc ram */ 4278 if (adev->gfx.imu.funcs->program_rlc_ram) 4279 adev->gfx.imu.funcs->program_rlc_ram(adev); 4280 } 4281 /* rlc autoload firmware */ 4282 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4283 if (r) 4284 return r; 4285 } else { 4286 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4287 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4288 if (adev->gfx.imu.funcs->load_microcode) 4289 adev->gfx.imu.funcs->load_microcode(adev); 4290 if (adev->gfx.imu.funcs->setup_imu) 4291 adev->gfx.imu.funcs->setup_imu(adev); 4292 if (adev->gfx.imu.funcs->start_imu) 4293 adev->gfx.imu.funcs->start_imu(adev); 4294 } 4295 4296 /* disable gpa mode in backdoor loading */ 4297 gfx_v11_0_disable_gpa_mode(adev); 4298 } 4299 } 4300 4301 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4302 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4303 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4304 if (r) { 4305 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4306 return r; 4307 } 4308 } 4309 4310 adev->gfx.is_poweron = true; 4311 4312 if(get_gb_addr_config(adev)) 4313 DRM_WARN("Invalid gb_addr_config !\n"); 4314 4315 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4316 adev->gfx.rs64_enable) 4317 gfx_v11_0_config_gfx_rs64(adev); 4318 4319 r = gfx_v11_0_gfxhub_enable(adev); 4320 if (r) 4321 return r; 4322 4323 if (!amdgpu_emu_mode) 4324 gfx_v11_0_init_golden_registers(adev); 4325 4326 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4327 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4328 /** 4329 * For gfx 11, rlc firmware loading relies on smu firmware is 4330 * loaded firstly, so in direct type, it has to load smc ucode 4331 * here before rlc. 4332 */ 4333 if (!(adev->flags & AMD_IS_APU)) { 4334 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4335 if (r) 4336 return r; 4337 } 4338 } 4339 4340 gfx_v11_0_constants_init(adev); 4341 4342 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4343 gfx_v11_0_select_cp_fw_arch(adev); 4344 4345 if (adev->nbio.funcs->gc_doorbell_init) 4346 adev->nbio.funcs->gc_doorbell_init(adev); 4347 4348 r = gfx_v11_0_rlc_resume(adev); 4349 if (r) 4350 return r; 4351 4352 /* 4353 * init golden registers and rlc resume may override some registers, 4354 * reconfig them here 4355 */ 4356 gfx_v11_0_tcp_harvest(adev); 4357 4358 r = gfx_v11_0_cp_resume(adev); 4359 if (r) 4360 return r; 4361 4362 return r; 4363 } 4364 4365 #ifndef BRING_UP_DEBUG 4366 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev) 4367 { 4368 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4369 struct amdgpu_ring *kiq_ring = &kiq->ring; 4370 int i, r = 0; 4371 4372 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4373 return -EINVAL; 4374 4375 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 4376 adev->gfx.num_gfx_rings)) 4377 return -ENOMEM; 4378 4379 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4380 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 4381 PREEMPT_QUEUES, 0, 0); 4382 4383 if (adev->gfx.kiq.ring.sched.ready) 4384 r = amdgpu_ring_test_helper(kiq_ring); 4385 4386 return r; 4387 } 4388 #endif 4389 4390 static int gfx_v11_0_hw_fini(void *handle) 4391 { 4392 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4393 int r; 4394 4395 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4396 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4397 4398 if (!adev->no_hw_access) { 4399 #ifndef BRING_UP_DEBUG 4400 if (amdgpu_async_gfx_ring) { 4401 r = gfx_v11_0_kiq_disable_kgq(adev); 4402 if (r) 4403 DRM_ERROR("KGQ disable failed\n"); 4404 } 4405 #endif 4406 if (amdgpu_gfx_disable_kcq(adev)) 4407 DRM_ERROR("KCQ disable failed\n"); 4408 4409 amdgpu_mes_kiq_hw_fini(adev); 4410 } 4411 4412 if (amdgpu_sriov_vf(adev)) 4413 /* Remove the steps disabling CPG and clearing KIQ position, 4414 * so that CP could perform IDLE-SAVE during switch. Those 4415 * steps are necessary to avoid a DMAR error in gfx9 but it is 4416 * not reproduced on gfx11. 4417 */ 4418 return 0; 4419 4420 gfx_v11_0_cp_enable(adev, false); 4421 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4422 4423 adev->gfxhub.funcs->gart_disable(adev); 4424 4425 adev->gfx.is_poweron = false; 4426 4427 return 0; 4428 } 4429 4430 static int gfx_v11_0_suspend(void *handle) 4431 { 4432 return gfx_v11_0_hw_fini(handle); 4433 } 4434 4435 static int gfx_v11_0_resume(void *handle) 4436 { 4437 return gfx_v11_0_hw_init(handle); 4438 } 4439 4440 static bool gfx_v11_0_is_idle(void *handle) 4441 { 4442 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4443 4444 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4445 GRBM_STATUS, GUI_ACTIVE)) 4446 return false; 4447 else 4448 return true; 4449 } 4450 4451 static int gfx_v11_0_wait_for_idle(void *handle) 4452 { 4453 unsigned i; 4454 u32 tmp; 4455 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4456 4457 for (i = 0; i < adev->usec_timeout; i++) { 4458 /* read MC_STATUS */ 4459 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4460 GRBM_STATUS__GUI_ACTIVE_MASK; 4461 4462 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4463 return 0; 4464 udelay(1); 4465 } 4466 return -ETIMEDOUT; 4467 } 4468 4469 static int gfx_v11_0_soft_reset(void *handle) 4470 { 4471 u32 grbm_soft_reset = 0; 4472 u32 tmp; 4473 int i, j, k; 4474 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4475 4476 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4477 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4478 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4479 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4480 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4481 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4482 4483 gfx_v11_0_set_safe_mode(adev); 4484 4485 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4486 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4487 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4488 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4489 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4490 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4491 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4492 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4493 4494 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4495 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4496 } 4497 } 4498 } 4499 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4500 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4501 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4502 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4503 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4504 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4505 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4506 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4507 4508 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4509 } 4510 } 4511 } 4512 4513 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4514 4515 // Read CP_VMID_RESET register three times. 4516 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4517 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4518 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4519 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4520 4521 for (i = 0; i < adev->usec_timeout; i++) { 4522 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4523 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4524 break; 4525 udelay(1); 4526 } 4527 if (i >= adev->usec_timeout) { 4528 printk("Failed to wait all pipes clean\n"); 4529 return -EINVAL; 4530 } 4531 4532 /********** trigger soft reset ***********/ 4533 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4534 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4535 SOFT_RESET_CP, 1); 4536 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4537 SOFT_RESET_GFX, 1); 4538 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4539 SOFT_RESET_CPF, 1); 4540 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4541 SOFT_RESET_CPC, 1); 4542 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4543 SOFT_RESET_CPG, 1); 4544 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4545 /********** exit soft reset ***********/ 4546 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4547 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4548 SOFT_RESET_CP, 0); 4549 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4550 SOFT_RESET_GFX, 0); 4551 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4552 SOFT_RESET_CPF, 0); 4553 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4554 SOFT_RESET_CPC, 0); 4555 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4556 SOFT_RESET_CPG, 0); 4557 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4558 4559 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4560 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4561 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4562 4563 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4564 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4565 4566 for (i = 0; i < adev->usec_timeout; i++) { 4567 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4568 break; 4569 udelay(1); 4570 } 4571 if (i >= adev->usec_timeout) { 4572 printk("Failed to wait CP_VMID_RESET to 0\n"); 4573 return -EINVAL; 4574 } 4575 4576 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4577 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4578 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4579 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4580 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4581 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4582 4583 gfx_v11_0_unset_safe_mode(adev); 4584 4585 return gfx_v11_0_cp_resume(adev); 4586 } 4587 4588 static bool gfx_v11_0_check_soft_reset(void *handle) 4589 { 4590 int i, r; 4591 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4592 struct amdgpu_ring *ring; 4593 long tmo = msecs_to_jiffies(1000); 4594 4595 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4596 ring = &adev->gfx.gfx_ring[i]; 4597 r = amdgpu_ring_test_ib(ring, tmo); 4598 if (r) 4599 return true; 4600 } 4601 4602 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4603 ring = &adev->gfx.compute_ring[i]; 4604 r = amdgpu_ring_test_ib(ring, tmo); 4605 if (r) 4606 return true; 4607 } 4608 4609 return false; 4610 } 4611 4612 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4613 { 4614 uint64_t clock; 4615 4616 amdgpu_gfx_off_ctrl(adev, false); 4617 mutex_lock(&adev->gfx.gpu_clock_mutex); 4618 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) | 4619 ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL); 4620 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4621 amdgpu_gfx_off_ctrl(adev, true); 4622 return clock; 4623 } 4624 4625 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4626 uint32_t vmid, 4627 uint32_t gds_base, uint32_t gds_size, 4628 uint32_t gws_base, uint32_t gws_size, 4629 uint32_t oa_base, uint32_t oa_size) 4630 { 4631 struct amdgpu_device *adev = ring->adev; 4632 4633 /* GDS Base */ 4634 gfx_v11_0_write_data_to_reg(ring, 0, false, 4635 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4636 gds_base); 4637 4638 /* GDS Size */ 4639 gfx_v11_0_write_data_to_reg(ring, 0, false, 4640 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4641 gds_size); 4642 4643 /* GWS */ 4644 gfx_v11_0_write_data_to_reg(ring, 0, false, 4645 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4646 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4647 4648 /* OA */ 4649 gfx_v11_0_write_data_to_reg(ring, 0, false, 4650 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4651 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4652 } 4653 4654 static int gfx_v11_0_early_init(void *handle) 4655 { 4656 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4657 4658 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 4659 4660 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4661 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4662 AMDGPU_MAX_COMPUTE_RINGS); 4663 4664 gfx_v11_0_set_kiq_pm4_funcs(adev); 4665 gfx_v11_0_set_ring_funcs(adev); 4666 gfx_v11_0_set_irq_funcs(adev); 4667 gfx_v11_0_set_gds_init(adev); 4668 gfx_v11_0_set_rlc_funcs(adev); 4669 gfx_v11_0_set_mqd_funcs(adev); 4670 gfx_v11_0_set_imu_funcs(adev); 4671 4672 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4673 4674 return gfx_v11_0_init_microcode(adev); 4675 } 4676 4677 static int gfx_v11_0_ras_late_init(void *handle) 4678 { 4679 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4680 struct ras_common_if *gfx_common_if; 4681 int ret; 4682 4683 gfx_common_if = kzalloc(sizeof(struct ras_common_if), GFP_KERNEL); 4684 if (!gfx_common_if) 4685 return -ENOMEM; 4686 4687 gfx_common_if->block = AMDGPU_RAS_BLOCK__GFX; 4688 4689 ret = amdgpu_ras_feature_enable(adev, gfx_common_if, true); 4690 if (ret) 4691 dev_warn(adev->dev, "Failed to enable gfx11 ras feature\n"); 4692 4693 kfree(gfx_common_if); 4694 return 0; 4695 } 4696 4697 static int gfx_v11_0_late_init(void *handle) 4698 { 4699 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4700 int r; 4701 4702 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4703 if (r) 4704 return r; 4705 4706 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4707 if (r) 4708 return r; 4709 4710 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) { 4711 r = gfx_v11_0_ras_late_init(handle); 4712 if (r) 4713 return r; 4714 } 4715 4716 return 0; 4717 } 4718 4719 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4720 { 4721 uint32_t rlc_cntl; 4722 4723 /* if RLC is not enabled, do nothing */ 4724 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4725 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4726 } 4727 4728 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev) 4729 { 4730 uint32_t data; 4731 unsigned i; 4732 4733 data = RLC_SAFE_MODE__CMD_MASK; 4734 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4735 4736 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4737 4738 /* wait for RLC_SAFE_MODE */ 4739 for (i = 0; i < adev->usec_timeout; i++) { 4740 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4741 RLC_SAFE_MODE, CMD)) 4742 break; 4743 udelay(1); 4744 } 4745 } 4746 4747 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev) 4748 { 4749 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4750 } 4751 4752 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 4753 bool enable) 4754 { 4755 uint32_t def, data; 4756 4757 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4758 return; 4759 4760 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4761 4762 if (enable) 4763 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4764 else 4765 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4766 4767 if (def != data) 4768 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4769 } 4770 4771 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 4772 bool enable) 4773 { 4774 uint32_t def, data; 4775 4776 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4777 return; 4778 4779 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4780 4781 if (enable) 4782 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4783 else 4784 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4785 4786 if (def != data) 4787 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4788 } 4789 4790 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 4791 bool enable) 4792 { 4793 uint32_t def, data; 4794 4795 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4796 return; 4797 4798 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4799 4800 if (enable) 4801 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4802 else 4803 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4804 4805 if (def != data) 4806 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4807 } 4808 4809 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4810 bool enable) 4811 { 4812 uint32_t data, def; 4813 4814 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4815 return; 4816 4817 /* It is disabled by HW by default */ 4818 if (enable) { 4819 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4820 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4821 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4822 4823 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4824 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4825 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4826 4827 if (def != data) 4828 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4829 } 4830 } else { 4831 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4832 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4833 4834 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4835 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4836 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4837 4838 if (def != data) 4839 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4840 } 4841 } 4842 } 4843 4844 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4845 bool enable) 4846 { 4847 uint32_t def, data; 4848 4849 if (!(adev->cg_flags & 4850 (AMD_CG_SUPPORT_GFX_CGCG | 4851 AMD_CG_SUPPORT_GFX_CGLS | 4852 AMD_CG_SUPPORT_GFX_3D_CGCG | 4853 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4854 return; 4855 4856 if (enable) { 4857 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4858 4859 /* unset CGCG override */ 4860 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4861 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4862 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4863 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4864 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4865 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4866 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4867 4868 /* update CGCG override bits */ 4869 if (def != data) 4870 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4871 4872 /* enable cgcg FSM(0x0000363F) */ 4873 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4874 4875 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4876 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4877 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4878 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4879 } 4880 4881 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4882 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4883 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4884 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4885 } 4886 4887 if (def != data) 4888 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4889 4890 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4891 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4892 4893 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4894 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4895 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4896 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4897 } 4898 4899 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4900 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4901 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4902 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4903 } 4904 4905 if (def != data) 4906 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4907 4908 /* set IDLE_POLL_COUNT(0x00900100) */ 4909 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4910 4911 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4912 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4913 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4914 4915 if (def != data) 4916 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4917 4918 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4919 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4920 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4921 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4922 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4923 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4924 4925 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4926 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4927 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4928 4929 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4930 if (adev->sdma.num_instances > 1) { 4931 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4932 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4933 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4934 } 4935 } else { 4936 /* Program RLC_CGCG_CGLS_CTRL */ 4937 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4938 4939 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4940 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4941 4942 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4943 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4944 4945 if (def != data) 4946 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4947 4948 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4949 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4950 4951 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4952 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4953 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4954 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4955 4956 if (def != data) 4957 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4958 4959 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4960 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4961 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4962 4963 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4964 if (adev->sdma.num_instances > 1) { 4965 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4966 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4967 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4968 } 4969 } 4970 } 4971 4972 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4973 bool enable) 4974 { 4975 amdgpu_gfx_rlc_enter_safe_mode(adev); 4976 4977 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 4978 4979 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 4980 4981 gfx_v11_0_update_repeater_fgcg(adev, enable); 4982 4983 gfx_v11_0_update_sram_fgcg(adev, enable); 4984 4985 gfx_v11_0_update_perf_clk(adev, enable); 4986 4987 if (adev->cg_flags & 4988 (AMD_CG_SUPPORT_GFX_MGCG | 4989 AMD_CG_SUPPORT_GFX_CGLS | 4990 AMD_CG_SUPPORT_GFX_CGCG | 4991 AMD_CG_SUPPORT_GFX_3D_CGCG | 4992 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4993 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 4994 4995 amdgpu_gfx_rlc_exit_safe_mode(adev); 4996 4997 return 0; 4998 } 4999 5000 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 5001 { 5002 u32 reg, data; 5003 5004 amdgpu_gfx_off_ctrl(adev, false); 5005 5006 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5007 if (amdgpu_sriov_is_pp_one_vf(adev)) 5008 data = RREG32_NO_KIQ(reg); 5009 else 5010 data = RREG32(reg); 5011 5012 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5013 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5014 5015 if (amdgpu_sriov_is_pp_one_vf(adev)) 5016 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5017 else 5018 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5019 5020 amdgpu_gfx_off_ctrl(adev, true); 5021 } 5022 5023 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5024 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5025 .set_safe_mode = gfx_v11_0_set_safe_mode, 5026 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5027 .init = gfx_v11_0_rlc_init, 5028 .get_csb_size = gfx_v11_0_get_csb_size, 5029 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5030 .resume = gfx_v11_0_rlc_resume, 5031 .stop = gfx_v11_0_rlc_stop, 5032 .reset = gfx_v11_0_rlc_reset, 5033 .start = gfx_v11_0_rlc_start, 5034 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5035 }; 5036 5037 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5038 { 5039 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5040 5041 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5042 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5043 else 5044 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5045 5046 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5047 5048 // Program RLC_PG_DELAY3 for CGPG hysteresis 5049 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5050 switch (adev->ip_versions[GC_HWIP][0]) { 5051 case IP_VERSION(11, 0, 1): 5052 case IP_VERSION(11, 0, 4): 5053 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5054 break; 5055 default: 5056 break; 5057 } 5058 } 5059 } 5060 5061 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5062 { 5063 amdgpu_gfx_rlc_enter_safe_mode(adev); 5064 5065 gfx_v11_cntl_power_gating(adev, enable); 5066 5067 amdgpu_gfx_rlc_exit_safe_mode(adev); 5068 } 5069 5070 static int gfx_v11_0_set_powergating_state(void *handle, 5071 enum amd_powergating_state state) 5072 { 5073 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5074 bool enable = (state == AMD_PG_STATE_GATE); 5075 5076 if (amdgpu_sriov_vf(adev)) 5077 return 0; 5078 5079 switch (adev->ip_versions[GC_HWIP][0]) { 5080 case IP_VERSION(11, 0, 0): 5081 case IP_VERSION(11, 0, 2): 5082 case IP_VERSION(11, 0, 3): 5083 amdgpu_gfx_off_ctrl(adev, enable); 5084 break; 5085 case IP_VERSION(11, 0, 1): 5086 case IP_VERSION(11, 0, 4): 5087 gfx_v11_cntl_pg(adev, enable); 5088 amdgpu_gfx_off_ctrl(adev, enable); 5089 break; 5090 default: 5091 break; 5092 } 5093 5094 return 0; 5095 } 5096 5097 static int gfx_v11_0_set_clockgating_state(void *handle, 5098 enum amd_clockgating_state state) 5099 { 5100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5101 5102 if (amdgpu_sriov_vf(adev)) 5103 return 0; 5104 5105 switch (adev->ip_versions[GC_HWIP][0]) { 5106 case IP_VERSION(11, 0, 0): 5107 case IP_VERSION(11, 0, 1): 5108 case IP_VERSION(11, 0, 2): 5109 case IP_VERSION(11, 0, 3): 5110 case IP_VERSION(11, 0, 4): 5111 gfx_v11_0_update_gfx_clock_gating(adev, 5112 state == AMD_CG_STATE_GATE); 5113 break; 5114 default: 5115 break; 5116 } 5117 5118 return 0; 5119 } 5120 5121 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5122 { 5123 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5124 int data; 5125 5126 /* AMD_CG_SUPPORT_GFX_MGCG */ 5127 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5128 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5129 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5130 5131 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5132 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5133 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5134 5135 /* AMD_CG_SUPPORT_GFX_FGCG */ 5136 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5137 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5138 5139 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5140 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5141 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5142 5143 /* AMD_CG_SUPPORT_GFX_CGCG */ 5144 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5145 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5146 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5147 5148 /* AMD_CG_SUPPORT_GFX_CGLS */ 5149 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5150 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5151 5152 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5153 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5154 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5155 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5156 5157 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5158 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5159 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5160 } 5161 5162 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5163 { 5164 /* gfx11 is 32bit rptr*/ 5165 return *(uint32_t *)ring->rptr_cpu_addr; 5166 } 5167 5168 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5169 { 5170 struct amdgpu_device *adev = ring->adev; 5171 u64 wptr; 5172 5173 /* XXX check if swapping is necessary on BE */ 5174 if (ring->use_doorbell) { 5175 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5176 } else { 5177 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5178 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5179 } 5180 5181 return wptr; 5182 } 5183 5184 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5185 { 5186 struct amdgpu_device *adev = ring->adev; 5187 uint32_t *wptr_saved; 5188 uint32_t *is_queue_unmap; 5189 uint64_t aggregated_db_index; 5190 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 5191 uint64_t wptr_tmp; 5192 5193 if (ring->is_mes_queue) { 5194 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5195 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5196 sizeof(uint32_t)); 5197 aggregated_db_index = 5198 amdgpu_mes_get_aggregated_doorbell_index(adev, 5199 ring->hw_prio); 5200 5201 wptr_tmp = ring->wptr & ring->buf_mask; 5202 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5203 *wptr_saved = wptr_tmp; 5204 /* assume doorbell always being used by mes mapped queue */ 5205 if (*is_queue_unmap) { 5206 WDOORBELL64(aggregated_db_index, wptr_tmp); 5207 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5208 } else { 5209 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5210 5211 if (*is_queue_unmap) 5212 WDOORBELL64(aggregated_db_index, wptr_tmp); 5213 } 5214 } else { 5215 if (ring->use_doorbell) { 5216 /* XXX check if swapping is necessary on BE */ 5217 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5218 ring->wptr); 5219 WDOORBELL64(ring->doorbell_index, ring->wptr); 5220 } else { 5221 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5222 lower_32_bits(ring->wptr)); 5223 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5224 upper_32_bits(ring->wptr)); 5225 } 5226 } 5227 } 5228 5229 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5230 { 5231 /* gfx11 hardware is 32bit rptr */ 5232 return *(uint32_t *)ring->rptr_cpu_addr; 5233 } 5234 5235 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5236 { 5237 u64 wptr; 5238 5239 /* XXX check if swapping is necessary on BE */ 5240 if (ring->use_doorbell) 5241 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5242 else 5243 BUG(); 5244 return wptr; 5245 } 5246 5247 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5248 { 5249 struct amdgpu_device *adev = ring->adev; 5250 uint32_t *wptr_saved; 5251 uint32_t *is_queue_unmap; 5252 uint64_t aggregated_db_index; 5253 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 5254 uint64_t wptr_tmp; 5255 5256 if (ring->is_mes_queue) { 5257 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5258 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5259 sizeof(uint32_t)); 5260 aggregated_db_index = 5261 amdgpu_mes_get_aggregated_doorbell_index(adev, 5262 ring->hw_prio); 5263 5264 wptr_tmp = ring->wptr & ring->buf_mask; 5265 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5266 *wptr_saved = wptr_tmp; 5267 /* assume doorbell always used by mes mapped queue */ 5268 if (*is_queue_unmap) { 5269 WDOORBELL64(aggregated_db_index, wptr_tmp); 5270 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5271 } else { 5272 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5273 5274 if (*is_queue_unmap) 5275 WDOORBELL64(aggregated_db_index, wptr_tmp); 5276 } 5277 } else { 5278 /* XXX check if swapping is necessary on BE */ 5279 if (ring->use_doorbell) { 5280 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5281 ring->wptr); 5282 WDOORBELL64(ring->doorbell_index, ring->wptr); 5283 } else { 5284 BUG(); /* only DOORBELL method supported on gfx11 now */ 5285 } 5286 } 5287 } 5288 5289 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5290 { 5291 struct amdgpu_device *adev = ring->adev; 5292 u32 ref_and_mask, reg_mem_engine; 5293 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5294 5295 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5296 switch (ring->me) { 5297 case 1: 5298 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5299 break; 5300 case 2: 5301 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5302 break; 5303 default: 5304 return; 5305 } 5306 reg_mem_engine = 0; 5307 } else { 5308 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5309 reg_mem_engine = 1; /* pfp */ 5310 } 5311 5312 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5313 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5314 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5315 ref_and_mask, ref_and_mask, 0x20); 5316 } 5317 5318 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5319 struct amdgpu_job *job, 5320 struct amdgpu_ib *ib, 5321 uint32_t flags) 5322 { 5323 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5324 u32 header, control = 0; 5325 5326 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5327 5328 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5329 5330 control |= ib->length_dw | (vmid << 24); 5331 5332 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5333 control |= INDIRECT_BUFFER_PRE_ENB(1); 5334 5335 if (flags & AMDGPU_IB_PREEMPTED) 5336 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5337 5338 if (vmid) 5339 gfx_v11_0_ring_emit_de_meta(ring, 5340 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5341 } 5342 5343 if (ring->is_mes_queue) 5344 /* inherit vmid from mqd */ 5345 control |= 0x400000; 5346 5347 amdgpu_ring_write(ring, header); 5348 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5349 amdgpu_ring_write(ring, 5350 #ifdef __BIG_ENDIAN 5351 (2 << 0) | 5352 #endif 5353 lower_32_bits(ib->gpu_addr)); 5354 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5355 amdgpu_ring_write(ring, control); 5356 } 5357 5358 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5359 struct amdgpu_job *job, 5360 struct amdgpu_ib *ib, 5361 uint32_t flags) 5362 { 5363 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5364 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5365 5366 if (ring->is_mes_queue) 5367 /* inherit vmid from mqd */ 5368 control |= 0x40000000; 5369 5370 /* Currently, there is a high possibility to get wave ID mismatch 5371 * between ME and GDS, leading to a hw deadlock, because ME generates 5372 * different wave IDs than the GDS expects. This situation happens 5373 * randomly when at least 5 compute pipes use GDS ordered append. 5374 * The wave IDs generated by ME are also wrong after suspend/resume. 5375 * Those are probably bugs somewhere else in the kernel driver. 5376 * 5377 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5378 * GDS to 0 for this ring (me/pipe). 5379 */ 5380 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5381 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5382 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5383 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5384 } 5385 5386 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5387 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5388 amdgpu_ring_write(ring, 5389 #ifdef __BIG_ENDIAN 5390 (2 << 0) | 5391 #endif 5392 lower_32_bits(ib->gpu_addr)); 5393 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5394 amdgpu_ring_write(ring, control); 5395 } 5396 5397 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5398 u64 seq, unsigned flags) 5399 { 5400 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5401 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5402 5403 /* RELEASE_MEM - flush caches, send int */ 5404 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5405 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5406 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5407 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5408 PACKET3_RELEASE_MEM_GCR_GL2_US | 5409 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5410 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5411 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5412 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5413 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5414 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5415 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5416 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5417 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5418 5419 /* 5420 * the address should be Qword aligned if 64bit write, Dword 5421 * aligned if only send 32bit data low (discard data high) 5422 */ 5423 if (write64bit) 5424 BUG_ON(addr & 0x7); 5425 else 5426 BUG_ON(addr & 0x3); 5427 amdgpu_ring_write(ring, lower_32_bits(addr)); 5428 amdgpu_ring_write(ring, upper_32_bits(addr)); 5429 amdgpu_ring_write(ring, lower_32_bits(seq)); 5430 amdgpu_ring_write(ring, upper_32_bits(seq)); 5431 amdgpu_ring_write(ring, ring->is_mes_queue ? 5432 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5433 } 5434 5435 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5436 { 5437 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5438 uint32_t seq = ring->fence_drv.sync_seq; 5439 uint64_t addr = ring->fence_drv.gpu_addr; 5440 5441 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5442 upper_32_bits(addr), seq, 0xffffffff, 4); 5443 } 5444 5445 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5446 uint16_t pasid, uint32_t flush_type, 5447 bool all_hub, uint8_t dst_sel) 5448 { 5449 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5450 amdgpu_ring_write(ring, 5451 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5452 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5453 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5454 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5455 } 5456 5457 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5458 unsigned vmid, uint64_t pd_addr) 5459 { 5460 if (ring->is_mes_queue) 5461 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5462 else 5463 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5464 5465 /* compute doesn't have PFP */ 5466 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5467 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5468 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5469 amdgpu_ring_write(ring, 0x0); 5470 } 5471 } 5472 5473 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5474 u64 seq, unsigned int flags) 5475 { 5476 struct amdgpu_device *adev = ring->adev; 5477 5478 /* we only allocate 32bit for each seq wb address */ 5479 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5480 5481 /* write fence seq to the "addr" */ 5482 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5483 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5484 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5485 amdgpu_ring_write(ring, lower_32_bits(addr)); 5486 amdgpu_ring_write(ring, upper_32_bits(addr)); 5487 amdgpu_ring_write(ring, lower_32_bits(seq)); 5488 5489 if (flags & AMDGPU_FENCE_FLAG_INT) { 5490 /* set register to trigger INT */ 5491 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5492 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5493 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5494 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5495 amdgpu_ring_write(ring, 0); 5496 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5497 } 5498 } 5499 5500 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5501 uint32_t flags) 5502 { 5503 uint32_t dw2 = 0; 5504 5505 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5506 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5507 /* set load_global_config & load_global_uconfig */ 5508 dw2 |= 0x8001; 5509 /* set load_cs_sh_regs */ 5510 dw2 |= 0x01000000; 5511 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5512 dw2 |= 0x10002; 5513 } 5514 5515 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5516 amdgpu_ring_write(ring, dw2); 5517 amdgpu_ring_write(ring, 0); 5518 } 5519 5520 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5521 { 5522 unsigned ret; 5523 5524 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5525 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5526 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5527 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5528 ret = ring->wptr & ring->buf_mask; 5529 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5530 5531 return ret; 5532 } 5533 5534 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5535 { 5536 unsigned cur; 5537 BUG_ON(offset > ring->buf_mask); 5538 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5539 5540 cur = (ring->wptr - 1) & ring->buf_mask; 5541 if (likely(cur > offset)) 5542 ring->ring[offset] = cur - offset; 5543 else 5544 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5545 } 5546 5547 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5548 { 5549 int i, r = 0; 5550 struct amdgpu_device *adev = ring->adev; 5551 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5552 struct amdgpu_ring *kiq_ring = &kiq->ring; 5553 unsigned long flags; 5554 5555 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5556 return -EINVAL; 5557 5558 spin_lock_irqsave(&kiq->ring_lock, flags); 5559 5560 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5561 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5562 return -ENOMEM; 5563 } 5564 5565 /* assert preemption condition */ 5566 amdgpu_ring_set_preempt_cond_exec(ring, false); 5567 5568 /* assert IB preemption, emit the trailing fence */ 5569 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5570 ring->trail_fence_gpu_addr, 5571 ++ring->trail_seq); 5572 amdgpu_ring_commit(kiq_ring); 5573 5574 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5575 5576 /* poll the trailing fence */ 5577 for (i = 0; i < adev->usec_timeout; i++) { 5578 if (ring->trail_seq == 5579 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5580 break; 5581 udelay(1); 5582 } 5583 5584 if (i >= adev->usec_timeout) { 5585 r = -EINVAL; 5586 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5587 } 5588 5589 /* deassert preemption condition */ 5590 amdgpu_ring_set_preempt_cond_exec(ring, true); 5591 return r; 5592 } 5593 5594 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5595 { 5596 struct amdgpu_device *adev = ring->adev; 5597 struct v10_de_ib_state de_payload = {0}; 5598 uint64_t offset, gds_addr, de_payload_gpu_addr; 5599 void *de_payload_cpu_addr; 5600 int cnt; 5601 5602 if (ring->is_mes_queue) { 5603 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5604 gfx[0].gfx_meta_data) + 5605 offsetof(struct v10_gfx_meta_data, de_payload); 5606 de_payload_gpu_addr = 5607 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5608 de_payload_cpu_addr = 5609 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5610 5611 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5612 gfx[0].gds_backup) + 5613 offsetof(struct v10_gfx_meta_data, de_payload); 5614 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5615 } else { 5616 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5617 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5618 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5619 5620 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5621 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5622 PAGE_SIZE); 5623 } 5624 5625 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5626 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5627 5628 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5629 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5630 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5631 WRITE_DATA_DST_SEL(8) | 5632 WR_CONFIRM) | 5633 WRITE_DATA_CACHE_POLICY(0)); 5634 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5635 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5636 5637 if (resume) 5638 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5639 sizeof(de_payload) >> 2); 5640 else 5641 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5642 sizeof(de_payload) >> 2); 5643 } 5644 5645 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5646 bool secure) 5647 { 5648 uint32_t v = secure ? FRAME_TMZ : 0; 5649 5650 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5651 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5652 } 5653 5654 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5655 uint32_t reg_val_offs) 5656 { 5657 struct amdgpu_device *adev = ring->adev; 5658 5659 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5660 amdgpu_ring_write(ring, 0 | /* src: register*/ 5661 (5 << 8) | /* dst: memory */ 5662 (1 << 20)); /* write confirm */ 5663 amdgpu_ring_write(ring, reg); 5664 amdgpu_ring_write(ring, 0); 5665 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5666 reg_val_offs * 4)); 5667 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5668 reg_val_offs * 4)); 5669 } 5670 5671 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5672 uint32_t val) 5673 { 5674 uint32_t cmd = 0; 5675 5676 switch (ring->funcs->type) { 5677 case AMDGPU_RING_TYPE_GFX: 5678 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5679 break; 5680 case AMDGPU_RING_TYPE_KIQ: 5681 cmd = (1 << 16); /* no inc addr */ 5682 break; 5683 default: 5684 cmd = WR_CONFIRM; 5685 break; 5686 } 5687 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5688 amdgpu_ring_write(ring, cmd); 5689 amdgpu_ring_write(ring, reg); 5690 amdgpu_ring_write(ring, 0); 5691 amdgpu_ring_write(ring, val); 5692 } 5693 5694 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5695 uint32_t val, uint32_t mask) 5696 { 5697 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5698 } 5699 5700 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5701 uint32_t reg0, uint32_t reg1, 5702 uint32_t ref, uint32_t mask) 5703 { 5704 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5705 5706 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5707 ref, mask, 0x20); 5708 } 5709 5710 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5711 unsigned vmid) 5712 { 5713 struct amdgpu_device *adev = ring->adev; 5714 uint32_t value = 0; 5715 5716 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5717 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5718 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5719 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5720 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5721 } 5722 5723 static void 5724 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5725 uint32_t me, uint32_t pipe, 5726 enum amdgpu_interrupt_state state) 5727 { 5728 uint32_t cp_int_cntl, cp_int_cntl_reg; 5729 5730 if (!me) { 5731 switch (pipe) { 5732 case 0: 5733 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5734 break; 5735 case 1: 5736 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5737 break; 5738 default: 5739 DRM_DEBUG("invalid pipe %d\n", pipe); 5740 return; 5741 } 5742 } else { 5743 DRM_DEBUG("invalid me %d\n", me); 5744 return; 5745 } 5746 5747 switch (state) { 5748 case AMDGPU_IRQ_STATE_DISABLE: 5749 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5750 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5751 TIME_STAMP_INT_ENABLE, 0); 5752 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5753 GENERIC0_INT_ENABLE, 0); 5754 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5755 break; 5756 case AMDGPU_IRQ_STATE_ENABLE: 5757 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5758 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5759 TIME_STAMP_INT_ENABLE, 1); 5760 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5761 GENERIC0_INT_ENABLE, 1); 5762 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5763 break; 5764 default: 5765 break; 5766 } 5767 } 5768 5769 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5770 int me, int pipe, 5771 enum amdgpu_interrupt_state state) 5772 { 5773 u32 mec_int_cntl, mec_int_cntl_reg; 5774 5775 /* 5776 * amdgpu controls only the first MEC. That's why this function only 5777 * handles the setting of interrupts for this specific MEC. All other 5778 * pipes' interrupts are set by amdkfd. 5779 */ 5780 5781 if (me == 1) { 5782 switch (pipe) { 5783 case 0: 5784 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5785 break; 5786 case 1: 5787 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5788 break; 5789 case 2: 5790 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5791 break; 5792 case 3: 5793 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5794 break; 5795 default: 5796 DRM_DEBUG("invalid pipe %d\n", pipe); 5797 return; 5798 } 5799 } else { 5800 DRM_DEBUG("invalid me %d\n", me); 5801 return; 5802 } 5803 5804 switch (state) { 5805 case AMDGPU_IRQ_STATE_DISABLE: 5806 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5807 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5808 TIME_STAMP_INT_ENABLE, 0); 5809 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5810 GENERIC0_INT_ENABLE, 0); 5811 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5812 break; 5813 case AMDGPU_IRQ_STATE_ENABLE: 5814 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5815 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5816 TIME_STAMP_INT_ENABLE, 1); 5817 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5818 GENERIC0_INT_ENABLE, 1); 5819 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5820 break; 5821 default: 5822 break; 5823 } 5824 } 5825 5826 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5827 struct amdgpu_irq_src *src, 5828 unsigned type, 5829 enum amdgpu_interrupt_state state) 5830 { 5831 switch (type) { 5832 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5833 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 5834 break; 5835 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 5836 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 5837 break; 5838 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5839 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5840 break; 5841 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5842 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5843 break; 5844 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5845 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5846 break; 5847 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5848 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5849 break; 5850 default: 5851 break; 5852 } 5853 return 0; 5854 } 5855 5856 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 5857 struct amdgpu_irq_src *source, 5858 struct amdgpu_iv_entry *entry) 5859 { 5860 int i; 5861 u8 me_id, pipe_id, queue_id; 5862 struct amdgpu_ring *ring; 5863 uint32_t mes_queue_id = entry->src_data[0]; 5864 5865 DRM_DEBUG("IH: CP EOP\n"); 5866 5867 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 5868 struct amdgpu_mes_queue *queue; 5869 5870 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 5871 5872 spin_lock(&adev->mes.queue_id_lock); 5873 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 5874 if (queue) { 5875 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 5876 amdgpu_fence_process(queue->ring); 5877 } 5878 spin_unlock(&adev->mes.queue_id_lock); 5879 } else { 5880 me_id = (entry->ring_id & 0x0c) >> 2; 5881 pipe_id = (entry->ring_id & 0x03) >> 0; 5882 queue_id = (entry->ring_id & 0x70) >> 4; 5883 5884 switch (me_id) { 5885 case 0: 5886 if (pipe_id == 0) 5887 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5888 else 5889 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5890 break; 5891 case 1: 5892 case 2: 5893 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5894 ring = &adev->gfx.compute_ring[i]; 5895 /* Per-queue interrupt is supported for MEC starting from VI. 5896 * The interrupt can only be enabled/disabled per pipe instead 5897 * of per queue. 5898 */ 5899 if ((ring->me == me_id) && 5900 (ring->pipe == pipe_id) && 5901 (ring->queue == queue_id)) 5902 amdgpu_fence_process(ring); 5903 } 5904 break; 5905 } 5906 } 5907 5908 return 0; 5909 } 5910 5911 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5912 struct amdgpu_irq_src *source, 5913 unsigned type, 5914 enum amdgpu_interrupt_state state) 5915 { 5916 switch (state) { 5917 case AMDGPU_IRQ_STATE_DISABLE: 5918 case AMDGPU_IRQ_STATE_ENABLE: 5919 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5920 PRIV_REG_INT_ENABLE, 5921 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5922 break; 5923 default: 5924 break; 5925 } 5926 5927 return 0; 5928 } 5929 5930 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5931 struct amdgpu_irq_src *source, 5932 unsigned type, 5933 enum amdgpu_interrupt_state state) 5934 { 5935 switch (state) { 5936 case AMDGPU_IRQ_STATE_DISABLE: 5937 case AMDGPU_IRQ_STATE_ENABLE: 5938 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5939 PRIV_INSTR_INT_ENABLE, 5940 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5941 break; 5942 default: 5943 break; 5944 } 5945 5946 return 0; 5947 } 5948 5949 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 5950 struct amdgpu_iv_entry *entry) 5951 { 5952 u8 me_id, pipe_id, queue_id; 5953 struct amdgpu_ring *ring; 5954 int i; 5955 5956 me_id = (entry->ring_id & 0x0c) >> 2; 5957 pipe_id = (entry->ring_id & 0x03) >> 0; 5958 queue_id = (entry->ring_id & 0x70) >> 4; 5959 5960 switch (me_id) { 5961 case 0: 5962 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5963 ring = &adev->gfx.gfx_ring[i]; 5964 /* we only enabled 1 gfx queue per pipe for now */ 5965 if (ring->me == me_id && ring->pipe == pipe_id) 5966 drm_sched_fault(&ring->sched); 5967 } 5968 break; 5969 case 1: 5970 case 2: 5971 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5972 ring = &adev->gfx.compute_ring[i]; 5973 if (ring->me == me_id && ring->pipe == pipe_id && 5974 ring->queue == queue_id) 5975 drm_sched_fault(&ring->sched); 5976 } 5977 break; 5978 default: 5979 BUG(); 5980 break; 5981 } 5982 } 5983 5984 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 5985 struct amdgpu_irq_src *source, 5986 struct amdgpu_iv_entry *entry) 5987 { 5988 DRM_ERROR("Illegal register access in command stream\n"); 5989 gfx_v11_0_handle_priv_fault(adev, entry); 5990 return 0; 5991 } 5992 5993 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 5994 struct amdgpu_irq_src *source, 5995 struct amdgpu_iv_entry *entry) 5996 { 5997 DRM_ERROR("Illegal instruction in command stream\n"); 5998 gfx_v11_0_handle_priv_fault(adev, entry); 5999 return 0; 6000 } 6001 6002 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6003 struct amdgpu_irq_src *source, 6004 struct amdgpu_iv_entry *entry) 6005 { 6006 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6007 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6008 6009 return 0; 6010 } 6011 6012 #if 0 6013 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6014 struct amdgpu_irq_src *src, 6015 unsigned int type, 6016 enum amdgpu_interrupt_state state) 6017 { 6018 uint32_t tmp, target; 6019 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 6020 6021 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6022 target += ring->pipe; 6023 6024 switch (type) { 6025 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6026 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6027 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6028 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6029 GENERIC2_INT_ENABLE, 0); 6030 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6031 6032 tmp = RREG32_SOC15_IP(GC, target); 6033 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6034 GENERIC2_INT_ENABLE, 0); 6035 WREG32_SOC15_IP(GC, target, tmp); 6036 } else { 6037 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6038 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6039 GENERIC2_INT_ENABLE, 1); 6040 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6041 6042 tmp = RREG32_SOC15_IP(GC, target); 6043 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6044 GENERIC2_INT_ENABLE, 1); 6045 WREG32_SOC15_IP(GC, target, tmp); 6046 } 6047 break; 6048 default: 6049 BUG(); /* kiq only support GENERIC2_INT now */ 6050 break; 6051 } 6052 return 0; 6053 } 6054 #endif 6055 6056 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6057 { 6058 const unsigned int gcr_cntl = 6059 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6060 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6061 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6062 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6063 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6064 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6065 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6066 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6067 6068 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6069 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6070 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6071 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6072 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6073 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6074 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6075 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6076 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6077 } 6078 6079 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6080 .name = "gfx_v11_0", 6081 .early_init = gfx_v11_0_early_init, 6082 .late_init = gfx_v11_0_late_init, 6083 .sw_init = gfx_v11_0_sw_init, 6084 .sw_fini = gfx_v11_0_sw_fini, 6085 .hw_init = gfx_v11_0_hw_init, 6086 .hw_fini = gfx_v11_0_hw_fini, 6087 .suspend = gfx_v11_0_suspend, 6088 .resume = gfx_v11_0_resume, 6089 .is_idle = gfx_v11_0_is_idle, 6090 .wait_for_idle = gfx_v11_0_wait_for_idle, 6091 .soft_reset = gfx_v11_0_soft_reset, 6092 .check_soft_reset = gfx_v11_0_check_soft_reset, 6093 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6094 .set_powergating_state = gfx_v11_0_set_powergating_state, 6095 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6096 }; 6097 6098 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6099 .type = AMDGPU_RING_TYPE_GFX, 6100 .align_mask = 0xff, 6101 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6102 .support_64bit_ptrs = true, 6103 .secure_submission_supported = true, 6104 .vmhub = AMDGPU_GFXHUB_0, 6105 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6106 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6107 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6108 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6109 5 + /* COND_EXEC */ 6110 7 + /* PIPELINE_SYNC */ 6111 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6112 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6113 2 + /* VM_FLUSH */ 6114 8 + /* FENCE for VM_FLUSH */ 6115 20 + /* GDS switch */ 6116 5 + /* COND_EXEC */ 6117 7 + /* HDP_flush */ 6118 4 + /* VGT_flush */ 6119 31 + /* DE_META */ 6120 3 + /* CNTX_CTRL */ 6121 5 + /* HDP_INVL */ 6122 8 + 8 + /* FENCE x2 */ 6123 8, /* gfx_v11_0_emit_mem_sync */ 6124 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6125 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6126 .emit_fence = gfx_v11_0_ring_emit_fence, 6127 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6128 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6129 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6130 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6131 .test_ring = gfx_v11_0_ring_test_ring, 6132 .test_ib = gfx_v11_0_ring_test_ib, 6133 .insert_nop = amdgpu_ring_insert_nop, 6134 .pad_ib = amdgpu_ring_generic_pad_ib, 6135 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6136 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6137 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6138 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6139 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6140 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6141 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6142 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6143 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6144 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6145 }; 6146 6147 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6148 .type = AMDGPU_RING_TYPE_COMPUTE, 6149 .align_mask = 0xff, 6150 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6151 .support_64bit_ptrs = true, 6152 .vmhub = AMDGPU_GFXHUB_0, 6153 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6154 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6155 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6156 .emit_frame_size = 6157 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6158 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6159 5 + /* hdp invalidate */ 6160 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6161 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6162 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6163 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6164 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6165 8, /* gfx_v11_0_emit_mem_sync */ 6166 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6167 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6168 .emit_fence = gfx_v11_0_ring_emit_fence, 6169 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6170 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6171 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6172 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6173 .test_ring = gfx_v11_0_ring_test_ring, 6174 .test_ib = gfx_v11_0_ring_test_ib, 6175 .insert_nop = amdgpu_ring_insert_nop, 6176 .pad_ib = amdgpu_ring_generic_pad_ib, 6177 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6178 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6179 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6180 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6181 }; 6182 6183 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6184 .type = AMDGPU_RING_TYPE_KIQ, 6185 .align_mask = 0xff, 6186 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6187 .support_64bit_ptrs = true, 6188 .vmhub = AMDGPU_GFXHUB_0, 6189 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6190 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6191 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6192 .emit_frame_size = 6193 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6194 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6195 5 + /*hdp invalidate */ 6196 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6197 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6198 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6199 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6200 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6201 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6202 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6203 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6204 .test_ring = gfx_v11_0_ring_test_ring, 6205 .test_ib = gfx_v11_0_ring_test_ib, 6206 .insert_nop = amdgpu_ring_insert_nop, 6207 .pad_ib = amdgpu_ring_generic_pad_ib, 6208 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6209 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6210 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6211 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6212 }; 6213 6214 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6215 { 6216 int i; 6217 6218 adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6219 6220 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6221 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6222 6223 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6224 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6225 } 6226 6227 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6228 .set = gfx_v11_0_set_eop_interrupt_state, 6229 .process = gfx_v11_0_eop_irq, 6230 }; 6231 6232 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6233 .set = gfx_v11_0_set_priv_reg_fault_state, 6234 .process = gfx_v11_0_priv_reg_irq, 6235 }; 6236 6237 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6238 .set = gfx_v11_0_set_priv_inst_fault_state, 6239 .process = gfx_v11_0_priv_inst_irq, 6240 }; 6241 6242 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 6243 .process = gfx_v11_0_rlc_gc_fed_irq, 6244 }; 6245 6246 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6247 { 6248 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6249 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6250 6251 adev->gfx.priv_reg_irq.num_types = 1; 6252 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6253 6254 adev->gfx.priv_inst_irq.num_types = 1; 6255 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6256 6257 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 6258 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 6259 } 6260 6261 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6262 { 6263 if (adev->flags & AMD_IS_APU) 6264 adev->gfx.imu.mode = MISSION_MODE; 6265 else 6266 adev->gfx.imu.mode = DEBUG_MODE; 6267 6268 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6269 } 6270 6271 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6272 { 6273 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6274 } 6275 6276 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6277 { 6278 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6279 adev->gfx.config.max_sh_per_se * 6280 adev->gfx.config.max_shader_engines; 6281 6282 adev->gds.gds_size = 0x1000; 6283 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6284 adev->gds.gws_size = 64; 6285 adev->gds.oa_size = 16; 6286 } 6287 6288 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6289 { 6290 /* set gfx eng mqd */ 6291 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6292 sizeof(struct v11_gfx_mqd); 6293 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6294 gfx_v11_0_gfx_mqd_init; 6295 /* set compute eng mqd */ 6296 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6297 sizeof(struct v11_compute_mqd); 6298 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6299 gfx_v11_0_compute_mqd_init; 6300 } 6301 6302 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6303 u32 bitmap) 6304 { 6305 u32 data; 6306 6307 if (!bitmap) 6308 return; 6309 6310 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6311 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6312 6313 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6314 } 6315 6316 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6317 { 6318 u32 data, wgp_bitmask; 6319 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6320 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6321 6322 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6323 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6324 6325 wgp_bitmask = 6326 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6327 6328 return (~data) & wgp_bitmask; 6329 } 6330 6331 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6332 { 6333 u32 wgp_idx, wgp_active_bitmap; 6334 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6335 6336 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6337 cu_active_bitmap = 0; 6338 6339 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6340 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6341 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6342 if (wgp_active_bitmap & (1 << wgp_idx)) 6343 cu_active_bitmap |= cu_bitmap_per_wgp; 6344 } 6345 6346 return cu_active_bitmap; 6347 } 6348 6349 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6350 struct amdgpu_cu_info *cu_info) 6351 { 6352 int i, j, k, counter, active_cu_number = 0; 6353 u32 mask, bitmap; 6354 unsigned disable_masks[8 * 2]; 6355 6356 if (!adev || !cu_info) 6357 return -EINVAL; 6358 6359 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6360 6361 mutex_lock(&adev->grbm_idx_mutex); 6362 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6363 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6364 mask = 1; 6365 counter = 0; 6366 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 6367 if (i < 8 && j < 2) 6368 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6369 adev, disable_masks[i * 2 + j]); 6370 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6371 6372 /** 6373 * GFX11 could support more than 4 SEs, while the bitmap 6374 * in cu_info struct is 4x4 and ioctl interface struct 6375 * drm_amdgpu_info_device should keep stable. 6376 * So we use last two columns of bitmap to store cu mask for 6377 * SEs 4 to 7, the layout of the bitmap is as below: 6378 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6379 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6380 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6381 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6382 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6383 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6384 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6385 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6386 */ 6387 cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; 6388 6389 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6390 if (bitmap & mask) 6391 counter++; 6392 6393 mask <<= 1; 6394 } 6395 active_cu_number += counter; 6396 } 6397 } 6398 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6399 mutex_unlock(&adev->grbm_idx_mutex); 6400 6401 cu_info->number = active_cu_number; 6402 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6403 6404 return 0; 6405 } 6406 6407 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6408 { 6409 .type = AMD_IP_BLOCK_TYPE_GFX, 6410 .major = 11, 6411 .minor = 0, 6412 .rev = 0, 6413 .funcs = &gfx_v11_0_ip_funcs, 6414 }; 6415