1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 52 #define GFX11_NUM_GFX_RINGS 1 53 #define GFX11_MEC_HPD_SIZE 2048 54 55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 56 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 57 58 #define regCGTT_WD_CLK_CTRL 0x5086 59 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 60 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 62 63 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 76 77 static const struct soc15_reg_golden golden_settings_gc_11_0[] = 78 { 79 /* Pending on emulation bring up */ 80 }; 81 82 static const struct soc15_reg_golden golden_settings_gc_11_0_0[] = 83 { 84 /* Pending on emulation bring up */ 85 }; 86 87 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_11_0[] = 88 { 89 /* Pending on emulation bring up */ 90 }; 91 92 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 93 { 94 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 103 }; 104 105 #define DEFAULT_SH_MEM_CONFIG \ 106 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 107 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 108 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 109 110 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 111 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 112 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 113 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 114 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 115 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 116 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 117 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 118 struct amdgpu_cu_info *cu_info); 119 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 120 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 121 u32 sh_num, u32 instance); 122 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 123 124 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 125 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 126 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 127 uint32_t val); 128 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 129 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 130 uint16_t pasid, uint32_t flush_type, 131 bool all_hub, uint8_t dst_sel); 132 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev); 133 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev); 134 135 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 136 { 137 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 138 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 139 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 140 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 141 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 142 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 143 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 144 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 145 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 146 } 147 148 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 149 struct amdgpu_ring *ring) 150 { 151 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 152 uint64_t wptr_addr = ring->wptr_gpu_addr; 153 uint32_t me = 0, eng_sel = 0; 154 155 switch (ring->funcs->type) { 156 case AMDGPU_RING_TYPE_COMPUTE: 157 me = 1; 158 eng_sel = 0; 159 break; 160 case AMDGPU_RING_TYPE_GFX: 161 me = 0; 162 eng_sel = 4; 163 break; 164 case AMDGPU_RING_TYPE_MES: 165 me = 2; 166 eng_sel = 5; 167 break; 168 default: 169 WARN_ON(1); 170 } 171 172 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 173 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 174 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 175 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 176 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 177 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 178 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 179 PACKET3_MAP_QUEUES_ME((me)) | 180 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 181 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 182 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 183 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 184 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 185 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 186 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 187 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 188 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 189 } 190 191 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 192 struct amdgpu_ring *ring, 193 enum amdgpu_unmap_queues_action action, 194 u64 gpu_addr, u64 seq) 195 { 196 struct amdgpu_device *adev = kiq_ring->adev; 197 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 198 199 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { 200 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 201 return; 202 } 203 204 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 205 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 206 PACKET3_UNMAP_QUEUES_ACTION(action) | 207 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 208 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 209 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 210 amdgpu_ring_write(kiq_ring, 211 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 212 213 if (action == PREEMPT_QUEUES_NO_UNMAP) { 214 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 215 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 216 amdgpu_ring_write(kiq_ring, seq); 217 } else { 218 amdgpu_ring_write(kiq_ring, 0); 219 amdgpu_ring_write(kiq_ring, 0); 220 amdgpu_ring_write(kiq_ring, 0); 221 } 222 } 223 224 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 225 struct amdgpu_ring *ring, 226 u64 addr, 227 u64 seq) 228 { 229 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 230 231 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 232 amdgpu_ring_write(kiq_ring, 233 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 234 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 235 PACKET3_QUERY_STATUS_COMMAND(2)); 236 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 237 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 238 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 239 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 240 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 241 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 242 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 243 } 244 245 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 246 uint16_t pasid, uint32_t flush_type, 247 bool all_hub) 248 { 249 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 250 } 251 252 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 253 .kiq_set_resources = gfx11_kiq_set_resources, 254 .kiq_map_queues = gfx11_kiq_map_queues, 255 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 256 .kiq_query_status = gfx11_kiq_query_status, 257 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 258 .set_resources_size = 8, 259 .map_queues_size = 7, 260 .unmap_queues_size = 6, 261 .query_status_size = 7, 262 .invalidate_tlbs_size = 2, 263 }; 264 265 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 266 { 267 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; 268 } 269 270 static void gfx_v11_0_init_spm_golden_registers(struct amdgpu_device *adev) 271 { 272 switch (adev->ip_versions[GC_HWIP][0]) { 273 case IP_VERSION(11, 0, 0): 274 soc15_program_register_sequence(adev, 275 golden_settings_gc_rlc_spm_11_0, 276 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_11_0)); 277 break; 278 default: 279 break; 280 } 281 } 282 283 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 284 { 285 switch (adev->ip_versions[GC_HWIP][0]) { 286 case IP_VERSION(11, 0, 0): 287 soc15_program_register_sequence(adev, 288 golden_settings_gc_11_0, 289 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 290 soc15_program_register_sequence(adev, 291 golden_settings_gc_11_0_0, 292 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_0)); 293 break; 294 case IP_VERSION(11, 0, 1): 295 soc15_program_register_sequence(adev, 296 golden_settings_gc_11_0, 297 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 298 soc15_program_register_sequence(adev, 299 golden_settings_gc_11_0_1, 300 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 301 break; 302 default: 303 break; 304 } 305 gfx_v11_0_init_spm_golden_registers(adev); 306 } 307 308 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 309 bool wc, uint32_t reg, uint32_t val) 310 { 311 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 312 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 313 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 314 amdgpu_ring_write(ring, reg); 315 amdgpu_ring_write(ring, 0); 316 amdgpu_ring_write(ring, val); 317 } 318 319 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 320 int mem_space, int opt, uint32_t addr0, 321 uint32_t addr1, uint32_t ref, uint32_t mask, 322 uint32_t inv) 323 { 324 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 325 amdgpu_ring_write(ring, 326 /* memory (1) or register (0) */ 327 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 328 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 329 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 330 WAIT_REG_MEM_ENGINE(eng_sel))); 331 332 if (mem_space) 333 BUG_ON(addr0 & 0x3); /* Dword align */ 334 amdgpu_ring_write(ring, addr0); 335 amdgpu_ring_write(ring, addr1); 336 amdgpu_ring_write(ring, ref); 337 amdgpu_ring_write(ring, mask); 338 amdgpu_ring_write(ring, inv); /* poll interval */ 339 } 340 341 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 342 { 343 struct amdgpu_device *adev = ring->adev; 344 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 345 uint32_t tmp = 0; 346 unsigned i; 347 int r; 348 349 WREG32(scratch, 0xCAFEDEAD); 350 r = amdgpu_ring_alloc(ring, 5); 351 if (r) { 352 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 353 ring->idx, r); 354 return r; 355 } 356 357 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 358 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 359 } else { 360 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 361 amdgpu_ring_write(ring, scratch - 362 PACKET3_SET_UCONFIG_REG_START); 363 amdgpu_ring_write(ring, 0xDEADBEEF); 364 } 365 amdgpu_ring_commit(ring); 366 367 for (i = 0; i < adev->usec_timeout; i++) { 368 tmp = RREG32(scratch); 369 if (tmp == 0xDEADBEEF) 370 break; 371 if (amdgpu_emu_mode == 1) 372 msleep(1); 373 else 374 udelay(1); 375 } 376 377 if (i >= adev->usec_timeout) 378 r = -ETIMEDOUT; 379 return r; 380 } 381 382 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 383 { 384 struct amdgpu_device *adev = ring->adev; 385 struct amdgpu_ib ib; 386 struct dma_fence *f = NULL; 387 unsigned index; 388 uint64_t gpu_addr; 389 volatile uint32_t *cpu_ptr; 390 long r; 391 392 /* MES KIQ fw hasn't indirect buffer support for now */ 393 if (adev->enable_mes_kiq && 394 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 395 return 0; 396 397 memset(&ib, 0, sizeof(ib)); 398 399 if (ring->is_mes_queue) { 400 uint32_t padding, offset; 401 402 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 403 padding = amdgpu_mes_ctx_get_offs(ring, 404 AMDGPU_MES_CTX_PADDING_OFFS); 405 406 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 407 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 408 409 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 410 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 411 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 412 } else { 413 r = amdgpu_device_wb_get(adev, &index); 414 if (r) 415 return r; 416 417 gpu_addr = adev->wb.gpu_addr + (index * 4); 418 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 419 cpu_ptr = &adev->wb.wb[index]; 420 421 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 422 if (r) { 423 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 424 goto err1; 425 } 426 } 427 428 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 429 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 430 ib.ptr[2] = lower_32_bits(gpu_addr); 431 ib.ptr[3] = upper_32_bits(gpu_addr); 432 ib.ptr[4] = 0xDEADBEEF; 433 ib.length_dw = 5; 434 435 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 436 if (r) 437 goto err2; 438 439 r = dma_fence_wait_timeout(f, false, timeout); 440 if (r == 0) { 441 r = -ETIMEDOUT; 442 goto err2; 443 } else if (r < 0) { 444 goto err2; 445 } 446 447 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 448 r = 0; 449 else 450 r = -EINVAL; 451 err2: 452 if (!ring->is_mes_queue) 453 amdgpu_ib_free(adev, &ib, NULL); 454 dma_fence_put(f); 455 err1: 456 if (!ring->is_mes_queue) 457 amdgpu_device_wb_free(adev, index); 458 return r; 459 } 460 461 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 462 { 463 release_firmware(adev->gfx.pfp_fw); 464 adev->gfx.pfp_fw = NULL; 465 release_firmware(adev->gfx.me_fw); 466 adev->gfx.me_fw = NULL; 467 release_firmware(adev->gfx.rlc_fw); 468 adev->gfx.rlc_fw = NULL; 469 release_firmware(adev->gfx.mec_fw); 470 adev->gfx.mec_fw = NULL; 471 472 kfree(adev->gfx.rlc.register_list_format); 473 } 474 475 static void gfx_v11_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 476 { 477 const struct rlc_firmware_header_v2_1 *rlc_hdr; 478 479 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 480 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 481 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 482 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 483 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 484 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 485 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 486 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 487 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 488 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 489 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 490 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 491 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 492 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 493 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 494 } 495 496 static void gfx_v11_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 497 { 498 const struct rlc_firmware_header_v2_2 *rlc_hdr; 499 500 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 501 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 502 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 503 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 504 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 505 } 506 507 static void gfx_v11_0_init_rlcp_rlcv_microcode(struct amdgpu_device *adev) 508 { 509 const struct rlc_firmware_header_v2_3 *rlc_hdr; 510 511 rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 512 adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes); 513 adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); 514 adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes); 515 adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); 516 } 517 518 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 519 { 520 char fw_name[40]; 521 char ucode_prefix[30]; 522 int err; 523 struct amdgpu_firmware_info *info = NULL; 524 const struct common_firmware_header *header = NULL; 525 const struct gfx_firmware_header_v1_0 *cp_hdr; 526 const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0; 527 const struct rlc_firmware_header_v2_0 *rlc_hdr; 528 unsigned int *tmp = NULL; 529 unsigned int i = 0; 530 uint16_t version_major; 531 uint16_t version_minor; 532 533 DRM_DEBUG("\n"); 534 535 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 536 537 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 538 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 539 if (err) 540 goto out; 541 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 542 if (err) 543 goto out; 544 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 545 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 546 (union amdgpu_firmware_header *) 547 adev->gfx.pfp_fw->data, 2, 0); 548 if (adev->gfx.rs64_enable) { 549 dev_info(adev->dev, "CP RS64 enable\n"); 550 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; 551 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 552 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 553 554 } else { 555 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 556 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 557 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 558 } 559 560 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 561 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 562 if (err) 563 goto out; 564 err = amdgpu_ucode_validate(adev->gfx.me_fw); 565 if (err) 566 goto out; 567 if (adev->gfx.rs64_enable) { 568 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; 569 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 570 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 571 572 } else { 573 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 574 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 575 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 576 } 577 578 if (!amdgpu_sriov_vf(adev)) { 579 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 580 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 581 if (err) 582 goto out; 583 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 584 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 585 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 586 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 587 588 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 589 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 590 adev->gfx.rlc.save_and_restore_offset = 591 le32_to_cpu(rlc_hdr->save_and_restore_offset); 592 adev->gfx.rlc.clear_state_descriptor_offset = 593 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 594 adev->gfx.rlc.avail_scratch_ram_locations = 595 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 596 adev->gfx.rlc.reg_restore_list_size = 597 le32_to_cpu(rlc_hdr->reg_restore_list_size); 598 adev->gfx.rlc.reg_list_format_start = 599 le32_to_cpu(rlc_hdr->reg_list_format_start); 600 adev->gfx.rlc.reg_list_format_separate_start = 601 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 602 adev->gfx.rlc.starting_offsets_start = 603 le32_to_cpu(rlc_hdr->starting_offsets_start); 604 adev->gfx.rlc.reg_list_format_size_bytes = 605 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 606 adev->gfx.rlc.reg_list_size_bytes = 607 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 608 adev->gfx.rlc.register_list_format = 609 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 610 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 611 if (!adev->gfx.rlc.register_list_format) { 612 err = -ENOMEM; 613 goto out; 614 } 615 616 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 617 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 618 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 619 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 620 621 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 622 623 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 624 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 625 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 626 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 627 628 if (version_major == 2) { 629 if (version_minor >= 1) 630 gfx_v11_0_init_rlc_ext_microcode(adev); 631 if (version_minor >= 2) 632 gfx_v11_0_init_rlc_iram_dram_microcode(adev); 633 if (version_minor == 3) 634 gfx_v11_0_init_rlcp_rlcv_microcode(adev); 635 } 636 } 637 638 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 639 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 640 if (err) 641 goto out; 642 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 643 if (err) 644 goto out; 645 if (adev->gfx.rs64_enable) { 646 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 647 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 648 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 649 650 } else { 651 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 652 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 653 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 654 } 655 656 /* only one MEC for gfx 11.0.0. */ 657 adev->gfx.mec2_fw = NULL; 658 659 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 660 if (adev->gfx.rs64_enable) { 661 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; 662 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP]; 663 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP; 664 info->fw = adev->gfx.pfp_fw; 665 header = (const struct common_firmware_header *)info->fw->data; 666 adev->firmware.fw_size += 667 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 668 669 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK]; 670 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK; 671 info->fw = adev->gfx.pfp_fw; 672 header = (const struct common_firmware_header *)info->fw->data; 673 adev->firmware.fw_size += 674 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 675 676 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK]; 677 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK; 678 info->fw = adev->gfx.pfp_fw; 679 header = (const struct common_firmware_header *)info->fw->data; 680 adev->firmware.fw_size += 681 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 682 683 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; 684 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME]; 685 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME; 686 info->fw = adev->gfx.me_fw; 687 header = (const struct common_firmware_header *)info->fw->data; 688 adev->firmware.fw_size += 689 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 690 691 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK]; 692 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK; 693 info->fw = adev->gfx.me_fw; 694 header = (const struct common_firmware_header *)info->fw->data; 695 adev->firmware.fw_size += 696 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 697 698 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK]; 699 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK; 700 info->fw = adev->gfx.me_fw; 701 header = (const struct common_firmware_header *)info->fw->data; 702 adev->firmware.fw_size += 703 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 704 705 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 706 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC]; 707 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC; 708 info->fw = adev->gfx.mec_fw; 709 header = (const struct common_firmware_header *)info->fw->data; 710 adev->firmware.fw_size += 711 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 712 713 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK]; 714 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK; 715 info->fw = adev->gfx.mec_fw; 716 header = (const struct common_firmware_header *)info->fw->data; 717 adev->firmware.fw_size += 718 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 719 720 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK]; 721 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK; 722 info->fw = adev->gfx.mec_fw; 723 header = (const struct common_firmware_header *)info->fw->data; 724 adev->firmware.fw_size += 725 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 726 727 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK]; 728 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK; 729 info->fw = adev->gfx.mec_fw; 730 header = (const struct common_firmware_header *)info->fw->data; 731 adev->firmware.fw_size += 732 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 733 734 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK]; 735 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK; 736 info->fw = adev->gfx.mec_fw; 737 header = (const struct common_firmware_header *)info->fw->data; 738 adev->firmware.fw_size += 739 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 740 } else { 741 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 742 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 743 info->fw = adev->gfx.pfp_fw; 744 header = (const struct common_firmware_header *)info->fw->data; 745 adev->firmware.fw_size += 746 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 747 748 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 749 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 750 info->fw = adev->gfx.me_fw; 751 header = (const struct common_firmware_header *)info->fw->data; 752 adev->firmware.fw_size += 753 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 754 755 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 756 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 757 info->fw = adev->gfx.mec_fw; 758 header = (const struct common_firmware_header *)info->fw->data; 759 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 760 adev->firmware.fw_size += 761 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 762 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 763 764 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 765 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 766 info->fw = adev->gfx.mec_fw; 767 adev->firmware.fw_size += 768 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 769 } 770 771 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 772 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 773 info->fw = adev->gfx.rlc_fw; 774 if (info->fw) { 775 header = (const struct common_firmware_header *)info->fw->data; 776 adev->firmware.fw_size += 777 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 778 } 779 if (adev->gfx.rlc.save_restore_list_gpm_size_bytes && 780 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 781 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 782 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 783 info->fw = adev->gfx.rlc_fw; 784 adev->firmware.fw_size += 785 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 786 787 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 788 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 789 info->fw = adev->gfx.rlc_fw; 790 adev->firmware.fw_size += 791 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 792 } 793 794 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 795 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 796 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 797 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 798 info->fw = adev->gfx.rlc_fw; 799 adev->firmware.fw_size += 800 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 801 802 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 803 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 804 info->fw = adev->gfx.rlc_fw; 805 adev->firmware.fw_size += 806 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 807 } 808 809 if (adev->gfx.rlc.rlcp_ucode_size_bytes) { 810 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; 811 info->ucode_id = AMDGPU_UCODE_ID_RLC_P; 812 info->fw = adev->gfx.rlc_fw; 813 adev->firmware.fw_size += 814 ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE); 815 } 816 817 if (adev->gfx.rlc.rlcv_ucode_size_bytes) { 818 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; 819 info->ucode_id = AMDGPU_UCODE_ID_RLC_V; 820 info->fw = adev->gfx.rlc_fw; 821 adev->firmware.fw_size += 822 ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE); 823 } 824 } 825 826 out: 827 if (err) { 828 dev_err(adev->dev, 829 "gfx11: Failed to load firmware \"%s\"\n", 830 fw_name); 831 release_firmware(adev->gfx.pfp_fw); 832 adev->gfx.pfp_fw = NULL; 833 release_firmware(adev->gfx.me_fw); 834 adev->gfx.me_fw = NULL; 835 release_firmware(adev->gfx.rlc_fw); 836 adev->gfx.rlc_fw = NULL; 837 release_firmware(adev->gfx.mec_fw); 838 adev->gfx.mec_fw = NULL; 839 } 840 841 return err; 842 } 843 844 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) 845 { 846 const struct psp_firmware_header_v1_0 *toc_hdr; 847 int err = 0; 848 char fw_name[40]; 849 char ucode_prefix[30]; 850 851 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 852 853 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 854 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 855 if (err) 856 goto out; 857 858 err = amdgpu_ucode_validate(adev->psp.toc_fw); 859 if (err) 860 goto out; 861 862 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 863 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 864 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 865 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 866 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 867 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 868 return 0; 869 out: 870 dev_err(adev->dev, "Failed to load TOC microcode\n"); 871 release_firmware(adev->psp.toc_fw); 872 adev->psp.toc_fw = NULL; 873 return err; 874 } 875 876 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 877 { 878 u32 count = 0; 879 const struct cs_section_def *sect = NULL; 880 const struct cs_extent_def *ext = NULL; 881 882 /* begin clear state */ 883 count += 2; 884 /* context control state */ 885 count += 3; 886 887 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 888 for (ext = sect->section; ext->extent != NULL; ++ext) { 889 if (sect->id == SECT_CONTEXT) 890 count += 2 + ext->reg_count; 891 else 892 return 0; 893 } 894 } 895 896 /* set PA_SC_TILE_STEERING_OVERRIDE */ 897 count += 3; 898 /* end clear state */ 899 count += 2; 900 /* clear state */ 901 count += 2; 902 903 return count; 904 } 905 906 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 907 volatile u32 *buffer) 908 { 909 u32 count = 0, i; 910 const struct cs_section_def *sect = NULL; 911 const struct cs_extent_def *ext = NULL; 912 int ctx_reg_offset; 913 914 if (adev->gfx.rlc.cs_data == NULL) 915 return; 916 if (buffer == NULL) 917 return; 918 919 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 920 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 921 922 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 923 buffer[count++] = cpu_to_le32(0x80000000); 924 buffer[count++] = cpu_to_le32(0x80000000); 925 926 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 927 for (ext = sect->section; ext->extent != NULL; ++ext) { 928 if (sect->id == SECT_CONTEXT) { 929 buffer[count++] = 930 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 931 buffer[count++] = cpu_to_le32(ext->reg_index - 932 PACKET3_SET_CONTEXT_REG_START); 933 for (i = 0; i < ext->reg_count; i++) 934 buffer[count++] = cpu_to_le32(ext->extent[i]); 935 } else { 936 return; 937 } 938 } 939 } 940 941 ctx_reg_offset = 942 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 943 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 944 buffer[count++] = cpu_to_le32(ctx_reg_offset); 945 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 946 947 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 948 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 949 950 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 951 buffer[count++] = cpu_to_le32(0); 952 } 953 954 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 955 { 956 /* clear state block */ 957 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 958 &adev->gfx.rlc.clear_state_gpu_addr, 959 (void **)&adev->gfx.rlc.cs_ptr); 960 961 /* jump table block */ 962 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 963 &adev->gfx.rlc.cp_table_gpu_addr, 964 (void **)&adev->gfx.rlc.cp_table_ptr); 965 } 966 967 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 968 { 969 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 970 971 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 972 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 973 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 974 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 975 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 976 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 977 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 978 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 979 adev->gfx.rlc.rlcg_reg_access_supported = true; 980 } 981 982 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 983 { 984 const struct cs_section_def *cs_data; 985 int r; 986 987 adev->gfx.rlc.cs_data = gfx11_cs_data; 988 989 cs_data = adev->gfx.rlc.cs_data; 990 991 if (cs_data) { 992 /* init clear state block */ 993 r = amdgpu_gfx_rlc_init_csb(adev); 994 if (r) 995 return r; 996 } 997 998 /* init spm vmid with 0xf */ 999 if (adev->gfx.rlc.funcs->update_spm_vmid) 1000 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1001 1002 return 0; 1003 } 1004 1005 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 1006 { 1007 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1008 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1009 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 1010 } 1011 1012 static int gfx_v11_0_me_init(struct amdgpu_device *adev) 1013 { 1014 int r; 1015 1016 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 1017 1018 amdgpu_gfx_graphics_queue_acquire(adev); 1019 1020 r = gfx_v11_0_init_microcode(adev); 1021 if (r) 1022 DRM_ERROR("Failed to load gfx firmware!\n"); 1023 1024 return r; 1025 } 1026 1027 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 1028 { 1029 int r; 1030 u32 *hpd; 1031 size_t mec_hpd_size; 1032 1033 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1034 1035 /* take ownership of the relevant compute queues */ 1036 amdgpu_gfx_compute_queue_acquire(adev); 1037 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 1038 1039 if (mec_hpd_size) { 1040 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1041 AMDGPU_GEM_DOMAIN_GTT, 1042 &adev->gfx.mec.hpd_eop_obj, 1043 &adev->gfx.mec.hpd_eop_gpu_addr, 1044 (void **)&hpd); 1045 if (r) { 1046 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1047 gfx_v11_0_mec_fini(adev); 1048 return r; 1049 } 1050 1051 memset(hpd, 0, mec_hpd_size); 1052 1053 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1054 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1055 } 1056 1057 return 0; 1058 } 1059 1060 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1061 { 1062 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1063 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1064 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1065 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1066 } 1067 1068 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1069 uint32_t thread, uint32_t regno, 1070 uint32_t num, uint32_t *out) 1071 { 1072 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1073 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1074 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1075 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1076 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1077 while (num--) 1078 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1079 } 1080 1081 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1082 { 1083 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 1084 * field when performing a select_se_sh so it should be 1085 * zero here */ 1086 WARN_ON(simd != 0); 1087 1088 /* type 2 wave data */ 1089 dst[(*no_fields)++] = 2; 1090 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1091 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1092 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1093 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1094 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1095 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1096 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1097 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1098 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1099 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1100 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1101 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1102 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1103 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1104 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 1105 } 1106 1107 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1108 uint32_t wave, uint32_t start, 1109 uint32_t size, uint32_t *dst) 1110 { 1111 WARN_ON(simd != 0); 1112 1113 wave_read_regs( 1114 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1115 dst); 1116 } 1117 1118 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1119 uint32_t wave, uint32_t thread, 1120 uint32_t start, uint32_t size, 1121 uint32_t *dst) 1122 { 1123 wave_read_regs( 1124 adev, wave, thread, 1125 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1126 } 1127 1128 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1129 u32 me, u32 pipe, u32 q, u32 vm) 1130 { 1131 soc21_grbm_select(adev, me, pipe, q, vm); 1132 } 1133 1134 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1135 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1136 .select_se_sh = &gfx_v11_0_select_se_sh, 1137 .read_wave_data = &gfx_v11_0_read_wave_data, 1138 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1139 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1140 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1141 .init_spm_golden = &gfx_v11_0_init_spm_golden_registers, 1142 }; 1143 1144 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1145 { 1146 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 1147 1148 switch (adev->ip_versions[GC_HWIP][0]) { 1149 case IP_VERSION(11, 0, 0): 1150 case IP_VERSION(11, 0, 2): 1151 adev->gfx.config.max_hw_contexts = 8; 1152 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1153 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1154 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1155 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1156 break; 1157 case IP_VERSION(11, 0, 1): 1158 adev->gfx.config.max_hw_contexts = 8; 1159 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1160 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1161 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1162 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1163 break; 1164 default: 1165 BUG(); 1166 break; 1167 } 1168 1169 return 0; 1170 } 1171 1172 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1173 int me, int pipe, int queue) 1174 { 1175 int r; 1176 struct amdgpu_ring *ring; 1177 unsigned int irq_type; 1178 1179 ring = &adev->gfx.gfx_ring[ring_id]; 1180 1181 ring->me = me; 1182 ring->pipe = pipe; 1183 ring->queue = queue; 1184 1185 ring->ring_obj = NULL; 1186 ring->use_doorbell = true; 1187 1188 if (!ring_id) 1189 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1190 else 1191 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1192 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1193 1194 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1195 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1196 AMDGPU_RING_PRIO_DEFAULT, NULL); 1197 if (r) 1198 return r; 1199 return 0; 1200 } 1201 1202 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1203 int mec, int pipe, int queue) 1204 { 1205 int r; 1206 unsigned irq_type; 1207 struct amdgpu_ring *ring; 1208 unsigned int hw_prio; 1209 1210 ring = &adev->gfx.compute_ring[ring_id]; 1211 1212 /* mec0 is me1 */ 1213 ring->me = mec + 1; 1214 ring->pipe = pipe; 1215 ring->queue = queue; 1216 1217 ring->ring_obj = NULL; 1218 ring->use_doorbell = true; 1219 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1220 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1221 + (ring_id * GFX11_MEC_HPD_SIZE); 1222 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1223 1224 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1225 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1226 + ring->pipe; 1227 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1228 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1229 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1230 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1231 hw_prio, NULL); 1232 if (r) 1233 return r; 1234 1235 return 0; 1236 } 1237 1238 static struct { 1239 SOC21_FIRMWARE_ID id; 1240 unsigned int offset; 1241 unsigned int size; 1242 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1243 1244 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1245 { 1246 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1247 1248 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1249 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1250 rlc_autoload_info[ucode->id].id = ucode->id; 1251 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1252 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1253 1254 ucode++; 1255 } 1256 } 1257 1258 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1259 { 1260 uint32_t total_size = 0; 1261 SOC21_FIRMWARE_ID id; 1262 1263 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1264 1265 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1266 total_size += rlc_autoload_info[id].size; 1267 1268 /* In case the offset in rlc toc ucode is aligned */ 1269 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1270 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1271 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1272 1273 return total_size; 1274 } 1275 1276 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1277 { 1278 int r; 1279 uint32_t total_size; 1280 1281 total_size = gfx_v11_0_calc_toc_total_size(adev); 1282 1283 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1284 AMDGPU_GEM_DOMAIN_VRAM, 1285 &adev->gfx.rlc.rlc_autoload_bo, 1286 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1287 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1288 1289 if (r) { 1290 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1291 return r; 1292 } 1293 1294 return 0; 1295 } 1296 1297 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1298 SOC21_FIRMWARE_ID id, 1299 const void *fw_data, 1300 uint32_t fw_size, 1301 uint32_t *fw_autoload_mask) 1302 { 1303 uint32_t toc_offset; 1304 uint32_t toc_fw_size; 1305 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1306 1307 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1308 return; 1309 1310 toc_offset = rlc_autoload_info[id].offset; 1311 toc_fw_size = rlc_autoload_info[id].size; 1312 1313 if (fw_size == 0) 1314 fw_size = toc_fw_size; 1315 1316 if (fw_size > toc_fw_size) 1317 fw_size = toc_fw_size; 1318 1319 memcpy(ptr + toc_offset, fw_data, fw_size); 1320 1321 if (fw_size < toc_fw_size) 1322 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1323 1324 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1325 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1326 } 1327 1328 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1329 uint32_t *fw_autoload_mask) 1330 { 1331 void *data; 1332 uint32_t size; 1333 uint64_t *toc_ptr; 1334 1335 *(uint64_t *)fw_autoload_mask |= 0x1; 1336 1337 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1338 1339 data = adev->psp.toc.start_addr; 1340 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1341 1342 toc_ptr = (uint64_t *)data + size / 8 - 1; 1343 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1344 1345 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1346 data, size, fw_autoload_mask); 1347 } 1348 1349 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1350 uint32_t *fw_autoload_mask) 1351 { 1352 const __le32 *fw_data; 1353 uint32_t fw_size; 1354 const struct gfx_firmware_header_v1_0 *cp_hdr; 1355 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1356 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1357 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1358 uint16_t version_major, version_minor; 1359 1360 if (adev->gfx.rs64_enable) { 1361 /* pfp ucode */ 1362 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1363 adev->gfx.pfp_fw->data; 1364 /* instruction */ 1365 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1366 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1367 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1368 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1369 fw_data, fw_size, fw_autoload_mask); 1370 /* data */ 1371 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1372 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1373 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1374 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1375 fw_data, fw_size, fw_autoload_mask); 1376 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1377 fw_data, fw_size, fw_autoload_mask); 1378 /* me ucode */ 1379 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1380 adev->gfx.me_fw->data; 1381 /* instruction */ 1382 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1383 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1384 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1385 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1386 fw_data, fw_size, fw_autoload_mask); 1387 /* data */ 1388 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1389 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1390 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1391 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1392 fw_data, fw_size, fw_autoload_mask); 1393 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1394 fw_data, fw_size, fw_autoload_mask); 1395 /* mec ucode */ 1396 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1397 adev->gfx.mec_fw->data; 1398 /* instruction */ 1399 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1400 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1401 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1402 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1403 fw_data, fw_size, fw_autoload_mask); 1404 /* data */ 1405 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1406 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1407 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1408 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1409 fw_data, fw_size, fw_autoload_mask); 1410 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1411 fw_data, fw_size, fw_autoload_mask); 1412 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1413 fw_data, fw_size, fw_autoload_mask); 1414 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1415 fw_data, fw_size, fw_autoload_mask); 1416 } else { 1417 /* pfp ucode */ 1418 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1419 adev->gfx.pfp_fw->data; 1420 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1421 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1422 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1423 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1424 fw_data, fw_size, fw_autoload_mask); 1425 1426 /* me ucode */ 1427 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1428 adev->gfx.me_fw->data; 1429 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1430 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1431 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1432 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1433 fw_data, fw_size, fw_autoload_mask); 1434 1435 /* mec ucode */ 1436 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1437 adev->gfx.mec_fw->data; 1438 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1439 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1440 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1441 cp_hdr->jt_size * 4; 1442 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1443 fw_data, fw_size, fw_autoload_mask); 1444 } 1445 1446 /* rlc ucode */ 1447 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1448 adev->gfx.rlc_fw->data; 1449 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1450 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1451 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1452 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1453 fw_data, fw_size, fw_autoload_mask); 1454 1455 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1456 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1457 if (version_major == 2) { 1458 if (version_minor >= 2) { 1459 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1460 1461 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1462 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1463 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1464 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1465 fw_data, fw_size, fw_autoload_mask); 1466 1467 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1468 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1469 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1470 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1471 fw_data, fw_size, fw_autoload_mask); 1472 } 1473 } 1474 } 1475 1476 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1477 uint32_t *fw_autoload_mask) 1478 { 1479 const __le32 *fw_data; 1480 uint32_t fw_size; 1481 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1482 1483 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1484 adev->sdma.instance[0].fw->data; 1485 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1486 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1487 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1488 1489 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1490 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1491 1492 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1493 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1494 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1495 1496 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1497 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1498 } 1499 1500 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1501 uint32_t *fw_autoload_mask) 1502 { 1503 const __le32 *fw_data; 1504 unsigned fw_size; 1505 const struct mes_firmware_header_v1_0 *mes_hdr; 1506 int pipe, ucode_id, data_id; 1507 1508 for (pipe = 0; pipe < 2; pipe++) { 1509 if (pipe==0) { 1510 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1511 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1512 } else { 1513 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1514 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1515 } 1516 1517 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1518 adev->mes.fw[pipe]->data; 1519 1520 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1521 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1522 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1523 1524 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1525 ucode_id, fw_data, fw_size, fw_autoload_mask); 1526 1527 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1528 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1529 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1530 1531 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1532 data_id, fw_data, fw_size, fw_autoload_mask); 1533 } 1534 } 1535 1536 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1537 { 1538 uint32_t rlc_g_offset, rlc_g_size; 1539 uint64_t gpu_addr; 1540 uint32_t autoload_fw_id[2]; 1541 1542 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1543 1544 /* RLC autoload sequence 2: copy ucode */ 1545 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1546 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1547 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1548 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1549 1550 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1551 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1552 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1553 1554 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1555 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1556 1557 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1558 1559 /* RLC autoload sequence 3: load IMU fw */ 1560 if (adev->gfx.imu.funcs->load_microcode) 1561 adev->gfx.imu.funcs->load_microcode(adev); 1562 /* RLC autoload sequence 4 init IMU fw */ 1563 if (adev->gfx.imu.funcs->setup_imu) 1564 adev->gfx.imu.funcs->setup_imu(adev); 1565 if (adev->gfx.imu.funcs->start_imu) 1566 adev->gfx.imu.funcs->start_imu(adev); 1567 1568 /* RLC autoload sequence 5 disable gpa mode */ 1569 gfx_v11_0_disable_gpa_mode(adev); 1570 1571 return 0; 1572 } 1573 1574 static int gfx_v11_0_sw_init(void *handle) 1575 { 1576 int i, j, k, r, ring_id = 0; 1577 struct amdgpu_kiq *kiq; 1578 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1579 1580 adev->gfxhub.funcs->init(adev); 1581 1582 switch (adev->ip_versions[GC_HWIP][0]) { 1583 case IP_VERSION(11, 0, 0): 1584 case IP_VERSION(11, 0, 1): 1585 case IP_VERSION(11, 0, 2): 1586 adev->gfx.me.num_me = 1; 1587 adev->gfx.me.num_pipe_per_me = 1; 1588 adev->gfx.me.num_queue_per_pipe = 1; 1589 adev->gfx.mec.num_mec = 2; 1590 adev->gfx.mec.num_pipe_per_mec = 4; 1591 adev->gfx.mec.num_queue_per_pipe = 4; 1592 break; 1593 default: 1594 adev->gfx.me.num_me = 1; 1595 adev->gfx.me.num_pipe_per_me = 1; 1596 adev->gfx.me.num_queue_per_pipe = 1; 1597 adev->gfx.mec.num_mec = 1; 1598 adev->gfx.mec.num_pipe_per_mec = 4; 1599 adev->gfx.mec.num_queue_per_pipe = 8; 1600 break; 1601 } 1602 1603 /* EOP Event */ 1604 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1605 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1606 &adev->gfx.eop_irq); 1607 if (r) 1608 return r; 1609 1610 /* Privileged reg */ 1611 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1612 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1613 &adev->gfx.priv_reg_irq); 1614 if (r) 1615 return r; 1616 1617 /* Privileged inst */ 1618 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1619 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1620 &adev->gfx.priv_inst_irq); 1621 if (r) 1622 return r; 1623 1624 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1625 1626 if (adev->gfx.imu.funcs) { 1627 if (adev->gfx.imu.funcs->init_microcode) { 1628 r = adev->gfx.imu.funcs->init_microcode(adev); 1629 if (r) 1630 DRM_ERROR("Failed to load imu firmware!\n"); 1631 } 1632 } 1633 1634 r = gfx_v11_0_me_init(adev); 1635 if (r) 1636 return r; 1637 1638 r = gfx_v11_0_rlc_init(adev); 1639 if (r) { 1640 DRM_ERROR("Failed to init rlc BOs!\n"); 1641 return r; 1642 } 1643 1644 r = gfx_v11_0_mec_init(adev); 1645 if (r) { 1646 DRM_ERROR("Failed to init MEC BOs!\n"); 1647 return r; 1648 } 1649 1650 /* set up the gfx ring */ 1651 for (i = 0; i < adev->gfx.me.num_me; i++) { 1652 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1653 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1654 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1655 continue; 1656 1657 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1658 i, k, j); 1659 if (r) 1660 return r; 1661 ring_id++; 1662 } 1663 } 1664 } 1665 1666 ring_id = 0; 1667 /* set up the compute queues - allocate horizontally across pipes */ 1668 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1669 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1670 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1671 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1672 j)) 1673 continue; 1674 1675 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1676 i, k, j); 1677 if (r) 1678 return r; 1679 1680 ring_id++; 1681 } 1682 } 1683 } 1684 1685 if (!adev->enable_mes_kiq) { 1686 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE); 1687 if (r) { 1688 DRM_ERROR("Failed to init KIQ BOs!\n"); 1689 return r; 1690 } 1691 1692 kiq = &adev->gfx.kiq; 1693 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1694 if (r) 1695 return r; 1696 } 1697 1698 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd)); 1699 if (r) 1700 return r; 1701 1702 /* allocate visible FB for rlc auto-loading fw */ 1703 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1704 r = gfx_v11_0_init_toc_microcode(adev); 1705 if (r) 1706 dev_err(adev->dev, "Failed to load toc firmware!\n"); 1707 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1708 if (r) 1709 return r; 1710 } 1711 1712 r = gfx_v11_0_gpu_early_init(adev); 1713 if (r) 1714 return r; 1715 1716 return 0; 1717 } 1718 1719 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1720 { 1721 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1722 &adev->gfx.pfp.pfp_fw_gpu_addr, 1723 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1724 1725 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1726 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1727 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1728 } 1729 1730 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1731 { 1732 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1733 &adev->gfx.me.me_fw_gpu_addr, 1734 (void **)&adev->gfx.me.me_fw_ptr); 1735 1736 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1737 &adev->gfx.me.me_fw_data_gpu_addr, 1738 (void **)&adev->gfx.me.me_fw_data_ptr); 1739 } 1740 1741 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1742 { 1743 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1744 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1745 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1746 } 1747 1748 static int gfx_v11_0_sw_fini(void *handle) 1749 { 1750 int i; 1751 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1752 1753 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1754 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1755 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1756 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1757 1758 amdgpu_gfx_mqd_sw_fini(adev); 1759 1760 if (!adev->enable_mes_kiq) { 1761 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1762 amdgpu_gfx_kiq_fini(adev); 1763 } 1764 1765 gfx_v11_0_pfp_fini(adev); 1766 gfx_v11_0_me_fini(adev); 1767 gfx_v11_0_rlc_fini(adev); 1768 gfx_v11_0_mec_fini(adev); 1769 1770 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1771 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1772 1773 gfx_v11_0_free_microcode(adev); 1774 1775 return 0; 1776 } 1777 1778 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1779 u32 sh_num, u32 instance) 1780 { 1781 u32 data; 1782 1783 if (instance == 0xffffffff) 1784 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1785 INSTANCE_BROADCAST_WRITES, 1); 1786 else 1787 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1788 instance); 1789 1790 if (se_num == 0xffffffff) 1791 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1792 1); 1793 else 1794 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1795 1796 if (sh_num == 0xffffffff) 1797 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1798 1); 1799 else 1800 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1801 1802 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1803 } 1804 1805 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1806 { 1807 u32 data, mask; 1808 1809 data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1810 data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1811 1812 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1813 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1814 1815 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1816 adev->gfx.config.max_sh_per_se); 1817 1818 return (~data) & mask; 1819 } 1820 1821 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1822 { 1823 int i, j; 1824 u32 data; 1825 u32 active_rbs = 0; 1826 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1827 adev->gfx.config.max_sh_per_se; 1828 1829 mutex_lock(&adev->grbm_idx_mutex); 1830 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1831 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1832 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 1833 data = gfx_v11_0_get_rb_active_bitmap(adev); 1834 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1835 rb_bitmap_width_per_sh); 1836 } 1837 } 1838 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1839 mutex_unlock(&adev->grbm_idx_mutex); 1840 1841 adev->gfx.config.backend_enable_mask = active_rbs; 1842 adev->gfx.config.num_rbs = hweight32(active_rbs); 1843 } 1844 1845 #define DEFAULT_SH_MEM_BASES (0x6000) 1846 #define LDS_APP_BASE 0x1 1847 #define SCRATCH_APP_BASE 0x2 1848 1849 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1850 { 1851 int i; 1852 uint32_t sh_mem_bases; 1853 uint32_t data; 1854 1855 /* 1856 * Configure apertures: 1857 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1858 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1859 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1860 */ 1861 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1862 SCRATCH_APP_BASE; 1863 1864 mutex_lock(&adev->srbm_mutex); 1865 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1866 soc21_grbm_select(adev, 0, 0, 0, i); 1867 /* CP and shaders */ 1868 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1869 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1870 1871 /* Enable trap for each kfd vmid. */ 1872 data = RREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL)); 1873 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1874 } 1875 soc21_grbm_select(adev, 0, 0, 0, 0); 1876 mutex_unlock(&adev->srbm_mutex); 1877 1878 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1879 acccess. These should be enabled by FW for target VMIDs. */ 1880 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1881 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1882 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1883 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1884 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1885 } 1886 } 1887 1888 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1889 { 1890 int vmid; 1891 1892 /* 1893 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1894 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1895 * the driver can enable them for graphics. VMID0 should maintain 1896 * access so that HWS firmware can save/restore entries. 1897 */ 1898 for (vmid = 1; vmid < 16; vmid++) { 1899 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1900 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1901 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1902 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1903 } 1904 } 1905 1906 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1907 { 1908 /* TODO: harvest feature to be added later. */ 1909 } 1910 1911 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1912 { 1913 /* TCCs are global (not instanced). */ 1914 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1915 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1916 1917 adev->gfx.config.tcc_disabled_mask = 1918 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1919 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1920 } 1921 1922 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1923 { 1924 u32 tmp; 1925 int i; 1926 1927 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1928 1929 gfx_v11_0_setup_rb(adev); 1930 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1931 gfx_v11_0_get_tcc_info(adev); 1932 adev->gfx.config.pa_sc_tile_steering_override = 0; 1933 1934 /* XXX SH_MEM regs */ 1935 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1936 mutex_lock(&adev->srbm_mutex); 1937 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1938 soc21_grbm_select(adev, 0, 0, 0, i); 1939 /* CP and shaders */ 1940 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1941 if (i != 0) { 1942 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1943 (adev->gmc.private_aperture_start >> 48)); 1944 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1945 (adev->gmc.shared_aperture_start >> 48)); 1946 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1947 } 1948 } 1949 soc21_grbm_select(adev, 0, 0, 0, 0); 1950 1951 mutex_unlock(&adev->srbm_mutex); 1952 1953 gfx_v11_0_init_compute_vmid(adev); 1954 gfx_v11_0_init_gds_vmid(adev); 1955 } 1956 1957 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1958 bool enable) 1959 { 1960 u32 tmp; 1961 1962 if (amdgpu_sriov_vf(adev)) 1963 return; 1964 1965 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1966 1967 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1968 enable ? 1 : 0); 1969 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1970 enable ? 1 : 0); 1971 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1972 enable ? 1 : 0); 1973 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1974 enable ? 1 : 0); 1975 1976 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1977 } 1978 1979 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1980 { 1981 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1982 1983 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1984 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1985 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1986 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1987 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1988 1989 return 0; 1990 } 1991 1992 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1993 { 1994 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1995 1996 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1997 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1998 } 1999 2000 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 2001 { 2002 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2003 udelay(50); 2004 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2005 udelay(50); 2006 } 2007 2008 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2009 bool enable) 2010 { 2011 uint32_t rlc_pg_cntl; 2012 2013 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2014 2015 if (!enable) { 2016 /* RLC_PG_CNTL[23] = 0 (default) 2017 * RLC will wait for handshake acks with SMU 2018 * GFXOFF will be enabled 2019 * RLC_PG_CNTL[23] = 1 2020 * RLC will not issue any message to SMU 2021 * hence no handshake between SMU & RLC 2022 * GFXOFF will be disabled 2023 */ 2024 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2025 } else 2026 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2027 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2028 } 2029 2030 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2031 { 2032 /* TODO: enable rlc & smu handshake until smu 2033 * and gfxoff feature works as expected */ 2034 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2035 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2036 2037 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2038 udelay(50); 2039 } 2040 2041 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2042 { 2043 uint32_t tmp; 2044 2045 /* enable Save Restore Machine */ 2046 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2047 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2048 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2049 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2050 } 2051 2052 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2053 { 2054 const struct rlc_firmware_header_v2_0 *hdr; 2055 const __le32 *fw_data; 2056 unsigned i, fw_size; 2057 2058 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2059 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2060 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2061 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2062 2063 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2064 RLCG_UCODE_LOADING_START_ADDRESS); 2065 2066 for (i = 0; i < fw_size; i++) 2067 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2068 le32_to_cpup(fw_data++)); 2069 2070 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2071 } 2072 2073 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2074 { 2075 const struct rlc_firmware_header_v2_2 *hdr; 2076 const __le32 *fw_data; 2077 unsigned i, fw_size; 2078 u32 tmp; 2079 2080 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2081 2082 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2083 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2084 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2085 2086 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2087 2088 for (i = 0; i < fw_size; i++) { 2089 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2090 msleep(1); 2091 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2092 le32_to_cpup(fw_data++)); 2093 } 2094 2095 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2096 2097 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2098 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2099 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2100 2101 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2102 for (i = 0; i < fw_size; i++) { 2103 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2104 msleep(1); 2105 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2106 le32_to_cpup(fw_data++)); 2107 } 2108 2109 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2110 2111 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2112 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2113 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2114 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2115 } 2116 2117 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2118 { 2119 const struct rlc_firmware_header_v2_3 *hdr; 2120 const __le32 *fw_data; 2121 unsigned i, fw_size; 2122 u32 tmp; 2123 2124 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2125 2126 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2127 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2128 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2129 2130 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2131 2132 for (i = 0; i < fw_size; i++) { 2133 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2134 msleep(1); 2135 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2136 le32_to_cpup(fw_data++)); 2137 } 2138 2139 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2140 2141 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2142 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2143 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2144 2145 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2146 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2147 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2148 2149 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2150 2151 for (i = 0; i < fw_size; i++) { 2152 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2153 msleep(1); 2154 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2155 le32_to_cpup(fw_data++)); 2156 } 2157 2158 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2159 2160 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2161 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2162 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2163 } 2164 2165 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2166 { 2167 const struct rlc_firmware_header_v2_0 *hdr; 2168 uint16_t version_major; 2169 uint16_t version_minor; 2170 2171 if (!adev->gfx.rlc_fw) 2172 return -EINVAL; 2173 2174 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2175 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2176 2177 version_major = le16_to_cpu(hdr->header.header_version_major); 2178 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2179 2180 if (version_major == 2) { 2181 gfx_v11_0_load_rlcg_microcode(adev); 2182 if (amdgpu_dpm == 1) { 2183 if (version_minor >= 2) 2184 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2185 if (version_minor == 3) 2186 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2187 } 2188 2189 return 0; 2190 } 2191 2192 return -EINVAL; 2193 } 2194 2195 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2196 { 2197 int r; 2198 2199 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2200 gfx_v11_0_init_csb(adev); 2201 2202 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2203 gfx_v11_0_rlc_enable_srm(adev); 2204 } else { 2205 if (amdgpu_sriov_vf(adev)) { 2206 gfx_v11_0_init_csb(adev); 2207 return 0; 2208 } 2209 2210 adev->gfx.rlc.funcs->stop(adev); 2211 2212 /* disable CG */ 2213 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2214 2215 /* disable PG */ 2216 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2217 2218 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2219 /* legacy rlc firmware loading */ 2220 r = gfx_v11_0_rlc_load_microcode(adev); 2221 if (r) 2222 return r; 2223 } 2224 2225 gfx_v11_0_init_csb(adev); 2226 2227 adev->gfx.rlc.funcs->start(adev); 2228 } 2229 return 0; 2230 } 2231 2232 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2233 { 2234 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2235 uint32_t tmp; 2236 int i; 2237 2238 /* Trigger an invalidation of the L1 instruction caches */ 2239 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2240 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2241 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2242 2243 /* Wait for invalidation complete */ 2244 for (i = 0; i < usec_timeout; i++) { 2245 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2246 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2247 INVALIDATE_CACHE_COMPLETE)) 2248 break; 2249 udelay(1); 2250 } 2251 2252 if (i >= usec_timeout) { 2253 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2254 return -EINVAL; 2255 } 2256 2257 if (amdgpu_emu_mode == 1) 2258 adev->hdp.funcs->flush_hdp(adev, NULL); 2259 2260 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2261 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2262 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2263 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2264 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2265 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2266 2267 /* Program me ucode address into intruction cache address register */ 2268 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2269 lower_32_bits(addr) & 0xFFFFF000); 2270 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2271 upper_32_bits(addr)); 2272 2273 return 0; 2274 } 2275 2276 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2277 { 2278 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2279 uint32_t tmp; 2280 int i; 2281 2282 /* Trigger an invalidation of the L1 instruction caches */ 2283 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2284 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2285 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2286 2287 /* Wait for invalidation complete */ 2288 for (i = 0; i < usec_timeout; i++) { 2289 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2290 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2291 INVALIDATE_CACHE_COMPLETE)) 2292 break; 2293 udelay(1); 2294 } 2295 2296 if (i >= usec_timeout) { 2297 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2298 return -EINVAL; 2299 } 2300 2301 if (amdgpu_emu_mode == 1) 2302 adev->hdp.funcs->flush_hdp(adev, NULL); 2303 2304 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2305 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2306 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2307 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2308 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2309 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2310 2311 /* Program pfp ucode address into intruction cache address register */ 2312 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2313 lower_32_bits(addr) & 0xFFFFF000); 2314 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2315 upper_32_bits(addr)); 2316 2317 return 0; 2318 } 2319 2320 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2321 { 2322 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2323 uint32_t tmp; 2324 int i; 2325 2326 /* Trigger an invalidation of the L1 instruction caches */ 2327 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2328 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2329 2330 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2331 2332 /* Wait for invalidation complete */ 2333 for (i = 0; i < usec_timeout; i++) { 2334 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2335 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2336 INVALIDATE_CACHE_COMPLETE)) 2337 break; 2338 udelay(1); 2339 } 2340 2341 if (i >= usec_timeout) { 2342 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2343 return -EINVAL; 2344 } 2345 2346 if (amdgpu_emu_mode == 1) 2347 adev->hdp.funcs->flush_hdp(adev, NULL); 2348 2349 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2350 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2351 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2352 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2353 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2354 2355 /* Program mec1 ucode address into intruction cache address register */ 2356 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2357 lower_32_bits(addr) & 0xFFFFF000); 2358 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2359 upper_32_bits(addr)); 2360 2361 return 0; 2362 } 2363 2364 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2365 { 2366 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2367 uint32_t tmp; 2368 unsigned i, pipe_id; 2369 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2370 2371 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2372 adev->gfx.pfp_fw->data; 2373 2374 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2375 lower_32_bits(addr)); 2376 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2377 upper_32_bits(addr)); 2378 2379 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2380 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2381 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2382 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2383 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2384 2385 /* 2386 * Programming any of the CP_PFP_IC_BASE registers 2387 * forces invalidation of the ME L1 I$. Wait for the 2388 * invalidation complete 2389 */ 2390 for (i = 0; i < usec_timeout; i++) { 2391 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2392 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2393 INVALIDATE_CACHE_COMPLETE)) 2394 break; 2395 udelay(1); 2396 } 2397 2398 if (i >= usec_timeout) { 2399 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2400 return -EINVAL; 2401 } 2402 2403 /* Prime the L1 instruction caches */ 2404 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2405 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2406 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2407 /* Waiting for cache primed*/ 2408 for (i = 0; i < usec_timeout; i++) { 2409 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2410 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2411 ICACHE_PRIMED)) 2412 break; 2413 udelay(1); 2414 } 2415 2416 if (i >= usec_timeout) { 2417 dev_err(adev->dev, "failed to prime instruction cache\n"); 2418 return -EINVAL; 2419 } 2420 2421 mutex_lock(&adev->srbm_mutex); 2422 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2423 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2424 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2425 (pfp_hdr->ucode_start_addr_hi << 30) | 2426 (pfp_hdr->ucode_start_addr_lo >> 2)); 2427 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2428 pfp_hdr->ucode_start_addr_hi >> 2); 2429 2430 /* 2431 * Program CP_ME_CNTL to reset given PIPE to take 2432 * effect of CP_PFP_PRGRM_CNTR_START. 2433 */ 2434 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2435 if (pipe_id == 0) 2436 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2437 PFP_PIPE0_RESET, 1); 2438 else 2439 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2440 PFP_PIPE1_RESET, 1); 2441 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2442 2443 /* Clear pfp pipe0 reset bit. */ 2444 if (pipe_id == 0) 2445 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2446 PFP_PIPE0_RESET, 0); 2447 else 2448 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2449 PFP_PIPE1_RESET, 0); 2450 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2451 2452 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2453 lower_32_bits(addr2)); 2454 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2455 upper_32_bits(addr2)); 2456 } 2457 soc21_grbm_select(adev, 0, 0, 0, 0); 2458 mutex_unlock(&adev->srbm_mutex); 2459 2460 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2461 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2462 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2463 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2464 2465 /* Invalidate the data caches */ 2466 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2467 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2468 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2469 2470 for (i = 0; i < usec_timeout; i++) { 2471 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2472 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2473 INVALIDATE_DCACHE_COMPLETE)) 2474 break; 2475 udelay(1); 2476 } 2477 2478 if (i >= usec_timeout) { 2479 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2480 return -EINVAL; 2481 } 2482 2483 return 0; 2484 } 2485 2486 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2487 { 2488 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2489 uint32_t tmp; 2490 unsigned i, pipe_id; 2491 const struct gfx_firmware_header_v2_0 *me_hdr; 2492 2493 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2494 adev->gfx.me_fw->data; 2495 2496 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2497 lower_32_bits(addr)); 2498 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2499 upper_32_bits(addr)); 2500 2501 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2502 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2503 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2504 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2505 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2506 2507 /* 2508 * Programming any of the CP_ME_IC_BASE registers 2509 * forces invalidation of the ME L1 I$. Wait for the 2510 * invalidation complete 2511 */ 2512 for (i = 0; i < usec_timeout; i++) { 2513 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2514 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2515 INVALIDATE_CACHE_COMPLETE)) 2516 break; 2517 udelay(1); 2518 } 2519 2520 if (i >= usec_timeout) { 2521 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2522 return -EINVAL; 2523 } 2524 2525 /* Prime the instruction caches */ 2526 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2527 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2528 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2529 2530 /* Waiting for instruction cache primed*/ 2531 for (i = 0; i < usec_timeout; i++) { 2532 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2533 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2534 ICACHE_PRIMED)) 2535 break; 2536 udelay(1); 2537 } 2538 2539 if (i >= usec_timeout) { 2540 dev_err(adev->dev, "failed to prime instruction cache\n"); 2541 return -EINVAL; 2542 } 2543 2544 mutex_lock(&adev->srbm_mutex); 2545 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2546 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2547 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2548 (me_hdr->ucode_start_addr_hi << 30) | 2549 (me_hdr->ucode_start_addr_lo >> 2) ); 2550 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2551 me_hdr->ucode_start_addr_hi>>2); 2552 2553 /* 2554 * Program CP_ME_CNTL to reset given PIPE to take 2555 * effect of CP_PFP_PRGRM_CNTR_START. 2556 */ 2557 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2558 if (pipe_id == 0) 2559 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2560 ME_PIPE0_RESET, 1); 2561 else 2562 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2563 ME_PIPE1_RESET, 1); 2564 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2565 2566 /* Clear pfp pipe0 reset bit. */ 2567 if (pipe_id == 0) 2568 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2569 ME_PIPE0_RESET, 0); 2570 else 2571 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2572 ME_PIPE1_RESET, 0); 2573 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2574 2575 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2576 lower_32_bits(addr2)); 2577 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2578 upper_32_bits(addr2)); 2579 } 2580 soc21_grbm_select(adev, 0, 0, 0, 0); 2581 mutex_unlock(&adev->srbm_mutex); 2582 2583 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2584 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2585 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2586 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2587 2588 /* Invalidate the data caches */ 2589 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2590 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2591 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2592 2593 for (i = 0; i < usec_timeout; i++) { 2594 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2595 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2596 INVALIDATE_DCACHE_COMPLETE)) 2597 break; 2598 udelay(1); 2599 } 2600 2601 if (i >= usec_timeout) { 2602 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2603 return -EINVAL; 2604 } 2605 2606 return 0; 2607 } 2608 2609 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2610 { 2611 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2612 uint32_t tmp; 2613 unsigned i; 2614 const struct gfx_firmware_header_v2_0 *mec_hdr; 2615 2616 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2617 adev->gfx.mec_fw->data; 2618 2619 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2620 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2621 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2622 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2623 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2624 2625 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2626 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2627 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2628 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2629 2630 mutex_lock(&adev->srbm_mutex); 2631 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2632 soc21_grbm_select(adev, 1, i, 0, 0); 2633 2634 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2635 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2636 upper_32_bits(addr2)); 2637 2638 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2639 mec_hdr->ucode_start_addr_lo >> 2 | 2640 mec_hdr->ucode_start_addr_hi << 30); 2641 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2642 mec_hdr->ucode_start_addr_hi >> 2); 2643 2644 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2645 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2646 upper_32_bits(addr)); 2647 } 2648 mutex_unlock(&adev->srbm_mutex); 2649 soc21_grbm_select(adev, 0, 0, 0, 0); 2650 2651 /* Trigger an invalidation of the L1 instruction caches */ 2652 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2653 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2654 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2655 2656 /* Wait for invalidation complete */ 2657 for (i = 0; i < usec_timeout; i++) { 2658 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2659 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2660 INVALIDATE_DCACHE_COMPLETE)) 2661 break; 2662 udelay(1); 2663 } 2664 2665 if (i >= usec_timeout) { 2666 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2667 return -EINVAL; 2668 } 2669 2670 /* Trigger an invalidation of the L1 instruction caches */ 2671 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2672 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2673 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2674 2675 /* Wait for invalidation complete */ 2676 for (i = 0; i < usec_timeout; i++) { 2677 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2678 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2679 INVALIDATE_CACHE_COMPLETE)) 2680 break; 2681 udelay(1); 2682 } 2683 2684 if (i >= usec_timeout) { 2685 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2686 return -EINVAL; 2687 } 2688 2689 return 0; 2690 } 2691 2692 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2693 { 2694 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2695 const struct gfx_firmware_header_v2_0 *me_hdr; 2696 const struct gfx_firmware_header_v2_0 *mec_hdr; 2697 uint32_t pipe_id, tmp; 2698 2699 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2700 adev->gfx.mec_fw->data; 2701 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2702 adev->gfx.me_fw->data; 2703 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2704 adev->gfx.pfp_fw->data; 2705 2706 /* config pfp program start addr */ 2707 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2708 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2709 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2710 (pfp_hdr->ucode_start_addr_hi << 30) | 2711 (pfp_hdr->ucode_start_addr_lo >> 2)); 2712 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2713 pfp_hdr->ucode_start_addr_hi >> 2); 2714 } 2715 soc21_grbm_select(adev, 0, 0, 0, 0); 2716 2717 /* reset pfp pipe */ 2718 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2719 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2720 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2721 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2722 2723 /* clear pfp pipe reset */ 2724 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2725 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2726 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2727 2728 /* config me program start addr */ 2729 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2730 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2731 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2732 (me_hdr->ucode_start_addr_hi << 30) | 2733 (me_hdr->ucode_start_addr_lo >> 2) ); 2734 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2735 me_hdr->ucode_start_addr_hi>>2); 2736 } 2737 soc21_grbm_select(adev, 0, 0, 0, 0); 2738 2739 /* reset me pipe */ 2740 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2741 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2742 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2743 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2744 2745 /* clear me pipe reset */ 2746 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2747 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2748 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2749 2750 /* config mec program start addr */ 2751 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2752 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2753 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2754 mec_hdr->ucode_start_addr_lo >> 2 | 2755 mec_hdr->ucode_start_addr_hi << 30); 2756 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2757 mec_hdr->ucode_start_addr_hi >> 2); 2758 } 2759 soc21_grbm_select(adev, 0, 0, 0, 0); 2760 } 2761 2762 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2763 { 2764 uint32_t cp_status; 2765 uint32_t bootload_status; 2766 int i, r; 2767 uint64_t addr, addr2; 2768 2769 for (i = 0; i < adev->usec_timeout; i++) { 2770 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2771 2772 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1)) 2773 bootload_status = RREG32_SOC15(GC, 0, 2774 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2775 else 2776 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2777 2778 if ((cp_status == 0) && 2779 (REG_GET_FIELD(bootload_status, 2780 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2781 break; 2782 } 2783 udelay(1); 2784 } 2785 2786 if (i >= adev->usec_timeout) { 2787 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2788 return -ETIMEDOUT; 2789 } 2790 2791 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2792 if (adev->gfx.rs64_enable) { 2793 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2794 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2795 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2796 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2797 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2798 if (r) 2799 return r; 2800 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2801 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2802 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2803 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2804 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2805 if (r) 2806 return r; 2807 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2808 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2809 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2810 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2811 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2812 if (r) 2813 return r; 2814 } else { 2815 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2816 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2817 r = gfx_v11_0_config_me_cache(adev, addr); 2818 if (r) 2819 return r; 2820 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2821 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2822 r = gfx_v11_0_config_pfp_cache(adev, addr); 2823 if (r) 2824 return r; 2825 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2826 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2827 r = gfx_v11_0_config_mec_cache(adev, addr); 2828 if (r) 2829 return r; 2830 } 2831 } 2832 2833 return 0; 2834 } 2835 2836 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2837 { 2838 int i; 2839 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2840 2841 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2842 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2843 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2844 2845 for (i = 0; i < adev->usec_timeout; i++) { 2846 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2847 break; 2848 udelay(1); 2849 } 2850 2851 if (i >= adev->usec_timeout) 2852 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2853 2854 return 0; 2855 } 2856 2857 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2858 { 2859 int r; 2860 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2861 const __le32 *fw_data; 2862 unsigned i, fw_size; 2863 2864 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2865 adev->gfx.pfp_fw->data; 2866 2867 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2868 2869 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2870 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2871 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2872 2873 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2874 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2875 &adev->gfx.pfp.pfp_fw_obj, 2876 &adev->gfx.pfp.pfp_fw_gpu_addr, 2877 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2878 if (r) { 2879 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2880 gfx_v11_0_pfp_fini(adev); 2881 return r; 2882 } 2883 2884 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2885 2886 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2887 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2888 2889 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2890 2891 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2892 2893 for (i = 0; i < pfp_hdr->jt_size; i++) 2894 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2895 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2896 2897 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2898 2899 return 0; 2900 } 2901 2902 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2903 { 2904 int r; 2905 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2906 const __le32 *fw_ucode, *fw_data; 2907 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2908 uint32_t tmp; 2909 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2910 2911 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2912 adev->gfx.pfp_fw->data; 2913 2914 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2915 2916 /* instruction */ 2917 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2918 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2919 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2920 /* data */ 2921 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2922 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2923 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2924 2925 /* 64kb align */ 2926 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2927 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2928 &adev->gfx.pfp.pfp_fw_obj, 2929 &adev->gfx.pfp.pfp_fw_gpu_addr, 2930 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2931 if (r) { 2932 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2933 gfx_v11_0_pfp_fini(adev); 2934 return r; 2935 } 2936 2937 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2938 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2939 &adev->gfx.pfp.pfp_fw_data_obj, 2940 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2941 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2942 if (r) { 2943 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2944 gfx_v11_0_pfp_fini(adev); 2945 return r; 2946 } 2947 2948 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2949 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2950 2951 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2952 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2953 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2954 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2955 2956 if (amdgpu_emu_mode == 1) 2957 adev->hdp.funcs->flush_hdp(adev, NULL); 2958 2959 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2960 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2961 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2962 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2963 2964 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2965 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2966 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2967 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2968 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2969 2970 /* 2971 * Programming any of the CP_PFP_IC_BASE registers 2972 * forces invalidation of the ME L1 I$. Wait for the 2973 * invalidation complete 2974 */ 2975 for (i = 0; i < usec_timeout; i++) { 2976 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2977 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2978 INVALIDATE_CACHE_COMPLETE)) 2979 break; 2980 udelay(1); 2981 } 2982 2983 if (i >= usec_timeout) { 2984 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2985 return -EINVAL; 2986 } 2987 2988 /* Prime the L1 instruction caches */ 2989 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2990 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2991 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2992 /* Waiting for cache primed*/ 2993 for (i = 0; i < usec_timeout; i++) { 2994 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2995 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2996 ICACHE_PRIMED)) 2997 break; 2998 udelay(1); 2999 } 3000 3001 if (i >= usec_timeout) { 3002 dev_err(adev->dev, "failed to prime instruction cache\n"); 3003 return -EINVAL; 3004 } 3005 3006 mutex_lock(&adev->srbm_mutex); 3007 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3008 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3009 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3010 (pfp_hdr->ucode_start_addr_hi << 30) | 3011 (pfp_hdr->ucode_start_addr_lo >> 2) ); 3012 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3013 pfp_hdr->ucode_start_addr_hi>>2); 3014 3015 /* 3016 * Program CP_ME_CNTL to reset given PIPE to take 3017 * effect of CP_PFP_PRGRM_CNTR_START. 3018 */ 3019 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3020 if (pipe_id == 0) 3021 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3022 PFP_PIPE0_RESET, 1); 3023 else 3024 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3025 PFP_PIPE1_RESET, 1); 3026 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3027 3028 /* Clear pfp pipe0 reset bit. */ 3029 if (pipe_id == 0) 3030 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3031 PFP_PIPE0_RESET, 0); 3032 else 3033 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3034 PFP_PIPE1_RESET, 0); 3035 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3036 3037 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3038 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3039 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3040 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3041 } 3042 soc21_grbm_select(adev, 0, 0, 0, 0); 3043 mutex_unlock(&adev->srbm_mutex); 3044 3045 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3046 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3047 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3048 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3049 3050 /* Invalidate the data caches */ 3051 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3052 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3053 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3054 3055 for (i = 0; i < usec_timeout; i++) { 3056 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3057 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3058 INVALIDATE_DCACHE_COMPLETE)) 3059 break; 3060 udelay(1); 3061 } 3062 3063 if (i >= usec_timeout) { 3064 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3065 return -EINVAL; 3066 } 3067 3068 return 0; 3069 } 3070 3071 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3072 { 3073 int r; 3074 const struct gfx_firmware_header_v1_0 *me_hdr; 3075 const __le32 *fw_data; 3076 unsigned i, fw_size; 3077 3078 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3079 adev->gfx.me_fw->data; 3080 3081 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3082 3083 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3084 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3085 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3086 3087 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3088 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3089 &adev->gfx.me.me_fw_obj, 3090 &adev->gfx.me.me_fw_gpu_addr, 3091 (void **)&adev->gfx.me.me_fw_ptr); 3092 if (r) { 3093 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3094 gfx_v11_0_me_fini(adev); 3095 return r; 3096 } 3097 3098 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3099 3100 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3101 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3102 3103 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3104 3105 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3106 3107 for (i = 0; i < me_hdr->jt_size; i++) 3108 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3109 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3110 3111 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3112 3113 return 0; 3114 } 3115 3116 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3117 { 3118 int r; 3119 const struct gfx_firmware_header_v2_0 *me_hdr; 3120 const __le32 *fw_ucode, *fw_data; 3121 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3122 uint32_t tmp; 3123 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3124 3125 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3126 adev->gfx.me_fw->data; 3127 3128 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3129 3130 /* instruction */ 3131 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3132 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3133 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3134 /* data */ 3135 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3136 le32_to_cpu(me_hdr->data_offset_bytes)); 3137 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3138 3139 /* 64kb align*/ 3140 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3141 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3142 &adev->gfx.me.me_fw_obj, 3143 &adev->gfx.me.me_fw_gpu_addr, 3144 (void **)&adev->gfx.me.me_fw_ptr); 3145 if (r) { 3146 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3147 gfx_v11_0_me_fini(adev); 3148 return r; 3149 } 3150 3151 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3152 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3153 &adev->gfx.me.me_fw_data_obj, 3154 &adev->gfx.me.me_fw_data_gpu_addr, 3155 (void **)&adev->gfx.me.me_fw_data_ptr); 3156 if (r) { 3157 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3158 gfx_v11_0_pfp_fini(adev); 3159 return r; 3160 } 3161 3162 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3163 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3164 3165 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3166 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3167 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3168 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3169 3170 if (amdgpu_emu_mode == 1) 3171 adev->hdp.funcs->flush_hdp(adev, NULL); 3172 3173 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3174 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3175 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3176 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3177 3178 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3179 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3180 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3181 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3182 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3183 3184 /* 3185 * Programming any of the CP_ME_IC_BASE registers 3186 * forces invalidation of the ME L1 I$. Wait for the 3187 * invalidation complete 3188 */ 3189 for (i = 0; i < usec_timeout; i++) { 3190 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3191 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3192 INVALIDATE_CACHE_COMPLETE)) 3193 break; 3194 udelay(1); 3195 } 3196 3197 if (i >= usec_timeout) { 3198 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3199 return -EINVAL; 3200 } 3201 3202 /* Prime the instruction caches */ 3203 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3204 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3205 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3206 3207 /* Waiting for instruction cache primed*/ 3208 for (i = 0; i < usec_timeout; i++) { 3209 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3210 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3211 ICACHE_PRIMED)) 3212 break; 3213 udelay(1); 3214 } 3215 3216 if (i >= usec_timeout) { 3217 dev_err(adev->dev, "failed to prime instruction cache\n"); 3218 return -EINVAL; 3219 } 3220 3221 mutex_lock(&adev->srbm_mutex); 3222 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3223 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3224 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3225 (me_hdr->ucode_start_addr_hi << 30) | 3226 (me_hdr->ucode_start_addr_lo >> 2) ); 3227 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3228 me_hdr->ucode_start_addr_hi>>2); 3229 3230 /* 3231 * Program CP_ME_CNTL to reset given PIPE to take 3232 * effect of CP_PFP_PRGRM_CNTR_START. 3233 */ 3234 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3235 if (pipe_id == 0) 3236 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3237 ME_PIPE0_RESET, 1); 3238 else 3239 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3240 ME_PIPE1_RESET, 1); 3241 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3242 3243 /* Clear pfp pipe0 reset bit. */ 3244 if (pipe_id == 0) 3245 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3246 ME_PIPE0_RESET, 0); 3247 else 3248 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3249 ME_PIPE1_RESET, 0); 3250 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3251 3252 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3253 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3254 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3255 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3256 } 3257 soc21_grbm_select(adev, 0, 0, 0, 0); 3258 mutex_unlock(&adev->srbm_mutex); 3259 3260 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3261 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3262 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3263 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3264 3265 /* Invalidate the data caches */ 3266 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3267 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3268 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3269 3270 for (i = 0; i < usec_timeout; i++) { 3271 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3272 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3273 INVALIDATE_DCACHE_COMPLETE)) 3274 break; 3275 udelay(1); 3276 } 3277 3278 if (i >= usec_timeout) { 3279 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3280 return -EINVAL; 3281 } 3282 3283 return 0; 3284 } 3285 3286 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3287 { 3288 int r; 3289 3290 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3291 return -EINVAL; 3292 3293 gfx_v11_0_cp_gfx_enable(adev, false); 3294 3295 if (adev->gfx.rs64_enable) 3296 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3297 else 3298 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3299 if (r) { 3300 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3301 return r; 3302 } 3303 3304 if (adev->gfx.rs64_enable) 3305 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3306 else 3307 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3308 if (r) { 3309 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3310 return r; 3311 } 3312 3313 return 0; 3314 } 3315 3316 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3317 { 3318 struct amdgpu_ring *ring; 3319 const struct cs_section_def *sect = NULL; 3320 const struct cs_extent_def *ext = NULL; 3321 int r, i; 3322 int ctx_reg_offset; 3323 3324 /* init the CP */ 3325 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3326 adev->gfx.config.max_hw_contexts - 1); 3327 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3328 3329 if (!amdgpu_async_gfx_ring) 3330 gfx_v11_0_cp_gfx_enable(adev, true); 3331 3332 ring = &adev->gfx.gfx_ring[0]; 3333 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3334 if (r) { 3335 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3336 return r; 3337 } 3338 3339 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3340 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3341 3342 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3343 amdgpu_ring_write(ring, 0x80000000); 3344 amdgpu_ring_write(ring, 0x80000000); 3345 3346 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3347 for (ext = sect->section; ext->extent != NULL; ++ext) { 3348 if (sect->id == SECT_CONTEXT) { 3349 amdgpu_ring_write(ring, 3350 PACKET3(PACKET3_SET_CONTEXT_REG, 3351 ext->reg_count)); 3352 amdgpu_ring_write(ring, ext->reg_index - 3353 PACKET3_SET_CONTEXT_REG_START); 3354 for (i = 0; i < ext->reg_count; i++) 3355 amdgpu_ring_write(ring, ext->extent[i]); 3356 } 3357 } 3358 } 3359 3360 ctx_reg_offset = 3361 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3362 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3363 amdgpu_ring_write(ring, ctx_reg_offset); 3364 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3365 3366 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3367 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3368 3369 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3370 amdgpu_ring_write(ring, 0); 3371 3372 amdgpu_ring_commit(ring); 3373 3374 /* submit cs packet to copy state 0 to next available state */ 3375 if (adev->gfx.num_gfx_rings > 1) { 3376 /* maximum supported gfx ring is 2 */ 3377 ring = &adev->gfx.gfx_ring[1]; 3378 r = amdgpu_ring_alloc(ring, 2); 3379 if (r) { 3380 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3381 return r; 3382 } 3383 3384 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3385 amdgpu_ring_write(ring, 0); 3386 3387 amdgpu_ring_commit(ring); 3388 } 3389 return 0; 3390 } 3391 3392 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3393 CP_PIPE_ID pipe) 3394 { 3395 u32 tmp; 3396 3397 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3398 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3399 3400 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3401 } 3402 3403 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3404 struct amdgpu_ring *ring) 3405 { 3406 u32 tmp; 3407 3408 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3409 if (ring->use_doorbell) { 3410 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3411 DOORBELL_OFFSET, ring->doorbell_index); 3412 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3413 DOORBELL_EN, 1); 3414 } else { 3415 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3416 DOORBELL_EN, 0); 3417 } 3418 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3419 3420 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3421 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3422 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3423 3424 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3425 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3426 } 3427 3428 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3429 { 3430 struct amdgpu_ring *ring; 3431 u32 tmp; 3432 u32 rb_bufsz; 3433 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3434 u32 i; 3435 3436 /* Set the write pointer delay */ 3437 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3438 3439 /* set the RB to use vmid 0 */ 3440 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3441 3442 /* Init gfx ring 0 for pipe 0 */ 3443 mutex_lock(&adev->srbm_mutex); 3444 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3445 3446 /* Set ring buffer size */ 3447 ring = &adev->gfx.gfx_ring[0]; 3448 rb_bufsz = order_base_2(ring->ring_size / 8); 3449 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3450 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3451 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3452 3453 /* Initialize the ring buffer's write pointers */ 3454 ring->wptr = 0; 3455 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3456 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3457 3458 /* set the wb address wether it's enabled or not */ 3459 rptr_addr = ring->rptr_gpu_addr; 3460 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3461 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3462 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3463 3464 wptr_gpu_addr = ring->wptr_gpu_addr; 3465 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3466 lower_32_bits(wptr_gpu_addr)); 3467 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3468 upper_32_bits(wptr_gpu_addr)); 3469 3470 mdelay(1); 3471 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3472 3473 rb_addr = ring->gpu_addr >> 8; 3474 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3475 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3476 3477 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3478 3479 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3480 mutex_unlock(&adev->srbm_mutex); 3481 3482 /* Init gfx ring 1 for pipe 1 */ 3483 if (adev->gfx.num_gfx_rings > 1) { 3484 mutex_lock(&adev->srbm_mutex); 3485 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3486 /* maximum supported gfx ring is 2 */ 3487 ring = &adev->gfx.gfx_ring[1]; 3488 rb_bufsz = order_base_2(ring->ring_size / 8); 3489 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3490 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3491 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3492 /* Initialize the ring buffer's write pointers */ 3493 ring->wptr = 0; 3494 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3495 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3496 /* Set the wb address wether it's enabled or not */ 3497 rptr_addr = ring->rptr_gpu_addr; 3498 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3499 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3500 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3501 wptr_gpu_addr = ring->wptr_gpu_addr; 3502 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3503 lower_32_bits(wptr_gpu_addr)); 3504 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3505 upper_32_bits(wptr_gpu_addr)); 3506 3507 mdelay(1); 3508 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3509 3510 rb_addr = ring->gpu_addr >> 8; 3511 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3512 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3513 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3514 3515 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3516 mutex_unlock(&adev->srbm_mutex); 3517 } 3518 /* Switch to pipe 0 */ 3519 mutex_lock(&adev->srbm_mutex); 3520 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3521 mutex_unlock(&adev->srbm_mutex); 3522 3523 /* start the ring */ 3524 gfx_v11_0_cp_gfx_start(adev); 3525 3526 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3527 ring = &adev->gfx.gfx_ring[i]; 3528 ring->sched.ready = true; 3529 } 3530 3531 return 0; 3532 } 3533 3534 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3535 { 3536 u32 data; 3537 3538 if (adev->gfx.rs64_enable) { 3539 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3540 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3541 enable ? 0 : 1); 3542 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3543 enable ? 0 : 1); 3544 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3545 enable ? 0 : 1); 3546 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3547 enable ? 0 : 1); 3548 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3549 enable ? 0 : 1); 3550 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3551 enable ? 1 : 0); 3552 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3553 enable ? 1 : 0); 3554 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3555 enable ? 1 : 0); 3556 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3557 enable ? 1 : 0); 3558 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3559 enable ? 0 : 1); 3560 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3561 } else { 3562 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3563 3564 if (enable) { 3565 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3566 if (!adev->enable_mes_kiq) 3567 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3568 MEC_ME2_HALT, 0); 3569 } else { 3570 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3571 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3572 } 3573 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3574 } 3575 3576 adev->gfx.kiq.ring.sched.ready = enable; 3577 3578 udelay(50); 3579 } 3580 3581 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3582 { 3583 const struct gfx_firmware_header_v1_0 *mec_hdr; 3584 const __le32 *fw_data; 3585 unsigned i, fw_size; 3586 u32 *fw = NULL; 3587 int r; 3588 3589 if (!adev->gfx.mec_fw) 3590 return -EINVAL; 3591 3592 gfx_v11_0_cp_compute_enable(adev, false); 3593 3594 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3595 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3596 3597 fw_data = (const __le32 *) 3598 (adev->gfx.mec_fw->data + 3599 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3600 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3601 3602 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3603 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3604 &adev->gfx.mec.mec_fw_obj, 3605 &adev->gfx.mec.mec_fw_gpu_addr, 3606 (void **)&fw); 3607 if (r) { 3608 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3609 gfx_v11_0_mec_fini(adev); 3610 return r; 3611 } 3612 3613 memcpy(fw, fw_data, fw_size); 3614 3615 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3616 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3617 3618 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3619 3620 /* MEC1 */ 3621 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3622 3623 for (i = 0; i < mec_hdr->jt_size; i++) 3624 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3625 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3626 3627 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3628 3629 return 0; 3630 } 3631 3632 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3633 { 3634 const struct gfx_firmware_header_v2_0 *mec_hdr; 3635 const __le32 *fw_ucode, *fw_data; 3636 u32 tmp, fw_ucode_size, fw_data_size; 3637 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3638 u32 *fw_ucode_ptr, *fw_data_ptr; 3639 int r; 3640 3641 if (!adev->gfx.mec_fw) 3642 return -EINVAL; 3643 3644 gfx_v11_0_cp_compute_enable(adev, false); 3645 3646 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3647 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3648 3649 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3650 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3651 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3652 3653 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3654 le32_to_cpu(mec_hdr->data_offset_bytes)); 3655 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3656 3657 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3658 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3659 &adev->gfx.mec.mec_fw_obj, 3660 &adev->gfx.mec.mec_fw_gpu_addr, 3661 (void **)&fw_ucode_ptr); 3662 if (r) { 3663 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3664 gfx_v11_0_mec_fini(adev); 3665 return r; 3666 } 3667 3668 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3669 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3670 &adev->gfx.mec.mec_fw_data_obj, 3671 &adev->gfx.mec.mec_fw_data_gpu_addr, 3672 (void **)&fw_data_ptr); 3673 if (r) { 3674 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3675 gfx_v11_0_mec_fini(adev); 3676 return r; 3677 } 3678 3679 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3680 memcpy(fw_data_ptr, fw_data, fw_data_size); 3681 3682 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3683 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3684 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3685 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3686 3687 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3688 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3689 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3690 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3691 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3692 3693 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3694 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3695 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3696 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3697 3698 mutex_lock(&adev->srbm_mutex); 3699 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3700 soc21_grbm_select(adev, 1, i, 0, 0); 3701 3702 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3703 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3704 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3705 3706 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3707 mec_hdr->ucode_start_addr_lo >> 2 | 3708 mec_hdr->ucode_start_addr_hi << 30); 3709 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3710 mec_hdr->ucode_start_addr_hi >> 2); 3711 3712 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3713 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3714 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3715 } 3716 mutex_unlock(&adev->srbm_mutex); 3717 soc21_grbm_select(adev, 0, 0, 0, 0); 3718 3719 /* Trigger an invalidation of the L1 instruction caches */ 3720 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3721 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3722 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3723 3724 /* Wait for invalidation complete */ 3725 for (i = 0; i < usec_timeout; i++) { 3726 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3727 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3728 INVALIDATE_DCACHE_COMPLETE)) 3729 break; 3730 udelay(1); 3731 } 3732 3733 if (i >= usec_timeout) { 3734 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3735 return -EINVAL; 3736 } 3737 3738 /* Trigger an invalidation of the L1 instruction caches */ 3739 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3740 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3741 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3742 3743 /* Wait for invalidation complete */ 3744 for (i = 0; i < usec_timeout; i++) { 3745 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3746 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3747 INVALIDATE_CACHE_COMPLETE)) 3748 break; 3749 udelay(1); 3750 } 3751 3752 if (i >= usec_timeout) { 3753 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3754 return -EINVAL; 3755 } 3756 3757 return 0; 3758 } 3759 3760 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3761 { 3762 uint32_t tmp; 3763 struct amdgpu_device *adev = ring->adev; 3764 3765 /* tell RLC which is KIQ queue */ 3766 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3767 tmp &= 0xffffff00; 3768 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3769 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3770 tmp |= 0x80; 3771 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3772 } 3773 3774 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3775 { 3776 /* set graphics engine doorbell range */ 3777 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3778 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3779 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3780 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3781 3782 /* set compute engine doorbell range */ 3783 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3784 (adev->doorbell_index.kiq * 2) << 2); 3785 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3786 (adev->doorbell_index.userqueue_end * 2) << 2); 3787 } 3788 3789 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3790 struct amdgpu_mqd_prop *prop) 3791 { 3792 struct v11_gfx_mqd *mqd = m; 3793 uint64_t hqd_gpu_addr, wb_gpu_addr; 3794 uint32_t tmp; 3795 uint32_t rb_bufsz; 3796 3797 /* set up gfx hqd wptr */ 3798 mqd->cp_gfx_hqd_wptr = 0; 3799 mqd->cp_gfx_hqd_wptr_hi = 0; 3800 3801 /* set the pointer to the MQD */ 3802 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3803 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3804 3805 /* set up mqd control */ 3806 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3807 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3808 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3809 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3810 mqd->cp_gfx_mqd_control = tmp; 3811 3812 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3813 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3814 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3815 mqd->cp_gfx_hqd_vmid = 0; 3816 3817 /* set up default queue priority level 3818 * 0x0 = low priority, 0x1 = high priority */ 3819 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3820 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3821 mqd->cp_gfx_hqd_queue_priority = tmp; 3822 3823 /* set up time quantum */ 3824 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3825 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3826 mqd->cp_gfx_hqd_quantum = tmp; 3827 3828 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3829 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3830 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3831 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3832 3833 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3834 wb_gpu_addr = prop->rptr_gpu_addr; 3835 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3836 mqd->cp_gfx_hqd_rptr_addr_hi = 3837 upper_32_bits(wb_gpu_addr) & 0xffff; 3838 3839 /* set up rb_wptr_poll addr */ 3840 wb_gpu_addr = prop->wptr_gpu_addr; 3841 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3842 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3843 3844 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3845 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3846 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3847 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3848 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3849 #ifdef __BIG_ENDIAN 3850 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3851 #endif 3852 mqd->cp_gfx_hqd_cntl = tmp; 3853 3854 /* set up cp_doorbell_control */ 3855 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3856 if (prop->use_doorbell) { 3857 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3858 DOORBELL_OFFSET, prop->doorbell_index); 3859 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3860 DOORBELL_EN, 1); 3861 } else 3862 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3863 DOORBELL_EN, 0); 3864 mqd->cp_rb_doorbell_control = tmp; 3865 3866 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3867 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3868 3869 /* active the queue */ 3870 mqd->cp_gfx_hqd_active = 1; 3871 3872 return 0; 3873 } 3874 3875 #ifdef BRING_UP_DEBUG 3876 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3877 { 3878 struct amdgpu_device *adev = ring->adev; 3879 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3880 3881 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3882 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3883 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3884 3885 /* set GFX_MQD_BASE */ 3886 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3887 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3888 3889 /* set GFX_MQD_CONTROL */ 3890 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3891 3892 /* set GFX_HQD_VMID to 0 */ 3893 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3894 3895 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY, 3896 mqd->cp_gfx_hqd_queue_priority); 3897 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3898 3899 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3900 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3901 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3902 3903 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3904 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3905 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3906 3907 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3908 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3909 3910 /* set RB_WPTR_POLL_ADDR */ 3911 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3912 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3913 3914 /* set RB_DOORBELL_CONTROL */ 3915 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3916 3917 /* active the queue */ 3918 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3919 3920 return 0; 3921 } 3922 #endif 3923 3924 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3925 { 3926 struct amdgpu_device *adev = ring->adev; 3927 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3928 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3929 3930 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3931 memset((void *)mqd, 0, sizeof(*mqd)); 3932 mutex_lock(&adev->srbm_mutex); 3933 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3934 amdgpu_ring_init_mqd(ring); 3935 #ifdef BRING_UP_DEBUG 3936 gfx_v11_0_gfx_queue_init_register(ring); 3937 #endif 3938 soc21_grbm_select(adev, 0, 0, 0, 0); 3939 mutex_unlock(&adev->srbm_mutex); 3940 if (adev->gfx.me.mqd_backup[mqd_idx]) 3941 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3942 } else if (amdgpu_in_reset(adev)) { 3943 /* reset mqd with the backup copy */ 3944 if (adev->gfx.me.mqd_backup[mqd_idx]) 3945 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3946 /* reset the ring */ 3947 ring->wptr = 0; 3948 *ring->wptr_cpu_addr = 0; 3949 amdgpu_ring_clear_ring(ring); 3950 #ifdef BRING_UP_DEBUG 3951 mutex_lock(&adev->srbm_mutex); 3952 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3953 gfx_v11_0_gfx_queue_init_register(ring); 3954 soc21_grbm_select(adev, 0, 0, 0, 0); 3955 mutex_unlock(&adev->srbm_mutex); 3956 #endif 3957 } else { 3958 amdgpu_ring_clear_ring(ring); 3959 } 3960 3961 return 0; 3962 } 3963 3964 #ifndef BRING_UP_DEBUG 3965 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev) 3966 { 3967 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3968 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3969 int r, i; 3970 3971 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3972 return -EINVAL; 3973 3974 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3975 adev->gfx.num_gfx_rings); 3976 if (r) { 3977 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3978 return r; 3979 } 3980 3981 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3982 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3983 3984 return amdgpu_ring_test_helper(kiq_ring); 3985 } 3986 #endif 3987 3988 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3989 { 3990 int r, i; 3991 struct amdgpu_ring *ring; 3992 3993 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3994 ring = &adev->gfx.gfx_ring[i]; 3995 3996 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3997 if (unlikely(r != 0)) 3998 goto done; 3999 4000 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4001 if (!r) { 4002 r = gfx_v11_0_gfx_init_queue(ring); 4003 amdgpu_bo_kunmap(ring->mqd_obj); 4004 ring->mqd_ptr = NULL; 4005 } 4006 amdgpu_bo_unreserve(ring->mqd_obj); 4007 if (r) 4008 goto done; 4009 } 4010 #ifndef BRING_UP_DEBUG 4011 r = gfx_v11_0_kiq_enable_kgq(adev); 4012 if (r) 4013 goto done; 4014 #endif 4015 r = gfx_v11_0_cp_gfx_start(adev); 4016 if (r) 4017 goto done; 4018 4019 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4020 ring = &adev->gfx.gfx_ring[i]; 4021 ring->sched.ready = true; 4022 } 4023 done: 4024 return r; 4025 } 4026 4027 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4028 struct amdgpu_mqd_prop *prop) 4029 { 4030 struct v11_compute_mqd *mqd = m; 4031 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4032 uint32_t tmp; 4033 4034 mqd->header = 0xC0310800; 4035 mqd->compute_pipelinestat_enable = 0x00000001; 4036 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4037 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4038 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4039 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4040 mqd->compute_misc_reserved = 0x00000007; 4041 4042 eop_base_addr = prop->eop_gpu_addr >> 8; 4043 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4044 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4045 4046 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4047 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 4048 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4049 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4050 4051 mqd->cp_hqd_eop_control = tmp; 4052 4053 /* enable doorbell? */ 4054 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4055 4056 if (prop->use_doorbell) { 4057 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4058 DOORBELL_OFFSET, prop->doorbell_index); 4059 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4060 DOORBELL_EN, 1); 4061 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4062 DOORBELL_SOURCE, 0); 4063 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4064 DOORBELL_HIT, 0); 4065 } else { 4066 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4067 DOORBELL_EN, 0); 4068 } 4069 4070 mqd->cp_hqd_pq_doorbell_control = tmp; 4071 4072 /* disable the queue if it's active */ 4073 mqd->cp_hqd_dequeue_request = 0; 4074 mqd->cp_hqd_pq_rptr = 0; 4075 mqd->cp_hqd_pq_wptr_lo = 0; 4076 mqd->cp_hqd_pq_wptr_hi = 0; 4077 4078 /* set the pointer to the MQD */ 4079 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4080 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4081 4082 /* set MQD vmid to 0 */ 4083 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 4084 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4085 mqd->cp_mqd_control = tmp; 4086 4087 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4088 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4089 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4090 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4091 4092 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4093 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 4094 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4095 (order_base_2(prop->queue_size / 4) - 1)); 4096 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4097 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4098 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 4099 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 4100 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4101 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4102 mqd->cp_hqd_pq_control = tmp; 4103 4104 /* set the wb address whether it's enabled or not */ 4105 wb_gpu_addr = prop->rptr_gpu_addr; 4106 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4107 mqd->cp_hqd_pq_rptr_report_addr_hi = 4108 upper_32_bits(wb_gpu_addr) & 0xffff; 4109 4110 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4111 wb_gpu_addr = prop->wptr_gpu_addr; 4112 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4113 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4114 4115 tmp = 0; 4116 /* enable the doorbell if requested */ 4117 if (prop->use_doorbell) { 4118 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4119 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4120 DOORBELL_OFFSET, prop->doorbell_index); 4121 4122 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4123 DOORBELL_EN, 1); 4124 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4125 DOORBELL_SOURCE, 0); 4126 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4127 DOORBELL_HIT, 0); 4128 } 4129 4130 mqd->cp_hqd_pq_doorbell_control = tmp; 4131 4132 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4133 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 4134 4135 /* set the vmid for the queue */ 4136 mqd->cp_hqd_vmid = 0; 4137 4138 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 4139 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4140 mqd->cp_hqd_persistent_state = tmp; 4141 4142 /* set MIN_IB_AVAIL_SIZE */ 4143 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 4144 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4145 mqd->cp_hqd_ib_control = tmp; 4146 4147 /* set static priority for a compute queue/ring */ 4148 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4149 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4150 4151 mqd->cp_hqd_active = prop->hqd_active; 4152 4153 return 0; 4154 } 4155 4156 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4157 { 4158 struct amdgpu_device *adev = ring->adev; 4159 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4160 int j; 4161 4162 /* inactivate the queue */ 4163 if (amdgpu_sriov_vf(adev)) 4164 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4165 4166 /* disable wptr polling */ 4167 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4168 4169 /* write the EOP addr */ 4170 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4171 mqd->cp_hqd_eop_base_addr_lo); 4172 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4173 mqd->cp_hqd_eop_base_addr_hi); 4174 4175 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4176 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4177 mqd->cp_hqd_eop_control); 4178 4179 /* enable doorbell? */ 4180 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4181 mqd->cp_hqd_pq_doorbell_control); 4182 4183 /* disable the queue if it's active */ 4184 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4185 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4186 for (j = 0; j < adev->usec_timeout; j++) { 4187 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4188 break; 4189 udelay(1); 4190 } 4191 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4192 mqd->cp_hqd_dequeue_request); 4193 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4194 mqd->cp_hqd_pq_rptr); 4195 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4196 mqd->cp_hqd_pq_wptr_lo); 4197 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4198 mqd->cp_hqd_pq_wptr_hi); 4199 } 4200 4201 /* set the pointer to the MQD */ 4202 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4203 mqd->cp_mqd_base_addr_lo); 4204 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4205 mqd->cp_mqd_base_addr_hi); 4206 4207 /* set MQD vmid to 0 */ 4208 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4209 mqd->cp_mqd_control); 4210 4211 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4212 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4213 mqd->cp_hqd_pq_base_lo); 4214 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4215 mqd->cp_hqd_pq_base_hi); 4216 4217 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4218 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4219 mqd->cp_hqd_pq_control); 4220 4221 /* set the wb address whether it's enabled or not */ 4222 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4223 mqd->cp_hqd_pq_rptr_report_addr_lo); 4224 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4225 mqd->cp_hqd_pq_rptr_report_addr_hi); 4226 4227 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4228 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4229 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4230 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4231 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4232 4233 /* enable the doorbell if requested */ 4234 if (ring->use_doorbell) { 4235 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4236 (adev->doorbell_index.kiq * 2) << 2); 4237 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4238 (adev->doorbell_index.userqueue_end * 2) << 2); 4239 } 4240 4241 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4242 mqd->cp_hqd_pq_doorbell_control); 4243 4244 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4245 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4246 mqd->cp_hqd_pq_wptr_lo); 4247 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4248 mqd->cp_hqd_pq_wptr_hi); 4249 4250 /* set the vmid for the queue */ 4251 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4252 4253 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4254 mqd->cp_hqd_persistent_state); 4255 4256 /* activate the queue */ 4257 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4258 mqd->cp_hqd_active); 4259 4260 if (ring->use_doorbell) 4261 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4262 4263 return 0; 4264 } 4265 4266 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4267 { 4268 struct amdgpu_device *adev = ring->adev; 4269 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4270 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 4271 4272 gfx_v11_0_kiq_setting(ring); 4273 4274 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4275 /* reset MQD to a clean status */ 4276 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4277 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4278 4279 /* reset ring buffer */ 4280 ring->wptr = 0; 4281 amdgpu_ring_clear_ring(ring); 4282 4283 mutex_lock(&adev->srbm_mutex); 4284 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4285 gfx_v11_0_kiq_init_register(ring); 4286 soc21_grbm_select(adev, 0, 0, 0, 0); 4287 mutex_unlock(&adev->srbm_mutex); 4288 } else { 4289 memset((void *)mqd, 0, sizeof(*mqd)); 4290 mutex_lock(&adev->srbm_mutex); 4291 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4292 amdgpu_ring_init_mqd(ring); 4293 gfx_v11_0_kiq_init_register(ring); 4294 soc21_grbm_select(adev, 0, 0, 0, 0); 4295 mutex_unlock(&adev->srbm_mutex); 4296 4297 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4298 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4299 } 4300 4301 return 0; 4302 } 4303 4304 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4305 { 4306 struct amdgpu_device *adev = ring->adev; 4307 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4308 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4309 4310 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4311 memset((void *)mqd, 0, sizeof(*mqd)); 4312 mutex_lock(&adev->srbm_mutex); 4313 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4314 amdgpu_ring_init_mqd(ring); 4315 soc21_grbm_select(adev, 0, 0, 0, 0); 4316 mutex_unlock(&adev->srbm_mutex); 4317 4318 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4319 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4320 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4321 /* reset MQD to a clean status */ 4322 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4323 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4324 4325 /* reset ring buffer */ 4326 ring->wptr = 0; 4327 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4328 amdgpu_ring_clear_ring(ring); 4329 } else { 4330 amdgpu_ring_clear_ring(ring); 4331 } 4332 4333 return 0; 4334 } 4335 4336 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4337 { 4338 struct amdgpu_ring *ring; 4339 int r; 4340 4341 ring = &adev->gfx.kiq.ring; 4342 4343 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4344 if (unlikely(r != 0)) 4345 return r; 4346 4347 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4348 if (unlikely(r != 0)) { 4349 amdgpu_bo_unreserve(ring->mqd_obj); 4350 return r; 4351 } 4352 4353 gfx_v11_0_kiq_init_queue(ring); 4354 amdgpu_bo_kunmap(ring->mqd_obj); 4355 ring->mqd_ptr = NULL; 4356 amdgpu_bo_unreserve(ring->mqd_obj); 4357 ring->sched.ready = true; 4358 return 0; 4359 } 4360 4361 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4362 { 4363 struct amdgpu_ring *ring = NULL; 4364 int r = 0, i; 4365 4366 if (!amdgpu_async_gfx_ring) 4367 gfx_v11_0_cp_compute_enable(adev, true); 4368 4369 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4370 ring = &adev->gfx.compute_ring[i]; 4371 4372 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4373 if (unlikely(r != 0)) 4374 goto done; 4375 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4376 if (!r) { 4377 r = gfx_v11_0_kcq_init_queue(ring); 4378 amdgpu_bo_kunmap(ring->mqd_obj); 4379 ring->mqd_ptr = NULL; 4380 } 4381 amdgpu_bo_unreserve(ring->mqd_obj); 4382 if (r) 4383 goto done; 4384 } 4385 4386 r = amdgpu_gfx_enable_kcq(adev); 4387 done: 4388 return r; 4389 } 4390 4391 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4392 { 4393 int r, i; 4394 struct amdgpu_ring *ring; 4395 4396 if (!(adev->flags & AMD_IS_APU)) 4397 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4398 4399 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4400 /* legacy firmware loading */ 4401 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4402 if (r) 4403 return r; 4404 4405 if (adev->gfx.rs64_enable) 4406 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4407 else 4408 r = gfx_v11_0_cp_compute_load_microcode(adev); 4409 if (r) 4410 return r; 4411 } 4412 4413 gfx_v11_0_cp_set_doorbell_range(adev); 4414 4415 if (amdgpu_async_gfx_ring) { 4416 gfx_v11_0_cp_compute_enable(adev, true); 4417 gfx_v11_0_cp_gfx_enable(adev, true); 4418 } 4419 4420 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4421 r = amdgpu_mes_kiq_hw_init(adev); 4422 else 4423 r = gfx_v11_0_kiq_resume(adev); 4424 if (r) 4425 return r; 4426 4427 r = gfx_v11_0_kcq_resume(adev); 4428 if (r) 4429 return r; 4430 4431 if (!amdgpu_async_gfx_ring) { 4432 r = gfx_v11_0_cp_gfx_resume(adev); 4433 if (r) 4434 return r; 4435 } else { 4436 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4437 if (r) 4438 return r; 4439 } 4440 4441 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4442 ring = &adev->gfx.gfx_ring[i]; 4443 r = amdgpu_ring_test_helper(ring); 4444 if (r) 4445 return r; 4446 } 4447 4448 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4449 ring = &adev->gfx.compute_ring[i]; 4450 r = amdgpu_ring_test_helper(ring); 4451 if (r) 4452 return r; 4453 } 4454 4455 return 0; 4456 } 4457 4458 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4459 { 4460 gfx_v11_0_cp_gfx_enable(adev, enable); 4461 gfx_v11_0_cp_compute_enable(adev, enable); 4462 } 4463 4464 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4465 { 4466 int r; 4467 bool value; 4468 4469 r = adev->gfxhub.funcs->gart_enable(adev); 4470 if (r) 4471 return r; 4472 4473 adev->hdp.funcs->flush_hdp(adev, NULL); 4474 4475 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4476 false : true; 4477 4478 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4479 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 4480 4481 return 0; 4482 } 4483 4484 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4485 { 4486 u32 tmp; 4487 4488 /* select RS64 */ 4489 if (adev->gfx.rs64_enable) { 4490 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4491 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4492 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4493 4494 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4495 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4496 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4497 } 4498 4499 if (amdgpu_emu_mode == 1) 4500 msleep(100); 4501 } 4502 4503 static int get_gb_addr_config(struct amdgpu_device * adev) 4504 { 4505 u32 gb_addr_config; 4506 4507 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4508 if (gb_addr_config == 0) 4509 return -EINVAL; 4510 4511 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4512 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4513 4514 adev->gfx.config.gb_addr_config = gb_addr_config; 4515 4516 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4517 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4518 GB_ADDR_CONFIG, NUM_PIPES); 4519 4520 adev->gfx.config.max_tile_pipes = 4521 adev->gfx.config.gb_addr_config_fields.num_pipes; 4522 4523 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4524 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4525 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4526 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4527 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4528 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4529 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4530 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4531 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4532 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4533 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4534 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4535 4536 return 0; 4537 } 4538 4539 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4540 { 4541 uint32_t data; 4542 4543 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4544 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4545 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4546 4547 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4548 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4549 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4550 } 4551 4552 static int gfx_v11_0_hw_init(void *handle) 4553 { 4554 int r; 4555 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4556 4557 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4558 if (adev->gfx.imu.funcs) { 4559 /* RLC autoload sequence 1: Program rlc ram */ 4560 if (adev->gfx.imu.funcs->program_rlc_ram) 4561 adev->gfx.imu.funcs->program_rlc_ram(adev); 4562 } 4563 /* rlc autoload firmware */ 4564 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4565 if (r) 4566 return r; 4567 } else { 4568 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4569 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4570 if (adev->gfx.imu.funcs->load_microcode) 4571 adev->gfx.imu.funcs->load_microcode(adev); 4572 if (adev->gfx.imu.funcs->setup_imu) 4573 adev->gfx.imu.funcs->setup_imu(adev); 4574 if (adev->gfx.imu.funcs->start_imu) 4575 adev->gfx.imu.funcs->start_imu(adev); 4576 } 4577 4578 /* disable gpa mode in backdoor loading */ 4579 gfx_v11_0_disable_gpa_mode(adev); 4580 } 4581 } 4582 4583 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4584 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4585 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4586 if (r) { 4587 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4588 return r; 4589 } 4590 } 4591 4592 adev->gfx.is_poweron = true; 4593 4594 if(get_gb_addr_config(adev)) 4595 DRM_WARN("Invalid gb_addr_config !\n"); 4596 4597 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4598 adev->gfx.rs64_enable) 4599 gfx_v11_0_config_gfx_rs64(adev); 4600 4601 r = gfx_v11_0_gfxhub_enable(adev); 4602 if (r) 4603 return r; 4604 4605 if (!amdgpu_emu_mode) 4606 gfx_v11_0_init_golden_registers(adev); 4607 4608 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4609 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4610 /** 4611 * For gfx 11, rlc firmware loading relies on smu firmware is 4612 * loaded firstly, so in direct type, it has to load smc ucode 4613 * here before rlc. 4614 */ 4615 if (!(adev->flags & AMD_IS_APU)) { 4616 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4617 if (r) 4618 return r; 4619 } 4620 } 4621 4622 gfx_v11_0_constants_init(adev); 4623 4624 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4625 gfx_v11_0_select_cp_fw_arch(adev); 4626 4627 if (adev->nbio.funcs->gc_doorbell_init) 4628 adev->nbio.funcs->gc_doorbell_init(adev); 4629 4630 r = gfx_v11_0_rlc_resume(adev); 4631 if (r) 4632 return r; 4633 4634 /* 4635 * init golden registers and rlc resume may override some registers, 4636 * reconfig them here 4637 */ 4638 gfx_v11_0_tcp_harvest(adev); 4639 4640 r = gfx_v11_0_cp_resume(adev); 4641 if (r) 4642 return r; 4643 4644 return r; 4645 } 4646 4647 #ifndef BRING_UP_DEBUG 4648 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev) 4649 { 4650 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4651 struct amdgpu_ring *kiq_ring = &kiq->ring; 4652 int i, r = 0; 4653 4654 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4655 return -EINVAL; 4656 4657 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 4658 adev->gfx.num_gfx_rings)) 4659 return -ENOMEM; 4660 4661 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4662 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 4663 PREEMPT_QUEUES, 0, 0); 4664 4665 if (adev->gfx.kiq.ring.sched.ready) 4666 r = amdgpu_ring_test_helper(kiq_ring); 4667 4668 return r; 4669 } 4670 #endif 4671 4672 static int gfx_v11_0_hw_fini(void *handle) 4673 { 4674 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4675 int r; 4676 uint32_t tmp; 4677 4678 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4679 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4680 4681 if (!adev->no_hw_access) { 4682 #ifndef BRING_UP_DEBUG 4683 if (amdgpu_async_gfx_ring) { 4684 r = gfx_v11_0_kiq_disable_kgq(adev); 4685 if (r) 4686 DRM_ERROR("KGQ disable failed\n"); 4687 } 4688 #endif 4689 if (amdgpu_gfx_disable_kcq(adev)) 4690 DRM_ERROR("KCQ disable failed\n"); 4691 4692 amdgpu_mes_kiq_hw_fini(adev); 4693 } 4694 4695 if (amdgpu_sriov_vf(adev)) { 4696 gfx_v11_0_cp_gfx_enable(adev, false); 4697 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 4698 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 4699 tmp &= 0xffffff00; 4700 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 4701 4702 return 0; 4703 } 4704 gfx_v11_0_cp_enable(adev, false); 4705 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4706 4707 adev->gfxhub.funcs->gart_disable(adev); 4708 4709 adev->gfx.is_poweron = false; 4710 4711 return 0; 4712 } 4713 4714 static int gfx_v11_0_suspend(void *handle) 4715 { 4716 return gfx_v11_0_hw_fini(handle); 4717 } 4718 4719 static int gfx_v11_0_resume(void *handle) 4720 { 4721 return gfx_v11_0_hw_init(handle); 4722 } 4723 4724 static bool gfx_v11_0_is_idle(void *handle) 4725 { 4726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4727 4728 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4729 GRBM_STATUS, GUI_ACTIVE)) 4730 return false; 4731 else 4732 return true; 4733 } 4734 4735 static int gfx_v11_0_wait_for_idle(void *handle) 4736 { 4737 unsigned i; 4738 u32 tmp; 4739 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4740 4741 for (i = 0; i < adev->usec_timeout; i++) { 4742 /* read MC_STATUS */ 4743 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4744 GRBM_STATUS__GUI_ACTIVE_MASK; 4745 4746 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4747 return 0; 4748 udelay(1); 4749 } 4750 return -ETIMEDOUT; 4751 } 4752 4753 static int gfx_v11_0_soft_reset(void *handle) 4754 { 4755 u32 grbm_soft_reset = 0; 4756 u32 tmp; 4757 int i, j, k; 4758 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4759 4760 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4761 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4762 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4763 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4764 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4765 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4766 4767 gfx_v11_0_set_safe_mode(adev); 4768 4769 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4770 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4771 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4772 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4773 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4774 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4775 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4776 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4777 4778 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4779 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4780 } 4781 } 4782 } 4783 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4784 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4785 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4786 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4787 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4788 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4789 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4790 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4791 4792 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4793 } 4794 } 4795 } 4796 4797 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4798 4799 // Read CP_VMID_RESET register three times. 4800 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4801 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4802 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4803 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4804 4805 for (i = 0; i < adev->usec_timeout; i++) { 4806 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4807 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4808 break; 4809 udelay(1); 4810 } 4811 if (i >= adev->usec_timeout) { 4812 printk("Failed to wait all pipes clean\n"); 4813 return -EINVAL; 4814 } 4815 4816 /********** trigger soft reset ***********/ 4817 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4818 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4819 SOFT_RESET_CP, 1); 4820 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4821 SOFT_RESET_GFX, 1); 4822 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4823 SOFT_RESET_CPF, 1); 4824 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4825 SOFT_RESET_CPC, 1); 4826 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4827 SOFT_RESET_CPG, 1); 4828 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4829 /********** exit soft reset ***********/ 4830 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4831 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4832 SOFT_RESET_CP, 0); 4833 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4834 SOFT_RESET_GFX, 0); 4835 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4836 SOFT_RESET_CPF, 0); 4837 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4838 SOFT_RESET_CPC, 0); 4839 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4840 SOFT_RESET_CPG, 0); 4841 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4842 4843 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4844 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4845 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4846 4847 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4848 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4849 4850 for (i = 0; i < adev->usec_timeout; i++) { 4851 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4852 break; 4853 udelay(1); 4854 } 4855 if (i >= adev->usec_timeout) { 4856 printk("Failed to wait CP_VMID_RESET to 0\n"); 4857 return -EINVAL; 4858 } 4859 4860 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4861 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4862 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4863 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4864 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4865 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4866 4867 gfx_v11_0_unset_safe_mode(adev); 4868 4869 return gfx_v11_0_cp_resume(adev); 4870 } 4871 4872 static bool gfx_v11_0_check_soft_reset(void *handle) 4873 { 4874 int i, r; 4875 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4876 struct amdgpu_ring *ring; 4877 long tmo = msecs_to_jiffies(1000); 4878 4879 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4880 ring = &adev->gfx.gfx_ring[i]; 4881 r = amdgpu_ring_test_ib(ring, tmo); 4882 if (r) 4883 return true; 4884 } 4885 4886 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4887 ring = &adev->gfx.compute_ring[i]; 4888 r = amdgpu_ring_test_ib(ring, tmo); 4889 if (r) 4890 return true; 4891 } 4892 4893 return false; 4894 } 4895 4896 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4897 { 4898 uint64_t clock; 4899 4900 amdgpu_gfx_off_ctrl(adev, false); 4901 mutex_lock(&adev->gfx.gpu_clock_mutex); 4902 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) | 4903 ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL); 4904 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4905 amdgpu_gfx_off_ctrl(adev, true); 4906 return clock; 4907 } 4908 4909 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4910 uint32_t vmid, 4911 uint32_t gds_base, uint32_t gds_size, 4912 uint32_t gws_base, uint32_t gws_size, 4913 uint32_t oa_base, uint32_t oa_size) 4914 { 4915 struct amdgpu_device *adev = ring->adev; 4916 4917 /* GDS Base */ 4918 gfx_v11_0_write_data_to_reg(ring, 0, false, 4919 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4920 gds_base); 4921 4922 /* GDS Size */ 4923 gfx_v11_0_write_data_to_reg(ring, 0, false, 4924 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4925 gds_size); 4926 4927 /* GWS */ 4928 gfx_v11_0_write_data_to_reg(ring, 0, false, 4929 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4930 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4931 4932 /* OA */ 4933 gfx_v11_0_write_data_to_reg(ring, 0, false, 4934 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4935 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4936 } 4937 4938 static int gfx_v11_0_early_init(void *handle) 4939 { 4940 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4941 4942 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4943 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4944 AMDGPU_MAX_COMPUTE_RINGS); 4945 4946 gfx_v11_0_set_kiq_pm4_funcs(adev); 4947 gfx_v11_0_set_ring_funcs(adev); 4948 gfx_v11_0_set_irq_funcs(adev); 4949 gfx_v11_0_set_gds_init(adev); 4950 gfx_v11_0_set_rlc_funcs(adev); 4951 gfx_v11_0_set_mqd_funcs(adev); 4952 gfx_v11_0_set_imu_funcs(adev); 4953 4954 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4955 4956 return 0; 4957 } 4958 4959 static int gfx_v11_0_late_init(void *handle) 4960 { 4961 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4962 int r; 4963 4964 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4965 if (r) 4966 return r; 4967 4968 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4969 if (r) 4970 return r; 4971 4972 return 0; 4973 } 4974 4975 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4976 { 4977 uint32_t rlc_cntl; 4978 4979 /* if RLC is not enabled, do nothing */ 4980 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4981 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4982 } 4983 4984 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev) 4985 { 4986 uint32_t data; 4987 unsigned i; 4988 4989 data = RLC_SAFE_MODE__CMD_MASK; 4990 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4991 4992 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4993 4994 /* wait for RLC_SAFE_MODE */ 4995 for (i = 0; i < adev->usec_timeout; i++) { 4996 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4997 RLC_SAFE_MODE, CMD)) 4998 break; 4999 udelay(1); 5000 } 5001 } 5002 5003 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev) 5004 { 5005 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 5006 } 5007 5008 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 5009 bool enable) 5010 { 5011 uint32_t def, data; 5012 5013 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 5014 return; 5015 5016 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5017 5018 if (enable) 5019 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5020 else 5021 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5022 5023 if (def != data) 5024 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5025 } 5026 5027 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 5028 bool enable) 5029 { 5030 uint32_t def, data; 5031 5032 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 5033 return; 5034 5035 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5036 5037 if (enable) 5038 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5039 else 5040 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5041 5042 if (def != data) 5043 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5044 } 5045 5046 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 5047 bool enable) 5048 { 5049 uint32_t def, data; 5050 5051 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 5052 return; 5053 5054 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5055 5056 if (enable) 5057 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5058 else 5059 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5060 5061 if (def != data) 5062 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5063 } 5064 5065 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5066 bool enable) 5067 { 5068 uint32_t data, def; 5069 5070 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 5071 return; 5072 5073 /* It is disabled by HW by default */ 5074 if (enable) { 5075 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5076 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 5077 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5078 5079 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5080 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5081 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5082 5083 if (def != data) 5084 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5085 } 5086 } else { 5087 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5088 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5089 5090 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5091 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5092 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5093 5094 if (def != data) 5095 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5096 } 5097 } 5098 } 5099 5100 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5101 bool enable) 5102 { 5103 uint32_t def, data; 5104 5105 if (!(adev->cg_flags & 5106 (AMD_CG_SUPPORT_GFX_CGCG | 5107 AMD_CG_SUPPORT_GFX_CGLS | 5108 AMD_CG_SUPPORT_GFX_3D_CGCG | 5109 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5110 return; 5111 5112 if (enable) { 5113 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5114 5115 /* unset CGCG override */ 5116 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5117 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5118 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5119 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5120 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5121 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5122 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5123 5124 /* update CGCG override bits */ 5125 if (def != data) 5126 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5127 5128 /* enable cgcg FSM(0x0000363F) */ 5129 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5130 5131 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5132 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5133 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5134 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5135 } 5136 5137 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5138 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5139 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5140 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5141 } 5142 5143 if (def != data) 5144 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5145 5146 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5147 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5148 5149 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5150 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5151 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5152 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5153 } 5154 5155 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5156 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5157 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5158 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5159 } 5160 5161 if (def != data) 5162 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5163 5164 /* set IDLE_POLL_COUNT(0x00900100) */ 5165 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5166 5167 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5168 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5169 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5170 5171 if (def != data) 5172 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5173 5174 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5175 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5176 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5177 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5178 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5179 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5180 5181 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5182 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5183 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5184 5185 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5186 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5187 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5188 } else { 5189 /* Program RLC_CGCG_CGLS_CTRL */ 5190 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5191 5192 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5193 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5194 5195 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5196 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5197 5198 if (def != data) 5199 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5200 5201 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5202 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5203 5204 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5205 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5206 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5207 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5208 5209 if (def != data) 5210 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5211 5212 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5213 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5214 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5215 5216 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5217 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5218 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5219 } 5220 } 5221 5222 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5223 bool enable) 5224 { 5225 amdgpu_gfx_rlc_enter_safe_mode(adev); 5226 5227 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5228 5229 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5230 5231 gfx_v11_0_update_repeater_fgcg(adev, enable); 5232 5233 gfx_v11_0_update_sram_fgcg(adev, enable); 5234 5235 gfx_v11_0_update_perf_clk(adev, enable); 5236 5237 if (adev->cg_flags & 5238 (AMD_CG_SUPPORT_GFX_MGCG | 5239 AMD_CG_SUPPORT_GFX_CGLS | 5240 AMD_CG_SUPPORT_GFX_CGCG | 5241 AMD_CG_SUPPORT_GFX_3D_CGCG | 5242 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5243 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5244 5245 amdgpu_gfx_rlc_exit_safe_mode(adev); 5246 5247 return 0; 5248 } 5249 5250 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 5251 { 5252 u32 reg, data; 5253 5254 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5255 if (amdgpu_sriov_is_pp_one_vf(adev)) 5256 data = RREG32_NO_KIQ(reg); 5257 else 5258 data = RREG32(reg); 5259 5260 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5261 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5262 5263 if (amdgpu_sriov_is_pp_one_vf(adev)) 5264 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5265 else 5266 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5267 } 5268 5269 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5270 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5271 .set_safe_mode = gfx_v11_0_set_safe_mode, 5272 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5273 .init = gfx_v11_0_rlc_init, 5274 .get_csb_size = gfx_v11_0_get_csb_size, 5275 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5276 .resume = gfx_v11_0_rlc_resume, 5277 .stop = gfx_v11_0_rlc_stop, 5278 .reset = gfx_v11_0_rlc_reset, 5279 .start = gfx_v11_0_rlc_start, 5280 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5281 }; 5282 5283 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5284 { 5285 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5286 5287 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5288 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5289 else 5290 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5291 5292 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5293 5294 // Program RLC_PG_DELAY3 for CGPG hysteresis 5295 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5296 switch (adev->ip_versions[GC_HWIP][0]) { 5297 case IP_VERSION(11, 0, 1): 5298 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5299 break; 5300 default: 5301 break; 5302 } 5303 } 5304 } 5305 5306 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5307 { 5308 amdgpu_gfx_rlc_enter_safe_mode(adev); 5309 5310 gfx_v11_cntl_power_gating(adev, enable); 5311 5312 amdgpu_gfx_rlc_exit_safe_mode(adev); 5313 } 5314 5315 static int gfx_v11_0_set_powergating_state(void *handle, 5316 enum amd_powergating_state state) 5317 { 5318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5319 bool enable = (state == AMD_PG_STATE_GATE); 5320 5321 if (amdgpu_sriov_vf(adev)) 5322 return 0; 5323 5324 switch (adev->ip_versions[GC_HWIP][0]) { 5325 case IP_VERSION(11, 0, 0): 5326 case IP_VERSION(11, 0, 2): 5327 amdgpu_gfx_off_ctrl(adev, enable); 5328 break; 5329 case IP_VERSION(11, 0, 1): 5330 gfx_v11_cntl_pg(adev, enable); 5331 /* TODO: Enable this when GFXOFF is ready */ 5332 // amdgpu_gfx_off_ctrl(adev, enable); 5333 break; 5334 default: 5335 break; 5336 } 5337 5338 return 0; 5339 } 5340 5341 static int gfx_v11_0_set_clockgating_state(void *handle, 5342 enum amd_clockgating_state state) 5343 { 5344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5345 5346 if (amdgpu_sriov_vf(adev)) 5347 return 0; 5348 5349 switch (adev->ip_versions[GC_HWIP][0]) { 5350 case IP_VERSION(11, 0, 0): 5351 case IP_VERSION(11, 0, 1): 5352 case IP_VERSION(11, 0, 2): 5353 gfx_v11_0_update_gfx_clock_gating(adev, 5354 state == AMD_CG_STATE_GATE); 5355 break; 5356 default: 5357 break; 5358 } 5359 5360 return 0; 5361 } 5362 5363 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5364 { 5365 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5366 int data; 5367 5368 /* AMD_CG_SUPPORT_GFX_MGCG */ 5369 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5370 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5371 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5372 5373 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5374 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5375 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5376 5377 /* AMD_CG_SUPPORT_GFX_FGCG */ 5378 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5379 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5380 5381 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5382 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5383 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5384 5385 /* AMD_CG_SUPPORT_GFX_CGCG */ 5386 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5387 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5388 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5389 5390 /* AMD_CG_SUPPORT_GFX_CGLS */ 5391 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5392 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5393 5394 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5395 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5396 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5397 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5398 5399 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5400 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5401 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5402 } 5403 5404 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5405 { 5406 /* gfx11 is 32bit rptr*/ 5407 return *(uint32_t *)ring->rptr_cpu_addr; 5408 } 5409 5410 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5411 { 5412 struct amdgpu_device *adev = ring->adev; 5413 u64 wptr; 5414 5415 /* XXX check if swapping is necessary on BE */ 5416 if (ring->use_doorbell) { 5417 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5418 } else { 5419 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5420 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5421 } 5422 5423 return wptr; 5424 } 5425 5426 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5427 { 5428 struct amdgpu_device *adev = ring->adev; 5429 uint32_t *wptr_saved; 5430 uint32_t *is_queue_unmap; 5431 uint64_t aggregated_db_index; 5432 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 5433 uint64_t wptr_tmp; 5434 5435 if (ring->is_mes_queue) { 5436 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5437 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5438 sizeof(uint32_t)); 5439 aggregated_db_index = 5440 amdgpu_mes_get_aggregated_doorbell_index(adev, 5441 ring->hw_prio); 5442 5443 wptr_tmp = ring->wptr & ring->buf_mask; 5444 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5445 *wptr_saved = wptr_tmp; 5446 /* assume doorbell always being used by mes mapped queue */ 5447 if (*is_queue_unmap) { 5448 WDOORBELL64(aggregated_db_index, wptr_tmp); 5449 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5450 } else { 5451 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5452 5453 if (*is_queue_unmap) 5454 WDOORBELL64(aggregated_db_index, wptr_tmp); 5455 } 5456 } else { 5457 if (ring->use_doorbell) { 5458 /* XXX check if swapping is necessary on BE */ 5459 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5460 ring->wptr); 5461 WDOORBELL64(ring->doorbell_index, ring->wptr); 5462 } else { 5463 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5464 lower_32_bits(ring->wptr)); 5465 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5466 upper_32_bits(ring->wptr)); 5467 } 5468 } 5469 } 5470 5471 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5472 { 5473 /* gfx11 hardware is 32bit rptr */ 5474 return *(uint32_t *)ring->rptr_cpu_addr; 5475 } 5476 5477 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5478 { 5479 u64 wptr; 5480 5481 /* XXX check if swapping is necessary on BE */ 5482 if (ring->use_doorbell) 5483 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5484 else 5485 BUG(); 5486 return wptr; 5487 } 5488 5489 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5490 { 5491 struct amdgpu_device *adev = ring->adev; 5492 uint32_t *wptr_saved; 5493 uint32_t *is_queue_unmap; 5494 uint64_t aggregated_db_index; 5495 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 5496 uint64_t wptr_tmp; 5497 5498 if (ring->is_mes_queue) { 5499 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5500 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5501 sizeof(uint32_t)); 5502 aggregated_db_index = 5503 amdgpu_mes_get_aggregated_doorbell_index(adev, 5504 ring->hw_prio); 5505 5506 wptr_tmp = ring->wptr & ring->buf_mask; 5507 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5508 *wptr_saved = wptr_tmp; 5509 /* assume doorbell always used by mes mapped queue */ 5510 if (*is_queue_unmap) { 5511 WDOORBELL64(aggregated_db_index, wptr_tmp); 5512 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5513 } else { 5514 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5515 5516 if (*is_queue_unmap) 5517 WDOORBELL64(aggregated_db_index, wptr_tmp); 5518 } 5519 } else { 5520 /* XXX check if swapping is necessary on BE */ 5521 if (ring->use_doorbell) { 5522 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5523 ring->wptr); 5524 WDOORBELL64(ring->doorbell_index, ring->wptr); 5525 } else { 5526 BUG(); /* only DOORBELL method supported on gfx11 now */ 5527 } 5528 } 5529 } 5530 5531 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5532 { 5533 struct amdgpu_device *adev = ring->adev; 5534 u32 ref_and_mask, reg_mem_engine; 5535 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5536 5537 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5538 switch (ring->me) { 5539 case 1: 5540 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5541 break; 5542 case 2: 5543 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5544 break; 5545 default: 5546 return; 5547 } 5548 reg_mem_engine = 0; 5549 } else { 5550 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5551 reg_mem_engine = 1; /* pfp */ 5552 } 5553 5554 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5555 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5556 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5557 ref_and_mask, ref_and_mask, 0x20); 5558 } 5559 5560 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5561 struct amdgpu_job *job, 5562 struct amdgpu_ib *ib, 5563 uint32_t flags) 5564 { 5565 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5566 u32 header, control = 0; 5567 5568 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5569 5570 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5571 5572 control |= ib->length_dw | (vmid << 24); 5573 5574 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5575 control |= INDIRECT_BUFFER_PRE_ENB(1); 5576 5577 if (flags & AMDGPU_IB_PREEMPTED) 5578 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5579 5580 if (vmid) 5581 gfx_v11_0_ring_emit_de_meta(ring, 5582 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5583 } 5584 5585 if (ring->is_mes_queue) 5586 /* inherit vmid from mqd */ 5587 control |= 0x400000; 5588 5589 amdgpu_ring_write(ring, header); 5590 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5591 amdgpu_ring_write(ring, 5592 #ifdef __BIG_ENDIAN 5593 (2 << 0) | 5594 #endif 5595 lower_32_bits(ib->gpu_addr)); 5596 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5597 amdgpu_ring_write(ring, control); 5598 } 5599 5600 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5601 struct amdgpu_job *job, 5602 struct amdgpu_ib *ib, 5603 uint32_t flags) 5604 { 5605 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5606 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5607 5608 if (ring->is_mes_queue) 5609 /* inherit vmid from mqd */ 5610 control |= 0x40000000; 5611 5612 /* Currently, there is a high possibility to get wave ID mismatch 5613 * between ME and GDS, leading to a hw deadlock, because ME generates 5614 * different wave IDs than the GDS expects. This situation happens 5615 * randomly when at least 5 compute pipes use GDS ordered append. 5616 * The wave IDs generated by ME are also wrong after suspend/resume. 5617 * Those are probably bugs somewhere else in the kernel driver. 5618 * 5619 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5620 * GDS to 0 for this ring (me/pipe). 5621 */ 5622 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5623 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5624 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5625 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5626 } 5627 5628 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5629 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5630 amdgpu_ring_write(ring, 5631 #ifdef __BIG_ENDIAN 5632 (2 << 0) | 5633 #endif 5634 lower_32_bits(ib->gpu_addr)); 5635 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5636 amdgpu_ring_write(ring, control); 5637 } 5638 5639 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5640 u64 seq, unsigned flags) 5641 { 5642 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5643 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5644 5645 /* RELEASE_MEM - flush caches, send int */ 5646 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5647 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5648 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5649 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5650 PACKET3_RELEASE_MEM_GCR_GL2_US | 5651 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5652 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5653 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5654 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5655 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5656 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5657 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5658 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5659 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5660 5661 /* 5662 * the address should be Qword aligned if 64bit write, Dword 5663 * aligned if only send 32bit data low (discard data high) 5664 */ 5665 if (write64bit) 5666 BUG_ON(addr & 0x7); 5667 else 5668 BUG_ON(addr & 0x3); 5669 amdgpu_ring_write(ring, lower_32_bits(addr)); 5670 amdgpu_ring_write(ring, upper_32_bits(addr)); 5671 amdgpu_ring_write(ring, lower_32_bits(seq)); 5672 amdgpu_ring_write(ring, upper_32_bits(seq)); 5673 amdgpu_ring_write(ring, ring->is_mes_queue ? 5674 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5675 } 5676 5677 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5678 { 5679 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5680 uint32_t seq = ring->fence_drv.sync_seq; 5681 uint64_t addr = ring->fence_drv.gpu_addr; 5682 5683 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5684 upper_32_bits(addr), seq, 0xffffffff, 4); 5685 } 5686 5687 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5688 uint16_t pasid, uint32_t flush_type, 5689 bool all_hub, uint8_t dst_sel) 5690 { 5691 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5692 amdgpu_ring_write(ring, 5693 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5694 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5695 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5696 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5697 } 5698 5699 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5700 unsigned vmid, uint64_t pd_addr) 5701 { 5702 if (ring->is_mes_queue) 5703 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5704 else 5705 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5706 5707 /* compute doesn't have PFP */ 5708 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5709 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5710 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5711 amdgpu_ring_write(ring, 0x0); 5712 } 5713 } 5714 5715 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5716 u64 seq, unsigned int flags) 5717 { 5718 struct amdgpu_device *adev = ring->adev; 5719 5720 /* we only allocate 32bit for each seq wb address */ 5721 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5722 5723 /* write fence seq to the "addr" */ 5724 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5725 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5726 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5727 amdgpu_ring_write(ring, lower_32_bits(addr)); 5728 amdgpu_ring_write(ring, upper_32_bits(addr)); 5729 amdgpu_ring_write(ring, lower_32_bits(seq)); 5730 5731 if (flags & AMDGPU_FENCE_FLAG_INT) { 5732 /* set register to trigger INT */ 5733 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5734 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5735 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5736 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5737 amdgpu_ring_write(ring, 0); 5738 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5739 } 5740 } 5741 5742 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5743 uint32_t flags) 5744 { 5745 uint32_t dw2 = 0; 5746 5747 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5748 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5749 /* set load_global_config & load_global_uconfig */ 5750 dw2 |= 0x8001; 5751 /* set load_cs_sh_regs */ 5752 dw2 |= 0x01000000; 5753 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5754 dw2 |= 0x10002; 5755 } 5756 5757 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5758 amdgpu_ring_write(ring, dw2); 5759 amdgpu_ring_write(ring, 0); 5760 } 5761 5762 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5763 { 5764 unsigned ret; 5765 5766 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5767 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5768 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5769 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5770 ret = ring->wptr & ring->buf_mask; 5771 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5772 5773 return ret; 5774 } 5775 5776 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5777 { 5778 unsigned cur; 5779 BUG_ON(offset > ring->buf_mask); 5780 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5781 5782 cur = (ring->wptr - 1) & ring->buf_mask; 5783 if (likely(cur > offset)) 5784 ring->ring[offset] = cur - offset; 5785 else 5786 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5787 } 5788 5789 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5790 { 5791 int i, r = 0; 5792 struct amdgpu_device *adev = ring->adev; 5793 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5794 struct amdgpu_ring *kiq_ring = &kiq->ring; 5795 unsigned long flags; 5796 5797 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5798 return -EINVAL; 5799 5800 spin_lock_irqsave(&kiq->ring_lock, flags); 5801 5802 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5803 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5804 return -ENOMEM; 5805 } 5806 5807 /* assert preemption condition */ 5808 amdgpu_ring_set_preempt_cond_exec(ring, false); 5809 5810 /* assert IB preemption, emit the trailing fence */ 5811 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5812 ring->trail_fence_gpu_addr, 5813 ++ring->trail_seq); 5814 amdgpu_ring_commit(kiq_ring); 5815 5816 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5817 5818 /* poll the trailing fence */ 5819 for (i = 0; i < adev->usec_timeout; i++) { 5820 if (ring->trail_seq == 5821 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5822 break; 5823 udelay(1); 5824 } 5825 5826 if (i >= adev->usec_timeout) { 5827 r = -EINVAL; 5828 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5829 } 5830 5831 /* deassert preemption condition */ 5832 amdgpu_ring_set_preempt_cond_exec(ring, true); 5833 return r; 5834 } 5835 5836 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5837 { 5838 struct amdgpu_device *adev = ring->adev; 5839 struct v10_de_ib_state de_payload = {0}; 5840 uint64_t offset, gds_addr, de_payload_gpu_addr; 5841 void *de_payload_cpu_addr; 5842 int cnt; 5843 5844 if (ring->is_mes_queue) { 5845 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5846 gfx[0].gfx_meta_data) + 5847 offsetof(struct v10_gfx_meta_data, de_payload); 5848 de_payload_gpu_addr = 5849 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5850 de_payload_cpu_addr = 5851 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5852 5853 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5854 gfx[0].gds_backup) + 5855 offsetof(struct v10_gfx_meta_data, de_payload); 5856 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5857 } else { 5858 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5859 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5860 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5861 5862 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5863 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5864 PAGE_SIZE); 5865 } 5866 5867 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5868 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5869 5870 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5871 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5872 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5873 WRITE_DATA_DST_SEL(8) | 5874 WR_CONFIRM) | 5875 WRITE_DATA_CACHE_POLICY(0)); 5876 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5877 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5878 5879 if (resume) 5880 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5881 sizeof(de_payload) >> 2); 5882 else 5883 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5884 sizeof(de_payload) >> 2); 5885 } 5886 5887 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5888 bool secure) 5889 { 5890 uint32_t v = secure ? FRAME_TMZ : 0; 5891 5892 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5893 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5894 } 5895 5896 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5897 uint32_t reg_val_offs) 5898 { 5899 struct amdgpu_device *adev = ring->adev; 5900 5901 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5902 amdgpu_ring_write(ring, 0 | /* src: register*/ 5903 (5 << 8) | /* dst: memory */ 5904 (1 << 20)); /* write confirm */ 5905 amdgpu_ring_write(ring, reg); 5906 amdgpu_ring_write(ring, 0); 5907 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5908 reg_val_offs * 4)); 5909 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5910 reg_val_offs * 4)); 5911 } 5912 5913 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5914 uint32_t val) 5915 { 5916 uint32_t cmd = 0; 5917 5918 switch (ring->funcs->type) { 5919 case AMDGPU_RING_TYPE_GFX: 5920 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5921 break; 5922 case AMDGPU_RING_TYPE_KIQ: 5923 cmd = (1 << 16); /* no inc addr */ 5924 break; 5925 default: 5926 cmd = WR_CONFIRM; 5927 break; 5928 } 5929 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5930 amdgpu_ring_write(ring, cmd); 5931 amdgpu_ring_write(ring, reg); 5932 amdgpu_ring_write(ring, 0); 5933 amdgpu_ring_write(ring, val); 5934 } 5935 5936 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5937 uint32_t val, uint32_t mask) 5938 { 5939 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5940 } 5941 5942 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5943 uint32_t reg0, uint32_t reg1, 5944 uint32_t ref, uint32_t mask) 5945 { 5946 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5947 5948 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5949 ref, mask, 0x20); 5950 } 5951 5952 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5953 unsigned vmid) 5954 { 5955 struct amdgpu_device *adev = ring->adev; 5956 uint32_t value = 0; 5957 5958 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5959 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5960 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5961 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5962 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5963 } 5964 5965 static void 5966 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5967 uint32_t me, uint32_t pipe, 5968 enum amdgpu_interrupt_state state) 5969 { 5970 uint32_t cp_int_cntl, cp_int_cntl_reg; 5971 5972 if (!me) { 5973 switch (pipe) { 5974 case 0: 5975 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5976 break; 5977 case 1: 5978 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5979 break; 5980 default: 5981 DRM_DEBUG("invalid pipe %d\n", pipe); 5982 return; 5983 } 5984 } else { 5985 DRM_DEBUG("invalid me %d\n", me); 5986 return; 5987 } 5988 5989 switch (state) { 5990 case AMDGPU_IRQ_STATE_DISABLE: 5991 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5992 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5993 TIME_STAMP_INT_ENABLE, 0); 5994 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5995 GENERIC0_INT_ENABLE, 0); 5996 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5997 break; 5998 case AMDGPU_IRQ_STATE_ENABLE: 5999 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 6000 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6001 TIME_STAMP_INT_ENABLE, 1); 6002 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 6003 GENERIC0_INT_ENABLE, 1); 6004 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 6005 break; 6006 default: 6007 break; 6008 } 6009 } 6010 6011 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6012 int me, int pipe, 6013 enum amdgpu_interrupt_state state) 6014 { 6015 u32 mec_int_cntl, mec_int_cntl_reg; 6016 6017 /* 6018 * amdgpu controls only the first MEC. That's why this function only 6019 * handles the setting of interrupts for this specific MEC. All other 6020 * pipes' interrupts are set by amdkfd. 6021 */ 6022 6023 if (me == 1) { 6024 switch (pipe) { 6025 case 0: 6026 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6027 break; 6028 case 1: 6029 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 6030 break; 6031 case 2: 6032 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 6033 break; 6034 case 3: 6035 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 6036 break; 6037 default: 6038 DRM_DEBUG("invalid pipe %d\n", pipe); 6039 return; 6040 } 6041 } else { 6042 DRM_DEBUG("invalid me %d\n", me); 6043 return; 6044 } 6045 6046 switch (state) { 6047 case AMDGPU_IRQ_STATE_DISABLE: 6048 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6049 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6050 TIME_STAMP_INT_ENABLE, 0); 6051 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6052 GENERIC0_INT_ENABLE, 0); 6053 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6054 break; 6055 case AMDGPU_IRQ_STATE_ENABLE: 6056 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6057 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6058 TIME_STAMP_INT_ENABLE, 1); 6059 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6060 GENERIC0_INT_ENABLE, 1); 6061 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6062 break; 6063 default: 6064 break; 6065 } 6066 } 6067 6068 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6069 struct amdgpu_irq_src *src, 6070 unsigned type, 6071 enum amdgpu_interrupt_state state) 6072 { 6073 switch (type) { 6074 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6075 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6076 break; 6077 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6078 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6079 break; 6080 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6081 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6082 break; 6083 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6084 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6085 break; 6086 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6087 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6088 break; 6089 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6090 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6091 break; 6092 default: 6093 break; 6094 } 6095 return 0; 6096 } 6097 6098 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6099 struct amdgpu_irq_src *source, 6100 struct amdgpu_iv_entry *entry) 6101 { 6102 int i; 6103 u8 me_id, pipe_id, queue_id; 6104 struct amdgpu_ring *ring; 6105 uint32_t mes_queue_id = entry->src_data[0]; 6106 6107 DRM_DEBUG("IH: CP EOP\n"); 6108 6109 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 6110 struct amdgpu_mes_queue *queue; 6111 6112 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 6113 6114 spin_lock(&adev->mes.queue_id_lock); 6115 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 6116 if (queue) { 6117 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 6118 amdgpu_fence_process(queue->ring); 6119 } 6120 spin_unlock(&adev->mes.queue_id_lock); 6121 } else { 6122 me_id = (entry->ring_id & 0x0c) >> 2; 6123 pipe_id = (entry->ring_id & 0x03) >> 0; 6124 queue_id = (entry->ring_id & 0x70) >> 4; 6125 6126 switch (me_id) { 6127 case 0: 6128 if (pipe_id == 0) 6129 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6130 else 6131 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 6132 break; 6133 case 1: 6134 case 2: 6135 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6136 ring = &adev->gfx.compute_ring[i]; 6137 /* Per-queue interrupt is supported for MEC starting from VI. 6138 * The interrupt can only be enabled/disabled per pipe instead 6139 * of per queue. 6140 */ 6141 if ((ring->me == me_id) && 6142 (ring->pipe == pipe_id) && 6143 (ring->queue == queue_id)) 6144 amdgpu_fence_process(ring); 6145 } 6146 break; 6147 } 6148 } 6149 6150 return 0; 6151 } 6152 6153 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6154 struct amdgpu_irq_src *source, 6155 unsigned type, 6156 enum amdgpu_interrupt_state state) 6157 { 6158 switch (state) { 6159 case AMDGPU_IRQ_STATE_DISABLE: 6160 case AMDGPU_IRQ_STATE_ENABLE: 6161 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 6162 PRIV_REG_INT_ENABLE, 6163 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6164 break; 6165 default: 6166 break; 6167 } 6168 6169 return 0; 6170 } 6171 6172 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6173 struct amdgpu_irq_src *source, 6174 unsigned type, 6175 enum amdgpu_interrupt_state state) 6176 { 6177 switch (state) { 6178 case AMDGPU_IRQ_STATE_DISABLE: 6179 case AMDGPU_IRQ_STATE_ENABLE: 6180 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 6181 PRIV_INSTR_INT_ENABLE, 6182 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6183 break; 6184 default: 6185 break; 6186 } 6187 6188 return 0; 6189 } 6190 6191 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6192 struct amdgpu_iv_entry *entry) 6193 { 6194 u8 me_id, pipe_id, queue_id; 6195 struct amdgpu_ring *ring; 6196 int i; 6197 6198 me_id = (entry->ring_id & 0x0c) >> 2; 6199 pipe_id = (entry->ring_id & 0x03) >> 0; 6200 queue_id = (entry->ring_id & 0x70) >> 4; 6201 6202 switch (me_id) { 6203 case 0: 6204 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6205 ring = &adev->gfx.gfx_ring[i]; 6206 /* we only enabled 1 gfx queue per pipe for now */ 6207 if (ring->me == me_id && ring->pipe == pipe_id) 6208 drm_sched_fault(&ring->sched); 6209 } 6210 break; 6211 case 1: 6212 case 2: 6213 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6214 ring = &adev->gfx.compute_ring[i]; 6215 if (ring->me == me_id && ring->pipe == pipe_id && 6216 ring->queue == queue_id) 6217 drm_sched_fault(&ring->sched); 6218 } 6219 break; 6220 default: 6221 BUG(); 6222 break; 6223 } 6224 } 6225 6226 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6227 struct amdgpu_irq_src *source, 6228 struct amdgpu_iv_entry *entry) 6229 { 6230 DRM_ERROR("Illegal register access in command stream\n"); 6231 gfx_v11_0_handle_priv_fault(adev, entry); 6232 return 0; 6233 } 6234 6235 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6236 struct amdgpu_irq_src *source, 6237 struct amdgpu_iv_entry *entry) 6238 { 6239 DRM_ERROR("Illegal instruction in command stream\n"); 6240 gfx_v11_0_handle_priv_fault(adev, entry); 6241 return 0; 6242 } 6243 6244 #if 0 6245 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6246 struct amdgpu_irq_src *src, 6247 unsigned int type, 6248 enum amdgpu_interrupt_state state) 6249 { 6250 uint32_t tmp, target; 6251 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 6252 6253 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6254 target += ring->pipe; 6255 6256 switch (type) { 6257 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6258 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6259 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6260 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6261 GENERIC2_INT_ENABLE, 0); 6262 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6263 6264 tmp = RREG32_SOC15_IP(GC, target); 6265 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6266 GENERIC2_INT_ENABLE, 0); 6267 WREG32_SOC15_IP(GC, target, tmp); 6268 } else { 6269 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6270 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6271 GENERIC2_INT_ENABLE, 1); 6272 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6273 6274 tmp = RREG32_SOC15_IP(GC, target); 6275 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6276 GENERIC2_INT_ENABLE, 1); 6277 WREG32_SOC15_IP(GC, target, tmp); 6278 } 6279 break; 6280 default: 6281 BUG(); /* kiq only support GENERIC2_INT now */ 6282 break; 6283 } 6284 return 0; 6285 } 6286 #endif 6287 6288 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6289 { 6290 const unsigned int gcr_cntl = 6291 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6292 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6293 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6294 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6295 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6296 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6297 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6298 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6299 6300 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6301 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6302 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6303 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6304 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6305 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6306 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6307 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6308 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6309 } 6310 6311 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6312 .name = "gfx_v11_0", 6313 .early_init = gfx_v11_0_early_init, 6314 .late_init = gfx_v11_0_late_init, 6315 .sw_init = gfx_v11_0_sw_init, 6316 .sw_fini = gfx_v11_0_sw_fini, 6317 .hw_init = gfx_v11_0_hw_init, 6318 .hw_fini = gfx_v11_0_hw_fini, 6319 .suspend = gfx_v11_0_suspend, 6320 .resume = gfx_v11_0_resume, 6321 .is_idle = gfx_v11_0_is_idle, 6322 .wait_for_idle = gfx_v11_0_wait_for_idle, 6323 .soft_reset = gfx_v11_0_soft_reset, 6324 .check_soft_reset = gfx_v11_0_check_soft_reset, 6325 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6326 .set_powergating_state = gfx_v11_0_set_powergating_state, 6327 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6328 }; 6329 6330 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6331 .type = AMDGPU_RING_TYPE_GFX, 6332 .align_mask = 0xff, 6333 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6334 .support_64bit_ptrs = true, 6335 .vmhub = AMDGPU_GFXHUB_0, 6336 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6337 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6338 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6339 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6340 5 + /* COND_EXEC */ 6341 7 + /* PIPELINE_SYNC */ 6342 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6343 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6344 2 + /* VM_FLUSH */ 6345 8 + /* FENCE for VM_FLUSH */ 6346 20 + /* GDS switch */ 6347 5 + /* COND_EXEC */ 6348 7 + /* HDP_flush */ 6349 4 + /* VGT_flush */ 6350 31 + /* DE_META */ 6351 3 + /* CNTX_CTRL */ 6352 5 + /* HDP_INVL */ 6353 8 + 8 + /* FENCE x2 */ 6354 8, /* gfx_v11_0_emit_mem_sync */ 6355 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6356 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6357 .emit_fence = gfx_v11_0_ring_emit_fence, 6358 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6359 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6360 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6361 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6362 .test_ring = gfx_v11_0_ring_test_ring, 6363 .test_ib = gfx_v11_0_ring_test_ib, 6364 .insert_nop = amdgpu_ring_insert_nop, 6365 .pad_ib = amdgpu_ring_generic_pad_ib, 6366 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6367 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6368 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6369 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6370 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6371 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6372 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6373 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6374 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6375 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6376 }; 6377 6378 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6379 .type = AMDGPU_RING_TYPE_COMPUTE, 6380 .align_mask = 0xff, 6381 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6382 .support_64bit_ptrs = true, 6383 .vmhub = AMDGPU_GFXHUB_0, 6384 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6385 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6386 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6387 .emit_frame_size = 6388 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6389 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6390 5 + /* hdp invalidate */ 6391 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6392 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6393 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6394 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6395 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6396 8, /* gfx_v11_0_emit_mem_sync */ 6397 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6398 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6399 .emit_fence = gfx_v11_0_ring_emit_fence, 6400 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6401 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6402 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6403 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6404 .test_ring = gfx_v11_0_ring_test_ring, 6405 .test_ib = gfx_v11_0_ring_test_ib, 6406 .insert_nop = amdgpu_ring_insert_nop, 6407 .pad_ib = amdgpu_ring_generic_pad_ib, 6408 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6409 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6410 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6411 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6412 }; 6413 6414 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6415 .type = AMDGPU_RING_TYPE_KIQ, 6416 .align_mask = 0xff, 6417 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6418 .support_64bit_ptrs = true, 6419 .vmhub = AMDGPU_GFXHUB_0, 6420 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6421 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6422 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6423 .emit_frame_size = 6424 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6425 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6426 5 + /*hdp invalidate */ 6427 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6428 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6429 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6430 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6431 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6432 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6433 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6434 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6435 .test_ring = gfx_v11_0_ring_test_ring, 6436 .test_ib = gfx_v11_0_ring_test_ib, 6437 .insert_nop = amdgpu_ring_insert_nop, 6438 .pad_ib = amdgpu_ring_generic_pad_ib, 6439 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6440 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6441 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6442 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6443 }; 6444 6445 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6446 { 6447 int i; 6448 6449 adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6450 6451 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6452 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6453 6454 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6455 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6456 } 6457 6458 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6459 .set = gfx_v11_0_set_eop_interrupt_state, 6460 .process = gfx_v11_0_eop_irq, 6461 }; 6462 6463 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6464 .set = gfx_v11_0_set_priv_reg_fault_state, 6465 .process = gfx_v11_0_priv_reg_irq, 6466 }; 6467 6468 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6469 .set = gfx_v11_0_set_priv_inst_fault_state, 6470 .process = gfx_v11_0_priv_inst_irq, 6471 }; 6472 6473 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6474 { 6475 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6476 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6477 6478 adev->gfx.priv_reg_irq.num_types = 1; 6479 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6480 6481 adev->gfx.priv_inst_irq.num_types = 1; 6482 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6483 } 6484 6485 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6486 { 6487 if (adev->flags & AMD_IS_APU) 6488 adev->gfx.imu.mode = MISSION_MODE; 6489 else 6490 adev->gfx.imu.mode = DEBUG_MODE; 6491 6492 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6493 } 6494 6495 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6496 { 6497 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6498 } 6499 6500 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6501 { 6502 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6503 adev->gfx.config.max_sh_per_se * 6504 adev->gfx.config.max_shader_engines; 6505 6506 adev->gds.gds_size = 0x1000; 6507 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6508 adev->gds.gws_size = 64; 6509 adev->gds.oa_size = 16; 6510 } 6511 6512 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6513 { 6514 /* set gfx eng mqd */ 6515 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6516 sizeof(struct v11_gfx_mqd); 6517 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6518 gfx_v11_0_gfx_mqd_init; 6519 /* set compute eng mqd */ 6520 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6521 sizeof(struct v11_compute_mqd); 6522 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6523 gfx_v11_0_compute_mqd_init; 6524 } 6525 6526 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6527 u32 bitmap) 6528 { 6529 u32 data; 6530 6531 if (!bitmap) 6532 return; 6533 6534 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6535 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6536 6537 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6538 } 6539 6540 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6541 { 6542 u32 data, wgp_bitmask; 6543 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6544 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6545 6546 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6547 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6548 6549 wgp_bitmask = 6550 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6551 6552 return (~data) & wgp_bitmask; 6553 } 6554 6555 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6556 { 6557 u32 wgp_idx, wgp_active_bitmap; 6558 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6559 6560 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6561 cu_active_bitmap = 0; 6562 6563 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6564 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6565 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6566 if (wgp_active_bitmap & (1 << wgp_idx)) 6567 cu_active_bitmap |= cu_bitmap_per_wgp; 6568 } 6569 6570 return cu_active_bitmap; 6571 } 6572 6573 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6574 struct amdgpu_cu_info *cu_info) 6575 { 6576 int i, j, k, counter, active_cu_number = 0; 6577 u32 mask, bitmap; 6578 unsigned disable_masks[8 * 2]; 6579 6580 if (!adev || !cu_info) 6581 return -EINVAL; 6582 6583 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6584 6585 mutex_lock(&adev->grbm_idx_mutex); 6586 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6587 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6588 mask = 1; 6589 counter = 0; 6590 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 6591 if (i < 8 && j < 2) 6592 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6593 adev, disable_masks[i * 2 + j]); 6594 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6595 6596 /** 6597 * GFX11 could support more than 4 SEs, while the bitmap 6598 * in cu_info struct is 4x4 and ioctl interface struct 6599 * drm_amdgpu_info_device should keep stable. 6600 * So we use last two columns of bitmap to store cu mask for 6601 * SEs 4 to 7, the layout of the bitmap is as below: 6602 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6603 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6604 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6605 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6606 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6607 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6608 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6609 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6610 */ 6611 cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; 6612 6613 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6614 if (bitmap & mask) 6615 counter++; 6616 6617 mask <<= 1; 6618 } 6619 active_cu_number += counter; 6620 } 6621 } 6622 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6623 mutex_unlock(&adev->grbm_idx_mutex); 6624 6625 cu_info->number = active_cu_number; 6626 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6627 6628 return 0; 6629 } 6630 6631 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6632 { 6633 .type = AMD_IP_BLOCK_TYPE_GFX, 6634 .major = 11, 6635 .minor = 0, 6636 .rev = 0, 6637 .funcs = &gfx_v11_0_ip_funcs, 6638 }; 6639