1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "gfx_v11_0_3.h" 50 #include "nbio_v4_3.h" 51 #include "mes_v11_0.h" 52 53 #define GFX11_NUM_GFX_RINGS 1 54 #define GFX11_MEC_HPD_SIZE 2048 55 56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 58 59 #define regCGTT_WD_CLK_CTRL 0x5086 60 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 63 64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 85 86 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 87 { 88 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 89 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 90 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 91 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 97 }; 98 99 #define DEFAULT_SH_MEM_CONFIG \ 100 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 101 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 102 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 103 104 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 105 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 106 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 107 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 108 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 109 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 110 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 111 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 112 struct amdgpu_cu_info *cu_info); 113 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 114 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 115 u32 sh_num, u32 instance, int xcc_id); 116 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 117 118 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 119 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 120 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 121 uint32_t val); 122 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 123 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 124 uint16_t pasid, uint32_t flush_type, 125 bool all_hub, uint8_t dst_sel); 126 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 127 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 128 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 129 bool enable); 130 131 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 132 { 133 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 134 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 135 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 136 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 137 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 138 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 139 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 140 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 141 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 142 } 143 144 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 145 struct amdgpu_ring *ring) 146 { 147 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 148 uint64_t wptr_addr = ring->wptr_gpu_addr; 149 uint32_t me = 0, eng_sel = 0; 150 151 switch (ring->funcs->type) { 152 case AMDGPU_RING_TYPE_COMPUTE: 153 me = 1; 154 eng_sel = 0; 155 break; 156 case AMDGPU_RING_TYPE_GFX: 157 me = 0; 158 eng_sel = 4; 159 break; 160 case AMDGPU_RING_TYPE_MES: 161 me = 2; 162 eng_sel = 5; 163 break; 164 default: 165 WARN_ON(1); 166 } 167 168 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 169 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 170 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 171 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 172 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 173 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 174 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 175 PACKET3_MAP_QUEUES_ME((me)) | 176 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 177 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 178 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 179 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 180 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 181 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 182 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 183 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 184 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 185 } 186 187 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 188 struct amdgpu_ring *ring, 189 enum amdgpu_unmap_queues_action action, 190 u64 gpu_addr, u64 seq) 191 { 192 struct amdgpu_device *adev = kiq_ring->adev; 193 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 194 195 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 196 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 197 return; 198 } 199 200 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 201 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 202 PACKET3_UNMAP_QUEUES_ACTION(action) | 203 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 204 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 205 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 206 amdgpu_ring_write(kiq_ring, 207 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 208 209 if (action == PREEMPT_QUEUES_NO_UNMAP) { 210 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 211 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 212 amdgpu_ring_write(kiq_ring, seq); 213 } else { 214 amdgpu_ring_write(kiq_ring, 0); 215 amdgpu_ring_write(kiq_ring, 0); 216 amdgpu_ring_write(kiq_ring, 0); 217 } 218 } 219 220 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 221 struct amdgpu_ring *ring, 222 u64 addr, 223 u64 seq) 224 { 225 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 226 227 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 228 amdgpu_ring_write(kiq_ring, 229 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 230 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 231 PACKET3_QUERY_STATUS_COMMAND(2)); 232 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 233 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 234 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 235 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 236 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 237 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 238 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 239 } 240 241 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 242 uint16_t pasid, uint32_t flush_type, 243 bool all_hub) 244 { 245 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 246 } 247 248 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 249 .kiq_set_resources = gfx11_kiq_set_resources, 250 .kiq_map_queues = gfx11_kiq_map_queues, 251 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 252 .kiq_query_status = gfx11_kiq_query_status, 253 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 254 .set_resources_size = 8, 255 .map_queues_size = 7, 256 .unmap_queues_size = 6, 257 .query_status_size = 7, 258 .invalidate_tlbs_size = 2, 259 }; 260 261 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 262 { 263 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; 264 } 265 266 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 267 { 268 switch (adev->ip_versions[GC_HWIP][0]) { 269 case IP_VERSION(11, 0, 1): 270 case IP_VERSION(11, 0, 4): 271 soc15_program_register_sequence(adev, 272 golden_settings_gc_11_0_1, 273 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 274 break; 275 default: 276 break; 277 } 278 } 279 280 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 281 bool wc, uint32_t reg, uint32_t val) 282 { 283 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 284 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 285 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 286 amdgpu_ring_write(ring, reg); 287 amdgpu_ring_write(ring, 0); 288 amdgpu_ring_write(ring, val); 289 } 290 291 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 292 int mem_space, int opt, uint32_t addr0, 293 uint32_t addr1, uint32_t ref, uint32_t mask, 294 uint32_t inv) 295 { 296 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 297 amdgpu_ring_write(ring, 298 /* memory (1) or register (0) */ 299 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 300 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 301 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 302 WAIT_REG_MEM_ENGINE(eng_sel))); 303 304 if (mem_space) 305 BUG_ON(addr0 & 0x3); /* Dword align */ 306 amdgpu_ring_write(ring, addr0); 307 amdgpu_ring_write(ring, addr1); 308 amdgpu_ring_write(ring, ref); 309 amdgpu_ring_write(ring, mask); 310 amdgpu_ring_write(ring, inv); /* poll interval */ 311 } 312 313 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 314 { 315 struct amdgpu_device *adev = ring->adev; 316 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 317 uint32_t tmp = 0; 318 unsigned i; 319 int r; 320 321 WREG32(scratch, 0xCAFEDEAD); 322 r = amdgpu_ring_alloc(ring, 5); 323 if (r) { 324 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 325 ring->idx, r); 326 return r; 327 } 328 329 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 330 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 331 } else { 332 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 333 amdgpu_ring_write(ring, scratch - 334 PACKET3_SET_UCONFIG_REG_START); 335 amdgpu_ring_write(ring, 0xDEADBEEF); 336 } 337 amdgpu_ring_commit(ring); 338 339 for (i = 0; i < adev->usec_timeout; i++) { 340 tmp = RREG32(scratch); 341 if (tmp == 0xDEADBEEF) 342 break; 343 if (amdgpu_emu_mode == 1) 344 msleep(1); 345 else 346 udelay(1); 347 } 348 349 if (i >= adev->usec_timeout) 350 r = -ETIMEDOUT; 351 return r; 352 } 353 354 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 355 { 356 struct amdgpu_device *adev = ring->adev; 357 struct amdgpu_ib ib; 358 struct dma_fence *f = NULL; 359 unsigned index; 360 uint64_t gpu_addr; 361 volatile uint32_t *cpu_ptr; 362 long r; 363 364 /* MES KIQ fw hasn't indirect buffer support for now */ 365 if (adev->enable_mes_kiq && 366 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 367 return 0; 368 369 memset(&ib, 0, sizeof(ib)); 370 371 if (ring->is_mes_queue) { 372 uint32_t padding, offset; 373 374 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 375 padding = amdgpu_mes_ctx_get_offs(ring, 376 AMDGPU_MES_CTX_PADDING_OFFS); 377 378 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 379 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 380 381 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 382 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 383 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 384 } else { 385 r = amdgpu_device_wb_get(adev, &index); 386 if (r) 387 return r; 388 389 gpu_addr = adev->wb.gpu_addr + (index * 4); 390 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 391 cpu_ptr = &adev->wb.wb[index]; 392 393 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 394 if (r) { 395 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 396 goto err1; 397 } 398 } 399 400 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 401 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 402 ib.ptr[2] = lower_32_bits(gpu_addr); 403 ib.ptr[3] = upper_32_bits(gpu_addr); 404 ib.ptr[4] = 0xDEADBEEF; 405 ib.length_dw = 5; 406 407 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 408 if (r) 409 goto err2; 410 411 r = dma_fence_wait_timeout(f, false, timeout); 412 if (r == 0) { 413 r = -ETIMEDOUT; 414 goto err2; 415 } else if (r < 0) { 416 goto err2; 417 } 418 419 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 420 r = 0; 421 else 422 r = -EINVAL; 423 err2: 424 if (!ring->is_mes_queue) 425 amdgpu_ib_free(adev, &ib, NULL); 426 dma_fence_put(f); 427 err1: 428 if (!ring->is_mes_queue) 429 amdgpu_device_wb_free(adev, index); 430 return r; 431 } 432 433 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 434 { 435 amdgpu_ucode_release(&adev->gfx.pfp_fw); 436 amdgpu_ucode_release(&adev->gfx.me_fw); 437 amdgpu_ucode_release(&adev->gfx.rlc_fw); 438 amdgpu_ucode_release(&adev->gfx.mec_fw); 439 440 kfree(adev->gfx.rlc.register_list_format); 441 } 442 443 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 444 { 445 const struct psp_firmware_header_v1_0 *toc_hdr; 446 int err = 0; 447 char fw_name[40]; 448 449 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 450 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 451 if (err) 452 goto out; 453 454 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 455 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 456 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 457 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 458 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 459 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 460 return 0; 461 out: 462 amdgpu_ucode_release(&adev->psp.toc_fw); 463 return err; 464 } 465 466 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev) 467 { 468 switch (adev->ip_versions[GC_HWIP][0]) { 469 case IP_VERSION(11, 0, 0): 470 case IP_VERSION(11, 0, 2): 471 case IP_VERSION(11, 0, 3): 472 if ((adev->gfx.me_fw_version >= 1505) && 473 (adev->gfx.pfp_fw_version >= 1600) && 474 (adev->gfx.mec_fw_version >= 512)) 475 adev->gfx.cp_gfx_shadow = true; 476 break; 477 default: 478 adev->gfx.cp_gfx_shadow = false; 479 break; 480 } 481 } 482 483 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 484 { 485 char fw_name[40]; 486 char ucode_prefix[30]; 487 int err; 488 const struct rlc_firmware_header_v2_0 *rlc_hdr; 489 uint16_t version_major; 490 uint16_t version_minor; 491 492 DRM_DEBUG("\n"); 493 494 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 495 496 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 497 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 498 if (err) 499 goto out; 500 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 501 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 502 (union amdgpu_firmware_header *) 503 adev->gfx.pfp_fw->data, 2, 0); 504 if (adev->gfx.rs64_enable) { 505 dev_info(adev->dev, "CP RS64 enable\n"); 506 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 507 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 508 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 509 } else { 510 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 511 } 512 513 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 514 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 515 if (err) 516 goto out; 517 if (adev->gfx.rs64_enable) { 518 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 519 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 520 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 521 } else { 522 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 523 } 524 525 if (!amdgpu_sriov_vf(adev)) { 526 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 527 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 528 if (err) 529 goto out; 530 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 531 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 532 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 533 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 534 if (err) 535 goto out; 536 } 537 538 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 539 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 540 if (err) 541 goto out; 542 if (adev->gfx.rs64_enable) { 543 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 544 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 545 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 546 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 547 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 548 } else { 549 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 550 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 551 } 552 553 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 554 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 555 556 /* only one MEC for gfx 11.0.0. */ 557 adev->gfx.mec2_fw = NULL; 558 559 gfx_v11_0_check_fw_cp_gfx_shadow(adev); 560 out: 561 if (err) { 562 amdgpu_ucode_release(&adev->gfx.pfp_fw); 563 amdgpu_ucode_release(&adev->gfx.me_fw); 564 amdgpu_ucode_release(&adev->gfx.rlc_fw); 565 amdgpu_ucode_release(&adev->gfx.mec_fw); 566 } 567 568 return err; 569 } 570 571 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 572 { 573 u32 count = 0; 574 const struct cs_section_def *sect = NULL; 575 const struct cs_extent_def *ext = NULL; 576 577 /* begin clear state */ 578 count += 2; 579 /* context control state */ 580 count += 3; 581 582 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 583 for (ext = sect->section; ext->extent != NULL; ++ext) { 584 if (sect->id == SECT_CONTEXT) 585 count += 2 + ext->reg_count; 586 else 587 return 0; 588 } 589 } 590 591 /* set PA_SC_TILE_STEERING_OVERRIDE */ 592 count += 3; 593 /* end clear state */ 594 count += 2; 595 /* clear state */ 596 count += 2; 597 598 return count; 599 } 600 601 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 602 volatile u32 *buffer) 603 { 604 u32 count = 0, i; 605 const struct cs_section_def *sect = NULL; 606 const struct cs_extent_def *ext = NULL; 607 int ctx_reg_offset; 608 609 if (adev->gfx.rlc.cs_data == NULL) 610 return; 611 if (buffer == NULL) 612 return; 613 614 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 615 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 616 617 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 618 buffer[count++] = cpu_to_le32(0x80000000); 619 buffer[count++] = cpu_to_le32(0x80000000); 620 621 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 622 for (ext = sect->section; ext->extent != NULL; ++ext) { 623 if (sect->id == SECT_CONTEXT) { 624 buffer[count++] = 625 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 626 buffer[count++] = cpu_to_le32(ext->reg_index - 627 PACKET3_SET_CONTEXT_REG_START); 628 for (i = 0; i < ext->reg_count; i++) 629 buffer[count++] = cpu_to_le32(ext->extent[i]); 630 } else { 631 return; 632 } 633 } 634 } 635 636 ctx_reg_offset = 637 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 638 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 639 buffer[count++] = cpu_to_le32(ctx_reg_offset); 640 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 641 642 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 643 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 644 645 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 646 buffer[count++] = cpu_to_le32(0); 647 } 648 649 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 650 { 651 /* clear state block */ 652 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 653 &adev->gfx.rlc.clear_state_gpu_addr, 654 (void **)&adev->gfx.rlc.cs_ptr); 655 656 /* jump table block */ 657 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 658 &adev->gfx.rlc.cp_table_gpu_addr, 659 (void **)&adev->gfx.rlc.cp_table_ptr); 660 } 661 662 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 663 { 664 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 665 666 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 667 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 668 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 669 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 670 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 671 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 672 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 673 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 674 adev->gfx.rlc.rlcg_reg_access_supported = true; 675 } 676 677 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 678 { 679 const struct cs_section_def *cs_data; 680 int r; 681 682 adev->gfx.rlc.cs_data = gfx11_cs_data; 683 684 cs_data = adev->gfx.rlc.cs_data; 685 686 if (cs_data) { 687 /* init clear state block */ 688 r = amdgpu_gfx_rlc_init_csb(adev); 689 if (r) 690 return r; 691 } 692 693 /* init spm vmid with 0xf */ 694 if (adev->gfx.rlc.funcs->update_spm_vmid) 695 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 696 697 return 0; 698 } 699 700 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 701 { 702 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 703 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 704 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 705 } 706 707 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 708 { 709 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 710 711 amdgpu_gfx_graphics_queue_acquire(adev); 712 } 713 714 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 715 { 716 int r; 717 u32 *hpd; 718 size_t mec_hpd_size; 719 720 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 721 722 /* take ownership of the relevant compute queues */ 723 amdgpu_gfx_compute_queue_acquire(adev); 724 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 725 726 if (mec_hpd_size) { 727 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 728 AMDGPU_GEM_DOMAIN_GTT, 729 &adev->gfx.mec.hpd_eop_obj, 730 &adev->gfx.mec.hpd_eop_gpu_addr, 731 (void **)&hpd); 732 if (r) { 733 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 734 gfx_v11_0_mec_fini(adev); 735 return r; 736 } 737 738 memset(hpd, 0, mec_hpd_size); 739 740 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 741 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 742 } 743 744 return 0; 745 } 746 747 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 748 { 749 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 750 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 751 (address << SQ_IND_INDEX__INDEX__SHIFT)); 752 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 753 } 754 755 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 756 uint32_t thread, uint32_t regno, 757 uint32_t num, uint32_t *out) 758 { 759 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 760 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 761 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 762 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 763 (SQ_IND_INDEX__AUTO_INCR_MASK)); 764 while (num--) 765 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 766 } 767 768 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 769 { 770 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 771 * field when performing a select_se_sh so it should be 772 * zero here */ 773 WARN_ON(simd != 0); 774 775 /* type 3 wave data */ 776 dst[(*no_fields)++] = 3; 777 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 778 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 779 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 780 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 781 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 782 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 783 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 784 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 785 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 786 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 787 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 788 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 789 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 790 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 791 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 792 } 793 794 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 795 uint32_t wave, uint32_t start, 796 uint32_t size, uint32_t *dst) 797 { 798 WARN_ON(simd != 0); 799 800 wave_read_regs( 801 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 802 dst); 803 } 804 805 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 806 uint32_t wave, uint32_t thread, 807 uint32_t start, uint32_t size, 808 uint32_t *dst) 809 { 810 wave_read_regs( 811 adev, wave, thread, 812 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 813 } 814 815 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 816 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 817 { 818 soc21_grbm_select(adev, me, pipe, q, vm); 819 } 820 821 /* all sizes are in bytes */ 822 #define MQD_SHADOW_BASE_SIZE 73728 823 #define MQD_SHADOW_BASE_ALIGNMENT 256 824 #define MQD_FWWORKAREA_SIZE 484 825 #define MQD_FWWORKAREA_ALIGNMENT 256 826 827 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, 828 struct amdgpu_gfx_shadow_info *shadow_info) 829 { 830 if (adev->gfx.cp_gfx_shadow) { 831 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; 832 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; 833 shadow_info->csa_size = MQD_FWWORKAREA_SIZE; 834 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; 835 return 0; 836 } else { 837 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); 838 return -ENOTSUPP; 839 } 840 } 841 842 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 843 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 844 .select_se_sh = &gfx_v11_0_select_se_sh, 845 .read_wave_data = &gfx_v11_0_read_wave_data, 846 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 847 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 848 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 849 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 850 .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, 851 }; 852 853 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 854 { 855 856 switch (adev->ip_versions[GC_HWIP][0]) { 857 case IP_VERSION(11, 0, 0): 858 case IP_VERSION(11, 0, 2): 859 adev->gfx.config.max_hw_contexts = 8; 860 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 861 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 862 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 863 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 864 break; 865 case IP_VERSION(11, 0, 3): 866 adev->gfx.ras = &gfx_v11_0_3_ras; 867 adev->gfx.config.max_hw_contexts = 8; 868 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 869 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 870 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 871 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 872 break; 873 case IP_VERSION(11, 0, 1): 874 case IP_VERSION(11, 0, 4): 875 adev->gfx.config.max_hw_contexts = 8; 876 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 877 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 878 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 879 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 880 break; 881 default: 882 BUG(); 883 break; 884 } 885 886 return 0; 887 } 888 889 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 890 int me, int pipe, int queue) 891 { 892 int r; 893 struct amdgpu_ring *ring; 894 unsigned int irq_type; 895 896 ring = &adev->gfx.gfx_ring[ring_id]; 897 898 ring->me = me; 899 ring->pipe = pipe; 900 ring->queue = queue; 901 902 ring->ring_obj = NULL; 903 ring->use_doorbell = true; 904 905 if (!ring_id) 906 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 907 else 908 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 909 ring->vm_hub = AMDGPU_GFXHUB(0); 910 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 911 912 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 913 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 914 AMDGPU_RING_PRIO_DEFAULT, NULL); 915 if (r) 916 return r; 917 return 0; 918 } 919 920 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 921 int mec, int pipe, int queue) 922 { 923 int r; 924 unsigned irq_type; 925 struct amdgpu_ring *ring; 926 unsigned int hw_prio; 927 928 ring = &adev->gfx.compute_ring[ring_id]; 929 930 /* mec0 is me1 */ 931 ring->me = mec + 1; 932 ring->pipe = pipe; 933 ring->queue = queue; 934 935 ring->ring_obj = NULL; 936 ring->use_doorbell = true; 937 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 938 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 939 + (ring_id * GFX11_MEC_HPD_SIZE); 940 ring->vm_hub = AMDGPU_GFXHUB(0); 941 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 942 943 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 944 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 945 + ring->pipe; 946 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 947 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 948 /* type-2 packets are deprecated on MEC, use type-3 instead */ 949 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 950 hw_prio, NULL); 951 if (r) 952 return r; 953 954 return 0; 955 } 956 957 static struct { 958 SOC21_FIRMWARE_ID id; 959 unsigned int offset; 960 unsigned int size; 961 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 962 963 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 964 { 965 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 966 967 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 968 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 969 rlc_autoload_info[ucode->id].id = ucode->id; 970 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 971 rlc_autoload_info[ucode->id].size = ucode->size * 4; 972 973 ucode++; 974 } 975 } 976 977 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 978 { 979 uint32_t total_size = 0; 980 SOC21_FIRMWARE_ID id; 981 982 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 983 984 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 985 total_size += rlc_autoload_info[id].size; 986 987 /* In case the offset in rlc toc ucode is aligned */ 988 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 989 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 990 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 991 992 return total_size; 993 } 994 995 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 996 { 997 int r; 998 uint32_t total_size; 999 1000 total_size = gfx_v11_0_calc_toc_total_size(adev); 1001 1002 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1003 AMDGPU_GEM_DOMAIN_VRAM | 1004 AMDGPU_GEM_DOMAIN_GTT, 1005 &adev->gfx.rlc.rlc_autoload_bo, 1006 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1007 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1008 1009 if (r) { 1010 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1011 return r; 1012 } 1013 1014 return 0; 1015 } 1016 1017 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1018 SOC21_FIRMWARE_ID id, 1019 const void *fw_data, 1020 uint32_t fw_size, 1021 uint32_t *fw_autoload_mask) 1022 { 1023 uint32_t toc_offset; 1024 uint32_t toc_fw_size; 1025 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1026 1027 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1028 return; 1029 1030 toc_offset = rlc_autoload_info[id].offset; 1031 toc_fw_size = rlc_autoload_info[id].size; 1032 1033 if (fw_size == 0) 1034 fw_size = toc_fw_size; 1035 1036 if (fw_size > toc_fw_size) 1037 fw_size = toc_fw_size; 1038 1039 memcpy(ptr + toc_offset, fw_data, fw_size); 1040 1041 if (fw_size < toc_fw_size) 1042 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1043 1044 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1045 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1046 } 1047 1048 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1049 uint32_t *fw_autoload_mask) 1050 { 1051 void *data; 1052 uint32_t size; 1053 uint64_t *toc_ptr; 1054 1055 *(uint64_t *)fw_autoload_mask |= 0x1; 1056 1057 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1058 1059 data = adev->psp.toc.start_addr; 1060 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1061 1062 toc_ptr = (uint64_t *)data + size / 8 - 1; 1063 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1064 1065 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1066 data, size, fw_autoload_mask); 1067 } 1068 1069 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1070 uint32_t *fw_autoload_mask) 1071 { 1072 const __le32 *fw_data; 1073 uint32_t fw_size; 1074 const struct gfx_firmware_header_v1_0 *cp_hdr; 1075 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1076 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1077 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1078 uint16_t version_major, version_minor; 1079 1080 if (adev->gfx.rs64_enable) { 1081 /* pfp ucode */ 1082 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1083 adev->gfx.pfp_fw->data; 1084 /* instruction */ 1085 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1086 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1087 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1088 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1089 fw_data, fw_size, fw_autoload_mask); 1090 /* data */ 1091 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1092 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1093 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1094 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1095 fw_data, fw_size, fw_autoload_mask); 1096 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1097 fw_data, fw_size, fw_autoload_mask); 1098 /* me ucode */ 1099 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1100 adev->gfx.me_fw->data; 1101 /* instruction */ 1102 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1103 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1104 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1105 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1106 fw_data, fw_size, fw_autoload_mask); 1107 /* data */ 1108 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1109 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1110 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1111 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1112 fw_data, fw_size, fw_autoload_mask); 1113 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1114 fw_data, fw_size, fw_autoload_mask); 1115 /* mec ucode */ 1116 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1117 adev->gfx.mec_fw->data; 1118 /* instruction */ 1119 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1120 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1121 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1122 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1123 fw_data, fw_size, fw_autoload_mask); 1124 /* data */ 1125 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1126 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1127 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1128 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1129 fw_data, fw_size, fw_autoload_mask); 1130 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1131 fw_data, fw_size, fw_autoload_mask); 1132 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1133 fw_data, fw_size, fw_autoload_mask); 1134 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1135 fw_data, fw_size, fw_autoload_mask); 1136 } else { 1137 /* pfp ucode */ 1138 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1139 adev->gfx.pfp_fw->data; 1140 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1141 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1142 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1143 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1144 fw_data, fw_size, fw_autoload_mask); 1145 1146 /* me ucode */ 1147 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1148 adev->gfx.me_fw->data; 1149 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1150 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1151 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1152 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1153 fw_data, fw_size, fw_autoload_mask); 1154 1155 /* mec ucode */ 1156 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1157 adev->gfx.mec_fw->data; 1158 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1159 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1160 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1161 cp_hdr->jt_size * 4; 1162 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1163 fw_data, fw_size, fw_autoload_mask); 1164 } 1165 1166 /* rlc ucode */ 1167 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1168 adev->gfx.rlc_fw->data; 1169 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1170 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1171 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1172 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1173 fw_data, fw_size, fw_autoload_mask); 1174 1175 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1176 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1177 if (version_major == 2) { 1178 if (version_minor >= 2) { 1179 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1180 1181 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1182 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1183 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1184 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1185 fw_data, fw_size, fw_autoload_mask); 1186 1187 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1188 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1189 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1190 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1191 fw_data, fw_size, fw_autoload_mask); 1192 } 1193 } 1194 } 1195 1196 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1197 uint32_t *fw_autoload_mask) 1198 { 1199 const __le32 *fw_data; 1200 uint32_t fw_size; 1201 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1202 1203 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1204 adev->sdma.instance[0].fw->data; 1205 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1206 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1207 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1208 1209 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1210 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1211 1212 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1213 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1214 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1215 1216 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1217 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1218 } 1219 1220 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1221 uint32_t *fw_autoload_mask) 1222 { 1223 const __le32 *fw_data; 1224 unsigned fw_size; 1225 const struct mes_firmware_header_v1_0 *mes_hdr; 1226 int pipe, ucode_id, data_id; 1227 1228 for (pipe = 0; pipe < 2; pipe++) { 1229 if (pipe==0) { 1230 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1231 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1232 } else { 1233 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1234 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1235 } 1236 1237 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1238 adev->mes.fw[pipe]->data; 1239 1240 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1241 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1242 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1243 1244 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1245 ucode_id, fw_data, fw_size, fw_autoload_mask); 1246 1247 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1248 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1249 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1250 1251 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1252 data_id, fw_data, fw_size, fw_autoload_mask); 1253 } 1254 } 1255 1256 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1257 { 1258 uint32_t rlc_g_offset, rlc_g_size; 1259 uint64_t gpu_addr; 1260 uint32_t autoload_fw_id[2]; 1261 1262 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1263 1264 /* RLC autoload sequence 2: copy ucode */ 1265 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1266 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1267 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1268 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1269 1270 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1271 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1272 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1273 1274 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1275 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1276 1277 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1278 1279 /* RLC autoload sequence 3: load IMU fw */ 1280 if (adev->gfx.imu.funcs->load_microcode) 1281 adev->gfx.imu.funcs->load_microcode(adev); 1282 /* RLC autoload sequence 4 init IMU fw */ 1283 if (adev->gfx.imu.funcs->setup_imu) 1284 adev->gfx.imu.funcs->setup_imu(adev); 1285 if (adev->gfx.imu.funcs->start_imu) 1286 adev->gfx.imu.funcs->start_imu(adev); 1287 1288 /* RLC autoload sequence 5 disable gpa mode */ 1289 gfx_v11_0_disable_gpa_mode(adev); 1290 1291 return 0; 1292 } 1293 1294 static int gfx_v11_0_sw_init(void *handle) 1295 { 1296 int i, j, k, r, ring_id = 0; 1297 struct amdgpu_kiq *kiq; 1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1299 1300 adev->gfxhub.funcs->init(adev); 1301 1302 switch (adev->ip_versions[GC_HWIP][0]) { 1303 case IP_VERSION(11, 0, 0): 1304 case IP_VERSION(11, 0, 2): 1305 case IP_VERSION(11, 0, 3): 1306 adev->gfx.me.num_me = 1; 1307 adev->gfx.me.num_pipe_per_me = 1; 1308 adev->gfx.me.num_queue_per_pipe = 1; 1309 adev->gfx.mec.num_mec = 2; 1310 adev->gfx.mec.num_pipe_per_mec = 4; 1311 adev->gfx.mec.num_queue_per_pipe = 4; 1312 break; 1313 case IP_VERSION(11, 0, 1): 1314 case IP_VERSION(11, 0, 4): 1315 adev->gfx.me.num_me = 1; 1316 adev->gfx.me.num_pipe_per_me = 1; 1317 adev->gfx.me.num_queue_per_pipe = 1; 1318 adev->gfx.mec.num_mec = 1; 1319 adev->gfx.mec.num_pipe_per_mec = 4; 1320 adev->gfx.mec.num_queue_per_pipe = 4; 1321 break; 1322 default: 1323 adev->gfx.me.num_me = 1; 1324 adev->gfx.me.num_pipe_per_me = 1; 1325 adev->gfx.me.num_queue_per_pipe = 1; 1326 adev->gfx.mec.num_mec = 1; 1327 adev->gfx.mec.num_pipe_per_mec = 4; 1328 adev->gfx.mec.num_queue_per_pipe = 8; 1329 break; 1330 } 1331 1332 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1333 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3) && 1334 amdgpu_sriov_is_pp_one_vf(adev)) 1335 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1336 1337 /* EOP Event */ 1338 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1339 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1340 &adev->gfx.eop_irq); 1341 if (r) 1342 return r; 1343 1344 /* Privileged reg */ 1345 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1346 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1347 &adev->gfx.priv_reg_irq); 1348 if (r) 1349 return r; 1350 1351 /* Privileged inst */ 1352 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1353 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1354 &adev->gfx.priv_inst_irq); 1355 if (r) 1356 return r; 1357 1358 /* FED error */ 1359 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1360 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1361 &adev->gfx.rlc_gc_fed_irq); 1362 if (r) 1363 return r; 1364 1365 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1366 1367 if (adev->gfx.imu.funcs) { 1368 if (adev->gfx.imu.funcs->init_microcode) { 1369 r = adev->gfx.imu.funcs->init_microcode(adev); 1370 if (r) 1371 DRM_ERROR("Failed to load imu firmware!\n"); 1372 } 1373 } 1374 1375 gfx_v11_0_me_init(adev); 1376 1377 r = gfx_v11_0_rlc_init(adev); 1378 if (r) { 1379 DRM_ERROR("Failed to init rlc BOs!\n"); 1380 return r; 1381 } 1382 1383 r = gfx_v11_0_mec_init(adev); 1384 if (r) { 1385 DRM_ERROR("Failed to init MEC BOs!\n"); 1386 return r; 1387 } 1388 1389 /* set up the gfx ring */ 1390 for (i = 0; i < adev->gfx.me.num_me; i++) { 1391 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1392 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1393 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1394 continue; 1395 1396 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1397 i, k, j); 1398 if (r) 1399 return r; 1400 ring_id++; 1401 } 1402 } 1403 } 1404 1405 ring_id = 0; 1406 /* set up the compute queues - allocate horizontally across pipes */ 1407 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1408 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1409 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1410 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 1411 k, j)) 1412 continue; 1413 1414 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1415 i, k, j); 1416 if (r) 1417 return r; 1418 1419 ring_id++; 1420 } 1421 } 1422 } 1423 1424 if (!adev->enable_mes_kiq) { 1425 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); 1426 if (r) { 1427 DRM_ERROR("Failed to init KIQ BOs!\n"); 1428 return r; 1429 } 1430 1431 kiq = &adev->gfx.kiq[0]; 1432 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 1433 if (r) 1434 return r; 1435 } 1436 1437 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); 1438 if (r) 1439 return r; 1440 1441 /* allocate visible FB for rlc auto-loading fw */ 1442 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1443 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1444 if (r) 1445 return r; 1446 } 1447 1448 r = gfx_v11_0_gpu_early_init(adev); 1449 if (r) 1450 return r; 1451 1452 if (amdgpu_gfx_ras_sw_init(adev)) { 1453 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1454 return -EINVAL; 1455 } 1456 1457 return 0; 1458 } 1459 1460 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1461 { 1462 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1463 &adev->gfx.pfp.pfp_fw_gpu_addr, 1464 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1465 1466 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1467 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1468 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1469 } 1470 1471 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1472 { 1473 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1474 &adev->gfx.me.me_fw_gpu_addr, 1475 (void **)&adev->gfx.me.me_fw_ptr); 1476 1477 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1478 &adev->gfx.me.me_fw_data_gpu_addr, 1479 (void **)&adev->gfx.me.me_fw_data_ptr); 1480 } 1481 1482 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1483 { 1484 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1485 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1486 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1487 } 1488 1489 static int gfx_v11_0_sw_fini(void *handle) 1490 { 1491 int i; 1492 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1493 1494 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1495 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1496 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1497 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1498 1499 amdgpu_gfx_mqd_sw_fini(adev, 0); 1500 1501 if (!adev->enable_mes_kiq) { 1502 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 1503 amdgpu_gfx_kiq_fini(adev, 0); 1504 } 1505 1506 gfx_v11_0_pfp_fini(adev); 1507 gfx_v11_0_me_fini(adev); 1508 gfx_v11_0_rlc_fini(adev); 1509 gfx_v11_0_mec_fini(adev); 1510 1511 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1512 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1513 1514 gfx_v11_0_free_microcode(adev); 1515 1516 return 0; 1517 } 1518 1519 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1520 u32 sh_num, u32 instance, int xcc_id) 1521 { 1522 u32 data; 1523 1524 if (instance == 0xffffffff) 1525 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1526 INSTANCE_BROADCAST_WRITES, 1); 1527 else 1528 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1529 instance); 1530 1531 if (se_num == 0xffffffff) 1532 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1533 1); 1534 else 1535 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1536 1537 if (sh_num == 0xffffffff) 1538 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1539 1); 1540 else 1541 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1542 1543 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1544 } 1545 1546 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1547 { 1548 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1549 1550 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1551 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1552 CC_GC_SA_UNIT_DISABLE, 1553 SA_DISABLE); 1554 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1555 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1556 GC_USER_SA_UNIT_DISABLE, 1557 SA_DISABLE); 1558 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1559 adev->gfx.config.max_shader_engines); 1560 1561 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1562 } 1563 1564 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1565 { 1566 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1567 u32 rb_mask; 1568 1569 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1570 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1571 CC_RB_BACKEND_DISABLE, 1572 BACKEND_DISABLE); 1573 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1574 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1575 GC_USER_RB_BACKEND_DISABLE, 1576 BACKEND_DISABLE); 1577 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1578 adev->gfx.config.max_shader_engines); 1579 1580 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1581 } 1582 1583 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1584 { 1585 u32 rb_bitmap_width_per_sa; 1586 u32 max_sa; 1587 u32 active_sa_bitmap; 1588 u32 global_active_rb_bitmap; 1589 u32 active_rb_bitmap = 0; 1590 u32 i; 1591 1592 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1593 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 1594 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1595 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 1596 1597 /* generate active rb bitmap according to active sa bitmap */ 1598 max_sa = adev->gfx.config.max_shader_engines * 1599 adev->gfx.config.max_sh_per_se; 1600 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1601 adev->gfx.config.max_sh_per_se; 1602 for (i = 0; i < max_sa; i++) { 1603 if (active_sa_bitmap & (1 << i)) 1604 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1605 } 1606 1607 active_rb_bitmap |= global_active_rb_bitmap; 1608 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1609 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1610 } 1611 1612 #define DEFAULT_SH_MEM_BASES (0x6000) 1613 #define LDS_APP_BASE 0x1 1614 #define SCRATCH_APP_BASE 0x2 1615 1616 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1617 { 1618 int i; 1619 uint32_t sh_mem_bases; 1620 uint32_t data; 1621 1622 /* 1623 * Configure apertures: 1624 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1625 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1626 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1627 */ 1628 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1629 SCRATCH_APP_BASE; 1630 1631 mutex_lock(&adev->srbm_mutex); 1632 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1633 soc21_grbm_select(adev, 0, 0, 0, i); 1634 /* CP and shaders */ 1635 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1636 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1637 1638 /* Enable trap for each kfd vmid. */ 1639 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1640 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1641 } 1642 soc21_grbm_select(adev, 0, 0, 0, 0); 1643 mutex_unlock(&adev->srbm_mutex); 1644 1645 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1646 acccess. These should be enabled by FW for target VMIDs. */ 1647 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1648 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1649 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1650 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1651 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1652 } 1653 } 1654 1655 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1656 { 1657 int vmid; 1658 1659 /* 1660 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1661 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1662 * the driver can enable them for graphics. VMID0 should maintain 1663 * access so that HWS firmware can save/restore entries. 1664 */ 1665 for (vmid = 1; vmid < 16; vmid++) { 1666 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1667 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1668 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1669 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1670 } 1671 } 1672 1673 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1674 { 1675 /* TODO: harvest feature to be added later. */ 1676 } 1677 1678 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1679 { 1680 /* TCCs are global (not instanced). */ 1681 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1682 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1683 1684 adev->gfx.config.tcc_disabled_mask = 1685 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1686 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1687 } 1688 1689 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1690 { 1691 u32 tmp; 1692 int i; 1693 1694 if (!amdgpu_sriov_vf(adev)) 1695 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1696 1697 gfx_v11_0_setup_rb(adev); 1698 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1699 gfx_v11_0_get_tcc_info(adev); 1700 adev->gfx.config.pa_sc_tile_steering_override = 0; 1701 1702 /* Set whether texture coordinate truncation is conformant. */ 1703 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 1704 adev->gfx.config.ta_cntl2_truncate_coord_mode = 1705 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 1706 1707 /* XXX SH_MEM regs */ 1708 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1709 mutex_lock(&adev->srbm_mutex); 1710 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1711 soc21_grbm_select(adev, 0, 0, 0, i); 1712 /* CP and shaders */ 1713 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1714 if (i != 0) { 1715 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1716 (adev->gmc.private_aperture_start >> 48)); 1717 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1718 (adev->gmc.shared_aperture_start >> 48)); 1719 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1720 } 1721 } 1722 soc21_grbm_select(adev, 0, 0, 0, 0); 1723 1724 mutex_unlock(&adev->srbm_mutex); 1725 1726 gfx_v11_0_init_compute_vmid(adev); 1727 gfx_v11_0_init_gds_vmid(adev); 1728 } 1729 1730 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1731 bool enable) 1732 { 1733 u32 tmp; 1734 1735 if (amdgpu_sriov_vf(adev)) 1736 return; 1737 1738 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1739 1740 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1741 enable ? 1 : 0); 1742 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1743 enable ? 1 : 0); 1744 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1745 enable ? 1 : 0); 1746 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1747 enable ? 1 : 0); 1748 1749 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1750 } 1751 1752 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1753 { 1754 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1755 1756 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1757 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1758 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1759 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1760 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1761 1762 return 0; 1763 } 1764 1765 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1766 { 1767 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1768 1769 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1770 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1771 } 1772 1773 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1774 { 1775 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1776 udelay(50); 1777 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1778 udelay(50); 1779 } 1780 1781 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1782 bool enable) 1783 { 1784 uint32_t rlc_pg_cntl; 1785 1786 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1787 1788 if (!enable) { 1789 /* RLC_PG_CNTL[23] = 0 (default) 1790 * RLC will wait for handshake acks with SMU 1791 * GFXOFF will be enabled 1792 * RLC_PG_CNTL[23] = 1 1793 * RLC will not issue any message to SMU 1794 * hence no handshake between SMU & RLC 1795 * GFXOFF will be disabled 1796 */ 1797 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1798 } else 1799 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1800 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1801 } 1802 1803 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 1804 { 1805 /* TODO: enable rlc & smu handshake until smu 1806 * and gfxoff feature works as expected */ 1807 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1808 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 1809 1810 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1811 udelay(50); 1812 } 1813 1814 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 1815 { 1816 uint32_t tmp; 1817 1818 /* enable Save Restore Machine */ 1819 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1820 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1821 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1822 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1823 } 1824 1825 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 1826 { 1827 const struct rlc_firmware_header_v2_0 *hdr; 1828 const __le32 *fw_data; 1829 unsigned i, fw_size; 1830 1831 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1832 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1833 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1834 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1835 1836 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1837 RLCG_UCODE_LOADING_START_ADDRESS); 1838 1839 for (i = 0; i < fw_size; i++) 1840 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1841 le32_to_cpup(fw_data++)); 1842 1843 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1844 } 1845 1846 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1847 { 1848 const struct rlc_firmware_header_v2_2 *hdr; 1849 const __le32 *fw_data; 1850 unsigned i, fw_size; 1851 u32 tmp; 1852 1853 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1854 1855 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1856 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1857 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1858 1859 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1860 1861 for (i = 0; i < fw_size; i++) { 1862 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1863 msleep(1); 1864 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1865 le32_to_cpup(fw_data++)); 1866 } 1867 1868 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1869 1870 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1871 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1872 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1873 1874 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1875 for (i = 0; i < fw_size; i++) { 1876 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1877 msleep(1); 1878 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1879 le32_to_cpup(fw_data++)); 1880 } 1881 1882 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1883 1884 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1885 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1886 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1887 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1888 } 1889 1890 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 1891 { 1892 const struct rlc_firmware_header_v2_3 *hdr; 1893 const __le32 *fw_data; 1894 unsigned i, fw_size; 1895 u32 tmp; 1896 1897 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 1898 1899 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1900 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 1901 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 1902 1903 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 1904 1905 for (i = 0; i < fw_size; i++) { 1906 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1907 msleep(1); 1908 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 1909 le32_to_cpup(fw_data++)); 1910 } 1911 1912 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 1913 1914 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1915 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1916 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 1917 1918 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1919 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 1920 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 1921 1922 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 1923 1924 for (i = 0; i < fw_size; i++) { 1925 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1926 msleep(1); 1927 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 1928 le32_to_cpup(fw_data++)); 1929 } 1930 1931 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 1932 1933 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 1934 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 1935 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 1936 } 1937 1938 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 1939 { 1940 const struct rlc_firmware_header_v2_0 *hdr; 1941 uint16_t version_major; 1942 uint16_t version_minor; 1943 1944 if (!adev->gfx.rlc_fw) 1945 return -EINVAL; 1946 1947 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1948 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1949 1950 version_major = le16_to_cpu(hdr->header.header_version_major); 1951 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1952 1953 if (version_major == 2) { 1954 gfx_v11_0_load_rlcg_microcode(adev); 1955 if (amdgpu_dpm == 1) { 1956 if (version_minor >= 2) 1957 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 1958 if (version_minor == 3) 1959 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 1960 } 1961 1962 return 0; 1963 } 1964 1965 return -EINVAL; 1966 } 1967 1968 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 1969 { 1970 int r; 1971 1972 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1973 gfx_v11_0_init_csb(adev); 1974 1975 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1976 gfx_v11_0_rlc_enable_srm(adev); 1977 } else { 1978 if (amdgpu_sriov_vf(adev)) { 1979 gfx_v11_0_init_csb(adev); 1980 return 0; 1981 } 1982 1983 adev->gfx.rlc.funcs->stop(adev); 1984 1985 /* disable CG */ 1986 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1987 1988 /* disable PG */ 1989 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1990 1991 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1992 /* legacy rlc firmware loading */ 1993 r = gfx_v11_0_rlc_load_microcode(adev); 1994 if (r) 1995 return r; 1996 } 1997 1998 gfx_v11_0_init_csb(adev); 1999 2000 adev->gfx.rlc.funcs->start(adev); 2001 } 2002 return 0; 2003 } 2004 2005 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2006 { 2007 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2008 uint32_t tmp; 2009 int i; 2010 2011 /* Trigger an invalidation of the L1 instruction caches */ 2012 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2013 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2014 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2015 2016 /* Wait for invalidation complete */ 2017 for (i = 0; i < usec_timeout; i++) { 2018 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2019 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2020 INVALIDATE_CACHE_COMPLETE)) 2021 break; 2022 udelay(1); 2023 } 2024 2025 if (i >= usec_timeout) { 2026 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2027 return -EINVAL; 2028 } 2029 2030 if (amdgpu_emu_mode == 1) 2031 adev->hdp.funcs->flush_hdp(adev, NULL); 2032 2033 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2034 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2035 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2036 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2037 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2038 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2039 2040 /* Program me ucode address into intruction cache address register */ 2041 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2042 lower_32_bits(addr) & 0xFFFFF000); 2043 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2044 upper_32_bits(addr)); 2045 2046 return 0; 2047 } 2048 2049 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2050 { 2051 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2052 uint32_t tmp; 2053 int i; 2054 2055 /* Trigger an invalidation of the L1 instruction caches */ 2056 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2057 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2058 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2059 2060 /* Wait for invalidation complete */ 2061 for (i = 0; i < usec_timeout; i++) { 2062 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2063 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2064 INVALIDATE_CACHE_COMPLETE)) 2065 break; 2066 udelay(1); 2067 } 2068 2069 if (i >= usec_timeout) { 2070 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2071 return -EINVAL; 2072 } 2073 2074 if (amdgpu_emu_mode == 1) 2075 adev->hdp.funcs->flush_hdp(adev, NULL); 2076 2077 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2078 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2079 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2080 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2081 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2082 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2083 2084 /* Program pfp ucode address into intruction cache address register */ 2085 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2086 lower_32_bits(addr) & 0xFFFFF000); 2087 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2088 upper_32_bits(addr)); 2089 2090 return 0; 2091 } 2092 2093 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2094 { 2095 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2096 uint32_t tmp; 2097 int i; 2098 2099 /* Trigger an invalidation of the L1 instruction caches */ 2100 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2101 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2102 2103 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2104 2105 /* Wait for invalidation complete */ 2106 for (i = 0; i < usec_timeout; i++) { 2107 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2108 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2109 INVALIDATE_CACHE_COMPLETE)) 2110 break; 2111 udelay(1); 2112 } 2113 2114 if (i >= usec_timeout) { 2115 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2116 return -EINVAL; 2117 } 2118 2119 if (amdgpu_emu_mode == 1) 2120 adev->hdp.funcs->flush_hdp(adev, NULL); 2121 2122 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2123 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2124 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2125 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2126 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2127 2128 /* Program mec1 ucode address into intruction cache address register */ 2129 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2130 lower_32_bits(addr) & 0xFFFFF000); 2131 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2132 upper_32_bits(addr)); 2133 2134 return 0; 2135 } 2136 2137 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2138 { 2139 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2140 uint32_t tmp; 2141 unsigned i, pipe_id; 2142 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2143 2144 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2145 adev->gfx.pfp_fw->data; 2146 2147 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2148 lower_32_bits(addr)); 2149 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2150 upper_32_bits(addr)); 2151 2152 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2153 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2154 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2155 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2156 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2157 2158 /* 2159 * Programming any of the CP_PFP_IC_BASE registers 2160 * forces invalidation of the ME L1 I$. Wait for the 2161 * invalidation complete 2162 */ 2163 for (i = 0; i < usec_timeout; i++) { 2164 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2165 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2166 INVALIDATE_CACHE_COMPLETE)) 2167 break; 2168 udelay(1); 2169 } 2170 2171 if (i >= usec_timeout) { 2172 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2173 return -EINVAL; 2174 } 2175 2176 /* Prime the L1 instruction caches */ 2177 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2178 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2179 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2180 /* Waiting for cache primed*/ 2181 for (i = 0; i < usec_timeout; i++) { 2182 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2183 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2184 ICACHE_PRIMED)) 2185 break; 2186 udelay(1); 2187 } 2188 2189 if (i >= usec_timeout) { 2190 dev_err(adev->dev, "failed to prime instruction cache\n"); 2191 return -EINVAL; 2192 } 2193 2194 mutex_lock(&adev->srbm_mutex); 2195 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2196 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2197 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2198 (pfp_hdr->ucode_start_addr_hi << 30) | 2199 (pfp_hdr->ucode_start_addr_lo >> 2)); 2200 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2201 pfp_hdr->ucode_start_addr_hi >> 2); 2202 2203 /* 2204 * Program CP_ME_CNTL to reset given PIPE to take 2205 * effect of CP_PFP_PRGRM_CNTR_START. 2206 */ 2207 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2208 if (pipe_id == 0) 2209 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2210 PFP_PIPE0_RESET, 1); 2211 else 2212 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2213 PFP_PIPE1_RESET, 1); 2214 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2215 2216 /* Clear pfp pipe0 reset bit. */ 2217 if (pipe_id == 0) 2218 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2219 PFP_PIPE0_RESET, 0); 2220 else 2221 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2222 PFP_PIPE1_RESET, 0); 2223 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2224 2225 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2226 lower_32_bits(addr2)); 2227 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2228 upper_32_bits(addr2)); 2229 } 2230 soc21_grbm_select(adev, 0, 0, 0, 0); 2231 mutex_unlock(&adev->srbm_mutex); 2232 2233 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2234 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2235 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2236 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2237 2238 /* Invalidate the data caches */ 2239 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2240 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2241 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2242 2243 for (i = 0; i < usec_timeout; i++) { 2244 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2245 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2246 INVALIDATE_DCACHE_COMPLETE)) 2247 break; 2248 udelay(1); 2249 } 2250 2251 if (i >= usec_timeout) { 2252 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2253 return -EINVAL; 2254 } 2255 2256 return 0; 2257 } 2258 2259 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2260 { 2261 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2262 uint32_t tmp; 2263 unsigned i, pipe_id; 2264 const struct gfx_firmware_header_v2_0 *me_hdr; 2265 2266 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2267 adev->gfx.me_fw->data; 2268 2269 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2270 lower_32_bits(addr)); 2271 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2272 upper_32_bits(addr)); 2273 2274 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2275 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2276 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2277 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2278 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2279 2280 /* 2281 * Programming any of the CP_ME_IC_BASE registers 2282 * forces invalidation of the ME L1 I$. Wait for the 2283 * invalidation complete 2284 */ 2285 for (i = 0; i < usec_timeout; i++) { 2286 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2287 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2288 INVALIDATE_CACHE_COMPLETE)) 2289 break; 2290 udelay(1); 2291 } 2292 2293 if (i >= usec_timeout) { 2294 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2295 return -EINVAL; 2296 } 2297 2298 /* Prime the instruction caches */ 2299 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2300 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2301 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2302 2303 /* Waiting for instruction cache primed*/ 2304 for (i = 0; i < usec_timeout; i++) { 2305 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2306 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2307 ICACHE_PRIMED)) 2308 break; 2309 udelay(1); 2310 } 2311 2312 if (i >= usec_timeout) { 2313 dev_err(adev->dev, "failed to prime instruction cache\n"); 2314 return -EINVAL; 2315 } 2316 2317 mutex_lock(&adev->srbm_mutex); 2318 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2319 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2320 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2321 (me_hdr->ucode_start_addr_hi << 30) | 2322 (me_hdr->ucode_start_addr_lo >> 2) ); 2323 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2324 me_hdr->ucode_start_addr_hi>>2); 2325 2326 /* 2327 * Program CP_ME_CNTL to reset given PIPE to take 2328 * effect of CP_PFP_PRGRM_CNTR_START. 2329 */ 2330 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2331 if (pipe_id == 0) 2332 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2333 ME_PIPE0_RESET, 1); 2334 else 2335 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2336 ME_PIPE1_RESET, 1); 2337 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2338 2339 /* Clear pfp pipe0 reset bit. */ 2340 if (pipe_id == 0) 2341 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2342 ME_PIPE0_RESET, 0); 2343 else 2344 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2345 ME_PIPE1_RESET, 0); 2346 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2347 2348 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2349 lower_32_bits(addr2)); 2350 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2351 upper_32_bits(addr2)); 2352 } 2353 soc21_grbm_select(adev, 0, 0, 0, 0); 2354 mutex_unlock(&adev->srbm_mutex); 2355 2356 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2357 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2358 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2359 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2360 2361 /* Invalidate the data caches */ 2362 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2363 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2364 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2365 2366 for (i = 0; i < usec_timeout; i++) { 2367 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2368 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2369 INVALIDATE_DCACHE_COMPLETE)) 2370 break; 2371 udelay(1); 2372 } 2373 2374 if (i >= usec_timeout) { 2375 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2376 return -EINVAL; 2377 } 2378 2379 return 0; 2380 } 2381 2382 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2383 { 2384 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2385 uint32_t tmp; 2386 unsigned i; 2387 const struct gfx_firmware_header_v2_0 *mec_hdr; 2388 2389 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2390 adev->gfx.mec_fw->data; 2391 2392 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2393 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2394 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2395 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2396 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2397 2398 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2399 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2400 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2401 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2402 2403 mutex_lock(&adev->srbm_mutex); 2404 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2405 soc21_grbm_select(adev, 1, i, 0, 0); 2406 2407 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2408 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2409 upper_32_bits(addr2)); 2410 2411 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2412 mec_hdr->ucode_start_addr_lo >> 2 | 2413 mec_hdr->ucode_start_addr_hi << 30); 2414 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2415 mec_hdr->ucode_start_addr_hi >> 2); 2416 2417 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2418 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2419 upper_32_bits(addr)); 2420 } 2421 mutex_unlock(&adev->srbm_mutex); 2422 soc21_grbm_select(adev, 0, 0, 0, 0); 2423 2424 /* Trigger an invalidation of the L1 instruction caches */ 2425 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2426 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2427 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2428 2429 /* Wait for invalidation complete */ 2430 for (i = 0; i < usec_timeout; i++) { 2431 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2432 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2433 INVALIDATE_DCACHE_COMPLETE)) 2434 break; 2435 udelay(1); 2436 } 2437 2438 if (i >= usec_timeout) { 2439 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2440 return -EINVAL; 2441 } 2442 2443 /* Trigger an invalidation of the L1 instruction caches */ 2444 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2445 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2446 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2447 2448 /* Wait for invalidation complete */ 2449 for (i = 0; i < usec_timeout; i++) { 2450 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2451 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2452 INVALIDATE_CACHE_COMPLETE)) 2453 break; 2454 udelay(1); 2455 } 2456 2457 if (i >= usec_timeout) { 2458 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2459 return -EINVAL; 2460 } 2461 2462 return 0; 2463 } 2464 2465 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2466 { 2467 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2468 const struct gfx_firmware_header_v2_0 *me_hdr; 2469 const struct gfx_firmware_header_v2_0 *mec_hdr; 2470 uint32_t pipe_id, tmp; 2471 2472 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2473 adev->gfx.mec_fw->data; 2474 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2475 adev->gfx.me_fw->data; 2476 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2477 adev->gfx.pfp_fw->data; 2478 2479 /* config pfp program start addr */ 2480 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2481 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2482 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2483 (pfp_hdr->ucode_start_addr_hi << 30) | 2484 (pfp_hdr->ucode_start_addr_lo >> 2)); 2485 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2486 pfp_hdr->ucode_start_addr_hi >> 2); 2487 } 2488 soc21_grbm_select(adev, 0, 0, 0, 0); 2489 2490 /* reset pfp pipe */ 2491 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2492 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2493 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2494 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2495 2496 /* clear pfp pipe reset */ 2497 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2498 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2499 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2500 2501 /* config me program start addr */ 2502 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2503 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2504 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2505 (me_hdr->ucode_start_addr_hi << 30) | 2506 (me_hdr->ucode_start_addr_lo >> 2) ); 2507 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2508 me_hdr->ucode_start_addr_hi>>2); 2509 } 2510 soc21_grbm_select(adev, 0, 0, 0, 0); 2511 2512 /* reset me pipe */ 2513 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2514 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2515 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2516 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2517 2518 /* clear me pipe reset */ 2519 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2520 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2521 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2522 2523 /* config mec program start addr */ 2524 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2525 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2526 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2527 mec_hdr->ucode_start_addr_lo >> 2 | 2528 mec_hdr->ucode_start_addr_hi << 30); 2529 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2530 mec_hdr->ucode_start_addr_hi >> 2); 2531 } 2532 soc21_grbm_select(adev, 0, 0, 0, 0); 2533 2534 /* reset mec pipe */ 2535 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2536 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2537 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2538 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2539 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2540 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2541 2542 /* clear mec pipe reset */ 2543 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2544 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2545 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2546 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2547 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2548 } 2549 2550 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2551 { 2552 uint32_t cp_status; 2553 uint32_t bootload_status; 2554 int i, r; 2555 uint64_t addr, addr2; 2556 2557 for (i = 0; i < adev->usec_timeout; i++) { 2558 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2559 2560 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) || 2561 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4)) 2562 bootload_status = RREG32_SOC15(GC, 0, 2563 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2564 else 2565 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2566 2567 if ((cp_status == 0) && 2568 (REG_GET_FIELD(bootload_status, 2569 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2570 break; 2571 } 2572 udelay(1); 2573 } 2574 2575 if (i >= adev->usec_timeout) { 2576 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2577 return -ETIMEDOUT; 2578 } 2579 2580 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2581 if (adev->gfx.rs64_enable) { 2582 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2583 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2584 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2585 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2586 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2587 if (r) 2588 return r; 2589 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2590 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2591 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2592 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2593 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2594 if (r) 2595 return r; 2596 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2597 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2598 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2599 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2600 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2601 if (r) 2602 return r; 2603 } else { 2604 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2605 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2606 r = gfx_v11_0_config_me_cache(adev, addr); 2607 if (r) 2608 return r; 2609 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2610 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2611 r = gfx_v11_0_config_pfp_cache(adev, addr); 2612 if (r) 2613 return r; 2614 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2615 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2616 r = gfx_v11_0_config_mec_cache(adev, addr); 2617 if (r) 2618 return r; 2619 } 2620 } 2621 2622 return 0; 2623 } 2624 2625 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2626 { 2627 int i; 2628 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2629 2630 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2631 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2632 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2633 2634 for (i = 0; i < adev->usec_timeout; i++) { 2635 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2636 break; 2637 udelay(1); 2638 } 2639 2640 if (i >= adev->usec_timeout) 2641 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2642 2643 return 0; 2644 } 2645 2646 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2647 { 2648 int r; 2649 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2650 const __le32 *fw_data; 2651 unsigned i, fw_size; 2652 2653 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2654 adev->gfx.pfp_fw->data; 2655 2656 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2657 2658 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2659 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2660 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2661 2662 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2663 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2664 &adev->gfx.pfp.pfp_fw_obj, 2665 &adev->gfx.pfp.pfp_fw_gpu_addr, 2666 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2667 if (r) { 2668 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2669 gfx_v11_0_pfp_fini(adev); 2670 return r; 2671 } 2672 2673 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2674 2675 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2676 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2677 2678 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2679 2680 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2681 2682 for (i = 0; i < pfp_hdr->jt_size; i++) 2683 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2684 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2685 2686 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2687 2688 return 0; 2689 } 2690 2691 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2692 { 2693 int r; 2694 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2695 const __le32 *fw_ucode, *fw_data; 2696 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2697 uint32_t tmp; 2698 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2699 2700 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2701 adev->gfx.pfp_fw->data; 2702 2703 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2704 2705 /* instruction */ 2706 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2707 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2708 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2709 /* data */ 2710 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2711 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2712 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2713 2714 /* 64kb align */ 2715 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2716 64 * 1024, 2717 AMDGPU_GEM_DOMAIN_VRAM | 2718 AMDGPU_GEM_DOMAIN_GTT, 2719 &adev->gfx.pfp.pfp_fw_obj, 2720 &adev->gfx.pfp.pfp_fw_gpu_addr, 2721 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2722 if (r) { 2723 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2724 gfx_v11_0_pfp_fini(adev); 2725 return r; 2726 } 2727 2728 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2729 64 * 1024, 2730 AMDGPU_GEM_DOMAIN_VRAM | 2731 AMDGPU_GEM_DOMAIN_GTT, 2732 &adev->gfx.pfp.pfp_fw_data_obj, 2733 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2734 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2735 if (r) { 2736 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2737 gfx_v11_0_pfp_fini(adev); 2738 return r; 2739 } 2740 2741 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2742 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2743 2744 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2745 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2746 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2747 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2748 2749 if (amdgpu_emu_mode == 1) 2750 adev->hdp.funcs->flush_hdp(adev, NULL); 2751 2752 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2753 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2754 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2755 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2756 2757 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2758 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2759 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2760 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2761 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2762 2763 /* 2764 * Programming any of the CP_PFP_IC_BASE registers 2765 * forces invalidation of the ME L1 I$. Wait for the 2766 * invalidation complete 2767 */ 2768 for (i = 0; i < usec_timeout; i++) { 2769 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2770 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2771 INVALIDATE_CACHE_COMPLETE)) 2772 break; 2773 udelay(1); 2774 } 2775 2776 if (i >= usec_timeout) { 2777 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2778 return -EINVAL; 2779 } 2780 2781 /* Prime the L1 instruction caches */ 2782 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2783 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2784 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2785 /* Waiting for cache primed*/ 2786 for (i = 0; i < usec_timeout; i++) { 2787 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2788 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2789 ICACHE_PRIMED)) 2790 break; 2791 udelay(1); 2792 } 2793 2794 if (i >= usec_timeout) { 2795 dev_err(adev->dev, "failed to prime instruction cache\n"); 2796 return -EINVAL; 2797 } 2798 2799 mutex_lock(&adev->srbm_mutex); 2800 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2801 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2802 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2803 (pfp_hdr->ucode_start_addr_hi << 30) | 2804 (pfp_hdr->ucode_start_addr_lo >> 2) ); 2805 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2806 pfp_hdr->ucode_start_addr_hi>>2); 2807 2808 /* 2809 * Program CP_ME_CNTL to reset given PIPE to take 2810 * effect of CP_PFP_PRGRM_CNTR_START. 2811 */ 2812 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2813 if (pipe_id == 0) 2814 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2815 PFP_PIPE0_RESET, 1); 2816 else 2817 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2818 PFP_PIPE1_RESET, 1); 2819 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2820 2821 /* Clear pfp pipe0 reset bit. */ 2822 if (pipe_id == 0) 2823 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2824 PFP_PIPE0_RESET, 0); 2825 else 2826 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2827 PFP_PIPE1_RESET, 0); 2828 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2829 2830 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2831 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2832 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2833 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2834 } 2835 soc21_grbm_select(adev, 0, 0, 0, 0); 2836 mutex_unlock(&adev->srbm_mutex); 2837 2838 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2839 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2840 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2841 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2842 2843 /* Invalidate the data caches */ 2844 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2845 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2846 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2847 2848 for (i = 0; i < usec_timeout; i++) { 2849 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2850 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2851 INVALIDATE_DCACHE_COMPLETE)) 2852 break; 2853 udelay(1); 2854 } 2855 2856 if (i >= usec_timeout) { 2857 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2858 return -EINVAL; 2859 } 2860 2861 return 0; 2862 } 2863 2864 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2865 { 2866 int r; 2867 const struct gfx_firmware_header_v1_0 *me_hdr; 2868 const __le32 *fw_data; 2869 unsigned i, fw_size; 2870 2871 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2872 adev->gfx.me_fw->data; 2873 2874 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2875 2876 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2877 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2878 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2879 2880 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2881 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2882 &adev->gfx.me.me_fw_obj, 2883 &adev->gfx.me.me_fw_gpu_addr, 2884 (void **)&adev->gfx.me.me_fw_ptr); 2885 if (r) { 2886 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2887 gfx_v11_0_me_fini(adev); 2888 return r; 2889 } 2890 2891 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2892 2893 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2894 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2895 2896 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 2897 2898 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 2899 2900 for (i = 0; i < me_hdr->jt_size; i++) 2901 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 2902 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 2903 2904 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 2905 2906 return 0; 2907 } 2908 2909 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2910 { 2911 int r; 2912 const struct gfx_firmware_header_v2_0 *me_hdr; 2913 const __le32 *fw_ucode, *fw_data; 2914 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2915 uint32_t tmp; 2916 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2917 2918 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2919 adev->gfx.me_fw->data; 2920 2921 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2922 2923 /* instruction */ 2924 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2925 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2926 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2927 /* data */ 2928 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2929 le32_to_cpu(me_hdr->data_offset_bytes)); 2930 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2931 2932 /* 64kb align*/ 2933 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2934 64 * 1024, 2935 AMDGPU_GEM_DOMAIN_VRAM | 2936 AMDGPU_GEM_DOMAIN_GTT, 2937 &adev->gfx.me.me_fw_obj, 2938 &adev->gfx.me.me_fw_gpu_addr, 2939 (void **)&adev->gfx.me.me_fw_ptr); 2940 if (r) { 2941 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2942 gfx_v11_0_me_fini(adev); 2943 return r; 2944 } 2945 2946 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2947 64 * 1024, 2948 AMDGPU_GEM_DOMAIN_VRAM | 2949 AMDGPU_GEM_DOMAIN_GTT, 2950 &adev->gfx.me.me_fw_data_obj, 2951 &adev->gfx.me.me_fw_data_gpu_addr, 2952 (void **)&adev->gfx.me.me_fw_data_ptr); 2953 if (r) { 2954 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2955 gfx_v11_0_pfp_fini(adev); 2956 return r; 2957 } 2958 2959 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2960 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2961 2962 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2963 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2964 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2965 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2966 2967 if (amdgpu_emu_mode == 1) 2968 adev->hdp.funcs->flush_hdp(adev, NULL); 2969 2970 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2971 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2972 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2973 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2974 2975 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2976 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2977 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2978 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2979 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2980 2981 /* 2982 * Programming any of the CP_ME_IC_BASE registers 2983 * forces invalidation of the ME L1 I$. Wait for the 2984 * invalidation complete 2985 */ 2986 for (i = 0; i < usec_timeout; i++) { 2987 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2988 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2989 INVALIDATE_CACHE_COMPLETE)) 2990 break; 2991 udelay(1); 2992 } 2993 2994 if (i >= usec_timeout) { 2995 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2996 return -EINVAL; 2997 } 2998 2999 /* Prime the instruction caches */ 3000 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3001 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3002 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3003 3004 /* Waiting for instruction cache primed*/ 3005 for (i = 0; i < usec_timeout; i++) { 3006 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3007 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3008 ICACHE_PRIMED)) 3009 break; 3010 udelay(1); 3011 } 3012 3013 if (i >= usec_timeout) { 3014 dev_err(adev->dev, "failed to prime instruction cache\n"); 3015 return -EINVAL; 3016 } 3017 3018 mutex_lock(&adev->srbm_mutex); 3019 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3020 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3021 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3022 (me_hdr->ucode_start_addr_hi << 30) | 3023 (me_hdr->ucode_start_addr_lo >> 2) ); 3024 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3025 me_hdr->ucode_start_addr_hi>>2); 3026 3027 /* 3028 * Program CP_ME_CNTL to reset given PIPE to take 3029 * effect of CP_PFP_PRGRM_CNTR_START. 3030 */ 3031 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3032 if (pipe_id == 0) 3033 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3034 ME_PIPE0_RESET, 1); 3035 else 3036 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3037 ME_PIPE1_RESET, 1); 3038 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3039 3040 /* Clear pfp pipe0 reset bit. */ 3041 if (pipe_id == 0) 3042 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3043 ME_PIPE0_RESET, 0); 3044 else 3045 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3046 ME_PIPE1_RESET, 0); 3047 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3048 3049 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3050 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3051 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3052 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3053 } 3054 soc21_grbm_select(adev, 0, 0, 0, 0); 3055 mutex_unlock(&adev->srbm_mutex); 3056 3057 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3058 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3059 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3060 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3061 3062 /* Invalidate the data caches */ 3063 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3064 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3065 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3066 3067 for (i = 0; i < usec_timeout; i++) { 3068 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3069 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3070 INVALIDATE_DCACHE_COMPLETE)) 3071 break; 3072 udelay(1); 3073 } 3074 3075 if (i >= usec_timeout) { 3076 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3077 return -EINVAL; 3078 } 3079 3080 return 0; 3081 } 3082 3083 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3084 { 3085 int r; 3086 3087 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3088 return -EINVAL; 3089 3090 gfx_v11_0_cp_gfx_enable(adev, false); 3091 3092 if (adev->gfx.rs64_enable) 3093 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3094 else 3095 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3096 if (r) { 3097 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3098 return r; 3099 } 3100 3101 if (adev->gfx.rs64_enable) 3102 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3103 else 3104 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3105 if (r) { 3106 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3107 return r; 3108 } 3109 3110 return 0; 3111 } 3112 3113 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3114 { 3115 struct amdgpu_ring *ring; 3116 const struct cs_section_def *sect = NULL; 3117 const struct cs_extent_def *ext = NULL; 3118 int r, i; 3119 int ctx_reg_offset; 3120 3121 /* init the CP */ 3122 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3123 adev->gfx.config.max_hw_contexts - 1); 3124 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3125 3126 if (!amdgpu_async_gfx_ring) 3127 gfx_v11_0_cp_gfx_enable(adev, true); 3128 3129 ring = &adev->gfx.gfx_ring[0]; 3130 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3131 if (r) { 3132 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3133 return r; 3134 } 3135 3136 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3137 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3138 3139 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3140 amdgpu_ring_write(ring, 0x80000000); 3141 amdgpu_ring_write(ring, 0x80000000); 3142 3143 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3144 for (ext = sect->section; ext->extent != NULL; ++ext) { 3145 if (sect->id == SECT_CONTEXT) { 3146 amdgpu_ring_write(ring, 3147 PACKET3(PACKET3_SET_CONTEXT_REG, 3148 ext->reg_count)); 3149 amdgpu_ring_write(ring, ext->reg_index - 3150 PACKET3_SET_CONTEXT_REG_START); 3151 for (i = 0; i < ext->reg_count; i++) 3152 amdgpu_ring_write(ring, ext->extent[i]); 3153 } 3154 } 3155 } 3156 3157 ctx_reg_offset = 3158 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3159 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3160 amdgpu_ring_write(ring, ctx_reg_offset); 3161 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3162 3163 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3164 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3165 3166 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3167 amdgpu_ring_write(ring, 0); 3168 3169 amdgpu_ring_commit(ring); 3170 3171 /* submit cs packet to copy state 0 to next available state */ 3172 if (adev->gfx.num_gfx_rings > 1) { 3173 /* maximum supported gfx ring is 2 */ 3174 ring = &adev->gfx.gfx_ring[1]; 3175 r = amdgpu_ring_alloc(ring, 2); 3176 if (r) { 3177 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3178 return r; 3179 } 3180 3181 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3182 amdgpu_ring_write(ring, 0); 3183 3184 amdgpu_ring_commit(ring); 3185 } 3186 return 0; 3187 } 3188 3189 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3190 CP_PIPE_ID pipe) 3191 { 3192 u32 tmp; 3193 3194 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3195 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3196 3197 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3198 } 3199 3200 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3201 struct amdgpu_ring *ring) 3202 { 3203 u32 tmp; 3204 3205 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3206 if (ring->use_doorbell) { 3207 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3208 DOORBELL_OFFSET, ring->doorbell_index); 3209 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3210 DOORBELL_EN, 1); 3211 } else { 3212 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3213 DOORBELL_EN, 0); 3214 } 3215 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3216 3217 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3218 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3219 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3220 3221 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3222 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3223 } 3224 3225 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3226 { 3227 struct amdgpu_ring *ring; 3228 u32 tmp; 3229 u32 rb_bufsz; 3230 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3231 u32 i; 3232 3233 /* Set the write pointer delay */ 3234 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3235 3236 /* set the RB to use vmid 0 */ 3237 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3238 3239 /* Init gfx ring 0 for pipe 0 */ 3240 mutex_lock(&adev->srbm_mutex); 3241 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3242 3243 /* Set ring buffer size */ 3244 ring = &adev->gfx.gfx_ring[0]; 3245 rb_bufsz = order_base_2(ring->ring_size / 8); 3246 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3247 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3248 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3249 3250 /* Initialize the ring buffer's write pointers */ 3251 ring->wptr = 0; 3252 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3253 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3254 3255 /* set the wb address wether it's enabled or not */ 3256 rptr_addr = ring->rptr_gpu_addr; 3257 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3258 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3259 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3260 3261 wptr_gpu_addr = ring->wptr_gpu_addr; 3262 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3263 lower_32_bits(wptr_gpu_addr)); 3264 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3265 upper_32_bits(wptr_gpu_addr)); 3266 3267 mdelay(1); 3268 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3269 3270 rb_addr = ring->gpu_addr >> 8; 3271 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3272 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3273 3274 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3275 3276 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3277 mutex_unlock(&adev->srbm_mutex); 3278 3279 /* Init gfx ring 1 for pipe 1 */ 3280 if (adev->gfx.num_gfx_rings > 1) { 3281 mutex_lock(&adev->srbm_mutex); 3282 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3283 /* maximum supported gfx ring is 2 */ 3284 ring = &adev->gfx.gfx_ring[1]; 3285 rb_bufsz = order_base_2(ring->ring_size / 8); 3286 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3287 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3288 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3289 /* Initialize the ring buffer's write pointers */ 3290 ring->wptr = 0; 3291 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3292 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3293 /* Set the wb address wether it's enabled or not */ 3294 rptr_addr = ring->rptr_gpu_addr; 3295 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3296 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3297 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3298 wptr_gpu_addr = ring->wptr_gpu_addr; 3299 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3300 lower_32_bits(wptr_gpu_addr)); 3301 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3302 upper_32_bits(wptr_gpu_addr)); 3303 3304 mdelay(1); 3305 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3306 3307 rb_addr = ring->gpu_addr >> 8; 3308 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3309 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3310 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3311 3312 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3313 mutex_unlock(&adev->srbm_mutex); 3314 } 3315 /* Switch to pipe 0 */ 3316 mutex_lock(&adev->srbm_mutex); 3317 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3318 mutex_unlock(&adev->srbm_mutex); 3319 3320 /* start the ring */ 3321 gfx_v11_0_cp_gfx_start(adev); 3322 3323 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3324 ring = &adev->gfx.gfx_ring[i]; 3325 ring->sched.ready = true; 3326 } 3327 3328 return 0; 3329 } 3330 3331 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3332 { 3333 u32 data; 3334 3335 if (adev->gfx.rs64_enable) { 3336 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3337 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3338 enable ? 0 : 1); 3339 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3340 enable ? 0 : 1); 3341 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3342 enable ? 0 : 1); 3343 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3344 enable ? 0 : 1); 3345 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3346 enable ? 0 : 1); 3347 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3348 enable ? 1 : 0); 3349 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3350 enable ? 1 : 0); 3351 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3352 enable ? 1 : 0); 3353 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3354 enable ? 1 : 0); 3355 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3356 enable ? 0 : 1); 3357 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3358 } else { 3359 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3360 3361 if (enable) { 3362 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3363 if (!adev->enable_mes_kiq) 3364 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3365 MEC_ME2_HALT, 0); 3366 } else { 3367 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3368 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3369 } 3370 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3371 } 3372 3373 adev->gfx.kiq[0].ring.sched.ready = enable; 3374 3375 udelay(50); 3376 } 3377 3378 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3379 { 3380 const struct gfx_firmware_header_v1_0 *mec_hdr; 3381 const __le32 *fw_data; 3382 unsigned i, fw_size; 3383 u32 *fw = NULL; 3384 int r; 3385 3386 if (!adev->gfx.mec_fw) 3387 return -EINVAL; 3388 3389 gfx_v11_0_cp_compute_enable(adev, false); 3390 3391 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3392 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3393 3394 fw_data = (const __le32 *) 3395 (adev->gfx.mec_fw->data + 3396 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3397 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3398 3399 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3400 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3401 &adev->gfx.mec.mec_fw_obj, 3402 &adev->gfx.mec.mec_fw_gpu_addr, 3403 (void **)&fw); 3404 if (r) { 3405 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3406 gfx_v11_0_mec_fini(adev); 3407 return r; 3408 } 3409 3410 memcpy(fw, fw_data, fw_size); 3411 3412 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3413 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3414 3415 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3416 3417 /* MEC1 */ 3418 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3419 3420 for (i = 0; i < mec_hdr->jt_size; i++) 3421 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3422 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3423 3424 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3425 3426 return 0; 3427 } 3428 3429 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3430 { 3431 const struct gfx_firmware_header_v2_0 *mec_hdr; 3432 const __le32 *fw_ucode, *fw_data; 3433 u32 tmp, fw_ucode_size, fw_data_size; 3434 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3435 u32 *fw_ucode_ptr, *fw_data_ptr; 3436 int r; 3437 3438 if (!adev->gfx.mec_fw) 3439 return -EINVAL; 3440 3441 gfx_v11_0_cp_compute_enable(adev, false); 3442 3443 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3444 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3445 3446 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3447 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3448 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3449 3450 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3451 le32_to_cpu(mec_hdr->data_offset_bytes)); 3452 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3453 3454 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3455 64 * 1024, 3456 AMDGPU_GEM_DOMAIN_VRAM | 3457 AMDGPU_GEM_DOMAIN_GTT, 3458 &adev->gfx.mec.mec_fw_obj, 3459 &adev->gfx.mec.mec_fw_gpu_addr, 3460 (void **)&fw_ucode_ptr); 3461 if (r) { 3462 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3463 gfx_v11_0_mec_fini(adev); 3464 return r; 3465 } 3466 3467 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3468 64 * 1024, 3469 AMDGPU_GEM_DOMAIN_VRAM | 3470 AMDGPU_GEM_DOMAIN_GTT, 3471 &adev->gfx.mec.mec_fw_data_obj, 3472 &adev->gfx.mec.mec_fw_data_gpu_addr, 3473 (void **)&fw_data_ptr); 3474 if (r) { 3475 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3476 gfx_v11_0_mec_fini(adev); 3477 return r; 3478 } 3479 3480 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3481 memcpy(fw_data_ptr, fw_data, fw_data_size); 3482 3483 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3484 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3485 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3486 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3487 3488 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3489 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3490 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3491 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3492 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3493 3494 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3495 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3496 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3497 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3498 3499 mutex_lock(&adev->srbm_mutex); 3500 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3501 soc21_grbm_select(adev, 1, i, 0, 0); 3502 3503 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3504 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3505 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3506 3507 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3508 mec_hdr->ucode_start_addr_lo >> 2 | 3509 mec_hdr->ucode_start_addr_hi << 30); 3510 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3511 mec_hdr->ucode_start_addr_hi >> 2); 3512 3513 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3514 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3515 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3516 } 3517 mutex_unlock(&adev->srbm_mutex); 3518 soc21_grbm_select(adev, 0, 0, 0, 0); 3519 3520 /* Trigger an invalidation of the L1 instruction caches */ 3521 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3522 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3523 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3524 3525 /* Wait for invalidation complete */ 3526 for (i = 0; i < usec_timeout; i++) { 3527 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3528 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3529 INVALIDATE_DCACHE_COMPLETE)) 3530 break; 3531 udelay(1); 3532 } 3533 3534 if (i >= usec_timeout) { 3535 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3536 return -EINVAL; 3537 } 3538 3539 /* Trigger an invalidation of the L1 instruction caches */ 3540 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3541 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3542 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3543 3544 /* Wait for invalidation complete */ 3545 for (i = 0; i < usec_timeout; i++) { 3546 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3547 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3548 INVALIDATE_CACHE_COMPLETE)) 3549 break; 3550 udelay(1); 3551 } 3552 3553 if (i >= usec_timeout) { 3554 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3555 return -EINVAL; 3556 } 3557 3558 return 0; 3559 } 3560 3561 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3562 { 3563 uint32_t tmp; 3564 struct amdgpu_device *adev = ring->adev; 3565 3566 /* tell RLC which is KIQ queue */ 3567 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3568 tmp &= 0xffffff00; 3569 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3570 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3571 tmp |= 0x80; 3572 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3573 } 3574 3575 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3576 { 3577 /* set graphics engine doorbell range */ 3578 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3579 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3580 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3581 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3582 3583 /* set compute engine doorbell range */ 3584 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3585 (adev->doorbell_index.kiq * 2) << 2); 3586 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3587 (adev->doorbell_index.userqueue_end * 2) << 2); 3588 } 3589 3590 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3591 struct amdgpu_mqd_prop *prop) 3592 { 3593 struct v11_gfx_mqd *mqd = m; 3594 uint64_t hqd_gpu_addr, wb_gpu_addr; 3595 uint32_t tmp; 3596 uint32_t rb_bufsz; 3597 3598 /* set up gfx hqd wptr */ 3599 mqd->cp_gfx_hqd_wptr = 0; 3600 mqd->cp_gfx_hqd_wptr_hi = 0; 3601 3602 /* set the pointer to the MQD */ 3603 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3604 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3605 3606 /* set up mqd control */ 3607 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3608 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3609 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3610 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3611 mqd->cp_gfx_mqd_control = tmp; 3612 3613 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3614 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3615 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3616 mqd->cp_gfx_hqd_vmid = 0; 3617 3618 /* set up default queue priority level 3619 * 0x0 = low priority, 0x1 = high priority */ 3620 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3621 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3622 mqd->cp_gfx_hqd_queue_priority = tmp; 3623 3624 /* set up time quantum */ 3625 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3626 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3627 mqd->cp_gfx_hqd_quantum = tmp; 3628 3629 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3630 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3631 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3632 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3633 3634 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3635 wb_gpu_addr = prop->rptr_gpu_addr; 3636 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3637 mqd->cp_gfx_hqd_rptr_addr_hi = 3638 upper_32_bits(wb_gpu_addr) & 0xffff; 3639 3640 /* set up rb_wptr_poll addr */ 3641 wb_gpu_addr = prop->wptr_gpu_addr; 3642 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3643 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3644 3645 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3646 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3647 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3648 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3649 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3650 #ifdef __BIG_ENDIAN 3651 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3652 #endif 3653 mqd->cp_gfx_hqd_cntl = tmp; 3654 3655 /* set up cp_doorbell_control */ 3656 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3657 if (prop->use_doorbell) { 3658 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3659 DOORBELL_OFFSET, prop->doorbell_index); 3660 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3661 DOORBELL_EN, 1); 3662 } else 3663 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3664 DOORBELL_EN, 0); 3665 mqd->cp_rb_doorbell_control = tmp; 3666 3667 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3668 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3669 3670 /* active the queue */ 3671 mqd->cp_gfx_hqd_active = 1; 3672 3673 return 0; 3674 } 3675 3676 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3677 { 3678 struct amdgpu_device *adev = ring->adev; 3679 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3680 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3681 3682 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3683 memset((void *)mqd, 0, sizeof(*mqd)); 3684 mutex_lock(&adev->srbm_mutex); 3685 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3686 amdgpu_ring_init_mqd(ring); 3687 soc21_grbm_select(adev, 0, 0, 0, 0); 3688 mutex_unlock(&adev->srbm_mutex); 3689 if (adev->gfx.me.mqd_backup[mqd_idx]) 3690 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3691 } else { 3692 /* restore mqd with the backup copy */ 3693 if (adev->gfx.me.mqd_backup[mqd_idx]) 3694 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3695 /* reset the ring */ 3696 ring->wptr = 0; 3697 *ring->wptr_cpu_addr = 0; 3698 amdgpu_ring_clear_ring(ring); 3699 } 3700 3701 return 0; 3702 } 3703 3704 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3705 { 3706 int r, i; 3707 struct amdgpu_ring *ring; 3708 3709 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3710 ring = &adev->gfx.gfx_ring[i]; 3711 3712 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3713 if (unlikely(r != 0)) 3714 goto done; 3715 3716 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3717 if (!r) { 3718 r = gfx_v11_0_gfx_init_queue(ring); 3719 amdgpu_bo_kunmap(ring->mqd_obj); 3720 ring->mqd_ptr = NULL; 3721 } 3722 amdgpu_bo_unreserve(ring->mqd_obj); 3723 if (r) 3724 goto done; 3725 } 3726 3727 r = amdgpu_gfx_enable_kgq(adev, 0); 3728 if (r) 3729 goto done; 3730 3731 r = gfx_v11_0_cp_gfx_start(adev); 3732 if (r) 3733 goto done; 3734 3735 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3736 ring = &adev->gfx.gfx_ring[i]; 3737 ring->sched.ready = true; 3738 } 3739 done: 3740 return r; 3741 } 3742 3743 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3744 struct amdgpu_mqd_prop *prop) 3745 { 3746 struct v11_compute_mqd *mqd = m; 3747 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3748 uint32_t tmp; 3749 3750 mqd->header = 0xC0310800; 3751 mqd->compute_pipelinestat_enable = 0x00000001; 3752 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3753 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3754 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3755 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3756 mqd->compute_misc_reserved = 0x00000007; 3757 3758 eop_base_addr = prop->eop_gpu_addr >> 8; 3759 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3760 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3761 3762 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3763 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3764 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3765 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 3766 3767 mqd->cp_hqd_eop_control = tmp; 3768 3769 /* enable doorbell? */ 3770 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3771 3772 if (prop->use_doorbell) { 3773 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3774 DOORBELL_OFFSET, prop->doorbell_index); 3775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3776 DOORBELL_EN, 1); 3777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3778 DOORBELL_SOURCE, 0); 3779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3780 DOORBELL_HIT, 0); 3781 } else { 3782 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3783 DOORBELL_EN, 0); 3784 } 3785 3786 mqd->cp_hqd_pq_doorbell_control = tmp; 3787 3788 /* disable the queue if it's active */ 3789 mqd->cp_hqd_dequeue_request = 0; 3790 mqd->cp_hqd_pq_rptr = 0; 3791 mqd->cp_hqd_pq_wptr_lo = 0; 3792 mqd->cp_hqd_pq_wptr_hi = 0; 3793 3794 /* set the pointer to the MQD */ 3795 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3796 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3797 3798 /* set MQD vmid to 0 */ 3799 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3800 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3801 mqd->cp_mqd_control = tmp; 3802 3803 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3804 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3805 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3806 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3807 3808 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3809 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3810 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3811 (order_base_2(prop->queue_size / 4) - 1)); 3812 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3813 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3814 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3815 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3816 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3817 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3818 mqd->cp_hqd_pq_control = tmp; 3819 3820 /* set the wb address whether it's enabled or not */ 3821 wb_gpu_addr = prop->rptr_gpu_addr; 3822 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3823 mqd->cp_hqd_pq_rptr_report_addr_hi = 3824 upper_32_bits(wb_gpu_addr) & 0xffff; 3825 3826 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3827 wb_gpu_addr = prop->wptr_gpu_addr; 3828 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3829 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3830 3831 tmp = 0; 3832 /* enable the doorbell if requested */ 3833 if (prop->use_doorbell) { 3834 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3835 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3836 DOORBELL_OFFSET, prop->doorbell_index); 3837 3838 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3839 DOORBELL_EN, 1); 3840 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3841 DOORBELL_SOURCE, 0); 3842 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3843 DOORBELL_HIT, 0); 3844 } 3845 3846 mqd->cp_hqd_pq_doorbell_control = tmp; 3847 3848 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3849 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3850 3851 /* set the vmid for the queue */ 3852 mqd->cp_hqd_vmid = 0; 3853 3854 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3855 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3856 mqd->cp_hqd_persistent_state = tmp; 3857 3858 /* set MIN_IB_AVAIL_SIZE */ 3859 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3860 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3861 mqd->cp_hqd_ib_control = tmp; 3862 3863 /* set static priority for a compute queue/ring */ 3864 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3865 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3866 3867 mqd->cp_hqd_active = prop->hqd_active; 3868 3869 return 0; 3870 } 3871 3872 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 3873 { 3874 struct amdgpu_device *adev = ring->adev; 3875 struct v11_compute_mqd *mqd = ring->mqd_ptr; 3876 int j; 3877 3878 /* inactivate the queue */ 3879 if (amdgpu_sriov_vf(adev)) 3880 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3881 3882 /* disable wptr polling */ 3883 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3884 3885 /* write the EOP addr */ 3886 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3887 mqd->cp_hqd_eop_base_addr_lo); 3888 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3889 mqd->cp_hqd_eop_base_addr_hi); 3890 3891 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3892 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3893 mqd->cp_hqd_eop_control); 3894 3895 /* enable doorbell? */ 3896 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3897 mqd->cp_hqd_pq_doorbell_control); 3898 3899 /* disable the queue if it's active */ 3900 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3901 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3902 for (j = 0; j < adev->usec_timeout; j++) { 3903 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3904 break; 3905 udelay(1); 3906 } 3907 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3908 mqd->cp_hqd_dequeue_request); 3909 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3910 mqd->cp_hqd_pq_rptr); 3911 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3912 mqd->cp_hqd_pq_wptr_lo); 3913 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3914 mqd->cp_hqd_pq_wptr_hi); 3915 } 3916 3917 /* set the pointer to the MQD */ 3918 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3919 mqd->cp_mqd_base_addr_lo); 3920 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3921 mqd->cp_mqd_base_addr_hi); 3922 3923 /* set MQD vmid to 0 */ 3924 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3925 mqd->cp_mqd_control); 3926 3927 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3928 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3929 mqd->cp_hqd_pq_base_lo); 3930 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3931 mqd->cp_hqd_pq_base_hi); 3932 3933 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3934 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3935 mqd->cp_hqd_pq_control); 3936 3937 /* set the wb address whether it's enabled or not */ 3938 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3939 mqd->cp_hqd_pq_rptr_report_addr_lo); 3940 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3941 mqd->cp_hqd_pq_rptr_report_addr_hi); 3942 3943 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3944 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3945 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3946 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3947 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3948 3949 /* enable the doorbell if requested */ 3950 if (ring->use_doorbell) { 3951 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3952 (adev->doorbell_index.kiq * 2) << 2); 3953 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3954 (adev->doorbell_index.userqueue_end * 2) << 2); 3955 } 3956 3957 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3958 mqd->cp_hqd_pq_doorbell_control); 3959 3960 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3961 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3962 mqd->cp_hqd_pq_wptr_lo); 3963 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3964 mqd->cp_hqd_pq_wptr_hi); 3965 3966 /* set the vmid for the queue */ 3967 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 3968 3969 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 3970 mqd->cp_hqd_persistent_state); 3971 3972 /* activate the queue */ 3973 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 3974 mqd->cp_hqd_active); 3975 3976 if (ring->use_doorbell) 3977 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3978 3979 return 0; 3980 } 3981 3982 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 3983 { 3984 struct amdgpu_device *adev = ring->adev; 3985 struct v11_compute_mqd *mqd = ring->mqd_ptr; 3986 3987 gfx_v11_0_kiq_setting(ring); 3988 3989 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3990 /* reset MQD to a clean status */ 3991 if (adev->gfx.kiq[0].mqd_backup) 3992 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 3993 3994 /* reset ring buffer */ 3995 ring->wptr = 0; 3996 amdgpu_ring_clear_ring(ring); 3997 3998 mutex_lock(&adev->srbm_mutex); 3999 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4000 gfx_v11_0_kiq_init_register(ring); 4001 soc21_grbm_select(adev, 0, 0, 0, 0); 4002 mutex_unlock(&adev->srbm_mutex); 4003 } else { 4004 memset((void *)mqd, 0, sizeof(*mqd)); 4005 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4006 amdgpu_ring_clear_ring(ring); 4007 mutex_lock(&adev->srbm_mutex); 4008 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4009 amdgpu_ring_init_mqd(ring); 4010 gfx_v11_0_kiq_init_register(ring); 4011 soc21_grbm_select(adev, 0, 0, 0, 0); 4012 mutex_unlock(&adev->srbm_mutex); 4013 4014 if (adev->gfx.kiq[0].mqd_backup) 4015 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 4016 } 4017 4018 return 0; 4019 } 4020 4021 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4022 { 4023 struct amdgpu_device *adev = ring->adev; 4024 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4025 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4026 4027 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4028 memset((void *)mqd, 0, sizeof(*mqd)); 4029 mutex_lock(&adev->srbm_mutex); 4030 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4031 amdgpu_ring_init_mqd(ring); 4032 soc21_grbm_select(adev, 0, 0, 0, 0); 4033 mutex_unlock(&adev->srbm_mutex); 4034 4035 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4036 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4037 } else { 4038 /* restore MQD to a clean status */ 4039 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4040 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4041 /* reset ring buffer */ 4042 ring->wptr = 0; 4043 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4044 amdgpu_ring_clear_ring(ring); 4045 } 4046 4047 return 0; 4048 } 4049 4050 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4051 { 4052 struct amdgpu_ring *ring; 4053 int r; 4054 4055 ring = &adev->gfx.kiq[0].ring; 4056 4057 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4058 if (unlikely(r != 0)) 4059 return r; 4060 4061 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4062 if (unlikely(r != 0)) { 4063 amdgpu_bo_unreserve(ring->mqd_obj); 4064 return r; 4065 } 4066 4067 gfx_v11_0_kiq_init_queue(ring); 4068 amdgpu_bo_kunmap(ring->mqd_obj); 4069 ring->mqd_ptr = NULL; 4070 amdgpu_bo_unreserve(ring->mqd_obj); 4071 ring->sched.ready = true; 4072 return 0; 4073 } 4074 4075 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4076 { 4077 struct amdgpu_ring *ring = NULL; 4078 int r = 0, i; 4079 4080 if (!amdgpu_async_gfx_ring) 4081 gfx_v11_0_cp_compute_enable(adev, true); 4082 4083 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4084 ring = &adev->gfx.compute_ring[i]; 4085 4086 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4087 if (unlikely(r != 0)) 4088 goto done; 4089 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4090 if (!r) { 4091 r = gfx_v11_0_kcq_init_queue(ring); 4092 amdgpu_bo_kunmap(ring->mqd_obj); 4093 ring->mqd_ptr = NULL; 4094 } 4095 amdgpu_bo_unreserve(ring->mqd_obj); 4096 if (r) 4097 goto done; 4098 } 4099 4100 r = amdgpu_gfx_enable_kcq(adev, 0); 4101 done: 4102 return r; 4103 } 4104 4105 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4106 { 4107 int r, i; 4108 struct amdgpu_ring *ring; 4109 4110 if (!(adev->flags & AMD_IS_APU)) 4111 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4112 4113 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4114 /* legacy firmware loading */ 4115 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4116 if (r) 4117 return r; 4118 4119 if (adev->gfx.rs64_enable) 4120 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4121 else 4122 r = gfx_v11_0_cp_compute_load_microcode(adev); 4123 if (r) 4124 return r; 4125 } 4126 4127 gfx_v11_0_cp_set_doorbell_range(adev); 4128 4129 if (amdgpu_async_gfx_ring) { 4130 gfx_v11_0_cp_compute_enable(adev, true); 4131 gfx_v11_0_cp_gfx_enable(adev, true); 4132 } 4133 4134 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4135 r = amdgpu_mes_kiq_hw_init(adev); 4136 else 4137 r = gfx_v11_0_kiq_resume(adev); 4138 if (r) 4139 return r; 4140 4141 r = gfx_v11_0_kcq_resume(adev); 4142 if (r) 4143 return r; 4144 4145 if (!amdgpu_async_gfx_ring) { 4146 r = gfx_v11_0_cp_gfx_resume(adev); 4147 if (r) 4148 return r; 4149 } else { 4150 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4151 if (r) 4152 return r; 4153 } 4154 4155 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4156 ring = &adev->gfx.gfx_ring[i]; 4157 r = amdgpu_ring_test_helper(ring); 4158 if (r) 4159 return r; 4160 } 4161 4162 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4163 ring = &adev->gfx.compute_ring[i]; 4164 r = amdgpu_ring_test_helper(ring); 4165 if (r) 4166 return r; 4167 } 4168 4169 return 0; 4170 } 4171 4172 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4173 { 4174 gfx_v11_0_cp_gfx_enable(adev, enable); 4175 gfx_v11_0_cp_compute_enable(adev, enable); 4176 } 4177 4178 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4179 { 4180 int r; 4181 bool value; 4182 4183 r = adev->gfxhub.funcs->gart_enable(adev); 4184 if (r) 4185 return r; 4186 4187 adev->hdp.funcs->flush_hdp(adev, NULL); 4188 4189 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4190 false : true; 4191 4192 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4193 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 4194 4195 return 0; 4196 } 4197 4198 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4199 { 4200 u32 tmp; 4201 4202 /* select RS64 */ 4203 if (adev->gfx.rs64_enable) { 4204 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4205 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4206 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4207 4208 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4209 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4210 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4211 } 4212 4213 if (amdgpu_emu_mode == 1) 4214 msleep(100); 4215 } 4216 4217 static int get_gb_addr_config(struct amdgpu_device * adev) 4218 { 4219 u32 gb_addr_config; 4220 4221 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4222 if (gb_addr_config == 0) 4223 return -EINVAL; 4224 4225 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4226 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4227 4228 adev->gfx.config.gb_addr_config = gb_addr_config; 4229 4230 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4231 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4232 GB_ADDR_CONFIG, NUM_PIPES); 4233 4234 adev->gfx.config.max_tile_pipes = 4235 adev->gfx.config.gb_addr_config_fields.num_pipes; 4236 4237 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4238 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4239 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4240 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4241 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4242 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4243 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4244 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4245 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4246 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4247 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4248 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4249 4250 return 0; 4251 } 4252 4253 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4254 { 4255 uint32_t data; 4256 4257 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4258 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4259 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4260 4261 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4262 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4263 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4264 } 4265 4266 static int gfx_v11_0_hw_init(void *handle) 4267 { 4268 int r; 4269 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4270 4271 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4272 if (adev->gfx.imu.funcs) { 4273 /* RLC autoload sequence 1: Program rlc ram */ 4274 if (adev->gfx.imu.funcs->program_rlc_ram) 4275 adev->gfx.imu.funcs->program_rlc_ram(adev); 4276 } 4277 /* rlc autoload firmware */ 4278 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4279 if (r) 4280 return r; 4281 } else { 4282 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4283 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4284 if (adev->gfx.imu.funcs->load_microcode) 4285 adev->gfx.imu.funcs->load_microcode(adev); 4286 if (adev->gfx.imu.funcs->setup_imu) 4287 adev->gfx.imu.funcs->setup_imu(adev); 4288 if (adev->gfx.imu.funcs->start_imu) 4289 adev->gfx.imu.funcs->start_imu(adev); 4290 } 4291 4292 /* disable gpa mode in backdoor loading */ 4293 gfx_v11_0_disable_gpa_mode(adev); 4294 } 4295 } 4296 4297 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4298 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4299 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4300 if (r) { 4301 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4302 return r; 4303 } 4304 } 4305 4306 adev->gfx.is_poweron = true; 4307 4308 if(get_gb_addr_config(adev)) 4309 DRM_WARN("Invalid gb_addr_config !\n"); 4310 4311 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4312 adev->gfx.rs64_enable) 4313 gfx_v11_0_config_gfx_rs64(adev); 4314 4315 r = gfx_v11_0_gfxhub_enable(adev); 4316 if (r) 4317 return r; 4318 4319 if (!amdgpu_emu_mode) 4320 gfx_v11_0_init_golden_registers(adev); 4321 4322 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4323 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4324 /** 4325 * For gfx 11, rlc firmware loading relies on smu firmware is 4326 * loaded firstly, so in direct type, it has to load smc ucode 4327 * here before rlc. 4328 */ 4329 if (!(adev->flags & AMD_IS_APU)) { 4330 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4331 if (r) 4332 return r; 4333 } 4334 } 4335 4336 gfx_v11_0_constants_init(adev); 4337 4338 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4339 gfx_v11_0_select_cp_fw_arch(adev); 4340 4341 if (adev->nbio.funcs->gc_doorbell_init) 4342 adev->nbio.funcs->gc_doorbell_init(adev); 4343 4344 r = gfx_v11_0_rlc_resume(adev); 4345 if (r) 4346 return r; 4347 4348 /* 4349 * init golden registers and rlc resume may override some registers, 4350 * reconfig them here 4351 */ 4352 gfx_v11_0_tcp_harvest(adev); 4353 4354 r = gfx_v11_0_cp_resume(adev); 4355 if (r) 4356 return r; 4357 4358 return r; 4359 } 4360 4361 static int gfx_v11_0_hw_fini(void *handle) 4362 { 4363 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4364 4365 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4366 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4367 4368 if (!adev->no_hw_access) { 4369 if (amdgpu_async_gfx_ring) { 4370 if (amdgpu_gfx_disable_kgq(adev, 0)) 4371 DRM_ERROR("KGQ disable failed\n"); 4372 } 4373 4374 if (amdgpu_gfx_disable_kcq(adev, 0)) 4375 DRM_ERROR("KCQ disable failed\n"); 4376 4377 amdgpu_mes_kiq_hw_fini(adev); 4378 } 4379 4380 if (amdgpu_sriov_vf(adev)) 4381 /* Remove the steps disabling CPG and clearing KIQ position, 4382 * so that CP could perform IDLE-SAVE during switch. Those 4383 * steps are necessary to avoid a DMAR error in gfx9 but it is 4384 * not reproduced on gfx11. 4385 */ 4386 return 0; 4387 4388 gfx_v11_0_cp_enable(adev, false); 4389 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4390 4391 adev->gfxhub.funcs->gart_disable(adev); 4392 4393 adev->gfx.is_poweron = false; 4394 4395 return 0; 4396 } 4397 4398 static int gfx_v11_0_suspend(void *handle) 4399 { 4400 return gfx_v11_0_hw_fini(handle); 4401 } 4402 4403 static int gfx_v11_0_resume(void *handle) 4404 { 4405 return gfx_v11_0_hw_init(handle); 4406 } 4407 4408 static bool gfx_v11_0_is_idle(void *handle) 4409 { 4410 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4411 4412 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4413 GRBM_STATUS, GUI_ACTIVE)) 4414 return false; 4415 else 4416 return true; 4417 } 4418 4419 static int gfx_v11_0_wait_for_idle(void *handle) 4420 { 4421 unsigned i; 4422 u32 tmp; 4423 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4424 4425 for (i = 0; i < adev->usec_timeout; i++) { 4426 /* read MC_STATUS */ 4427 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4428 GRBM_STATUS__GUI_ACTIVE_MASK; 4429 4430 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4431 return 0; 4432 udelay(1); 4433 } 4434 return -ETIMEDOUT; 4435 } 4436 4437 static int gfx_v11_0_soft_reset(void *handle) 4438 { 4439 u32 grbm_soft_reset = 0; 4440 u32 tmp; 4441 int i, j, k; 4442 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4443 4444 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4445 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4446 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4447 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4448 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4449 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4450 4451 gfx_v11_0_set_safe_mode(adev, 0); 4452 4453 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4454 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4455 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4456 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4457 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4458 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4459 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4460 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4461 4462 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4463 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4464 } 4465 } 4466 } 4467 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4468 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4469 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4470 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4471 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4472 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4473 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4474 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4475 4476 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4477 } 4478 } 4479 } 4480 4481 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4482 4483 // Read CP_VMID_RESET register three times. 4484 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4485 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4486 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4487 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4488 4489 for (i = 0; i < adev->usec_timeout; i++) { 4490 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4491 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4492 break; 4493 udelay(1); 4494 } 4495 if (i >= adev->usec_timeout) { 4496 printk("Failed to wait all pipes clean\n"); 4497 return -EINVAL; 4498 } 4499 4500 /********** trigger soft reset ***********/ 4501 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4502 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4503 SOFT_RESET_CP, 1); 4504 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4505 SOFT_RESET_GFX, 1); 4506 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4507 SOFT_RESET_CPF, 1); 4508 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4509 SOFT_RESET_CPC, 1); 4510 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4511 SOFT_RESET_CPG, 1); 4512 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4513 /********** exit soft reset ***********/ 4514 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4515 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4516 SOFT_RESET_CP, 0); 4517 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4518 SOFT_RESET_GFX, 0); 4519 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4520 SOFT_RESET_CPF, 0); 4521 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4522 SOFT_RESET_CPC, 0); 4523 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4524 SOFT_RESET_CPG, 0); 4525 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4526 4527 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4528 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4529 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4530 4531 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4532 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4533 4534 for (i = 0; i < adev->usec_timeout; i++) { 4535 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4536 break; 4537 udelay(1); 4538 } 4539 if (i >= adev->usec_timeout) { 4540 printk("Failed to wait CP_VMID_RESET to 0\n"); 4541 return -EINVAL; 4542 } 4543 4544 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4545 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4546 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4547 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4548 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4549 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4550 4551 gfx_v11_0_unset_safe_mode(adev, 0); 4552 4553 return gfx_v11_0_cp_resume(adev); 4554 } 4555 4556 static bool gfx_v11_0_check_soft_reset(void *handle) 4557 { 4558 int i, r; 4559 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4560 struct amdgpu_ring *ring; 4561 long tmo = msecs_to_jiffies(1000); 4562 4563 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4564 ring = &adev->gfx.gfx_ring[i]; 4565 r = amdgpu_ring_test_ib(ring, tmo); 4566 if (r) 4567 return true; 4568 } 4569 4570 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4571 ring = &adev->gfx.compute_ring[i]; 4572 r = amdgpu_ring_test_ib(ring, tmo); 4573 if (r) 4574 return true; 4575 } 4576 4577 return false; 4578 } 4579 4580 static int gfx_v11_0_post_soft_reset(void *handle) 4581 { 4582 /** 4583 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 4584 */ 4585 return amdgpu_mes_resume((struct amdgpu_device *)handle); 4586 } 4587 4588 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4589 { 4590 uint64_t clock; 4591 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 4592 4593 if (amdgpu_sriov_vf(adev)) { 4594 amdgpu_gfx_off_ctrl(adev, false); 4595 mutex_lock(&adev->gfx.gpu_clock_mutex); 4596 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4597 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4598 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4599 if (clock_counter_hi_pre != clock_counter_hi_after) 4600 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4601 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4602 amdgpu_gfx_off_ctrl(adev, true); 4603 } else { 4604 preempt_disable(); 4605 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4606 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4607 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4608 if (clock_counter_hi_pre != clock_counter_hi_after) 4609 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4610 preempt_enable(); 4611 } 4612 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 4613 4614 return clock; 4615 } 4616 4617 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4618 uint32_t vmid, 4619 uint32_t gds_base, uint32_t gds_size, 4620 uint32_t gws_base, uint32_t gws_size, 4621 uint32_t oa_base, uint32_t oa_size) 4622 { 4623 struct amdgpu_device *adev = ring->adev; 4624 4625 /* GDS Base */ 4626 gfx_v11_0_write_data_to_reg(ring, 0, false, 4627 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4628 gds_base); 4629 4630 /* GDS Size */ 4631 gfx_v11_0_write_data_to_reg(ring, 0, false, 4632 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4633 gds_size); 4634 4635 /* GWS */ 4636 gfx_v11_0_write_data_to_reg(ring, 0, false, 4637 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4638 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4639 4640 /* OA */ 4641 gfx_v11_0_write_data_to_reg(ring, 0, false, 4642 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4643 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4644 } 4645 4646 static int gfx_v11_0_early_init(void *handle) 4647 { 4648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4649 4650 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 4651 4652 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4653 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4654 AMDGPU_MAX_COMPUTE_RINGS); 4655 4656 gfx_v11_0_set_kiq_pm4_funcs(adev); 4657 gfx_v11_0_set_ring_funcs(adev); 4658 gfx_v11_0_set_irq_funcs(adev); 4659 gfx_v11_0_set_gds_init(adev); 4660 gfx_v11_0_set_rlc_funcs(adev); 4661 gfx_v11_0_set_mqd_funcs(adev); 4662 gfx_v11_0_set_imu_funcs(adev); 4663 4664 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4665 4666 return gfx_v11_0_init_microcode(adev); 4667 } 4668 4669 static int gfx_v11_0_ras_late_init(void *handle) 4670 { 4671 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4672 struct ras_common_if *gfx_common_if; 4673 int ret; 4674 4675 gfx_common_if = kzalloc(sizeof(struct ras_common_if), GFP_KERNEL); 4676 if (!gfx_common_if) 4677 return -ENOMEM; 4678 4679 gfx_common_if->block = AMDGPU_RAS_BLOCK__GFX; 4680 4681 ret = amdgpu_ras_feature_enable(adev, gfx_common_if, true); 4682 if (ret) 4683 dev_warn(adev->dev, "Failed to enable gfx11 ras feature\n"); 4684 4685 kfree(gfx_common_if); 4686 return 0; 4687 } 4688 4689 static int gfx_v11_0_late_init(void *handle) 4690 { 4691 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4692 int r; 4693 4694 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4695 if (r) 4696 return r; 4697 4698 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4699 if (r) 4700 return r; 4701 4702 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) { 4703 r = gfx_v11_0_ras_late_init(handle); 4704 if (r) 4705 return r; 4706 } 4707 4708 return 0; 4709 } 4710 4711 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4712 { 4713 uint32_t rlc_cntl; 4714 4715 /* if RLC is not enabled, do nothing */ 4716 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4717 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4718 } 4719 4720 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 4721 { 4722 uint32_t data; 4723 unsigned i; 4724 4725 data = RLC_SAFE_MODE__CMD_MASK; 4726 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4727 4728 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4729 4730 /* wait for RLC_SAFE_MODE */ 4731 for (i = 0; i < adev->usec_timeout; i++) { 4732 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4733 RLC_SAFE_MODE, CMD)) 4734 break; 4735 udelay(1); 4736 } 4737 } 4738 4739 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 4740 { 4741 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4742 } 4743 4744 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 4745 bool enable) 4746 { 4747 uint32_t def, data; 4748 4749 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4750 return; 4751 4752 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4753 4754 if (enable) 4755 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4756 else 4757 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4758 4759 if (def != data) 4760 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4761 } 4762 4763 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 4764 bool enable) 4765 { 4766 uint32_t def, data; 4767 4768 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4769 return; 4770 4771 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4772 4773 if (enable) 4774 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4775 else 4776 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4777 4778 if (def != data) 4779 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4780 } 4781 4782 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 4783 bool enable) 4784 { 4785 uint32_t def, data; 4786 4787 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4788 return; 4789 4790 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4791 4792 if (enable) 4793 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4794 else 4795 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4796 4797 if (def != data) 4798 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4799 } 4800 4801 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4802 bool enable) 4803 { 4804 uint32_t data, def; 4805 4806 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4807 return; 4808 4809 /* It is disabled by HW by default */ 4810 if (enable) { 4811 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4812 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4813 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4814 4815 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4816 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4817 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4818 4819 if (def != data) 4820 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4821 } 4822 } else { 4823 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4824 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4825 4826 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4827 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4828 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4829 4830 if (def != data) 4831 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4832 } 4833 } 4834 } 4835 4836 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4837 bool enable) 4838 { 4839 uint32_t def, data; 4840 4841 if (!(adev->cg_flags & 4842 (AMD_CG_SUPPORT_GFX_CGCG | 4843 AMD_CG_SUPPORT_GFX_CGLS | 4844 AMD_CG_SUPPORT_GFX_3D_CGCG | 4845 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4846 return; 4847 4848 if (enable) { 4849 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4850 4851 /* unset CGCG override */ 4852 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4853 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4854 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4855 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4856 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4857 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4858 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4859 4860 /* update CGCG override bits */ 4861 if (def != data) 4862 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4863 4864 /* enable cgcg FSM(0x0000363F) */ 4865 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4866 4867 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4868 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4869 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4870 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4871 } 4872 4873 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4874 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4875 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4876 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4877 } 4878 4879 if (def != data) 4880 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4881 4882 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4883 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4884 4885 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4886 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4887 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4888 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4889 } 4890 4891 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4892 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4893 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4894 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4895 } 4896 4897 if (def != data) 4898 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4899 4900 /* set IDLE_POLL_COUNT(0x00900100) */ 4901 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4902 4903 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4904 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4905 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4906 4907 if (def != data) 4908 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4909 4910 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4911 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4912 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4913 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4914 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4915 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4916 4917 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4918 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4919 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4920 4921 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4922 if (adev->sdma.num_instances > 1) { 4923 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4924 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 4925 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4926 } 4927 } else { 4928 /* Program RLC_CGCG_CGLS_CTRL */ 4929 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4930 4931 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4932 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4933 4934 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4935 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4936 4937 if (def != data) 4938 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4939 4940 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4941 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4942 4943 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4944 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4945 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4946 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4947 4948 if (def != data) 4949 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4950 4951 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 4952 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4953 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 4954 4955 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 4956 if (adev->sdma.num_instances > 1) { 4957 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 4958 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 4959 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 4960 } 4961 } 4962 } 4963 4964 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4965 bool enable) 4966 { 4967 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4968 4969 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 4970 4971 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 4972 4973 gfx_v11_0_update_repeater_fgcg(adev, enable); 4974 4975 gfx_v11_0_update_sram_fgcg(adev, enable); 4976 4977 gfx_v11_0_update_perf_clk(adev, enable); 4978 4979 if (adev->cg_flags & 4980 (AMD_CG_SUPPORT_GFX_MGCG | 4981 AMD_CG_SUPPORT_GFX_CGLS | 4982 AMD_CG_SUPPORT_GFX_CGCG | 4983 AMD_CG_SUPPORT_GFX_3D_CGCG | 4984 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4985 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 4986 4987 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4988 4989 return 0; 4990 } 4991 4992 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4993 { 4994 u32 reg, data; 4995 4996 amdgpu_gfx_off_ctrl(adev, false); 4997 4998 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 4999 if (amdgpu_sriov_is_pp_one_vf(adev)) 5000 data = RREG32_NO_KIQ(reg); 5001 else 5002 data = RREG32(reg); 5003 5004 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5005 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5006 5007 if (amdgpu_sriov_is_pp_one_vf(adev)) 5008 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5009 else 5010 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5011 5012 amdgpu_gfx_off_ctrl(adev, true); 5013 } 5014 5015 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5016 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5017 .set_safe_mode = gfx_v11_0_set_safe_mode, 5018 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5019 .init = gfx_v11_0_rlc_init, 5020 .get_csb_size = gfx_v11_0_get_csb_size, 5021 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5022 .resume = gfx_v11_0_rlc_resume, 5023 .stop = gfx_v11_0_rlc_stop, 5024 .reset = gfx_v11_0_rlc_reset, 5025 .start = gfx_v11_0_rlc_start, 5026 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5027 }; 5028 5029 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5030 { 5031 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5032 5033 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5034 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5035 else 5036 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5037 5038 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5039 5040 // Program RLC_PG_DELAY3 for CGPG hysteresis 5041 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5042 switch (adev->ip_versions[GC_HWIP][0]) { 5043 case IP_VERSION(11, 0, 1): 5044 case IP_VERSION(11, 0, 4): 5045 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5046 break; 5047 default: 5048 break; 5049 } 5050 } 5051 } 5052 5053 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5054 { 5055 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 5056 5057 gfx_v11_cntl_power_gating(adev, enable); 5058 5059 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 5060 } 5061 5062 static int gfx_v11_0_set_powergating_state(void *handle, 5063 enum amd_powergating_state state) 5064 { 5065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5066 bool enable = (state == AMD_PG_STATE_GATE); 5067 5068 if (amdgpu_sriov_vf(adev)) 5069 return 0; 5070 5071 switch (adev->ip_versions[GC_HWIP][0]) { 5072 case IP_VERSION(11, 0, 0): 5073 case IP_VERSION(11, 0, 2): 5074 case IP_VERSION(11, 0, 3): 5075 amdgpu_gfx_off_ctrl(adev, enable); 5076 break; 5077 case IP_VERSION(11, 0, 1): 5078 case IP_VERSION(11, 0, 4): 5079 if (!enable) 5080 amdgpu_gfx_off_ctrl(adev, false); 5081 5082 gfx_v11_cntl_pg(adev, enable); 5083 5084 if (enable) 5085 amdgpu_gfx_off_ctrl(adev, true); 5086 5087 break; 5088 default: 5089 break; 5090 } 5091 5092 return 0; 5093 } 5094 5095 static int gfx_v11_0_set_clockgating_state(void *handle, 5096 enum amd_clockgating_state state) 5097 { 5098 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5099 5100 if (amdgpu_sriov_vf(adev)) 5101 return 0; 5102 5103 switch (adev->ip_versions[GC_HWIP][0]) { 5104 case IP_VERSION(11, 0, 0): 5105 case IP_VERSION(11, 0, 1): 5106 case IP_VERSION(11, 0, 2): 5107 case IP_VERSION(11, 0, 3): 5108 case IP_VERSION(11, 0, 4): 5109 gfx_v11_0_update_gfx_clock_gating(adev, 5110 state == AMD_CG_STATE_GATE); 5111 break; 5112 default: 5113 break; 5114 } 5115 5116 return 0; 5117 } 5118 5119 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5120 { 5121 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5122 int data; 5123 5124 /* AMD_CG_SUPPORT_GFX_MGCG */ 5125 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5126 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5127 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5128 5129 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5130 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5131 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5132 5133 /* AMD_CG_SUPPORT_GFX_FGCG */ 5134 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5135 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5136 5137 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5138 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5139 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5140 5141 /* AMD_CG_SUPPORT_GFX_CGCG */ 5142 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5143 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5144 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5145 5146 /* AMD_CG_SUPPORT_GFX_CGLS */ 5147 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5148 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5149 5150 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5151 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5152 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5153 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5154 5155 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5156 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5157 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5158 } 5159 5160 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5161 { 5162 /* gfx11 is 32bit rptr*/ 5163 return *(uint32_t *)ring->rptr_cpu_addr; 5164 } 5165 5166 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5167 { 5168 struct amdgpu_device *adev = ring->adev; 5169 u64 wptr; 5170 5171 /* XXX check if swapping is necessary on BE */ 5172 if (ring->use_doorbell) { 5173 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5174 } else { 5175 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5176 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5177 } 5178 5179 return wptr; 5180 } 5181 5182 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5183 { 5184 struct amdgpu_device *adev = ring->adev; 5185 uint32_t *wptr_saved; 5186 uint32_t *is_queue_unmap; 5187 uint64_t aggregated_db_index; 5188 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 5189 uint64_t wptr_tmp; 5190 5191 if (ring->is_mes_queue) { 5192 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5193 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5194 sizeof(uint32_t)); 5195 aggregated_db_index = 5196 amdgpu_mes_get_aggregated_doorbell_index(adev, 5197 ring->hw_prio); 5198 5199 wptr_tmp = ring->wptr & ring->buf_mask; 5200 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5201 *wptr_saved = wptr_tmp; 5202 /* assume doorbell always being used by mes mapped queue */ 5203 if (*is_queue_unmap) { 5204 WDOORBELL64(aggregated_db_index, wptr_tmp); 5205 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5206 } else { 5207 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5208 5209 if (*is_queue_unmap) 5210 WDOORBELL64(aggregated_db_index, wptr_tmp); 5211 } 5212 } else { 5213 if (ring->use_doorbell) { 5214 /* XXX check if swapping is necessary on BE */ 5215 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5216 ring->wptr); 5217 WDOORBELL64(ring->doorbell_index, ring->wptr); 5218 } else { 5219 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5220 lower_32_bits(ring->wptr)); 5221 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5222 upper_32_bits(ring->wptr)); 5223 } 5224 } 5225 } 5226 5227 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5228 { 5229 /* gfx11 hardware is 32bit rptr */ 5230 return *(uint32_t *)ring->rptr_cpu_addr; 5231 } 5232 5233 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5234 { 5235 u64 wptr; 5236 5237 /* XXX check if swapping is necessary on BE */ 5238 if (ring->use_doorbell) 5239 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5240 else 5241 BUG(); 5242 return wptr; 5243 } 5244 5245 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5246 { 5247 struct amdgpu_device *adev = ring->adev; 5248 uint32_t *wptr_saved; 5249 uint32_t *is_queue_unmap; 5250 uint64_t aggregated_db_index; 5251 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 5252 uint64_t wptr_tmp; 5253 5254 if (ring->is_mes_queue) { 5255 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5256 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5257 sizeof(uint32_t)); 5258 aggregated_db_index = 5259 amdgpu_mes_get_aggregated_doorbell_index(adev, 5260 ring->hw_prio); 5261 5262 wptr_tmp = ring->wptr & ring->buf_mask; 5263 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5264 *wptr_saved = wptr_tmp; 5265 /* assume doorbell always used by mes mapped queue */ 5266 if (*is_queue_unmap) { 5267 WDOORBELL64(aggregated_db_index, wptr_tmp); 5268 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5269 } else { 5270 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5271 5272 if (*is_queue_unmap) 5273 WDOORBELL64(aggregated_db_index, wptr_tmp); 5274 } 5275 } else { 5276 /* XXX check if swapping is necessary on BE */ 5277 if (ring->use_doorbell) { 5278 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5279 ring->wptr); 5280 WDOORBELL64(ring->doorbell_index, ring->wptr); 5281 } else { 5282 BUG(); /* only DOORBELL method supported on gfx11 now */ 5283 } 5284 } 5285 } 5286 5287 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5288 { 5289 struct amdgpu_device *adev = ring->adev; 5290 u32 ref_and_mask, reg_mem_engine; 5291 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5292 5293 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5294 switch (ring->me) { 5295 case 1: 5296 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5297 break; 5298 case 2: 5299 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5300 break; 5301 default: 5302 return; 5303 } 5304 reg_mem_engine = 0; 5305 } else { 5306 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5307 reg_mem_engine = 1; /* pfp */ 5308 } 5309 5310 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5311 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5312 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5313 ref_and_mask, ref_and_mask, 0x20); 5314 } 5315 5316 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5317 struct amdgpu_job *job, 5318 struct amdgpu_ib *ib, 5319 uint32_t flags) 5320 { 5321 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5322 u32 header, control = 0; 5323 5324 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5325 5326 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5327 5328 control |= ib->length_dw | (vmid << 24); 5329 5330 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5331 control |= INDIRECT_BUFFER_PRE_ENB(1); 5332 5333 if (flags & AMDGPU_IB_PREEMPTED) 5334 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5335 5336 if (vmid) 5337 gfx_v11_0_ring_emit_de_meta(ring, 5338 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5339 } 5340 5341 if (ring->is_mes_queue) 5342 /* inherit vmid from mqd */ 5343 control |= 0x400000; 5344 5345 amdgpu_ring_write(ring, header); 5346 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5347 amdgpu_ring_write(ring, 5348 #ifdef __BIG_ENDIAN 5349 (2 << 0) | 5350 #endif 5351 lower_32_bits(ib->gpu_addr)); 5352 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5353 amdgpu_ring_write(ring, control); 5354 } 5355 5356 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5357 struct amdgpu_job *job, 5358 struct amdgpu_ib *ib, 5359 uint32_t flags) 5360 { 5361 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5362 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5363 5364 if (ring->is_mes_queue) 5365 /* inherit vmid from mqd */ 5366 control |= 0x40000000; 5367 5368 /* Currently, there is a high possibility to get wave ID mismatch 5369 * between ME and GDS, leading to a hw deadlock, because ME generates 5370 * different wave IDs than the GDS expects. This situation happens 5371 * randomly when at least 5 compute pipes use GDS ordered append. 5372 * The wave IDs generated by ME are also wrong after suspend/resume. 5373 * Those are probably bugs somewhere else in the kernel driver. 5374 * 5375 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5376 * GDS to 0 for this ring (me/pipe). 5377 */ 5378 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5379 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5380 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5381 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5382 } 5383 5384 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5385 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5386 amdgpu_ring_write(ring, 5387 #ifdef __BIG_ENDIAN 5388 (2 << 0) | 5389 #endif 5390 lower_32_bits(ib->gpu_addr)); 5391 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5392 amdgpu_ring_write(ring, control); 5393 } 5394 5395 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5396 u64 seq, unsigned flags) 5397 { 5398 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5399 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5400 5401 /* RELEASE_MEM - flush caches, send int */ 5402 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5403 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5404 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5405 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5406 PACKET3_RELEASE_MEM_GCR_GL2_US | 5407 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5408 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5409 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5410 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5411 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5412 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5413 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5414 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5415 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5416 5417 /* 5418 * the address should be Qword aligned if 64bit write, Dword 5419 * aligned if only send 32bit data low (discard data high) 5420 */ 5421 if (write64bit) 5422 BUG_ON(addr & 0x7); 5423 else 5424 BUG_ON(addr & 0x3); 5425 amdgpu_ring_write(ring, lower_32_bits(addr)); 5426 amdgpu_ring_write(ring, upper_32_bits(addr)); 5427 amdgpu_ring_write(ring, lower_32_bits(seq)); 5428 amdgpu_ring_write(ring, upper_32_bits(seq)); 5429 amdgpu_ring_write(ring, ring->is_mes_queue ? 5430 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5431 } 5432 5433 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5434 { 5435 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5436 uint32_t seq = ring->fence_drv.sync_seq; 5437 uint64_t addr = ring->fence_drv.gpu_addr; 5438 5439 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5440 upper_32_bits(addr), seq, 0xffffffff, 4); 5441 } 5442 5443 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5444 uint16_t pasid, uint32_t flush_type, 5445 bool all_hub, uint8_t dst_sel) 5446 { 5447 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5448 amdgpu_ring_write(ring, 5449 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5450 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5451 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5452 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5453 } 5454 5455 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5456 unsigned vmid, uint64_t pd_addr) 5457 { 5458 if (ring->is_mes_queue) 5459 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5460 else 5461 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5462 5463 /* compute doesn't have PFP */ 5464 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5465 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5466 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5467 amdgpu_ring_write(ring, 0x0); 5468 } 5469 } 5470 5471 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5472 u64 seq, unsigned int flags) 5473 { 5474 struct amdgpu_device *adev = ring->adev; 5475 5476 /* we only allocate 32bit for each seq wb address */ 5477 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5478 5479 /* write fence seq to the "addr" */ 5480 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5481 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5482 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5483 amdgpu_ring_write(ring, lower_32_bits(addr)); 5484 amdgpu_ring_write(ring, upper_32_bits(addr)); 5485 amdgpu_ring_write(ring, lower_32_bits(seq)); 5486 5487 if (flags & AMDGPU_FENCE_FLAG_INT) { 5488 /* set register to trigger INT */ 5489 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5490 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5491 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5492 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5493 amdgpu_ring_write(ring, 0); 5494 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5495 } 5496 } 5497 5498 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5499 uint32_t flags) 5500 { 5501 uint32_t dw2 = 0; 5502 5503 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5504 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5505 /* set load_global_config & load_global_uconfig */ 5506 dw2 |= 0x8001; 5507 /* set load_cs_sh_regs */ 5508 dw2 |= 0x01000000; 5509 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5510 dw2 |= 0x10002; 5511 } 5512 5513 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5514 amdgpu_ring_write(ring, dw2); 5515 amdgpu_ring_write(ring, 0); 5516 } 5517 5518 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring, 5519 u64 shadow_va, u64 csa_va, 5520 u64 gds_va, bool init_shadow, 5521 int vmid) 5522 { 5523 struct amdgpu_device *adev = ring->adev; 5524 5525 if (!adev->gfx.cp_gfx_shadow) 5526 return; 5527 5528 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7)); 5529 amdgpu_ring_write(ring, lower_32_bits(shadow_va)); 5530 amdgpu_ring_write(ring, upper_32_bits(shadow_va)); 5531 amdgpu_ring_write(ring, lower_32_bits(gds_va)); 5532 amdgpu_ring_write(ring, upper_32_bits(gds_va)); 5533 amdgpu_ring_write(ring, lower_32_bits(csa_va)); 5534 amdgpu_ring_write(ring, upper_32_bits(csa_va)); 5535 amdgpu_ring_write(ring, shadow_va ? 5536 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); 5537 amdgpu_ring_write(ring, init_shadow ? 5538 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); 5539 } 5540 5541 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5542 { 5543 unsigned ret; 5544 5545 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5546 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5547 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5548 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5549 ret = ring->wptr & ring->buf_mask; 5550 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5551 5552 return ret; 5553 } 5554 5555 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5556 { 5557 unsigned cur; 5558 BUG_ON(offset > ring->buf_mask); 5559 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5560 5561 cur = (ring->wptr - 1) & ring->buf_mask; 5562 if (likely(cur > offset)) 5563 ring->ring[offset] = cur - offset; 5564 else 5565 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5566 } 5567 5568 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5569 { 5570 int i, r = 0; 5571 struct amdgpu_device *adev = ring->adev; 5572 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 5573 struct amdgpu_ring *kiq_ring = &kiq->ring; 5574 unsigned long flags; 5575 5576 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5577 return -EINVAL; 5578 5579 spin_lock_irqsave(&kiq->ring_lock, flags); 5580 5581 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5582 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5583 return -ENOMEM; 5584 } 5585 5586 /* assert preemption condition */ 5587 amdgpu_ring_set_preempt_cond_exec(ring, false); 5588 5589 /* assert IB preemption, emit the trailing fence */ 5590 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5591 ring->trail_fence_gpu_addr, 5592 ++ring->trail_seq); 5593 amdgpu_ring_commit(kiq_ring); 5594 5595 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5596 5597 /* poll the trailing fence */ 5598 for (i = 0; i < adev->usec_timeout; i++) { 5599 if (ring->trail_seq == 5600 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5601 break; 5602 udelay(1); 5603 } 5604 5605 if (i >= adev->usec_timeout) { 5606 r = -EINVAL; 5607 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5608 } 5609 5610 /* deassert preemption condition */ 5611 amdgpu_ring_set_preempt_cond_exec(ring, true); 5612 return r; 5613 } 5614 5615 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5616 { 5617 struct amdgpu_device *adev = ring->adev; 5618 struct v10_de_ib_state de_payload = {0}; 5619 uint64_t offset, gds_addr, de_payload_gpu_addr; 5620 void *de_payload_cpu_addr; 5621 int cnt; 5622 5623 if (ring->is_mes_queue) { 5624 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5625 gfx[0].gfx_meta_data) + 5626 offsetof(struct v10_gfx_meta_data, de_payload); 5627 de_payload_gpu_addr = 5628 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5629 de_payload_cpu_addr = 5630 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5631 5632 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5633 gfx[0].gds_backup) + 5634 offsetof(struct v10_gfx_meta_data, de_payload); 5635 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5636 } else { 5637 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5638 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5639 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5640 5641 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5642 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5643 PAGE_SIZE); 5644 } 5645 5646 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5647 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5648 5649 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5650 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5651 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5652 WRITE_DATA_DST_SEL(8) | 5653 WR_CONFIRM) | 5654 WRITE_DATA_CACHE_POLICY(0)); 5655 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5656 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5657 5658 if (resume) 5659 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5660 sizeof(de_payload) >> 2); 5661 else 5662 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5663 sizeof(de_payload) >> 2); 5664 } 5665 5666 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5667 bool secure) 5668 { 5669 uint32_t v = secure ? FRAME_TMZ : 0; 5670 5671 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5672 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5673 } 5674 5675 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5676 uint32_t reg_val_offs) 5677 { 5678 struct amdgpu_device *adev = ring->adev; 5679 5680 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5681 amdgpu_ring_write(ring, 0 | /* src: register*/ 5682 (5 << 8) | /* dst: memory */ 5683 (1 << 20)); /* write confirm */ 5684 amdgpu_ring_write(ring, reg); 5685 amdgpu_ring_write(ring, 0); 5686 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5687 reg_val_offs * 4)); 5688 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5689 reg_val_offs * 4)); 5690 } 5691 5692 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5693 uint32_t val) 5694 { 5695 uint32_t cmd = 0; 5696 5697 switch (ring->funcs->type) { 5698 case AMDGPU_RING_TYPE_GFX: 5699 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5700 break; 5701 case AMDGPU_RING_TYPE_KIQ: 5702 cmd = (1 << 16); /* no inc addr */ 5703 break; 5704 default: 5705 cmd = WR_CONFIRM; 5706 break; 5707 } 5708 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5709 amdgpu_ring_write(ring, cmd); 5710 amdgpu_ring_write(ring, reg); 5711 amdgpu_ring_write(ring, 0); 5712 amdgpu_ring_write(ring, val); 5713 } 5714 5715 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5716 uint32_t val, uint32_t mask) 5717 { 5718 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5719 } 5720 5721 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5722 uint32_t reg0, uint32_t reg1, 5723 uint32_t ref, uint32_t mask) 5724 { 5725 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5726 5727 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5728 ref, mask, 0x20); 5729 } 5730 5731 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5732 unsigned vmid) 5733 { 5734 struct amdgpu_device *adev = ring->adev; 5735 uint32_t value = 0; 5736 5737 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5738 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5739 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5740 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5741 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5742 } 5743 5744 static void 5745 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5746 uint32_t me, uint32_t pipe, 5747 enum amdgpu_interrupt_state state) 5748 { 5749 uint32_t cp_int_cntl, cp_int_cntl_reg; 5750 5751 if (!me) { 5752 switch (pipe) { 5753 case 0: 5754 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5755 break; 5756 case 1: 5757 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5758 break; 5759 default: 5760 DRM_DEBUG("invalid pipe %d\n", pipe); 5761 return; 5762 } 5763 } else { 5764 DRM_DEBUG("invalid me %d\n", me); 5765 return; 5766 } 5767 5768 switch (state) { 5769 case AMDGPU_IRQ_STATE_DISABLE: 5770 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5771 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5772 TIME_STAMP_INT_ENABLE, 0); 5773 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5774 GENERIC0_INT_ENABLE, 0); 5775 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5776 break; 5777 case AMDGPU_IRQ_STATE_ENABLE: 5778 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5779 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5780 TIME_STAMP_INT_ENABLE, 1); 5781 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5782 GENERIC0_INT_ENABLE, 1); 5783 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5784 break; 5785 default: 5786 break; 5787 } 5788 } 5789 5790 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5791 int me, int pipe, 5792 enum amdgpu_interrupt_state state) 5793 { 5794 u32 mec_int_cntl, mec_int_cntl_reg; 5795 5796 /* 5797 * amdgpu controls only the first MEC. That's why this function only 5798 * handles the setting of interrupts for this specific MEC. All other 5799 * pipes' interrupts are set by amdkfd. 5800 */ 5801 5802 if (me == 1) { 5803 switch (pipe) { 5804 case 0: 5805 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5806 break; 5807 case 1: 5808 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5809 break; 5810 case 2: 5811 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5812 break; 5813 case 3: 5814 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5815 break; 5816 default: 5817 DRM_DEBUG("invalid pipe %d\n", pipe); 5818 return; 5819 } 5820 } else { 5821 DRM_DEBUG("invalid me %d\n", me); 5822 return; 5823 } 5824 5825 switch (state) { 5826 case AMDGPU_IRQ_STATE_DISABLE: 5827 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5828 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5829 TIME_STAMP_INT_ENABLE, 0); 5830 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5831 GENERIC0_INT_ENABLE, 0); 5832 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5833 break; 5834 case AMDGPU_IRQ_STATE_ENABLE: 5835 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5836 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5837 TIME_STAMP_INT_ENABLE, 1); 5838 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5839 GENERIC0_INT_ENABLE, 1); 5840 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5841 break; 5842 default: 5843 break; 5844 } 5845 } 5846 5847 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5848 struct amdgpu_irq_src *src, 5849 unsigned type, 5850 enum amdgpu_interrupt_state state) 5851 { 5852 switch (type) { 5853 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5854 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 5855 break; 5856 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 5857 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 5858 break; 5859 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5860 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5861 break; 5862 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5863 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5864 break; 5865 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5866 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5867 break; 5868 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5869 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5870 break; 5871 default: 5872 break; 5873 } 5874 return 0; 5875 } 5876 5877 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 5878 struct amdgpu_irq_src *source, 5879 struct amdgpu_iv_entry *entry) 5880 { 5881 int i; 5882 u8 me_id, pipe_id, queue_id; 5883 struct amdgpu_ring *ring; 5884 uint32_t mes_queue_id = entry->src_data[0]; 5885 5886 DRM_DEBUG("IH: CP EOP\n"); 5887 5888 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 5889 struct amdgpu_mes_queue *queue; 5890 5891 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 5892 5893 spin_lock(&adev->mes.queue_id_lock); 5894 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 5895 if (queue) { 5896 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 5897 amdgpu_fence_process(queue->ring); 5898 } 5899 spin_unlock(&adev->mes.queue_id_lock); 5900 } else { 5901 me_id = (entry->ring_id & 0x0c) >> 2; 5902 pipe_id = (entry->ring_id & 0x03) >> 0; 5903 queue_id = (entry->ring_id & 0x70) >> 4; 5904 5905 switch (me_id) { 5906 case 0: 5907 if (pipe_id == 0) 5908 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5909 else 5910 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5911 break; 5912 case 1: 5913 case 2: 5914 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5915 ring = &adev->gfx.compute_ring[i]; 5916 /* Per-queue interrupt is supported for MEC starting from VI. 5917 * The interrupt can only be enabled/disabled per pipe instead 5918 * of per queue. 5919 */ 5920 if ((ring->me == me_id) && 5921 (ring->pipe == pipe_id) && 5922 (ring->queue == queue_id)) 5923 amdgpu_fence_process(ring); 5924 } 5925 break; 5926 } 5927 } 5928 5929 return 0; 5930 } 5931 5932 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5933 struct amdgpu_irq_src *source, 5934 unsigned type, 5935 enum amdgpu_interrupt_state state) 5936 { 5937 switch (state) { 5938 case AMDGPU_IRQ_STATE_DISABLE: 5939 case AMDGPU_IRQ_STATE_ENABLE: 5940 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5941 PRIV_REG_INT_ENABLE, 5942 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5943 break; 5944 default: 5945 break; 5946 } 5947 5948 return 0; 5949 } 5950 5951 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5952 struct amdgpu_irq_src *source, 5953 unsigned type, 5954 enum amdgpu_interrupt_state state) 5955 { 5956 switch (state) { 5957 case AMDGPU_IRQ_STATE_DISABLE: 5958 case AMDGPU_IRQ_STATE_ENABLE: 5959 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5960 PRIV_INSTR_INT_ENABLE, 5961 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5962 break; 5963 default: 5964 break; 5965 } 5966 5967 return 0; 5968 } 5969 5970 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 5971 struct amdgpu_iv_entry *entry) 5972 { 5973 u8 me_id, pipe_id, queue_id; 5974 struct amdgpu_ring *ring; 5975 int i; 5976 5977 me_id = (entry->ring_id & 0x0c) >> 2; 5978 pipe_id = (entry->ring_id & 0x03) >> 0; 5979 queue_id = (entry->ring_id & 0x70) >> 4; 5980 5981 switch (me_id) { 5982 case 0: 5983 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5984 ring = &adev->gfx.gfx_ring[i]; 5985 /* we only enabled 1 gfx queue per pipe for now */ 5986 if (ring->me == me_id && ring->pipe == pipe_id) 5987 drm_sched_fault(&ring->sched); 5988 } 5989 break; 5990 case 1: 5991 case 2: 5992 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5993 ring = &adev->gfx.compute_ring[i]; 5994 if (ring->me == me_id && ring->pipe == pipe_id && 5995 ring->queue == queue_id) 5996 drm_sched_fault(&ring->sched); 5997 } 5998 break; 5999 default: 6000 BUG(); 6001 break; 6002 } 6003 } 6004 6005 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6006 struct amdgpu_irq_src *source, 6007 struct amdgpu_iv_entry *entry) 6008 { 6009 DRM_ERROR("Illegal register access in command stream\n"); 6010 gfx_v11_0_handle_priv_fault(adev, entry); 6011 return 0; 6012 } 6013 6014 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6015 struct amdgpu_irq_src *source, 6016 struct amdgpu_iv_entry *entry) 6017 { 6018 DRM_ERROR("Illegal instruction in command stream\n"); 6019 gfx_v11_0_handle_priv_fault(adev, entry); 6020 return 0; 6021 } 6022 6023 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6024 struct amdgpu_irq_src *source, 6025 struct amdgpu_iv_entry *entry) 6026 { 6027 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6028 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6029 6030 return 0; 6031 } 6032 6033 #if 0 6034 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6035 struct amdgpu_irq_src *src, 6036 unsigned int type, 6037 enum amdgpu_interrupt_state state) 6038 { 6039 uint32_t tmp, target; 6040 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 6041 6042 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6043 target += ring->pipe; 6044 6045 switch (type) { 6046 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6047 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6048 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6049 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6050 GENERIC2_INT_ENABLE, 0); 6051 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6052 6053 tmp = RREG32_SOC15_IP(GC, target); 6054 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6055 GENERIC2_INT_ENABLE, 0); 6056 WREG32_SOC15_IP(GC, target, tmp); 6057 } else { 6058 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6059 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6060 GENERIC2_INT_ENABLE, 1); 6061 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6062 6063 tmp = RREG32_SOC15_IP(GC, target); 6064 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6065 GENERIC2_INT_ENABLE, 1); 6066 WREG32_SOC15_IP(GC, target, tmp); 6067 } 6068 break; 6069 default: 6070 BUG(); /* kiq only support GENERIC2_INT now */ 6071 break; 6072 } 6073 return 0; 6074 } 6075 #endif 6076 6077 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6078 { 6079 const unsigned int gcr_cntl = 6080 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6081 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6082 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6083 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6084 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6085 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6086 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6087 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6088 6089 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6090 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6091 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6092 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6093 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6094 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6095 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6096 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6097 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6098 } 6099 6100 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6101 .name = "gfx_v11_0", 6102 .early_init = gfx_v11_0_early_init, 6103 .late_init = gfx_v11_0_late_init, 6104 .sw_init = gfx_v11_0_sw_init, 6105 .sw_fini = gfx_v11_0_sw_fini, 6106 .hw_init = gfx_v11_0_hw_init, 6107 .hw_fini = gfx_v11_0_hw_fini, 6108 .suspend = gfx_v11_0_suspend, 6109 .resume = gfx_v11_0_resume, 6110 .is_idle = gfx_v11_0_is_idle, 6111 .wait_for_idle = gfx_v11_0_wait_for_idle, 6112 .soft_reset = gfx_v11_0_soft_reset, 6113 .check_soft_reset = gfx_v11_0_check_soft_reset, 6114 .post_soft_reset = gfx_v11_0_post_soft_reset, 6115 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6116 .set_powergating_state = gfx_v11_0_set_powergating_state, 6117 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6118 }; 6119 6120 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6121 .type = AMDGPU_RING_TYPE_GFX, 6122 .align_mask = 0xff, 6123 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6124 .support_64bit_ptrs = true, 6125 .secure_submission_supported = true, 6126 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6127 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6128 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6129 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6130 5 + /* COND_EXEC */ 6131 9 + /* SET_Q_PREEMPTION_MODE */ 6132 7 + /* PIPELINE_SYNC */ 6133 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6134 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6135 2 + /* VM_FLUSH */ 6136 8 + /* FENCE for VM_FLUSH */ 6137 20 + /* GDS switch */ 6138 5 + /* COND_EXEC */ 6139 7 + /* HDP_flush */ 6140 4 + /* VGT_flush */ 6141 31 + /* DE_META */ 6142 3 + /* CNTX_CTRL */ 6143 5 + /* HDP_INVL */ 6144 8 + 8 + /* FENCE x2 */ 6145 8, /* gfx_v11_0_emit_mem_sync */ 6146 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6147 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6148 .emit_fence = gfx_v11_0_ring_emit_fence, 6149 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6150 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6151 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6152 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6153 .test_ring = gfx_v11_0_ring_test_ring, 6154 .test_ib = gfx_v11_0_ring_test_ib, 6155 .insert_nop = amdgpu_ring_insert_nop, 6156 .pad_ib = amdgpu_ring_generic_pad_ib, 6157 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6158 .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow, 6159 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6160 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6161 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6162 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6163 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6164 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6165 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6166 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6167 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6168 }; 6169 6170 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6171 .type = AMDGPU_RING_TYPE_COMPUTE, 6172 .align_mask = 0xff, 6173 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6174 .support_64bit_ptrs = true, 6175 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6176 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6177 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6178 .emit_frame_size = 6179 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6180 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6181 5 + /* hdp invalidate */ 6182 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6183 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6184 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6185 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6186 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6187 8, /* gfx_v11_0_emit_mem_sync */ 6188 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6189 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6190 .emit_fence = gfx_v11_0_ring_emit_fence, 6191 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6192 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6193 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6194 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6195 .test_ring = gfx_v11_0_ring_test_ring, 6196 .test_ib = gfx_v11_0_ring_test_ib, 6197 .insert_nop = amdgpu_ring_insert_nop, 6198 .pad_ib = amdgpu_ring_generic_pad_ib, 6199 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6200 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6201 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6202 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6203 }; 6204 6205 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6206 .type = AMDGPU_RING_TYPE_KIQ, 6207 .align_mask = 0xff, 6208 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6209 .support_64bit_ptrs = true, 6210 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6211 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6212 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6213 .emit_frame_size = 6214 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6215 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6216 5 + /*hdp invalidate */ 6217 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6218 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6219 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6220 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6221 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6222 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6223 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6224 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6225 .test_ring = gfx_v11_0_ring_test_ring, 6226 .test_ib = gfx_v11_0_ring_test_ib, 6227 .insert_nop = amdgpu_ring_insert_nop, 6228 .pad_ib = amdgpu_ring_generic_pad_ib, 6229 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6230 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6231 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6232 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6233 }; 6234 6235 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6236 { 6237 int i; 6238 6239 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6240 6241 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6242 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6243 6244 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6245 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6246 } 6247 6248 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6249 .set = gfx_v11_0_set_eop_interrupt_state, 6250 .process = gfx_v11_0_eop_irq, 6251 }; 6252 6253 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6254 .set = gfx_v11_0_set_priv_reg_fault_state, 6255 .process = gfx_v11_0_priv_reg_irq, 6256 }; 6257 6258 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6259 .set = gfx_v11_0_set_priv_inst_fault_state, 6260 .process = gfx_v11_0_priv_inst_irq, 6261 }; 6262 6263 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 6264 .process = gfx_v11_0_rlc_gc_fed_irq, 6265 }; 6266 6267 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6268 { 6269 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6270 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6271 6272 adev->gfx.priv_reg_irq.num_types = 1; 6273 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6274 6275 adev->gfx.priv_inst_irq.num_types = 1; 6276 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6277 6278 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 6279 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 6280 6281 } 6282 6283 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6284 { 6285 if (adev->flags & AMD_IS_APU) 6286 adev->gfx.imu.mode = MISSION_MODE; 6287 else 6288 adev->gfx.imu.mode = DEBUG_MODE; 6289 6290 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6291 } 6292 6293 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6294 { 6295 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6296 } 6297 6298 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6299 { 6300 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6301 adev->gfx.config.max_sh_per_se * 6302 adev->gfx.config.max_shader_engines; 6303 6304 adev->gds.gds_size = 0x1000; 6305 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6306 adev->gds.gws_size = 64; 6307 adev->gds.oa_size = 16; 6308 } 6309 6310 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6311 { 6312 /* set gfx eng mqd */ 6313 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6314 sizeof(struct v11_gfx_mqd); 6315 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6316 gfx_v11_0_gfx_mqd_init; 6317 /* set compute eng mqd */ 6318 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6319 sizeof(struct v11_compute_mqd); 6320 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6321 gfx_v11_0_compute_mqd_init; 6322 } 6323 6324 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6325 u32 bitmap) 6326 { 6327 u32 data; 6328 6329 if (!bitmap) 6330 return; 6331 6332 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6333 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6334 6335 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6336 } 6337 6338 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6339 { 6340 u32 data, wgp_bitmask; 6341 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6342 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6343 6344 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6345 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6346 6347 wgp_bitmask = 6348 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6349 6350 return (~data) & wgp_bitmask; 6351 } 6352 6353 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6354 { 6355 u32 wgp_idx, wgp_active_bitmap; 6356 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6357 6358 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6359 cu_active_bitmap = 0; 6360 6361 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6362 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6363 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6364 if (wgp_active_bitmap & (1 << wgp_idx)) 6365 cu_active_bitmap |= cu_bitmap_per_wgp; 6366 } 6367 6368 return cu_active_bitmap; 6369 } 6370 6371 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6372 struct amdgpu_cu_info *cu_info) 6373 { 6374 int i, j, k, counter, active_cu_number = 0; 6375 u32 mask, bitmap; 6376 unsigned disable_masks[8 * 2]; 6377 6378 if (!adev || !cu_info) 6379 return -EINVAL; 6380 6381 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6382 6383 mutex_lock(&adev->grbm_idx_mutex); 6384 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6385 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6386 mask = 1; 6387 counter = 0; 6388 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 6389 if (i < 8 && j < 2) 6390 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6391 adev, disable_masks[i * 2 + j]); 6392 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6393 6394 /** 6395 * GFX11 could support more than 4 SEs, while the bitmap 6396 * in cu_info struct is 4x4 and ioctl interface struct 6397 * drm_amdgpu_info_device should keep stable. 6398 * So we use last two columns of bitmap to store cu mask for 6399 * SEs 4 to 7, the layout of the bitmap is as below: 6400 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6401 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6402 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6403 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6404 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6405 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6406 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6407 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6408 */ 6409 cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; 6410 6411 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6412 if (bitmap & mask) 6413 counter++; 6414 6415 mask <<= 1; 6416 } 6417 active_cu_number += counter; 6418 } 6419 } 6420 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6421 mutex_unlock(&adev->grbm_idx_mutex); 6422 6423 cu_info->number = active_cu_number; 6424 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6425 6426 return 0; 6427 } 6428 6429 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6430 { 6431 .type = AMD_IP_BLOCK_TYPE_GFX, 6432 .major = 11, 6433 .minor = 0, 6434 .rev = 0, 6435 .funcs = &gfx_v11_0_ip_funcs, 6436 }; 6437