1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 52 #define GFX11_NUM_GFX_RINGS 1 53 #define GFX11_MEC_HPD_SIZE 2048 54 55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 56 57 #define regCGTT_WD_CLK_CTRL 0x5086 58 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 59 60 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 73 74 static const struct soc15_reg_golden golden_settings_gc_11_0[] = 75 { 76 /* Pending on emulation bring up */ 77 }; 78 79 static const struct soc15_reg_golden golden_settings_gc_11_0_0[] = 80 { 81 /* Pending on emulation bring up */ 82 }; 83 84 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_11_0[] = 85 { 86 /* Pending on emulation bring up */ 87 }; 88 89 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 90 { 91 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 100 }; 101 102 #define DEFAULT_SH_MEM_CONFIG \ 103 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 104 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 105 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 106 107 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 108 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 109 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 110 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 111 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 112 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 113 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 114 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 115 struct amdgpu_cu_info *cu_info); 116 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 117 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 118 u32 sh_num, u32 instance); 119 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 120 121 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 122 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 123 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 124 uint32_t val); 125 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 126 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 127 uint16_t pasid, uint32_t flush_type, 128 bool all_hub, uint8_t dst_sel); 129 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev); 130 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev); 131 132 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 133 { 134 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 135 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 136 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 137 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 138 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 139 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 140 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 141 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 142 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 143 } 144 145 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 146 struct amdgpu_ring *ring) 147 { 148 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 149 uint64_t wptr_addr = ring->wptr_gpu_addr; 150 uint32_t me = 0, eng_sel = 0; 151 152 switch (ring->funcs->type) { 153 case AMDGPU_RING_TYPE_COMPUTE: 154 me = 1; 155 eng_sel = 0; 156 break; 157 case AMDGPU_RING_TYPE_GFX: 158 me = 0; 159 eng_sel = 4; 160 break; 161 case AMDGPU_RING_TYPE_MES: 162 me = 2; 163 eng_sel = 5; 164 break; 165 default: 166 WARN_ON(1); 167 } 168 169 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 170 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 171 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 172 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 173 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 174 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 175 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 176 PACKET3_MAP_QUEUES_ME((me)) | 177 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 178 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 179 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 180 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 181 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 182 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 183 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 184 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 185 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 186 } 187 188 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 189 struct amdgpu_ring *ring, 190 enum amdgpu_unmap_queues_action action, 191 u64 gpu_addr, u64 seq) 192 { 193 struct amdgpu_device *adev = kiq_ring->adev; 194 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 195 196 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { 197 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 198 return; 199 } 200 201 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 202 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 203 PACKET3_UNMAP_QUEUES_ACTION(action) | 204 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 205 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 206 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 207 amdgpu_ring_write(kiq_ring, 208 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 209 210 if (action == PREEMPT_QUEUES_NO_UNMAP) { 211 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 212 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 213 amdgpu_ring_write(kiq_ring, seq); 214 } else { 215 amdgpu_ring_write(kiq_ring, 0); 216 amdgpu_ring_write(kiq_ring, 0); 217 amdgpu_ring_write(kiq_ring, 0); 218 } 219 } 220 221 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 222 struct amdgpu_ring *ring, 223 u64 addr, 224 u64 seq) 225 { 226 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 227 228 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 229 amdgpu_ring_write(kiq_ring, 230 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 231 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 232 PACKET3_QUERY_STATUS_COMMAND(2)); 233 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 234 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 235 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 236 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 237 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 238 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 239 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 240 } 241 242 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 243 uint16_t pasid, uint32_t flush_type, 244 bool all_hub) 245 { 246 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 247 } 248 249 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 250 .kiq_set_resources = gfx11_kiq_set_resources, 251 .kiq_map_queues = gfx11_kiq_map_queues, 252 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 253 .kiq_query_status = gfx11_kiq_query_status, 254 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 255 .set_resources_size = 8, 256 .map_queues_size = 7, 257 .unmap_queues_size = 6, 258 .query_status_size = 7, 259 .invalidate_tlbs_size = 2, 260 }; 261 262 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 263 { 264 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; 265 } 266 267 static void gfx_v11_0_init_spm_golden_registers(struct amdgpu_device *adev) 268 { 269 switch (adev->ip_versions[GC_HWIP][0]) { 270 case IP_VERSION(11, 0, 0): 271 soc15_program_register_sequence(adev, 272 golden_settings_gc_rlc_spm_11_0, 273 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_11_0)); 274 break; 275 default: 276 break; 277 } 278 } 279 280 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 281 { 282 switch (adev->ip_versions[GC_HWIP][0]) { 283 case IP_VERSION(11, 0, 0): 284 soc15_program_register_sequence(adev, 285 golden_settings_gc_11_0, 286 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 287 soc15_program_register_sequence(adev, 288 golden_settings_gc_11_0_0, 289 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_0)); 290 break; 291 case IP_VERSION(11, 0, 1): 292 soc15_program_register_sequence(adev, 293 golden_settings_gc_11_0, 294 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 295 soc15_program_register_sequence(adev, 296 golden_settings_gc_11_0_1, 297 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 298 break; 299 default: 300 break; 301 } 302 gfx_v11_0_init_spm_golden_registers(adev); 303 } 304 305 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 306 bool wc, uint32_t reg, uint32_t val) 307 { 308 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 309 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 310 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 311 amdgpu_ring_write(ring, reg); 312 amdgpu_ring_write(ring, 0); 313 amdgpu_ring_write(ring, val); 314 } 315 316 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 317 int mem_space, int opt, uint32_t addr0, 318 uint32_t addr1, uint32_t ref, uint32_t mask, 319 uint32_t inv) 320 { 321 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 322 amdgpu_ring_write(ring, 323 /* memory (1) or register (0) */ 324 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 325 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 326 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 327 WAIT_REG_MEM_ENGINE(eng_sel))); 328 329 if (mem_space) 330 BUG_ON(addr0 & 0x3); /* Dword align */ 331 amdgpu_ring_write(ring, addr0); 332 amdgpu_ring_write(ring, addr1); 333 amdgpu_ring_write(ring, ref); 334 amdgpu_ring_write(ring, mask); 335 amdgpu_ring_write(ring, inv); /* poll interval */ 336 } 337 338 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 339 { 340 struct amdgpu_device *adev = ring->adev; 341 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 342 uint32_t tmp = 0; 343 unsigned i; 344 int r; 345 346 WREG32(scratch, 0xCAFEDEAD); 347 r = amdgpu_ring_alloc(ring, 5); 348 if (r) { 349 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 350 ring->idx, r); 351 return r; 352 } 353 354 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 355 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 356 } else { 357 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 358 amdgpu_ring_write(ring, scratch - 359 PACKET3_SET_UCONFIG_REG_START); 360 amdgpu_ring_write(ring, 0xDEADBEEF); 361 } 362 amdgpu_ring_commit(ring); 363 364 for (i = 0; i < adev->usec_timeout; i++) { 365 tmp = RREG32(scratch); 366 if (tmp == 0xDEADBEEF) 367 break; 368 if (amdgpu_emu_mode == 1) 369 msleep(1); 370 else 371 udelay(1); 372 } 373 374 if (i >= adev->usec_timeout) 375 r = -ETIMEDOUT; 376 return r; 377 } 378 379 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 380 { 381 struct amdgpu_device *adev = ring->adev; 382 struct amdgpu_ib ib; 383 struct dma_fence *f = NULL; 384 unsigned index; 385 uint64_t gpu_addr; 386 volatile uint32_t *cpu_ptr; 387 long r; 388 389 /* MES KIQ fw hasn't indirect buffer support for now */ 390 if (adev->enable_mes_kiq && 391 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 392 return 0; 393 394 memset(&ib, 0, sizeof(ib)); 395 396 if (ring->is_mes_queue) { 397 uint32_t padding, offset; 398 399 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 400 padding = amdgpu_mes_ctx_get_offs(ring, 401 AMDGPU_MES_CTX_PADDING_OFFS); 402 403 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 404 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 405 406 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 407 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 408 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 409 } else { 410 r = amdgpu_device_wb_get(adev, &index); 411 if (r) 412 return r; 413 414 gpu_addr = adev->wb.gpu_addr + (index * 4); 415 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 416 cpu_ptr = &adev->wb.wb[index]; 417 418 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 419 if (r) { 420 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 421 goto err1; 422 } 423 } 424 425 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 426 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 427 ib.ptr[2] = lower_32_bits(gpu_addr); 428 ib.ptr[3] = upper_32_bits(gpu_addr); 429 ib.ptr[4] = 0xDEADBEEF; 430 ib.length_dw = 5; 431 432 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 433 if (r) 434 goto err2; 435 436 r = dma_fence_wait_timeout(f, false, timeout); 437 if (r == 0) { 438 r = -ETIMEDOUT; 439 goto err2; 440 } else if (r < 0) { 441 goto err2; 442 } 443 444 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 445 r = 0; 446 else 447 r = -EINVAL; 448 err2: 449 if (!ring->is_mes_queue) 450 amdgpu_ib_free(adev, &ib, NULL); 451 dma_fence_put(f); 452 err1: 453 if (!ring->is_mes_queue) 454 amdgpu_device_wb_free(adev, index); 455 return r; 456 } 457 458 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 459 { 460 release_firmware(adev->gfx.pfp_fw); 461 adev->gfx.pfp_fw = NULL; 462 release_firmware(adev->gfx.me_fw); 463 adev->gfx.me_fw = NULL; 464 release_firmware(adev->gfx.rlc_fw); 465 adev->gfx.rlc_fw = NULL; 466 release_firmware(adev->gfx.mec_fw); 467 adev->gfx.mec_fw = NULL; 468 469 kfree(adev->gfx.rlc.register_list_format); 470 } 471 472 static void gfx_v11_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 473 { 474 const struct rlc_firmware_header_v2_1 *rlc_hdr; 475 476 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 477 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 478 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 479 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 480 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 481 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 482 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 483 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 484 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 485 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 486 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 487 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 488 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 489 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 490 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 491 } 492 493 static void gfx_v11_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 494 { 495 const struct rlc_firmware_header_v2_2 *rlc_hdr; 496 497 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 498 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 499 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 500 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 501 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 502 } 503 504 static void gfx_v11_0_init_rlcp_rlcv_microcode(struct amdgpu_device *adev) 505 { 506 const struct rlc_firmware_header_v2_3 *rlc_hdr; 507 508 rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 509 adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes); 510 adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); 511 adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes); 512 adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); 513 } 514 515 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 516 { 517 char fw_name[40]; 518 char ucode_prefix[30]; 519 int err; 520 struct amdgpu_firmware_info *info = NULL; 521 const struct common_firmware_header *header = NULL; 522 const struct gfx_firmware_header_v1_0 *cp_hdr; 523 const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0; 524 const struct rlc_firmware_header_v2_0 *rlc_hdr; 525 unsigned int *tmp = NULL; 526 unsigned int i = 0; 527 uint16_t version_major; 528 uint16_t version_minor; 529 530 DRM_DEBUG("\n"); 531 532 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 533 534 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 535 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 536 if (err) 537 goto out; 538 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 539 if (err) 540 goto out; 541 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 542 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 543 (union amdgpu_firmware_header *) 544 adev->gfx.pfp_fw->data, 2, 0); 545 if (adev->gfx.rs64_enable) { 546 dev_info(adev->dev, "CP RS64 enable\n"); 547 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; 548 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 549 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 550 551 } else { 552 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 553 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 554 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 555 } 556 557 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 558 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 559 if (err) 560 goto out; 561 err = amdgpu_ucode_validate(adev->gfx.me_fw); 562 if (err) 563 goto out; 564 if (adev->gfx.rs64_enable) { 565 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; 566 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 567 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 568 569 } else { 570 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 571 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 572 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 573 } 574 575 if (!amdgpu_sriov_vf(adev)) { 576 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 577 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 578 if (err) 579 goto out; 580 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 581 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 582 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 583 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 584 585 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 586 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 587 adev->gfx.rlc.save_and_restore_offset = 588 le32_to_cpu(rlc_hdr->save_and_restore_offset); 589 adev->gfx.rlc.clear_state_descriptor_offset = 590 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 591 adev->gfx.rlc.avail_scratch_ram_locations = 592 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 593 adev->gfx.rlc.reg_restore_list_size = 594 le32_to_cpu(rlc_hdr->reg_restore_list_size); 595 adev->gfx.rlc.reg_list_format_start = 596 le32_to_cpu(rlc_hdr->reg_list_format_start); 597 adev->gfx.rlc.reg_list_format_separate_start = 598 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 599 adev->gfx.rlc.starting_offsets_start = 600 le32_to_cpu(rlc_hdr->starting_offsets_start); 601 adev->gfx.rlc.reg_list_format_size_bytes = 602 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 603 adev->gfx.rlc.reg_list_size_bytes = 604 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 605 adev->gfx.rlc.register_list_format = 606 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 607 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 608 if (!adev->gfx.rlc.register_list_format) { 609 err = -ENOMEM; 610 goto out; 611 } 612 613 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 614 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 615 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 616 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 617 618 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 619 620 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 621 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 622 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 623 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 624 625 if (version_major == 2) { 626 if (version_minor >= 1) 627 gfx_v11_0_init_rlc_ext_microcode(adev); 628 if (version_minor >= 2) 629 gfx_v11_0_init_rlc_iram_dram_microcode(adev); 630 if (version_minor == 3) 631 gfx_v11_0_init_rlcp_rlcv_microcode(adev); 632 } 633 } 634 635 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 636 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 637 if (err) 638 goto out; 639 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 640 if (err) 641 goto out; 642 if (adev->gfx.rs64_enable) { 643 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 644 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 645 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 646 647 } else { 648 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 649 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 650 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 651 } 652 653 /* only one MEC for gfx 11.0.0. */ 654 adev->gfx.mec2_fw = NULL; 655 656 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 657 if (adev->gfx.rs64_enable) { 658 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; 659 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP]; 660 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP; 661 info->fw = adev->gfx.pfp_fw; 662 header = (const struct common_firmware_header *)info->fw->data; 663 adev->firmware.fw_size += 664 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 665 666 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK]; 667 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK; 668 info->fw = adev->gfx.pfp_fw; 669 header = (const struct common_firmware_header *)info->fw->data; 670 adev->firmware.fw_size += 671 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 672 673 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK]; 674 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK; 675 info->fw = adev->gfx.pfp_fw; 676 header = (const struct common_firmware_header *)info->fw->data; 677 adev->firmware.fw_size += 678 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 679 680 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; 681 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME]; 682 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME; 683 info->fw = adev->gfx.me_fw; 684 header = (const struct common_firmware_header *)info->fw->data; 685 adev->firmware.fw_size += 686 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 687 688 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK]; 689 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK; 690 info->fw = adev->gfx.me_fw; 691 header = (const struct common_firmware_header *)info->fw->data; 692 adev->firmware.fw_size += 693 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 694 695 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK]; 696 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK; 697 info->fw = adev->gfx.me_fw; 698 header = (const struct common_firmware_header *)info->fw->data; 699 adev->firmware.fw_size += 700 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 701 702 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 703 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC]; 704 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC; 705 info->fw = adev->gfx.mec_fw; 706 header = (const struct common_firmware_header *)info->fw->data; 707 adev->firmware.fw_size += 708 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 709 710 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK]; 711 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK; 712 info->fw = adev->gfx.mec_fw; 713 header = (const struct common_firmware_header *)info->fw->data; 714 adev->firmware.fw_size += 715 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 716 717 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK]; 718 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK; 719 info->fw = adev->gfx.mec_fw; 720 header = (const struct common_firmware_header *)info->fw->data; 721 adev->firmware.fw_size += 722 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 723 724 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK]; 725 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK; 726 info->fw = adev->gfx.mec_fw; 727 header = (const struct common_firmware_header *)info->fw->data; 728 adev->firmware.fw_size += 729 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 730 731 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK]; 732 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK; 733 info->fw = adev->gfx.mec_fw; 734 header = (const struct common_firmware_header *)info->fw->data; 735 adev->firmware.fw_size += 736 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 737 } else { 738 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 739 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 740 info->fw = adev->gfx.pfp_fw; 741 header = (const struct common_firmware_header *)info->fw->data; 742 adev->firmware.fw_size += 743 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 744 745 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 746 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 747 info->fw = adev->gfx.me_fw; 748 header = (const struct common_firmware_header *)info->fw->data; 749 adev->firmware.fw_size += 750 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 751 752 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 753 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 754 info->fw = adev->gfx.mec_fw; 755 header = (const struct common_firmware_header *)info->fw->data; 756 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 757 adev->firmware.fw_size += 758 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 759 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 760 761 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 762 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 763 info->fw = adev->gfx.mec_fw; 764 adev->firmware.fw_size += 765 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 766 } 767 768 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 769 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 770 info->fw = adev->gfx.rlc_fw; 771 if (info->fw) { 772 header = (const struct common_firmware_header *)info->fw->data; 773 adev->firmware.fw_size += 774 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 775 } 776 if (adev->gfx.rlc.save_restore_list_gpm_size_bytes && 777 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 778 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 779 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 780 info->fw = adev->gfx.rlc_fw; 781 adev->firmware.fw_size += 782 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 783 784 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 785 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 786 info->fw = adev->gfx.rlc_fw; 787 adev->firmware.fw_size += 788 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 789 } 790 791 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 792 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 793 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 794 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 795 info->fw = adev->gfx.rlc_fw; 796 adev->firmware.fw_size += 797 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 798 799 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 800 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 801 info->fw = adev->gfx.rlc_fw; 802 adev->firmware.fw_size += 803 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 804 } 805 806 if (adev->gfx.rlc.rlcp_ucode_size_bytes) { 807 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; 808 info->ucode_id = AMDGPU_UCODE_ID_RLC_P; 809 info->fw = adev->gfx.rlc_fw; 810 adev->firmware.fw_size += 811 ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE); 812 } 813 814 if (adev->gfx.rlc.rlcv_ucode_size_bytes) { 815 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; 816 info->ucode_id = AMDGPU_UCODE_ID_RLC_V; 817 info->fw = adev->gfx.rlc_fw; 818 adev->firmware.fw_size += 819 ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE); 820 } 821 } 822 823 out: 824 if (err) { 825 dev_err(adev->dev, 826 "gfx11: Failed to load firmware \"%s\"\n", 827 fw_name); 828 release_firmware(adev->gfx.pfp_fw); 829 adev->gfx.pfp_fw = NULL; 830 release_firmware(adev->gfx.me_fw); 831 adev->gfx.me_fw = NULL; 832 release_firmware(adev->gfx.rlc_fw); 833 adev->gfx.rlc_fw = NULL; 834 release_firmware(adev->gfx.mec_fw); 835 adev->gfx.mec_fw = NULL; 836 } 837 838 return err; 839 } 840 841 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) 842 { 843 const struct psp_firmware_header_v1_0 *toc_hdr; 844 int err = 0; 845 char fw_name[40]; 846 char ucode_prefix[30]; 847 848 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 849 850 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 851 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 852 if (err) 853 goto out; 854 855 err = amdgpu_ucode_validate(adev->psp.toc_fw); 856 if (err) 857 goto out; 858 859 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 860 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 861 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 862 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 863 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 864 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 865 return 0; 866 out: 867 dev_err(adev->dev, "Failed to load TOC microcode\n"); 868 release_firmware(adev->psp.toc_fw); 869 adev->psp.toc_fw = NULL; 870 return err; 871 } 872 873 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 874 { 875 u32 count = 0; 876 const struct cs_section_def *sect = NULL; 877 const struct cs_extent_def *ext = NULL; 878 879 /* begin clear state */ 880 count += 2; 881 /* context control state */ 882 count += 3; 883 884 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 885 for (ext = sect->section; ext->extent != NULL; ++ext) { 886 if (sect->id == SECT_CONTEXT) 887 count += 2 + ext->reg_count; 888 else 889 return 0; 890 } 891 } 892 893 /* set PA_SC_TILE_STEERING_OVERRIDE */ 894 count += 3; 895 /* end clear state */ 896 count += 2; 897 /* clear state */ 898 count += 2; 899 900 return count; 901 } 902 903 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 904 volatile u32 *buffer) 905 { 906 u32 count = 0, i; 907 const struct cs_section_def *sect = NULL; 908 const struct cs_extent_def *ext = NULL; 909 int ctx_reg_offset; 910 911 if (adev->gfx.rlc.cs_data == NULL) 912 return; 913 if (buffer == NULL) 914 return; 915 916 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 917 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 918 919 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 920 buffer[count++] = cpu_to_le32(0x80000000); 921 buffer[count++] = cpu_to_le32(0x80000000); 922 923 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 924 for (ext = sect->section; ext->extent != NULL; ++ext) { 925 if (sect->id == SECT_CONTEXT) { 926 buffer[count++] = 927 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 928 buffer[count++] = cpu_to_le32(ext->reg_index - 929 PACKET3_SET_CONTEXT_REG_START); 930 for (i = 0; i < ext->reg_count; i++) 931 buffer[count++] = cpu_to_le32(ext->extent[i]); 932 } else { 933 return; 934 } 935 } 936 } 937 938 ctx_reg_offset = 939 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 940 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 941 buffer[count++] = cpu_to_le32(ctx_reg_offset); 942 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 943 944 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 945 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 946 947 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 948 buffer[count++] = cpu_to_le32(0); 949 } 950 951 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 952 { 953 /* clear state block */ 954 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 955 &adev->gfx.rlc.clear_state_gpu_addr, 956 (void **)&adev->gfx.rlc.cs_ptr); 957 958 /* jump table block */ 959 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 960 &adev->gfx.rlc.cp_table_gpu_addr, 961 (void **)&adev->gfx.rlc.cp_table_ptr); 962 } 963 964 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 965 { 966 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 967 968 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 969 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 970 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 971 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 972 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 973 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 974 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 975 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 976 adev->gfx.rlc.rlcg_reg_access_supported = true; 977 } 978 979 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 980 { 981 const struct cs_section_def *cs_data; 982 int r; 983 984 adev->gfx.rlc.cs_data = gfx11_cs_data; 985 986 cs_data = adev->gfx.rlc.cs_data; 987 988 if (cs_data) { 989 /* init clear state block */ 990 r = amdgpu_gfx_rlc_init_csb(adev); 991 if (r) 992 return r; 993 } 994 995 /* init spm vmid with 0xf */ 996 if (adev->gfx.rlc.funcs->update_spm_vmid) 997 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 998 999 return 0; 1000 } 1001 1002 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 1003 { 1004 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1005 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1006 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 1007 } 1008 1009 static int gfx_v11_0_me_init(struct amdgpu_device *adev) 1010 { 1011 int r; 1012 1013 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 1014 1015 amdgpu_gfx_graphics_queue_acquire(adev); 1016 1017 r = gfx_v11_0_init_microcode(adev); 1018 if (r) 1019 DRM_ERROR("Failed to load gfx firmware!\n"); 1020 1021 return r; 1022 } 1023 1024 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 1025 { 1026 int r; 1027 u32 *hpd; 1028 size_t mec_hpd_size; 1029 1030 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1031 1032 /* take ownership of the relevant compute queues */ 1033 amdgpu_gfx_compute_queue_acquire(adev); 1034 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 1035 1036 if (mec_hpd_size) { 1037 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1038 AMDGPU_GEM_DOMAIN_GTT, 1039 &adev->gfx.mec.hpd_eop_obj, 1040 &adev->gfx.mec.hpd_eop_gpu_addr, 1041 (void **)&hpd); 1042 if (r) { 1043 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1044 gfx_v11_0_mec_fini(adev); 1045 return r; 1046 } 1047 1048 memset(hpd, 0, mec_hpd_size); 1049 1050 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1051 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1052 } 1053 1054 return 0; 1055 } 1056 1057 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1058 { 1059 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1060 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1061 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1062 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1063 } 1064 1065 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1066 uint32_t thread, uint32_t regno, 1067 uint32_t num, uint32_t *out) 1068 { 1069 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1070 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1071 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1072 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1073 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1074 while (num--) 1075 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1076 } 1077 1078 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1079 { 1080 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 1081 * field when performing a select_se_sh so it should be 1082 * zero here */ 1083 WARN_ON(simd != 0); 1084 1085 /* type 2 wave data */ 1086 dst[(*no_fields)++] = 2; 1087 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1088 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1089 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1090 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1091 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1092 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1093 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1094 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1095 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1096 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1097 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1098 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1099 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1100 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1101 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 1102 } 1103 1104 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1105 uint32_t wave, uint32_t start, 1106 uint32_t size, uint32_t *dst) 1107 { 1108 WARN_ON(simd != 0); 1109 1110 wave_read_regs( 1111 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1112 dst); 1113 } 1114 1115 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1116 uint32_t wave, uint32_t thread, 1117 uint32_t start, uint32_t size, 1118 uint32_t *dst) 1119 { 1120 wave_read_regs( 1121 adev, wave, thread, 1122 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1123 } 1124 1125 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1126 u32 me, u32 pipe, u32 q, u32 vm) 1127 { 1128 soc21_grbm_select(adev, me, pipe, q, vm); 1129 } 1130 1131 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1132 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1133 .select_se_sh = &gfx_v11_0_select_se_sh, 1134 .read_wave_data = &gfx_v11_0_read_wave_data, 1135 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1136 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1137 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1138 .init_spm_golden = &gfx_v11_0_init_spm_golden_registers, 1139 }; 1140 1141 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1142 { 1143 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 1144 1145 switch (adev->ip_versions[GC_HWIP][0]) { 1146 case IP_VERSION(11, 0, 0): 1147 case IP_VERSION(11, 0, 2): 1148 adev->gfx.config.max_hw_contexts = 8; 1149 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1150 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1151 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1152 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1153 break; 1154 case IP_VERSION(11, 0, 1): 1155 adev->gfx.config.max_hw_contexts = 8; 1156 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1157 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1158 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1159 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 1160 break; 1161 default: 1162 BUG(); 1163 break; 1164 } 1165 1166 return 0; 1167 } 1168 1169 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1170 int me, int pipe, int queue) 1171 { 1172 int r; 1173 struct amdgpu_ring *ring; 1174 unsigned int irq_type; 1175 1176 ring = &adev->gfx.gfx_ring[ring_id]; 1177 1178 ring->me = me; 1179 ring->pipe = pipe; 1180 ring->queue = queue; 1181 1182 ring->ring_obj = NULL; 1183 ring->use_doorbell = true; 1184 1185 if (!ring_id) 1186 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1187 else 1188 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1189 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1190 1191 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1192 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1193 AMDGPU_RING_PRIO_DEFAULT, NULL); 1194 if (r) 1195 return r; 1196 return 0; 1197 } 1198 1199 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1200 int mec, int pipe, int queue) 1201 { 1202 int r; 1203 unsigned irq_type; 1204 struct amdgpu_ring *ring; 1205 unsigned int hw_prio; 1206 1207 ring = &adev->gfx.compute_ring[ring_id]; 1208 1209 /* mec0 is me1 */ 1210 ring->me = mec + 1; 1211 ring->pipe = pipe; 1212 ring->queue = queue; 1213 1214 ring->ring_obj = NULL; 1215 ring->use_doorbell = true; 1216 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1217 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1218 + (ring_id * GFX11_MEC_HPD_SIZE); 1219 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1220 1221 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1222 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1223 + ring->pipe; 1224 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1225 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1226 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1227 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1228 hw_prio, NULL); 1229 if (r) 1230 return r; 1231 1232 return 0; 1233 } 1234 1235 static struct { 1236 SOC21_FIRMWARE_ID id; 1237 unsigned int offset; 1238 unsigned int size; 1239 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1240 1241 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1242 { 1243 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1244 1245 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1246 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1247 rlc_autoload_info[ucode->id].id = ucode->id; 1248 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1249 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1250 1251 ucode++; 1252 } 1253 } 1254 1255 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1256 { 1257 uint32_t total_size = 0; 1258 SOC21_FIRMWARE_ID id; 1259 1260 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1261 1262 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1263 total_size += rlc_autoload_info[id].size; 1264 1265 /* In case the offset in rlc toc ucode is aligned */ 1266 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1267 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1268 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1269 1270 return total_size; 1271 } 1272 1273 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1274 { 1275 int r; 1276 uint32_t total_size; 1277 1278 total_size = gfx_v11_0_calc_toc_total_size(adev); 1279 1280 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1281 AMDGPU_GEM_DOMAIN_VRAM, 1282 &adev->gfx.rlc.rlc_autoload_bo, 1283 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1284 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1285 1286 if (r) { 1287 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1288 return r; 1289 } 1290 1291 return 0; 1292 } 1293 1294 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1295 SOC21_FIRMWARE_ID id, 1296 const void *fw_data, 1297 uint32_t fw_size, 1298 uint32_t *fw_autoload_mask) 1299 { 1300 uint32_t toc_offset; 1301 uint32_t toc_fw_size; 1302 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1303 1304 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1305 return; 1306 1307 toc_offset = rlc_autoload_info[id].offset; 1308 toc_fw_size = rlc_autoload_info[id].size; 1309 1310 if (fw_size == 0) 1311 fw_size = toc_fw_size; 1312 1313 if (fw_size > toc_fw_size) 1314 fw_size = toc_fw_size; 1315 1316 memcpy(ptr + toc_offset, fw_data, fw_size); 1317 1318 if (fw_size < toc_fw_size) 1319 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1320 1321 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1322 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1323 } 1324 1325 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1326 uint32_t *fw_autoload_mask) 1327 { 1328 void *data; 1329 uint32_t size; 1330 uint64_t *toc_ptr; 1331 1332 *(uint64_t *)fw_autoload_mask |= 0x1; 1333 1334 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1335 1336 data = adev->psp.toc.start_addr; 1337 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1338 1339 toc_ptr = (uint64_t *)data + size / 8 - 1; 1340 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1341 1342 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1343 data, size, fw_autoload_mask); 1344 } 1345 1346 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1347 uint32_t *fw_autoload_mask) 1348 { 1349 const __le32 *fw_data; 1350 uint32_t fw_size; 1351 const struct gfx_firmware_header_v1_0 *cp_hdr; 1352 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1353 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1354 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1355 uint16_t version_major, version_minor; 1356 1357 if (adev->gfx.rs64_enable) { 1358 /* pfp ucode */ 1359 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1360 adev->gfx.pfp_fw->data; 1361 /* instruction */ 1362 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1363 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1364 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1365 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1366 fw_data, fw_size, fw_autoload_mask); 1367 /* data */ 1368 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1369 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1370 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1371 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1372 fw_data, fw_size, fw_autoload_mask); 1373 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1374 fw_data, fw_size, fw_autoload_mask); 1375 /* me ucode */ 1376 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1377 adev->gfx.me_fw->data; 1378 /* instruction */ 1379 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1380 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1381 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1382 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1383 fw_data, fw_size, fw_autoload_mask); 1384 /* data */ 1385 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1386 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1387 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1388 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1389 fw_data, fw_size, fw_autoload_mask); 1390 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1391 fw_data, fw_size, fw_autoload_mask); 1392 /* mec ucode */ 1393 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1394 adev->gfx.mec_fw->data; 1395 /* instruction */ 1396 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1397 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1398 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1399 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1400 fw_data, fw_size, fw_autoload_mask); 1401 /* data */ 1402 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1403 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1404 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1405 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1406 fw_data, fw_size, fw_autoload_mask); 1407 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1408 fw_data, fw_size, fw_autoload_mask); 1409 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1410 fw_data, fw_size, fw_autoload_mask); 1411 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1412 fw_data, fw_size, fw_autoload_mask); 1413 } else { 1414 /* pfp ucode */ 1415 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1416 adev->gfx.pfp_fw->data; 1417 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1418 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1419 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1420 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1421 fw_data, fw_size, fw_autoload_mask); 1422 1423 /* me ucode */ 1424 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1425 adev->gfx.me_fw->data; 1426 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1427 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1428 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1429 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1430 fw_data, fw_size, fw_autoload_mask); 1431 1432 /* mec ucode */ 1433 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1434 adev->gfx.mec_fw->data; 1435 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1436 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1437 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1438 cp_hdr->jt_size * 4; 1439 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1440 fw_data, fw_size, fw_autoload_mask); 1441 } 1442 1443 /* rlc ucode */ 1444 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1445 adev->gfx.rlc_fw->data; 1446 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1447 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1448 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1449 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1450 fw_data, fw_size, fw_autoload_mask); 1451 1452 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1453 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1454 if (version_major == 2) { 1455 if (version_minor >= 2) { 1456 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1457 1458 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1459 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1460 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1461 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1462 fw_data, fw_size, fw_autoload_mask); 1463 1464 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1465 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1466 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1467 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1468 fw_data, fw_size, fw_autoload_mask); 1469 } 1470 } 1471 } 1472 1473 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1474 uint32_t *fw_autoload_mask) 1475 { 1476 const __le32 *fw_data; 1477 uint32_t fw_size; 1478 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1479 1480 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1481 adev->sdma.instance[0].fw->data; 1482 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1483 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1484 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1485 1486 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1487 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1488 1489 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1490 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1491 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1492 1493 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1494 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1495 } 1496 1497 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1498 uint32_t *fw_autoload_mask) 1499 { 1500 const __le32 *fw_data; 1501 unsigned fw_size; 1502 const struct mes_firmware_header_v1_0 *mes_hdr; 1503 int pipe, ucode_id, data_id; 1504 1505 for (pipe = 0; pipe < 2; pipe++) { 1506 if (pipe==0) { 1507 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1508 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1509 } else { 1510 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1511 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1512 } 1513 1514 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1515 adev->mes.fw[pipe]->data; 1516 1517 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1518 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1519 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1520 1521 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1522 ucode_id, fw_data, fw_size, fw_autoload_mask); 1523 1524 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1525 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1526 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1527 1528 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1529 data_id, fw_data, fw_size, fw_autoload_mask); 1530 } 1531 } 1532 1533 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1534 { 1535 uint32_t rlc_g_offset, rlc_g_size; 1536 uint64_t gpu_addr; 1537 uint32_t autoload_fw_id[2]; 1538 1539 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1540 1541 /* RLC autoload sequence 2: copy ucode */ 1542 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1543 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1544 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1545 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1546 1547 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1548 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1549 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1550 1551 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1552 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1553 1554 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1555 1556 /* RLC autoload sequence 3: load IMU fw */ 1557 if (adev->gfx.imu.funcs->load_microcode) 1558 adev->gfx.imu.funcs->load_microcode(adev); 1559 /* RLC autoload sequence 4 init IMU fw */ 1560 if (adev->gfx.imu.funcs->setup_imu) 1561 adev->gfx.imu.funcs->setup_imu(adev); 1562 if (adev->gfx.imu.funcs->start_imu) 1563 adev->gfx.imu.funcs->start_imu(adev); 1564 1565 /* RLC autoload sequence 5 disable gpa mode */ 1566 gfx_v11_0_disable_gpa_mode(adev); 1567 1568 return 0; 1569 } 1570 1571 static int gfx_v11_0_sw_init(void *handle) 1572 { 1573 int i, j, k, r, ring_id = 0; 1574 struct amdgpu_kiq *kiq; 1575 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1576 1577 adev->gfxhub.funcs->init(adev); 1578 1579 switch (adev->ip_versions[GC_HWIP][0]) { 1580 case IP_VERSION(11, 0, 0): 1581 case IP_VERSION(11, 0, 1): 1582 case IP_VERSION(11, 0, 2): 1583 adev->gfx.me.num_me = 1; 1584 adev->gfx.me.num_pipe_per_me = 1; 1585 adev->gfx.me.num_queue_per_pipe = 1; 1586 adev->gfx.mec.num_mec = 2; 1587 adev->gfx.mec.num_pipe_per_mec = 4; 1588 adev->gfx.mec.num_queue_per_pipe = 4; 1589 break; 1590 default: 1591 adev->gfx.me.num_me = 1; 1592 adev->gfx.me.num_pipe_per_me = 1; 1593 adev->gfx.me.num_queue_per_pipe = 1; 1594 adev->gfx.mec.num_mec = 1; 1595 adev->gfx.mec.num_pipe_per_mec = 4; 1596 adev->gfx.mec.num_queue_per_pipe = 8; 1597 break; 1598 } 1599 1600 /* EOP Event */ 1601 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1602 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1603 &adev->gfx.eop_irq); 1604 if (r) 1605 return r; 1606 1607 /* Privileged reg */ 1608 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1609 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1610 &adev->gfx.priv_reg_irq); 1611 if (r) 1612 return r; 1613 1614 /* Privileged inst */ 1615 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1616 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1617 &adev->gfx.priv_inst_irq); 1618 if (r) 1619 return r; 1620 1621 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1622 1623 if (adev->gfx.imu.funcs) { 1624 if (adev->gfx.imu.funcs->init_microcode) { 1625 r = adev->gfx.imu.funcs->init_microcode(adev); 1626 if (r) 1627 DRM_ERROR("Failed to load imu firmware!\n"); 1628 } 1629 } 1630 1631 r = gfx_v11_0_me_init(adev); 1632 if (r) 1633 return r; 1634 1635 r = gfx_v11_0_rlc_init(adev); 1636 if (r) { 1637 DRM_ERROR("Failed to init rlc BOs!\n"); 1638 return r; 1639 } 1640 1641 r = gfx_v11_0_mec_init(adev); 1642 if (r) { 1643 DRM_ERROR("Failed to init MEC BOs!\n"); 1644 return r; 1645 } 1646 1647 /* set up the gfx ring */ 1648 for (i = 0; i < adev->gfx.me.num_me; i++) { 1649 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1650 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1651 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1652 continue; 1653 1654 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1655 i, k, j); 1656 if (r) 1657 return r; 1658 ring_id++; 1659 } 1660 } 1661 } 1662 1663 ring_id = 0; 1664 /* set up the compute queues - allocate horizontally across pipes */ 1665 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1666 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1667 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1668 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1669 j)) 1670 continue; 1671 1672 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1673 i, k, j); 1674 if (r) 1675 return r; 1676 1677 ring_id++; 1678 } 1679 } 1680 } 1681 1682 if (!adev->enable_mes_kiq) { 1683 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE); 1684 if (r) { 1685 DRM_ERROR("Failed to init KIQ BOs!\n"); 1686 return r; 1687 } 1688 1689 kiq = &adev->gfx.kiq; 1690 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1691 if (r) 1692 return r; 1693 } 1694 1695 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd)); 1696 if (r) 1697 return r; 1698 1699 /* allocate visible FB for rlc auto-loading fw */ 1700 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1701 r = gfx_v11_0_init_toc_microcode(adev); 1702 if (r) 1703 dev_err(adev->dev, "Failed to load toc firmware!\n"); 1704 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1705 if (r) 1706 return r; 1707 } 1708 1709 r = gfx_v11_0_gpu_early_init(adev); 1710 if (r) 1711 return r; 1712 1713 return 0; 1714 } 1715 1716 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1717 { 1718 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1719 &adev->gfx.pfp.pfp_fw_gpu_addr, 1720 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1721 1722 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1723 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1724 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1725 } 1726 1727 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1728 { 1729 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1730 &adev->gfx.me.me_fw_gpu_addr, 1731 (void **)&adev->gfx.me.me_fw_ptr); 1732 1733 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1734 &adev->gfx.me.me_fw_data_gpu_addr, 1735 (void **)&adev->gfx.me.me_fw_data_ptr); 1736 } 1737 1738 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1739 { 1740 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1741 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1742 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1743 } 1744 1745 static int gfx_v11_0_sw_fini(void *handle) 1746 { 1747 int i; 1748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1749 1750 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1751 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1752 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1753 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1754 1755 amdgpu_gfx_mqd_sw_fini(adev); 1756 1757 if (!adev->enable_mes_kiq) { 1758 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1759 amdgpu_gfx_kiq_fini(adev); 1760 } 1761 1762 gfx_v11_0_pfp_fini(adev); 1763 gfx_v11_0_me_fini(adev); 1764 gfx_v11_0_rlc_fini(adev); 1765 gfx_v11_0_mec_fini(adev); 1766 1767 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1768 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1769 1770 gfx_v11_0_free_microcode(adev); 1771 1772 return 0; 1773 } 1774 1775 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1776 u32 sh_num, u32 instance) 1777 { 1778 u32 data; 1779 1780 if (instance == 0xffffffff) 1781 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1782 INSTANCE_BROADCAST_WRITES, 1); 1783 else 1784 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1785 instance); 1786 1787 if (se_num == 0xffffffff) 1788 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1789 1); 1790 else 1791 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1792 1793 if (sh_num == 0xffffffff) 1794 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1795 1); 1796 else 1797 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1798 1799 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1800 } 1801 1802 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1803 { 1804 u32 data, mask; 1805 1806 data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1807 data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1808 1809 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1810 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1811 1812 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1813 adev->gfx.config.max_sh_per_se); 1814 1815 return (~data) & mask; 1816 } 1817 1818 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1819 { 1820 int i, j; 1821 u32 data; 1822 u32 active_rbs = 0; 1823 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1824 adev->gfx.config.max_sh_per_se; 1825 1826 mutex_lock(&adev->grbm_idx_mutex); 1827 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1828 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1829 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 1830 data = gfx_v11_0_get_rb_active_bitmap(adev); 1831 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1832 rb_bitmap_width_per_sh); 1833 } 1834 } 1835 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1836 mutex_unlock(&adev->grbm_idx_mutex); 1837 1838 adev->gfx.config.backend_enable_mask = active_rbs; 1839 adev->gfx.config.num_rbs = hweight32(active_rbs); 1840 } 1841 1842 #define DEFAULT_SH_MEM_BASES (0x6000) 1843 #define LDS_APP_BASE 0x1 1844 #define SCRATCH_APP_BASE 0x2 1845 1846 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1847 { 1848 int i; 1849 uint32_t sh_mem_bases; 1850 uint32_t data; 1851 1852 /* 1853 * Configure apertures: 1854 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1855 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1856 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1857 */ 1858 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1859 SCRATCH_APP_BASE; 1860 1861 mutex_lock(&adev->srbm_mutex); 1862 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1863 soc21_grbm_select(adev, 0, 0, 0, i); 1864 /* CP and shaders */ 1865 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1866 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1867 1868 /* Enable trap for each kfd vmid. */ 1869 data = RREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL)); 1870 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1871 } 1872 soc21_grbm_select(adev, 0, 0, 0, 0); 1873 mutex_unlock(&adev->srbm_mutex); 1874 1875 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1876 acccess. These should be enabled by FW for target VMIDs. */ 1877 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1878 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1879 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1880 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1881 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1882 } 1883 } 1884 1885 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1886 { 1887 int vmid; 1888 1889 /* 1890 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1891 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1892 * the driver can enable them for graphics. VMID0 should maintain 1893 * access so that HWS firmware can save/restore entries. 1894 */ 1895 for (vmid = 1; vmid < 16; vmid++) { 1896 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1897 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1898 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1899 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1900 } 1901 } 1902 1903 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1904 { 1905 /* TODO: harvest feature to be added later. */ 1906 } 1907 1908 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1909 { 1910 /* TCCs are global (not instanced). */ 1911 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1912 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1913 1914 adev->gfx.config.tcc_disabled_mask = 1915 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1916 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1917 } 1918 1919 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1920 { 1921 u32 tmp; 1922 int i; 1923 1924 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1925 1926 gfx_v11_0_setup_rb(adev); 1927 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1928 gfx_v11_0_get_tcc_info(adev); 1929 adev->gfx.config.pa_sc_tile_steering_override = 0; 1930 1931 /* XXX SH_MEM regs */ 1932 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1933 mutex_lock(&adev->srbm_mutex); 1934 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1935 soc21_grbm_select(adev, 0, 0, 0, i); 1936 /* CP and shaders */ 1937 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1938 if (i != 0) { 1939 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1940 (adev->gmc.private_aperture_start >> 48)); 1941 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1942 (adev->gmc.shared_aperture_start >> 48)); 1943 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1944 } 1945 } 1946 soc21_grbm_select(adev, 0, 0, 0, 0); 1947 1948 mutex_unlock(&adev->srbm_mutex); 1949 1950 gfx_v11_0_init_compute_vmid(adev); 1951 gfx_v11_0_init_gds_vmid(adev); 1952 } 1953 1954 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1955 bool enable) 1956 { 1957 u32 tmp; 1958 1959 if (amdgpu_sriov_vf(adev)) 1960 return; 1961 1962 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1963 1964 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1965 enable ? 1 : 0); 1966 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1967 enable ? 1 : 0); 1968 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1969 enable ? 1 : 0); 1970 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1971 enable ? 1 : 0); 1972 1973 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1974 } 1975 1976 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1977 { 1978 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1979 1980 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1981 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1982 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1983 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1984 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1985 1986 return 0; 1987 } 1988 1989 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1990 { 1991 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1992 1993 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1994 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1995 } 1996 1997 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1998 { 1999 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2000 udelay(50); 2001 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2002 udelay(50); 2003 } 2004 2005 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 2006 bool enable) 2007 { 2008 uint32_t rlc_pg_cntl; 2009 2010 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 2011 2012 if (!enable) { 2013 /* RLC_PG_CNTL[23] = 0 (default) 2014 * RLC will wait for handshake acks with SMU 2015 * GFXOFF will be enabled 2016 * RLC_PG_CNTL[23] = 1 2017 * RLC will not issue any message to SMU 2018 * hence no handshake between SMU & RLC 2019 * GFXOFF will be disabled 2020 */ 2021 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2022 } else 2023 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 2024 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 2025 } 2026 2027 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 2028 { 2029 /* TODO: enable rlc & smu handshake until smu 2030 * and gfxoff feature works as expected */ 2031 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2032 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2033 2034 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2035 udelay(50); 2036 } 2037 2038 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2039 { 2040 uint32_t tmp; 2041 2042 /* enable Save Restore Machine */ 2043 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2044 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2045 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2046 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2047 } 2048 2049 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2050 { 2051 const struct rlc_firmware_header_v2_0 *hdr; 2052 const __le32 *fw_data; 2053 unsigned i, fw_size; 2054 2055 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2056 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2057 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2058 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2059 2060 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2061 RLCG_UCODE_LOADING_START_ADDRESS); 2062 2063 for (i = 0; i < fw_size; i++) 2064 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2065 le32_to_cpup(fw_data++)); 2066 2067 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2068 } 2069 2070 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2071 { 2072 const struct rlc_firmware_header_v2_2 *hdr; 2073 const __le32 *fw_data; 2074 unsigned i, fw_size; 2075 u32 tmp; 2076 2077 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2078 2079 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2080 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2081 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2082 2083 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2084 2085 for (i = 0; i < fw_size; i++) { 2086 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2087 msleep(1); 2088 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2089 le32_to_cpup(fw_data++)); 2090 } 2091 2092 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2093 2094 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2095 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2096 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2097 2098 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2099 for (i = 0; i < fw_size; i++) { 2100 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2101 msleep(1); 2102 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2103 le32_to_cpup(fw_data++)); 2104 } 2105 2106 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2107 2108 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2109 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2110 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2111 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2112 } 2113 2114 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2115 { 2116 const struct rlc_firmware_header_v2_3 *hdr; 2117 const __le32 *fw_data; 2118 unsigned i, fw_size; 2119 u32 tmp; 2120 2121 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2122 2123 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2124 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2125 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2126 2127 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2128 2129 for (i = 0; i < fw_size; i++) { 2130 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2131 msleep(1); 2132 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2133 le32_to_cpup(fw_data++)); 2134 } 2135 2136 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2137 2138 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2139 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2140 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2141 2142 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2143 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2144 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2145 2146 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2147 2148 for (i = 0; i < fw_size; i++) { 2149 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2150 msleep(1); 2151 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2152 le32_to_cpup(fw_data++)); 2153 } 2154 2155 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2156 2157 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2158 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2159 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2160 } 2161 2162 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2163 { 2164 const struct rlc_firmware_header_v2_0 *hdr; 2165 uint16_t version_major; 2166 uint16_t version_minor; 2167 2168 if (!adev->gfx.rlc_fw) 2169 return -EINVAL; 2170 2171 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2172 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2173 2174 version_major = le16_to_cpu(hdr->header.header_version_major); 2175 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2176 2177 if (version_major == 2) { 2178 gfx_v11_0_load_rlcg_microcode(adev); 2179 if (amdgpu_dpm == 1) { 2180 if (version_minor >= 2) 2181 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2182 if (version_minor == 3) 2183 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2184 } 2185 2186 return 0; 2187 } 2188 2189 return -EINVAL; 2190 } 2191 2192 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2193 { 2194 int r; 2195 2196 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2197 gfx_v11_0_init_csb(adev); 2198 2199 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2200 gfx_v11_0_rlc_enable_srm(adev); 2201 } else { 2202 if (amdgpu_sriov_vf(adev)) { 2203 gfx_v11_0_init_csb(adev); 2204 return 0; 2205 } 2206 2207 adev->gfx.rlc.funcs->stop(adev); 2208 2209 /* disable CG */ 2210 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2211 2212 /* disable PG */ 2213 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2214 2215 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2216 /* legacy rlc firmware loading */ 2217 r = gfx_v11_0_rlc_load_microcode(adev); 2218 if (r) 2219 return r; 2220 } 2221 2222 gfx_v11_0_init_csb(adev); 2223 2224 adev->gfx.rlc.funcs->start(adev); 2225 } 2226 return 0; 2227 } 2228 2229 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2230 { 2231 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2232 uint32_t tmp; 2233 int i; 2234 2235 /* Trigger an invalidation of the L1 instruction caches */ 2236 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2237 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2238 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2239 2240 /* Wait for invalidation complete */ 2241 for (i = 0; i < usec_timeout; i++) { 2242 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2243 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2244 INVALIDATE_CACHE_COMPLETE)) 2245 break; 2246 udelay(1); 2247 } 2248 2249 if (i >= usec_timeout) { 2250 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2251 return -EINVAL; 2252 } 2253 2254 if (amdgpu_emu_mode == 1) 2255 adev->hdp.funcs->flush_hdp(adev, NULL); 2256 2257 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2258 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2259 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2260 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2261 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2262 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2263 2264 /* Program me ucode address into intruction cache address register */ 2265 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2266 lower_32_bits(addr) & 0xFFFFF000); 2267 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2268 upper_32_bits(addr)); 2269 2270 return 0; 2271 } 2272 2273 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2274 { 2275 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2276 uint32_t tmp; 2277 int i; 2278 2279 /* Trigger an invalidation of the L1 instruction caches */ 2280 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2281 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2282 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2283 2284 /* Wait for invalidation complete */ 2285 for (i = 0; i < usec_timeout; i++) { 2286 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2287 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2288 INVALIDATE_CACHE_COMPLETE)) 2289 break; 2290 udelay(1); 2291 } 2292 2293 if (i >= usec_timeout) { 2294 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2295 return -EINVAL; 2296 } 2297 2298 if (amdgpu_emu_mode == 1) 2299 adev->hdp.funcs->flush_hdp(adev, NULL); 2300 2301 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2302 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2303 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2304 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2305 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2306 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2307 2308 /* Program pfp ucode address into intruction cache address register */ 2309 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2310 lower_32_bits(addr) & 0xFFFFF000); 2311 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2312 upper_32_bits(addr)); 2313 2314 return 0; 2315 } 2316 2317 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2318 { 2319 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2320 uint32_t tmp; 2321 int i; 2322 2323 /* Trigger an invalidation of the L1 instruction caches */ 2324 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2325 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2326 2327 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2328 2329 /* Wait for invalidation complete */ 2330 for (i = 0; i < usec_timeout; i++) { 2331 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2332 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2333 INVALIDATE_CACHE_COMPLETE)) 2334 break; 2335 udelay(1); 2336 } 2337 2338 if (i >= usec_timeout) { 2339 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2340 return -EINVAL; 2341 } 2342 2343 if (amdgpu_emu_mode == 1) 2344 adev->hdp.funcs->flush_hdp(adev, NULL); 2345 2346 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2347 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2348 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2349 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2350 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2351 2352 /* Program mec1 ucode address into intruction cache address register */ 2353 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2354 lower_32_bits(addr) & 0xFFFFF000); 2355 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2356 upper_32_bits(addr)); 2357 2358 return 0; 2359 } 2360 2361 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2362 { 2363 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2364 uint32_t tmp; 2365 unsigned i, pipe_id; 2366 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2367 2368 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2369 adev->gfx.pfp_fw->data; 2370 2371 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2372 lower_32_bits(addr)); 2373 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2374 upper_32_bits(addr)); 2375 2376 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2377 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2378 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2379 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2380 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2381 2382 /* 2383 * Programming any of the CP_PFP_IC_BASE registers 2384 * forces invalidation of the ME L1 I$. Wait for the 2385 * invalidation complete 2386 */ 2387 for (i = 0; i < usec_timeout; i++) { 2388 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2389 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2390 INVALIDATE_CACHE_COMPLETE)) 2391 break; 2392 udelay(1); 2393 } 2394 2395 if (i >= usec_timeout) { 2396 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2397 return -EINVAL; 2398 } 2399 2400 /* Prime the L1 instruction caches */ 2401 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2402 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2403 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2404 /* Waiting for cache primed*/ 2405 for (i = 0; i < usec_timeout; i++) { 2406 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2407 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2408 ICACHE_PRIMED)) 2409 break; 2410 udelay(1); 2411 } 2412 2413 if (i >= usec_timeout) { 2414 dev_err(adev->dev, "failed to prime instruction cache\n"); 2415 return -EINVAL; 2416 } 2417 2418 mutex_lock(&adev->srbm_mutex); 2419 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2420 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2421 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2422 (pfp_hdr->ucode_start_addr_hi << 30) | 2423 (pfp_hdr->ucode_start_addr_lo >> 2)); 2424 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2425 pfp_hdr->ucode_start_addr_hi >> 2); 2426 2427 /* 2428 * Program CP_ME_CNTL to reset given PIPE to take 2429 * effect of CP_PFP_PRGRM_CNTR_START. 2430 */ 2431 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2432 if (pipe_id == 0) 2433 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2434 PFP_PIPE0_RESET, 1); 2435 else 2436 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2437 PFP_PIPE1_RESET, 1); 2438 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2439 2440 /* Clear pfp pipe0 reset bit. */ 2441 if (pipe_id == 0) 2442 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2443 PFP_PIPE0_RESET, 0); 2444 else 2445 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2446 PFP_PIPE1_RESET, 0); 2447 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2448 2449 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2450 lower_32_bits(addr2)); 2451 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2452 upper_32_bits(addr2)); 2453 } 2454 soc21_grbm_select(adev, 0, 0, 0, 0); 2455 mutex_unlock(&adev->srbm_mutex); 2456 2457 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2458 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2459 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2460 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2461 2462 /* Invalidate the data caches */ 2463 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2464 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2465 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2466 2467 for (i = 0; i < usec_timeout; i++) { 2468 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2469 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2470 INVALIDATE_DCACHE_COMPLETE)) 2471 break; 2472 udelay(1); 2473 } 2474 2475 if (i >= usec_timeout) { 2476 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2477 return -EINVAL; 2478 } 2479 2480 return 0; 2481 } 2482 2483 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2484 { 2485 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2486 uint32_t tmp; 2487 unsigned i, pipe_id; 2488 const struct gfx_firmware_header_v2_0 *me_hdr; 2489 2490 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2491 adev->gfx.me_fw->data; 2492 2493 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2494 lower_32_bits(addr)); 2495 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2496 upper_32_bits(addr)); 2497 2498 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2499 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2500 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2501 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2502 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2503 2504 /* 2505 * Programming any of the CP_ME_IC_BASE registers 2506 * forces invalidation of the ME L1 I$. Wait for the 2507 * invalidation complete 2508 */ 2509 for (i = 0; i < usec_timeout; i++) { 2510 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2511 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2512 INVALIDATE_CACHE_COMPLETE)) 2513 break; 2514 udelay(1); 2515 } 2516 2517 if (i >= usec_timeout) { 2518 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2519 return -EINVAL; 2520 } 2521 2522 /* Prime the instruction caches */ 2523 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2524 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2525 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2526 2527 /* Waiting for instruction cache primed*/ 2528 for (i = 0; i < usec_timeout; i++) { 2529 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2530 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2531 ICACHE_PRIMED)) 2532 break; 2533 udelay(1); 2534 } 2535 2536 if (i >= usec_timeout) { 2537 dev_err(adev->dev, "failed to prime instruction cache\n"); 2538 return -EINVAL; 2539 } 2540 2541 mutex_lock(&adev->srbm_mutex); 2542 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2543 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2544 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2545 (me_hdr->ucode_start_addr_hi << 30) | 2546 (me_hdr->ucode_start_addr_lo >> 2) ); 2547 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2548 me_hdr->ucode_start_addr_hi>>2); 2549 2550 /* 2551 * Program CP_ME_CNTL to reset given PIPE to take 2552 * effect of CP_PFP_PRGRM_CNTR_START. 2553 */ 2554 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2555 if (pipe_id == 0) 2556 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2557 ME_PIPE0_RESET, 1); 2558 else 2559 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2560 ME_PIPE1_RESET, 1); 2561 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2562 2563 /* Clear pfp pipe0 reset bit. */ 2564 if (pipe_id == 0) 2565 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2566 ME_PIPE0_RESET, 0); 2567 else 2568 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2569 ME_PIPE1_RESET, 0); 2570 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2571 2572 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2573 lower_32_bits(addr2)); 2574 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2575 upper_32_bits(addr2)); 2576 } 2577 soc21_grbm_select(adev, 0, 0, 0, 0); 2578 mutex_unlock(&adev->srbm_mutex); 2579 2580 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2581 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2582 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2583 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2584 2585 /* Invalidate the data caches */ 2586 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2587 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2588 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2589 2590 for (i = 0; i < usec_timeout; i++) { 2591 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2592 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2593 INVALIDATE_DCACHE_COMPLETE)) 2594 break; 2595 udelay(1); 2596 } 2597 2598 if (i >= usec_timeout) { 2599 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2600 return -EINVAL; 2601 } 2602 2603 return 0; 2604 } 2605 2606 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2607 { 2608 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2609 uint32_t tmp; 2610 unsigned i; 2611 const struct gfx_firmware_header_v2_0 *mec_hdr; 2612 2613 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2614 adev->gfx.mec_fw->data; 2615 2616 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2617 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2618 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2619 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2620 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2621 2622 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2623 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2624 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2625 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2626 2627 mutex_lock(&adev->srbm_mutex); 2628 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2629 soc21_grbm_select(adev, 1, i, 0, 0); 2630 2631 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2632 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2633 upper_32_bits(addr2)); 2634 2635 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2636 mec_hdr->ucode_start_addr_lo >> 2 | 2637 mec_hdr->ucode_start_addr_hi << 30); 2638 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2639 mec_hdr->ucode_start_addr_hi >> 2); 2640 2641 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2642 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2643 upper_32_bits(addr)); 2644 } 2645 mutex_unlock(&adev->srbm_mutex); 2646 soc21_grbm_select(adev, 0, 0, 0, 0); 2647 2648 /* Trigger an invalidation of the L1 instruction caches */ 2649 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2650 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2651 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2652 2653 /* Wait for invalidation complete */ 2654 for (i = 0; i < usec_timeout; i++) { 2655 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2656 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2657 INVALIDATE_DCACHE_COMPLETE)) 2658 break; 2659 udelay(1); 2660 } 2661 2662 if (i >= usec_timeout) { 2663 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2664 return -EINVAL; 2665 } 2666 2667 /* Trigger an invalidation of the L1 instruction caches */ 2668 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2669 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2670 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2671 2672 /* Wait for invalidation complete */ 2673 for (i = 0; i < usec_timeout; i++) { 2674 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2675 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2676 INVALIDATE_CACHE_COMPLETE)) 2677 break; 2678 udelay(1); 2679 } 2680 2681 if (i >= usec_timeout) { 2682 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2683 return -EINVAL; 2684 } 2685 2686 return 0; 2687 } 2688 2689 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2690 { 2691 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2692 const struct gfx_firmware_header_v2_0 *me_hdr; 2693 const struct gfx_firmware_header_v2_0 *mec_hdr; 2694 uint32_t pipe_id, tmp; 2695 2696 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2697 adev->gfx.mec_fw->data; 2698 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2699 adev->gfx.me_fw->data; 2700 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2701 adev->gfx.pfp_fw->data; 2702 2703 /* config pfp program start addr */ 2704 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2705 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2706 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2707 (pfp_hdr->ucode_start_addr_hi << 30) | 2708 (pfp_hdr->ucode_start_addr_lo >> 2)); 2709 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2710 pfp_hdr->ucode_start_addr_hi >> 2); 2711 } 2712 soc21_grbm_select(adev, 0, 0, 0, 0); 2713 2714 /* reset pfp pipe */ 2715 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2716 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2717 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2718 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2719 2720 /* clear pfp pipe reset */ 2721 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2722 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2723 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2724 2725 /* config me program start addr */ 2726 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2727 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2728 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2729 (me_hdr->ucode_start_addr_hi << 30) | 2730 (me_hdr->ucode_start_addr_lo >> 2) ); 2731 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2732 me_hdr->ucode_start_addr_hi>>2); 2733 } 2734 soc21_grbm_select(adev, 0, 0, 0, 0); 2735 2736 /* reset me pipe */ 2737 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2738 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2739 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2740 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2741 2742 /* clear me pipe reset */ 2743 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2744 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2745 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2746 2747 /* config mec program start addr */ 2748 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2749 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2750 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2751 mec_hdr->ucode_start_addr_lo >> 2 | 2752 mec_hdr->ucode_start_addr_hi << 30); 2753 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2754 mec_hdr->ucode_start_addr_hi >> 2); 2755 } 2756 soc21_grbm_select(adev, 0, 0, 0, 0); 2757 } 2758 2759 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2760 { 2761 uint32_t cp_status; 2762 uint32_t bootload_status; 2763 int i, r; 2764 uint64_t addr, addr2; 2765 2766 for (i = 0; i < adev->usec_timeout; i++) { 2767 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2768 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2769 if ((cp_status == 0) && 2770 (REG_GET_FIELD(bootload_status, 2771 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2772 break; 2773 } 2774 udelay(1); 2775 } 2776 2777 if (i >= adev->usec_timeout) { 2778 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2779 return -ETIMEDOUT; 2780 } 2781 2782 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2783 if (adev->gfx.rs64_enable) { 2784 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2785 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2786 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2787 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2788 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2789 if (r) 2790 return r; 2791 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2792 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2793 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2794 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2795 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2796 if (r) 2797 return r; 2798 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2799 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2800 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2801 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2802 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2803 if (r) 2804 return r; 2805 } else { 2806 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2807 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2808 r = gfx_v11_0_config_me_cache(adev, addr); 2809 if (r) 2810 return r; 2811 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2812 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2813 r = gfx_v11_0_config_pfp_cache(adev, addr); 2814 if (r) 2815 return r; 2816 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2817 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2818 r = gfx_v11_0_config_mec_cache(adev, addr); 2819 if (r) 2820 return r; 2821 } 2822 } 2823 2824 return 0; 2825 } 2826 2827 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2828 { 2829 int i; 2830 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2831 2832 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2833 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2834 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2835 2836 for (i = 0; i < adev->usec_timeout; i++) { 2837 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2838 break; 2839 udelay(1); 2840 } 2841 2842 if (i >= adev->usec_timeout) 2843 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2844 2845 return 0; 2846 } 2847 2848 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2849 { 2850 int r; 2851 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2852 const __le32 *fw_data; 2853 unsigned i, fw_size; 2854 2855 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2856 adev->gfx.pfp_fw->data; 2857 2858 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2859 2860 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2861 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2862 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2863 2864 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2865 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2866 &adev->gfx.pfp.pfp_fw_obj, 2867 &adev->gfx.pfp.pfp_fw_gpu_addr, 2868 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2869 if (r) { 2870 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2871 gfx_v11_0_pfp_fini(adev); 2872 return r; 2873 } 2874 2875 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2876 2877 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2878 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2879 2880 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2881 2882 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2883 2884 for (i = 0; i < pfp_hdr->jt_size; i++) 2885 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2886 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2887 2888 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2889 2890 return 0; 2891 } 2892 2893 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2894 { 2895 int r; 2896 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2897 const __le32 *fw_ucode, *fw_data; 2898 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2899 uint32_t tmp; 2900 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2901 2902 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2903 adev->gfx.pfp_fw->data; 2904 2905 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2906 2907 /* instruction */ 2908 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2909 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2910 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2911 /* data */ 2912 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2913 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2914 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2915 2916 /* 64kb align */ 2917 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2918 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2919 &adev->gfx.pfp.pfp_fw_obj, 2920 &adev->gfx.pfp.pfp_fw_gpu_addr, 2921 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2922 if (r) { 2923 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2924 gfx_v11_0_pfp_fini(adev); 2925 return r; 2926 } 2927 2928 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2929 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2930 &adev->gfx.pfp.pfp_fw_data_obj, 2931 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2932 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2933 if (r) { 2934 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2935 gfx_v11_0_pfp_fini(adev); 2936 return r; 2937 } 2938 2939 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2940 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2941 2942 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2943 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2944 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2945 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2946 2947 if (amdgpu_emu_mode == 1) 2948 adev->hdp.funcs->flush_hdp(adev, NULL); 2949 2950 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2951 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2952 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2953 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2954 2955 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2956 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2957 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2958 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2959 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2960 2961 /* 2962 * Programming any of the CP_PFP_IC_BASE registers 2963 * forces invalidation of the ME L1 I$. Wait for the 2964 * invalidation complete 2965 */ 2966 for (i = 0; i < usec_timeout; i++) { 2967 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2968 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2969 INVALIDATE_CACHE_COMPLETE)) 2970 break; 2971 udelay(1); 2972 } 2973 2974 if (i >= usec_timeout) { 2975 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2976 return -EINVAL; 2977 } 2978 2979 /* Prime the L1 instruction caches */ 2980 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2981 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2982 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2983 /* Waiting for cache primed*/ 2984 for (i = 0; i < usec_timeout; i++) { 2985 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2986 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2987 ICACHE_PRIMED)) 2988 break; 2989 udelay(1); 2990 } 2991 2992 if (i >= usec_timeout) { 2993 dev_err(adev->dev, "failed to prime instruction cache\n"); 2994 return -EINVAL; 2995 } 2996 2997 mutex_lock(&adev->srbm_mutex); 2998 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2999 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3000 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 3001 (pfp_hdr->ucode_start_addr_hi << 30) | 3002 (pfp_hdr->ucode_start_addr_lo >> 2) ); 3003 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 3004 pfp_hdr->ucode_start_addr_hi>>2); 3005 3006 /* 3007 * Program CP_ME_CNTL to reset given PIPE to take 3008 * effect of CP_PFP_PRGRM_CNTR_START. 3009 */ 3010 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3011 if (pipe_id == 0) 3012 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3013 PFP_PIPE0_RESET, 1); 3014 else 3015 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3016 PFP_PIPE1_RESET, 1); 3017 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3018 3019 /* Clear pfp pipe0 reset bit. */ 3020 if (pipe_id == 0) 3021 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3022 PFP_PIPE0_RESET, 0); 3023 else 3024 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3025 PFP_PIPE1_RESET, 0); 3026 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3027 3028 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 3029 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3030 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3031 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3032 } 3033 soc21_grbm_select(adev, 0, 0, 0, 0); 3034 mutex_unlock(&adev->srbm_mutex); 3035 3036 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3037 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3038 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3039 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3040 3041 /* Invalidate the data caches */ 3042 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3043 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3044 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3045 3046 for (i = 0; i < usec_timeout; i++) { 3047 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3048 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3049 INVALIDATE_DCACHE_COMPLETE)) 3050 break; 3051 udelay(1); 3052 } 3053 3054 if (i >= usec_timeout) { 3055 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3056 return -EINVAL; 3057 } 3058 3059 return 0; 3060 } 3061 3062 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3063 { 3064 int r; 3065 const struct gfx_firmware_header_v1_0 *me_hdr; 3066 const __le32 *fw_data; 3067 unsigned i, fw_size; 3068 3069 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3070 adev->gfx.me_fw->data; 3071 3072 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3073 3074 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3075 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3076 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3077 3078 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3079 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3080 &adev->gfx.me.me_fw_obj, 3081 &adev->gfx.me.me_fw_gpu_addr, 3082 (void **)&adev->gfx.me.me_fw_ptr); 3083 if (r) { 3084 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3085 gfx_v11_0_me_fini(adev); 3086 return r; 3087 } 3088 3089 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3090 3091 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3092 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3093 3094 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3095 3096 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3097 3098 for (i = 0; i < me_hdr->jt_size; i++) 3099 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3100 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3101 3102 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3103 3104 return 0; 3105 } 3106 3107 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3108 { 3109 int r; 3110 const struct gfx_firmware_header_v2_0 *me_hdr; 3111 const __le32 *fw_ucode, *fw_data; 3112 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3113 uint32_t tmp; 3114 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3115 3116 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3117 adev->gfx.me_fw->data; 3118 3119 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3120 3121 /* instruction */ 3122 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3123 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3124 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3125 /* data */ 3126 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3127 le32_to_cpu(me_hdr->data_offset_bytes)); 3128 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3129 3130 /* 64kb align*/ 3131 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3132 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3133 &adev->gfx.me.me_fw_obj, 3134 &adev->gfx.me.me_fw_gpu_addr, 3135 (void **)&adev->gfx.me.me_fw_ptr); 3136 if (r) { 3137 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3138 gfx_v11_0_me_fini(adev); 3139 return r; 3140 } 3141 3142 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3143 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3144 &adev->gfx.me.me_fw_data_obj, 3145 &adev->gfx.me.me_fw_data_gpu_addr, 3146 (void **)&adev->gfx.me.me_fw_data_ptr); 3147 if (r) { 3148 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3149 gfx_v11_0_pfp_fini(adev); 3150 return r; 3151 } 3152 3153 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3154 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3155 3156 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3157 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3158 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3159 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3160 3161 if (amdgpu_emu_mode == 1) 3162 adev->hdp.funcs->flush_hdp(adev, NULL); 3163 3164 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3165 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3166 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3167 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3168 3169 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3170 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3171 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3172 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3173 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3174 3175 /* 3176 * Programming any of the CP_ME_IC_BASE registers 3177 * forces invalidation of the ME L1 I$. Wait for the 3178 * invalidation complete 3179 */ 3180 for (i = 0; i < usec_timeout; i++) { 3181 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3182 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3183 INVALIDATE_CACHE_COMPLETE)) 3184 break; 3185 udelay(1); 3186 } 3187 3188 if (i >= usec_timeout) { 3189 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3190 return -EINVAL; 3191 } 3192 3193 /* Prime the instruction caches */ 3194 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3195 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3196 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3197 3198 /* Waiting for instruction cache primed*/ 3199 for (i = 0; i < usec_timeout; i++) { 3200 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3201 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3202 ICACHE_PRIMED)) 3203 break; 3204 udelay(1); 3205 } 3206 3207 if (i >= usec_timeout) { 3208 dev_err(adev->dev, "failed to prime instruction cache\n"); 3209 return -EINVAL; 3210 } 3211 3212 mutex_lock(&adev->srbm_mutex); 3213 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3214 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3215 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3216 (me_hdr->ucode_start_addr_hi << 30) | 3217 (me_hdr->ucode_start_addr_lo >> 2) ); 3218 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3219 me_hdr->ucode_start_addr_hi>>2); 3220 3221 /* 3222 * Program CP_ME_CNTL to reset given PIPE to take 3223 * effect of CP_PFP_PRGRM_CNTR_START. 3224 */ 3225 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3226 if (pipe_id == 0) 3227 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3228 ME_PIPE0_RESET, 1); 3229 else 3230 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3231 ME_PIPE1_RESET, 1); 3232 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3233 3234 /* Clear pfp pipe0 reset bit. */ 3235 if (pipe_id == 0) 3236 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3237 ME_PIPE0_RESET, 0); 3238 else 3239 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3240 ME_PIPE1_RESET, 0); 3241 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3242 3243 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3244 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3245 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3246 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3247 } 3248 soc21_grbm_select(adev, 0, 0, 0, 0); 3249 mutex_unlock(&adev->srbm_mutex); 3250 3251 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3252 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3253 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3254 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3255 3256 /* Invalidate the data caches */ 3257 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3258 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3259 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3260 3261 for (i = 0; i < usec_timeout; i++) { 3262 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3263 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3264 INVALIDATE_DCACHE_COMPLETE)) 3265 break; 3266 udelay(1); 3267 } 3268 3269 if (i >= usec_timeout) { 3270 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3271 return -EINVAL; 3272 } 3273 3274 return 0; 3275 } 3276 3277 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3278 { 3279 int r; 3280 3281 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3282 return -EINVAL; 3283 3284 gfx_v11_0_cp_gfx_enable(adev, false); 3285 3286 if (adev->gfx.rs64_enable) 3287 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3288 else 3289 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3290 if (r) { 3291 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3292 return r; 3293 } 3294 3295 if (adev->gfx.rs64_enable) 3296 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3297 else 3298 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3299 if (r) { 3300 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3301 return r; 3302 } 3303 3304 return 0; 3305 } 3306 3307 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3308 { 3309 struct amdgpu_ring *ring; 3310 const struct cs_section_def *sect = NULL; 3311 const struct cs_extent_def *ext = NULL; 3312 int r, i; 3313 int ctx_reg_offset; 3314 3315 /* init the CP */ 3316 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3317 adev->gfx.config.max_hw_contexts - 1); 3318 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3319 3320 if (!amdgpu_async_gfx_ring) 3321 gfx_v11_0_cp_gfx_enable(adev, true); 3322 3323 ring = &adev->gfx.gfx_ring[0]; 3324 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3325 if (r) { 3326 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3327 return r; 3328 } 3329 3330 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3331 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3332 3333 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3334 amdgpu_ring_write(ring, 0x80000000); 3335 amdgpu_ring_write(ring, 0x80000000); 3336 3337 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3338 for (ext = sect->section; ext->extent != NULL; ++ext) { 3339 if (sect->id == SECT_CONTEXT) { 3340 amdgpu_ring_write(ring, 3341 PACKET3(PACKET3_SET_CONTEXT_REG, 3342 ext->reg_count)); 3343 amdgpu_ring_write(ring, ext->reg_index - 3344 PACKET3_SET_CONTEXT_REG_START); 3345 for (i = 0; i < ext->reg_count; i++) 3346 amdgpu_ring_write(ring, ext->extent[i]); 3347 } 3348 } 3349 } 3350 3351 ctx_reg_offset = 3352 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3353 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3354 amdgpu_ring_write(ring, ctx_reg_offset); 3355 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3356 3357 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3358 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3359 3360 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3361 amdgpu_ring_write(ring, 0); 3362 3363 amdgpu_ring_commit(ring); 3364 3365 /* submit cs packet to copy state 0 to next available state */ 3366 if (adev->gfx.num_gfx_rings > 1) { 3367 /* maximum supported gfx ring is 2 */ 3368 ring = &adev->gfx.gfx_ring[1]; 3369 r = amdgpu_ring_alloc(ring, 2); 3370 if (r) { 3371 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3372 return r; 3373 } 3374 3375 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3376 amdgpu_ring_write(ring, 0); 3377 3378 amdgpu_ring_commit(ring); 3379 } 3380 return 0; 3381 } 3382 3383 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3384 CP_PIPE_ID pipe) 3385 { 3386 u32 tmp; 3387 3388 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3389 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3390 3391 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3392 } 3393 3394 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3395 struct amdgpu_ring *ring) 3396 { 3397 u32 tmp; 3398 3399 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3400 if (ring->use_doorbell) { 3401 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3402 DOORBELL_OFFSET, ring->doorbell_index); 3403 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3404 DOORBELL_EN, 1); 3405 } else { 3406 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3407 DOORBELL_EN, 0); 3408 } 3409 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3410 3411 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3412 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3413 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3414 3415 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3416 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3417 } 3418 3419 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3420 { 3421 struct amdgpu_ring *ring; 3422 u32 tmp; 3423 u32 rb_bufsz; 3424 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3425 u32 i; 3426 3427 /* Set the write pointer delay */ 3428 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3429 3430 /* set the RB to use vmid 0 */ 3431 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3432 3433 /* Init gfx ring 0 for pipe 0 */ 3434 mutex_lock(&adev->srbm_mutex); 3435 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3436 3437 /* Set ring buffer size */ 3438 ring = &adev->gfx.gfx_ring[0]; 3439 rb_bufsz = order_base_2(ring->ring_size / 8); 3440 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3441 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3442 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3443 3444 /* Initialize the ring buffer's write pointers */ 3445 ring->wptr = 0; 3446 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3447 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3448 3449 /* set the wb address wether it's enabled or not */ 3450 rptr_addr = ring->rptr_gpu_addr; 3451 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3452 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3453 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3454 3455 wptr_gpu_addr = ring->wptr_gpu_addr; 3456 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3457 lower_32_bits(wptr_gpu_addr)); 3458 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3459 upper_32_bits(wptr_gpu_addr)); 3460 3461 mdelay(1); 3462 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3463 3464 rb_addr = ring->gpu_addr >> 8; 3465 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3466 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3467 3468 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3469 3470 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3471 mutex_unlock(&adev->srbm_mutex); 3472 3473 /* Init gfx ring 1 for pipe 1 */ 3474 if (adev->gfx.num_gfx_rings > 1) { 3475 mutex_lock(&adev->srbm_mutex); 3476 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3477 /* maximum supported gfx ring is 2 */ 3478 ring = &adev->gfx.gfx_ring[1]; 3479 rb_bufsz = order_base_2(ring->ring_size / 8); 3480 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3481 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3482 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3483 /* Initialize the ring buffer's write pointers */ 3484 ring->wptr = 0; 3485 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3486 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3487 /* Set the wb address wether it's enabled or not */ 3488 rptr_addr = ring->rptr_gpu_addr; 3489 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3490 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3491 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3492 wptr_gpu_addr = ring->wptr_gpu_addr; 3493 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3494 lower_32_bits(wptr_gpu_addr)); 3495 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3496 upper_32_bits(wptr_gpu_addr)); 3497 3498 mdelay(1); 3499 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3500 3501 rb_addr = ring->gpu_addr >> 8; 3502 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3503 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3504 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3505 3506 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3507 mutex_unlock(&adev->srbm_mutex); 3508 } 3509 /* Switch to pipe 0 */ 3510 mutex_lock(&adev->srbm_mutex); 3511 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3512 mutex_unlock(&adev->srbm_mutex); 3513 3514 /* start the ring */ 3515 gfx_v11_0_cp_gfx_start(adev); 3516 3517 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3518 ring = &adev->gfx.gfx_ring[i]; 3519 ring->sched.ready = true; 3520 } 3521 3522 return 0; 3523 } 3524 3525 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3526 { 3527 u32 data; 3528 3529 if (adev->gfx.rs64_enable) { 3530 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3531 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3532 enable ? 0 : 1); 3533 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3534 enable ? 0 : 1); 3535 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3536 enable ? 0 : 1); 3537 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3538 enable ? 0 : 1); 3539 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3540 enable ? 0 : 1); 3541 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3542 enable ? 1 : 0); 3543 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3544 enable ? 1 : 0); 3545 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3546 enable ? 1 : 0); 3547 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3548 enable ? 1 : 0); 3549 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3550 enable ? 0 : 1); 3551 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3552 } else { 3553 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3554 3555 if (enable) { 3556 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3557 if (!adev->enable_mes_kiq) 3558 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3559 MEC_ME2_HALT, 0); 3560 } else { 3561 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3562 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3563 } 3564 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3565 } 3566 3567 adev->gfx.kiq.ring.sched.ready = enable; 3568 3569 udelay(50); 3570 } 3571 3572 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3573 { 3574 const struct gfx_firmware_header_v1_0 *mec_hdr; 3575 const __le32 *fw_data; 3576 unsigned i, fw_size; 3577 u32 *fw = NULL; 3578 int r; 3579 3580 if (!adev->gfx.mec_fw) 3581 return -EINVAL; 3582 3583 gfx_v11_0_cp_compute_enable(adev, false); 3584 3585 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3586 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3587 3588 fw_data = (const __le32 *) 3589 (adev->gfx.mec_fw->data + 3590 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3591 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3592 3593 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3594 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3595 &adev->gfx.mec.mec_fw_obj, 3596 &adev->gfx.mec.mec_fw_gpu_addr, 3597 (void **)&fw); 3598 if (r) { 3599 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3600 gfx_v11_0_mec_fini(adev); 3601 return r; 3602 } 3603 3604 memcpy(fw, fw_data, fw_size); 3605 3606 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3607 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3608 3609 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3610 3611 /* MEC1 */ 3612 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3613 3614 for (i = 0; i < mec_hdr->jt_size; i++) 3615 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3616 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3617 3618 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3619 3620 return 0; 3621 } 3622 3623 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3624 { 3625 const struct gfx_firmware_header_v2_0 *mec_hdr; 3626 const __le32 *fw_ucode, *fw_data; 3627 u32 tmp, fw_ucode_size, fw_data_size; 3628 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3629 u32 *fw_ucode_ptr, *fw_data_ptr; 3630 int r; 3631 3632 if (!adev->gfx.mec_fw) 3633 return -EINVAL; 3634 3635 gfx_v11_0_cp_compute_enable(adev, false); 3636 3637 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3638 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3639 3640 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3641 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3642 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3643 3644 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3645 le32_to_cpu(mec_hdr->data_offset_bytes)); 3646 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3647 3648 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3649 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3650 &adev->gfx.mec.mec_fw_obj, 3651 &adev->gfx.mec.mec_fw_gpu_addr, 3652 (void **)&fw_ucode_ptr); 3653 if (r) { 3654 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3655 gfx_v11_0_mec_fini(adev); 3656 return r; 3657 } 3658 3659 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3660 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3661 &adev->gfx.mec.mec_fw_data_obj, 3662 &adev->gfx.mec.mec_fw_data_gpu_addr, 3663 (void **)&fw_data_ptr); 3664 if (r) { 3665 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3666 gfx_v11_0_mec_fini(adev); 3667 return r; 3668 } 3669 3670 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3671 memcpy(fw_data_ptr, fw_data, fw_data_size); 3672 3673 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3674 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3675 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3676 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3677 3678 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3679 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3680 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3681 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3682 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3683 3684 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3685 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3686 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3687 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3688 3689 mutex_lock(&adev->srbm_mutex); 3690 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3691 soc21_grbm_select(adev, 1, i, 0, 0); 3692 3693 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3694 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3695 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3696 3697 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3698 mec_hdr->ucode_start_addr_lo >> 2 | 3699 mec_hdr->ucode_start_addr_hi << 30); 3700 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3701 mec_hdr->ucode_start_addr_hi >> 2); 3702 3703 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3704 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3705 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3706 } 3707 mutex_unlock(&adev->srbm_mutex); 3708 soc21_grbm_select(adev, 0, 0, 0, 0); 3709 3710 /* Trigger an invalidation of the L1 instruction caches */ 3711 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3712 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3713 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3714 3715 /* Wait for invalidation complete */ 3716 for (i = 0; i < usec_timeout; i++) { 3717 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3718 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3719 INVALIDATE_DCACHE_COMPLETE)) 3720 break; 3721 udelay(1); 3722 } 3723 3724 if (i >= usec_timeout) { 3725 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3726 return -EINVAL; 3727 } 3728 3729 /* Trigger an invalidation of the L1 instruction caches */ 3730 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3731 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3732 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3733 3734 /* Wait for invalidation complete */ 3735 for (i = 0; i < usec_timeout; i++) { 3736 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3737 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3738 INVALIDATE_CACHE_COMPLETE)) 3739 break; 3740 udelay(1); 3741 } 3742 3743 if (i >= usec_timeout) { 3744 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3745 return -EINVAL; 3746 } 3747 3748 return 0; 3749 } 3750 3751 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3752 { 3753 uint32_t tmp; 3754 struct amdgpu_device *adev = ring->adev; 3755 3756 /* tell RLC which is KIQ queue */ 3757 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3758 tmp &= 0xffffff00; 3759 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3760 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3761 tmp |= 0x80; 3762 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3763 } 3764 3765 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3766 { 3767 /* set graphics engine doorbell range */ 3768 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3769 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3770 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3771 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3772 3773 /* set compute engine doorbell range */ 3774 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3775 (adev->doorbell_index.kiq * 2) << 2); 3776 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3777 (adev->doorbell_index.userqueue_end * 2) << 2); 3778 } 3779 3780 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3781 struct amdgpu_mqd_prop *prop) 3782 { 3783 struct v11_gfx_mqd *mqd = m; 3784 uint64_t hqd_gpu_addr, wb_gpu_addr; 3785 uint32_t tmp; 3786 uint32_t rb_bufsz; 3787 3788 /* set up gfx hqd wptr */ 3789 mqd->cp_gfx_hqd_wptr = 0; 3790 mqd->cp_gfx_hqd_wptr_hi = 0; 3791 3792 /* set the pointer to the MQD */ 3793 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3794 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3795 3796 /* set up mqd control */ 3797 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3798 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3799 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3800 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3801 mqd->cp_gfx_mqd_control = tmp; 3802 3803 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3804 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3805 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3806 mqd->cp_gfx_hqd_vmid = 0; 3807 3808 /* set up default queue priority level 3809 * 0x0 = low priority, 0x1 = high priority */ 3810 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3811 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3812 mqd->cp_gfx_hqd_queue_priority = tmp; 3813 3814 /* set up time quantum */ 3815 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3816 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3817 mqd->cp_gfx_hqd_quantum = tmp; 3818 3819 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3820 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3821 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3822 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3823 3824 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3825 wb_gpu_addr = prop->rptr_gpu_addr; 3826 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3827 mqd->cp_gfx_hqd_rptr_addr_hi = 3828 upper_32_bits(wb_gpu_addr) & 0xffff; 3829 3830 /* set up rb_wptr_poll addr */ 3831 wb_gpu_addr = prop->wptr_gpu_addr; 3832 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3833 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3834 3835 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3836 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3837 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3838 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3839 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3840 #ifdef __BIG_ENDIAN 3841 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3842 #endif 3843 mqd->cp_gfx_hqd_cntl = tmp; 3844 3845 /* set up cp_doorbell_control */ 3846 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3847 if (prop->use_doorbell) { 3848 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3849 DOORBELL_OFFSET, prop->doorbell_index); 3850 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3851 DOORBELL_EN, 1); 3852 } else 3853 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3854 DOORBELL_EN, 0); 3855 mqd->cp_rb_doorbell_control = tmp; 3856 3857 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3858 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3859 3860 /* active the queue */ 3861 mqd->cp_gfx_hqd_active = 1; 3862 3863 return 0; 3864 } 3865 3866 #ifdef BRING_UP_DEBUG 3867 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3868 { 3869 struct amdgpu_device *adev = ring->adev; 3870 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3871 3872 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3873 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3874 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3875 3876 /* set GFX_MQD_BASE */ 3877 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3878 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3879 3880 /* set GFX_MQD_CONTROL */ 3881 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3882 3883 /* set GFX_HQD_VMID to 0 */ 3884 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3885 3886 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY, 3887 mqd->cp_gfx_hqd_queue_priority); 3888 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3889 3890 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3891 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3892 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3893 3894 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3895 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3896 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3897 3898 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3899 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3900 3901 /* set RB_WPTR_POLL_ADDR */ 3902 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3903 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3904 3905 /* set RB_DOORBELL_CONTROL */ 3906 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3907 3908 /* active the queue */ 3909 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3910 3911 return 0; 3912 } 3913 #endif 3914 3915 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3916 { 3917 struct amdgpu_device *adev = ring->adev; 3918 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3919 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3920 3921 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3922 memset((void *)mqd, 0, sizeof(*mqd)); 3923 mutex_lock(&adev->srbm_mutex); 3924 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3925 amdgpu_ring_init_mqd(ring); 3926 #ifdef BRING_UP_DEBUG 3927 gfx_v11_0_gfx_queue_init_register(ring); 3928 #endif 3929 soc21_grbm_select(adev, 0, 0, 0, 0); 3930 mutex_unlock(&adev->srbm_mutex); 3931 if (adev->gfx.me.mqd_backup[mqd_idx]) 3932 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3933 } else if (amdgpu_in_reset(adev)) { 3934 /* reset mqd with the backup copy */ 3935 if (adev->gfx.me.mqd_backup[mqd_idx]) 3936 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3937 /* reset the ring */ 3938 ring->wptr = 0; 3939 *ring->wptr_cpu_addr = 0; 3940 amdgpu_ring_clear_ring(ring); 3941 #ifdef BRING_UP_DEBUG 3942 mutex_lock(&adev->srbm_mutex); 3943 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3944 gfx_v11_0_gfx_queue_init_register(ring); 3945 soc21_grbm_select(adev, 0, 0, 0, 0); 3946 mutex_unlock(&adev->srbm_mutex); 3947 #endif 3948 } else { 3949 amdgpu_ring_clear_ring(ring); 3950 } 3951 3952 return 0; 3953 } 3954 3955 #ifndef BRING_UP_DEBUG 3956 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev) 3957 { 3958 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3959 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3960 int r, i; 3961 3962 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3963 return -EINVAL; 3964 3965 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3966 adev->gfx.num_gfx_rings); 3967 if (r) { 3968 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3969 return r; 3970 } 3971 3972 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3973 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3974 3975 return amdgpu_ring_test_helper(kiq_ring); 3976 } 3977 #endif 3978 3979 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3980 { 3981 int r, i; 3982 struct amdgpu_ring *ring; 3983 3984 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3985 ring = &adev->gfx.gfx_ring[i]; 3986 3987 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3988 if (unlikely(r != 0)) 3989 goto done; 3990 3991 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3992 if (!r) { 3993 r = gfx_v11_0_gfx_init_queue(ring); 3994 amdgpu_bo_kunmap(ring->mqd_obj); 3995 ring->mqd_ptr = NULL; 3996 } 3997 amdgpu_bo_unreserve(ring->mqd_obj); 3998 if (r) 3999 goto done; 4000 } 4001 #ifndef BRING_UP_DEBUG 4002 r = gfx_v11_0_kiq_enable_kgq(adev); 4003 if (r) 4004 goto done; 4005 #endif 4006 r = gfx_v11_0_cp_gfx_start(adev); 4007 if (r) 4008 goto done; 4009 4010 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4011 ring = &adev->gfx.gfx_ring[i]; 4012 ring->sched.ready = true; 4013 } 4014 done: 4015 return r; 4016 } 4017 4018 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4019 struct amdgpu_mqd_prop *prop) 4020 { 4021 struct v11_compute_mqd *mqd = m; 4022 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4023 uint32_t tmp; 4024 4025 mqd->header = 0xC0310800; 4026 mqd->compute_pipelinestat_enable = 0x00000001; 4027 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4028 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4029 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4030 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4031 mqd->compute_misc_reserved = 0x00000007; 4032 4033 eop_base_addr = prop->eop_gpu_addr >> 8; 4034 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4035 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4036 4037 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4038 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 4039 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4040 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4041 4042 mqd->cp_hqd_eop_control = tmp; 4043 4044 /* enable doorbell? */ 4045 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4046 4047 if (prop->use_doorbell) { 4048 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4049 DOORBELL_OFFSET, prop->doorbell_index); 4050 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4051 DOORBELL_EN, 1); 4052 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4053 DOORBELL_SOURCE, 0); 4054 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4055 DOORBELL_HIT, 0); 4056 } else { 4057 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4058 DOORBELL_EN, 0); 4059 } 4060 4061 mqd->cp_hqd_pq_doorbell_control = tmp; 4062 4063 /* disable the queue if it's active */ 4064 mqd->cp_hqd_dequeue_request = 0; 4065 mqd->cp_hqd_pq_rptr = 0; 4066 mqd->cp_hqd_pq_wptr_lo = 0; 4067 mqd->cp_hqd_pq_wptr_hi = 0; 4068 4069 /* set the pointer to the MQD */ 4070 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4071 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4072 4073 /* set MQD vmid to 0 */ 4074 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 4075 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4076 mqd->cp_mqd_control = tmp; 4077 4078 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4079 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4080 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4081 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4082 4083 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4084 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 4085 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4086 (order_base_2(prop->queue_size / 4) - 1)); 4087 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4088 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 4089 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 4090 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 4091 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4092 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4093 mqd->cp_hqd_pq_control = tmp; 4094 4095 /* set the wb address whether it's enabled or not */ 4096 wb_gpu_addr = prop->rptr_gpu_addr; 4097 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4098 mqd->cp_hqd_pq_rptr_report_addr_hi = 4099 upper_32_bits(wb_gpu_addr) & 0xffff; 4100 4101 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4102 wb_gpu_addr = prop->wptr_gpu_addr; 4103 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4104 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4105 4106 tmp = 0; 4107 /* enable the doorbell if requested */ 4108 if (prop->use_doorbell) { 4109 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4110 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4111 DOORBELL_OFFSET, prop->doorbell_index); 4112 4113 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4114 DOORBELL_EN, 1); 4115 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4116 DOORBELL_SOURCE, 0); 4117 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4118 DOORBELL_HIT, 0); 4119 } 4120 4121 mqd->cp_hqd_pq_doorbell_control = tmp; 4122 4123 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4124 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 4125 4126 /* set the vmid for the queue */ 4127 mqd->cp_hqd_vmid = 0; 4128 4129 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 4130 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4131 mqd->cp_hqd_persistent_state = tmp; 4132 4133 /* set MIN_IB_AVAIL_SIZE */ 4134 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 4135 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4136 mqd->cp_hqd_ib_control = tmp; 4137 4138 /* set static priority for a compute queue/ring */ 4139 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4140 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4141 4142 mqd->cp_hqd_active = prop->hqd_active; 4143 4144 return 0; 4145 } 4146 4147 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4148 { 4149 struct amdgpu_device *adev = ring->adev; 4150 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4151 int j; 4152 4153 /* inactivate the queue */ 4154 if (amdgpu_sriov_vf(adev)) 4155 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4156 4157 /* disable wptr polling */ 4158 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4159 4160 /* write the EOP addr */ 4161 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4162 mqd->cp_hqd_eop_base_addr_lo); 4163 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4164 mqd->cp_hqd_eop_base_addr_hi); 4165 4166 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4167 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4168 mqd->cp_hqd_eop_control); 4169 4170 /* enable doorbell? */ 4171 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4172 mqd->cp_hqd_pq_doorbell_control); 4173 4174 /* disable the queue if it's active */ 4175 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4176 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4177 for (j = 0; j < adev->usec_timeout; j++) { 4178 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4179 break; 4180 udelay(1); 4181 } 4182 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4183 mqd->cp_hqd_dequeue_request); 4184 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4185 mqd->cp_hqd_pq_rptr); 4186 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4187 mqd->cp_hqd_pq_wptr_lo); 4188 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4189 mqd->cp_hqd_pq_wptr_hi); 4190 } 4191 4192 /* set the pointer to the MQD */ 4193 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4194 mqd->cp_mqd_base_addr_lo); 4195 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4196 mqd->cp_mqd_base_addr_hi); 4197 4198 /* set MQD vmid to 0 */ 4199 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4200 mqd->cp_mqd_control); 4201 4202 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4203 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4204 mqd->cp_hqd_pq_base_lo); 4205 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4206 mqd->cp_hqd_pq_base_hi); 4207 4208 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4209 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4210 mqd->cp_hqd_pq_control); 4211 4212 /* set the wb address whether it's enabled or not */ 4213 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4214 mqd->cp_hqd_pq_rptr_report_addr_lo); 4215 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4216 mqd->cp_hqd_pq_rptr_report_addr_hi); 4217 4218 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4219 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4220 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4221 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4222 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4223 4224 /* enable the doorbell if requested */ 4225 if (ring->use_doorbell) { 4226 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4227 (adev->doorbell_index.kiq * 2) << 2); 4228 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4229 (adev->doorbell_index.userqueue_end * 2) << 2); 4230 } 4231 4232 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4233 mqd->cp_hqd_pq_doorbell_control); 4234 4235 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4236 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4237 mqd->cp_hqd_pq_wptr_lo); 4238 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4239 mqd->cp_hqd_pq_wptr_hi); 4240 4241 /* set the vmid for the queue */ 4242 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4243 4244 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4245 mqd->cp_hqd_persistent_state); 4246 4247 /* activate the queue */ 4248 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4249 mqd->cp_hqd_active); 4250 4251 if (ring->use_doorbell) 4252 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4253 4254 return 0; 4255 } 4256 4257 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4258 { 4259 struct amdgpu_device *adev = ring->adev; 4260 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4261 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 4262 4263 gfx_v11_0_kiq_setting(ring); 4264 4265 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4266 /* reset MQD to a clean status */ 4267 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4268 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4269 4270 /* reset ring buffer */ 4271 ring->wptr = 0; 4272 amdgpu_ring_clear_ring(ring); 4273 4274 mutex_lock(&adev->srbm_mutex); 4275 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4276 gfx_v11_0_kiq_init_register(ring); 4277 soc21_grbm_select(adev, 0, 0, 0, 0); 4278 mutex_unlock(&adev->srbm_mutex); 4279 } else { 4280 memset((void *)mqd, 0, sizeof(*mqd)); 4281 mutex_lock(&adev->srbm_mutex); 4282 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4283 amdgpu_ring_init_mqd(ring); 4284 gfx_v11_0_kiq_init_register(ring); 4285 soc21_grbm_select(adev, 0, 0, 0, 0); 4286 mutex_unlock(&adev->srbm_mutex); 4287 4288 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4289 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4290 } 4291 4292 return 0; 4293 } 4294 4295 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4296 { 4297 struct amdgpu_device *adev = ring->adev; 4298 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4299 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4300 4301 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4302 memset((void *)mqd, 0, sizeof(*mqd)); 4303 mutex_lock(&adev->srbm_mutex); 4304 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4305 amdgpu_ring_init_mqd(ring); 4306 soc21_grbm_select(adev, 0, 0, 0, 0); 4307 mutex_unlock(&adev->srbm_mutex); 4308 4309 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4310 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4311 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4312 /* reset MQD to a clean status */ 4313 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4314 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4315 4316 /* reset ring buffer */ 4317 ring->wptr = 0; 4318 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4319 amdgpu_ring_clear_ring(ring); 4320 } else { 4321 amdgpu_ring_clear_ring(ring); 4322 } 4323 4324 return 0; 4325 } 4326 4327 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4328 { 4329 struct amdgpu_ring *ring; 4330 int r; 4331 4332 ring = &adev->gfx.kiq.ring; 4333 4334 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4335 if (unlikely(r != 0)) 4336 return r; 4337 4338 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4339 if (unlikely(r != 0)) { 4340 amdgpu_bo_unreserve(ring->mqd_obj); 4341 return r; 4342 } 4343 4344 gfx_v11_0_kiq_init_queue(ring); 4345 amdgpu_bo_kunmap(ring->mqd_obj); 4346 ring->mqd_ptr = NULL; 4347 amdgpu_bo_unreserve(ring->mqd_obj); 4348 ring->sched.ready = true; 4349 return 0; 4350 } 4351 4352 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4353 { 4354 struct amdgpu_ring *ring = NULL; 4355 int r = 0, i; 4356 4357 if (!amdgpu_async_gfx_ring) 4358 gfx_v11_0_cp_compute_enable(adev, true); 4359 4360 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4361 ring = &adev->gfx.compute_ring[i]; 4362 4363 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4364 if (unlikely(r != 0)) 4365 goto done; 4366 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4367 if (!r) { 4368 r = gfx_v11_0_kcq_init_queue(ring); 4369 amdgpu_bo_kunmap(ring->mqd_obj); 4370 ring->mqd_ptr = NULL; 4371 } 4372 amdgpu_bo_unreserve(ring->mqd_obj); 4373 if (r) 4374 goto done; 4375 } 4376 4377 r = amdgpu_gfx_enable_kcq(adev); 4378 done: 4379 return r; 4380 } 4381 4382 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4383 { 4384 int r, i; 4385 struct amdgpu_ring *ring; 4386 4387 if (!(adev->flags & AMD_IS_APU)) 4388 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4389 4390 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4391 /* legacy firmware loading */ 4392 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4393 if (r) 4394 return r; 4395 4396 if (adev->gfx.rs64_enable) 4397 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4398 else 4399 r = gfx_v11_0_cp_compute_load_microcode(adev); 4400 if (r) 4401 return r; 4402 } 4403 4404 gfx_v11_0_cp_set_doorbell_range(adev); 4405 4406 if (amdgpu_async_gfx_ring) { 4407 gfx_v11_0_cp_compute_enable(adev, true); 4408 gfx_v11_0_cp_gfx_enable(adev, true); 4409 } 4410 4411 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4412 r = amdgpu_mes_kiq_hw_init(adev); 4413 else 4414 r = gfx_v11_0_kiq_resume(adev); 4415 if (r) 4416 return r; 4417 4418 r = gfx_v11_0_kcq_resume(adev); 4419 if (r) 4420 return r; 4421 4422 if (!amdgpu_async_gfx_ring) { 4423 r = gfx_v11_0_cp_gfx_resume(adev); 4424 if (r) 4425 return r; 4426 } else { 4427 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4428 if (r) 4429 return r; 4430 } 4431 4432 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4433 ring = &adev->gfx.gfx_ring[i]; 4434 r = amdgpu_ring_test_helper(ring); 4435 if (r) 4436 return r; 4437 } 4438 4439 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4440 ring = &adev->gfx.compute_ring[i]; 4441 r = amdgpu_ring_test_helper(ring); 4442 if (r) 4443 return r; 4444 } 4445 4446 return 0; 4447 } 4448 4449 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4450 { 4451 gfx_v11_0_cp_gfx_enable(adev, enable); 4452 gfx_v11_0_cp_compute_enable(adev, enable); 4453 } 4454 4455 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4456 { 4457 int r; 4458 bool value; 4459 4460 r = adev->gfxhub.funcs->gart_enable(adev); 4461 if (r) 4462 return r; 4463 4464 adev->hdp.funcs->flush_hdp(adev, NULL); 4465 4466 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4467 false : true; 4468 4469 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4470 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 4471 4472 return 0; 4473 } 4474 4475 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4476 { 4477 u32 tmp; 4478 4479 /* select RS64 */ 4480 if (adev->gfx.rs64_enable) { 4481 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4482 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4483 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4484 4485 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4486 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4487 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4488 } 4489 4490 if (amdgpu_emu_mode == 1) 4491 msleep(100); 4492 } 4493 4494 static int get_gb_addr_config(struct amdgpu_device * adev) 4495 { 4496 u32 gb_addr_config; 4497 4498 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4499 if (gb_addr_config == 0) 4500 return -EINVAL; 4501 4502 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4503 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4504 4505 adev->gfx.config.gb_addr_config = gb_addr_config; 4506 4507 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4508 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4509 GB_ADDR_CONFIG, NUM_PIPES); 4510 4511 adev->gfx.config.max_tile_pipes = 4512 adev->gfx.config.gb_addr_config_fields.num_pipes; 4513 4514 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4515 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4516 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4517 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4518 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4519 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4520 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4521 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4522 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4523 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4524 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4525 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4526 4527 return 0; 4528 } 4529 4530 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4531 { 4532 uint32_t data; 4533 4534 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4535 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4536 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4537 4538 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4539 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4540 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4541 } 4542 4543 static int gfx_v11_0_hw_init(void *handle) 4544 { 4545 int r; 4546 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4547 4548 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4549 if (adev->gfx.imu.funcs) { 4550 /* RLC autoload sequence 1: Program rlc ram */ 4551 if (adev->gfx.imu.funcs->program_rlc_ram) 4552 adev->gfx.imu.funcs->program_rlc_ram(adev); 4553 } 4554 /* rlc autoload firmware */ 4555 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4556 if (r) 4557 return r; 4558 } else { 4559 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4560 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4561 if (adev->gfx.imu.funcs->load_microcode) 4562 adev->gfx.imu.funcs->load_microcode(adev); 4563 if (adev->gfx.imu.funcs->setup_imu) 4564 adev->gfx.imu.funcs->setup_imu(adev); 4565 if (adev->gfx.imu.funcs->start_imu) 4566 adev->gfx.imu.funcs->start_imu(adev); 4567 } 4568 4569 /* disable gpa mode in backdoor loading */ 4570 gfx_v11_0_disable_gpa_mode(adev); 4571 } 4572 } 4573 4574 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4575 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4576 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4577 if (r) { 4578 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4579 return r; 4580 } 4581 } 4582 4583 adev->gfx.is_poweron = true; 4584 4585 if(get_gb_addr_config(adev)) 4586 DRM_WARN("Invalid gb_addr_config !\n"); 4587 4588 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4589 adev->gfx.rs64_enable) 4590 gfx_v11_0_config_gfx_rs64(adev); 4591 4592 r = gfx_v11_0_gfxhub_enable(adev); 4593 if (r) 4594 return r; 4595 4596 if (!amdgpu_emu_mode) 4597 gfx_v11_0_init_golden_registers(adev); 4598 4599 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4600 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4601 /** 4602 * For gfx 11, rlc firmware loading relies on smu firmware is 4603 * loaded firstly, so in direct type, it has to load smc ucode 4604 * here before rlc. 4605 */ 4606 if (!(adev->flags & AMD_IS_APU)) { 4607 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4608 if (r) 4609 return r; 4610 } 4611 } 4612 4613 gfx_v11_0_constants_init(adev); 4614 4615 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4616 gfx_v11_0_select_cp_fw_arch(adev); 4617 4618 if (adev->nbio.funcs->gc_doorbell_init) 4619 adev->nbio.funcs->gc_doorbell_init(adev); 4620 4621 r = gfx_v11_0_rlc_resume(adev); 4622 if (r) 4623 return r; 4624 4625 /* 4626 * init golden registers and rlc resume may override some registers, 4627 * reconfig them here 4628 */ 4629 gfx_v11_0_tcp_harvest(adev); 4630 4631 r = gfx_v11_0_cp_resume(adev); 4632 if (r) 4633 return r; 4634 4635 return r; 4636 } 4637 4638 #ifndef BRING_UP_DEBUG 4639 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev) 4640 { 4641 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4642 struct amdgpu_ring *kiq_ring = &kiq->ring; 4643 int i, r = 0; 4644 4645 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4646 return -EINVAL; 4647 4648 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 4649 adev->gfx.num_gfx_rings)) 4650 return -ENOMEM; 4651 4652 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4653 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 4654 PREEMPT_QUEUES, 0, 0); 4655 4656 if (adev->gfx.kiq.ring.sched.ready) 4657 r = amdgpu_ring_test_helper(kiq_ring); 4658 4659 return r; 4660 } 4661 #endif 4662 4663 static int gfx_v11_0_hw_fini(void *handle) 4664 { 4665 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4666 int r; 4667 uint32_t tmp; 4668 4669 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4670 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4671 4672 if (!adev->no_hw_access) { 4673 #ifndef BRING_UP_DEBUG 4674 if (amdgpu_async_gfx_ring) { 4675 r = gfx_v11_0_kiq_disable_kgq(adev); 4676 if (r) 4677 DRM_ERROR("KGQ disable failed\n"); 4678 } 4679 #endif 4680 if (amdgpu_gfx_disable_kcq(adev)) 4681 DRM_ERROR("KCQ disable failed\n"); 4682 4683 amdgpu_mes_kiq_hw_fini(adev); 4684 } 4685 4686 if (amdgpu_sriov_vf(adev)) { 4687 gfx_v11_0_cp_gfx_enable(adev, false); 4688 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 4689 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 4690 tmp &= 0xffffff00; 4691 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 4692 4693 return 0; 4694 } 4695 gfx_v11_0_cp_enable(adev, false); 4696 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4697 4698 adev->gfxhub.funcs->gart_disable(adev); 4699 4700 adev->gfx.is_poweron = false; 4701 4702 return 0; 4703 } 4704 4705 static int gfx_v11_0_suspend(void *handle) 4706 { 4707 return gfx_v11_0_hw_fini(handle); 4708 } 4709 4710 static int gfx_v11_0_resume(void *handle) 4711 { 4712 return gfx_v11_0_hw_init(handle); 4713 } 4714 4715 static bool gfx_v11_0_is_idle(void *handle) 4716 { 4717 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4718 4719 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4720 GRBM_STATUS, GUI_ACTIVE)) 4721 return false; 4722 else 4723 return true; 4724 } 4725 4726 static int gfx_v11_0_wait_for_idle(void *handle) 4727 { 4728 unsigned i; 4729 u32 tmp; 4730 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4731 4732 for (i = 0; i < adev->usec_timeout; i++) { 4733 /* read MC_STATUS */ 4734 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4735 GRBM_STATUS__GUI_ACTIVE_MASK; 4736 4737 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4738 return 0; 4739 udelay(1); 4740 } 4741 return -ETIMEDOUT; 4742 } 4743 4744 static int gfx_v11_0_soft_reset(void *handle) 4745 { 4746 u32 grbm_soft_reset = 0; 4747 u32 tmp; 4748 int i, j, k; 4749 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4750 4751 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4752 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4753 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4754 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4755 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4756 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4757 4758 gfx_v11_0_set_safe_mode(adev); 4759 4760 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4761 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4762 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4763 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4764 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4765 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4766 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4767 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4768 4769 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4770 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4771 } 4772 } 4773 } 4774 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4775 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4776 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4777 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4778 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4779 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4780 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4781 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4782 4783 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4784 } 4785 } 4786 } 4787 4788 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4789 4790 // Read CP_VMID_RESET register three times. 4791 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4792 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4793 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4794 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4795 4796 for (i = 0; i < adev->usec_timeout; i++) { 4797 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4798 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4799 break; 4800 udelay(1); 4801 } 4802 if (i >= adev->usec_timeout) { 4803 printk("Failed to wait all pipes clean\n"); 4804 return -EINVAL; 4805 } 4806 4807 /********** trigger soft reset ***********/ 4808 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4809 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4810 SOFT_RESET_CP, 1); 4811 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4812 SOFT_RESET_GFX, 1); 4813 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4814 SOFT_RESET_CPF, 1); 4815 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4816 SOFT_RESET_CPC, 1); 4817 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4818 SOFT_RESET_CPG, 1); 4819 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4820 /********** exit soft reset ***********/ 4821 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4822 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4823 SOFT_RESET_CP, 0); 4824 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4825 SOFT_RESET_GFX, 0); 4826 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4827 SOFT_RESET_CPF, 0); 4828 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4829 SOFT_RESET_CPC, 0); 4830 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4831 SOFT_RESET_CPG, 0); 4832 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4833 4834 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4835 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4836 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4837 4838 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4839 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4840 4841 for (i = 0; i < adev->usec_timeout; i++) { 4842 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4843 break; 4844 udelay(1); 4845 } 4846 if (i >= adev->usec_timeout) { 4847 printk("Failed to wait CP_VMID_RESET to 0\n"); 4848 return -EINVAL; 4849 } 4850 4851 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4852 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4853 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4854 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4855 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4856 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4857 4858 gfx_v11_0_unset_safe_mode(adev); 4859 4860 return gfx_v11_0_cp_resume(adev); 4861 } 4862 4863 static bool gfx_v11_0_check_soft_reset(void *handle) 4864 { 4865 int i, r; 4866 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4867 struct amdgpu_ring *ring; 4868 long tmo = msecs_to_jiffies(1000); 4869 4870 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4871 ring = &adev->gfx.gfx_ring[i]; 4872 r = amdgpu_ring_test_ib(ring, tmo); 4873 if (r) 4874 return true; 4875 } 4876 4877 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4878 ring = &adev->gfx.compute_ring[i]; 4879 r = amdgpu_ring_test_ib(ring, tmo); 4880 if (r) 4881 return true; 4882 } 4883 4884 return false; 4885 } 4886 4887 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4888 { 4889 uint64_t clock; 4890 4891 amdgpu_gfx_off_ctrl(adev, false); 4892 mutex_lock(&adev->gfx.gpu_clock_mutex); 4893 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) | 4894 ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL); 4895 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4896 amdgpu_gfx_off_ctrl(adev, true); 4897 return clock; 4898 } 4899 4900 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4901 uint32_t vmid, 4902 uint32_t gds_base, uint32_t gds_size, 4903 uint32_t gws_base, uint32_t gws_size, 4904 uint32_t oa_base, uint32_t oa_size) 4905 { 4906 struct amdgpu_device *adev = ring->adev; 4907 4908 /* GDS Base */ 4909 gfx_v11_0_write_data_to_reg(ring, 0, false, 4910 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4911 gds_base); 4912 4913 /* GDS Size */ 4914 gfx_v11_0_write_data_to_reg(ring, 0, false, 4915 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4916 gds_size); 4917 4918 /* GWS */ 4919 gfx_v11_0_write_data_to_reg(ring, 0, false, 4920 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4921 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4922 4923 /* OA */ 4924 gfx_v11_0_write_data_to_reg(ring, 0, false, 4925 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4926 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4927 } 4928 4929 static int gfx_v11_0_early_init(void *handle) 4930 { 4931 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4932 4933 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4934 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4935 AMDGPU_MAX_COMPUTE_RINGS); 4936 4937 gfx_v11_0_set_kiq_pm4_funcs(adev); 4938 gfx_v11_0_set_ring_funcs(adev); 4939 gfx_v11_0_set_irq_funcs(adev); 4940 gfx_v11_0_set_gds_init(adev); 4941 gfx_v11_0_set_rlc_funcs(adev); 4942 gfx_v11_0_set_mqd_funcs(adev); 4943 gfx_v11_0_set_imu_funcs(adev); 4944 4945 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4946 4947 return 0; 4948 } 4949 4950 static int gfx_v11_0_late_init(void *handle) 4951 { 4952 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4953 int r; 4954 4955 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4956 if (r) 4957 return r; 4958 4959 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4960 if (r) 4961 return r; 4962 4963 return 0; 4964 } 4965 4966 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4967 { 4968 uint32_t rlc_cntl; 4969 4970 /* if RLC is not enabled, do nothing */ 4971 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4972 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4973 } 4974 4975 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev) 4976 { 4977 uint32_t data; 4978 unsigned i; 4979 4980 data = RLC_SAFE_MODE__CMD_MASK; 4981 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4982 4983 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4984 4985 /* wait for RLC_SAFE_MODE */ 4986 for (i = 0; i < adev->usec_timeout; i++) { 4987 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4988 RLC_SAFE_MODE, CMD)) 4989 break; 4990 udelay(1); 4991 } 4992 } 4993 4994 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev) 4995 { 4996 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4997 } 4998 4999 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 5000 bool enable) 5001 { 5002 uint32_t def, data; 5003 5004 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 5005 return; 5006 5007 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5008 5009 if (enable) 5010 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5011 else 5012 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 5013 5014 if (def != data) 5015 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5016 } 5017 5018 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 5019 bool enable) 5020 { 5021 uint32_t def, data; 5022 5023 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 5024 return; 5025 5026 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5027 5028 if (enable) 5029 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5030 else 5031 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 5032 5033 if (def != data) 5034 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5035 } 5036 5037 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 5038 bool enable) 5039 { 5040 uint32_t def, data; 5041 5042 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 5043 return; 5044 5045 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5046 5047 if (enable) 5048 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5049 else 5050 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 5051 5052 if (def != data) 5053 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5054 } 5055 5056 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5057 bool enable) 5058 { 5059 uint32_t data, def; 5060 5061 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 5062 return; 5063 5064 /* It is disabled by HW by default */ 5065 if (enable) { 5066 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5067 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 5068 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5069 5070 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5071 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5072 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5073 5074 if (def != data) 5075 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5076 } 5077 } else { 5078 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 5079 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5080 5081 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 5082 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 5083 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 5084 5085 if (def != data) 5086 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5087 } 5088 } 5089 } 5090 5091 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5092 bool enable) 5093 { 5094 uint32_t def, data; 5095 5096 if (!(adev->cg_flags & 5097 (AMD_CG_SUPPORT_GFX_CGCG | 5098 AMD_CG_SUPPORT_GFX_CGLS | 5099 AMD_CG_SUPPORT_GFX_3D_CGCG | 5100 AMD_CG_SUPPORT_GFX_3D_CGLS))) 5101 return; 5102 5103 if (enable) { 5104 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5105 5106 /* unset CGCG override */ 5107 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5108 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 5109 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5110 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 5111 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 5112 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5113 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 5114 5115 /* update CGCG override bits */ 5116 if (def != data) 5117 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 5118 5119 /* enable cgcg FSM(0x0000363F) */ 5120 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5121 5122 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 5123 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 5124 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5125 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5126 } 5127 5128 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5129 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 5130 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5131 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5132 } 5133 5134 if (def != data) 5135 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5136 5137 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5138 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5139 5140 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 5141 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 5142 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 5143 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5144 } 5145 5146 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 5147 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 5148 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 5149 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5150 } 5151 5152 if (def != data) 5153 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5154 5155 /* set IDLE_POLL_COUNT(0x00900100) */ 5156 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 5157 5158 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 5159 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 5160 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 5161 5162 if (def != data) 5163 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 5164 5165 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 5166 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5167 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5168 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5169 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5170 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5171 5172 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5173 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5174 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5175 5176 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5177 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5178 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5179 } else { 5180 /* Program RLC_CGCG_CGLS_CTRL */ 5181 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5182 5183 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5184 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5185 5186 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5187 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5188 5189 if (def != data) 5190 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5191 5192 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5193 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5194 5195 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5196 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5197 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5198 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5199 5200 if (def != data) 5201 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5202 5203 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5204 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5205 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5206 5207 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5208 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5209 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5210 } 5211 } 5212 5213 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5214 bool enable) 5215 { 5216 amdgpu_gfx_rlc_enter_safe_mode(adev); 5217 5218 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5219 5220 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5221 5222 gfx_v11_0_update_repeater_fgcg(adev, enable); 5223 5224 gfx_v11_0_update_sram_fgcg(adev, enable); 5225 5226 gfx_v11_0_update_perf_clk(adev, enable); 5227 5228 if (adev->cg_flags & 5229 (AMD_CG_SUPPORT_GFX_MGCG | 5230 AMD_CG_SUPPORT_GFX_CGLS | 5231 AMD_CG_SUPPORT_GFX_CGCG | 5232 AMD_CG_SUPPORT_GFX_3D_CGCG | 5233 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5234 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5235 5236 amdgpu_gfx_rlc_exit_safe_mode(adev); 5237 5238 return 0; 5239 } 5240 5241 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 5242 { 5243 u32 reg, data; 5244 5245 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5246 if (amdgpu_sriov_is_pp_one_vf(adev)) 5247 data = RREG32_NO_KIQ(reg); 5248 else 5249 data = RREG32(reg); 5250 5251 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5252 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5253 5254 if (amdgpu_sriov_is_pp_one_vf(adev)) 5255 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5256 else 5257 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5258 } 5259 5260 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5261 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5262 .set_safe_mode = gfx_v11_0_set_safe_mode, 5263 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5264 .init = gfx_v11_0_rlc_init, 5265 .get_csb_size = gfx_v11_0_get_csb_size, 5266 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5267 .resume = gfx_v11_0_rlc_resume, 5268 .stop = gfx_v11_0_rlc_stop, 5269 .reset = gfx_v11_0_rlc_reset, 5270 .start = gfx_v11_0_rlc_start, 5271 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5272 }; 5273 5274 static int gfx_v11_0_set_powergating_state(void *handle, 5275 enum amd_powergating_state state) 5276 { 5277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5278 bool enable = (state == AMD_PG_STATE_GATE); 5279 5280 if (amdgpu_sriov_vf(adev)) 5281 return 0; 5282 5283 switch (adev->ip_versions[GC_HWIP][0]) { 5284 case IP_VERSION(11, 0, 0): 5285 case IP_VERSION(11, 0, 2): 5286 amdgpu_gfx_off_ctrl(adev, enable); 5287 break; 5288 default: 5289 break; 5290 } 5291 5292 return 0; 5293 } 5294 5295 static int gfx_v11_0_set_clockgating_state(void *handle, 5296 enum amd_clockgating_state state) 5297 { 5298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5299 5300 if (amdgpu_sriov_vf(adev)) 5301 return 0; 5302 5303 switch (adev->ip_versions[GC_HWIP][0]) { 5304 case IP_VERSION(11, 0, 0): 5305 case IP_VERSION(11, 0, 2): 5306 gfx_v11_0_update_gfx_clock_gating(adev, 5307 state == AMD_CG_STATE_GATE); 5308 break; 5309 default: 5310 break; 5311 } 5312 5313 return 0; 5314 } 5315 5316 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5317 { 5318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5319 int data; 5320 5321 /* AMD_CG_SUPPORT_GFX_MGCG */ 5322 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5323 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5324 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5325 5326 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5327 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5328 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5329 5330 /* AMD_CG_SUPPORT_GFX_FGCG */ 5331 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5332 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5333 5334 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5335 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5336 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5337 5338 /* AMD_CG_SUPPORT_GFX_CGCG */ 5339 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5340 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5341 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5342 5343 /* AMD_CG_SUPPORT_GFX_CGLS */ 5344 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5345 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5346 5347 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5348 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5349 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5350 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5351 5352 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5353 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5354 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5355 } 5356 5357 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5358 { 5359 /* gfx11 is 32bit rptr*/ 5360 return *(uint32_t *)ring->rptr_cpu_addr; 5361 } 5362 5363 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5364 { 5365 struct amdgpu_device *adev = ring->adev; 5366 u64 wptr; 5367 5368 /* XXX check if swapping is necessary on BE */ 5369 if (ring->use_doorbell) { 5370 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5371 } else { 5372 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5373 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5374 } 5375 5376 return wptr; 5377 } 5378 5379 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5380 { 5381 struct amdgpu_device *adev = ring->adev; 5382 uint32_t *wptr_saved; 5383 uint32_t *is_queue_unmap; 5384 uint64_t aggregated_db_index; 5385 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 5386 uint64_t wptr_tmp; 5387 5388 if (ring->is_mes_queue) { 5389 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5390 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5391 sizeof(uint32_t)); 5392 aggregated_db_index = 5393 amdgpu_mes_get_aggregated_doorbell_index(adev, 5394 ring->hw_prio); 5395 5396 wptr_tmp = ring->wptr & ring->buf_mask; 5397 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5398 *wptr_saved = wptr_tmp; 5399 /* assume doorbell always being used by mes mapped queue */ 5400 if (*is_queue_unmap) { 5401 WDOORBELL64(aggregated_db_index, wptr_tmp); 5402 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5403 } else { 5404 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5405 5406 if (*is_queue_unmap) 5407 WDOORBELL64(aggregated_db_index, wptr_tmp); 5408 } 5409 } else { 5410 if (ring->use_doorbell) { 5411 /* XXX check if swapping is necessary on BE */ 5412 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5413 ring->wptr); 5414 WDOORBELL64(ring->doorbell_index, ring->wptr); 5415 } else { 5416 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5417 lower_32_bits(ring->wptr)); 5418 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5419 upper_32_bits(ring->wptr)); 5420 } 5421 } 5422 } 5423 5424 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5425 { 5426 /* gfx11 hardware is 32bit rptr */ 5427 return *(uint32_t *)ring->rptr_cpu_addr; 5428 } 5429 5430 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5431 { 5432 u64 wptr; 5433 5434 /* XXX check if swapping is necessary on BE */ 5435 if (ring->use_doorbell) 5436 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5437 else 5438 BUG(); 5439 return wptr; 5440 } 5441 5442 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5443 { 5444 struct amdgpu_device *adev = ring->adev; 5445 uint32_t *wptr_saved; 5446 uint32_t *is_queue_unmap; 5447 uint64_t aggregated_db_index; 5448 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 5449 uint64_t wptr_tmp; 5450 5451 if (ring->is_mes_queue) { 5452 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5453 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5454 sizeof(uint32_t)); 5455 aggregated_db_index = 5456 amdgpu_mes_get_aggregated_doorbell_index(adev, 5457 ring->hw_prio); 5458 5459 wptr_tmp = ring->wptr & ring->buf_mask; 5460 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5461 *wptr_saved = wptr_tmp; 5462 /* assume doorbell always used by mes mapped queue */ 5463 if (*is_queue_unmap) { 5464 WDOORBELL64(aggregated_db_index, wptr_tmp); 5465 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5466 } else { 5467 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5468 5469 if (*is_queue_unmap) 5470 WDOORBELL64(aggregated_db_index, wptr_tmp); 5471 } 5472 } else { 5473 /* XXX check if swapping is necessary on BE */ 5474 if (ring->use_doorbell) { 5475 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5476 ring->wptr); 5477 WDOORBELL64(ring->doorbell_index, ring->wptr); 5478 } else { 5479 BUG(); /* only DOORBELL method supported on gfx11 now */ 5480 } 5481 } 5482 } 5483 5484 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5485 { 5486 struct amdgpu_device *adev = ring->adev; 5487 u32 ref_and_mask, reg_mem_engine; 5488 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5489 5490 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5491 switch (ring->me) { 5492 case 1: 5493 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5494 break; 5495 case 2: 5496 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5497 break; 5498 default: 5499 return; 5500 } 5501 reg_mem_engine = 0; 5502 } else { 5503 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5504 reg_mem_engine = 1; /* pfp */ 5505 } 5506 5507 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5508 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5509 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5510 ref_and_mask, ref_and_mask, 0x20); 5511 } 5512 5513 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5514 struct amdgpu_job *job, 5515 struct amdgpu_ib *ib, 5516 uint32_t flags) 5517 { 5518 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5519 u32 header, control = 0; 5520 5521 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5522 5523 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5524 5525 control |= ib->length_dw | (vmid << 24); 5526 5527 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5528 control |= INDIRECT_BUFFER_PRE_ENB(1); 5529 5530 if (flags & AMDGPU_IB_PREEMPTED) 5531 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5532 5533 if (vmid) 5534 gfx_v11_0_ring_emit_de_meta(ring, 5535 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5536 } 5537 5538 if (ring->is_mes_queue) 5539 /* inherit vmid from mqd */ 5540 control |= 0x400000; 5541 5542 amdgpu_ring_write(ring, header); 5543 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5544 amdgpu_ring_write(ring, 5545 #ifdef __BIG_ENDIAN 5546 (2 << 0) | 5547 #endif 5548 lower_32_bits(ib->gpu_addr)); 5549 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5550 amdgpu_ring_write(ring, control); 5551 } 5552 5553 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5554 struct amdgpu_job *job, 5555 struct amdgpu_ib *ib, 5556 uint32_t flags) 5557 { 5558 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5559 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5560 5561 if (ring->is_mes_queue) 5562 /* inherit vmid from mqd */ 5563 control |= 0x40000000; 5564 5565 /* Currently, there is a high possibility to get wave ID mismatch 5566 * between ME and GDS, leading to a hw deadlock, because ME generates 5567 * different wave IDs than the GDS expects. This situation happens 5568 * randomly when at least 5 compute pipes use GDS ordered append. 5569 * The wave IDs generated by ME are also wrong after suspend/resume. 5570 * Those are probably bugs somewhere else in the kernel driver. 5571 * 5572 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5573 * GDS to 0 for this ring (me/pipe). 5574 */ 5575 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5576 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5577 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5578 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5579 } 5580 5581 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5582 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5583 amdgpu_ring_write(ring, 5584 #ifdef __BIG_ENDIAN 5585 (2 << 0) | 5586 #endif 5587 lower_32_bits(ib->gpu_addr)); 5588 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5589 amdgpu_ring_write(ring, control); 5590 } 5591 5592 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5593 u64 seq, unsigned flags) 5594 { 5595 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5596 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5597 5598 /* RELEASE_MEM - flush caches, send int */ 5599 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5600 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5601 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5602 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5603 PACKET3_RELEASE_MEM_GCR_GL2_US | 5604 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5605 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5606 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5607 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5608 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5609 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5610 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5611 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5612 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5613 5614 /* 5615 * the address should be Qword aligned if 64bit write, Dword 5616 * aligned if only send 32bit data low (discard data high) 5617 */ 5618 if (write64bit) 5619 BUG_ON(addr & 0x7); 5620 else 5621 BUG_ON(addr & 0x3); 5622 amdgpu_ring_write(ring, lower_32_bits(addr)); 5623 amdgpu_ring_write(ring, upper_32_bits(addr)); 5624 amdgpu_ring_write(ring, lower_32_bits(seq)); 5625 amdgpu_ring_write(ring, upper_32_bits(seq)); 5626 amdgpu_ring_write(ring, ring->is_mes_queue ? 5627 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5628 } 5629 5630 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5631 { 5632 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5633 uint32_t seq = ring->fence_drv.sync_seq; 5634 uint64_t addr = ring->fence_drv.gpu_addr; 5635 5636 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5637 upper_32_bits(addr), seq, 0xffffffff, 4); 5638 } 5639 5640 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5641 uint16_t pasid, uint32_t flush_type, 5642 bool all_hub, uint8_t dst_sel) 5643 { 5644 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5645 amdgpu_ring_write(ring, 5646 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5647 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5648 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5649 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5650 } 5651 5652 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5653 unsigned vmid, uint64_t pd_addr) 5654 { 5655 if (ring->is_mes_queue) 5656 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5657 else 5658 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5659 5660 /* compute doesn't have PFP */ 5661 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5662 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5663 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5664 amdgpu_ring_write(ring, 0x0); 5665 } 5666 } 5667 5668 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5669 u64 seq, unsigned int flags) 5670 { 5671 struct amdgpu_device *adev = ring->adev; 5672 5673 /* we only allocate 32bit for each seq wb address */ 5674 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5675 5676 /* write fence seq to the "addr" */ 5677 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5678 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5679 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5680 amdgpu_ring_write(ring, lower_32_bits(addr)); 5681 amdgpu_ring_write(ring, upper_32_bits(addr)); 5682 amdgpu_ring_write(ring, lower_32_bits(seq)); 5683 5684 if (flags & AMDGPU_FENCE_FLAG_INT) { 5685 /* set register to trigger INT */ 5686 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5687 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5688 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5689 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5690 amdgpu_ring_write(ring, 0); 5691 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5692 } 5693 } 5694 5695 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5696 uint32_t flags) 5697 { 5698 uint32_t dw2 = 0; 5699 5700 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5701 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5702 /* set load_global_config & load_global_uconfig */ 5703 dw2 |= 0x8001; 5704 /* set load_cs_sh_regs */ 5705 dw2 |= 0x01000000; 5706 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5707 dw2 |= 0x10002; 5708 } 5709 5710 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5711 amdgpu_ring_write(ring, dw2); 5712 amdgpu_ring_write(ring, 0); 5713 } 5714 5715 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5716 { 5717 unsigned ret; 5718 5719 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5720 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5721 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5722 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5723 ret = ring->wptr & ring->buf_mask; 5724 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5725 5726 return ret; 5727 } 5728 5729 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5730 { 5731 unsigned cur; 5732 BUG_ON(offset > ring->buf_mask); 5733 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5734 5735 cur = (ring->wptr - 1) & ring->buf_mask; 5736 if (likely(cur > offset)) 5737 ring->ring[offset] = cur - offset; 5738 else 5739 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5740 } 5741 5742 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5743 { 5744 int i, r = 0; 5745 struct amdgpu_device *adev = ring->adev; 5746 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5747 struct amdgpu_ring *kiq_ring = &kiq->ring; 5748 unsigned long flags; 5749 5750 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5751 return -EINVAL; 5752 5753 spin_lock_irqsave(&kiq->ring_lock, flags); 5754 5755 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5756 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5757 return -ENOMEM; 5758 } 5759 5760 /* assert preemption condition */ 5761 amdgpu_ring_set_preempt_cond_exec(ring, false); 5762 5763 /* assert IB preemption, emit the trailing fence */ 5764 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5765 ring->trail_fence_gpu_addr, 5766 ++ring->trail_seq); 5767 amdgpu_ring_commit(kiq_ring); 5768 5769 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5770 5771 /* poll the trailing fence */ 5772 for (i = 0; i < adev->usec_timeout; i++) { 5773 if (ring->trail_seq == 5774 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5775 break; 5776 udelay(1); 5777 } 5778 5779 if (i >= adev->usec_timeout) { 5780 r = -EINVAL; 5781 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5782 } 5783 5784 /* deassert preemption condition */ 5785 amdgpu_ring_set_preempt_cond_exec(ring, true); 5786 return r; 5787 } 5788 5789 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5790 { 5791 struct amdgpu_device *adev = ring->adev; 5792 struct v10_de_ib_state de_payload = {0}; 5793 uint64_t offset, gds_addr, de_payload_gpu_addr; 5794 void *de_payload_cpu_addr; 5795 int cnt; 5796 5797 if (ring->is_mes_queue) { 5798 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5799 gfx[0].gfx_meta_data) + 5800 offsetof(struct v10_gfx_meta_data, de_payload); 5801 de_payload_gpu_addr = 5802 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5803 de_payload_cpu_addr = 5804 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5805 5806 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5807 gfx[0].gds_backup) + 5808 offsetof(struct v10_gfx_meta_data, de_payload); 5809 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5810 } else { 5811 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5812 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5813 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5814 5815 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5816 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5817 PAGE_SIZE); 5818 } 5819 5820 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5821 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5822 5823 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5824 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5825 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5826 WRITE_DATA_DST_SEL(8) | 5827 WR_CONFIRM) | 5828 WRITE_DATA_CACHE_POLICY(0)); 5829 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5830 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5831 5832 if (resume) 5833 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5834 sizeof(de_payload) >> 2); 5835 else 5836 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5837 sizeof(de_payload) >> 2); 5838 } 5839 5840 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5841 bool secure) 5842 { 5843 uint32_t v = secure ? FRAME_TMZ : 0; 5844 5845 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5846 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5847 } 5848 5849 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5850 uint32_t reg_val_offs) 5851 { 5852 struct amdgpu_device *adev = ring->adev; 5853 5854 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5855 amdgpu_ring_write(ring, 0 | /* src: register*/ 5856 (5 << 8) | /* dst: memory */ 5857 (1 << 20)); /* write confirm */ 5858 amdgpu_ring_write(ring, reg); 5859 amdgpu_ring_write(ring, 0); 5860 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5861 reg_val_offs * 4)); 5862 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5863 reg_val_offs * 4)); 5864 } 5865 5866 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5867 uint32_t val) 5868 { 5869 uint32_t cmd = 0; 5870 5871 switch (ring->funcs->type) { 5872 case AMDGPU_RING_TYPE_GFX: 5873 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5874 break; 5875 case AMDGPU_RING_TYPE_KIQ: 5876 cmd = (1 << 16); /* no inc addr */ 5877 break; 5878 default: 5879 cmd = WR_CONFIRM; 5880 break; 5881 } 5882 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5883 amdgpu_ring_write(ring, cmd); 5884 amdgpu_ring_write(ring, reg); 5885 amdgpu_ring_write(ring, 0); 5886 amdgpu_ring_write(ring, val); 5887 } 5888 5889 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5890 uint32_t val, uint32_t mask) 5891 { 5892 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5893 } 5894 5895 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5896 uint32_t reg0, uint32_t reg1, 5897 uint32_t ref, uint32_t mask) 5898 { 5899 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5900 5901 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5902 ref, mask, 0x20); 5903 } 5904 5905 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5906 unsigned vmid) 5907 { 5908 struct amdgpu_device *adev = ring->adev; 5909 uint32_t value = 0; 5910 5911 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5912 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5913 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5914 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5915 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5916 } 5917 5918 static void 5919 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5920 uint32_t me, uint32_t pipe, 5921 enum amdgpu_interrupt_state state) 5922 { 5923 uint32_t cp_int_cntl, cp_int_cntl_reg; 5924 5925 if (!me) { 5926 switch (pipe) { 5927 case 0: 5928 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5929 break; 5930 case 1: 5931 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5932 break; 5933 default: 5934 DRM_DEBUG("invalid pipe %d\n", pipe); 5935 return; 5936 } 5937 } else { 5938 DRM_DEBUG("invalid me %d\n", me); 5939 return; 5940 } 5941 5942 switch (state) { 5943 case AMDGPU_IRQ_STATE_DISABLE: 5944 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5945 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5946 TIME_STAMP_INT_ENABLE, 0); 5947 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5948 GENERIC0_INT_ENABLE, 0); 5949 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5950 break; 5951 case AMDGPU_IRQ_STATE_ENABLE: 5952 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5953 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5954 TIME_STAMP_INT_ENABLE, 1); 5955 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5956 GENERIC0_INT_ENABLE, 1); 5957 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5958 break; 5959 default: 5960 break; 5961 } 5962 } 5963 5964 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5965 int me, int pipe, 5966 enum amdgpu_interrupt_state state) 5967 { 5968 u32 mec_int_cntl, mec_int_cntl_reg; 5969 5970 /* 5971 * amdgpu controls only the first MEC. That's why this function only 5972 * handles the setting of interrupts for this specific MEC. All other 5973 * pipes' interrupts are set by amdkfd. 5974 */ 5975 5976 if (me == 1) { 5977 switch (pipe) { 5978 case 0: 5979 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5980 break; 5981 case 1: 5982 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5983 break; 5984 case 2: 5985 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5986 break; 5987 case 3: 5988 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5989 break; 5990 default: 5991 DRM_DEBUG("invalid pipe %d\n", pipe); 5992 return; 5993 } 5994 } else { 5995 DRM_DEBUG("invalid me %d\n", me); 5996 return; 5997 } 5998 5999 switch (state) { 6000 case AMDGPU_IRQ_STATE_DISABLE: 6001 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6002 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6003 TIME_STAMP_INT_ENABLE, 0); 6004 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6005 GENERIC0_INT_ENABLE, 0); 6006 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6007 break; 6008 case AMDGPU_IRQ_STATE_ENABLE: 6009 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6010 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6011 TIME_STAMP_INT_ENABLE, 1); 6012 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 6013 GENERIC0_INT_ENABLE, 1); 6014 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 6015 break; 6016 default: 6017 break; 6018 } 6019 } 6020 6021 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6022 struct amdgpu_irq_src *src, 6023 unsigned type, 6024 enum amdgpu_interrupt_state state) 6025 { 6026 switch (type) { 6027 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 6028 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 6029 break; 6030 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 6031 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 6032 break; 6033 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6034 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6035 break; 6036 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6037 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6038 break; 6039 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6040 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6041 break; 6042 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6043 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6044 break; 6045 default: 6046 break; 6047 } 6048 return 0; 6049 } 6050 6051 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 6052 struct amdgpu_irq_src *source, 6053 struct amdgpu_iv_entry *entry) 6054 { 6055 int i; 6056 u8 me_id, pipe_id, queue_id; 6057 struct amdgpu_ring *ring; 6058 uint32_t mes_queue_id = entry->src_data[0]; 6059 6060 DRM_DEBUG("IH: CP EOP\n"); 6061 6062 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 6063 struct amdgpu_mes_queue *queue; 6064 6065 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 6066 6067 spin_lock(&adev->mes.queue_id_lock); 6068 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 6069 if (queue) { 6070 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 6071 amdgpu_fence_process(queue->ring); 6072 } 6073 spin_unlock(&adev->mes.queue_id_lock); 6074 } else { 6075 me_id = (entry->ring_id & 0x0c) >> 2; 6076 pipe_id = (entry->ring_id & 0x03) >> 0; 6077 queue_id = (entry->ring_id & 0x70) >> 4; 6078 6079 switch (me_id) { 6080 case 0: 6081 if (pipe_id == 0) 6082 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6083 else 6084 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 6085 break; 6086 case 1: 6087 case 2: 6088 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6089 ring = &adev->gfx.compute_ring[i]; 6090 /* Per-queue interrupt is supported for MEC starting from VI. 6091 * The interrupt can only be enabled/disabled per pipe instead 6092 * of per queue. 6093 */ 6094 if ((ring->me == me_id) && 6095 (ring->pipe == pipe_id) && 6096 (ring->queue == queue_id)) 6097 amdgpu_fence_process(ring); 6098 } 6099 break; 6100 } 6101 } 6102 6103 return 0; 6104 } 6105 6106 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6107 struct amdgpu_irq_src *source, 6108 unsigned type, 6109 enum amdgpu_interrupt_state state) 6110 { 6111 switch (state) { 6112 case AMDGPU_IRQ_STATE_DISABLE: 6113 case AMDGPU_IRQ_STATE_ENABLE: 6114 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 6115 PRIV_REG_INT_ENABLE, 6116 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6117 break; 6118 default: 6119 break; 6120 } 6121 6122 return 0; 6123 } 6124 6125 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6126 struct amdgpu_irq_src *source, 6127 unsigned type, 6128 enum amdgpu_interrupt_state state) 6129 { 6130 switch (state) { 6131 case AMDGPU_IRQ_STATE_DISABLE: 6132 case AMDGPU_IRQ_STATE_ENABLE: 6133 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 6134 PRIV_INSTR_INT_ENABLE, 6135 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6136 break; 6137 default: 6138 break; 6139 } 6140 6141 return 0; 6142 } 6143 6144 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6145 struct amdgpu_iv_entry *entry) 6146 { 6147 u8 me_id, pipe_id, queue_id; 6148 struct amdgpu_ring *ring; 6149 int i; 6150 6151 me_id = (entry->ring_id & 0x0c) >> 2; 6152 pipe_id = (entry->ring_id & 0x03) >> 0; 6153 queue_id = (entry->ring_id & 0x70) >> 4; 6154 6155 switch (me_id) { 6156 case 0: 6157 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6158 ring = &adev->gfx.gfx_ring[i]; 6159 /* we only enabled 1 gfx queue per pipe for now */ 6160 if (ring->me == me_id && ring->pipe == pipe_id) 6161 drm_sched_fault(&ring->sched); 6162 } 6163 break; 6164 case 1: 6165 case 2: 6166 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6167 ring = &adev->gfx.compute_ring[i]; 6168 if (ring->me == me_id && ring->pipe == pipe_id && 6169 ring->queue == queue_id) 6170 drm_sched_fault(&ring->sched); 6171 } 6172 break; 6173 default: 6174 BUG(); 6175 break; 6176 } 6177 } 6178 6179 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6180 struct amdgpu_irq_src *source, 6181 struct amdgpu_iv_entry *entry) 6182 { 6183 DRM_ERROR("Illegal register access in command stream\n"); 6184 gfx_v11_0_handle_priv_fault(adev, entry); 6185 return 0; 6186 } 6187 6188 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6189 struct amdgpu_irq_src *source, 6190 struct amdgpu_iv_entry *entry) 6191 { 6192 DRM_ERROR("Illegal instruction in command stream\n"); 6193 gfx_v11_0_handle_priv_fault(adev, entry); 6194 return 0; 6195 } 6196 6197 #if 0 6198 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6199 struct amdgpu_irq_src *src, 6200 unsigned int type, 6201 enum amdgpu_interrupt_state state) 6202 { 6203 uint32_t tmp, target; 6204 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 6205 6206 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6207 target += ring->pipe; 6208 6209 switch (type) { 6210 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6211 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6212 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6213 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6214 GENERIC2_INT_ENABLE, 0); 6215 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6216 6217 tmp = RREG32_SOC15_IP(GC, target); 6218 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6219 GENERIC2_INT_ENABLE, 0); 6220 WREG32_SOC15_IP(GC, target, tmp); 6221 } else { 6222 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6223 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6224 GENERIC2_INT_ENABLE, 1); 6225 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6226 6227 tmp = RREG32_SOC15_IP(GC, target); 6228 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6229 GENERIC2_INT_ENABLE, 1); 6230 WREG32_SOC15_IP(GC, target, tmp); 6231 } 6232 break; 6233 default: 6234 BUG(); /* kiq only support GENERIC2_INT now */ 6235 break; 6236 } 6237 return 0; 6238 } 6239 #endif 6240 6241 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6242 { 6243 const unsigned int gcr_cntl = 6244 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6245 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6246 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6247 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6248 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6249 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6250 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6251 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6252 6253 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6254 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6255 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6256 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6257 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6258 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6259 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6260 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6261 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6262 } 6263 6264 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6265 .name = "gfx_v11_0", 6266 .early_init = gfx_v11_0_early_init, 6267 .late_init = gfx_v11_0_late_init, 6268 .sw_init = gfx_v11_0_sw_init, 6269 .sw_fini = gfx_v11_0_sw_fini, 6270 .hw_init = gfx_v11_0_hw_init, 6271 .hw_fini = gfx_v11_0_hw_fini, 6272 .suspend = gfx_v11_0_suspend, 6273 .resume = gfx_v11_0_resume, 6274 .is_idle = gfx_v11_0_is_idle, 6275 .wait_for_idle = gfx_v11_0_wait_for_idle, 6276 .soft_reset = gfx_v11_0_soft_reset, 6277 .check_soft_reset = gfx_v11_0_check_soft_reset, 6278 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6279 .set_powergating_state = gfx_v11_0_set_powergating_state, 6280 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6281 }; 6282 6283 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6284 .type = AMDGPU_RING_TYPE_GFX, 6285 .align_mask = 0xff, 6286 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6287 .support_64bit_ptrs = true, 6288 .vmhub = AMDGPU_GFXHUB_0, 6289 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6290 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6291 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6292 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6293 5 + /* COND_EXEC */ 6294 7 + /* PIPELINE_SYNC */ 6295 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6296 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6297 2 + /* VM_FLUSH */ 6298 8 + /* FENCE for VM_FLUSH */ 6299 20 + /* GDS switch */ 6300 5 + /* COND_EXEC */ 6301 7 + /* HDP_flush */ 6302 4 + /* VGT_flush */ 6303 31 + /* DE_META */ 6304 3 + /* CNTX_CTRL */ 6305 5 + /* HDP_INVL */ 6306 8 + 8 + /* FENCE x2 */ 6307 8, /* gfx_v11_0_emit_mem_sync */ 6308 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6309 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6310 .emit_fence = gfx_v11_0_ring_emit_fence, 6311 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6312 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6313 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6314 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6315 .test_ring = gfx_v11_0_ring_test_ring, 6316 .test_ib = gfx_v11_0_ring_test_ib, 6317 .insert_nop = amdgpu_ring_insert_nop, 6318 .pad_ib = amdgpu_ring_generic_pad_ib, 6319 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6320 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6321 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6322 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6323 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6324 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6325 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6326 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6327 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6328 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6329 }; 6330 6331 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6332 .type = AMDGPU_RING_TYPE_COMPUTE, 6333 .align_mask = 0xff, 6334 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6335 .support_64bit_ptrs = true, 6336 .vmhub = AMDGPU_GFXHUB_0, 6337 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6338 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6339 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6340 .emit_frame_size = 6341 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6342 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6343 5 + /* hdp invalidate */ 6344 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6345 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6346 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6347 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6348 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6349 8, /* gfx_v11_0_emit_mem_sync */ 6350 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6351 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6352 .emit_fence = gfx_v11_0_ring_emit_fence, 6353 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6354 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6355 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6356 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6357 .test_ring = gfx_v11_0_ring_test_ring, 6358 .test_ib = gfx_v11_0_ring_test_ib, 6359 .insert_nop = amdgpu_ring_insert_nop, 6360 .pad_ib = amdgpu_ring_generic_pad_ib, 6361 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6362 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6363 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6364 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6365 }; 6366 6367 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6368 .type = AMDGPU_RING_TYPE_KIQ, 6369 .align_mask = 0xff, 6370 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6371 .support_64bit_ptrs = true, 6372 .vmhub = AMDGPU_GFXHUB_0, 6373 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6374 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6375 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6376 .emit_frame_size = 6377 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6378 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6379 5 + /*hdp invalidate */ 6380 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6381 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6382 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6383 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6384 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6385 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6386 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6387 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6388 .test_ring = gfx_v11_0_ring_test_ring, 6389 .test_ib = gfx_v11_0_ring_test_ib, 6390 .insert_nop = amdgpu_ring_insert_nop, 6391 .pad_ib = amdgpu_ring_generic_pad_ib, 6392 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6393 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6394 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6395 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6396 }; 6397 6398 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6399 { 6400 int i; 6401 6402 adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6403 6404 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6405 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6406 6407 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6408 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6409 } 6410 6411 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6412 .set = gfx_v11_0_set_eop_interrupt_state, 6413 .process = gfx_v11_0_eop_irq, 6414 }; 6415 6416 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6417 .set = gfx_v11_0_set_priv_reg_fault_state, 6418 .process = gfx_v11_0_priv_reg_irq, 6419 }; 6420 6421 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6422 .set = gfx_v11_0_set_priv_inst_fault_state, 6423 .process = gfx_v11_0_priv_inst_irq, 6424 }; 6425 6426 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6427 { 6428 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6429 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6430 6431 adev->gfx.priv_reg_irq.num_types = 1; 6432 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6433 6434 adev->gfx.priv_inst_irq.num_types = 1; 6435 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6436 } 6437 6438 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6439 { 6440 if (adev->flags & AMD_IS_APU) 6441 adev->gfx.imu.mode = MISSION_MODE; 6442 else 6443 adev->gfx.imu.mode = DEBUG_MODE; 6444 6445 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6446 } 6447 6448 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6449 { 6450 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6451 } 6452 6453 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6454 { 6455 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6456 adev->gfx.config.max_sh_per_se * 6457 adev->gfx.config.max_shader_engines; 6458 6459 adev->gds.gds_size = 0x1000; 6460 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6461 adev->gds.gws_size = 64; 6462 adev->gds.oa_size = 16; 6463 } 6464 6465 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6466 { 6467 /* set gfx eng mqd */ 6468 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6469 sizeof(struct v11_gfx_mqd); 6470 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6471 gfx_v11_0_gfx_mqd_init; 6472 /* set compute eng mqd */ 6473 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6474 sizeof(struct v11_compute_mqd); 6475 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6476 gfx_v11_0_compute_mqd_init; 6477 } 6478 6479 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6480 u32 bitmap) 6481 { 6482 u32 data; 6483 6484 if (!bitmap) 6485 return; 6486 6487 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6488 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6489 6490 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6491 } 6492 6493 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6494 { 6495 u32 data, wgp_bitmask; 6496 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6497 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6498 6499 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6500 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6501 6502 wgp_bitmask = 6503 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6504 6505 return (~data) & wgp_bitmask; 6506 } 6507 6508 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6509 { 6510 u32 wgp_idx, wgp_active_bitmap; 6511 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6512 6513 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6514 cu_active_bitmap = 0; 6515 6516 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6517 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6518 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6519 if (wgp_active_bitmap & (1 << wgp_idx)) 6520 cu_active_bitmap |= cu_bitmap_per_wgp; 6521 } 6522 6523 return cu_active_bitmap; 6524 } 6525 6526 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6527 struct amdgpu_cu_info *cu_info) 6528 { 6529 int i, j, k, counter, active_cu_number = 0; 6530 u32 mask, bitmap; 6531 unsigned disable_masks[8 * 2]; 6532 6533 if (!adev || !cu_info) 6534 return -EINVAL; 6535 6536 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6537 6538 mutex_lock(&adev->grbm_idx_mutex); 6539 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6540 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6541 mask = 1; 6542 counter = 0; 6543 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 6544 if (i < 8 && j < 2) 6545 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6546 adev, disable_masks[i * 2 + j]); 6547 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6548 6549 /** 6550 * GFX11 could support more than 4 SEs, while the bitmap 6551 * in cu_info struct is 4x4 and ioctl interface struct 6552 * drm_amdgpu_info_device should keep stable. 6553 * So we use last two columns of bitmap to store cu mask for 6554 * SEs 4 to 7, the layout of the bitmap is as below: 6555 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6556 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6557 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6558 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6559 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6560 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6561 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6562 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6563 */ 6564 cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; 6565 6566 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6567 if (bitmap & mask) 6568 counter++; 6569 6570 mask <<= 1; 6571 } 6572 active_cu_number += counter; 6573 } 6574 } 6575 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6576 mutex_unlock(&adev->grbm_idx_mutex); 6577 6578 cu_info->number = active_cu_number; 6579 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6580 6581 return 0; 6582 } 6583 6584 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6585 { 6586 .type = AMD_IP_BLOCK_TYPE_GFX, 6587 .major = 11, 6588 .minor = 0, 6589 .rev = 0, 6590 .funcs = &gfx_v11_0_ip_funcs, 6591 }; 6592