1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "nbio_v4_3.h" 50 #include "mes_v11_0.h" 51 52 #define GFX11_NUM_GFX_RINGS 1 53 #define GFX11_MEC_HPD_SIZE 2048 54 55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 56 57 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 62 63 static const struct soc15_reg_golden golden_settings_gc_11_0[] = 64 { 65 /* Pending on emulation bring up */ 66 }; 67 68 static const struct soc15_reg_golden golden_settings_gc_11_0_0[] = 69 { 70 /* Pending on emulation bring up */ 71 }; 72 73 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_11_0[] = 74 { 75 /* Pending on emulation bring up */ 76 }; 77 78 #define DEFAULT_SH_MEM_CONFIG \ 79 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 80 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 81 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 82 83 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 84 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 85 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 86 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 87 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 88 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 89 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 90 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 91 struct amdgpu_cu_info *cu_info); 92 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 93 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 94 u32 sh_num, u32 instance); 95 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 96 97 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 98 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 99 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 100 uint32_t val); 101 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 102 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 103 uint16_t pasid, uint32_t flush_type, 104 bool all_hub, uint8_t dst_sel); 105 106 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 107 { 108 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 109 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 110 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 111 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 112 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 113 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 114 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 115 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 116 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 117 } 118 119 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 120 struct amdgpu_ring *ring) 121 { 122 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 123 uint64_t wptr_addr = ring->wptr_gpu_addr; 124 uint32_t eng_sel = 0; 125 126 switch (ring->funcs->type) { 127 case AMDGPU_RING_TYPE_COMPUTE: 128 eng_sel = 0; 129 break; 130 case AMDGPU_RING_TYPE_GFX: 131 eng_sel = 4; 132 break; 133 case AMDGPU_RING_TYPE_MES: 134 eng_sel = 5; 135 break; 136 default: 137 WARN_ON(1); 138 } 139 140 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 141 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 142 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 143 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 144 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 145 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 146 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 147 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 148 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 149 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 150 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 151 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 152 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 153 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 154 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 155 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 156 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 157 } 158 159 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 160 struct amdgpu_ring *ring, 161 enum amdgpu_unmap_queues_action action, 162 u64 gpu_addr, u64 seq) 163 { 164 struct amdgpu_device *adev = kiq_ring->adev; 165 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 166 167 if (!adev->gfx.kiq.ring.sched.ready) { 168 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 169 return; 170 } 171 172 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 173 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 174 PACKET3_UNMAP_QUEUES_ACTION(action) | 175 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 176 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 177 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 178 amdgpu_ring_write(kiq_ring, 179 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 180 181 if (action == PREEMPT_QUEUES_NO_UNMAP) { 182 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 183 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 184 amdgpu_ring_write(kiq_ring, seq); 185 } else { 186 amdgpu_ring_write(kiq_ring, 0); 187 amdgpu_ring_write(kiq_ring, 0); 188 amdgpu_ring_write(kiq_ring, 0); 189 } 190 } 191 192 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 193 struct amdgpu_ring *ring, 194 u64 addr, 195 u64 seq) 196 { 197 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 198 199 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 200 amdgpu_ring_write(kiq_ring, 201 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 202 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 203 PACKET3_QUERY_STATUS_COMMAND(2)); 204 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 205 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 206 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 207 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 208 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 209 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 210 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 211 } 212 213 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 214 uint16_t pasid, uint32_t flush_type, 215 bool all_hub) 216 { 217 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 218 } 219 220 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 221 .kiq_set_resources = gfx11_kiq_set_resources, 222 .kiq_map_queues = gfx11_kiq_map_queues, 223 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 224 .kiq_query_status = gfx11_kiq_query_status, 225 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 226 .set_resources_size = 8, 227 .map_queues_size = 7, 228 .unmap_queues_size = 6, 229 .query_status_size = 7, 230 .invalidate_tlbs_size = 2, 231 }; 232 233 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 234 { 235 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; 236 } 237 238 static void gfx_v11_0_init_spm_golden_registers(struct amdgpu_device *adev) 239 { 240 switch (adev->ip_versions[GC_HWIP][0]) { 241 case IP_VERSION(11, 0, 0): 242 soc15_program_register_sequence(adev, 243 golden_settings_gc_rlc_spm_11_0, 244 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_11_0)); 245 break; 246 default: 247 break; 248 } 249 } 250 251 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 252 { 253 switch (adev->ip_versions[GC_HWIP][0]) { 254 case IP_VERSION(11, 0, 0): 255 soc15_program_register_sequence(adev, 256 golden_settings_gc_11_0, 257 (const u32)ARRAY_SIZE(golden_settings_gc_11_0)); 258 soc15_program_register_sequence(adev, 259 golden_settings_gc_11_0_0, 260 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_0)); 261 break; 262 default: 263 break; 264 } 265 gfx_v11_0_init_spm_golden_registers(adev); 266 } 267 268 static void gfx_v11_0_scratch_init(struct amdgpu_device *adev) 269 { 270 adev->gfx.scratch.num_reg = 8; 271 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 272 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 273 } 274 275 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 276 bool wc, uint32_t reg, uint32_t val) 277 { 278 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 279 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 280 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 281 amdgpu_ring_write(ring, reg); 282 amdgpu_ring_write(ring, 0); 283 amdgpu_ring_write(ring, val); 284 } 285 286 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 287 int mem_space, int opt, uint32_t addr0, 288 uint32_t addr1, uint32_t ref, uint32_t mask, 289 uint32_t inv) 290 { 291 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 292 amdgpu_ring_write(ring, 293 /* memory (1) or register (0) */ 294 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 295 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 296 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 297 WAIT_REG_MEM_ENGINE(eng_sel))); 298 299 if (mem_space) 300 BUG_ON(addr0 & 0x3); /* Dword align */ 301 amdgpu_ring_write(ring, addr0); 302 amdgpu_ring_write(ring, addr1); 303 amdgpu_ring_write(ring, ref); 304 amdgpu_ring_write(ring, mask); 305 amdgpu_ring_write(ring, inv); /* poll interval */ 306 } 307 308 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 309 { 310 struct amdgpu_device *adev = ring->adev; 311 uint32_t scratch; 312 uint32_t tmp = 0; 313 unsigned i; 314 int r; 315 316 r = amdgpu_gfx_scratch_get(adev, &scratch); 317 if (r) { 318 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 319 return r; 320 } 321 322 WREG32(scratch, 0xCAFEDEAD); 323 324 r = amdgpu_ring_alloc(ring, 5); 325 if (r) { 326 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 327 ring->idx, r); 328 amdgpu_gfx_scratch_free(adev, scratch); 329 return r; 330 } 331 332 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 333 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 334 } else { 335 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 336 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 337 amdgpu_ring_write(ring, 0xDEADBEEF); 338 } 339 amdgpu_ring_commit(ring); 340 341 for (i = 0; i < adev->usec_timeout; i++) { 342 tmp = RREG32(scratch); 343 if (tmp == 0xDEADBEEF) 344 break; 345 if (amdgpu_emu_mode == 1) 346 msleep(1); 347 else 348 udelay(1); 349 } 350 351 if (i >= adev->usec_timeout) 352 r = -ETIMEDOUT; 353 354 amdgpu_gfx_scratch_free(adev, scratch); 355 356 return r; 357 } 358 359 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 360 { 361 struct amdgpu_device *adev = ring->adev; 362 struct amdgpu_ib ib; 363 struct dma_fence *f = NULL; 364 unsigned index; 365 uint64_t gpu_addr; 366 volatile uint32_t *cpu_ptr; 367 long r; 368 369 /* MES KIQ fw hasn't indirect buffer support for now */ 370 if (adev->enable_mes_kiq && 371 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 372 return 0; 373 374 memset(&ib, 0, sizeof(ib)); 375 376 if (ring->is_mes_queue) { 377 uint32_t padding, offset; 378 379 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 380 padding = amdgpu_mes_ctx_get_offs(ring, 381 AMDGPU_MES_CTX_PADDING_OFFS); 382 383 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 384 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 385 386 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 387 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 388 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 389 } else { 390 r = amdgpu_device_wb_get(adev, &index); 391 if (r) 392 return r; 393 394 gpu_addr = adev->wb.gpu_addr + (index * 4); 395 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 396 cpu_ptr = &adev->wb.wb[index]; 397 398 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 399 if (r) { 400 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 401 goto err1; 402 } 403 } 404 405 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 406 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 407 ib.ptr[2] = lower_32_bits(gpu_addr); 408 ib.ptr[3] = upper_32_bits(gpu_addr); 409 ib.ptr[4] = 0xDEADBEEF; 410 ib.length_dw = 5; 411 412 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 413 if (r) 414 goto err2; 415 416 r = dma_fence_wait_timeout(f, false, timeout); 417 if (r == 0) { 418 r = -ETIMEDOUT; 419 goto err2; 420 } else if (r < 0) { 421 goto err2; 422 } 423 424 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 425 r = 0; 426 else 427 r = -EINVAL; 428 err2: 429 if (!ring->is_mes_queue) 430 amdgpu_ib_free(adev, &ib, NULL); 431 dma_fence_put(f); 432 err1: 433 amdgpu_device_wb_free(adev, index); 434 return r; 435 } 436 437 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 438 { 439 release_firmware(adev->gfx.pfp_fw); 440 adev->gfx.pfp_fw = NULL; 441 release_firmware(adev->gfx.me_fw); 442 adev->gfx.me_fw = NULL; 443 release_firmware(adev->gfx.rlc_fw); 444 adev->gfx.rlc_fw = NULL; 445 release_firmware(adev->gfx.mec_fw); 446 adev->gfx.mec_fw = NULL; 447 448 kfree(adev->gfx.rlc.register_list_format); 449 } 450 451 static void gfx_v11_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 452 { 453 const struct rlc_firmware_header_v2_1 *rlc_hdr; 454 455 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 456 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 457 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 458 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 459 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 460 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 461 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 462 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 463 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 464 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 465 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 466 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 467 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 468 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 469 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 470 } 471 472 static void gfx_v11_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 473 { 474 const struct rlc_firmware_header_v2_2 *rlc_hdr; 475 476 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 477 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 478 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 479 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 480 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 481 } 482 483 static void gfx_v11_0_init_rlcp_rlcv_microcode(struct amdgpu_device *adev) 484 { 485 const struct rlc_firmware_header_v2_3 *rlc_hdr; 486 487 rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 488 adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes); 489 adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); 490 adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes); 491 adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); 492 } 493 494 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 495 { 496 char fw_name[40]; 497 char ucode_prefix[30]; 498 int err; 499 struct amdgpu_firmware_info *info = NULL; 500 const struct common_firmware_header *header = NULL; 501 const struct gfx_firmware_header_v1_0 *cp_hdr; 502 const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0; 503 const struct rlc_firmware_header_v2_0 *rlc_hdr; 504 unsigned int *tmp = NULL; 505 unsigned int i = 0; 506 uint16_t version_major; 507 uint16_t version_minor; 508 509 DRM_DEBUG("\n"); 510 511 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 512 513 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 514 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 515 if (err) 516 goto out; 517 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 518 if (err) 519 goto out; 520 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 521 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 522 (union amdgpu_firmware_header *) 523 adev->gfx.pfp_fw->data, 2, 0); 524 if (adev->gfx.rs64_enable) { 525 dev_info(adev->dev, "CP RS64 enable\n"); 526 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; 527 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 528 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 529 530 } else { 531 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 532 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 533 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 534 } 535 536 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 537 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 538 if (err) 539 goto out; 540 err = amdgpu_ucode_validate(adev->gfx.me_fw); 541 if (err) 542 goto out; 543 if (adev->gfx.rs64_enable) { 544 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; 545 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 546 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 547 548 } else { 549 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 550 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 551 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 552 } 553 554 if (!amdgpu_sriov_vf(adev)) { 555 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 556 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 557 if (err) 558 goto out; 559 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 560 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 561 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 562 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 563 564 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 565 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 566 adev->gfx.rlc.save_and_restore_offset = 567 le32_to_cpu(rlc_hdr->save_and_restore_offset); 568 adev->gfx.rlc.clear_state_descriptor_offset = 569 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 570 adev->gfx.rlc.avail_scratch_ram_locations = 571 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 572 adev->gfx.rlc.reg_restore_list_size = 573 le32_to_cpu(rlc_hdr->reg_restore_list_size); 574 adev->gfx.rlc.reg_list_format_start = 575 le32_to_cpu(rlc_hdr->reg_list_format_start); 576 adev->gfx.rlc.reg_list_format_separate_start = 577 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 578 adev->gfx.rlc.starting_offsets_start = 579 le32_to_cpu(rlc_hdr->starting_offsets_start); 580 adev->gfx.rlc.reg_list_format_size_bytes = 581 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 582 adev->gfx.rlc.reg_list_size_bytes = 583 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 584 adev->gfx.rlc.register_list_format = 585 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 586 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 587 if (!adev->gfx.rlc.register_list_format) { 588 err = -ENOMEM; 589 goto out; 590 } 591 592 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 593 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 594 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 595 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 596 597 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 598 599 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 600 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 601 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 602 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 603 604 if (version_major == 2) { 605 if (version_minor >= 1) 606 gfx_v11_0_init_rlc_ext_microcode(adev); 607 if (version_minor >= 2) 608 gfx_v11_0_init_rlc_iram_dram_microcode(adev); 609 if (version_minor == 3) 610 gfx_v11_0_init_rlcp_rlcv_microcode(adev); 611 } 612 } 613 614 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 615 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 616 if (err) 617 goto out; 618 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 619 if (err) 620 goto out; 621 if (adev->gfx.rs64_enable) { 622 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 623 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 624 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 625 626 } else { 627 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 628 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 629 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 630 } 631 632 /* only one MEC for gfx 11.0.0. */ 633 adev->gfx.mec2_fw = NULL; 634 635 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 636 if (adev->gfx.rs64_enable) { 637 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.pfp_fw->data; 638 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP]; 639 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP; 640 info->fw = adev->gfx.pfp_fw; 641 header = (const struct common_firmware_header *)info->fw->data; 642 adev->firmware.fw_size += 643 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 644 645 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK]; 646 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK; 647 info->fw = adev->gfx.pfp_fw; 648 header = (const struct common_firmware_header *)info->fw->data; 649 adev->firmware.fw_size += 650 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 651 652 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK]; 653 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK; 654 info->fw = adev->gfx.pfp_fw; 655 header = (const struct common_firmware_header *)info->fw->data; 656 adev->firmware.fw_size += 657 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 658 659 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.me_fw->data; 660 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME]; 661 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME; 662 info->fw = adev->gfx.me_fw; 663 header = (const struct common_firmware_header *)info->fw->data; 664 adev->firmware.fw_size += 665 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 666 667 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK]; 668 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK; 669 info->fw = adev->gfx.me_fw; 670 header = (const struct common_firmware_header *)info->fw->data; 671 adev->firmware.fw_size += 672 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 673 674 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK]; 675 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK; 676 info->fw = adev->gfx.me_fw; 677 header = (const struct common_firmware_header *)info->fw->data; 678 adev->firmware.fw_size += 679 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 680 681 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 682 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC]; 683 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC; 684 info->fw = adev->gfx.mec_fw; 685 header = (const struct common_firmware_header *)info->fw->data; 686 adev->firmware.fw_size += 687 ALIGN(le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes), PAGE_SIZE); 688 689 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK]; 690 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK; 691 info->fw = adev->gfx.mec_fw; 692 header = (const struct common_firmware_header *)info->fw->data; 693 adev->firmware.fw_size += 694 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 695 696 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK]; 697 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK; 698 info->fw = adev->gfx.mec_fw; 699 header = (const struct common_firmware_header *)info->fw->data; 700 adev->firmware.fw_size += 701 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 702 703 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK]; 704 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK; 705 info->fw = adev->gfx.mec_fw; 706 header = (const struct common_firmware_header *)info->fw->data; 707 adev->firmware.fw_size += 708 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 709 710 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK]; 711 info->ucode_id = AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK; 712 info->fw = adev->gfx.mec_fw; 713 header = (const struct common_firmware_header *)info->fw->data; 714 adev->firmware.fw_size += 715 ALIGN(le32_to_cpu(cp_hdr_v2_0->data_size_bytes), PAGE_SIZE); 716 } else { 717 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 718 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 719 info->fw = adev->gfx.pfp_fw; 720 header = (const struct common_firmware_header *)info->fw->data; 721 adev->firmware.fw_size += 722 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 723 724 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 725 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 726 info->fw = adev->gfx.me_fw; 727 header = (const struct common_firmware_header *)info->fw->data; 728 adev->firmware.fw_size += 729 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 730 731 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 732 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 733 info->fw = adev->gfx.mec_fw; 734 header = (const struct common_firmware_header *)info->fw->data; 735 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 736 adev->firmware.fw_size += 737 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 738 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 739 740 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 741 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 742 info->fw = adev->gfx.mec_fw; 743 adev->firmware.fw_size += 744 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 745 } 746 747 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 748 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 749 info->fw = adev->gfx.rlc_fw; 750 if (info->fw) { 751 header = (const struct common_firmware_header *)info->fw->data; 752 adev->firmware.fw_size += 753 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 754 } 755 if (adev->gfx.rlc.save_restore_list_gpm_size_bytes && 756 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 757 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 758 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 759 info->fw = adev->gfx.rlc_fw; 760 adev->firmware.fw_size += 761 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 762 763 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 764 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 765 info->fw = adev->gfx.rlc_fw; 766 adev->firmware.fw_size += 767 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 768 } 769 770 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 771 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 772 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 773 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 774 info->fw = adev->gfx.rlc_fw; 775 adev->firmware.fw_size += 776 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 777 778 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 779 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 780 info->fw = adev->gfx.rlc_fw; 781 adev->firmware.fw_size += 782 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 783 } 784 785 if (adev->gfx.rlc.rlcp_ucode_size_bytes) { 786 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; 787 info->ucode_id = AMDGPU_UCODE_ID_RLC_P; 788 info->fw = adev->gfx.rlc_fw; 789 adev->firmware.fw_size += 790 ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE); 791 } 792 793 if (adev->gfx.rlc.rlcv_ucode_size_bytes) { 794 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; 795 info->ucode_id = AMDGPU_UCODE_ID_RLC_V; 796 info->fw = adev->gfx.rlc_fw; 797 adev->firmware.fw_size += 798 ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE); 799 } 800 } 801 802 out: 803 if (err) { 804 dev_err(adev->dev, 805 "gfx11: Failed to load firmware \"%s\"\n", 806 fw_name); 807 release_firmware(adev->gfx.pfp_fw); 808 adev->gfx.pfp_fw = NULL; 809 release_firmware(adev->gfx.me_fw); 810 adev->gfx.me_fw = NULL; 811 release_firmware(adev->gfx.rlc_fw); 812 adev->gfx.rlc_fw = NULL; 813 release_firmware(adev->gfx.mec_fw); 814 adev->gfx.mec_fw = NULL; 815 } 816 817 return err; 818 } 819 820 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) 821 { 822 const struct psp_firmware_header_v1_0 *toc_hdr; 823 int err = 0; 824 char fw_name[40]; 825 char ucode_prefix[30]; 826 827 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 828 829 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 830 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 831 if (err) 832 goto out; 833 834 err = amdgpu_ucode_validate(adev->psp.toc_fw); 835 if (err) 836 goto out; 837 838 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 839 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 840 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 841 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 842 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 843 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 844 return 0; 845 out: 846 dev_err(adev->dev, "Failed to load TOC microcode\n"); 847 release_firmware(adev->psp.toc_fw); 848 adev->psp.toc_fw = NULL; 849 return err; 850 } 851 852 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 853 { 854 u32 count = 0; 855 const struct cs_section_def *sect = NULL; 856 const struct cs_extent_def *ext = NULL; 857 858 /* begin clear state */ 859 count += 2; 860 /* context control state */ 861 count += 3; 862 863 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 864 for (ext = sect->section; ext->extent != NULL; ++ext) { 865 if (sect->id == SECT_CONTEXT) 866 count += 2 + ext->reg_count; 867 else 868 return 0; 869 } 870 } 871 872 /* set PA_SC_TILE_STEERING_OVERRIDE */ 873 count += 3; 874 /* end clear state */ 875 count += 2; 876 /* clear state */ 877 count += 2; 878 879 return count; 880 } 881 882 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 883 volatile u32 *buffer) 884 { 885 u32 count = 0, i; 886 const struct cs_section_def *sect = NULL; 887 const struct cs_extent_def *ext = NULL; 888 int ctx_reg_offset; 889 890 if (adev->gfx.rlc.cs_data == NULL) 891 return; 892 if (buffer == NULL) 893 return; 894 895 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 896 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 897 898 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 899 buffer[count++] = cpu_to_le32(0x80000000); 900 buffer[count++] = cpu_to_le32(0x80000000); 901 902 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 903 for (ext = sect->section; ext->extent != NULL; ++ext) { 904 if (sect->id == SECT_CONTEXT) { 905 buffer[count++] = 906 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 907 buffer[count++] = cpu_to_le32(ext->reg_index - 908 PACKET3_SET_CONTEXT_REG_START); 909 for (i = 0; i < ext->reg_count; i++) 910 buffer[count++] = cpu_to_le32(ext->extent[i]); 911 } else { 912 return; 913 } 914 } 915 } 916 917 ctx_reg_offset = 918 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 919 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 920 buffer[count++] = cpu_to_le32(ctx_reg_offset); 921 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 922 923 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 924 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 925 926 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 927 buffer[count++] = cpu_to_le32(0); 928 } 929 930 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 931 { 932 /* clear state block */ 933 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 934 &adev->gfx.rlc.clear_state_gpu_addr, 935 (void **)&adev->gfx.rlc.cs_ptr); 936 937 /* jump table block */ 938 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 939 &adev->gfx.rlc.cp_table_gpu_addr, 940 (void **)&adev->gfx.rlc.cp_table_ptr); 941 } 942 943 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 944 { 945 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 946 947 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 948 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 949 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 950 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 951 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 952 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 953 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 954 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 955 adev->gfx.rlc.rlcg_reg_access_supported = true; 956 } 957 958 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 959 { 960 const struct cs_section_def *cs_data; 961 int r; 962 963 adev->gfx.rlc.cs_data = gfx11_cs_data; 964 965 cs_data = adev->gfx.rlc.cs_data; 966 967 if (cs_data) { 968 /* init clear state block */ 969 r = amdgpu_gfx_rlc_init_csb(adev); 970 if (r) 971 return r; 972 } 973 974 /* init spm vmid with 0xf */ 975 if (adev->gfx.rlc.funcs->update_spm_vmid) 976 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 977 978 return 0; 979 } 980 981 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 982 { 983 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 984 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 985 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 986 } 987 988 static int gfx_v11_0_me_init(struct amdgpu_device *adev) 989 { 990 int r; 991 992 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 993 994 amdgpu_gfx_graphics_queue_acquire(adev); 995 996 r = gfx_v11_0_init_microcode(adev); 997 if (r) 998 DRM_ERROR("Failed to load gfx firmware!\n"); 999 1000 return r; 1001 } 1002 1003 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 1004 { 1005 int r; 1006 u32 *hpd; 1007 size_t mec_hpd_size; 1008 1009 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1010 1011 /* take ownership of the relevant compute queues */ 1012 amdgpu_gfx_compute_queue_acquire(adev); 1013 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 1014 1015 if (mec_hpd_size) { 1016 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1017 AMDGPU_GEM_DOMAIN_GTT, 1018 &adev->gfx.mec.hpd_eop_obj, 1019 &adev->gfx.mec.hpd_eop_gpu_addr, 1020 (void **)&hpd); 1021 if (r) { 1022 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1023 gfx_v11_0_mec_fini(adev); 1024 return r; 1025 } 1026 1027 memset(hpd, 0, mec_hpd_size); 1028 1029 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1030 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1031 } 1032 1033 return 0; 1034 } 1035 1036 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1037 { 1038 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1039 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1040 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1041 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1042 } 1043 1044 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1045 uint32_t thread, uint32_t regno, 1046 uint32_t num, uint32_t *out) 1047 { 1048 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 1049 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1050 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1051 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1052 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1053 while (num--) 1054 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 1055 } 1056 1057 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1058 { 1059 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 1060 * field when performing a select_se_sh so it should be 1061 * zero here */ 1062 WARN_ON(simd != 0); 1063 1064 /* type 2 wave data */ 1065 dst[(*no_fields)++] = 2; 1066 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1067 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1068 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1069 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1070 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1071 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1072 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1073 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1074 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1075 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1076 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1077 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1078 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1079 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1080 } 1081 1082 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1083 uint32_t wave, uint32_t start, 1084 uint32_t size, uint32_t *dst) 1085 { 1086 WARN_ON(simd != 0); 1087 1088 wave_read_regs( 1089 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1090 dst); 1091 } 1092 1093 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1094 uint32_t wave, uint32_t thread, 1095 uint32_t start, uint32_t size, 1096 uint32_t *dst) 1097 { 1098 wave_read_regs( 1099 adev, wave, thread, 1100 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1101 } 1102 1103 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 1104 u32 me, u32 pipe, u32 q, u32 vm) 1105 { 1106 soc21_grbm_select(adev, me, pipe, q, vm); 1107 } 1108 1109 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 1110 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 1111 .select_se_sh = &gfx_v11_0_select_se_sh, 1112 .read_wave_data = &gfx_v11_0_read_wave_data, 1113 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 1114 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 1115 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 1116 .init_spm_golden = &gfx_v11_0_init_spm_golden_registers, 1117 }; 1118 1119 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 1120 { 1121 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 1122 1123 switch (adev->ip_versions[GC_HWIP][0]) { 1124 case IP_VERSION(11, 0, 0): 1125 adev->gfx.config.max_hw_contexts = 8; 1126 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1127 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1128 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1129 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1130 break; 1131 default: 1132 BUG(); 1133 break; 1134 } 1135 1136 return 0; 1137 } 1138 1139 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1140 int me, int pipe, int queue) 1141 { 1142 int r; 1143 struct amdgpu_ring *ring; 1144 unsigned int irq_type; 1145 1146 ring = &adev->gfx.gfx_ring[ring_id]; 1147 1148 ring->me = me; 1149 ring->pipe = pipe; 1150 ring->queue = queue; 1151 1152 ring->ring_obj = NULL; 1153 ring->use_doorbell = true; 1154 1155 if (!ring_id) 1156 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1157 else 1158 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1159 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1160 1161 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1162 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1163 AMDGPU_RING_PRIO_DEFAULT, NULL); 1164 if (r) 1165 return r; 1166 return 0; 1167 } 1168 1169 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1170 int mec, int pipe, int queue) 1171 { 1172 int r; 1173 unsigned irq_type; 1174 struct amdgpu_ring *ring; 1175 unsigned int hw_prio; 1176 1177 ring = &adev->gfx.compute_ring[ring_id]; 1178 1179 /* mec0 is me1 */ 1180 ring->me = mec + 1; 1181 ring->pipe = pipe; 1182 ring->queue = queue; 1183 1184 ring->ring_obj = NULL; 1185 ring->use_doorbell = true; 1186 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1187 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1188 + (ring_id * GFX11_MEC_HPD_SIZE); 1189 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1190 1191 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1192 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1193 + ring->pipe; 1194 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1195 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1196 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1197 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1198 hw_prio, NULL); 1199 if (r) 1200 return r; 1201 1202 return 0; 1203 } 1204 1205 static struct { 1206 SOC21_FIRMWARE_ID id; 1207 unsigned int offset; 1208 unsigned int size; 1209 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 1210 1211 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 1212 { 1213 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 1214 1215 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 1216 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 1217 rlc_autoload_info[ucode->id].id = ucode->id; 1218 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 1219 rlc_autoload_info[ucode->id].size = ucode->size * 4; 1220 1221 ucode++; 1222 }; 1223 } 1224 1225 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 1226 { 1227 uint32_t total_size = 0; 1228 SOC21_FIRMWARE_ID id; 1229 1230 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 1231 1232 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 1233 total_size += rlc_autoload_info[id].size; 1234 1235 /* In case the offset in rlc toc ucode is aligned */ 1236 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 1237 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 1238 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 1239 1240 return total_size; 1241 } 1242 1243 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 1244 { 1245 int r; 1246 uint32_t total_size; 1247 1248 total_size = gfx_v11_0_calc_toc_total_size(adev); 1249 1250 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 1251 AMDGPU_GEM_DOMAIN_VRAM, 1252 &adev->gfx.rlc.rlc_autoload_bo, 1253 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1254 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1255 1256 if (r) { 1257 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1258 return r; 1259 } 1260 1261 return 0; 1262 } 1263 1264 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1265 SOC21_FIRMWARE_ID id, 1266 const void *fw_data, 1267 uint32_t fw_size, 1268 uint32_t *fw_autoload_mask) 1269 { 1270 uint32_t toc_offset; 1271 uint32_t toc_fw_size; 1272 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1273 1274 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 1275 return; 1276 1277 toc_offset = rlc_autoload_info[id].offset; 1278 toc_fw_size = rlc_autoload_info[id].size; 1279 1280 if (fw_size == 0) 1281 fw_size = toc_fw_size; 1282 1283 if (fw_size > toc_fw_size) 1284 fw_size = toc_fw_size; 1285 1286 memcpy(ptr + toc_offset, fw_data, fw_size); 1287 1288 if (fw_size < toc_fw_size) 1289 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1290 1291 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1292 *(uint64_t *)fw_autoload_mask |= 1 << id; 1293 } 1294 1295 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1296 uint32_t *fw_autoload_mask) 1297 { 1298 void *data; 1299 uint32_t size; 1300 uint64_t *toc_ptr; 1301 1302 *(uint64_t *)fw_autoload_mask |= 0x1; 1303 1304 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1305 1306 data = adev->psp.toc.start_addr; 1307 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1308 1309 toc_ptr = (uint64_t *)data + size / 8 - 1; 1310 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1311 1312 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1313 data, size, fw_autoload_mask); 1314 } 1315 1316 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1317 uint32_t *fw_autoload_mask) 1318 { 1319 const __le32 *fw_data; 1320 uint32_t fw_size; 1321 const struct gfx_firmware_header_v1_0 *cp_hdr; 1322 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1323 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1324 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1325 uint16_t version_major, version_minor; 1326 1327 if (adev->gfx.rs64_enable) { 1328 /* pfp ucode */ 1329 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1330 adev->gfx.pfp_fw->data; 1331 /* instruction */ 1332 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1333 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1334 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1335 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1336 fw_data, fw_size, fw_autoload_mask); 1337 /* data */ 1338 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1339 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1340 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1341 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1342 fw_data, fw_size, fw_autoload_mask); 1343 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1344 fw_data, fw_size, fw_autoload_mask); 1345 /* me ucode */ 1346 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1347 adev->gfx.me_fw->data; 1348 /* instruction */ 1349 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1350 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1351 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1352 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1353 fw_data, fw_size, fw_autoload_mask); 1354 /* data */ 1355 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1356 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1357 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1358 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1359 fw_data, fw_size, fw_autoload_mask); 1360 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1361 fw_data, fw_size, fw_autoload_mask); 1362 /* mec ucode */ 1363 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1364 adev->gfx.mec_fw->data; 1365 /* instruction */ 1366 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1367 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1368 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1369 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1370 fw_data, fw_size, fw_autoload_mask); 1371 /* data */ 1372 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1373 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1374 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1375 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1376 fw_data, fw_size, fw_autoload_mask); 1377 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1378 fw_data, fw_size, fw_autoload_mask); 1379 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1380 fw_data, fw_size, fw_autoload_mask); 1381 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1382 fw_data, fw_size, fw_autoload_mask); 1383 } else { 1384 /* pfp ucode */ 1385 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1386 adev->gfx.pfp_fw->data; 1387 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1388 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1389 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1390 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1391 fw_data, fw_size, fw_autoload_mask); 1392 1393 /* me ucode */ 1394 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1395 adev->gfx.me_fw->data; 1396 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1397 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1398 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1399 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1400 fw_data, fw_size, fw_autoload_mask); 1401 1402 /* mec ucode */ 1403 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1404 adev->gfx.mec_fw->data; 1405 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1406 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1407 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1408 cp_hdr->jt_size * 4; 1409 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1410 fw_data, fw_size, fw_autoload_mask); 1411 } 1412 1413 /* rlc ucode */ 1414 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1415 adev->gfx.rlc_fw->data; 1416 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1417 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1418 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1419 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1420 fw_data, fw_size, fw_autoload_mask); 1421 1422 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1423 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1424 if (version_major == 2) { 1425 if (version_minor >= 2) { 1426 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1427 1428 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1429 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1430 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1431 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1432 fw_data, fw_size, fw_autoload_mask); 1433 1434 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1435 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1436 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1437 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1438 fw_data, fw_size, fw_autoload_mask); 1439 } 1440 } 1441 } 1442 1443 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1444 uint32_t *fw_autoload_mask) 1445 { 1446 const __le32 *fw_data; 1447 uint32_t fw_size; 1448 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1449 1450 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1451 adev->sdma.instance[0].fw->data; 1452 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1453 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1454 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1455 1456 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1457 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1458 1459 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1460 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1461 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1462 1463 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1464 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1465 } 1466 1467 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1468 uint32_t *fw_autoload_mask) 1469 { 1470 const __le32 *fw_data; 1471 unsigned fw_size; 1472 const struct mes_firmware_header_v1_0 *mes_hdr; 1473 int pipe, ucode_id, data_id; 1474 1475 for (pipe = 0; pipe < 2; pipe++) { 1476 if (pipe==0) { 1477 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1478 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1479 } else { 1480 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1481 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1482 } 1483 1484 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1485 adev->mes.fw[pipe]->data; 1486 1487 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1488 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1489 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1490 1491 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1492 ucode_id, fw_data, fw_size, fw_autoload_mask); 1493 1494 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1495 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1496 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1497 1498 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1499 data_id, fw_data, fw_size, fw_autoload_mask); 1500 } 1501 } 1502 1503 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1504 { 1505 uint32_t rlc_g_offset, rlc_g_size; 1506 uint64_t gpu_addr; 1507 uint32_t autoload_fw_id[2]; 1508 1509 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1510 1511 /* RLC autoload sequence 2: copy ucode */ 1512 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1513 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1514 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1515 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1516 1517 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1518 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1519 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1520 1521 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1522 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1523 1524 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1525 1526 /* RLC autoload sequence 3: load IMU fw */ 1527 if (adev->gfx.imu.funcs->load_microcode) 1528 adev->gfx.imu.funcs->load_microcode(adev); 1529 /* RLC autoload sequence 4 init IMU fw */ 1530 if (adev->gfx.imu.funcs->setup_imu) 1531 adev->gfx.imu.funcs->setup_imu(adev); 1532 if (adev->gfx.imu.funcs->start_imu) 1533 adev->gfx.imu.funcs->start_imu(adev); 1534 1535 /* RLC autoload sequence 5 disable gpa mode */ 1536 gfx_v11_0_disable_gpa_mode(adev); 1537 1538 return 0; 1539 } 1540 1541 static int gfx_v11_0_sw_init(void *handle) 1542 { 1543 int i, j, k, r, ring_id = 0; 1544 struct amdgpu_kiq *kiq; 1545 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1546 1547 adev->gfxhub.funcs->init(adev); 1548 1549 switch (adev->ip_versions[GC_HWIP][0]) { 1550 case IP_VERSION(11, 0, 0): 1551 adev->gfx.me.num_me = 1; 1552 adev->gfx.me.num_pipe_per_me = 1; 1553 adev->gfx.me.num_queue_per_pipe = 1; 1554 adev->gfx.mec.num_mec = 2; 1555 adev->gfx.mec.num_pipe_per_mec = 4; 1556 adev->gfx.mec.num_queue_per_pipe = 4; 1557 break; 1558 default: 1559 adev->gfx.me.num_me = 1; 1560 adev->gfx.me.num_pipe_per_me = 1; 1561 adev->gfx.me.num_queue_per_pipe = 1; 1562 adev->gfx.mec.num_mec = 1; 1563 adev->gfx.mec.num_pipe_per_mec = 4; 1564 adev->gfx.mec.num_queue_per_pipe = 8; 1565 break; 1566 } 1567 1568 /* EOP Event */ 1569 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1570 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1571 &adev->gfx.eop_irq); 1572 if (r) 1573 return r; 1574 1575 /* Privileged reg */ 1576 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1577 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1578 &adev->gfx.priv_reg_irq); 1579 if (r) 1580 return r; 1581 1582 /* Privileged inst */ 1583 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1584 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1585 &adev->gfx.priv_inst_irq); 1586 if (r) 1587 return r; 1588 1589 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1590 1591 gfx_v11_0_scratch_init(adev); 1592 1593 if (adev->gfx.imu.funcs) { 1594 if (adev->gfx.imu.funcs->init_microcode) { 1595 r = adev->gfx.imu.funcs->init_microcode(adev); 1596 if (r) 1597 DRM_ERROR("Failed to load imu firmware!\n"); 1598 } 1599 } 1600 1601 r = gfx_v11_0_me_init(adev); 1602 if (r) 1603 return r; 1604 1605 r = gfx_v11_0_rlc_init(adev); 1606 if (r) { 1607 DRM_ERROR("Failed to init rlc BOs!\n"); 1608 return r; 1609 } 1610 1611 r = gfx_v11_0_mec_init(adev); 1612 if (r) { 1613 DRM_ERROR("Failed to init MEC BOs!\n"); 1614 return r; 1615 } 1616 1617 /* set up the gfx ring */ 1618 for (i = 0; i < adev->gfx.me.num_me; i++) { 1619 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1620 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1621 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1622 continue; 1623 1624 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1625 i, k, j); 1626 if (r) 1627 return r; 1628 ring_id++; 1629 } 1630 } 1631 } 1632 1633 ring_id = 0; 1634 /* set up the compute queues - allocate horizontally across pipes */ 1635 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1636 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1637 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1638 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1639 j)) 1640 continue; 1641 1642 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1643 i, k, j); 1644 if (r) 1645 return r; 1646 1647 ring_id++; 1648 } 1649 } 1650 } 1651 1652 if (!adev->enable_mes_kiq) { 1653 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE); 1654 if (r) { 1655 DRM_ERROR("Failed to init KIQ BOs!\n"); 1656 return r; 1657 } 1658 1659 kiq = &adev->gfx.kiq; 1660 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1661 if (r) 1662 return r; 1663 } 1664 1665 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd)); 1666 if (r) 1667 return r; 1668 1669 /* allocate visible FB for rlc auto-loading fw */ 1670 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1671 r = gfx_v11_0_init_toc_microcode(adev); 1672 if (r) 1673 dev_err(adev->dev, "Failed to load toc firmware!\n"); 1674 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1675 if (r) 1676 return r; 1677 } 1678 1679 r = gfx_v11_0_gpu_early_init(adev); 1680 if (r) 1681 return r; 1682 1683 return 0; 1684 } 1685 1686 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1687 { 1688 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1689 &adev->gfx.pfp.pfp_fw_gpu_addr, 1690 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1691 1692 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1693 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1694 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1695 } 1696 1697 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1698 { 1699 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1700 &adev->gfx.me.me_fw_gpu_addr, 1701 (void **)&adev->gfx.me.me_fw_ptr); 1702 1703 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1704 &adev->gfx.me.me_fw_data_gpu_addr, 1705 (void **)&adev->gfx.me.me_fw_data_ptr); 1706 } 1707 1708 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1709 { 1710 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1711 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1712 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1713 } 1714 1715 static int gfx_v11_0_sw_fini(void *handle) 1716 { 1717 int i; 1718 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1719 1720 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1721 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1722 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1723 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1724 1725 amdgpu_gfx_mqd_sw_fini(adev); 1726 1727 if (!adev->enable_mes_kiq) { 1728 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1729 amdgpu_gfx_kiq_fini(adev); 1730 } 1731 1732 gfx_v11_0_pfp_fini(adev); 1733 gfx_v11_0_me_fini(adev); 1734 gfx_v11_0_rlc_fini(adev); 1735 gfx_v11_0_mec_fini(adev); 1736 1737 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1738 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1739 1740 gfx_v11_0_free_microcode(adev); 1741 1742 return 0; 1743 } 1744 1745 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1746 u32 sh_num, u32 instance) 1747 { 1748 u32 data; 1749 1750 if (instance == 0xffffffff) 1751 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1752 INSTANCE_BROADCAST_WRITES, 1); 1753 else 1754 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1755 instance); 1756 1757 if (se_num == 0xffffffff) 1758 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1759 1); 1760 else 1761 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1762 1763 if (sh_num == 0xffffffff) 1764 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1765 1); 1766 else 1767 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1768 1769 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1770 } 1771 1772 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1773 { 1774 u32 data, mask; 1775 1776 data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1777 data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1778 1779 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1780 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1781 1782 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1783 adev->gfx.config.max_sh_per_se); 1784 1785 return (~data) & mask; 1786 } 1787 1788 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1789 { 1790 int i, j; 1791 u32 data; 1792 u32 active_rbs = 0; 1793 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1794 adev->gfx.config.max_sh_per_se; 1795 1796 mutex_lock(&adev->grbm_idx_mutex); 1797 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1798 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1799 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 1800 data = gfx_v11_0_get_rb_active_bitmap(adev); 1801 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1802 rb_bitmap_width_per_sh); 1803 } 1804 } 1805 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1806 mutex_unlock(&adev->grbm_idx_mutex); 1807 1808 adev->gfx.config.backend_enable_mask = active_rbs; 1809 adev->gfx.config.num_rbs = hweight32(active_rbs); 1810 } 1811 1812 #define DEFAULT_SH_MEM_BASES (0x6000) 1813 #define LDS_APP_BASE 0x1 1814 #define SCRATCH_APP_BASE 0x2 1815 1816 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1817 { 1818 int i; 1819 uint32_t sh_mem_bases; 1820 uint32_t data; 1821 1822 /* 1823 * Configure apertures: 1824 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1825 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1826 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1827 */ 1828 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1829 SCRATCH_APP_BASE; 1830 1831 mutex_lock(&adev->srbm_mutex); 1832 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1833 soc21_grbm_select(adev, 0, 0, 0, i); 1834 /* CP and shaders */ 1835 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1836 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1837 1838 /* Enable trap for each kfd vmid. */ 1839 data = RREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL)); 1840 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1841 } 1842 soc21_grbm_select(adev, 0, 0, 0, 0); 1843 mutex_unlock(&adev->srbm_mutex); 1844 1845 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1846 acccess. These should be enabled by FW for target VMIDs. */ 1847 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1848 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1849 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1850 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1851 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1852 } 1853 } 1854 1855 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1856 { 1857 int vmid; 1858 1859 /* 1860 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1861 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1862 * the driver can enable them for graphics. VMID0 should maintain 1863 * access so that HWS firmware can save/restore entries. 1864 */ 1865 for (vmid = 1; vmid < 16; vmid++) { 1866 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1867 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1868 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1869 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1870 } 1871 } 1872 1873 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1874 { 1875 /* TODO: harvest feature to be added later. */ 1876 } 1877 1878 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1879 { 1880 /* TCCs are global (not instanced). */ 1881 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1882 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1883 1884 adev->gfx.config.tcc_disabled_mask = 1885 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1886 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1887 } 1888 1889 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1890 { 1891 u32 tmp; 1892 int i; 1893 1894 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1895 1896 gfx_v11_0_setup_rb(adev); 1897 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1898 gfx_v11_0_get_tcc_info(adev); 1899 adev->gfx.config.pa_sc_tile_steering_override = 0; 1900 1901 /* XXX SH_MEM regs */ 1902 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1903 mutex_lock(&adev->srbm_mutex); 1904 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1905 soc21_grbm_select(adev, 0, 0, 0, i); 1906 /* CP and shaders */ 1907 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1908 if (i != 0) { 1909 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1910 (adev->gmc.private_aperture_start >> 48)); 1911 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1912 (adev->gmc.shared_aperture_start >> 48)); 1913 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1914 } 1915 } 1916 soc21_grbm_select(adev, 0, 0, 0, 0); 1917 1918 mutex_unlock(&adev->srbm_mutex); 1919 1920 gfx_v11_0_init_compute_vmid(adev); 1921 gfx_v11_0_init_gds_vmid(adev); 1922 } 1923 1924 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1925 bool enable) 1926 { 1927 u32 tmp; 1928 1929 if (amdgpu_sriov_vf(adev)) 1930 return; 1931 1932 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1933 1934 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1935 enable ? 1 : 0); 1936 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1937 enable ? 1 : 0); 1938 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1939 enable ? 1 : 0); 1940 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1941 enable ? 1 : 0); 1942 1943 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1944 } 1945 1946 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1947 { 1948 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1949 1950 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1951 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1952 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1953 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1954 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1955 1956 return 0; 1957 } 1958 1959 void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1960 { 1961 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1962 1963 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1964 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1965 } 1966 1967 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1968 { 1969 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1970 udelay(50); 1971 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1972 udelay(50); 1973 } 1974 1975 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1976 bool enable) 1977 { 1978 uint32_t rlc_pg_cntl; 1979 1980 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1981 1982 if (!enable) { 1983 /* RLC_PG_CNTL[23] = 0 (default) 1984 * RLC will wait for handshake acks with SMU 1985 * GFXOFF will be enabled 1986 * RLC_PG_CNTL[23] = 1 1987 * RLC will not issue any message to SMU 1988 * hence no handshake between SMU & RLC 1989 * GFXOFF will be disabled 1990 */ 1991 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1992 } else 1993 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1994 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1995 } 1996 1997 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 1998 { 1999 /* TODO: enable rlc & smu handshake until smu 2000 * and gfxoff feature works as expected */ 2001 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 2002 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 2003 2004 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2005 udelay(50); 2006 } 2007 2008 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 2009 { 2010 uint32_t tmp; 2011 2012 /* enable Save Restore Machine */ 2013 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 2014 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2015 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 2016 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 2017 } 2018 2019 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 2020 { 2021 const struct rlc_firmware_header_v2_0 *hdr; 2022 const __le32 *fw_data; 2023 unsigned i, fw_size; 2024 2025 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2026 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2027 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2028 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2029 2030 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 2031 RLCG_UCODE_LOADING_START_ADDRESS); 2032 2033 for (i = 0; i < fw_size; i++) 2034 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 2035 le32_to_cpup(fw_data++)); 2036 2037 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2038 } 2039 2040 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 2041 { 2042 const struct rlc_firmware_header_v2_2 *hdr; 2043 const __le32 *fw_data; 2044 unsigned i, fw_size; 2045 u32 tmp; 2046 2047 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 2048 2049 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2050 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 2051 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 2052 2053 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 2054 2055 for (i = 0; i < fw_size; i++) { 2056 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2057 msleep(1); 2058 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 2059 le32_to_cpup(fw_data++)); 2060 } 2061 2062 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2063 2064 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2065 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 2066 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 2067 2068 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 2069 for (i = 0; i < fw_size; i++) { 2070 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2071 msleep(1); 2072 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 2073 le32_to_cpup(fw_data++)); 2074 } 2075 2076 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 2077 2078 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 2079 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 2080 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 2081 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 2082 } 2083 2084 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 2085 { 2086 const struct rlc_firmware_header_v2_3 *hdr; 2087 const __le32 *fw_data; 2088 unsigned i, fw_size; 2089 u32 tmp; 2090 2091 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 2092 2093 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2094 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 2095 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 2096 2097 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 2098 2099 for (i = 0; i < fw_size; i++) { 2100 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2101 msleep(1); 2102 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 2103 le32_to_cpup(fw_data++)); 2104 } 2105 2106 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 2107 2108 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 2109 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 2110 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 2111 2112 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2113 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 2114 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 2115 2116 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 2117 2118 for (i = 0; i < fw_size; i++) { 2119 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 2120 msleep(1); 2121 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 2122 le32_to_cpup(fw_data++)); 2123 } 2124 2125 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 2126 2127 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 2128 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 2129 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 2130 } 2131 2132 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 2133 { 2134 const struct rlc_firmware_header_v2_0 *hdr; 2135 uint16_t version_major; 2136 uint16_t version_minor; 2137 2138 if (!adev->gfx.rlc_fw) 2139 return -EINVAL; 2140 2141 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2142 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2143 2144 version_major = le16_to_cpu(hdr->header.header_version_major); 2145 version_minor = le16_to_cpu(hdr->header.header_version_minor); 2146 2147 if (version_major == 2) { 2148 gfx_v11_0_load_rlcg_microcode(adev); 2149 if (amdgpu_dpm == 1) { 2150 if (version_minor >= 2) 2151 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 2152 if (version_minor == 3) 2153 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 2154 } 2155 2156 return 0; 2157 } 2158 2159 return -EINVAL; 2160 } 2161 2162 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 2163 { 2164 int r; 2165 2166 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2167 gfx_v11_0_init_csb(adev); 2168 2169 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 2170 gfx_v11_0_rlc_enable_srm(adev); 2171 } else { 2172 if (amdgpu_sriov_vf(adev)) { 2173 gfx_v11_0_init_csb(adev); 2174 return 0; 2175 } 2176 2177 adev->gfx.rlc.funcs->stop(adev); 2178 2179 /* disable CG */ 2180 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 2181 2182 /* disable PG */ 2183 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 2184 2185 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2186 /* legacy rlc firmware loading */ 2187 r = gfx_v11_0_rlc_load_microcode(adev); 2188 if (r) 2189 return r; 2190 } 2191 2192 gfx_v11_0_init_csb(adev); 2193 2194 adev->gfx.rlc.funcs->start(adev); 2195 } 2196 return 0; 2197 } 2198 2199 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 2200 { 2201 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2202 uint32_t tmp; 2203 int i; 2204 2205 /* Trigger an invalidation of the L1 instruction caches */ 2206 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2207 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2208 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2209 2210 /* Wait for invalidation complete */ 2211 for (i = 0; i < usec_timeout; i++) { 2212 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2213 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2214 INVALIDATE_CACHE_COMPLETE)) 2215 break; 2216 udelay(1); 2217 } 2218 2219 if (i >= usec_timeout) { 2220 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2221 return -EINVAL; 2222 } 2223 2224 if (amdgpu_emu_mode == 1) 2225 adev->hdp.funcs->flush_hdp(adev, NULL); 2226 2227 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2228 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2229 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2230 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2231 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2232 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2233 2234 /* Program me ucode address into intruction cache address register */ 2235 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2236 lower_32_bits(addr) & 0xFFFFF000); 2237 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2238 upper_32_bits(addr)); 2239 2240 return 0; 2241 } 2242 2243 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2244 { 2245 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2246 uint32_t tmp; 2247 int i; 2248 2249 /* Trigger an invalidation of the L1 instruction caches */ 2250 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2251 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2252 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2253 2254 /* Wait for invalidation complete */ 2255 for (i = 0; i < usec_timeout; i++) { 2256 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2257 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2258 INVALIDATE_CACHE_COMPLETE)) 2259 break; 2260 udelay(1); 2261 } 2262 2263 if (i >= usec_timeout) { 2264 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2265 return -EINVAL; 2266 } 2267 2268 if (amdgpu_emu_mode == 1) 2269 adev->hdp.funcs->flush_hdp(adev, NULL); 2270 2271 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2272 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2273 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2274 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2275 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2276 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2277 2278 /* Program pfp ucode address into intruction cache address register */ 2279 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2280 lower_32_bits(addr) & 0xFFFFF000); 2281 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2282 upper_32_bits(addr)); 2283 2284 return 0; 2285 } 2286 2287 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2288 { 2289 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2290 uint32_t tmp; 2291 int i; 2292 2293 /* Trigger an invalidation of the L1 instruction caches */ 2294 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2295 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2296 2297 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2298 2299 /* Wait for invalidation complete */ 2300 for (i = 0; i < usec_timeout; i++) { 2301 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2302 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2303 INVALIDATE_CACHE_COMPLETE)) 2304 break; 2305 udelay(1); 2306 } 2307 2308 if (i >= usec_timeout) { 2309 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2310 return -EINVAL; 2311 } 2312 2313 if (amdgpu_emu_mode == 1) 2314 adev->hdp.funcs->flush_hdp(adev, NULL); 2315 2316 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2317 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2318 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2319 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2320 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2321 2322 /* Program mec1 ucode address into intruction cache address register */ 2323 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2324 lower_32_bits(addr) & 0xFFFFF000); 2325 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2326 upper_32_bits(addr)); 2327 2328 return 0; 2329 } 2330 2331 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2332 { 2333 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2334 uint32_t tmp; 2335 unsigned i, pipe_id; 2336 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2337 2338 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2339 adev->gfx.pfp_fw->data; 2340 2341 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2342 lower_32_bits(addr)); 2343 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2344 upper_32_bits(addr)); 2345 2346 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2347 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2348 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2349 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2350 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2351 2352 /* 2353 * Programming any of the CP_PFP_IC_BASE registers 2354 * forces invalidation of the ME L1 I$. Wait for the 2355 * invalidation complete 2356 */ 2357 for (i = 0; i < usec_timeout; i++) { 2358 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2359 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2360 INVALIDATE_CACHE_COMPLETE)) 2361 break; 2362 udelay(1); 2363 } 2364 2365 if (i >= usec_timeout) { 2366 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2367 return -EINVAL; 2368 } 2369 2370 /* Prime the L1 instruction caches */ 2371 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2372 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2373 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2374 /* Waiting for cache primed*/ 2375 for (i = 0; i < usec_timeout; i++) { 2376 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2377 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2378 ICACHE_PRIMED)) 2379 break; 2380 udelay(1); 2381 } 2382 2383 if (i >= usec_timeout) { 2384 dev_err(adev->dev, "failed to prime instruction cache\n"); 2385 return -EINVAL; 2386 } 2387 2388 mutex_lock(&adev->srbm_mutex); 2389 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2390 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2391 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2392 (pfp_hdr->ucode_start_addr_hi << 30) | 2393 (pfp_hdr->ucode_start_addr_lo >> 2)); 2394 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2395 pfp_hdr->ucode_start_addr_hi >> 2); 2396 2397 /* 2398 * Program CP_ME_CNTL to reset given PIPE to take 2399 * effect of CP_PFP_PRGRM_CNTR_START. 2400 */ 2401 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2402 if (pipe_id == 0) 2403 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2404 PFP_PIPE0_RESET, 1); 2405 else 2406 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2407 PFP_PIPE1_RESET, 1); 2408 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2409 2410 /* Clear pfp pipe0 reset bit. */ 2411 if (pipe_id == 0) 2412 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2413 PFP_PIPE0_RESET, 0); 2414 else 2415 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2416 PFP_PIPE1_RESET, 0); 2417 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2418 2419 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2420 lower_32_bits(addr2)); 2421 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2422 upper_32_bits(addr2)); 2423 } 2424 soc21_grbm_select(adev, 0, 0, 0, 0); 2425 mutex_unlock(&adev->srbm_mutex); 2426 2427 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2428 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2429 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2430 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2431 2432 /* Invalidate the data caches */ 2433 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2434 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2435 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2436 2437 for (i = 0; i < usec_timeout; i++) { 2438 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2439 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2440 INVALIDATE_DCACHE_COMPLETE)) 2441 break; 2442 udelay(1); 2443 } 2444 2445 if (i >= usec_timeout) { 2446 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2447 return -EINVAL; 2448 } 2449 2450 return 0; 2451 } 2452 2453 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2454 { 2455 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2456 uint32_t tmp; 2457 unsigned i, pipe_id; 2458 const struct gfx_firmware_header_v2_0 *me_hdr; 2459 2460 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2461 adev->gfx.me_fw->data; 2462 2463 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2464 lower_32_bits(addr)); 2465 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2466 upper_32_bits(addr)); 2467 2468 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2469 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2470 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2471 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2472 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2473 2474 /* 2475 * Programming any of the CP_ME_IC_BASE registers 2476 * forces invalidation of the ME L1 I$. Wait for the 2477 * invalidation complete 2478 */ 2479 for (i = 0; i < usec_timeout; i++) { 2480 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2481 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2482 INVALIDATE_CACHE_COMPLETE)) 2483 break; 2484 udelay(1); 2485 } 2486 2487 if (i >= usec_timeout) { 2488 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2489 return -EINVAL; 2490 } 2491 2492 /* Prime the instruction caches */ 2493 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2494 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2495 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2496 2497 /* Waiting for instruction cache primed*/ 2498 for (i = 0; i < usec_timeout; i++) { 2499 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2500 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2501 ICACHE_PRIMED)) 2502 break; 2503 udelay(1); 2504 } 2505 2506 if (i >= usec_timeout) { 2507 dev_err(adev->dev, "failed to prime instruction cache\n"); 2508 return -EINVAL; 2509 } 2510 2511 mutex_lock(&adev->srbm_mutex); 2512 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2513 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2514 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2515 (me_hdr->ucode_start_addr_hi << 30) | 2516 (me_hdr->ucode_start_addr_lo >> 2) ); 2517 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2518 me_hdr->ucode_start_addr_hi>>2); 2519 2520 /* 2521 * Program CP_ME_CNTL to reset given PIPE to take 2522 * effect of CP_PFP_PRGRM_CNTR_START. 2523 */ 2524 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2525 if (pipe_id == 0) 2526 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2527 ME_PIPE0_RESET, 1); 2528 else 2529 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2530 ME_PIPE1_RESET, 1); 2531 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2532 2533 /* Clear pfp pipe0 reset bit. */ 2534 if (pipe_id == 0) 2535 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2536 ME_PIPE0_RESET, 0); 2537 else 2538 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2539 ME_PIPE1_RESET, 0); 2540 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2541 2542 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2543 lower_32_bits(addr2)); 2544 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2545 upper_32_bits(addr2)); 2546 } 2547 soc21_grbm_select(adev, 0, 0, 0, 0); 2548 mutex_unlock(&adev->srbm_mutex); 2549 2550 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2551 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2552 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2553 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2554 2555 /* Invalidate the data caches */ 2556 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2557 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2558 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2559 2560 for (i = 0; i < usec_timeout; i++) { 2561 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2562 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2563 INVALIDATE_DCACHE_COMPLETE)) 2564 break; 2565 udelay(1); 2566 } 2567 2568 if (i >= usec_timeout) { 2569 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2570 return -EINVAL; 2571 } 2572 2573 return 0; 2574 } 2575 2576 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2577 { 2578 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2579 uint32_t tmp; 2580 unsigned i; 2581 const struct gfx_firmware_header_v2_0 *mec_hdr; 2582 2583 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2584 adev->gfx.mec_fw->data; 2585 2586 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2587 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2588 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2589 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2590 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2591 2592 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2593 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2594 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2595 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2596 2597 mutex_lock(&adev->srbm_mutex); 2598 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2599 soc21_grbm_select(adev, 1, i, 0, 0); 2600 2601 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2602 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2603 upper_32_bits(addr2)); 2604 2605 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2606 mec_hdr->ucode_start_addr_lo >> 2 | 2607 mec_hdr->ucode_start_addr_hi << 30); 2608 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2609 mec_hdr->ucode_start_addr_hi >> 2); 2610 2611 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2612 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2613 upper_32_bits(addr)); 2614 } 2615 mutex_unlock(&adev->srbm_mutex); 2616 soc21_grbm_select(adev, 0, 0, 0, 0); 2617 2618 /* Trigger an invalidation of the L1 instruction caches */ 2619 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2620 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2621 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2622 2623 /* Wait for invalidation complete */ 2624 for (i = 0; i < usec_timeout; i++) { 2625 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2626 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2627 INVALIDATE_DCACHE_COMPLETE)) 2628 break; 2629 udelay(1); 2630 } 2631 2632 if (i >= usec_timeout) { 2633 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2634 return -EINVAL; 2635 } 2636 2637 /* Trigger an invalidation of the L1 instruction caches */ 2638 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2639 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2640 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2641 2642 /* Wait for invalidation complete */ 2643 for (i = 0; i < usec_timeout; i++) { 2644 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2645 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2646 INVALIDATE_CACHE_COMPLETE)) 2647 break; 2648 udelay(1); 2649 } 2650 2651 if (i >= usec_timeout) { 2652 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2653 return -EINVAL; 2654 } 2655 2656 return 0; 2657 } 2658 2659 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2660 { 2661 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2662 const struct gfx_firmware_header_v2_0 *me_hdr; 2663 const struct gfx_firmware_header_v2_0 *mec_hdr; 2664 uint32_t pipe_id, tmp; 2665 2666 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2667 adev->gfx.mec_fw->data; 2668 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2669 adev->gfx.me_fw->data; 2670 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2671 adev->gfx.pfp_fw->data; 2672 2673 /* config pfp program start addr */ 2674 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2675 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2676 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2677 (pfp_hdr->ucode_start_addr_hi << 30) | 2678 (pfp_hdr->ucode_start_addr_lo >> 2)); 2679 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2680 pfp_hdr->ucode_start_addr_hi >> 2); 2681 } 2682 soc21_grbm_select(adev, 0, 0, 0, 0); 2683 2684 /* reset pfp pipe */ 2685 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2686 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2687 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2688 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2689 2690 /* clear pfp pipe reset */ 2691 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2692 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2693 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2694 2695 /* config me program start addr */ 2696 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2697 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2698 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2699 (me_hdr->ucode_start_addr_hi << 30) | 2700 (me_hdr->ucode_start_addr_lo >> 2) ); 2701 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2702 me_hdr->ucode_start_addr_hi>>2); 2703 } 2704 soc21_grbm_select(adev, 0, 0, 0, 0); 2705 2706 /* reset me pipe */ 2707 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2708 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2709 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2710 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2711 2712 /* clear me pipe reset */ 2713 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2714 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2715 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2716 2717 /* config mec program start addr */ 2718 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2719 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2720 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2721 mec_hdr->ucode_start_addr_lo >> 2 | 2722 mec_hdr->ucode_start_addr_hi << 30); 2723 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2724 mec_hdr->ucode_start_addr_hi >> 2); 2725 } 2726 soc21_grbm_select(adev, 0, 0, 0, 0); 2727 } 2728 2729 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2730 { 2731 uint32_t cp_status; 2732 uint32_t bootload_status; 2733 int i, r; 2734 uint64_t addr, addr2; 2735 2736 for (i = 0; i < adev->usec_timeout; i++) { 2737 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2738 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2739 if ((cp_status == 0) && 2740 (REG_GET_FIELD(bootload_status, 2741 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2742 break; 2743 } 2744 udelay(1); 2745 } 2746 2747 if (i >= adev->usec_timeout) { 2748 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2749 return -ETIMEDOUT; 2750 } 2751 2752 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2753 if (adev->gfx.rs64_enable) { 2754 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2755 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2756 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2757 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2758 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2759 if (r) 2760 return r; 2761 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2762 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2763 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2764 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2765 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2766 if (r) 2767 return r; 2768 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2769 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2770 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2771 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2772 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2773 if (r) 2774 return r; 2775 } else { 2776 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2777 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2778 r = gfx_v11_0_config_me_cache(adev, addr); 2779 if (r) 2780 return r; 2781 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2782 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2783 r = gfx_v11_0_config_pfp_cache(adev, addr); 2784 if (r) 2785 return r; 2786 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2787 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2788 r = gfx_v11_0_config_mec_cache(adev, addr); 2789 if (r) 2790 return r; 2791 } 2792 } 2793 2794 return 0; 2795 } 2796 2797 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2798 { 2799 int i; 2800 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2801 2802 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2803 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2804 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2805 2806 for (i = 0; i < adev->usec_timeout; i++) { 2807 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2808 break; 2809 udelay(1); 2810 } 2811 2812 if (i >= adev->usec_timeout) 2813 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2814 2815 return 0; 2816 } 2817 2818 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2819 { 2820 int r; 2821 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2822 const __le32 *fw_data; 2823 unsigned i, fw_size; 2824 2825 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2826 adev->gfx.pfp_fw->data; 2827 2828 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2829 2830 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2831 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2832 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2833 2834 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2835 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2836 &adev->gfx.pfp.pfp_fw_obj, 2837 &adev->gfx.pfp.pfp_fw_gpu_addr, 2838 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2839 if (r) { 2840 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2841 gfx_v11_0_pfp_fini(adev); 2842 return r; 2843 } 2844 2845 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2846 2847 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2848 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2849 2850 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2851 2852 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2853 2854 for (i = 0; i < pfp_hdr->jt_size; i++) 2855 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2856 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2857 2858 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2859 2860 return 0; 2861 } 2862 2863 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2864 { 2865 int r; 2866 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2867 const __le32 *fw_ucode, *fw_data; 2868 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2869 uint32_t tmp; 2870 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2871 2872 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2873 adev->gfx.pfp_fw->data; 2874 2875 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2876 2877 /* instruction */ 2878 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2879 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2880 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2881 /* data */ 2882 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2883 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2884 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2885 2886 /* 64kb align */ 2887 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2888 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2889 &adev->gfx.pfp.pfp_fw_obj, 2890 &adev->gfx.pfp.pfp_fw_gpu_addr, 2891 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2892 if (r) { 2893 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2894 gfx_v11_0_pfp_fini(adev); 2895 return r; 2896 } 2897 2898 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2899 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2900 &adev->gfx.pfp.pfp_fw_data_obj, 2901 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2902 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2903 if (r) { 2904 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2905 gfx_v11_0_pfp_fini(adev); 2906 return r; 2907 } 2908 2909 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2910 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2911 2912 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2913 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2914 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2915 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2916 2917 if (amdgpu_emu_mode == 1) 2918 adev->hdp.funcs->flush_hdp(adev, NULL); 2919 2920 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2921 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2922 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2923 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2924 2925 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2926 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2927 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2928 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2929 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2930 2931 /* 2932 * Programming any of the CP_PFP_IC_BASE registers 2933 * forces invalidation of the ME L1 I$. Wait for the 2934 * invalidation complete 2935 */ 2936 for (i = 0; i < usec_timeout; i++) { 2937 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2938 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2939 INVALIDATE_CACHE_COMPLETE)) 2940 break; 2941 udelay(1); 2942 } 2943 2944 if (i >= usec_timeout) { 2945 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2946 return -EINVAL; 2947 } 2948 2949 /* Prime the L1 instruction caches */ 2950 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2951 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2952 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2953 /* Waiting for cache primed*/ 2954 for (i = 0; i < usec_timeout; i++) { 2955 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2956 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2957 ICACHE_PRIMED)) 2958 break; 2959 udelay(1); 2960 } 2961 2962 if (i >= usec_timeout) { 2963 dev_err(adev->dev, "failed to prime instruction cache\n"); 2964 return -EINVAL; 2965 } 2966 2967 mutex_lock(&adev->srbm_mutex); 2968 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2969 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2970 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2971 (pfp_hdr->ucode_start_addr_hi << 30) | 2972 (pfp_hdr->ucode_start_addr_lo >> 2) ); 2973 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2974 pfp_hdr->ucode_start_addr_hi>>2); 2975 2976 /* 2977 * Program CP_ME_CNTL to reset given PIPE to take 2978 * effect of CP_PFP_PRGRM_CNTR_START. 2979 */ 2980 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2981 if (pipe_id == 0) 2982 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2983 PFP_PIPE0_RESET, 1); 2984 else 2985 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2986 PFP_PIPE1_RESET, 1); 2987 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2988 2989 /* Clear pfp pipe0 reset bit. */ 2990 if (pipe_id == 0) 2991 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2992 PFP_PIPE0_RESET, 0); 2993 else 2994 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2995 PFP_PIPE1_RESET, 0); 2996 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2997 2998 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2999 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3000 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 3001 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 3002 } 3003 soc21_grbm_select(adev, 0, 0, 0, 0); 3004 mutex_unlock(&adev->srbm_mutex); 3005 3006 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3007 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3008 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3009 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3010 3011 /* Invalidate the data caches */ 3012 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3013 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3014 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3015 3016 for (i = 0; i < usec_timeout; i++) { 3017 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3018 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3019 INVALIDATE_DCACHE_COMPLETE)) 3020 break; 3021 udelay(1); 3022 } 3023 3024 if (i >= usec_timeout) { 3025 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3026 return -EINVAL; 3027 } 3028 3029 return 0; 3030 } 3031 3032 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 3033 { 3034 int r; 3035 const struct gfx_firmware_header_v1_0 *me_hdr; 3036 const __le32 *fw_data; 3037 unsigned i, fw_size; 3038 3039 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3040 adev->gfx.me_fw->data; 3041 3042 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3043 3044 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3045 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3046 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 3047 3048 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 3049 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3050 &adev->gfx.me.me_fw_obj, 3051 &adev->gfx.me.me_fw_gpu_addr, 3052 (void **)&adev->gfx.me.me_fw_ptr); 3053 if (r) { 3054 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 3055 gfx_v11_0_me_fini(adev); 3056 return r; 3057 } 3058 3059 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 3060 3061 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3062 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3063 3064 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 3065 3066 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 3067 3068 for (i = 0; i < me_hdr->jt_size; i++) 3069 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 3070 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 3071 3072 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 3073 3074 return 0; 3075 } 3076 3077 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 3078 { 3079 int r; 3080 const struct gfx_firmware_header_v2_0 *me_hdr; 3081 const __le32 *fw_ucode, *fw_data; 3082 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 3083 uint32_t tmp; 3084 uint32_t usec_timeout = 50000; /* wait for 50ms */ 3085 3086 me_hdr = (const struct gfx_firmware_header_v2_0 *) 3087 adev->gfx.me_fw->data; 3088 3089 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3090 3091 /* instruction */ 3092 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 3093 le32_to_cpu(me_hdr->ucode_offset_bytes)); 3094 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 3095 /* data */ 3096 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 3097 le32_to_cpu(me_hdr->data_offset_bytes)); 3098 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 3099 3100 /* 64kb align*/ 3101 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3102 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3103 &adev->gfx.me.me_fw_obj, 3104 &adev->gfx.me.me_fw_gpu_addr, 3105 (void **)&adev->gfx.me.me_fw_ptr); 3106 if (r) { 3107 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 3108 gfx_v11_0_me_fini(adev); 3109 return r; 3110 } 3111 3112 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3113 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3114 &adev->gfx.me.me_fw_data_obj, 3115 &adev->gfx.me.me_fw_data_gpu_addr, 3116 (void **)&adev->gfx.me.me_fw_data_ptr); 3117 if (r) { 3118 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 3119 gfx_v11_0_pfp_fini(adev); 3120 return r; 3121 } 3122 3123 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 3124 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 3125 3126 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 3127 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 3128 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 3129 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 3130 3131 if (amdgpu_emu_mode == 1) 3132 adev->hdp.funcs->flush_hdp(adev, NULL); 3133 3134 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 3135 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3136 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 3137 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 3138 3139 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 3140 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 3141 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 3142 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 3143 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 3144 3145 /* 3146 * Programming any of the CP_ME_IC_BASE registers 3147 * forces invalidation of the ME L1 I$. Wait for the 3148 * invalidation complete 3149 */ 3150 for (i = 0; i < usec_timeout; i++) { 3151 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3152 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3153 INVALIDATE_CACHE_COMPLETE)) 3154 break; 3155 udelay(1); 3156 } 3157 3158 if (i >= usec_timeout) { 3159 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3160 return -EINVAL; 3161 } 3162 3163 /* Prime the instruction caches */ 3164 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3165 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 3166 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 3167 3168 /* Waiting for instruction cache primed*/ 3169 for (i = 0; i < usec_timeout; i++) { 3170 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 3171 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 3172 ICACHE_PRIMED)) 3173 break; 3174 udelay(1); 3175 } 3176 3177 if (i >= usec_timeout) { 3178 dev_err(adev->dev, "failed to prime instruction cache\n"); 3179 return -EINVAL; 3180 } 3181 3182 mutex_lock(&adev->srbm_mutex); 3183 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 3184 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 3185 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 3186 (me_hdr->ucode_start_addr_hi << 30) | 3187 (me_hdr->ucode_start_addr_lo >> 2) ); 3188 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 3189 me_hdr->ucode_start_addr_hi>>2); 3190 3191 /* 3192 * Program CP_ME_CNTL to reset given PIPE to take 3193 * effect of CP_PFP_PRGRM_CNTR_START. 3194 */ 3195 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 3196 if (pipe_id == 0) 3197 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3198 ME_PIPE0_RESET, 1); 3199 else 3200 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3201 ME_PIPE1_RESET, 1); 3202 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3203 3204 /* Clear pfp pipe0 reset bit. */ 3205 if (pipe_id == 0) 3206 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3207 ME_PIPE0_RESET, 0); 3208 else 3209 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3210 ME_PIPE1_RESET, 0); 3211 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3212 3213 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3214 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3215 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3216 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3217 } 3218 soc21_grbm_select(adev, 0, 0, 0, 0); 3219 mutex_unlock(&adev->srbm_mutex); 3220 3221 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3222 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3223 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3224 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3225 3226 /* Invalidate the data caches */ 3227 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3228 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3229 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3230 3231 for (i = 0; i < usec_timeout; i++) { 3232 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3233 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3234 INVALIDATE_DCACHE_COMPLETE)) 3235 break; 3236 udelay(1); 3237 } 3238 3239 if (i >= usec_timeout) { 3240 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3241 return -EINVAL; 3242 } 3243 3244 return 0; 3245 } 3246 3247 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3248 { 3249 int r; 3250 3251 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3252 return -EINVAL; 3253 3254 gfx_v11_0_cp_gfx_enable(adev, false); 3255 3256 if (adev->gfx.rs64_enable) 3257 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3258 else 3259 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3260 if (r) { 3261 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3262 return r; 3263 } 3264 3265 if (adev->gfx.rs64_enable) 3266 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3267 else 3268 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3269 if (r) { 3270 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3271 return r; 3272 } 3273 3274 return 0; 3275 } 3276 3277 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3278 { 3279 struct amdgpu_ring *ring; 3280 const struct cs_section_def *sect = NULL; 3281 const struct cs_extent_def *ext = NULL; 3282 int r, i; 3283 int ctx_reg_offset; 3284 3285 /* init the CP */ 3286 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3287 adev->gfx.config.max_hw_contexts - 1); 3288 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3289 3290 if (!amdgpu_async_gfx_ring) 3291 gfx_v11_0_cp_gfx_enable(adev, true); 3292 3293 ring = &adev->gfx.gfx_ring[0]; 3294 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3295 if (r) { 3296 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3297 return r; 3298 } 3299 3300 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3301 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3302 3303 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3304 amdgpu_ring_write(ring, 0x80000000); 3305 amdgpu_ring_write(ring, 0x80000000); 3306 3307 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3308 for (ext = sect->section; ext->extent != NULL; ++ext) { 3309 if (sect->id == SECT_CONTEXT) { 3310 amdgpu_ring_write(ring, 3311 PACKET3(PACKET3_SET_CONTEXT_REG, 3312 ext->reg_count)); 3313 amdgpu_ring_write(ring, ext->reg_index - 3314 PACKET3_SET_CONTEXT_REG_START); 3315 for (i = 0; i < ext->reg_count; i++) 3316 amdgpu_ring_write(ring, ext->extent[i]); 3317 } 3318 } 3319 } 3320 3321 ctx_reg_offset = 3322 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3323 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3324 amdgpu_ring_write(ring, ctx_reg_offset); 3325 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3326 3327 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3328 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3329 3330 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3331 amdgpu_ring_write(ring, 0); 3332 3333 amdgpu_ring_commit(ring); 3334 3335 /* submit cs packet to copy state 0 to next available state */ 3336 if (adev->gfx.num_gfx_rings > 1) { 3337 /* maximum supported gfx ring is 2 */ 3338 ring = &adev->gfx.gfx_ring[1]; 3339 r = amdgpu_ring_alloc(ring, 2); 3340 if (r) { 3341 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3342 return r; 3343 } 3344 3345 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3346 amdgpu_ring_write(ring, 0); 3347 3348 amdgpu_ring_commit(ring); 3349 } 3350 return 0; 3351 } 3352 3353 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3354 CP_PIPE_ID pipe) 3355 { 3356 u32 tmp; 3357 3358 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3359 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3360 3361 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3362 } 3363 3364 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3365 struct amdgpu_ring *ring) 3366 { 3367 u32 tmp; 3368 3369 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3370 if (ring->use_doorbell) { 3371 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3372 DOORBELL_OFFSET, ring->doorbell_index); 3373 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3374 DOORBELL_EN, 1); 3375 } else { 3376 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3377 DOORBELL_EN, 0); 3378 } 3379 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3380 3381 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3382 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3383 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3384 3385 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3386 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3387 } 3388 3389 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3390 { 3391 struct amdgpu_ring *ring; 3392 u32 tmp; 3393 u32 rb_bufsz; 3394 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3395 u32 i; 3396 3397 /* Set the write pointer delay */ 3398 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3399 3400 /* set the RB to use vmid 0 */ 3401 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3402 3403 /* Init gfx ring 0 for pipe 0 */ 3404 mutex_lock(&adev->srbm_mutex); 3405 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3406 3407 /* Set ring buffer size */ 3408 ring = &adev->gfx.gfx_ring[0]; 3409 rb_bufsz = order_base_2(ring->ring_size / 8); 3410 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3411 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3412 #ifdef __BIG_ENDIAN 3413 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3414 #endif 3415 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3416 3417 /* Initialize the ring buffer's write pointers */ 3418 ring->wptr = 0; 3419 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3420 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3421 3422 /* set the wb address wether it's enabled or not */ 3423 rptr_addr = ring->rptr_gpu_addr; 3424 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3425 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3426 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3427 3428 wptr_gpu_addr = ring->wptr_gpu_addr; 3429 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3430 lower_32_bits(wptr_gpu_addr)); 3431 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3432 upper_32_bits(wptr_gpu_addr)); 3433 3434 mdelay(1); 3435 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3436 3437 rb_addr = ring->gpu_addr >> 8; 3438 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3439 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3440 3441 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3442 3443 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3444 mutex_unlock(&adev->srbm_mutex); 3445 3446 /* Init gfx ring 1 for pipe 1 */ 3447 if (adev->gfx.num_gfx_rings > 1) { 3448 mutex_lock(&adev->srbm_mutex); 3449 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3450 /* maximum supported gfx ring is 2 */ 3451 ring = &adev->gfx.gfx_ring[1]; 3452 rb_bufsz = order_base_2(ring->ring_size / 8); 3453 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3454 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3455 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3456 /* Initialize the ring buffer's write pointers */ 3457 ring->wptr = 0; 3458 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3459 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3460 /* Set the wb address wether it's enabled or not */ 3461 rptr_addr = ring->rptr_gpu_addr; 3462 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3463 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3464 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3465 wptr_gpu_addr = ring->wptr_gpu_addr; 3466 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3467 lower_32_bits(wptr_gpu_addr)); 3468 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3469 upper_32_bits(wptr_gpu_addr)); 3470 3471 mdelay(1); 3472 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3473 3474 rb_addr = ring->gpu_addr >> 8; 3475 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3476 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3477 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3478 3479 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3480 mutex_unlock(&adev->srbm_mutex); 3481 } 3482 /* Switch to pipe 0 */ 3483 mutex_lock(&adev->srbm_mutex); 3484 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3485 mutex_unlock(&adev->srbm_mutex); 3486 3487 /* start the ring */ 3488 gfx_v11_0_cp_gfx_start(adev); 3489 3490 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3491 ring = &adev->gfx.gfx_ring[i]; 3492 ring->sched.ready = true; 3493 } 3494 3495 return 0; 3496 } 3497 3498 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3499 { 3500 u32 data; 3501 3502 if (adev->gfx.rs64_enable) { 3503 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3504 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3505 enable ? 0 : 1); 3506 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3507 enable ? 0 : 1); 3508 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3509 enable ? 0 : 1); 3510 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3511 enable ? 0 : 1); 3512 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3513 enable ? 0 : 1); 3514 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3515 enable ? 1 : 0); 3516 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3517 enable ? 1 : 0); 3518 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3519 enable ? 1 : 0); 3520 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3521 enable ? 1 : 0); 3522 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3523 enable ? 0 : 1); 3524 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3525 } else { 3526 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3527 3528 if (enable) { 3529 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3530 if (!adev->enable_mes_kiq) 3531 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3532 MEC_ME2_HALT, 0); 3533 } else { 3534 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3535 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3536 } 3537 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3538 } 3539 3540 adev->gfx.kiq.ring.sched.ready = enable; 3541 3542 udelay(50); 3543 } 3544 3545 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3546 { 3547 const struct gfx_firmware_header_v1_0 *mec_hdr; 3548 const __le32 *fw_data; 3549 unsigned i, fw_size; 3550 u32 *fw = NULL; 3551 int r; 3552 3553 if (!adev->gfx.mec_fw) 3554 return -EINVAL; 3555 3556 gfx_v11_0_cp_compute_enable(adev, false); 3557 3558 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3559 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3560 3561 fw_data = (const __le32 *) 3562 (adev->gfx.mec_fw->data + 3563 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3564 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3565 3566 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3567 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3568 &adev->gfx.mec.mec_fw_obj, 3569 &adev->gfx.mec.mec_fw_gpu_addr, 3570 (void **)&fw); 3571 if (r) { 3572 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3573 gfx_v11_0_mec_fini(adev); 3574 return r; 3575 } 3576 3577 memcpy(fw, fw_data, fw_size); 3578 3579 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3580 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3581 3582 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3583 3584 /* MEC1 */ 3585 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3586 3587 for (i = 0; i < mec_hdr->jt_size; i++) 3588 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3589 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3590 3591 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3592 3593 return 0; 3594 } 3595 3596 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3597 { 3598 const struct gfx_firmware_header_v2_0 *mec_hdr; 3599 const __le32 *fw_ucode, *fw_data; 3600 u32 tmp, fw_ucode_size, fw_data_size; 3601 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3602 u32 *fw_ucode_ptr, *fw_data_ptr; 3603 int r; 3604 3605 if (!adev->gfx.mec_fw) 3606 return -EINVAL; 3607 3608 gfx_v11_0_cp_compute_enable(adev, false); 3609 3610 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3611 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3612 3613 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3614 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3615 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3616 3617 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3618 le32_to_cpu(mec_hdr->data_offset_bytes)); 3619 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3620 3621 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3622 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3623 &adev->gfx.mec.mec_fw_obj, 3624 &adev->gfx.mec.mec_fw_gpu_addr, 3625 (void **)&fw_ucode_ptr); 3626 if (r) { 3627 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3628 gfx_v11_0_mec_fini(adev); 3629 return r; 3630 } 3631 3632 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3633 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 3634 &adev->gfx.mec.mec_fw_data_obj, 3635 &adev->gfx.mec.mec_fw_data_gpu_addr, 3636 (void **)&fw_data_ptr); 3637 if (r) { 3638 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3639 gfx_v11_0_mec_fini(adev); 3640 return r; 3641 } 3642 3643 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3644 memcpy(fw_data_ptr, fw_data, fw_data_size); 3645 3646 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3647 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3648 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3649 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3650 3651 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3652 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3653 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3654 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3655 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3656 3657 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3658 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3659 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3660 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3661 3662 mutex_lock(&adev->srbm_mutex); 3663 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3664 soc21_grbm_select(adev, 1, i, 0, 0); 3665 3666 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3667 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3668 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3669 3670 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3671 mec_hdr->ucode_start_addr_lo >> 2 | 3672 mec_hdr->ucode_start_addr_hi << 30); 3673 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3674 mec_hdr->ucode_start_addr_hi >> 2); 3675 3676 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3677 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3678 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3679 } 3680 mutex_unlock(&adev->srbm_mutex); 3681 soc21_grbm_select(adev, 0, 0, 0, 0); 3682 3683 /* Trigger an invalidation of the L1 instruction caches */ 3684 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3685 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3686 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3687 3688 /* Wait for invalidation complete */ 3689 for (i = 0; i < usec_timeout; i++) { 3690 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3691 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3692 INVALIDATE_DCACHE_COMPLETE)) 3693 break; 3694 udelay(1); 3695 } 3696 3697 if (i >= usec_timeout) { 3698 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3699 return -EINVAL; 3700 } 3701 3702 /* Trigger an invalidation of the L1 instruction caches */ 3703 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3704 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3705 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3706 3707 /* Wait for invalidation complete */ 3708 for (i = 0; i < usec_timeout; i++) { 3709 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3710 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3711 INVALIDATE_CACHE_COMPLETE)) 3712 break; 3713 udelay(1); 3714 } 3715 3716 if (i >= usec_timeout) { 3717 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3718 return -EINVAL; 3719 } 3720 3721 return 0; 3722 } 3723 3724 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3725 { 3726 uint32_t tmp; 3727 struct amdgpu_device *adev = ring->adev; 3728 3729 /* tell RLC which is KIQ queue */ 3730 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3731 tmp &= 0xffffff00; 3732 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3733 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3734 tmp |= 0x80; 3735 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3736 } 3737 3738 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3739 { 3740 /* set graphics engine doorbell range */ 3741 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3742 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3743 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3744 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3745 3746 /* set compute engine doorbell range */ 3747 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3748 (adev->doorbell_index.kiq * 2) << 2); 3749 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3750 (adev->doorbell_index.userqueue_end * 2) << 2); 3751 } 3752 3753 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3754 struct amdgpu_mqd_prop *prop) 3755 { 3756 struct v11_gfx_mqd *mqd = m; 3757 uint64_t hqd_gpu_addr, wb_gpu_addr; 3758 uint32_t tmp; 3759 uint32_t rb_bufsz; 3760 3761 /* set up gfx hqd wptr */ 3762 mqd->cp_gfx_hqd_wptr = 0; 3763 mqd->cp_gfx_hqd_wptr_hi = 0; 3764 3765 /* set the pointer to the MQD */ 3766 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3767 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3768 3769 /* set up mqd control */ 3770 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3771 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3772 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3773 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3774 mqd->cp_gfx_mqd_control = tmp; 3775 3776 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3777 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3778 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3779 mqd->cp_gfx_hqd_vmid = 0; 3780 3781 /* set up default queue priority level 3782 * 0x0 = low priority, 0x1 = high priority */ 3783 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3784 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3785 mqd->cp_gfx_hqd_queue_priority = tmp; 3786 3787 /* set up time quantum */ 3788 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3789 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3790 mqd->cp_gfx_hqd_quantum = tmp; 3791 3792 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3793 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3794 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3795 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3796 3797 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3798 wb_gpu_addr = prop->rptr_gpu_addr; 3799 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3800 mqd->cp_gfx_hqd_rptr_addr_hi = 3801 upper_32_bits(wb_gpu_addr) & 0xffff; 3802 3803 /* set up rb_wptr_poll addr */ 3804 wb_gpu_addr = prop->wptr_gpu_addr; 3805 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3806 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3807 3808 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3809 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3810 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3811 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3812 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3813 #ifdef __BIG_ENDIAN 3814 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3815 #endif 3816 mqd->cp_gfx_hqd_cntl = tmp; 3817 3818 /* set up cp_doorbell_control */ 3819 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3820 if (prop->use_doorbell) { 3821 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3822 DOORBELL_OFFSET, prop->doorbell_index); 3823 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3824 DOORBELL_EN, 1); 3825 } else 3826 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3827 DOORBELL_EN, 0); 3828 mqd->cp_rb_doorbell_control = tmp; 3829 3830 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3831 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3832 3833 /* active the queue */ 3834 mqd->cp_gfx_hqd_active = 1; 3835 3836 return 0; 3837 } 3838 3839 #ifdef BRING_UP_DEBUG 3840 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3841 { 3842 struct amdgpu_device *adev = ring->adev; 3843 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3844 3845 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3846 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3847 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3848 3849 /* set GFX_MQD_BASE */ 3850 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3851 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3852 3853 /* set GFX_MQD_CONTROL */ 3854 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3855 3856 /* set GFX_HQD_VMID to 0 */ 3857 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3858 3859 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY, 3860 mqd->cp_gfx_hqd_queue_priority); 3861 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3862 3863 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3864 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3865 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3866 3867 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3868 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3869 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3870 3871 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3872 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3873 3874 /* set RB_WPTR_POLL_ADDR */ 3875 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3876 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3877 3878 /* set RB_DOORBELL_CONTROL */ 3879 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3880 3881 /* active the queue */ 3882 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3883 3884 return 0; 3885 } 3886 #endif 3887 3888 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3889 { 3890 struct amdgpu_device *adev = ring->adev; 3891 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3892 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3893 3894 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3895 memset((void *)mqd, 0, sizeof(*mqd)); 3896 mutex_lock(&adev->srbm_mutex); 3897 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3898 amdgpu_ring_init_mqd(ring); 3899 #ifdef BRING_UP_DEBUG 3900 gfx_v11_0_gfx_queue_init_register(ring); 3901 #endif 3902 soc21_grbm_select(adev, 0, 0, 0, 0); 3903 mutex_unlock(&adev->srbm_mutex); 3904 if (adev->gfx.me.mqd_backup[mqd_idx]) 3905 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3906 } else if (amdgpu_in_reset(adev)) { 3907 /* reset mqd with the backup copy */ 3908 if (adev->gfx.me.mqd_backup[mqd_idx]) 3909 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3910 /* reset the ring */ 3911 ring->wptr = 0; 3912 *ring->wptr_cpu_addr = 0; 3913 amdgpu_ring_clear_ring(ring); 3914 #ifdef BRING_UP_DEBUG 3915 mutex_lock(&adev->srbm_mutex); 3916 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3917 gfx_v11_0_gfx_queue_init_register(ring); 3918 soc21_grbm_select(adev, 0, 0, 0, 0); 3919 mutex_unlock(&adev->srbm_mutex); 3920 #endif 3921 } else { 3922 amdgpu_ring_clear_ring(ring); 3923 } 3924 3925 return 0; 3926 } 3927 3928 #ifndef BRING_UP_DEBUG 3929 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev) 3930 { 3931 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3932 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3933 int r, i; 3934 3935 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3936 return -EINVAL; 3937 3938 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3939 adev->gfx.num_gfx_rings); 3940 if (r) { 3941 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3942 return r; 3943 } 3944 3945 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3946 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3947 3948 return amdgpu_ring_test_helper(kiq_ring); 3949 } 3950 #endif 3951 3952 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3953 { 3954 int r, i; 3955 struct amdgpu_ring *ring; 3956 3957 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3958 ring = &adev->gfx.gfx_ring[i]; 3959 3960 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3961 if (unlikely(r != 0)) 3962 goto done; 3963 3964 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3965 if (!r) { 3966 r = gfx_v11_0_gfx_init_queue(ring); 3967 amdgpu_bo_kunmap(ring->mqd_obj); 3968 ring->mqd_ptr = NULL; 3969 } 3970 amdgpu_bo_unreserve(ring->mqd_obj); 3971 if (r) 3972 goto done; 3973 } 3974 #ifndef BRING_UP_DEBUG 3975 r = gfx_v11_0_kiq_enable_kgq(adev); 3976 if (r) 3977 goto done; 3978 #endif 3979 r = gfx_v11_0_cp_gfx_start(adev); 3980 if (r) 3981 goto done; 3982 3983 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3984 ring = &adev->gfx.gfx_ring[i]; 3985 ring->sched.ready = true; 3986 } 3987 done: 3988 return r; 3989 } 3990 3991 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3992 struct amdgpu_mqd_prop *prop) 3993 { 3994 struct v11_compute_mqd *mqd = m; 3995 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3996 uint32_t tmp; 3997 3998 mqd->header = 0xC0310800; 3999 mqd->compute_pipelinestat_enable = 0x00000001; 4000 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4001 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4002 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4003 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4004 mqd->compute_misc_reserved = 0x00000007; 4005 4006 eop_base_addr = prop->eop_gpu_addr >> 8; 4007 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4008 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4009 4010 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4011 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 4012 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4013 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 4014 4015 mqd->cp_hqd_eop_control = tmp; 4016 4017 /* enable doorbell? */ 4018 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4019 4020 if (prop->use_doorbell) { 4021 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4022 DOORBELL_OFFSET, prop->doorbell_index); 4023 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4024 DOORBELL_EN, 1); 4025 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4026 DOORBELL_SOURCE, 0); 4027 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4028 DOORBELL_HIT, 0); 4029 } else { 4030 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4031 DOORBELL_EN, 0); 4032 } 4033 4034 mqd->cp_hqd_pq_doorbell_control = tmp; 4035 4036 /* disable the queue if it's active */ 4037 mqd->cp_hqd_dequeue_request = 0; 4038 mqd->cp_hqd_pq_rptr = 0; 4039 mqd->cp_hqd_pq_wptr_lo = 0; 4040 mqd->cp_hqd_pq_wptr_hi = 0; 4041 4042 /* set the pointer to the MQD */ 4043 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 4044 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 4045 4046 /* set MQD vmid to 0 */ 4047 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 4048 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4049 mqd->cp_mqd_control = tmp; 4050 4051 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4052 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 4053 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4054 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4055 4056 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4057 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 4058 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4059 (order_base_2(prop->queue_size / 4) - 1)); 4060 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4061 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 4062 #ifdef __BIG_ENDIAN 4063 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 4064 #endif 4065 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 4066 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 4067 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4068 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4069 mqd->cp_hqd_pq_control = tmp; 4070 4071 /* set the wb address whether it's enabled or not */ 4072 wb_gpu_addr = prop->rptr_gpu_addr; 4073 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4074 mqd->cp_hqd_pq_rptr_report_addr_hi = 4075 upper_32_bits(wb_gpu_addr) & 0xffff; 4076 4077 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4078 wb_gpu_addr = prop->wptr_gpu_addr; 4079 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4080 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4081 4082 tmp = 0; 4083 /* enable the doorbell if requested */ 4084 if (prop->use_doorbell) { 4085 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 4086 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4087 DOORBELL_OFFSET, prop->doorbell_index); 4088 4089 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4090 DOORBELL_EN, 1); 4091 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4092 DOORBELL_SOURCE, 0); 4093 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4094 DOORBELL_HIT, 0); 4095 } 4096 4097 mqd->cp_hqd_pq_doorbell_control = tmp; 4098 4099 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4100 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 4101 4102 /* set the vmid for the queue */ 4103 mqd->cp_hqd_vmid = 0; 4104 4105 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 4106 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 4107 mqd->cp_hqd_persistent_state = tmp; 4108 4109 /* set MIN_IB_AVAIL_SIZE */ 4110 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 4111 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4112 mqd->cp_hqd_ib_control = tmp; 4113 4114 /* set static priority for a compute queue/ring */ 4115 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 4116 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 4117 4118 mqd->cp_hqd_active = prop->hqd_active; 4119 4120 return 0; 4121 } 4122 4123 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 4124 { 4125 struct amdgpu_device *adev = ring->adev; 4126 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4127 int j; 4128 4129 /* inactivate the queue */ 4130 if (amdgpu_sriov_vf(adev)) 4131 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 4132 4133 /* disable wptr polling */ 4134 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4135 4136 /* write the EOP addr */ 4137 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 4138 mqd->cp_hqd_eop_base_addr_lo); 4139 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 4140 mqd->cp_hqd_eop_base_addr_hi); 4141 4142 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4143 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 4144 mqd->cp_hqd_eop_control); 4145 4146 /* enable doorbell? */ 4147 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4148 mqd->cp_hqd_pq_doorbell_control); 4149 4150 /* disable the queue if it's active */ 4151 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 4152 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 4153 for (j = 0; j < adev->usec_timeout; j++) { 4154 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 4155 break; 4156 udelay(1); 4157 } 4158 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 4159 mqd->cp_hqd_dequeue_request); 4160 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 4161 mqd->cp_hqd_pq_rptr); 4162 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4163 mqd->cp_hqd_pq_wptr_lo); 4164 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4165 mqd->cp_hqd_pq_wptr_hi); 4166 } 4167 4168 /* set the pointer to the MQD */ 4169 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 4170 mqd->cp_mqd_base_addr_lo); 4171 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 4172 mqd->cp_mqd_base_addr_hi); 4173 4174 /* set MQD vmid to 0 */ 4175 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 4176 mqd->cp_mqd_control); 4177 4178 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4179 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 4180 mqd->cp_hqd_pq_base_lo); 4181 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 4182 mqd->cp_hqd_pq_base_hi); 4183 4184 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4185 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 4186 mqd->cp_hqd_pq_control); 4187 4188 /* set the wb address whether it's enabled or not */ 4189 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 4190 mqd->cp_hqd_pq_rptr_report_addr_lo); 4191 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4192 mqd->cp_hqd_pq_rptr_report_addr_hi); 4193 4194 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4195 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 4196 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4197 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4198 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4199 4200 /* enable the doorbell if requested */ 4201 if (ring->use_doorbell) { 4202 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4203 (adev->doorbell_index.kiq * 2) << 2); 4204 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4205 (adev->doorbell_index.userqueue_end * 2) << 2); 4206 } 4207 4208 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4209 mqd->cp_hqd_pq_doorbell_control); 4210 4211 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4212 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4213 mqd->cp_hqd_pq_wptr_lo); 4214 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4215 mqd->cp_hqd_pq_wptr_hi); 4216 4217 /* set the vmid for the queue */ 4218 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4219 4220 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4221 mqd->cp_hqd_persistent_state); 4222 4223 /* activate the queue */ 4224 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4225 mqd->cp_hqd_active); 4226 4227 if (ring->use_doorbell) 4228 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4229 4230 return 0; 4231 } 4232 4233 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4234 { 4235 struct amdgpu_device *adev = ring->adev; 4236 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4237 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 4238 4239 gfx_v11_0_kiq_setting(ring); 4240 4241 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4242 /* reset MQD to a clean status */ 4243 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4244 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4245 4246 /* reset ring buffer */ 4247 ring->wptr = 0; 4248 amdgpu_ring_clear_ring(ring); 4249 4250 mutex_lock(&adev->srbm_mutex); 4251 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4252 gfx_v11_0_kiq_init_register(ring); 4253 soc21_grbm_select(adev, 0, 0, 0, 0); 4254 mutex_unlock(&adev->srbm_mutex); 4255 } else { 4256 memset((void *)mqd, 0, sizeof(*mqd)); 4257 mutex_lock(&adev->srbm_mutex); 4258 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4259 amdgpu_ring_init_mqd(ring); 4260 gfx_v11_0_kiq_init_register(ring); 4261 soc21_grbm_select(adev, 0, 0, 0, 0); 4262 mutex_unlock(&adev->srbm_mutex); 4263 4264 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4265 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4266 } 4267 4268 return 0; 4269 } 4270 4271 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4272 { 4273 struct amdgpu_device *adev = ring->adev; 4274 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4275 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4276 4277 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4278 memset((void *)mqd, 0, sizeof(*mqd)); 4279 mutex_lock(&adev->srbm_mutex); 4280 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4281 amdgpu_ring_init_mqd(ring); 4282 soc21_grbm_select(adev, 0, 0, 0, 0); 4283 mutex_unlock(&adev->srbm_mutex); 4284 4285 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4286 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4287 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4288 /* reset MQD to a clean status */ 4289 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4290 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4291 4292 /* reset ring buffer */ 4293 ring->wptr = 0; 4294 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4295 amdgpu_ring_clear_ring(ring); 4296 } else { 4297 amdgpu_ring_clear_ring(ring); 4298 } 4299 4300 return 0; 4301 } 4302 4303 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4304 { 4305 struct amdgpu_ring *ring; 4306 int r; 4307 4308 ring = &adev->gfx.kiq.ring; 4309 4310 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4311 if (unlikely(r != 0)) 4312 return r; 4313 4314 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4315 if (unlikely(r != 0)) 4316 return r; 4317 4318 gfx_v11_0_kiq_init_queue(ring); 4319 amdgpu_bo_kunmap(ring->mqd_obj); 4320 ring->mqd_ptr = NULL; 4321 amdgpu_bo_unreserve(ring->mqd_obj); 4322 ring->sched.ready = true; 4323 return 0; 4324 } 4325 4326 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4327 { 4328 struct amdgpu_ring *ring = NULL; 4329 int r = 0, i; 4330 4331 if (!amdgpu_async_gfx_ring) 4332 gfx_v11_0_cp_compute_enable(adev, true); 4333 4334 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4335 ring = &adev->gfx.compute_ring[i]; 4336 4337 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4338 if (unlikely(r != 0)) 4339 goto done; 4340 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4341 if (!r) { 4342 r = gfx_v11_0_kcq_init_queue(ring); 4343 amdgpu_bo_kunmap(ring->mqd_obj); 4344 ring->mqd_ptr = NULL; 4345 } 4346 amdgpu_bo_unreserve(ring->mqd_obj); 4347 if (r) 4348 goto done; 4349 } 4350 4351 r = amdgpu_gfx_enable_kcq(adev); 4352 done: 4353 return r; 4354 } 4355 4356 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4357 { 4358 int r, i; 4359 struct amdgpu_ring *ring; 4360 4361 if (!(adev->flags & AMD_IS_APU)) 4362 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4363 4364 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4365 /* legacy firmware loading */ 4366 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4367 if (r) 4368 return r; 4369 4370 if (adev->gfx.rs64_enable) 4371 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4372 else 4373 r = gfx_v11_0_cp_compute_load_microcode(adev); 4374 if (r) 4375 return r; 4376 } 4377 4378 gfx_v11_0_cp_set_doorbell_range(adev); 4379 4380 if (amdgpu_async_gfx_ring) { 4381 gfx_v11_0_cp_compute_enable(adev, true); 4382 gfx_v11_0_cp_gfx_enable(adev, true); 4383 } 4384 4385 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4386 r = amdgpu_mes_kiq_hw_init(adev); 4387 else 4388 r = gfx_v11_0_kiq_resume(adev); 4389 if (r) 4390 return r; 4391 4392 r = gfx_v11_0_kcq_resume(adev); 4393 if (r) 4394 return r; 4395 4396 if (!amdgpu_async_gfx_ring) { 4397 r = gfx_v11_0_cp_gfx_resume(adev); 4398 if (r) 4399 return r; 4400 } else { 4401 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4402 if (r) 4403 return r; 4404 } 4405 4406 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4407 ring = &adev->gfx.gfx_ring[i]; 4408 r = amdgpu_ring_test_helper(ring); 4409 if (r) 4410 return r; 4411 } 4412 4413 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4414 ring = &adev->gfx.compute_ring[i]; 4415 r = amdgpu_ring_test_helper(ring); 4416 if (r) 4417 return r; 4418 } 4419 4420 return 0; 4421 } 4422 4423 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4424 { 4425 gfx_v11_0_cp_gfx_enable(adev, enable); 4426 gfx_v11_0_cp_compute_enable(adev, enable); 4427 } 4428 4429 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4430 { 4431 int r; 4432 bool value; 4433 4434 r = adev->gfxhub.funcs->gart_enable(adev); 4435 if (r) 4436 return r; 4437 4438 adev->hdp.funcs->flush_hdp(adev, NULL); 4439 4440 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4441 false : true; 4442 4443 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4444 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 4445 4446 return 0; 4447 } 4448 4449 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4450 { 4451 u32 tmp; 4452 4453 /* select RS64 */ 4454 if (adev->gfx.rs64_enable) { 4455 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4456 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4457 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4458 4459 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4460 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4461 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4462 } 4463 4464 if (amdgpu_emu_mode == 1) 4465 msleep(100); 4466 } 4467 4468 static int get_gb_addr_config(struct amdgpu_device * adev) 4469 { 4470 u32 gb_addr_config; 4471 4472 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4473 if (gb_addr_config == 0) 4474 return -EINVAL; 4475 4476 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4477 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4478 4479 adev->gfx.config.gb_addr_config = gb_addr_config; 4480 4481 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4482 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4483 GB_ADDR_CONFIG, NUM_PIPES); 4484 4485 adev->gfx.config.max_tile_pipes = 4486 adev->gfx.config.gb_addr_config_fields.num_pipes; 4487 4488 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4489 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4490 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4491 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4492 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4493 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4494 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4495 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4496 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4497 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4498 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4499 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4500 4501 return 0; 4502 } 4503 4504 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4505 { 4506 uint32_t data; 4507 4508 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4509 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4510 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4511 4512 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4513 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4514 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4515 } 4516 4517 static int gfx_v11_0_hw_init(void *handle) 4518 { 4519 int r; 4520 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4521 4522 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4523 if (adev->gfx.imu.funcs) { 4524 /* RLC autoload sequence 1: Program rlc ram */ 4525 if (adev->gfx.imu.funcs->program_rlc_ram) 4526 adev->gfx.imu.funcs->program_rlc_ram(adev); 4527 } 4528 /* rlc autoload firmware */ 4529 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4530 if (r) 4531 return r; 4532 } else { 4533 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4534 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4535 if (adev->gfx.imu.funcs->load_microcode) 4536 adev->gfx.imu.funcs->load_microcode(adev); 4537 if (adev->gfx.imu.funcs->setup_imu) 4538 adev->gfx.imu.funcs->setup_imu(adev); 4539 if (adev->gfx.imu.funcs->start_imu) 4540 adev->gfx.imu.funcs->start_imu(adev); 4541 } 4542 } 4543 } 4544 4545 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4546 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4547 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4548 if (r) { 4549 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4550 return r; 4551 } 4552 } 4553 4554 adev->gfx.is_poweron = true; 4555 4556 if(get_gb_addr_config(adev)) 4557 DRM_WARN("Invalid gb_addr_config !\n"); 4558 4559 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4560 adev->gfx.rs64_enable) 4561 gfx_v11_0_config_gfx_rs64(adev); 4562 4563 r = gfx_v11_0_gfxhub_enable(adev); 4564 if (r) 4565 return r; 4566 4567 if (!amdgpu_emu_mode) 4568 gfx_v11_0_init_golden_registers(adev); 4569 4570 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4571 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4572 /** 4573 * For gfx 11, rlc firmware loading relies on smu firmware is 4574 * loaded firstly, so in direct type, it has to load smc ucode 4575 * here before rlc. 4576 */ 4577 if (!(adev->flags & AMD_IS_APU)) { 4578 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4579 if (r) 4580 return r; 4581 } 4582 } 4583 4584 gfx_v11_0_constants_init(adev); 4585 4586 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4587 gfx_v11_0_select_cp_fw_arch(adev); 4588 4589 adev->nbio.funcs->gc_doorbell_init(adev); 4590 4591 r = gfx_v11_0_rlc_resume(adev); 4592 if (r) 4593 return r; 4594 4595 /* 4596 * init golden registers and rlc resume may override some registers, 4597 * reconfig them here 4598 */ 4599 gfx_v11_0_tcp_harvest(adev); 4600 4601 r = gfx_v11_0_cp_resume(adev); 4602 if (r) 4603 return r; 4604 4605 return r; 4606 } 4607 4608 #ifndef BRING_UP_DEBUG 4609 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev) 4610 { 4611 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4612 struct amdgpu_ring *kiq_ring = &kiq->ring; 4613 int i, r = 0; 4614 4615 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4616 return -EINVAL; 4617 4618 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 4619 adev->gfx.num_gfx_rings)) 4620 return -ENOMEM; 4621 4622 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4623 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 4624 PREEMPT_QUEUES, 0, 0); 4625 4626 if (adev->gfx.kiq.ring.sched.ready) 4627 r = amdgpu_ring_test_helper(kiq_ring); 4628 4629 return r; 4630 } 4631 #endif 4632 4633 static int gfx_v11_0_hw_fini(void *handle) 4634 { 4635 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4636 int r; 4637 uint32_t tmp; 4638 4639 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4640 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4641 4642 if (!adev->no_hw_access) { 4643 #ifndef BRING_UP_DEBUG 4644 if (amdgpu_async_gfx_ring) { 4645 r = gfx_v11_0_kiq_disable_kgq(adev); 4646 if (r) 4647 DRM_ERROR("KGQ disable failed\n"); 4648 } 4649 #endif 4650 if (amdgpu_gfx_disable_kcq(adev)) 4651 DRM_ERROR("KCQ disable failed\n"); 4652 4653 amdgpu_mes_kiq_hw_fini(adev); 4654 } 4655 4656 if (amdgpu_sriov_vf(adev)) { 4657 gfx_v11_0_cp_gfx_enable(adev, false); 4658 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 4659 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 4660 tmp &= 0xffffff00; 4661 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 4662 4663 return 0; 4664 } 4665 gfx_v11_0_cp_enable(adev, false); 4666 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4667 4668 adev->gfxhub.funcs->gart_disable(adev); 4669 4670 adev->gfx.is_poweron = false; 4671 4672 return 0; 4673 } 4674 4675 static int gfx_v11_0_suspend(void *handle) 4676 { 4677 return gfx_v11_0_hw_fini(handle); 4678 } 4679 4680 static int gfx_v11_0_resume(void *handle) 4681 { 4682 return gfx_v11_0_hw_init(handle); 4683 } 4684 4685 static bool gfx_v11_0_is_idle(void *handle) 4686 { 4687 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4688 4689 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4690 GRBM_STATUS, GUI_ACTIVE)) 4691 return false; 4692 else 4693 return true; 4694 } 4695 4696 static int gfx_v11_0_wait_for_idle(void *handle) 4697 { 4698 unsigned i; 4699 u32 tmp; 4700 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4701 4702 for (i = 0; i < adev->usec_timeout; i++) { 4703 /* read MC_STATUS */ 4704 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4705 GRBM_STATUS__GUI_ACTIVE_MASK; 4706 4707 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4708 return 0; 4709 udelay(1); 4710 } 4711 return -ETIMEDOUT; 4712 } 4713 4714 static int gfx_v11_0_soft_reset(void *handle) 4715 { 4716 u32 grbm_soft_reset = 0; 4717 u32 tmp; 4718 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4719 4720 /* GRBM_STATUS */ 4721 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS); 4722 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4723 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4724 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 4725 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 4726 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 4727 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4728 GRBM_SOFT_RESET, SOFT_RESET_CP, 4729 1); 4730 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4731 GRBM_SOFT_RESET, SOFT_RESET_GFX, 4732 1); 4733 } 4734 4735 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4736 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4737 GRBM_SOFT_RESET, SOFT_RESET_CP, 4738 1); 4739 } 4740 4741 /* GRBM_STATUS2 */ 4742 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS2); 4743 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 4744 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4745 GRBM_SOFT_RESET, 4746 SOFT_RESET_RLC, 4747 1); 4748 4749 if (grbm_soft_reset) { 4750 /* stop the rlc */ 4751 gfx_v11_0_rlc_stop(adev); 4752 4753 /* Disable GFX parsing/prefetching */ 4754 gfx_v11_0_cp_gfx_enable(adev, false); 4755 4756 /* Disable MEC parsing/prefetching */ 4757 gfx_v11_0_cp_compute_enable(adev, false); 4758 4759 if (grbm_soft_reset) { 4760 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4761 tmp |= grbm_soft_reset; 4762 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4763 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 4764 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4765 4766 udelay(50); 4767 4768 tmp &= ~grbm_soft_reset; 4769 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 4770 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4771 } 4772 4773 /* Wait a little for things to settle down */ 4774 udelay(50); 4775 } 4776 return 0; 4777 } 4778 4779 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4780 { 4781 uint64_t clock; 4782 4783 amdgpu_gfx_off_ctrl(adev, false); 4784 mutex_lock(&adev->gfx.gpu_clock_mutex); 4785 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) | 4786 ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL); 4787 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4788 amdgpu_gfx_off_ctrl(adev, true); 4789 return clock; 4790 } 4791 4792 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4793 uint32_t vmid, 4794 uint32_t gds_base, uint32_t gds_size, 4795 uint32_t gws_base, uint32_t gws_size, 4796 uint32_t oa_base, uint32_t oa_size) 4797 { 4798 struct amdgpu_device *adev = ring->adev; 4799 4800 /* GDS Base */ 4801 gfx_v11_0_write_data_to_reg(ring, 0, false, 4802 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4803 gds_base); 4804 4805 /* GDS Size */ 4806 gfx_v11_0_write_data_to_reg(ring, 0, false, 4807 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4808 gds_size); 4809 4810 /* GWS */ 4811 gfx_v11_0_write_data_to_reg(ring, 0, false, 4812 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4813 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4814 4815 /* OA */ 4816 gfx_v11_0_write_data_to_reg(ring, 0, false, 4817 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4818 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4819 } 4820 4821 static int gfx_v11_0_early_init(void *handle) 4822 { 4823 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4824 4825 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4826 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4827 AMDGPU_MAX_COMPUTE_RINGS); 4828 4829 gfx_v11_0_set_kiq_pm4_funcs(adev); 4830 gfx_v11_0_set_ring_funcs(adev); 4831 gfx_v11_0_set_irq_funcs(adev); 4832 gfx_v11_0_set_gds_init(adev); 4833 gfx_v11_0_set_rlc_funcs(adev); 4834 gfx_v11_0_set_mqd_funcs(adev); 4835 gfx_v11_0_set_imu_funcs(adev); 4836 4837 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4838 4839 return 0; 4840 } 4841 4842 static int gfx_v11_0_late_init(void *handle) 4843 { 4844 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4845 int r; 4846 4847 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4848 if (r) 4849 return r; 4850 4851 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4852 if (r) 4853 return r; 4854 4855 return 0; 4856 } 4857 4858 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4859 { 4860 uint32_t rlc_cntl; 4861 4862 /* if RLC is not enabled, do nothing */ 4863 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4864 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4865 } 4866 4867 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev) 4868 { 4869 uint32_t data; 4870 unsigned i; 4871 4872 data = RLC_SAFE_MODE__CMD_MASK; 4873 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4874 4875 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4876 4877 /* wait for RLC_SAFE_MODE */ 4878 for (i = 0; i < adev->usec_timeout; i++) { 4879 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4880 RLC_SAFE_MODE, CMD)) 4881 break; 4882 udelay(1); 4883 } 4884 } 4885 4886 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev) 4887 { 4888 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4889 } 4890 4891 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 4892 bool enable) 4893 { 4894 uint32_t def, data; 4895 4896 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4897 return; 4898 4899 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4900 4901 if (enable) 4902 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4903 else 4904 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4905 4906 if (def != data) 4907 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4908 } 4909 4910 #if 0 4911 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4912 bool enable) 4913 { 4914 /* TODO: add power related feature later. */ 4915 } 4916 4917 static void gfx_v11_0_update_3d_clock_gating(struct amdgpu_device *adev, 4918 bool enable) 4919 { 4920 /* TODO: add power related feature later. */ 4921 } 4922 #endif 4923 4924 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4925 bool enable) 4926 { 4927 uint32_t def, data; 4928 4929 if (!(adev->cg_flags & 4930 (AMD_CG_SUPPORT_GFX_CGCG | 4931 AMD_CG_SUPPORT_GFX_CGLS | 4932 AMD_CG_SUPPORT_GFX_3D_CGCG | 4933 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4934 return; 4935 4936 if (enable) { 4937 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4938 4939 /* unset CGCG override */ 4940 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4941 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4942 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4943 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4944 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4945 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4946 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4947 4948 /* update CGCG override bits */ 4949 if (def != data) 4950 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4951 4952 /* enable cgcg FSM(0x0000363F) */ 4953 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4954 4955 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4956 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4957 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4958 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4959 } 4960 4961 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4962 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4963 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4964 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4965 } 4966 4967 if (def != data) 4968 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4969 4970 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4971 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4972 4973 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4974 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4975 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4976 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4977 } 4978 4979 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4980 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4981 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4982 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4983 } 4984 4985 if (def != data) 4986 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4987 4988 /* set IDLE_POLL_COUNT(0x00900100) */ 4989 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4990 4991 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4992 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4993 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4994 4995 if (def != data) 4996 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4997 4998 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4999 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 5000 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 5001 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 5002 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 5003 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 5004 5005 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5006 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5007 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5008 5009 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5010 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5011 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5012 } else { 5013 /* Program RLC_CGCG_CGLS_CTRL */ 5014 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5015 5016 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5017 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5018 5019 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5020 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5021 5022 if (def != data) 5023 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5024 5025 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5026 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5027 5028 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5029 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5030 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5031 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5032 5033 if (def != data) 5034 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5035 5036 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5037 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5038 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5039 5040 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5041 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5042 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5043 } 5044 } 5045 5046 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5047 bool enable) 5048 { 5049 amdgpu_gfx_rlc_enter_safe_mode(adev); 5050 5051 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5052 5053 gfx_v11_0_update_repeater_fgcg(adev, enable); 5054 5055 if (adev->cg_flags & 5056 (AMD_CG_SUPPORT_GFX_MGCG | 5057 AMD_CG_SUPPORT_GFX_CGLS | 5058 AMD_CG_SUPPORT_GFX_CGCG | 5059 AMD_CG_SUPPORT_GFX_3D_CGCG | 5060 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5061 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5062 5063 amdgpu_gfx_rlc_exit_safe_mode(adev); 5064 5065 return 0; 5066 } 5067 5068 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 5069 { 5070 u32 reg, data; 5071 5072 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5073 if (amdgpu_sriov_is_pp_one_vf(adev)) 5074 data = RREG32_NO_KIQ(reg); 5075 else 5076 data = RREG32(reg); 5077 5078 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5079 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5080 5081 if (amdgpu_sriov_is_pp_one_vf(adev)) 5082 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5083 else 5084 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5085 } 5086 5087 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5088 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5089 .set_safe_mode = gfx_v11_0_set_safe_mode, 5090 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5091 .init = gfx_v11_0_rlc_init, 5092 .get_csb_size = gfx_v11_0_get_csb_size, 5093 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5094 .resume = gfx_v11_0_rlc_resume, 5095 .stop = gfx_v11_0_rlc_stop, 5096 .reset = gfx_v11_0_rlc_reset, 5097 .start = gfx_v11_0_rlc_start, 5098 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5099 }; 5100 5101 static int gfx_v11_0_set_powergating_state(void *handle, 5102 enum amd_powergating_state state) 5103 { 5104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5105 bool enable = (state == AMD_PG_STATE_GATE); 5106 5107 if (amdgpu_sriov_vf(adev)) 5108 return 0; 5109 5110 switch (adev->ip_versions[GC_HWIP][0]) { 5111 case IP_VERSION(11, 0, 0): 5112 amdgpu_gfx_off_ctrl(adev, enable); 5113 break; 5114 default: 5115 break; 5116 } 5117 5118 return 0; 5119 } 5120 5121 static int gfx_v11_0_set_clockgating_state(void *handle, 5122 enum amd_clockgating_state state) 5123 { 5124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5125 5126 if (amdgpu_sriov_vf(adev)) 5127 return 0; 5128 5129 switch (adev->ip_versions[GC_HWIP][0]) { 5130 case IP_VERSION(11, 0, 0): 5131 case IP_VERSION(11, 0, 2): 5132 gfx_v11_0_update_gfx_clock_gating(adev, 5133 state == AMD_CG_STATE_GATE); 5134 break; 5135 default: 5136 break; 5137 } 5138 5139 return 0; 5140 } 5141 5142 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5143 { 5144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5145 int data; 5146 5147 /* AMD_CG_SUPPORT_GFX_FGCG */ 5148 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5149 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5150 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5151 5152 /* AMD_CG_SUPPORT_GFX_MGCG */ 5153 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5154 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5155 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5156 5157 /* AMD_CG_SUPPORT_GFX_CGCG */ 5158 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5159 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5160 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5161 5162 /* AMD_CG_SUPPORT_GFX_CGLS */ 5163 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5164 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5165 5166 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5167 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5168 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5169 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5170 5171 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5172 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5173 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5174 } 5175 5176 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5177 { 5178 /* gfx11 is 32bit rptr*/ 5179 return *(uint32_t *)ring->rptr_cpu_addr; 5180 } 5181 5182 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5183 { 5184 struct amdgpu_device *adev = ring->adev; 5185 u64 wptr; 5186 5187 /* XXX check if swapping is necessary on BE */ 5188 if (ring->use_doorbell) { 5189 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5190 } else { 5191 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5192 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5193 } 5194 5195 return wptr; 5196 } 5197 5198 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5199 { 5200 struct amdgpu_device *adev = ring->adev; 5201 5202 if (ring->use_doorbell) { 5203 /* XXX check if swapping is necessary on BE */ 5204 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5205 WDOORBELL64(ring->doorbell_index, ring->wptr); 5206 } else { 5207 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5208 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5209 } 5210 } 5211 5212 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5213 { 5214 /* gfx11 hardware is 32bit rptr */ 5215 return *(uint32_t *)ring->rptr_cpu_addr; 5216 } 5217 5218 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5219 { 5220 u64 wptr; 5221 5222 /* XXX check if swapping is necessary on BE */ 5223 if (ring->use_doorbell) 5224 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5225 else 5226 BUG(); 5227 return wptr; 5228 } 5229 5230 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5231 { 5232 struct amdgpu_device *adev = ring->adev; 5233 5234 /* XXX check if swapping is necessary on BE */ 5235 if (ring->use_doorbell) { 5236 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5237 WDOORBELL64(ring->doorbell_index, ring->wptr); 5238 } else { 5239 BUG(); /* only DOORBELL method supported on gfx11 now */ 5240 } 5241 } 5242 5243 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5244 { 5245 struct amdgpu_device *adev = ring->adev; 5246 u32 ref_and_mask, reg_mem_engine; 5247 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5248 5249 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5250 switch (ring->me) { 5251 case 1: 5252 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5253 break; 5254 case 2: 5255 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5256 break; 5257 default: 5258 return; 5259 } 5260 reg_mem_engine = 0; 5261 } else { 5262 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5263 reg_mem_engine = 1; /* pfp */ 5264 } 5265 5266 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5267 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5268 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5269 ref_and_mask, ref_and_mask, 0x20); 5270 } 5271 5272 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5273 struct amdgpu_job *job, 5274 struct amdgpu_ib *ib, 5275 uint32_t flags) 5276 { 5277 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5278 u32 header, control = 0; 5279 5280 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5281 5282 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5283 5284 control |= ib->length_dw | (vmid << 24); 5285 5286 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5287 control |= INDIRECT_BUFFER_PRE_ENB(1); 5288 5289 if (flags & AMDGPU_IB_PREEMPTED) 5290 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5291 5292 if (vmid) 5293 gfx_v11_0_ring_emit_de_meta(ring, 5294 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5295 } 5296 5297 if (ring->is_mes_queue) 5298 /* inherit vmid from mqd */ 5299 control |= 0x400000; 5300 5301 amdgpu_ring_write(ring, header); 5302 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5303 amdgpu_ring_write(ring, 5304 #ifdef __BIG_ENDIAN 5305 (2 << 0) | 5306 #endif 5307 lower_32_bits(ib->gpu_addr)); 5308 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5309 amdgpu_ring_write(ring, control); 5310 } 5311 5312 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5313 struct amdgpu_job *job, 5314 struct amdgpu_ib *ib, 5315 uint32_t flags) 5316 { 5317 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5318 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5319 5320 if (ring->is_mes_queue) 5321 /* inherit vmid from mqd */ 5322 control |= 0x40000000; 5323 5324 /* Currently, there is a high possibility to get wave ID mismatch 5325 * between ME and GDS, leading to a hw deadlock, because ME generates 5326 * different wave IDs than the GDS expects. This situation happens 5327 * randomly when at least 5 compute pipes use GDS ordered append. 5328 * The wave IDs generated by ME are also wrong after suspend/resume. 5329 * Those are probably bugs somewhere else in the kernel driver. 5330 * 5331 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5332 * GDS to 0 for this ring (me/pipe). 5333 */ 5334 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5335 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5336 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5337 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5338 } 5339 5340 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5341 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5342 amdgpu_ring_write(ring, 5343 #ifdef __BIG_ENDIAN 5344 (2 << 0) | 5345 #endif 5346 lower_32_bits(ib->gpu_addr)); 5347 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5348 amdgpu_ring_write(ring, control); 5349 } 5350 5351 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5352 u64 seq, unsigned flags) 5353 { 5354 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5355 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5356 5357 /* RELEASE_MEM - flush caches, send int */ 5358 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5359 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5360 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5361 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5362 PACKET3_RELEASE_MEM_GCR_GL2_US | 5363 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5364 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5365 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5366 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5367 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5368 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5369 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5370 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5371 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5372 5373 /* 5374 * the address should be Qword aligned if 64bit write, Dword 5375 * aligned if only send 32bit data low (discard data high) 5376 */ 5377 if (write64bit) 5378 BUG_ON(addr & 0x7); 5379 else 5380 BUG_ON(addr & 0x3); 5381 amdgpu_ring_write(ring, lower_32_bits(addr)); 5382 amdgpu_ring_write(ring, upper_32_bits(addr)); 5383 amdgpu_ring_write(ring, lower_32_bits(seq)); 5384 amdgpu_ring_write(ring, upper_32_bits(seq)); 5385 amdgpu_ring_write(ring, ring->is_mes_queue ? 5386 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5387 } 5388 5389 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5390 { 5391 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5392 uint32_t seq = ring->fence_drv.sync_seq; 5393 uint64_t addr = ring->fence_drv.gpu_addr; 5394 5395 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5396 upper_32_bits(addr), seq, 0xffffffff, 4); 5397 } 5398 5399 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5400 uint16_t pasid, uint32_t flush_type, 5401 bool all_hub, uint8_t dst_sel) 5402 { 5403 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5404 amdgpu_ring_write(ring, 5405 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5406 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5407 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5408 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5409 } 5410 5411 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5412 unsigned vmid, uint64_t pd_addr) 5413 { 5414 if (ring->is_mes_queue) 5415 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5416 else 5417 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5418 5419 /* compute doesn't have PFP */ 5420 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5421 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5422 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5423 amdgpu_ring_write(ring, 0x0); 5424 } 5425 } 5426 5427 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5428 u64 seq, unsigned int flags) 5429 { 5430 struct amdgpu_device *adev = ring->adev; 5431 5432 /* we only allocate 32bit for each seq wb address */ 5433 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5434 5435 /* write fence seq to the "addr" */ 5436 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5437 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5438 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5439 amdgpu_ring_write(ring, lower_32_bits(addr)); 5440 amdgpu_ring_write(ring, upper_32_bits(addr)); 5441 amdgpu_ring_write(ring, lower_32_bits(seq)); 5442 5443 if (flags & AMDGPU_FENCE_FLAG_INT) { 5444 /* set register to trigger INT */ 5445 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5446 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5447 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5448 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5449 amdgpu_ring_write(ring, 0); 5450 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5451 } 5452 } 5453 5454 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5455 uint32_t flags) 5456 { 5457 uint32_t dw2 = 0; 5458 5459 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5460 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5461 /* set load_global_config & load_global_uconfig */ 5462 dw2 |= 0x8001; 5463 /* set load_cs_sh_regs */ 5464 dw2 |= 0x01000000; 5465 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5466 dw2 |= 0x10002; 5467 } 5468 5469 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5470 amdgpu_ring_write(ring, dw2); 5471 amdgpu_ring_write(ring, 0); 5472 } 5473 5474 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5475 { 5476 unsigned ret; 5477 5478 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5479 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5480 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5481 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5482 ret = ring->wptr & ring->buf_mask; 5483 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5484 5485 return ret; 5486 } 5487 5488 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5489 { 5490 unsigned cur; 5491 BUG_ON(offset > ring->buf_mask); 5492 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5493 5494 cur = (ring->wptr - 1) & ring->buf_mask; 5495 if (likely(cur > offset)) 5496 ring->ring[offset] = cur - offset; 5497 else 5498 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5499 } 5500 5501 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5502 { 5503 int i, r = 0; 5504 struct amdgpu_device *adev = ring->adev; 5505 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5506 struct amdgpu_ring *kiq_ring = &kiq->ring; 5507 unsigned long flags; 5508 5509 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5510 return -EINVAL; 5511 5512 spin_lock_irqsave(&kiq->ring_lock, flags); 5513 5514 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5515 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5516 return -ENOMEM; 5517 } 5518 5519 /* assert preemption condition */ 5520 amdgpu_ring_set_preempt_cond_exec(ring, false); 5521 5522 /* assert IB preemption, emit the trailing fence */ 5523 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5524 ring->trail_fence_gpu_addr, 5525 ++ring->trail_seq); 5526 amdgpu_ring_commit(kiq_ring); 5527 5528 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5529 5530 /* poll the trailing fence */ 5531 for (i = 0; i < adev->usec_timeout; i++) { 5532 if (ring->trail_seq == 5533 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5534 break; 5535 udelay(1); 5536 } 5537 5538 if (i >= adev->usec_timeout) { 5539 r = -EINVAL; 5540 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5541 } 5542 5543 /* deassert preemption condition */ 5544 amdgpu_ring_set_preempt_cond_exec(ring, true); 5545 return r; 5546 } 5547 5548 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5549 { 5550 struct amdgpu_device *adev = ring->adev; 5551 struct v10_de_ib_state de_payload = {0}; 5552 uint64_t offset, gds_addr, de_payload_gpu_addr; 5553 void *de_payload_cpu_addr; 5554 int cnt; 5555 5556 if (ring->is_mes_queue) { 5557 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5558 gfx[0].gfx_meta_data) + 5559 offsetof(struct v10_gfx_meta_data, de_payload); 5560 de_payload_gpu_addr = 5561 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5562 de_payload_cpu_addr = 5563 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5564 5565 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5566 gfx[0].gds_backup) + 5567 offsetof(struct v10_gfx_meta_data, de_payload); 5568 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5569 } else { 5570 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5571 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5572 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5573 5574 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5575 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5576 PAGE_SIZE); 5577 } 5578 5579 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5580 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5581 5582 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5583 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5584 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5585 WRITE_DATA_DST_SEL(8) | 5586 WR_CONFIRM) | 5587 WRITE_DATA_CACHE_POLICY(0)); 5588 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5589 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5590 5591 if (resume) 5592 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5593 sizeof(de_payload) >> 2); 5594 else 5595 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5596 sizeof(de_payload) >> 2); 5597 } 5598 5599 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5600 bool secure) 5601 { 5602 uint32_t v = secure ? FRAME_TMZ : 0; 5603 5604 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5605 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5606 } 5607 5608 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5609 uint32_t reg_val_offs) 5610 { 5611 struct amdgpu_device *adev = ring->adev; 5612 5613 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5614 amdgpu_ring_write(ring, 0 | /* src: register*/ 5615 (5 << 8) | /* dst: memory */ 5616 (1 << 20)); /* write confirm */ 5617 amdgpu_ring_write(ring, reg); 5618 amdgpu_ring_write(ring, 0); 5619 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5620 reg_val_offs * 4)); 5621 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5622 reg_val_offs * 4)); 5623 } 5624 5625 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5626 uint32_t val) 5627 { 5628 uint32_t cmd = 0; 5629 5630 switch (ring->funcs->type) { 5631 case AMDGPU_RING_TYPE_GFX: 5632 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5633 break; 5634 case AMDGPU_RING_TYPE_KIQ: 5635 cmd = (1 << 16); /* no inc addr */ 5636 break; 5637 default: 5638 cmd = WR_CONFIRM; 5639 break; 5640 } 5641 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5642 amdgpu_ring_write(ring, cmd); 5643 amdgpu_ring_write(ring, reg); 5644 amdgpu_ring_write(ring, 0); 5645 amdgpu_ring_write(ring, val); 5646 } 5647 5648 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5649 uint32_t val, uint32_t mask) 5650 { 5651 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5652 } 5653 5654 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5655 uint32_t reg0, uint32_t reg1, 5656 uint32_t ref, uint32_t mask) 5657 { 5658 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5659 5660 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5661 ref, mask, 0x20); 5662 } 5663 5664 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5665 unsigned vmid) 5666 { 5667 struct amdgpu_device *adev = ring->adev; 5668 uint32_t value = 0; 5669 5670 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5671 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5672 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5673 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5674 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5675 } 5676 5677 static void 5678 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5679 uint32_t me, uint32_t pipe, 5680 enum amdgpu_interrupt_state state) 5681 { 5682 uint32_t cp_int_cntl, cp_int_cntl_reg; 5683 5684 if (!me) { 5685 switch (pipe) { 5686 case 0: 5687 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5688 break; 5689 case 1: 5690 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5691 break; 5692 default: 5693 DRM_DEBUG("invalid pipe %d\n", pipe); 5694 return; 5695 } 5696 } else { 5697 DRM_DEBUG("invalid me %d\n", me); 5698 return; 5699 } 5700 5701 switch (state) { 5702 case AMDGPU_IRQ_STATE_DISABLE: 5703 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5704 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5705 TIME_STAMP_INT_ENABLE, 0); 5706 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5707 GENERIC0_INT_ENABLE, 0); 5708 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5709 break; 5710 case AMDGPU_IRQ_STATE_ENABLE: 5711 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5712 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5713 TIME_STAMP_INT_ENABLE, 1); 5714 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5715 GENERIC0_INT_ENABLE, 1); 5716 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5717 break; 5718 default: 5719 break; 5720 } 5721 } 5722 5723 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5724 int me, int pipe, 5725 enum amdgpu_interrupt_state state) 5726 { 5727 u32 mec_int_cntl, mec_int_cntl_reg; 5728 5729 /* 5730 * amdgpu controls only the first MEC. That's why this function only 5731 * handles the setting of interrupts for this specific MEC. All other 5732 * pipes' interrupts are set by amdkfd. 5733 */ 5734 5735 if (me == 1) { 5736 switch (pipe) { 5737 case 0: 5738 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5739 break; 5740 case 1: 5741 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5742 break; 5743 case 2: 5744 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5745 break; 5746 case 3: 5747 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5748 break; 5749 default: 5750 DRM_DEBUG("invalid pipe %d\n", pipe); 5751 return; 5752 } 5753 } else { 5754 DRM_DEBUG("invalid me %d\n", me); 5755 return; 5756 } 5757 5758 switch (state) { 5759 case AMDGPU_IRQ_STATE_DISABLE: 5760 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5761 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5762 TIME_STAMP_INT_ENABLE, 0); 5763 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5764 GENERIC0_INT_ENABLE, 0); 5765 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5766 break; 5767 case AMDGPU_IRQ_STATE_ENABLE: 5768 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5769 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5770 TIME_STAMP_INT_ENABLE, 1); 5771 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5772 GENERIC0_INT_ENABLE, 1); 5773 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5774 break; 5775 default: 5776 break; 5777 } 5778 } 5779 5780 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5781 struct amdgpu_irq_src *src, 5782 unsigned type, 5783 enum amdgpu_interrupt_state state) 5784 { 5785 switch (type) { 5786 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5787 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 5788 break; 5789 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 5790 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 5791 break; 5792 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5793 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5794 break; 5795 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5796 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5797 break; 5798 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5799 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5800 break; 5801 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5802 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5803 break; 5804 default: 5805 break; 5806 } 5807 return 0; 5808 } 5809 5810 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 5811 struct amdgpu_irq_src *source, 5812 struct amdgpu_iv_entry *entry) 5813 { 5814 int i; 5815 u8 me_id, pipe_id, queue_id; 5816 struct amdgpu_ring *ring; 5817 uint32_t mes_queue_id = entry->src_data[0]; 5818 5819 DRM_DEBUG("IH: CP EOP\n"); 5820 5821 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 5822 struct amdgpu_mes_queue *queue; 5823 5824 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 5825 5826 spin_lock(&adev->mes.queue_id_lock); 5827 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 5828 if (queue) { 5829 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 5830 amdgpu_fence_process(queue->ring); 5831 } 5832 spin_unlock(&adev->mes.queue_id_lock); 5833 } else { 5834 me_id = (entry->ring_id & 0x0c) >> 2; 5835 pipe_id = (entry->ring_id & 0x03) >> 0; 5836 queue_id = (entry->ring_id & 0x70) >> 4; 5837 5838 switch (me_id) { 5839 case 0: 5840 if (pipe_id == 0) 5841 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5842 else 5843 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5844 break; 5845 case 1: 5846 case 2: 5847 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5848 ring = &adev->gfx.compute_ring[i]; 5849 /* Per-queue interrupt is supported for MEC starting from VI. 5850 * The interrupt can only be enabled/disabled per pipe instead 5851 * of per queue. 5852 */ 5853 if ((ring->me == me_id) && 5854 (ring->pipe == pipe_id) && 5855 (ring->queue == queue_id)) 5856 amdgpu_fence_process(ring); 5857 } 5858 break; 5859 } 5860 } 5861 5862 return 0; 5863 } 5864 5865 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5866 struct amdgpu_irq_src *source, 5867 unsigned type, 5868 enum amdgpu_interrupt_state state) 5869 { 5870 switch (state) { 5871 case AMDGPU_IRQ_STATE_DISABLE: 5872 case AMDGPU_IRQ_STATE_ENABLE: 5873 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5874 PRIV_REG_INT_ENABLE, 5875 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5876 break; 5877 default: 5878 break; 5879 } 5880 5881 return 0; 5882 } 5883 5884 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5885 struct amdgpu_irq_src *source, 5886 unsigned type, 5887 enum amdgpu_interrupt_state state) 5888 { 5889 switch (state) { 5890 case AMDGPU_IRQ_STATE_DISABLE: 5891 case AMDGPU_IRQ_STATE_ENABLE: 5892 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 5893 PRIV_INSTR_INT_ENABLE, 5894 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5895 default: 5896 break; 5897 } 5898 5899 return 0; 5900 } 5901 5902 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 5903 struct amdgpu_iv_entry *entry) 5904 { 5905 u8 me_id, pipe_id, queue_id; 5906 struct amdgpu_ring *ring; 5907 int i; 5908 5909 me_id = (entry->ring_id & 0x0c) >> 2; 5910 pipe_id = (entry->ring_id & 0x03) >> 0; 5911 queue_id = (entry->ring_id & 0x70) >> 4; 5912 5913 switch (me_id) { 5914 case 0: 5915 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5916 ring = &adev->gfx.gfx_ring[i]; 5917 /* we only enabled 1 gfx queue per pipe for now */ 5918 if (ring->me == me_id && ring->pipe == pipe_id) 5919 drm_sched_fault(&ring->sched); 5920 } 5921 break; 5922 case 1: 5923 case 2: 5924 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5925 ring = &adev->gfx.compute_ring[i]; 5926 if (ring->me == me_id && ring->pipe == pipe_id && 5927 ring->queue == queue_id) 5928 drm_sched_fault(&ring->sched); 5929 } 5930 break; 5931 default: 5932 BUG(); 5933 } 5934 } 5935 5936 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 5937 struct amdgpu_irq_src *source, 5938 struct amdgpu_iv_entry *entry) 5939 { 5940 DRM_ERROR("Illegal register access in command stream\n"); 5941 gfx_v11_0_handle_priv_fault(adev, entry); 5942 return 0; 5943 } 5944 5945 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 5946 struct amdgpu_irq_src *source, 5947 struct amdgpu_iv_entry *entry) 5948 { 5949 DRM_ERROR("Illegal instruction in command stream\n"); 5950 gfx_v11_0_handle_priv_fault(adev, entry); 5951 return 0; 5952 } 5953 5954 #if 0 5955 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 5956 struct amdgpu_irq_src *src, 5957 unsigned int type, 5958 enum amdgpu_interrupt_state state) 5959 { 5960 uint32_t tmp, target; 5961 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5962 5963 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5964 target += ring->pipe; 5965 5966 switch (type) { 5967 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 5968 if (state == AMDGPU_IRQ_STATE_DISABLE) { 5969 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 5970 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5971 GENERIC2_INT_ENABLE, 0); 5972 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 5973 5974 tmp = RREG32_SOC15_IP(GC, target); 5975 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 5976 GENERIC2_INT_ENABLE, 0); 5977 WREG32_SOC15_IP(GC, target, tmp); 5978 } else { 5979 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 5980 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5981 GENERIC2_INT_ENABLE, 1); 5982 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 5983 5984 tmp = RREG32_SOC15_IP(GC, target); 5985 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 5986 GENERIC2_INT_ENABLE, 1); 5987 WREG32_SOC15_IP(GC, target, tmp); 5988 } 5989 break; 5990 default: 5991 BUG(); /* kiq only support GENERIC2_INT now */ 5992 break; 5993 } 5994 return 0; 5995 } 5996 #endif 5997 5998 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 5999 { 6000 const unsigned int gcr_cntl = 6001 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6002 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6003 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6004 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6005 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6006 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6007 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6008 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6009 6010 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6011 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6012 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6013 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6014 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6015 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6016 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6017 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6018 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6019 } 6020 6021 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6022 .name = "gfx_v11_0", 6023 .early_init = gfx_v11_0_early_init, 6024 .late_init = gfx_v11_0_late_init, 6025 .sw_init = gfx_v11_0_sw_init, 6026 .sw_fini = gfx_v11_0_sw_fini, 6027 .hw_init = gfx_v11_0_hw_init, 6028 .hw_fini = gfx_v11_0_hw_fini, 6029 .suspend = gfx_v11_0_suspend, 6030 .resume = gfx_v11_0_resume, 6031 .is_idle = gfx_v11_0_is_idle, 6032 .wait_for_idle = gfx_v11_0_wait_for_idle, 6033 .soft_reset = gfx_v11_0_soft_reset, 6034 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6035 .set_powergating_state = gfx_v11_0_set_powergating_state, 6036 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6037 }; 6038 6039 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6040 .type = AMDGPU_RING_TYPE_GFX, 6041 .align_mask = 0xff, 6042 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6043 .support_64bit_ptrs = true, 6044 .vmhub = AMDGPU_GFXHUB_0, 6045 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6046 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6047 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6048 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6049 5 + /* COND_EXEC */ 6050 7 + /* PIPELINE_SYNC */ 6051 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6052 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6053 2 + /* VM_FLUSH */ 6054 8 + /* FENCE for VM_FLUSH */ 6055 20 + /* GDS switch */ 6056 5 + /* COND_EXEC */ 6057 7 + /* HDP_flush */ 6058 4 + /* VGT_flush */ 6059 31 + /* DE_META */ 6060 3 + /* CNTX_CTRL */ 6061 5 + /* HDP_INVL */ 6062 8 + 8 + /* FENCE x2 */ 6063 8, /* gfx_v11_0_emit_mem_sync */ 6064 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6065 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6066 .emit_fence = gfx_v11_0_ring_emit_fence, 6067 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6068 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6069 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6070 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6071 .test_ring = gfx_v11_0_ring_test_ring, 6072 .test_ib = gfx_v11_0_ring_test_ib, 6073 .insert_nop = amdgpu_ring_insert_nop, 6074 .pad_ib = amdgpu_ring_generic_pad_ib, 6075 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6076 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6077 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6078 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6079 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6080 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6081 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6082 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6083 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6084 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6085 }; 6086 6087 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6088 .type = AMDGPU_RING_TYPE_COMPUTE, 6089 .align_mask = 0xff, 6090 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6091 .support_64bit_ptrs = true, 6092 .vmhub = AMDGPU_GFXHUB_0, 6093 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6094 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6095 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6096 .emit_frame_size = 6097 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6098 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6099 5 + /* hdp invalidate */ 6100 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6101 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6102 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6103 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6104 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6105 8, /* gfx_v11_0_emit_mem_sync */ 6106 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6107 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6108 .emit_fence = gfx_v11_0_ring_emit_fence, 6109 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6110 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6111 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6112 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6113 .test_ring = gfx_v11_0_ring_test_ring, 6114 .test_ib = gfx_v11_0_ring_test_ib, 6115 .insert_nop = amdgpu_ring_insert_nop, 6116 .pad_ib = amdgpu_ring_generic_pad_ib, 6117 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6118 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6119 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6120 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6121 }; 6122 6123 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6124 .type = AMDGPU_RING_TYPE_KIQ, 6125 .align_mask = 0xff, 6126 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6127 .support_64bit_ptrs = true, 6128 .vmhub = AMDGPU_GFXHUB_0, 6129 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6130 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6131 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6132 .emit_frame_size = 6133 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6134 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6135 5 + /*hdp invalidate */ 6136 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6137 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6138 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6139 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6140 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6141 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6142 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6143 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6144 .test_ring = gfx_v11_0_ring_test_ring, 6145 .test_ib = gfx_v11_0_ring_test_ib, 6146 .insert_nop = amdgpu_ring_insert_nop, 6147 .pad_ib = amdgpu_ring_generic_pad_ib, 6148 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6149 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6150 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6151 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6152 }; 6153 6154 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6155 { 6156 int i; 6157 6158 adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6159 6160 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6161 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6162 6163 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6164 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6165 } 6166 6167 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6168 .set = gfx_v11_0_set_eop_interrupt_state, 6169 .process = gfx_v11_0_eop_irq, 6170 }; 6171 6172 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6173 .set = gfx_v11_0_set_priv_reg_fault_state, 6174 .process = gfx_v11_0_priv_reg_irq, 6175 }; 6176 6177 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6178 .set = gfx_v11_0_set_priv_inst_fault_state, 6179 .process = gfx_v11_0_priv_inst_irq, 6180 }; 6181 6182 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6183 { 6184 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6185 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6186 6187 adev->gfx.priv_reg_irq.num_types = 1; 6188 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6189 6190 adev->gfx.priv_inst_irq.num_types = 1; 6191 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6192 } 6193 6194 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6195 { 6196 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6197 } 6198 6199 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6200 { 6201 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6202 } 6203 6204 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6205 { 6206 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6207 adev->gfx.config.max_sh_per_se * 6208 adev->gfx.config.max_shader_engines; 6209 6210 adev->gds.gds_size = 0x1000; 6211 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6212 adev->gds.gws_size = 64; 6213 adev->gds.oa_size = 16; 6214 } 6215 6216 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6217 { 6218 /* set gfx eng mqd */ 6219 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6220 sizeof(struct v11_gfx_mqd); 6221 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6222 gfx_v11_0_gfx_mqd_init; 6223 /* set compute eng mqd */ 6224 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6225 sizeof(struct v11_compute_mqd); 6226 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6227 gfx_v11_0_compute_mqd_init; 6228 } 6229 6230 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6231 u32 bitmap) 6232 { 6233 u32 data; 6234 6235 if (!bitmap) 6236 return; 6237 6238 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6239 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6240 6241 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6242 } 6243 6244 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6245 { 6246 u32 data, wgp_bitmask; 6247 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6248 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6249 6250 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6251 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6252 6253 wgp_bitmask = 6254 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6255 6256 return (~data) & wgp_bitmask; 6257 } 6258 6259 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6260 { 6261 u32 wgp_idx, wgp_active_bitmap; 6262 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6263 6264 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6265 cu_active_bitmap = 0; 6266 6267 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6268 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6269 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6270 if (wgp_active_bitmap & (1 << wgp_idx)) 6271 cu_active_bitmap |= cu_bitmap_per_wgp; 6272 } 6273 6274 return cu_active_bitmap; 6275 } 6276 6277 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6278 struct amdgpu_cu_info *cu_info) 6279 { 6280 int i, j, k, counter, active_cu_number = 0; 6281 u32 mask, bitmap; 6282 unsigned disable_masks[8 * 2]; 6283 6284 if (!adev || !cu_info) 6285 return -EINVAL; 6286 6287 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6288 6289 mutex_lock(&adev->grbm_idx_mutex); 6290 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6291 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6292 mask = 1; 6293 counter = 0; 6294 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 6295 if (i < 8 && j < 2) 6296 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6297 adev, disable_masks[i * 2 + j]); 6298 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6299 6300 /** 6301 * GFX11 could support more than 4 SEs, while the bitmap 6302 * in cu_info struct is 4x4 and ioctl interface struct 6303 * drm_amdgpu_info_device should keep stable. 6304 * So we use last two columns of bitmap to store cu mask for 6305 * SEs 4 to 7, the layout of the bitmap is as below: 6306 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6307 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6308 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6309 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6310 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6311 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6312 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6313 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6314 */ 6315 cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; 6316 6317 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6318 if (bitmap & mask) 6319 counter++; 6320 6321 mask <<= 1; 6322 } 6323 active_cu_number += counter; 6324 } 6325 } 6326 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6327 mutex_unlock(&adev->grbm_idx_mutex); 6328 6329 cu_info->number = active_cu_number; 6330 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6331 6332 return 0; 6333 } 6334 6335 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6336 { 6337 .type = AMD_IP_BLOCK_TYPE_GFX, 6338 .major = 11, 6339 .minor = 0, 6340 .rev = 0, 6341 .funcs = &gfx_v11_0_ip_funcs, 6342 }; 6343