1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "imu_v11_0.h" 34 #include "soc21.h" 35 #include "nvd.h" 36 37 #include "gc/gc_11_0_0_offset.h" 38 #include "gc/gc_11_0_0_sh_mask.h" 39 #include "smuio/smuio_13_0_6_offset.h" 40 #include "smuio/smuio_13_0_6_sh_mask.h" 41 #include "navi10_enum.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "clearstate_gfx11.h" 47 #include "v11_structs.h" 48 #include "gfx_v11_0.h" 49 #include "gfx_v11_0_3.h" 50 #include "nbio_v4_3.h" 51 #include "mes_v11_0.h" 52 53 #define GFX11_NUM_GFX_RINGS 1 54 #define GFX11_MEC_HPD_SIZE 2048 55 56 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388 58 59 #define regCGTT_WD_CLK_CTRL 0x5086 60 #define regCGTT_WD_CLK_CTRL_BASE_IDX 1 61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e 62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 63 64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); 67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); 68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); 69 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); 71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); 73 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); 75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); 77 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); 78 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); 79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); 80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); 81 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); 82 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); 83 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); 84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); 85 86 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = 87 { 88 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010), 89 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010), 90 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 91 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 97 }; 98 99 #define DEFAULT_SH_MEM_CONFIG \ 100 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 101 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 102 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 103 104 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev); 105 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev); 106 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev); 107 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev); 108 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev); 109 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev); 110 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev); 111 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 112 struct amdgpu_cu_info *cu_info); 113 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 114 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 115 u32 sh_num, u32 instance); 116 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 117 118 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 119 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 120 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 121 uint32_t val); 122 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 123 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 124 uint16_t pasid, uint32_t flush_type, 125 bool all_hub, uint8_t dst_sel); 126 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev); 127 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev); 128 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 129 bool enable); 130 131 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 132 { 133 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 134 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 135 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 136 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 137 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 138 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 139 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 140 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 141 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 142 } 143 144 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, 145 struct amdgpu_ring *ring) 146 { 147 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 148 uint64_t wptr_addr = ring->wptr_gpu_addr; 149 uint32_t me = 0, eng_sel = 0; 150 151 switch (ring->funcs->type) { 152 case AMDGPU_RING_TYPE_COMPUTE: 153 me = 1; 154 eng_sel = 0; 155 break; 156 case AMDGPU_RING_TYPE_GFX: 157 me = 0; 158 eng_sel = 4; 159 break; 160 case AMDGPU_RING_TYPE_MES: 161 me = 2; 162 eng_sel = 5; 163 break; 164 default: 165 WARN_ON(1); 166 } 167 168 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 169 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 170 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 171 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 172 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 173 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 174 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 175 PACKET3_MAP_QUEUES_ME((me)) | 176 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 177 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 178 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 179 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 180 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 181 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 182 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 183 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 184 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 185 } 186 187 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 188 struct amdgpu_ring *ring, 189 enum amdgpu_unmap_queues_action action, 190 u64 gpu_addr, u64 seq) 191 { 192 struct amdgpu_device *adev = kiq_ring->adev; 193 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 194 195 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { 196 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 197 return; 198 } 199 200 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 201 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 202 PACKET3_UNMAP_QUEUES_ACTION(action) | 203 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 204 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 205 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 206 amdgpu_ring_write(kiq_ring, 207 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 208 209 if (action == PREEMPT_QUEUES_NO_UNMAP) { 210 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 211 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 212 amdgpu_ring_write(kiq_ring, seq); 213 } else { 214 amdgpu_ring_write(kiq_ring, 0); 215 amdgpu_ring_write(kiq_ring, 0); 216 amdgpu_ring_write(kiq_ring, 0); 217 } 218 } 219 220 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring, 221 struct amdgpu_ring *ring, 222 u64 addr, 223 u64 seq) 224 { 225 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 226 227 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 228 amdgpu_ring_write(kiq_ring, 229 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 230 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 231 PACKET3_QUERY_STATUS_COMMAND(2)); 232 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 233 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 234 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 235 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 236 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 237 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 238 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 239 } 240 241 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 242 uint16_t pasid, uint32_t flush_type, 243 bool all_hub) 244 { 245 gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 246 } 247 248 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = { 249 .kiq_set_resources = gfx11_kiq_set_resources, 250 .kiq_map_queues = gfx11_kiq_map_queues, 251 .kiq_unmap_queues = gfx11_kiq_unmap_queues, 252 .kiq_query_status = gfx11_kiq_query_status, 253 .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs, 254 .set_resources_size = 8, 255 .map_queues_size = 7, 256 .unmap_queues_size = 6, 257 .query_status_size = 7, 258 .invalidate_tlbs_size = 2, 259 }; 260 261 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 262 { 263 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; 264 } 265 266 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 267 { 268 switch (adev->ip_versions[GC_HWIP][0]) { 269 case IP_VERSION(11, 0, 1): 270 case IP_VERSION(11, 0, 4): 271 soc15_program_register_sequence(adev, 272 golden_settings_gc_11_0_1, 273 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 274 break; 275 default: 276 break; 277 } 278 } 279 280 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 281 bool wc, uint32_t reg, uint32_t val) 282 { 283 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 284 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 285 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 286 amdgpu_ring_write(ring, reg); 287 amdgpu_ring_write(ring, 0); 288 amdgpu_ring_write(ring, val); 289 } 290 291 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 292 int mem_space, int opt, uint32_t addr0, 293 uint32_t addr1, uint32_t ref, uint32_t mask, 294 uint32_t inv) 295 { 296 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 297 amdgpu_ring_write(ring, 298 /* memory (1) or register (0) */ 299 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 300 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 301 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 302 WAIT_REG_MEM_ENGINE(eng_sel))); 303 304 if (mem_space) 305 BUG_ON(addr0 & 0x3); /* Dword align */ 306 amdgpu_ring_write(ring, addr0); 307 amdgpu_ring_write(ring, addr1); 308 amdgpu_ring_write(ring, ref); 309 amdgpu_ring_write(ring, mask); 310 amdgpu_ring_write(ring, inv); /* poll interval */ 311 } 312 313 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) 314 { 315 struct amdgpu_device *adev = ring->adev; 316 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 317 uint32_t tmp = 0; 318 unsigned i; 319 int r; 320 321 WREG32(scratch, 0xCAFEDEAD); 322 r = amdgpu_ring_alloc(ring, 5); 323 if (r) { 324 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 325 ring->idx, r); 326 return r; 327 } 328 329 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { 330 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); 331 } else { 332 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 333 amdgpu_ring_write(ring, scratch - 334 PACKET3_SET_UCONFIG_REG_START); 335 amdgpu_ring_write(ring, 0xDEADBEEF); 336 } 337 amdgpu_ring_commit(ring); 338 339 for (i = 0; i < adev->usec_timeout; i++) { 340 tmp = RREG32(scratch); 341 if (tmp == 0xDEADBEEF) 342 break; 343 if (amdgpu_emu_mode == 1) 344 msleep(1); 345 else 346 udelay(1); 347 } 348 349 if (i >= adev->usec_timeout) 350 r = -ETIMEDOUT; 351 return r; 352 } 353 354 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 355 { 356 struct amdgpu_device *adev = ring->adev; 357 struct amdgpu_ib ib; 358 struct dma_fence *f = NULL; 359 unsigned index; 360 uint64_t gpu_addr; 361 volatile uint32_t *cpu_ptr; 362 long r; 363 364 /* MES KIQ fw hasn't indirect buffer support for now */ 365 if (adev->enable_mes_kiq && 366 ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 367 return 0; 368 369 memset(&ib, 0, sizeof(ib)); 370 371 if (ring->is_mes_queue) { 372 uint32_t padding, offset; 373 374 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 375 padding = amdgpu_mes_ctx_get_offs(ring, 376 AMDGPU_MES_CTX_PADDING_OFFS); 377 378 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 379 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 380 381 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 382 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 383 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 384 } else { 385 r = amdgpu_device_wb_get(adev, &index); 386 if (r) 387 return r; 388 389 gpu_addr = adev->wb.gpu_addr + (index * 4); 390 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 391 cpu_ptr = &adev->wb.wb[index]; 392 393 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); 394 if (r) { 395 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 396 goto err1; 397 } 398 } 399 400 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 401 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 402 ib.ptr[2] = lower_32_bits(gpu_addr); 403 ib.ptr[3] = upper_32_bits(gpu_addr); 404 ib.ptr[4] = 0xDEADBEEF; 405 ib.length_dw = 5; 406 407 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 408 if (r) 409 goto err2; 410 411 r = dma_fence_wait_timeout(f, false, timeout); 412 if (r == 0) { 413 r = -ETIMEDOUT; 414 goto err2; 415 } else if (r < 0) { 416 goto err2; 417 } 418 419 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 420 r = 0; 421 else 422 r = -EINVAL; 423 err2: 424 if (!ring->is_mes_queue) 425 amdgpu_ib_free(adev, &ib, NULL); 426 dma_fence_put(f); 427 err1: 428 if (!ring->is_mes_queue) 429 amdgpu_device_wb_free(adev, index); 430 return r; 431 } 432 433 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) 434 { 435 amdgpu_ucode_release(&adev->gfx.pfp_fw); 436 amdgpu_ucode_release(&adev->gfx.me_fw); 437 amdgpu_ucode_release(&adev->gfx.rlc_fw); 438 amdgpu_ucode_release(&adev->gfx.mec_fw); 439 440 kfree(adev->gfx.rlc.register_list_format); 441 } 442 443 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 444 { 445 const struct psp_firmware_header_v1_0 *toc_hdr; 446 int err = 0; 447 char fw_name[40]; 448 449 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); 450 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name); 451 if (err) 452 goto out; 453 454 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 455 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 456 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 457 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 458 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 459 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 460 return 0; 461 out: 462 amdgpu_ucode_release(&adev->psp.toc_fw); 463 return err; 464 } 465 466 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) 467 { 468 char fw_name[40]; 469 char ucode_prefix[30]; 470 int err; 471 const struct rlc_firmware_header_v2_0 *rlc_hdr; 472 uint16_t version_major; 473 uint16_t version_minor; 474 475 DRM_DEBUG("\n"); 476 477 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 478 479 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); 480 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 481 if (err) 482 goto out; 483 /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ 484 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( 485 (union amdgpu_firmware_header *) 486 adev->gfx.pfp_fw->data, 2, 0); 487 if (adev->gfx.rs64_enable) { 488 dev_info(adev->dev, "CP RS64 enable\n"); 489 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); 490 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); 491 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK); 492 } else { 493 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 494 } 495 496 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); 497 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 498 if (err) 499 goto out; 500 if (adev->gfx.rs64_enable) { 501 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME); 502 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); 503 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK); 504 } else { 505 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 506 } 507 508 if (!amdgpu_sriov_vf(adev)) { 509 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 510 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 511 if (err) 512 goto out; 513 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 514 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 515 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 516 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 517 if (err) 518 goto out; 519 } 520 521 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); 522 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 523 if (err) 524 goto out; 525 if (adev->gfx.rs64_enable) { 526 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 527 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 528 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 529 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 530 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 531 } else { 532 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 533 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 534 } 535 536 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 537 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix); 538 539 /* only one MEC for gfx 11.0.0. */ 540 adev->gfx.mec2_fw = NULL; 541 542 out: 543 if (err) { 544 amdgpu_ucode_release(&adev->gfx.pfp_fw); 545 amdgpu_ucode_release(&adev->gfx.me_fw); 546 amdgpu_ucode_release(&adev->gfx.rlc_fw); 547 amdgpu_ucode_release(&adev->gfx.mec_fw); 548 } 549 550 return err; 551 } 552 553 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) 554 { 555 u32 count = 0; 556 const struct cs_section_def *sect = NULL; 557 const struct cs_extent_def *ext = NULL; 558 559 /* begin clear state */ 560 count += 2; 561 /* context control state */ 562 count += 3; 563 564 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 565 for (ext = sect->section; ext->extent != NULL; ++ext) { 566 if (sect->id == SECT_CONTEXT) 567 count += 2 + ext->reg_count; 568 else 569 return 0; 570 } 571 } 572 573 /* set PA_SC_TILE_STEERING_OVERRIDE */ 574 count += 3; 575 /* end clear state */ 576 count += 2; 577 /* clear state */ 578 count += 2; 579 580 return count; 581 } 582 583 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, 584 volatile u32 *buffer) 585 { 586 u32 count = 0, i; 587 const struct cs_section_def *sect = NULL; 588 const struct cs_extent_def *ext = NULL; 589 int ctx_reg_offset; 590 591 if (adev->gfx.rlc.cs_data == NULL) 592 return; 593 if (buffer == NULL) 594 return; 595 596 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 597 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 598 599 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 600 buffer[count++] = cpu_to_le32(0x80000000); 601 buffer[count++] = cpu_to_le32(0x80000000); 602 603 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 604 for (ext = sect->section; ext->extent != NULL; ++ext) { 605 if (sect->id == SECT_CONTEXT) { 606 buffer[count++] = 607 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 608 buffer[count++] = cpu_to_le32(ext->reg_index - 609 PACKET3_SET_CONTEXT_REG_START); 610 for (i = 0; i < ext->reg_count; i++) 611 buffer[count++] = cpu_to_le32(ext->extent[i]); 612 } else { 613 return; 614 } 615 } 616 } 617 618 ctx_reg_offset = 619 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 620 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 621 buffer[count++] = cpu_to_le32(ctx_reg_offset); 622 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 623 624 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 625 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 626 627 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 628 buffer[count++] = cpu_to_le32(0); 629 } 630 631 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev) 632 { 633 /* clear state block */ 634 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 635 &adev->gfx.rlc.clear_state_gpu_addr, 636 (void **)&adev->gfx.rlc.cs_ptr); 637 638 /* jump table block */ 639 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 640 &adev->gfx.rlc.cp_table_gpu_addr, 641 (void **)&adev->gfx.rlc.cp_table_ptr); 642 } 643 644 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 645 { 646 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 647 648 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 649 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 650 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); 651 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); 652 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); 653 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); 654 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); 655 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); 656 adev->gfx.rlc.rlcg_reg_access_supported = true; 657 } 658 659 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) 660 { 661 const struct cs_section_def *cs_data; 662 int r; 663 664 adev->gfx.rlc.cs_data = gfx11_cs_data; 665 666 cs_data = adev->gfx.rlc.cs_data; 667 668 if (cs_data) { 669 /* init clear state block */ 670 r = amdgpu_gfx_rlc_init_csb(adev); 671 if (r) 672 return r; 673 } 674 675 /* init spm vmid with 0xf */ 676 if (adev->gfx.rlc.funcs->update_spm_vmid) 677 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 678 679 return 0; 680 } 681 682 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev) 683 { 684 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 685 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 686 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 687 } 688 689 static void gfx_v11_0_me_init(struct amdgpu_device *adev) 690 { 691 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 692 693 amdgpu_gfx_graphics_queue_acquire(adev); 694 } 695 696 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) 697 { 698 int r; 699 u32 *hpd; 700 size_t mec_hpd_size; 701 702 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 703 704 /* take ownership of the relevant compute queues */ 705 amdgpu_gfx_compute_queue_acquire(adev); 706 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; 707 708 if (mec_hpd_size) { 709 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 710 AMDGPU_GEM_DOMAIN_GTT, 711 &adev->gfx.mec.hpd_eop_obj, 712 &adev->gfx.mec.hpd_eop_gpu_addr, 713 (void **)&hpd); 714 if (r) { 715 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 716 gfx_v11_0_mec_fini(adev); 717 return r; 718 } 719 720 memset(hpd, 0, mec_hpd_size); 721 722 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 723 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 724 } 725 726 return 0; 727 } 728 729 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 730 { 731 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 732 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 733 (address << SQ_IND_INDEX__INDEX__SHIFT)); 734 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 735 } 736 737 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 738 uint32_t thread, uint32_t regno, 739 uint32_t num, uint32_t *out) 740 { 741 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, 742 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 743 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 744 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 745 (SQ_IND_INDEX__AUTO_INCR_MASK)); 746 while (num--) 747 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 748 } 749 750 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 751 { 752 /* in gfx11 the SIMD_ID is specified as part of the INSTANCE 753 * field when performing a select_se_sh so it should be 754 * zero here */ 755 WARN_ON(simd != 0); 756 757 /* type 3 wave data */ 758 dst[(*no_fields)++] = 3; 759 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 760 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 761 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 762 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 763 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 764 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 765 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 766 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 767 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 768 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 769 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 770 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 771 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 772 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 773 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 774 } 775 776 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 777 uint32_t wave, uint32_t start, 778 uint32_t size, uint32_t *dst) 779 { 780 WARN_ON(simd != 0); 781 782 wave_read_regs( 783 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 784 dst); 785 } 786 787 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 788 uint32_t wave, uint32_t thread, 789 uint32_t start, uint32_t size, 790 uint32_t *dst) 791 { 792 wave_read_regs( 793 adev, wave, thread, 794 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 795 } 796 797 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, 798 u32 me, u32 pipe, u32 q, u32 vm) 799 { 800 soc21_grbm_select(adev, me, pipe, q, vm); 801 } 802 803 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { 804 .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter, 805 .select_se_sh = &gfx_v11_0_select_se_sh, 806 .read_wave_data = &gfx_v11_0_read_wave_data, 807 .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs, 808 .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs, 809 .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, 810 .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, 811 }; 812 813 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) 814 { 815 816 switch (adev->ip_versions[GC_HWIP][0]) { 817 case IP_VERSION(11, 0, 0): 818 case IP_VERSION(11, 0, 2): 819 adev->gfx.config.max_hw_contexts = 8; 820 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 821 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 822 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 823 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 824 break; 825 case IP_VERSION(11, 0, 3): 826 adev->gfx.ras = &gfx_v11_0_3_ras; 827 adev->gfx.config.max_hw_contexts = 8; 828 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 829 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 830 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 831 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 832 break; 833 case IP_VERSION(11, 0, 1): 834 case IP_VERSION(11, 0, 4): 835 adev->gfx.config.max_hw_contexts = 8; 836 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 837 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 838 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 839 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; 840 break; 841 default: 842 BUG(); 843 break; 844 } 845 846 return 0; 847 } 848 849 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 850 int me, int pipe, int queue) 851 { 852 int r; 853 struct amdgpu_ring *ring; 854 unsigned int irq_type; 855 856 ring = &adev->gfx.gfx_ring[ring_id]; 857 858 ring->me = me; 859 ring->pipe = pipe; 860 ring->queue = queue; 861 862 ring->ring_obj = NULL; 863 ring->use_doorbell = true; 864 865 if (!ring_id) 866 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 867 else 868 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 869 ring->vm_hub = AMDGPU_GFXHUB_0; 870 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 871 872 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 873 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 874 AMDGPU_RING_PRIO_DEFAULT, NULL); 875 if (r) 876 return r; 877 return 0; 878 } 879 880 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 881 int mec, int pipe, int queue) 882 { 883 int r; 884 unsigned irq_type; 885 struct amdgpu_ring *ring; 886 unsigned int hw_prio; 887 888 ring = &adev->gfx.compute_ring[ring_id]; 889 890 /* mec0 is me1 */ 891 ring->me = mec + 1; 892 ring->pipe = pipe; 893 ring->queue = queue; 894 895 ring->ring_obj = NULL; 896 ring->use_doorbell = true; 897 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 898 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 899 + (ring_id * GFX11_MEC_HPD_SIZE); 900 ring->vm_hub = AMDGPU_GFXHUB_0; 901 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 902 903 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 904 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 905 + ring->pipe; 906 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 907 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 908 /* type-2 packets are deprecated on MEC, use type-3 instead */ 909 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 910 hw_prio, NULL); 911 if (r) 912 return r; 913 914 return 0; 915 } 916 917 static struct { 918 SOC21_FIRMWARE_ID id; 919 unsigned int offset; 920 unsigned int size; 921 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX]; 922 923 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 924 { 925 RLC_TABLE_OF_CONTENT *ucode = rlc_toc; 926 927 while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) && 928 (ucode->id < SOC21_FIRMWARE_ID_MAX)) { 929 rlc_autoload_info[ucode->id].id = ucode->id; 930 rlc_autoload_info[ucode->id].offset = ucode->offset * 4; 931 rlc_autoload_info[ucode->id].size = ucode->size * 4; 932 933 ucode++; 934 } 935 } 936 937 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev) 938 { 939 uint32_t total_size = 0; 940 SOC21_FIRMWARE_ID id; 941 942 gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr); 943 944 for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++) 945 total_size += rlc_autoload_info[id].size; 946 947 /* In case the offset in rlc toc ucode is aligned */ 948 if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset) 949 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset + 950 rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size; 951 952 return total_size; 953 } 954 955 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev) 956 { 957 int r; 958 uint32_t total_size; 959 960 total_size = gfx_v11_0_calc_toc_total_size(adev); 961 962 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 963 AMDGPU_GEM_DOMAIN_VRAM | 964 AMDGPU_GEM_DOMAIN_GTT, 965 &adev->gfx.rlc.rlc_autoload_bo, 966 &adev->gfx.rlc.rlc_autoload_gpu_addr, 967 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 968 969 if (r) { 970 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 971 return r; 972 } 973 974 return 0; 975 } 976 977 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 978 SOC21_FIRMWARE_ID id, 979 const void *fw_data, 980 uint32_t fw_size, 981 uint32_t *fw_autoload_mask) 982 { 983 uint32_t toc_offset; 984 uint32_t toc_fw_size; 985 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 986 987 if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX) 988 return; 989 990 toc_offset = rlc_autoload_info[id].offset; 991 toc_fw_size = rlc_autoload_info[id].size; 992 993 if (fw_size == 0) 994 fw_size = toc_fw_size; 995 996 if (fw_size > toc_fw_size) 997 fw_size = toc_fw_size; 998 999 memcpy(ptr + toc_offset, fw_data, fw_size); 1000 1001 if (fw_size < toc_fw_size) 1002 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1003 1004 if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME)) 1005 *(uint64_t *)fw_autoload_mask |= 1ULL << id; 1006 } 1007 1008 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev, 1009 uint32_t *fw_autoload_mask) 1010 { 1011 void *data; 1012 uint32_t size; 1013 uint64_t *toc_ptr; 1014 1015 *(uint64_t *)fw_autoload_mask |= 0x1; 1016 1017 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); 1018 1019 data = adev->psp.toc.start_addr; 1020 size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size; 1021 1022 toc_ptr = (uint64_t *)data + size / 8 - 1; 1023 *toc_ptr = *(uint64_t *)fw_autoload_mask; 1024 1025 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC, 1026 data, size, fw_autoload_mask); 1027 } 1028 1029 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev, 1030 uint32_t *fw_autoload_mask) 1031 { 1032 const __le32 *fw_data; 1033 uint32_t fw_size; 1034 const struct gfx_firmware_header_v1_0 *cp_hdr; 1035 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 1036 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1037 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 1038 uint16_t version_major, version_minor; 1039 1040 if (adev->gfx.rs64_enable) { 1041 /* pfp ucode */ 1042 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1043 adev->gfx.pfp_fw->data; 1044 /* instruction */ 1045 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1046 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1047 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1048 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP, 1049 fw_data, fw_size, fw_autoload_mask); 1050 /* data */ 1051 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1052 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1053 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1054 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK, 1055 fw_data, fw_size, fw_autoload_mask); 1056 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK, 1057 fw_data, fw_size, fw_autoload_mask); 1058 /* me ucode */ 1059 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1060 adev->gfx.me_fw->data; 1061 /* instruction */ 1062 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1063 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1064 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1065 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME, 1066 fw_data, fw_size, fw_autoload_mask); 1067 /* data */ 1068 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1069 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1070 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1071 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK, 1072 fw_data, fw_size, fw_autoload_mask); 1073 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK, 1074 fw_data, fw_size, fw_autoload_mask); 1075 /* mec ucode */ 1076 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 1077 adev->gfx.mec_fw->data; 1078 /* instruction */ 1079 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1080 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 1081 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 1082 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC, 1083 fw_data, fw_size, fw_autoload_mask); 1084 /* data */ 1085 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1086 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 1087 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 1088 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK, 1089 fw_data, fw_size, fw_autoload_mask); 1090 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK, 1091 fw_data, fw_size, fw_autoload_mask); 1092 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK, 1093 fw_data, fw_size, fw_autoload_mask); 1094 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK, 1095 fw_data, fw_size, fw_autoload_mask); 1096 } else { 1097 /* pfp ucode */ 1098 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1099 adev->gfx.pfp_fw->data; 1100 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1101 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1102 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1103 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP, 1104 fw_data, fw_size, fw_autoload_mask); 1105 1106 /* me ucode */ 1107 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1108 adev->gfx.me_fw->data; 1109 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1110 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1111 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1112 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME, 1113 fw_data, fw_size, fw_autoload_mask); 1114 1115 /* mec ucode */ 1116 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1117 adev->gfx.mec_fw->data; 1118 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1119 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1120 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1121 cp_hdr->jt_size * 4; 1122 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC, 1123 fw_data, fw_size, fw_autoload_mask); 1124 } 1125 1126 /* rlc ucode */ 1127 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1128 adev->gfx.rlc_fw->data; 1129 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1130 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1131 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1132 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE, 1133 fw_data, fw_size, fw_autoload_mask); 1134 1135 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1136 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1137 if (version_major == 2) { 1138 if (version_minor >= 2) { 1139 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1140 1141 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1142 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1143 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1144 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE, 1145 fw_data, fw_size, fw_autoload_mask); 1146 1147 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1148 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1149 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1150 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT, 1151 fw_data, fw_size, fw_autoload_mask); 1152 } 1153 } 1154 } 1155 1156 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev, 1157 uint32_t *fw_autoload_mask) 1158 { 1159 const __le32 *fw_data; 1160 uint32_t fw_size; 1161 const struct sdma_firmware_header_v2_0 *sdma_hdr; 1162 1163 sdma_hdr = (const struct sdma_firmware_header_v2_0 *) 1164 adev->sdma.instance[0].fw->data; 1165 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1166 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 1167 fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes); 1168 1169 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1170 SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask); 1171 1172 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1173 le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 1174 fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes); 1175 1176 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1177 SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask); 1178 } 1179 1180 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev, 1181 uint32_t *fw_autoload_mask) 1182 { 1183 const __le32 *fw_data; 1184 unsigned fw_size; 1185 const struct mes_firmware_header_v1_0 *mes_hdr; 1186 int pipe, ucode_id, data_id; 1187 1188 for (pipe = 0; pipe < 2; pipe++) { 1189 if (pipe==0) { 1190 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0; 1191 data_id = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK; 1192 } else { 1193 ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1; 1194 data_id = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK; 1195 } 1196 1197 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1198 adev->mes.fw[pipe]->data; 1199 1200 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1201 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1202 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1203 1204 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1205 ucode_id, fw_data, fw_size, fw_autoload_mask); 1206 1207 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1208 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1209 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1210 1211 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, 1212 data_id, fw_data, fw_size, fw_autoload_mask); 1213 } 1214 } 1215 1216 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1217 { 1218 uint32_t rlc_g_offset, rlc_g_size; 1219 uint64_t gpu_addr; 1220 uint32_t autoload_fw_id[2]; 1221 1222 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); 1223 1224 /* RLC autoload sequence 2: copy ucode */ 1225 gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id); 1226 gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id); 1227 gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id); 1228 gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id); 1229 1230 rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset; 1231 rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size; 1232 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 1233 1234 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); 1235 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); 1236 1237 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); 1238 1239 /* RLC autoload sequence 3: load IMU fw */ 1240 if (adev->gfx.imu.funcs->load_microcode) 1241 adev->gfx.imu.funcs->load_microcode(adev); 1242 /* RLC autoload sequence 4 init IMU fw */ 1243 if (adev->gfx.imu.funcs->setup_imu) 1244 adev->gfx.imu.funcs->setup_imu(adev); 1245 if (adev->gfx.imu.funcs->start_imu) 1246 adev->gfx.imu.funcs->start_imu(adev); 1247 1248 /* RLC autoload sequence 5 disable gpa mode */ 1249 gfx_v11_0_disable_gpa_mode(adev); 1250 1251 return 0; 1252 } 1253 1254 static int gfx_v11_0_sw_init(void *handle) 1255 { 1256 int i, j, k, r, ring_id = 0; 1257 struct amdgpu_kiq *kiq; 1258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1259 1260 adev->gfxhub.funcs->init(adev); 1261 1262 switch (adev->ip_versions[GC_HWIP][0]) { 1263 case IP_VERSION(11, 0, 0): 1264 case IP_VERSION(11, 0, 2): 1265 case IP_VERSION(11, 0, 3): 1266 adev->gfx.me.num_me = 1; 1267 adev->gfx.me.num_pipe_per_me = 1; 1268 adev->gfx.me.num_queue_per_pipe = 1; 1269 adev->gfx.mec.num_mec = 2; 1270 adev->gfx.mec.num_pipe_per_mec = 4; 1271 adev->gfx.mec.num_queue_per_pipe = 4; 1272 break; 1273 case IP_VERSION(11, 0, 1): 1274 case IP_VERSION(11, 0, 4): 1275 adev->gfx.me.num_me = 1; 1276 adev->gfx.me.num_pipe_per_me = 1; 1277 adev->gfx.me.num_queue_per_pipe = 1; 1278 adev->gfx.mec.num_mec = 1; 1279 adev->gfx.mec.num_pipe_per_mec = 4; 1280 adev->gfx.mec.num_queue_per_pipe = 4; 1281 break; 1282 default: 1283 adev->gfx.me.num_me = 1; 1284 adev->gfx.me.num_pipe_per_me = 1; 1285 adev->gfx.me.num_queue_per_pipe = 1; 1286 adev->gfx.mec.num_mec = 1; 1287 adev->gfx.mec.num_pipe_per_mec = 4; 1288 adev->gfx.mec.num_queue_per_pipe = 8; 1289 break; 1290 } 1291 1292 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ 1293 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3) && 1294 amdgpu_sriov_is_pp_one_vf(adev)) 1295 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG; 1296 1297 /* EOP Event */ 1298 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1299 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT, 1300 &adev->gfx.eop_irq); 1301 if (r) 1302 return r; 1303 1304 /* Privileged reg */ 1305 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1306 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT, 1307 &adev->gfx.priv_reg_irq); 1308 if (r) 1309 return r; 1310 1311 /* Privileged inst */ 1312 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1313 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT, 1314 &adev->gfx.priv_inst_irq); 1315 if (r) 1316 return r; 1317 1318 /* ECC error */ 1319 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1320 GFX_11_0_0__SRCID__CP_ECC_ERROR, 1321 &adev->gfx.cp_ecc_error_irq); 1322 if (r) 1323 return r; 1324 1325 /* FED error */ 1326 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1327 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, 1328 &adev->gfx.rlc_gc_fed_irq); 1329 if (r) 1330 return r; 1331 1332 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1333 1334 if (adev->gfx.imu.funcs) { 1335 if (adev->gfx.imu.funcs->init_microcode) { 1336 r = adev->gfx.imu.funcs->init_microcode(adev); 1337 if (r) 1338 DRM_ERROR("Failed to load imu firmware!\n"); 1339 } 1340 } 1341 1342 gfx_v11_0_me_init(adev); 1343 1344 r = gfx_v11_0_rlc_init(adev); 1345 if (r) { 1346 DRM_ERROR("Failed to init rlc BOs!\n"); 1347 return r; 1348 } 1349 1350 r = gfx_v11_0_mec_init(adev); 1351 if (r) { 1352 DRM_ERROR("Failed to init MEC BOs!\n"); 1353 return r; 1354 } 1355 1356 /* set up the gfx ring */ 1357 for (i = 0; i < adev->gfx.me.num_me; i++) { 1358 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1359 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1360 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1361 continue; 1362 1363 r = gfx_v11_0_gfx_ring_init(adev, ring_id, 1364 i, k, j); 1365 if (r) 1366 return r; 1367 ring_id++; 1368 } 1369 } 1370 } 1371 1372 ring_id = 0; 1373 /* set up the compute queues - allocate horizontally across pipes */ 1374 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1375 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1376 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1377 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1378 j)) 1379 continue; 1380 1381 r = gfx_v11_0_compute_ring_init(adev, ring_id, 1382 i, k, j); 1383 if (r) 1384 return r; 1385 1386 ring_id++; 1387 } 1388 } 1389 } 1390 1391 if (!adev->enable_mes_kiq) { 1392 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE); 1393 if (r) { 1394 DRM_ERROR("Failed to init KIQ BOs!\n"); 1395 return r; 1396 } 1397 1398 kiq = &adev->gfx.kiq; 1399 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1400 if (r) 1401 return r; 1402 } 1403 1404 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd)); 1405 if (r) 1406 return r; 1407 1408 /* allocate visible FB for rlc auto-loading fw */ 1409 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1410 r = gfx_v11_0_rlc_autoload_buffer_init(adev); 1411 if (r) 1412 return r; 1413 } 1414 1415 r = gfx_v11_0_gpu_early_init(adev); 1416 if (r) 1417 return r; 1418 1419 if (amdgpu_gfx_ras_sw_init(adev)) { 1420 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 1421 return -EINVAL; 1422 } 1423 1424 return 0; 1425 } 1426 1427 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev) 1428 { 1429 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1430 &adev->gfx.pfp.pfp_fw_gpu_addr, 1431 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1432 1433 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj, 1434 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 1435 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 1436 } 1437 1438 static void gfx_v11_0_me_fini(struct amdgpu_device *adev) 1439 { 1440 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1441 &adev->gfx.me.me_fw_gpu_addr, 1442 (void **)&adev->gfx.me.me_fw_ptr); 1443 1444 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj, 1445 &adev->gfx.me.me_fw_data_gpu_addr, 1446 (void **)&adev->gfx.me.me_fw_data_ptr); 1447 } 1448 1449 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1450 { 1451 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1452 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1453 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1454 } 1455 1456 static int gfx_v11_0_sw_fini(void *handle) 1457 { 1458 int i; 1459 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1460 1461 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1462 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1463 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1464 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1465 1466 amdgpu_gfx_mqd_sw_fini(adev); 1467 1468 if (!adev->enable_mes_kiq) { 1469 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1470 amdgpu_gfx_kiq_fini(adev); 1471 } 1472 1473 gfx_v11_0_pfp_fini(adev); 1474 gfx_v11_0_me_fini(adev); 1475 gfx_v11_0_rlc_fini(adev); 1476 gfx_v11_0_mec_fini(adev); 1477 1478 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1479 gfx_v11_0_rlc_autoload_buffer_fini(adev); 1480 1481 gfx_v11_0_free_microcode(adev); 1482 1483 return 0; 1484 } 1485 1486 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1487 u32 sh_num, u32 instance) 1488 { 1489 u32 data; 1490 1491 if (instance == 0xffffffff) 1492 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1493 INSTANCE_BROADCAST_WRITES, 1); 1494 else 1495 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1496 instance); 1497 1498 if (se_num == 0xffffffff) 1499 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1500 1); 1501 else 1502 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1503 1504 if (sh_num == 0xffffffff) 1505 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1506 1); 1507 else 1508 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1509 1510 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); 1511 } 1512 1513 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) 1514 { 1515 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1516 1517 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); 1518 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1519 CC_GC_SA_UNIT_DISABLE, 1520 SA_DISABLE); 1521 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); 1522 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1523 GC_USER_SA_UNIT_DISABLE, 1524 SA_DISABLE); 1525 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1526 adev->gfx.config.max_shader_engines); 1527 1528 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1529 } 1530 1531 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1532 { 1533 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; 1534 u32 rb_mask; 1535 1536 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 1537 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, 1538 CC_RB_BACKEND_DISABLE, 1539 BACKEND_DISABLE); 1540 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 1541 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, 1542 GC_USER_RB_BACKEND_DISABLE, 1543 BACKEND_DISABLE); 1544 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * 1545 adev->gfx.config.max_shader_engines); 1546 1547 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); 1548 } 1549 1550 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) 1551 { 1552 u32 rb_bitmap_width_per_sa; 1553 u32 max_sa; 1554 u32 active_sa_bitmap; 1555 u32 global_active_rb_bitmap; 1556 u32 active_rb_bitmap = 0; 1557 u32 i; 1558 1559 /* query sa bitmap from SA_UNIT_DISABLE registers */ 1560 active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); 1561 /* query rb bitmap from RB_BACKEND_DISABLE registers */ 1562 global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); 1563 1564 /* generate active rb bitmap according to active sa bitmap */ 1565 max_sa = adev->gfx.config.max_shader_engines * 1566 adev->gfx.config.max_sh_per_se; 1567 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / 1568 adev->gfx.config.max_sh_per_se; 1569 for (i = 0; i < max_sa; i++) { 1570 if (active_sa_bitmap & (1 << i)) 1571 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); 1572 } 1573 1574 active_rb_bitmap |= global_active_rb_bitmap; 1575 adev->gfx.config.backend_enable_mask = active_rb_bitmap; 1576 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); 1577 } 1578 1579 #define DEFAULT_SH_MEM_BASES (0x6000) 1580 #define LDS_APP_BASE 0x1 1581 #define SCRATCH_APP_BASE 0x2 1582 1583 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) 1584 { 1585 int i; 1586 uint32_t sh_mem_bases; 1587 uint32_t data; 1588 1589 /* 1590 * Configure apertures: 1591 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1592 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1593 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1594 */ 1595 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | 1596 SCRATCH_APP_BASE; 1597 1598 mutex_lock(&adev->srbm_mutex); 1599 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1600 soc21_grbm_select(adev, 0, 0, 0, i); 1601 /* CP and shaders */ 1602 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1603 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); 1604 1605 /* Enable trap for each kfd vmid. */ 1606 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); 1607 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1608 } 1609 soc21_grbm_select(adev, 0, 0, 0, 0); 1610 mutex_unlock(&adev->srbm_mutex); 1611 1612 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1613 acccess. These should be enabled by FW for target VMIDs. */ 1614 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1615 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); 1616 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); 1617 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); 1618 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); 1619 } 1620 } 1621 1622 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev) 1623 { 1624 int vmid; 1625 1626 /* 1627 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1628 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1629 * the driver can enable them for graphics. VMID0 should maintain 1630 * access so that HWS firmware can save/restore entries. 1631 */ 1632 for (vmid = 1; vmid < 16; vmid++) { 1633 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); 1634 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); 1635 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); 1636 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); 1637 } 1638 } 1639 1640 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev) 1641 { 1642 /* TODO: harvest feature to be added later. */ 1643 } 1644 1645 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev) 1646 { 1647 /* TCCs are global (not instanced). */ 1648 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | 1649 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); 1650 1651 adev->gfx.config.tcc_disabled_mask = 1652 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1653 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1654 } 1655 1656 static void gfx_v11_0_constants_init(struct amdgpu_device *adev) 1657 { 1658 u32 tmp; 1659 int i; 1660 1661 if (!amdgpu_sriov_vf(adev)) 1662 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1663 1664 gfx_v11_0_setup_rb(adev); 1665 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info); 1666 gfx_v11_0_get_tcc_info(adev); 1667 adev->gfx.config.pa_sc_tile_steering_override = 0; 1668 1669 /* Set whether texture coordinate truncation is conformant. */ 1670 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); 1671 adev->gfx.config.ta_cntl2_truncate_coord_mode = 1672 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); 1673 1674 /* XXX SH_MEM regs */ 1675 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1676 mutex_lock(&adev->srbm_mutex); 1677 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1678 soc21_grbm_select(adev, 0, 0, 0, i); 1679 /* CP and shaders */ 1680 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1681 if (i != 0) { 1682 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1683 (adev->gmc.private_aperture_start >> 48)); 1684 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1685 (adev->gmc.shared_aperture_start >> 48)); 1686 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); 1687 } 1688 } 1689 soc21_grbm_select(adev, 0, 0, 0, 0); 1690 1691 mutex_unlock(&adev->srbm_mutex); 1692 1693 gfx_v11_0_init_compute_vmid(adev); 1694 gfx_v11_0_init_gds_vmid(adev); 1695 } 1696 1697 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1698 bool enable) 1699 { 1700 u32 tmp; 1701 1702 if (amdgpu_sriov_vf(adev)) 1703 return; 1704 1705 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); 1706 1707 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1708 enable ? 1 : 0); 1709 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1710 enable ? 1 : 0); 1711 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1712 enable ? 1 : 0); 1713 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1714 enable ? 1 : 0); 1715 1716 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); 1717 } 1718 1719 static int gfx_v11_0_init_csb(struct amdgpu_device *adev) 1720 { 1721 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1722 1723 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, 1724 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1725 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, 1726 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1727 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1728 1729 return 0; 1730 } 1731 1732 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev) 1733 { 1734 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); 1735 1736 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1737 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); 1738 } 1739 1740 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev) 1741 { 1742 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1743 udelay(50); 1744 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1745 udelay(50); 1746 } 1747 1748 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1749 bool enable) 1750 { 1751 uint32_t rlc_pg_cntl; 1752 1753 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 1754 1755 if (!enable) { 1756 /* RLC_PG_CNTL[23] = 0 (default) 1757 * RLC will wait for handshake acks with SMU 1758 * GFXOFF will be enabled 1759 * RLC_PG_CNTL[23] = 1 1760 * RLC will not issue any message to SMU 1761 * hence no handshake between SMU & RLC 1762 * GFXOFF will be disabled 1763 */ 1764 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1765 } else 1766 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1767 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); 1768 } 1769 1770 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev) 1771 { 1772 /* TODO: enable rlc & smu handshake until smu 1773 * and gfxoff feature works as expected */ 1774 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1775 gfx_v11_0_rlc_smu_handshake_cntl(adev, false); 1776 1777 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1778 udelay(50); 1779 } 1780 1781 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev) 1782 { 1783 uint32_t tmp; 1784 1785 /* enable Save Restore Machine */ 1786 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); 1787 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1788 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1789 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); 1790 } 1791 1792 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev) 1793 { 1794 const struct rlc_firmware_header_v2_0 *hdr; 1795 const __le32 *fw_data; 1796 unsigned i, fw_size; 1797 1798 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1799 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1800 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1801 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1802 1803 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, 1804 RLCG_UCODE_LOADING_START_ADDRESS); 1805 1806 for (i = 0; i < fw_size; i++) 1807 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, 1808 le32_to_cpup(fw_data++)); 1809 1810 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1811 } 1812 1813 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev) 1814 { 1815 const struct rlc_firmware_header_v2_2 *hdr; 1816 const __le32 *fw_data; 1817 unsigned i, fw_size; 1818 u32 tmp; 1819 1820 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1821 1822 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1823 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1824 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1825 1826 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); 1827 1828 for (i = 0; i < fw_size; i++) { 1829 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1830 msleep(1); 1831 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, 1832 le32_to_cpup(fw_data++)); 1833 } 1834 1835 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1836 1837 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1838 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1839 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1840 1841 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); 1842 for (i = 0; i < fw_size; i++) { 1843 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1844 msleep(1); 1845 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, 1846 le32_to_cpup(fw_data++)); 1847 } 1848 1849 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1850 1851 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); 1852 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1853 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1854 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); 1855 } 1856 1857 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev) 1858 { 1859 const struct rlc_firmware_header_v2_3 *hdr; 1860 const __le32 *fw_data; 1861 unsigned i, fw_size; 1862 u32 tmp; 1863 1864 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; 1865 1866 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1867 le32_to_cpu(hdr->rlcp_ucode_offset_bytes)); 1868 fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4; 1869 1870 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); 1871 1872 for (i = 0; i < fw_size; i++) { 1873 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1874 msleep(1); 1875 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, 1876 le32_to_cpup(fw_data++)); 1877 } 1878 1879 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); 1880 1881 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); 1882 tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1883 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); 1884 1885 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1886 le32_to_cpu(hdr->rlcv_ucode_offset_bytes)); 1887 fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4; 1888 1889 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); 1890 1891 for (i = 0; i < fw_size; i++) { 1892 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1893 msleep(1); 1894 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, 1895 le32_to_cpup(fw_data++)); 1896 } 1897 1898 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); 1899 1900 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); 1901 tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1); 1902 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); 1903 } 1904 1905 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) 1906 { 1907 const struct rlc_firmware_header_v2_0 *hdr; 1908 uint16_t version_major; 1909 uint16_t version_minor; 1910 1911 if (!adev->gfx.rlc_fw) 1912 return -EINVAL; 1913 1914 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1915 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1916 1917 version_major = le16_to_cpu(hdr->header.header_version_major); 1918 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1919 1920 if (version_major == 2) { 1921 gfx_v11_0_load_rlcg_microcode(adev); 1922 if (amdgpu_dpm == 1) { 1923 if (version_minor >= 2) 1924 gfx_v11_0_load_rlc_iram_dram_microcode(adev); 1925 if (version_minor == 3) 1926 gfx_v11_0_load_rlcp_rlcv_microcode(adev); 1927 } 1928 1929 return 0; 1930 } 1931 1932 return -EINVAL; 1933 } 1934 1935 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev) 1936 { 1937 int r; 1938 1939 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1940 gfx_v11_0_init_csb(adev); 1941 1942 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1943 gfx_v11_0_rlc_enable_srm(adev); 1944 } else { 1945 if (amdgpu_sriov_vf(adev)) { 1946 gfx_v11_0_init_csb(adev); 1947 return 0; 1948 } 1949 1950 adev->gfx.rlc.funcs->stop(adev); 1951 1952 /* disable CG */ 1953 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); 1954 1955 /* disable PG */ 1956 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); 1957 1958 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1959 /* legacy rlc firmware loading */ 1960 r = gfx_v11_0_rlc_load_microcode(adev); 1961 if (r) 1962 return r; 1963 } 1964 1965 gfx_v11_0_init_csb(adev); 1966 1967 adev->gfx.rlc.funcs->start(adev); 1968 } 1969 return 0; 1970 } 1971 1972 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr) 1973 { 1974 uint32_t usec_timeout = 50000; /* wait for 50ms */ 1975 uint32_t tmp; 1976 int i; 1977 1978 /* Trigger an invalidation of the L1 instruction caches */ 1979 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 1980 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1981 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 1982 1983 /* Wait for invalidation complete */ 1984 for (i = 0; i < usec_timeout; i++) { 1985 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 1986 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 1987 INVALIDATE_CACHE_COMPLETE)) 1988 break; 1989 udelay(1); 1990 } 1991 1992 if (i >= usec_timeout) { 1993 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 1994 return -EINVAL; 1995 } 1996 1997 if (amdgpu_emu_mode == 1) 1998 adev->hdp.funcs->flush_hdp(adev, NULL); 1999 2000 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2001 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2002 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2003 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2004 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2005 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2006 2007 /* Program me ucode address into intruction cache address register */ 2008 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2009 lower_32_bits(addr) & 0xFFFFF000); 2010 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2011 upper_32_bits(addr)); 2012 2013 return 0; 2014 } 2015 2016 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr) 2017 { 2018 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2019 uint32_t tmp; 2020 int i; 2021 2022 /* Trigger an invalidation of the L1 instruction caches */ 2023 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2024 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2025 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2026 2027 /* Wait for invalidation complete */ 2028 for (i = 0; i < usec_timeout; i++) { 2029 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2030 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2031 INVALIDATE_CACHE_COMPLETE)) 2032 break; 2033 udelay(1); 2034 } 2035 2036 if (i >= usec_timeout) { 2037 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2038 return -EINVAL; 2039 } 2040 2041 if (amdgpu_emu_mode == 1) 2042 adev->hdp.funcs->flush_hdp(adev, NULL); 2043 2044 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2045 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2046 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2047 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2048 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2049 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2050 2051 /* Program pfp ucode address into intruction cache address register */ 2052 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2053 lower_32_bits(addr) & 0xFFFFF000); 2054 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2055 upper_32_bits(addr)); 2056 2057 return 0; 2058 } 2059 2060 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr) 2061 { 2062 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2063 uint32_t tmp; 2064 int i; 2065 2066 /* Trigger an invalidation of the L1 instruction caches */ 2067 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2068 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2069 2070 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2071 2072 /* Wait for invalidation complete */ 2073 for (i = 0; i < usec_timeout; i++) { 2074 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2075 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2076 INVALIDATE_CACHE_COMPLETE)) 2077 break; 2078 udelay(1); 2079 } 2080 2081 if (i >= usec_timeout) { 2082 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2083 return -EINVAL; 2084 } 2085 2086 if (amdgpu_emu_mode == 1) 2087 adev->hdp.funcs->flush_hdp(adev, NULL); 2088 2089 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2090 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2091 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2092 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2093 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2094 2095 /* Program mec1 ucode address into intruction cache address register */ 2096 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, 2097 lower_32_bits(addr) & 0xFFFFF000); 2098 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2099 upper_32_bits(addr)); 2100 2101 return 0; 2102 } 2103 2104 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2105 { 2106 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2107 uint32_t tmp; 2108 unsigned i, pipe_id; 2109 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2110 2111 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2112 adev->gfx.pfp_fw->data; 2113 2114 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2115 lower_32_bits(addr)); 2116 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2117 upper_32_bits(addr)); 2118 2119 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2120 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2121 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2122 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2123 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2124 2125 /* 2126 * Programming any of the CP_PFP_IC_BASE registers 2127 * forces invalidation of the ME L1 I$. Wait for the 2128 * invalidation complete 2129 */ 2130 for (i = 0; i < usec_timeout; i++) { 2131 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2132 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2133 INVALIDATE_CACHE_COMPLETE)) 2134 break; 2135 udelay(1); 2136 } 2137 2138 if (i >= usec_timeout) { 2139 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2140 return -EINVAL; 2141 } 2142 2143 /* Prime the L1 instruction caches */ 2144 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2145 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2146 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2147 /* Waiting for cache primed*/ 2148 for (i = 0; i < usec_timeout; i++) { 2149 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2150 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2151 ICACHE_PRIMED)) 2152 break; 2153 udelay(1); 2154 } 2155 2156 if (i >= usec_timeout) { 2157 dev_err(adev->dev, "failed to prime instruction cache\n"); 2158 return -EINVAL; 2159 } 2160 2161 mutex_lock(&adev->srbm_mutex); 2162 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2163 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2164 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2165 (pfp_hdr->ucode_start_addr_hi << 30) | 2166 (pfp_hdr->ucode_start_addr_lo >> 2)); 2167 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2168 pfp_hdr->ucode_start_addr_hi >> 2); 2169 2170 /* 2171 * Program CP_ME_CNTL to reset given PIPE to take 2172 * effect of CP_PFP_PRGRM_CNTR_START. 2173 */ 2174 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2175 if (pipe_id == 0) 2176 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2177 PFP_PIPE0_RESET, 1); 2178 else 2179 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2180 PFP_PIPE1_RESET, 1); 2181 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2182 2183 /* Clear pfp pipe0 reset bit. */ 2184 if (pipe_id == 0) 2185 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2186 PFP_PIPE0_RESET, 0); 2187 else 2188 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2189 PFP_PIPE1_RESET, 0); 2190 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2191 2192 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2193 lower_32_bits(addr2)); 2194 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2195 upper_32_bits(addr2)); 2196 } 2197 soc21_grbm_select(adev, 0, 0, 0, 0); 2198 mutex_unlock(&adev->srbm_mutex); 2199 2200 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2201 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2202 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2203 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2204 2205 /* Invalidate the data caches */ 2206 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2207 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2208 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2209 2210 for (i = 0; i < usec_timeout; i++) { 2211 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2212 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2213 INVALIDATE_DCACHE_COMPLETE)) 2214 break; 2215 udelay(1); 2216 } 2217 2218 if (i >= usec_timeout) { 2219 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2220 return -EINVAL; 2221 } 2222 2223 return 0; 2224 } 2225 2226 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2227 { 2228 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2229 uint32_t tmp; 2230 unsigned i, pipe_id; 2231 const struct gfx_firmware_header_v2_0 *me_hdr; 2232 2233 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2234 adev->gfx.me_fw->data; 2235 2236 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2237 lower_32_bits(addr)); 2238 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2239 upper_32_bits(addr)); 2240 2241 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2242 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2243 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2244 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2245 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2246 2247 /* 2248 * Programming any of the CP_ME_IC_BASE registers 2249 * forces invalidation of the ME L1 I$. Wait for the 2250 * invalidation complete 2251 */ 2252 for (i = 0; i < usec_timeout; i++) { 2253 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2254 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2255 INVALIDATE_CACHE_COMPLETE)) 2256 break; 2257 udelay(1); 2258 } 2259 2260 if (i >= usec_timeout) { 2261 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2262 return -EINVAL; 2263 } 2264 2265 /* Prime the instruction caches */ 2266 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2267 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2268 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2269 2270 /* Waiting for instruction cache primed*/ 2271 for (i = 0; i < usec_timeout; i++) { 2272 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2273 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2274 ICACHE_PRIMED)) 2275 break; 2276 udelay(1); 2277 } 2278 2279 if (i >= usec_timeout) { 2280 dev_err(adev->dev, "failed to prime instruction cache\n"); 2281 return -EINVAL; 2282 } 2283 2284 mutex_lock(&adev->srbm_mutex); 2285 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2286 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2287 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2288 (me_hdr->ucode_start_addr_hi << 30) | 2289 (me_hdr->ucode_start_addr_lo >> 2) ); 2290 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2291 me_hdr->ucode_start_addr_hi>>2); 2292 2293 /* 2294 * Program CP_ME_CNTL to reset given PIPE to take 2295 * effect of CP_PFP_PRGRM_CNTR_START. 2296 */ 2297 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2298 if (pipe_id == 0) 2299 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2300 ME_PIPE0_RESET, 1); 2301 else 2302 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2303 ME_PIPE1_RESET, 1); 2304 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2305 2306 /* Clear pfp pipe0 reset bit. */ 2307 if (pipe_id == 0) 2308 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2309 ME_PIPE0_RESET, 0); 2310 else 2311 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2312 ME_PIPE1_RESET, 0); 2313 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2314 2315 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 2316 lower_32_bits(addr2)); 2317 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 2318 upper_32_bits(addr2)); 2319 } 2320 soc21_grbm_select(adev, 0, 0, 0, 0); 2321 mutex_unlock(&adev->srbm_mutex); 2322 2323 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2324 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2325 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2326 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2327 2328 /* Invalidate the data caches */ 2329 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2330 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2331 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2332 2333 for (i = 0; i < usec_timeout; i++) { 2334 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2335 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2336 INVALIDATE_DCACHE_COMPLETE)) 2337 break; 2338 udelay(1); 2339 } 2340 2341 if (i >= usec_timeout) { 2342 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2343 return -EINVAL; 2344 } 2345 2346 return 0; 2347 } 2348 2349 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2) 2350 { 2351 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2352 uint32_t tmp; 2353 unsigned i; 2354 const struct gfx_firmware_header_v2_0 *mec_hdr; 2355 2356 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2357 adev->gfx.mec_fw->data; 2358 2359 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 2360 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2361 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2362 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2363 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 2364 2365 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 2366 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2367 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2368 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 2369 2370 mutex_lock(&adev->srbm_mutex); 2371 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2372 soc21_grbm_select(adev, 1, i, 0, 0); 2373 2374 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); 2375 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 2376 upper_32_bits(addr2)); 2377 2378 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2379 mec_hdr->ucode_start_addr_lo >> 2 | 2380 mec_hdr->ucode_start_addr_hi << 30); 2381 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2382 mec_hdr->ucode_start_addr_hi >> 2); 2383 2384 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); 2385 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 2386 upper_32_bits(addr)); 2387 } 2388 mutex_unlock(&adev->srbm_mutex); 2389 soc21_grbm_select(adev, 0, 0, 0, 0); 2390 2391 /* Trigger an invalidation of the L1 instruction caches */ 2392 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2393 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2394 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 2395 2396 /* Wait for invalidation complete */ 2397 for (i = 0; i < usec_timeout; i++) { 2398 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 2399 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2400 INVALIDATE_DCACHE_COMPLETE)) 2401 break; 2402 udelay(1); 2403 } 2404 2405 if (i >= usec_timeout) { 2406 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2407 return -EINVAL; 2408 } 2409 2410 /* Trigger an invalidation of the L1 instruction caches */ 2411 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2412 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2413 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 2414 2415 /* Wait for invalidation complete */ 2416 for (i = 0; i < usec_timeout; i++) { 2417 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 2418 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2419 INVALIDATE_CACHE_COMPLETE)) 2420 break; 2421 udelay(1); 2422 } 2423 2424 if (i >= usec_timeout) { 2425 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2426 return -EINVAL; 2427 } 2428 2429 return 0; 2430 } 2431 2432 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 2433 { 2434 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2435 const struct gfx_firmware_header_v2_0 *me_hdr; 2436 const struct gfx_firmware_header_v2_0 *mec_hdr; 2437 uint32_t pipe_id, tmp; 2438 2439 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 2440 adev->gfx.mec_fw->data; 2441 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2442 adev->gfx.me_fw->data; 2443 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2444 adev->gfx.pfp_fw->data; 2445 2446 /* config pfp program start addr */ 2447 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2448 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2449 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2450 (pfp_hdr->ucode_start_addr_hi << 30) | 2451 (pfp_hdr->ucode_start_addr_lo >> 2)); 2452 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2453 pfp_hdr->ucode_start_addr_hi >> 2); 2454 } 2455 soc21_grbm_select(adev, 0, 0, 0, 0); 2456 2457 /* reset pfp pipe */ 2458 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2459 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1); 2460 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1); 2461 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2462 2463 /* clear pfp pipe reset */ 2464 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); 2465 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); 2466 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2467 2468 /* config me program start addr */ 2469 for (pipe_id = 0; pipe_id < 2; pipe_id++) { 2470 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2471 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2472 (me_hdr->ucode_start_addr_hi << 30) | 2473 (me_hdr->ucode_start_addr_lo >> 2) ); 2474 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2475 me_hdr->ucode_start_addr_hi>>2); 2476 } 2477 soc21_grbm_select(adev, 0, 0, 0, 0); 2478 2479 /* reset me pipe */ 2480 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2481 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); 2482 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); 2483 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2484 2485 /* clear me pipe reset */ 2486 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); 2487 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); 2488 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2489 2490 /* config mec program start addr */ 2491 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 2492 soc21_grbm_select(adev, 1, pipe_id, 0, 0); 2493 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 2494 mec_hdr->ucode_start_addr_lo >> 2 | 2495 mec_hdr->ucode_start_addr_hi << 30); 2496 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 2497 mec_hdr->ucode_start_addr_hi >> 2); 2498 } 2499 soc21_grbm_select(adev, 0, 0, 0, 0); 2500 2501 /* reset mec pipe */ 2502 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 2503 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 2504 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 2505 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 2506 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 2507 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2508 2509 /* clear mec pipe reset */ 2510 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 2511 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 2512 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 2513 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 2514 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); 2515 } 2516 2517 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2518 { 2519 uint32_t cp_status; 2520 uint32_t bootload_status; 2521 int i, r; 2522 uint64_t addr, addr2; 2523 2524 for (i = 0; i < adev->usec_timeout; i++) { 2525 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); 2526 2527 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) || 2528 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4)) 2529 bootload_status = RREG32_SOC15(GC, 0, 2530 regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); 2531 else 2532 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); 2533 2534 if ((cp_status == 0) && 2535 (REG_GET_FIELD(bootload_status, 2536 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2537 break; 2538 } 2539 udelay(1); 2540 } 2541 2542 if (i >= adev->usec_timeout) { 2543 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2544 return -ETIMEDOUT; 2545 } 2546 2547 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2548 if (adev->gfx.rs64_enable) { 2549 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2550 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset; 2551 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2552 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset; 2553 r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2); 2554 if (r) 2555 return r; 2556 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2557 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset; 2558 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2559 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset; 2560 r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2); 2561 if (r) 2562 return r; 2563 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2564 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset; 2565 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr + 2566 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset; 2567 r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2); 2568 if (r) 2569 return r; 2570 } else { 2571 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2572 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset; 2573 r = gfx_v11_0_config_me_cache(adev, addr); 2574 if (r) 2575 return r; 2576 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2577 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset; 2578 r = gfx_v11_0_config_pfp_cache(adev, addr); 2579 if (r) 2580 return r; 2581 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2582 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset; 2583 r = gfx_v11_0_config_mec_cache(adev, addr); 2584 if (r) 2585 return r; 2586 } 2587 } 2588 2589 return 0; 2590 } 2591 2592 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2593 { 2594 int i; 2595 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2596 2597 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2598 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2599 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2600 2601 for (i = 0; i < adev->usec_timeout; i++) { 2602 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) 2603 break; 2604 udelay(1); 2605 } 2606 2607 if (i >= adev->usec_timeout) 2608 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2609 2610 return 0; 2611 } 2612 2613 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2614 { 2615 int r; 2616 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2617 const __le32 *fw_data; 2618 unsigned i, fw_size; 2619 2620 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2621 adev->gfx.pfp_fw->data; 2622 2623 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2624 2625 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2626 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2627 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2628 2629 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2630 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2631 &adev->gfx.pfp.pfp_fw_obj, 2632 &adev->gfx.pfp.pfp_fw_gpu_addr, 2633 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2634 if (r) { 2635 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2636 gfx_v11_0_pfp_fini(adev); 2637 return r; 2638 } 2639 2640 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2641 2642 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2643 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2644 2645 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr); 2646 2647 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); 2648 2649 for (i = 0; i < pfp_hdr->jt_size; i++) 2650 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, 2651 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 2652 2653 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2654 2655 return 0; 2656 } 2657 2658 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev) 2659 { 2660 int r; 2661 const struct gfx_firmware_header_v2_0 *pfp_hdr; 2662 const __le32 *fw_ucode, *fw_data; 2663 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2664 uint32_t tmp; 2665 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2666 2667 pfp_hdr = (const struct gfx_firmware_header_v2_0 *) 2668 adev->gfx.pfp_fw->data; 2669 2670 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2671 2672 /* instruction */ 2673 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data + 2674 le32_to_cpu(pfp_hdr->ucode_offset_bytes)); 2675 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes); 2676 /* data */ 2677 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2678 le32_to_cpu(pfp_hdr->data_offset_bytes)); 2679 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes); 2680 2681 /* 64kb align */ 2682 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2683 64 * 1024, 2684 AMDGPU_GEM_DOMAIN_VRAM | 2685 AMDGPU_GEM_DOMAIN_GTT, 2686 &adev->gfx.pfp.pfp_fw_obj, 2687 &adev->gfx.pfp.pfp_fw_gpu_addr, 2688 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2689 if (r) { 2690 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r); 2691 gfx_v11_0_pfp_fini(adev); 2692 return r; 2693 } 2694 2695 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2696 64 * 1024, 2697 AMDGPU_GEM_DOMAIN_VRAM | 2698 AMDGPU_GEM_DOMAIN_GTT, 2699 &adev->gfx.pfp.pfp_fw_data_obj, 2700 &adev->gfx.pfp.pfp_fw_data_gpu_addr, 2701 (void **)&adev->gfx.pfp.pfp_fw_data_ptr); 2702 if (r) { 2703 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r); 2704 gfx_v11_0_pfp_fini(adev); 2705 return r; 2706 } 2707 2708 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size); 2709 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size); 2710 2711 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2712 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj); 2713 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2714 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj); 2715 2716 if (amdgpu_emu_mode == 1) 2717 adev->hdp.funcs->flush_hdp(adev, NULL); 2718 2719 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, 2720 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2721 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, 2722 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2723 2724 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); 2725 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2726 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2727 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2728 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); 2729 2730 /* 2731 * Programming any of the CP_PFP_IC_BASE registers 2732 * forces invalidation of the ME L1 I$. Wait for the 2733 * invalidation complete 2734 */ 2735 for (i = 0; i < usec_timeout; i++) { 2736 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2737 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2738 INVALIDATE_CACHE_COMPLETE)) 2739 break; 2740 udelay(1); 2741 } 2742 2743 if (i >= usec_timeout) { 2744 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2745 return -EINVAL; 2746 } 2747 2748 /* Prime the L1 instruction caches */ 2749 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2750 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1); 2751 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); 2752 /* Waiting for cache primed*/ 2753 for (i = 0; i < usec_timeout; i++) { 2754 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); 2755 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2756 ICACHE_PRIMED)) 2757 break; 2758 udelay(1); 2759 } 2760 2761 if (i >= usec_timeout) { 2762 dev_err(adev->dev, "failed to prime instruction cache\n"); 2763 return -EINVAL; 2764 } 2765 2766 mutex_lock(&adev->srbm_mutex); 2767 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2768 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2769 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, 2770 (pfp_hdr->ucode_start_addr_hi << 30) | 2771 (pfp_hdr->ucode_start_addr_lo >> 2) ); 2772 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, 2773 pfp_hdr->ucode_start_addr_hi>>2); 2774 2775 /* 2776 * Program CP_ME_CNTL to reset given PIPE to take 2777 * effect of CP_PFP_PRGRM_CNTR_START. 2778 */ 2779 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2780 if (pipe_id == 0) 2781 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2782 PFP_PIPE0_RESET, 1); 2783 else 2784 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2785 PFP_PIPE1_RESET, 1); 2786 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2787 2788 /* Clear pfp pipe0 reset bit. */ 2789 if (pipe_id == 0) 2790 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2791 PFP_PIPE0_RESET, 0); 2792 else 2793 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 2794 PFP_PIPE1_RESET, 0); 2795 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 2796 2797 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, 2798 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2799 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, 2800 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr)); 2801 } 2802 soc21_grbm_select(adev, 0, 0, 0, 0); 2803 mutex_unlock(&adev->srbm_mutex); 2804 2805 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 2806 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 2807 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 2808 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 2809 2810 /* Invalidate the data caches */ 2811 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2812 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2813 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 2814 2815 for (i = 0; i < usec_timeout; i++) { 2816 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 2817 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 2818 INVALIDATE_DCACHE_COMPLETE)) 2819 break; 2820 udelay(1); 2821 } 2822 2823 if (i >= usec_timeout) { 2824 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 2825 return -EINVAL; 2826 } 2827 2828 return 0; 2829 } 2830 2831 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2832 { 2833 int r; 2834 const struct gfx_firmware_header_v1_0 *me_hdr; 2835 const __le32 *fw_data; 2836 unsigned i, fw_size; 2837 2838 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2839 adev->gfx.me_fw->data; 2840 2841 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2842 2843 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2844 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2845 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2846 2847 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2848 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2849 &adev->gfx.me.me_fw_obj, 2850 &adev->gfx.me.me_fw_gpu_addr, 2851 (void **)&adev->gfx.me.me_fw_ptr); 2852 if (r) { 2853 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2854 gfx_v11_0_me_fini(adev); 2855 return r; 2856 } 2857 2858 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2859 2860 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2861 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2862 2863 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr); 2864 2865 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); 2866 2867 for (i = 0; i < me_hdr->jt_size; i++) 2868 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, 2869 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 2870 2871 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 2872 2873 return 0; 2874 } 2875 2876 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev) 2877 { 2878 int r; 2879 const struct gfx_firmware_header_v2_0 *me_hdr; 2880 const __le32 *fw_ucode, *fw_data; 2881 unsigned i, pipe_id, fw_ucode_size, fw_data_size; 2882 uint32_t tmp; 2883 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2884 2885 me_hdr = (const struct gfx_firmware_header_v2_0 *) 2886 adev->gfx.me_fw->data; 2887 2888 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2889 2890 /* instruction */ 2891 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data + 2892 le32_to_cpu(me_hdr->ucode_offset_bytes)); 2893 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); 2894 /* data */ 2895 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2896 le32_to_cpu(me_hdr->data_offset_bytes)); 2897 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes); 2898 2899 /* 64kb align*/ 2900 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2901 64 * 1024, 2902 AMDGPU_GEM_DOMAIN_VRAM | 2903 AMDGPU_GEM_DOMAIN_GTT, 2904 &adev->gfx.me.me_fw_obj, 2905 &adev->gfx.me.me_fw_gpu_addr, 2906 (void **)&adev->gfx.me.me_fw_ptr); 2907 if (r) { 2908 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r); 2909 gfx_v11_0_me_fini(adev); 2910 return r; 2911 } 2912 2913 r = amdgpu_bo_create_reserved(adev, fw_data_size, 2914 64 * 1024, 2915 AMDGPU_GEM_DOMAIN_VRAM | 2916 AMDGPU_GEM_DOMAIN_GTT, 2917 &adev->gfx.me.me_fw_data_obj, 2918 &adev->gfx.me.me_fw_data_gpu_addr, 2919 (void **)&adev->gfx.me.me_fw_data_ptr); 2920 if (r) { 2921 dev_err(adev->dev, "(%d) failed to create me data bo\n", r); 2922 gfx_v11_0_pfp_fini(adev); 2923 return r; 2924 } 2925 2926 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size); 2927 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size); 2928 2929 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2930 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj); 2931 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2932 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj); 2933 2934 if (amdgpu_emu_mode == 1) 2935 adev->hdp.funcs->flush_hdp(adev, NULL); 2936 2937 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, 2938 lower_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2939 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, 2940 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2941 2942 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); 2943 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2944 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2945 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2946 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); 2947 2948 /* 2949 * Programming any of the CP_ME_IC_BASE registers 2950 * forces invalidation of the ME L1 I$. Wait for the 2951 * invalidation complete 2952 */ 2953 for (i = 0; i < usec_timeout; i++) { 2954 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2955 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2956 INVALIDATE_CACHE_COMPLETE)) 2957 break; 2958 udelay(1); 2959 } 2960 2961 if (i >= usec_timeout) { 2962 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2963 return -EINVAL; 2964 } 2965 2966 /* Prime the instruction caches */ 2967 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2968 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1); 2969 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); 2970 2971 /* Waiting for instruction cache primed*/ 2972 for (i = 0; i < usec_timeout; i++) { 2973 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); 2974 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2975 ICACHE_PRIMED)) 2976 break; 2977 udelay(1); 2978 } 2979 2980 if (i >= usec_timeout) { 2981 dev_err(adev->dev, "failed to prime instruction cache\n"); 2982 return -EINVAL; 2983 } 2984 2985 mutex_lock(&adev->srbm_mutex); 2986 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { 2987 soc21_grbm_select(adev, 0, pipe_id, 0, 0); 2988 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, 2989 (me_hdr->ucode_start_addr_hi << 30) | 2990 (me_hdr->ucode_start_addr_lo >> 2) ); 2991 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, 2992 me_hdr->ucode_start_addr_hi>>2); 2993 2994 /* 2995 * Program CP_ME_CNTL to reset given PIPE to take 2996 * effect of CP_PFP_PRGRM_CNTR_START. 2997 */ 2998 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); 2999 if (pipe_id == 0) 3000 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3001 ME_PIPE0_RESET, 1); 3002 else 3003 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3004 ME_PIPE1_RESET, 1); 3005 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3006 3007 /* Clear pfp pipe0 reset bit. */ 3008 if (pipe_id == 0) 3009 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3010 ME_PIPE0_RESET, 0); 3011 else 3012 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, 3013 ME_PIPE1_RESET, 0); 3014 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); 3015 3016 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, 3017 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3018 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, 3019 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr)); 3020 } 3021 soc21_grbm_select(adev, 0, 0, 0, 0); 3022 mutex_unlock(&adev->srbm_mutex); 3023 3024 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); 3025 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); 3026 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); 3027 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); 3028 3029 /* Invalidate the data caches */ 3030 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3031 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3032 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); 3033 3034 for (i = 0; i < usec_timeout; i++) { 3035 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); 3036 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, 3037 INVALIDATE_DCACHE_COMPLETE)) 3038 break; 3039 udelay(1); 3040 } 3041 3042 if (i >= usec_timeout) { 3043 dev_err(adev->dev, "failed to invalidate RS64 data cache\n"); 3044 return -EINVAL; 3045 } 3046 3047 return 0; 3048 } 3049 3050 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3051 { 3052 int r; 3053 3054 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw) 3055 return -EINVAL; 3056 3057 gfx_v11_0_cp_gfx_enable(adev, false); 3058 3059 if (adev->gfx.rs64_enable) 3060 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev); 3061 else 3062 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev); 3063 if (r) { 3064 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 3065 return r; 3066 } 3067 3068 if (adev->gfx.rs64_enable) 3069 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev); 3070 else 3071 r = gfx_v11_0_cp_gfx_load_me_microcode(adev); 3072 if (r) { 3073 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 3074 return r; 3075 } 3076 3077 return 0; 3078 } 3079 3080 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) 3081 { 3082 struct amdgpu_ring *ring; 3083 const struct cs_section_def *sect = NULL; 3084 const struct cs_extent_def *ext = NULL; 3085 int r, i; 3086 int ctx_reg_offset; 3087 3088 /* init the CP */ 3089 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, 3090 adev->gfx.config.max_hw_contexts - 1); 3091 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); 3092 3093 if (!amdgpu_async_gfx_ring) 3094 gfx_v11_0_cp_gfx_enable(adev, true); 3095 3096 ring = &adev->gfx.gfx_ring[0]; 3097 r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); 3098 if (r) { 3099 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3100 return r; 3101 } 3102 3103 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3104 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3105 3106 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3107 amdgpu_ring_write(ring, 0x80000000); 3108 amdgpu_ring_write(ring, 0x80000000); 3109 3110 for (sect = gfx11_cs_data; sect->section != NULL; ++sect) { 3111 for (ext = sect->section; ext->extent != NULL; ++ext) { 3112 if (sect->id == SECT_CONTEXT) { 3113 amdgpu_ring_write(ring, 3114 PACKET3(PACKET3_SET_CONTEXT_REG, 3115 ext->reg_count)); 3116 amdgpu_ring_write(ring, ext->reg_index - 3117 PACKET3_SET_CONTEXT_REG_START); 3118 for (i = 0; i < ext->reg_count; i++) 3119 amdgpu_ring_write(ring, ext->extent[i]); 3120 } 3121 } 3122 } 3123 3124 ctx_reg_offset = 3125 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 3126 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3127 amdgpu_ring_write(ring, ctx_reg_offset); 3128 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 3129 3130 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3131 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3132 3133 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3134 amdgpu_ring_write(ring, 0); 3135 3136 amdgpu_ring_commit(ring); 3137 3138 /* submit cs packet to copy state 0 to next available state */ 3139 if (adev->gfx.num_gfx_rings > 1) { 3140 /* maximum supported gfx ring is 2 */ 3141 ring = &adev->gfx.gfx_ring[1]; 3142 r = amdgpu_ring_alloc(ring, 2); 3143 if (r) { 3144 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3145 return r; 3146 } 3147 3148 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3149 amdgpu_ring_write(ring, 0); 3150 3151 amdgpu_ring_commit(ring); 3152 } 3153 return 0; 3154 } 3155 3156 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 3157 CP_PIPE_ID pipe) 3158 { 3159 u32 tmp; 3160 3161 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 3162 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 3163 3164 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 3165 } 3166 3167 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 3168 struct amdgpu_ring *ring) 3169 { 3170 u32 tmp; 3171 3172 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3173 if (ring->use_doorbell) { 3174 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3175 DOORBELL_OFFSET, ring->doorbell_index); 3176 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3177 DOORBELL_EN, 1); 3178 } else { 3179 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3180 DOORBELL_EN, 0); 3181 } 3182 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); 3183 3184 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3185 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3186 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); 3187 3188 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3189 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3190 } 3191 3192 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 3193 { 3194 struct amdgpu_ring *ring; 3195 u32 tmp; 3196 u32 rb_bufsz; 3197 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3198 u32 i; 3199 3200 /* Set the write pointer delay */ 3201 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); 3202 3203 /* set the RB to use vmid 0 */ 3204 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); 3205 3206 /* Init gfx ring 0 for pipe 0 */ 3207 mutex_lock(&adev->srbm_mutex); 3208 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3209 3210 /* Set ring buffer size */ 3211 ring = &adev->gfx.gfx_ring[0]; 3212 rb_bufsz = order_base_2(ring->ring_size / 8); 3213 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3214 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3215 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3216 3217 /* Initialize the ring buffer's write pointers */ 3218 ring->wptr = 0; 3219 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3220 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3221 3222 /* set the wb address wether it's enabled or not */ 3223 rptr_addr = ring->rptr_gpu_addr; 3224 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3225 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3226 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3227 3228 wptr_gpu_addr = ring->wptr_gpu_addr; 3229 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3230 lower_32_bits(wptr_gpu_addr)); 3231 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3232 upper_32_bits(wptr_gpu_addr)); 3233 3234 mdelay(1); 3235 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); 3236 3237 rb_addr = ring->gpu_addr >> 8; 3238 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); 3239 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3240 3241 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); 3242 3243 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3244 mutex_unlock(&adev->srbm_mutex); 3245 3246 /* Init gfx ring 1 for pipe 1 */ 3247 if (adev->gfx.num_gfx_rings > 1) { 3248 mutex_lock(&adev->srbm_mutex); 3249 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 3250 /* maximum supported gfx ring is 2 */ 3251 ring = &adev->gfx.gfx_ring[1]; 3252 rb_bufsz = order_base_2(ring->ring_size / 8); 3253 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 3254 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3255 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3256 /* Initialize the ring buffer's write pointers */ 3257 ring->wptr = 0; 3258 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); 3259 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 3260 /* Set the wb address wether it's enabled or not */ 3261 rptr_addr = ring->rptr_gpu_addr; 3262 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 3263 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 3264 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3265 wptr_gpu_addr = ring->wptr_gpu_addr; 3266 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, 3267 lower_32_bits(wptr_gpu_addr)); 3268 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, 3269 upper_32_bits(wptr_gpu_addr)); 3270 3271 mdelay(1); 3272 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); 3273 3274 rb_addr = ring->gpu_addr >> 8; 3275 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); 3276 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 3277 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); 3278 3279 gfx_v11_0_cp_gfx_set_doorbell(adev, ring); 3280 mutex_unlock(&adev->srbm_mutex); 3281 } 3282 /* Switch to pipe 0 */ 3283 mutex_lock(&adev->srbm_mutex); 3284 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 3285 mutex_unlock(&adev->srbm_mutex); 3286 3287 /* start the ring */ 3288 gfx_v11_0_cp_gfx_start(adev); 3289 3290 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3291 ring = &adev->gfx.gfx_ring[i]; 3292 ring->sched.ready = true; 3293 } 3294 3295 return 0; 3296 } 3297 3298 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3299 { 3300 u32 data; 3301 3302 if (adev->gfx.rs64_enable) { 3303 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 3304 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 3305 enable ? 0 : 1); 3306 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 3307 enable ? 0 : 1); 3308 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 3309 enable ? 0 : 1); 3310 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 3311 enable ? 0 : 1); 3312 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 3313 enable ? 0 : 1); 3314 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 3315 enable ? 1 : 0); 3316 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 3317 enable ? 1 : 0); 3318 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 3319 enable ? 1 : 0); 3320 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 3321 enable ? 1 : 0); 3322 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 3323 enable ? 0 : 1); 3324 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); 3325 } else { 3326 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 3327 3328 if (enable) { 3329 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); 3330 if (!adev->enable_mes_kiq) 3331 data = REG_SET_FIELD(data, CP_MEC_CNTL, 3332 MEC_ME2_HALT, 0); 3333 } else { 3334 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); 3335 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); 3336 } 3337 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); 3338 } 3339 3340 adev->gfx.kiq.ring.sched.ready = enable; 3341 3342 udelay(50); 3343 } 3344 3345 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3346 { 3347 const struct gfx_firmware_header_v1_0 *mec_hdr; 3348 const __le32 *fw_data; 3349 unsigned i, fw_size; 3350 u32 *fw = NULL; 3351 int r; 3352 3353 if (!adev->gfx.mec_fw) 3354 return -EINVAL; 3355 3356 gfx_v11_0_cp_compute_enable(adev, false); 3357 3358 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3359 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3360 3361 fw_data = (const __le32 *) 3362 (adev->gfx.mec_fw->data + 3363 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3364 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 3365 3366 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 3367 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 3368 &adev->gfx.mec.mec_fw_obj, 3369 &adev->gfx.mec.mec_fw_gpu_addr, 3370 (void **)&fw); 3371 if (r) { 3372 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 3373 gfx_v11_0_mec_fini(adev); 3374 return r; 3375 } 3376 3377 memcpy(fw, fw_data, fw_size); 3378 3379 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3380 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3381 3382 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr); 3383 3384 /* MEC1 */ 3385 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); 3386 3387 for (i = 0; i < mec_hdr->jt_size; i++) 3388 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, 3389 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3390 3391 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3392 3393 return 0; 3394 } 3395 3396 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev) 3397 { 3398 const struct gfx_firmware_header_v2_0 *mec_hdr; 3399 const __le32 *fw_ucode, *fw_data; 3400 u32 tmp, fw_ucode_size, fw_data_size; 3401 u32 i, usec_timeout = 50000; /* Wait for 50 ms */ 3402 u32 *fw_ucode_ptr, *fw_data_ptr; 3403 int r; 3404 3405 if (!adev->gfx.mec_fw) 3406 return -EINVAL; 3407 3408 gfx_v11_0_cp_compute_enable(adev, false); 3409 3410 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 3411 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3412 3413 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 3414 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 3415 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 3416 3417 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 3418 le32_to_cpu(mec_hdr->data_offset_bytes)); 3419 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 3420 3421 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 3422 64 * 1024, 3423 AMDGPU_GEM_DOMAIN_VRAM | 3424 AMDGPU_GEM_DOMAIN_GTT, 3425 &adev->gfx.mec.mec_fw_obj, 3426 &adev->gfx.mec.mec_fw_gpu_addr, 3427 (void **)&fw_ucode_ptr); 3428 if (r) { 3429 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3430 gfx_v11_0_mec_fini(adev); 3431 return r; 3432 } 3433 3434 r = amdgpu_bo_create_reserved(adev, fw_data_size, 3435 64 * 1024, 3436 AMDGPU_GEM_DOMAIN_VRAM | 3437 AMDGPU_GEM_DOMAIN_GTT, 3438 &adev->gfx.mec.mec_fw_data_obj, 3439 &adev->gfx.mec.mec_fw_data_gpu_addr, 3440 (void **)&fw_data_ptr); 3441 if (r) { 3442 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 3443 gfx_v11_0_mec_fini(adev); 3444 return r; 3445 } 3446 3447 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 3448 memcpy(fw_data_ptr, fw_data, fw_data_size); 3449 3450 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 3451 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 3452 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 3453 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 3454 3455 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); 3456 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3457 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 3458 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3459 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); 3460 3461 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); 3462 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 3463 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 3464 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); 3465 3466 mutex_lock(&adev->srbm_mutex); 3467 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3468 soc21_grbm_select(adev, 1, i, 0, 0); 3469 3470 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); 3471 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, 3472 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr)); 3473 3474 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, 3475 mec_hdr->ucode_start_addr_lo >> 2 | 3476 mec_hdr->ucode_start_addr_hi << 30); 3477 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, 3478 mec_hdr->ucode_start_addr_hi >> 2); 3479 3480 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); 3481 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, 3482 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3483 } 3484 mutex_unlock(&adev->srbm_mutex); 3485 soc21_grbm_select(adev, 0, 0, 0, 0); 3486 3487 /* Trigger an invalidation of the L1 instruction caches */ 3488 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3489 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 3490 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); 3491 3492 /* Wait for invalidation complete */ 3493 for (i = 0; i < usec_timeout; i++) { 3494 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); 3495 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 3496 INVALIDATE_DCACHE_COMPLETE)) 3497 break; 3498 udelay(1); 3499 } 3500 3501 if (i >= usec_timeout) { 3502 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3503 return -EINVAL; 3504 } 3505 3506 /* Trigger an invalidation of the L1 instruction caches */ 3507 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3508 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 3509 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); 3510 3511 /* Wait for invalidation complete */ 3512 for (i = 0; i < usec_timeout; i++) { 3513 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); 3514 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 3515 INVALIDATE_CACHE_COMPLETE)) 3516 break; 3517 udelay(1); 3518 } 3519 3520 if (i >= usec_timeout) { 3521 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 3522 return -EINVAL; 3523 } 3524 3525 return 0; 3526 } 3527 3528 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring) 3529 { 3530 uint32_t tmp; 3531 struct amdgpu_device *adev = ring->adev; 3532 3533 /* tell RLC which is KIQ queue */ 3534 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 3535 tmp &= 0xffffff00; 3536 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3537 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3538 tmp |= 0x80; 3539 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 3540 } 3541 3542 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev) 3543 { 3544 /* set graphics engine doorbell range */ 3545 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, 3546 (adev->doorbell_index.gfx_ring0 * 2) << 2); 3547 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, 3548 (adev->doorbell_index.gfx_userqueue_end * 2) << 2); 3549 3550 /* set compute engine doorbell range */ 3551 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 3552 (adev->doorbell_index.kiq * 2) << 2); 3553 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 3554 (adev->doorbell_index.userqueue_end * 2) << 2); 3555 } 3556 3557 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 3558 struct amdgpu_mqd_prop *prop) 3559 { 3560 struct v11_gfx_mqd *mqd = m; 3561 uint64_t hqd_gpu_addr, wb_gpu_addr; 3562 uint32_t tmp; 3563 uint32_t rb_bufsz; 3564 3565 /* set up gfx hqd wptr */ 3566 mqd->cp_gfx_hqd_wptr = 0; 3567 mqd->cp_gfx_hqd_wptr_hi = 0; 3568 3569 /* set the pointer to the MQD */ 3570 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 3571 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3572 3573 /* set up mqd control */ 3574 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); 3575 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3576 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3577 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3578 mqd->cp_gfx_mqd_control = tmp; 3579 3580 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3581 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); 3582 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3583 mqd->cp_gfx_hqd_vmid = 0; 3584 3585 /* set up default queue priority level 3586 * 0x0 = low priority, 0x1 = high priority */ 3587 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); 3588 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3589 mqd->cp_gfx_hqd_queue_priority = tmp; 3590 3591 /* set up time quantum */ 3592 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); 3593 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3594 mqd->cp_gfx_hqd_quantum = tmp; 3595 3596 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3597 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3598 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3599 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3600 3601 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3602 wb_gpu_addr = prop->rptr_gpu_addr; 3603 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3604 mqd->cp_gfx_hqd_rptr_addr_hi = 3605 upper_32_bits(wb_gpu_addr) & 0xffff; 3606 3607 /* set up rb_wptr_poll addr */ 3608 wb_gpu_addr = prop->wptr_gpu_addr; 3609 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3610 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3611 3612 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3613 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 3614 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); 3615 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3616 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3617 #ifdef __BIG_ENDIAN 3618 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3619 #endif 3620 mqd->cp_gfx_hqd_cntl = tmp; 3621 3622 /* set up cp_doorbell_control */ 3623 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); 3624 if (prop->use_doorbell) { 3625 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3626 DOORBELL_OFFSET, prop->doorbell_index); 3627 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3628 DOORBELL_EN, 1); 3629 } else 3630 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3631 DOORBELL_EN, 0); 3632 mqd->cp_rb_doorbell_control = tmp; 3633 3634 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3635 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); 3636 3637 /* active the queue */ 3638 mqd->cp_gfx_hqd_active = 1; 3639 3640 return 0; 3641 } 3642 3643 #ifdef BRING_UP_DEBUG 3644 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3645 { 3646 struct amdgpu_device *adev = ring->adev; 3647 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3648 3649 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3650 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3651 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3652 3653 /* set GFX_MQD_BASE */ 3654 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3655 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3656 3657 /* set GFX_MQD_CONTROL */ 3658 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3659 3660 /* set GFX_HQD_VMID to 0 */ 3661 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3662 3663 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY, 3664 mqd->cp_gfx_hqd_queue_priority); 3665 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3666 3667 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3668 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3669 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3670 3671 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3672 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3673 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3674 3675 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3676 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3677 3678 /* set RB_WPTR_POLL_ADDR */ 3679 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3680 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3681 3682 /* set RB_DOORBELL_CONTROL */ 3683 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3684 3685 /* active the queue */ 3686 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3687 3688 return 0; 3689 } 3690 #endif 3691 3692 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) 3693 { 3694 struct amdgpu_device *adev = ring->adev; 3695 struct v11_gfx_mqd *mqd = ring->mqd_ptr; 3696 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3697 3698 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3699 memset((void *)mqd, 0, sizeof(*mqd)); 3700 mutex_lock(&adev->srbm_mutex); 3701 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3702 amdgpu_ring_init_mqd(ring); 3703 #ifdef BRING_UP_DEBUG 3704 gfx_v11_0_gfx_queue_init_register(ring); 3705 #endif 3706 soc21_grbm_select(adev, 0, 0, 0, 0); 3707 mutex_unlock(&adev->srbm_mutex); 3708 if (adev->gfx.me.mqd_backup[mqd_idx]) 3709 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3710 } else if (amdgpu_in_reset(adev)) { 3711 /* reset mqd with the backup copy */ 3712 if (adev->gfx.me.mqd_backup[mqd_idx]) 3713 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3714 /* reset the ring */ 3715 ring->wptr = 0; 3716 *ring->wptr_cpu_addr = 0; 3717 amdgpu_ring_clear_ring(ring); 3718 #ifdef BRING_UP_DEBUG 3719 mutex_lock(&adev->srbm_mutex); 3720 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3721 gfx_v11_0_gfx_queue_init_register(ring); 3722 soc21_grbm_select(adev, 0, 0, 0, 0); 3723 mutex_unlock(&adev->srbm_mutex); 3724 #endif 3725 } else { 3726 amdgpu_ring_clear_ring(ring); 3727 } 3728 3729 return 0; 3730 } 3731 3732 #ifndef BRING_UP_DEBUG 3733 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev) 3734 { 3735 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3736 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3737 int r, i; 3738 3739 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3740 return -EINVAL; 3741 3742 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3743 adev->gfx.num_gfx_rings); 3744 if (r) { 3745 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3746 return r; 3747 } 3748 3749 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3750 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3751 3752 return amdgpu_ring_test_helper(kiq_ring); 3753 } 3754 #endif 3755 3756 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3757 { 3758 int r, i; 3759 struct amdgpu_ring *ring; 3760 3761 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3762 ring = &adev->gfx.gfx_ring[i]; 3763 3764 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3765 if (unlikely(r != 0)) 3766 goto done; 3767 3768 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3769 if (!r) { 3770 r = gfx_v11_0_gfx_init_queue(ring); 3771 amdgpu_bo_kunmap(ring->mqd_obj); 3772 ring->mqd_ptr = NULL; 3773 } 3774 amdgpu_bo_unreserve(ring->mqd_obj); 3775 if (r) 3776 goto done; 3777 } 3778 #ifndef BRING_UP_DEBUG 3779 r = gfx_v11_0_kiq_enable_kgq(adev); 3780 if (r) 3781 goto done; 3782 #endif 3783 r = gfx_v11_0_cp_gfx_start(adev); 3784 if (r) 3785 goto done; 3786 3787 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3788 ring = &adev->gfx.gfx_ring[i]; 3789 ring->sched.ready = true; 3790 } 3791 done: 3792 return r; 3793 } 3794 3795 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3796 struct amdgpu_mqd_prop *prop) 3797 { 3798 struct v11_compute_mqd *mqd = m; 3799 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3800 uint32_t tmp; 3801 3802 mqd->header = 0xC0310800; 3803 mqd->compute_pipelinestat_enable = 0x00000001; 3804 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3805 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3806 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3807 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3808 mqd->compute_misc_reserved = 0x00000007; 3809 3810 eop_base_addr = prop->eop_gpu_addr >> 8; 3811 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3812 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3813 3814 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3815 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 3816 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3817 (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1)); 3818 3819 mqd->cp_hqd_eop_control = tmp; 3820 3821 /* enable doorbell? */ 3822 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3823 3824 if (prop->use_doorbell) { 3825 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3826 DOORBELL_OFFSET, prop->doorbell_index); 3827 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3828 DOORBELL_EN, 1); 3829 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3830 DOORBELL_SOURCE, 0); 3831 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3832 DOORBELL_HIT, 0); 3833 } else { 3834 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3835 DOORBELL_EN, 0); 3836 } 3837 3838 mqd->cp_hqd_pq_doorbell_control = tmp; 3839 3840 /* disable the queue if it's active */ 3841 mqd->cp_hqd_dequeue_request = 0; 3842 mqd->cp_hqd_pq_rptr = 0; 3843 mqd->cp_hqd_pq_wptr_lo = 0; 3844 mqd->cp_hqd_pq_wptr_hi = 0; 3845 3846 /* set the pointer to the MQD */ 3847 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 3848 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 3849 3850 /* set MQD vmid to 0 */ 3851 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 3852 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3853 mqd->cp_mqd_control = tmp; 3854 3855 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3856 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 3857 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3858 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3859 3860 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3861 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 3862 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3863 (order_base_2(prop->queue_size / 4) - 1)); 3864 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3865 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3866 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3867 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3868 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3869 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3870 mqd->cp_hqd_pq_control = tmp; 3871 3872 /* set the wb address whether it's enabled or not */ 3873 wb_gpu_addr = prop->rptr_gpu_addr; 3874 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3875 mqd->cp_hqd_pq_rptr_report_addr_hi = 3876 upper_32_bits(wb_gpu_addr) & 0xffff; 3877 3878 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3879 wb_gpu_addr = prop->wptr_gpu_addr; 3880 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3881 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3882 3883 tmp = 0; 3884 /* enable the doorbell if requested */ 3885 if (prop->use_doorbell) { 3886 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 3887 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3888 DOORBELL_OFFSET, prop->doorbell_index); 3889 3890 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3891 DOORBELL_EN, 1); 3892 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3893 DOORBELL_SOURCE, 0); 3894 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3895 DOORBELL_HIT, 0); 3896 } 3897 3898 mqd->cp_hqd_pq_doorbell_control = tmp; 3899 3900 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3901 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 3902 3903 /* set the vmid for the queue */ 3904 mqd->cp_hqd_vmid = 0; 3905 3906 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 3907 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); 3908 mqd->cp_hqd_persistent_state = tmp; 3909 3910 /* set MIN_IB_AVAIL_SIZE */ 3911 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 3912 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3913 mqd->cp_hqd_ib_control = tmp; 3914 3915 /* set static priority for a compute queue/ring */ 3916 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 3917 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 3918 3919 mqd->cp_hqd_active = prop->hqd_active; 3920 3921 return 0; 3922 } 3923 3924 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) 3925 { 3926 struct amdgpu_device *adev = ring->adev; 3927 struct v11_compute_mqd *mqd = ring->mqd_ptr; 3928 int j; 3929 3930 /* inactivate the queue */ 3931 if (amdgpu_sriov_vf(adev)) 3932 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 3933 3934 /* disable wptr polling */ 3935 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3936 3937 /* write the EOP addr */ 3938 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, 3939 mqd->cp_hqd_eop_base_addr_lo); 3940 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, 3941 mqd->cp_hqd_eop_base_addr_hi); 3942 3943 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3944 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, 3945 mqd->cp_hqd_eop_control); 3946 3947 /* enable doorbell? */ 3948 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 3949 mqd->cp_hqd_pq_doorbell_control); 3950 3951 /* disable the queue if it's active */ 3952 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 3953 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 3954 for (j = 0; j < adev->usec_timeout; j++) { 3955 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 3956 break; 3957 udelay(1); 3958 } 3959 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 3960 mqd->cp_hqd_dequeue_request); 3961 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 3962 mqd->cp_hqd_pq_rptr); 3963 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 3964 mqd->cp_hqd_pq_wptr_lo); 3965 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 3966 mqd->cp_hqd_pq_wptr_hi); 3967 } 3968 3969 /* set the pointer to the MQD */ 3970 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, 3971 mqd->cp_mqd_base_addr_lo); 3972 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, 3973 mqd->cp_mqd_base_addr_hi); 3974 3975 /* set MQD vmid to 0 */ 3976 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 3977 mqd->cp_mqd_control); 3978 3979 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3980 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, 3981 mqd->cp_hqd_pq_base_lo); 3982 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, 3983 mqd->cp_hqd_pq_base_hi); 3984 3985 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3986 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, 3987 mqd->cp_hqd_pq_control); 3988 3989 /* set the wb address whether it's enabled or not */ 3990 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 3991 mqd->cp_hqd_pq_rptr_report_addr_lo); 3992 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3993 mqd->cp_hqd_pq_rptr_report_addr_hi); 3994 3995 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3996 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 3997 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3998 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3999 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4000 4001 /* enable the doorbell if requested */ 4002 if (ring->use_doorbell) { 4003 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, 4004 (adev->doorbell_index.kiq * 2) << 2); 4005 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, 4006 (adev->doorbell_index.userqueue_end * 2) << 2); 4007 } 4008 4009 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 4010 mqd->cp_hqd_pq_doorbell_control); 4011 4012 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4013 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 4014 mqd->cp_hqd_pq_wptr_lo); 4015 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 4016 mqd->cp_hqd_pq_wptr_hi); 4017 4018 /* set the vmid for the queue */ 4019 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); 4020 4021 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, 4022 mqd->cp_hqd_persistent_state); 4023 4024 /* activate the queue */ 4025 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 4026 mqd->cp_hqd_active); 4027 4028 if (ring->use_doorbell) 4029 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4030 4031 return 0; 4032 } 4033 4034 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) 4035 { 4036 struct amdgpu_device *adev = ring->adev; 4037 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4038 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 4039 4040 gfx_v11_0_kiq_setting(ring); 4041 4042 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4043 /* reset MQD to a clean status */ 4044 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4045 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4046 4047 /* reset ring buffer */ 4048 ring->wptr = 0; 4049 amdgpu_ring_clear_ring(ring); 4050 4051 mutex_lock(&adev->srbm_mutex); 4052 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4053 gfx_v11_0_kiq_init_register(ring); 4054 soc21_grbm_select(adev, 0, 0, 0, 0); 4055 mutex_unlock(&adev->srbm_mutex); 4056 } else { 4057 memset((void *)mqd, 0, sizeof(*mqd)); 4058 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 4059 amdgpu_ring_clear_ring(ring); 4060 mutex_lock(&adev->srbm_mutex); 4061 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4062 amdgpu_ring_init_mqd(ring); 4063 gfx_v11_0_kiq_init_register(ring); 4064 soc21_grbm_select(adev, 0, 0, 0, 0); 4065 mutex_unlock(&adev->srbm_mutex); 4066 4067 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4068 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4069 } 4070 4071 return 0; 4072 } 4073 4074 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) 4075 { 4076 struct amdgpu_device *adev = ring->adev; 4077 struct v11_compute_mqd *mqd = ring->mqd_ptr; 4078 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4079 4080 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 4081 memset((void *)mqd, 0, sizeof(*mqd)); 4082 mutex_lock(&adev->srbm_mutex); 4083 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4084 amdgpu_ring_init_mqd(ring); 4085 soc21_grbm_select(adev, 0, 0, 0, 0); 4086 mutex_unlock(&adev->srbm_mutex); 4087 4088 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4089 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 4090 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 4091 /* reset MQD to a clean status */ 4092 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4093 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 4094 4095 /* reset ring buffer */ 4096 ring->wptr = 0; 4097 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4098 amdgpu_ring_clear_ring(ring); 4099 } else { 4100 amdgpu_ring_clear_ring(ring); 4101 } 4102 4103 return 0; 4104 } 4105 4106 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev) 4107 { 4108 struct amdgpu_ring *ring; 4109 int r; 4110 4111 ring = &adev->gfx.kiq.ring; 4112 4113 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4114 if (unlikely(r != 0)) 4115 return r; 4116 4117 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4118 if (unlikely(r != 0)) { 4119 amdgpu_bo_unreserve(ring->mqd_obj); 4120 return r; 4121 } 4122 4123 gfx_v11_0_kiq_init_queue(ring); 4124 amdgpu_bo_kunmap(ring->mqd_obj); 4125 ring->mqd_ptr = NULL; 4126 amdgpu_bo_unreserve(ring->mqd_obj); 4127 ring->sched.ready = true; 4128 return 0; 4129 } 4130 4131 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) 4132 { 4133 struct amdgpu_ring *ring = NULL; 4134 int r = 0, i; 4135 4136 if (!amdgpu_async_gfx_ring) 4137 gfx_v11_0_cp_compute_enable(adev, true); 4138 4139 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4140 ring = &adev->gfx.compute_ring[i]; 4141 4142 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4143 if (unlikely(r != 0)) 4144 goto done; 4145 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 4146 if (!r) { 4147 r = gfx_v11_0_kcq_init_queue(ring); 4148 amdgpu_bo_kunmap(ring->mqd_obj); 4149 ring->mqd_ptr = NULL; 4150 } 4151 amdgpu_bo_unreserve(ring->mqd_obj); 4152 if (r) 4153 goto done; 4154 } 4155 4156 r = amdgpu_gfx_enable_kcq(adev); 4157 done: 4158 return r; 4159 } 4160 4161 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) 4162 { 4163 int r, i; 4164 struct amdgpu_ring *ring; 4165 4166 if (!(adev->flags & AMD_IS_APU)) 4167 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4168 4169 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4170 /* legacy firmware loading */ 4171 r = gfx_v11_0_cp_gfx_load_microcode(adev); 4172 if (r) 4173 return r; 4174 4175 if (adev->gfx.rs64_enable) 4176 r = gfx_v11_0_cp_compute_load_microcode_rs64(adev); 4177 else 4178 r = gfx_v11_0_cp_compute_load_microcode(adev); 4179 if (r) 4180 return r; 4181 } 4182 4183 gfx_v11_0_cp_set_doorbell_range(adev); 4184 4185 if (amdgpu_async_gfx_ring) { 4186 gfx_v11_0_cp_compute_enable(adev, true); 4187 gfx_v11_0_cp_gfx_enable(adev, true); 4188 } 4189 4190 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4191 r = amdgpu_mes_kiq_hw_init(adev); 4192 else 4193 r = gfx_v11_0_kiq_resume(adev); 4194 if (r) 4195 return r; 4196 4197 r = gfx_v11_0_kcq_resume(adev); 4198 if (r) 4199 return r; 4200 4201 if (!amdgpu_async_gfx_ring) { 4202 r = gfx_v11_0_cp_gfx_resume(adev); 4203 if (r) 4204 return r; 4205 } else { 4206 r = gfx_v11_0_cp_async_gfx_ring_resume(adev); 4207 if (r) 4208 return r; 4209 } 4210 4211 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4212 ring = &adev->gfx.gfx_ring[i]; 4213 r = amdgpu_ring_test_helper(ring); 4214 if (r) 4215 return r; 4216 } 4217 4218 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4219 ring = &adev->gfx.compute_ring[i]; 4220 r = amdgpu_ring_test_helper(ring); 4221 if (r) 4222 return r; 4223 } 4224 4225 return 0; 4226 } 4227 4228 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable) 4229 { 4230 gfx_v11_0_cp_gfx_enable(adev, enable); 4231 gfx_v11_0_cp_compute_enable(adev, enable); 4232 } 4233 4234 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) 4235 { 4236 int r; 4237 bool value; 4238 4239 r = adev->gfxhub.funcs->gart_enable(adev); 4240 if (r) 4241 return r; 4242 4243 adev->hdp.funcs->flush_hdp(adev, NULL); 4244 4245 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4246 false : true; 4247 4248 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4249 amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 4250 4251 return 0; 4252 } 4253 4254 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev) 4255 { 4256 u32 tmp; 4257 4258 /* select RS64 */ 4259 if (adev->gfx.rs64_enable) { 4260 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); 4261 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1); 4262 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); 4263 4264 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); 4265 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1); 4266 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); 4267 } 4268 4269 if (amdgpu_emu_mode == 1) 4270 msleep(100); 4271 } 4272 4273 static int get_gb_addr_config(struct amdgpu_device * adev) 4274 { 4275 u32 gb_addr_config; 4276 4277 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 4278 if (gb_addr_config == 0) 4279 return -EINVAL; 4280 4281 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4282 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4283 4284 adev->gfx.config.gb_addr_config = gb_addr_config; 4285 4286 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4287 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4288 GB_ADDR_CONFIG, NUM_PIPES); 4289 4290 adev->gfx.config.max_tile_pipes = 4291 adev->gfx.config.gb_addr_config_fields.num_pipes; 4292 4293 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4294 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4295 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4296 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4297 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4298 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4299 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4300 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4301 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4302 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4303 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4304 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4305 4306 return 0; 4307 } 4308 4309 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) 4310 { 4311 uint32_t data; 4312 4313 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); 4314 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 4315 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); 4316 4317 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); 4318 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 4319 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); 4320 } 4321 4322 static int gfx_v11_0_hw_init(void *handle) 4323 { 4324 int r; 4325 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4326 4327 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4328 if (adev->gfx.imu.funcs) { 4329 /* RLC autoload sequence 1: Program rlc ram */ 4330 if (adev->gfx.imu.funcs->program_rlc_ram) 4331 adev->gfx.imu.funcs->program_rlc_ram(adev); 4332 } 4333 /* rlc autoload firmware */ 4334 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev); 4335 if (r) 4336 return r; 4337 } else { 4338 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4339 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { 4340 if (adev->gfx.imu.funcs->load_microcode) 4341 adev->gfx.imu.funcs->load_microcode(adev); 4342 if (adev->gfx.imu.funcs->setup_imu) 4343 adev->gfx.imu.funcs->setup_imu(adev); 4344 if (adev->gfx.imu.funcs->start_imu) 4345 adev->gfx.imu.funcs->start_imu(adev); 4346 } 4347 4348 /* disable gpa mode in backdoor loading */ 4349 gfx_v11_0_disable_gpa_mode(adev); 4350 } 4351 } 4352 4353 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 4354 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4355 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev); 4356 if (r) { 4357 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 4358 return r; 4359 } 4360 } 4361 4362 adev->gfx.is_poweron = true; 4363 4364 if(get_gb_addr_config(adev)) 4365 DRM_WARN("Invalid gb_addr_config !\n"); 4366 4367 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4368 adev->gfx.rs64_enable) 4369 gfx_v11_0_config_gfx_rs64(adev); 4370 4371 r = gfx_v11_0_gfxhub_enable(adev); 4372 if (r) 4373 return r; 4374 4375 if (!amdgpu_emu_mode) 4376 gfx_v11_0_init_golden_registers(adev); 4377 4378 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 4379 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 4380 /** 4381 * For gfx 11, rlc firmware loading relies on smu firmware is 4382 * loaded firstly, so in direct type, it has to load smc ucode 4383 * here before rlc. 4384 */ 4385 if (!(adev->flags & AMD_IS_APU)) { 4386 r = amdgpu_pm_load_smu_firmware(adev, NULL); 4387 if (r) 4388 return r; 4389 } 4390 } 4391 4392 gfx_v11_0_constants_init(adev); 4393 4394 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4395 gfx_v11_0_select_cp_fw_arch(adev); 4396 4397 if (adev->nbio.funcs->gc_doorbell_init) 4398 adev->nbio.funcs->gc_doorbell_init(adev); 4399 4400 r = gfx_v11_0_rlc_resume(adev); 4401 if (r) 4402 return r; 4403 4404 /* 4405 * init golden registers and rlc resume may override some registers, 4406 * reconfig them here 4407 */ 4408 gfx_v11_0_tcp_harvest(adev); 4409 4410 r = gfx_v11_0_cp_resume(adev); 4411 if (r) 4412 return r; 4413 4414 return r; 4415 } 4416 4417 #ifndef BRING_UP_DEBUG 4418 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev) 4419 { 4420 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4421 struct amdgpu_ring *kiq_ring = &kiq->ring; 4422 int i, r = 0; 4423 4424 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4425 return -EINVAL; 4426 4427 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 4428 adev->gfx.num_gfx_rings)) 4429 return -ENOMEM; 4430 4431 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4432 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 4433 PREEMPT_QUEUES, 0, 0); 4434 4435 if (adev->gfx.kiq.ring.sched.ready) 4436 r = amdgpu_ring_test_helper(kiq_ring); 4437 4438 return r; 4439 } 4440 #endif 4441 4442 static int gfx_v11_0_hw_fini(void *handle) 4443 { 4444 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4445 int r; 4446 4447 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 4448 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4449 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4450 4451 if (!adev->no_hw_access) { 4452 #ifndef BRING_UP_DEBUG 4453 if (amdgpu_async_gfx_ring) { 4454 r = gfx_v11_0_kiq_disable_kgq(adev); 4455 if (r) 4456 DRM_ERROR("KGQ disable failed\n"); 4457 } 4458 #endif 4459 if (amdgpu_gfx_disable_kcq(adev)) 4460 DRM_ERROR("KCQ disable failed\n"); 4461 4462 amdgpu_mes_kiq_hw_fini(adev); 4463 } 4464 4465 if (amdgpu_sriov_vf(adev)) 4466 /* Remove the steps disabling CPG and clearing KIQ position, 4467 * so that CP could perform IDLE-SAVE during switch. Those 4468 * steps are necessary to avoid a DMAR error in gfx9 but it is 4469 * not reproduced on gfx11. 4470 */ 4471 return 0; 4472 4473 gfx_v11_0_cp_enable(adev, false); 4474 gfx_v11_0_enable_gui_idle_interrupt(adev, false); 4475 4476 adev->gfxhub.funcs->gart_disable(adev); 4477 4478 adev->gfx.is_poweron = false; 4479 4480 return 0; 4481 } 4482 4483 static int gfx_v11_0_suspend(void *handle) 4484 { 4485 return gfx_v11_0_hw_fini(handle); 4486 } 4487 4488 static int gfx_v11_0_resume(void *handle) 4489 { 4490 return gfx_v11_0_hw_init(handle); 4491 } 4492 4493 static bool gfx_v11_0_is_idle(void *handle) 4494 { 4495 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4496 4497 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), 4498 GRBM_STATUS, GUI_ACTIVE)) 4499 return false; 4500 else 4501 return true; 4502 } 4503 4504 static int gfx_v11_0_wait_for_idle(void *handle) 4505 { 4506 unsigned i; 4507 u32 tmp; 4508 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4509 4510 for (i = 0; i < adev->usec_timeout; i++) { 4511 /* read MC_STATUS */ 4512 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & 4513 GRBM_STATUS__GUI_ACTIVE_MASK; 4514 4515 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 4516 return 0; 4517 udelay(1); 4518 } 4519 return -ETIMEDOUT; 4520 } 4521 4522 static int gfx_v11_0_soft_reset(void *handle) 4523 { 4524 u32 grbm_soft_reset = 0; 4525 u32 tmp; 4526 int i, j, k; 4527 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4528 4529 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4530 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); 4531 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); 4532 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); 4533 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); 4534 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4535 4536 gfx_v11_0_set_safe_mode(adev); 4537 4538 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4539 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4540 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4541 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4542 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4543 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4544 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4545 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4546 4547 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 4548 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 4549 } 4550 } 4551 } 4552 for (i = 0; i < adev->gfx.me.num_me; ++i) { 4553 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4554 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4555 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); 4556 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i); 4557 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j); 4558 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k); 4559 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); 4560 4561 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); 4562 } 4563 } 4564 } 4565 4566 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); 4567 4568 // Read CP_VMID_RESET register three times. 4569 // to get sufficient time for GFX_HQD_ACTIVE reach 0 4570 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4571 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4572 RREG32_SOC15(GC, 0, regCP_VMID_RESET); 4573 4574 for (i = 0; i < adev->usec_timeout; i++) { 4575 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && 4576 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) 4577 break; 4578 udelay(1); 4579 } 4580 if (i >= adev->usec_timeout) { 4581 printk("Failed to wait all pipes clean\n"); 4582 return -EINVAL; 4583 } 4584 4585 /********** trigger soft reset ***********/ 4586 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4587 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4588 SOFT_RESET_CP, 1); 4589 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4590 SOFT_RESET_GFX, 1); 4591 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4592 SOFT_RESET_CPF, 1); 4593 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4594 SOFT_RESET_CPC, 1); 4595 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4596 SOFT_RESET_CPG, 1); 4597 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4598 /********** exit soft reset ***********/ 4599 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 4600 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4601 SOFT_RESET_CP, 0); 4602 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4603 SOFT_RESET_GFX, 0); 4604 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4605 SOFT_RESET_CPF, 0); 4606 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4607 SOFT_RESET_CPC, 0); 4608 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 4609 SOFT_RESET_CPG, 0); 4610 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); 4611 4612 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); 4613 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); 4614 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); 4615 4616 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); 4617 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); 4618 4619 for (i = 0; i < adev->usec_timeout; i++) { 4620 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) 4621 break; 4622 udelay(1); 4623 } 4624 if (i >= adev->usec_timeout) { 4625 printk("Failed to wait CP_VMID_RESET to 0\n"); 4626 return -EINVAL; 4627 } 4628 4629 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4630 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4631 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4632 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4633 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4634 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); 4635 4636 gfx_v11_0_unset_safe_mode(adev); 4637 4638 return gfx_v11_0_cp_resume(adev); 4639 } 4640 4641 static bool gfx_v11_0_check_soft_reset(void *handle) 4642 { 4643 int i, r; 4644 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4645 struct amdgpu_ring *ring; 4646 long tmo = msecs_to_jiffies(1000); 4647 4648 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4649 ring = &adev->gfx.gfx_ring[i]; 4650 r = amdgpu_ring_test_ib(ring, tmo); 4651 if (r) 4652 return true; 4653 } 4654 4655 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4656 ring = &adev->gfx.compute_ring[i]; 4657 r = amdgpu_ring_test_ib(ring, tmo); 4658 if (r) 4659 return true; 4660 } 4661 4662 return false; 4663 } 4664 4665 static int gfx_v11_0_post_soft_reset(void *handle) 4666 { 4667 /** 4668 * GFX soft reset will impact MES, need resume MES when do GFX soft reset 4669 */ 4670 return amdgpu_mes_resume((struct amdgpu_device *)handle); 4671 } 4672 4673 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4674 { 4675 uint64_t clock; 4676 uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 4677 4678 amdgpu_gfx_off_ctrl(adev, false); 4679 mutex_lock(&adev->gfx.gpu_clock_mutex); 4680 if (amdgpu_sriov_vf(adev)) { 4681 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4682 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4683 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); 4684 if (clock_counter_hi_pre != clock_counter_hi_after) 4685 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); 4686 } else { 4687 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4688 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4689 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 4690 if (clock_counter_hi_pre != clock_counter_hi_after) 4691 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 4692 } 4693 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 4694 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4695 amdgpu_gfx_off_ctrl(adev, true); 4696 return clock; 4697 } 4698 4699 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4700 uint32_t vmid, 4701 uint32_t gds_base, uint32_t gds_size, 4702 uint32_t gws_base, uint32_t gws_size, 4703 uint32_t oa_base, uint32_t oa_size) 4704 { 4705 struct amdgpu_device *adev = ring->adev; 4706 4707 /* GDS Base */ 4708 gfx_v11_0_write_data_to_reg(ring, 0, false, 4709 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 4710 gds_base); 4711 4712 /* GDS Size */ 4713 gfx_v11_0_write_data_to_reg(ring, 0, false, 4714 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 4715 gds_size); 4716 4717 /* GWS */ 4718 gfx_v11_0_write_data_to_reg(ring, 0, false, 4719 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 4720 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4721 4722 /* OA */ 4723 gfx_v11_0_write_data_to_reg(ring, 0, false, 4724 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 4725 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4726 } 4727 4728 static int gfx_v11_0_early_init(void *handle) 4729 { 4730 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4731 4732 adev->gfx.funcs = &gfx_v11_0_gfx_funcs; 4733 4734 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS; 4735 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4736 AMDGPU_MAX_COMPUTE_RINGS); 4737 4738 gfx_v11_0_set_kiq_pm4_funcs(adev); 4739 gfx_v11_0_set_ring_funcs(adev); 4740 gfx_v11_0_set_irq_funcs(adev); 4741 gfx_v11_0_set_gds_init(adev); 4742 gfx_v11_0_set_rlc_funcs(adev); 4743 gfx_v11_0_set_mqd_funcs(adev); 4744 gfx_v11_0_set_imu_funcs(adev); 4745 4746 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); 4747 4748 return gfx_v11_0_init_microcode(adev); 4749 } 4750 4751 static int gfx_v11_0_ras_late_init(void *handle) 4752 { 4753 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4754 struct ras_common_if *gfx_common_if; 4755 int ret; 4756 4757 gfx_common_if = kzalloc(sizeof(struct ras_common_if), GFP_KERNEL); 4758 if (!gfx_common_if) 4759 return -ENOMEM; 4760 4761 gfx_common_if->block = AMDGPU_RAS_BLOCK__GFX; 4762 4763 ret = amdgpu_ras_feature_enable(adev, gfx_common_if, true); 4764 if (ret) 4765 dev_warn(adev->dev, "Failed to enable gfx11 ras feature\n"); 4766 4767 kfree(gfx_common_if); 4768 return 0; 4769 } 4770 4771 static int gfx_v11_0_late_init(void *handle) 4772 { 4773 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4774 int r; 4775 4776 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4777 if (r) 4778 return r; 4779 4780 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4781 if (r) 4782 return r; 4783 4784 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) { 4785 r = gfx_v11_0_ras_late_init(handle); 4786 if (r) 4787 return r; 4788 } 4789 4790 return 0; 4791 } 4792 4793 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev) 4794 { 4795 uint32_t rlc_cntl; 4796 4797 /* if RLC is not enabled, do nothing */ 4798 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); 4799 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4800 } 4801 4802 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev) 4803 { 4804 uint32_t data; 4805 unsigned i; 4806 4807 data = RLC_SAFE_MODE__CMD_MASK; 4808 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4809 4810 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); 4811 4812 /* wait for RLC_SAFE_MODE */ 4813 for (i = 0; i < adev->usec_timeout; i++) { 4814 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), 4815 RLC_SAFE_MODE, CMD)) 4816 break; 4817 udelay(1); 4818 } 4819 } 4820 4821 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev) 4822 { 4823 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 4824 } 4825 4826 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev, 4827 bool enable) 4828 { 4829 uint32_t def, data; 4830 4831 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 4832 return; 4833 4834 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4835 4836 if (enable) 4837 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4838 else 4839 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 4840 4841 if (def != data) 4842 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4843 } 4844 4845 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev, 4846 bool enable) 4847 { 4848 uint32_t def, data; 4849 4850 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 4851 return; 4852 4853 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4854 4855 if (enable) 4856 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4857 else 4858 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 4859 4860 if (def != data) 4861 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4862 } 4863 4864 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev, 4865 bool enable) 4866 { 4867 uint32_t def, data; 4868 4869 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 4870 return; 4871 4872 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4873 4874 if (enable) 4875 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4876 else 4877 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK; 4878 4879 if (def != data) 4880 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4881 } 4882 4883 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4884 bool enable) 4885 { 4886 uint32_t data, def; 4887 4888 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 4889 return; 4890 4891 /* It is disabled by HW by default */ 4892 if (enable) { 4893 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4894 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4895 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4896 4897 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4898 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4899 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4900 4901 if (def != data) 4902 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4903 } 4904 } else { 4905 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 4906 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4907 4908 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4909 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4910 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 4911 4912 if (def != data) 4913 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4914 } 4915 } 4916 } 4917 4918 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4919 bool enable) 4920 { 4921 uint32_t def, data; 4922 4923 if (!(adev->cg_flags & 4924 (AMD_CG_SUPPORT_GFX_CGCG | 4925 AMD_CG_SUPPORT_GFX_CGLS | 4926 AMD_CG_SUPPORT_GFX_3D_CGCG | 4927 AMD_CG_SUPPORT_GFX_3D_CGLS))) 4928 return; 4929 4930 if (enable) { 4931 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 4932 4933 /* unset CGCG override */ 4934 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 4935 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4936 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4937 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4938 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 4939 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4940 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4941 4942 /* update CGCG override bits */ 4943 if (def != data) 4944 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); 4945 4946 /* enable cgcg FSM(0x0000363F) */ 4947 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 4948 4949 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 4950 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 4951 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4952 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4953 } 4954 4955 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 4956 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 4957 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4958 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4959 } 4960 4961 if (def != data) 4962 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 4963 4964 /* Program RLC_CGCG_CGLS_CTRL_3D */ 4965 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 4966 4967 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 4968 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK; 4969 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4970 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4971 } 4972 4973 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 4974 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK; 4975 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4976 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4977 } 4978 4979 if (def != data) 4980 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 4981 4982 /* set IDLE_POLL_COUNT(0x00900100) */ 4983 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); 4984 4985 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK); 4986 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4987 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4988 4989 if (def != data) 4990 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); 4991 4992 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); 4993 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 4994 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 4995 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 4996 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 4997 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); 4998 4999 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5000 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5001 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5002 5003 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5004 if (adev->sdma.num_instances > 1) { 5005 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5006 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); 5007 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5008 } 5009 } else { 5010 /* Program RLC_CGCG_CGLS_CTRL */ 5011 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5012 5013 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 5014 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5015 5016 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 5017 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5018 5019 if (def != data) 5020 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); 5021 5022 /* Program RLC_CGCG_CGLS_CTRL_3D */ 5023 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5024 5025 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 5026 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 5027 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 5028 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 5029 5030 if (def != data) 5031 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); 5032 5033 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); 5034 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5035 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); 5036 5037 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ 5038 if (adev->sdma.num_instances > 1) { 5039 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); 5040 data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; 5041 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); 5042 } 5043 } 5044 } 5045 5046 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5047 bool enable) 5048 { 5049 amdgpu_gfx_rlc_enter_safe_mode(adev); 5050 5051 gfx_v11_0_update_coarse_grain_clock_gating(adev, enable); 5052 5053 gfx_v11_0_update_medium_grain_clock_gating(adev, enable); 5054 5055 gfx_v11_0_update_repeater_fgcg(adev, enable); 5056 5057 gfx_v11_0_update_sram_fgcg(adev, enable); 5058 5059 gfx_v11_0_update_perf_clk(adev, enable); 5060 5061 if (adev->cg_flags & 5062 (AMD_CG_SUPPORT_GFX_MGCG | 5063 AMD_CG_SUPPORT_GFX_CGLS | 5064 AMD_CG_SUPPORT_GFX_CGCG | 5065 AMD_CG_SUPPORT_GFX_3D_CGCG | 5066 AMD_CG_SUPPORT_GFX_3D_CGLS)) 5067 gfx_v11_0_enable_gui_idle_interrupt(adev, enable); 5068 5069 amdgpu_gfx_rlc_exit_safe_mode(adev); 5070 5071 return 0; 5072 } 5073 5074 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 5075 { 5076 u32 reg, data; 5077 5078 amdgpu_gfx_off_ctrl(adev, false); 5079 5080 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 5081 if (amdgpu_sriov_is_pp_one_vf(adev)) 5082 data = RREG32_NO_KIQ(reg); 5083 else 5084 data = RREG32(reg); 5085 5086 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5087 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5088 5089 if (amdgpu_sriov_is_pp_one_vf(adev)) 5090 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 5091 else 5092 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 5093 5094 amdgpu_gfx_off_ctrl(adev, true); 5095 } 5096 5097 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = { 5098 .is_rlc_enabled = gfx_v11_0_is_rlc_enabled, 5099 .set_safe_mode = gfx_v11_0_set_safe_mode, 5100 .unset_safe_mode = gfx_v11_0_unset_safe_mode, 5101 .init = gfx_v11_0_rlc_init, 5102 .get_csb_size = gfx_v11_0_get_csb_size, 5103 .get_csb_buffer = gfx_v11_0_get_csb_buffer, 5104 .resume = gfx_v11_0_rlc_resume, 5105 .stop = gfx_v11_0_rlc_stop, 5106 .reset = gfx_v11_0_rlc_reset, 5107 .start = gfx_v11_0_rlc_start, 5108 .update_spm_vmid = gfx_v11_0_update_spm_vmid, 5109 }; 5110 5111 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 5112 { 5113 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); 5114 5115 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 5116 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5117 else 5118 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 5119 5120 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); 5121 5122 // Program RLC_PG_DELAY3 for CGPG hysteresis 5123 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 5124 switch (adev->ip_versions[GC_HWIP][0]) { 5125 case IP_VERSION(11, 0, 1): 5126 case IP_VERSION(11, 0, 4): 5127 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); 5128 break; 5129 default: 5130 break; 5131 } 5132 } 5133 } 5134 5135 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable) 5136 { 5137 amdgpu_gfx_rlc_enter_safe_mode(adev); 5138 5139 gfx_v11_cntl_power_gating(adev, enable); 5140 5141 amdgpu_gfx_rlc_exit_safe_mode(adev); 5142 } 5143 5144 static int gfx_v11_0_set_powergating_state(void *handle, 5145 enum amd_powergating_state state) 5146 { 5147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5148 bool enable = (state == AMD_PG_STATE_GATE); 5149 5150 if (amdgpu_sriov_vf(adev)) 5151 return 0; 5152 5153 switch (adev->ip_versions[GC_HWIP][0]) { 5154 case IP_VERSION(11, 0, 0): 5155 case IP_VERSION(11, 0, 2): 5156 case IP_VERSION(11, 0, 3): 5157 amdgpu_gfx_off_ctrl(adev, enable); 5158 break; 5159 case IP_VERSION(11, 0, 1): 5160 case IP_VERSION(11, 0, 4): 5161 gfx_v11_cntl_pg(adev, enable); 5162 amdgpu_gfx_off_ctrl(adev, enable); 5163 break; 5164 default: 5165 break; 5166 } 5167 5168 return 0; 5169 } 5170 5171 static int gfx_v11_0_set_clockgating_state(void *handle, 5172 enum amd_clockgating_state state) 5173 { 5174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5175 5176 if (amdgpu_sriov_vf(adev)) 5177 return 0; 5178 5179 switch (adev->ip_versions[GC_HWIP][0]) { 5180 case IP_VERSION(11, 0, 0): 5181 case IP_VERSION(11, 0, 1): 5182 case IP_VERSION(11, 0, 2): 5183 case IP_VERSION(11, 0, 3): 5184 case IP_VERSION(11, 0, 4): 5185 gfx_v11_0_update_gfx_clock_gating(adev, 5186 state == AMD_CG_STATE_GATE); 5187 break; 5188 default: 5189 break; 5190 } 5191 5192 return 0; 5193 } 5194 5195 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags) 5196 { 5197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5198 int data; 5199 5200 /* AMD_CG_SUPPORT_GFX_MGCG */ 5201 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); 5202 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5203 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5204 5205 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 5206 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 5207 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 5208 5209 /* AMD_CG_SUPPORT_GFX_FGCG */ 5210 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 5211 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 5212 5213 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 5214 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 5215 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 5216 5217 /* AMD_CG_SUPPORT_GFX_CGCG */ 5218 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); 5219 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5220 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5221 5222 /* AMD_CG_SUPPORT_GFX_CGLS */ 5223 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5224 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5225 5226 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5227 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); 5228 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5229 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5230 5231 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5232 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5233 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5234 } 5235 5236 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5237 { 5238 /* gfx11 is 32bit rptr*/ 5239 return *(uint32_t *)ring->rptr_cpu_addr; 5240 } 5241 5242 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5243 { 5244 struct amdgpu_device *adev = ring->adev; 5245 u64 wptr; 5246 5247 /* XXX check if swapping is necessary on BE */ 5248 if (ring->use_doorbell) { 5249 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5250 } else { 5251 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); 5252 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; 5253 } 5254 5255 return wptr; 5256 } 5257 5258 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5259 { 5260 struct amdgpu_device *adev = ring->adev; 5261 uint32_t *wptr_saved; 5262 uint32_t *is_queue_unmap; 5263 uint64_t aggregated_db_index; 5264 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 5265 uint64_t wptr_tmp; 5266 5267 if (ring->is_mes_queue) { 5268 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5269 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5270 sizeof(uint32_t)); 5271 aggregated_db_index = 5272 amdgpu_mes_get_aggregated_doorbell_index(adev, 5273 ring->hw_prio); 5274 5275 wptr_tmp = ring->wptr & ring->buf_mask; 5276 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5277 *wptr_saved = wptr_tmp; 5278 /* assume doorbell always being used by mes mapped queue */ 5279 if (*is_queue_unmap) { 5280 WDOORBELL64(aggregated_db_index, wptr_tmp); 5281 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5282 } else { 5283 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5284 5285 if (*is_queue_unmap) 5286 WDOORBELL64(aggregated_db_index, wptr_tmp); 5287 } 5288 } else { 5289 if (ring->use_doorbell) { 5290 /* XXX check if swapping is necessary on BE */ 5291 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5292 ring->wptr); 5293 WDOORBELL64(ring->doorbell_index, ring->wptr); 5294 } else { 5295 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, 5296 lower_32_bits(ring->wptr)); 5297 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, 5298 upper_32_bits(ring->wptr)); 5299 } 5300 } 5301 } 5302 5303 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5304 { 5305 /* gfx11 hardware is 32bit rptr */ 5306 return *(uint32_t *)ring->rptr_cpu_addr; 5307 } 5308 5309 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5310 { 5311 u64 wptr; 5312 5313 /* XXX check if swapping is necessary on BE */ 5314 if (ring->use_doorbell) 5315 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5316 else 5317 BUG(); 5318 return wptr; 5319 } 5320 5321 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5322 { 5323 struct amdgpu_device *adev = ring->adev; 5324 uint32_t *wptr_saved; 5325 uint32_t *is_queue_unmap; 5326 uint64_t aggregated_db_index; 5327 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 5328 uint64_t wptr_tmp; 5329 5330 if (ring->is_mes_queue) { 5331 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 5332 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 5333 sizeof(uint32_t)); 5334 aggregated_db_index = 5335 amdgpu_mes_get_aggregated_doorbell_index(adev, 5336 ring->hw_prio); 5337 5338 wptr_tmp = ring->wptr & ring->buf_mask; 5339 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 5340 *wptr_saved = wptr_tmp; 5341 /* assume doorbell always used by mes mapped queue */ 5342 if (*is_queue_unmap) { 5343 WDOORBELL64(aggregated_db_index, wptr_tmp); 5344 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5345 } else { 5346 WDOORBELL64(ring->doorbell_index, wptr_tmp); 5347 5348 if (*is_queue_unmap) 5349 WDOORBELL64(aggregated_db_index, wptr_tmp); 5350 } 5351 } else { 5352 /* XXX check if swapping is necessary on BE */ 5353 if (ring->use_doorbell) { 5354 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 5355 ring->wptr); 5356 WDOORBELL64(ring->doorbell_index, ring->wptr); 5357 } else { 5358 BUG(); /* only DOORBELL method supported on gfx11 now */ 5359 } 5360 } 5361 } 5362 5363 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5364 { 5365 struct amdgpu_device *adev = ring->adev; 5366 u32 ref_and_mask, reg_mem_engine; 5367 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5368 5369 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5370 switch (ring->me) { 5371 case 1: 5372 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5373 break; 5374 case 2: 5375 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5376 break; 5377 default: 5378 return; 5379 } 5380 reg_mem_engine = 0; 5381 } else { 5382 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5383 reg_mem_engine = 1; /* pfp */ 5384 } 5385 5386 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5387 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5388 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5389 ref_and_mask, ref_and_mask, 0x20); 5390 } 5391 5392 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5393 struct amdgpu_job *job, 5394 struct amdgpu_ib *ib, 5395 uint32_t flags) 5396 { 5397 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5398 u32 header, control = 0; 5399 5400 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); 5401 5402 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5403 5404 control |= ib->length_dw | (vmid << 24); 5405 5406 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5407 control |= INDIRECT_BUFFER_PRE_ENB(1); 5408 5409 if (flags & AMDGPU_IB_PREEMPTED) 5410 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5411 5412 if (vmid) 5413 gfx_v11_0_ring_emit_de_meta(ring, 5414 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5415 } 5416 5417 if (ring->is_mes_queue) 5418 /* inherit vmid from mqd */ 5419 control |= 0x400000; 5420 5421 amdgpu_ring_write(ring, header); 5422 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5423 amdgpu_ring_write(ring, 5424 #ifdef __BIG_ENDIAN 5425 (2 << 0) | 5426 #endif 5427 lower_32_bits(ib->gpu_addr)); 5428 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5429 amdgpu_ring_write(ring, control); 5430 } 5431 5432 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5433 struct amdgpu_job *job, 5434 struct amdgpu_ib *ib, 5435 uint32_t flags) 5436 { 5437 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5438 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5439 5440 if (ring->is_mes_queue) 5441 /* inherit vmid from mqd */ 5442 control |= 0x40000000; 5443 5444 /* Currently, there is a high possibility to get wave ID mismatch 5445 * between ME and GDS, leading to a hw deadlock, because ME generates 5446 * different wave IDs than the GDS expects. This situation happens 5447 * randomly when at least 5 compute pipes use GDS ordered append. 5448 * The wave IDs generated by ME are also wrong after suspend/resume. 5449 * Those are probably bugs somewhere else in the kernel driver. 5450 * 5451 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5452 * GDS to 0 for this ring (me/pipe). 5453 */ 5454 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5455 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5456 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 5457 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5458 } 5459 5460 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5461 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5462 amdgpu_ring_write(ring, 5463 #ifdef __BIG_ENDIAN 5464 (2 << 0) | 5465 #endif 5466 lower_32_bits(ib->gpu_addr)); 5467 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5468 amdgpu_ring_write(ring, control); 5469 } 5470 5471 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5472 u64 seq, unsigned flags) 5473 { 5474 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5475 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5476 5477 /* RELEASE_MEM - flush caches, send int */ 5478 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5479 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 5480 PACKET3_RELEASE_MEM_GCR_GL2_WB | 5481 PACKET3_RELEASE_MEM_GCR_GL2_INV | 5482 PACKET3_RELEASE_MEM_GCR_GL2_US | 5483 PACKET3_RELEASE_MEM_GCR_GL1_INV | 5484 PACKET3_RELEASE_MEM_GCR_GLV_INV | 5485 PACKET3_RELEASE_MEM_GCR_GLM_INV | 5486 PACKET3_RELEASE_MEM_GCR_GLM_WB | 5487 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 5488 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5489 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 5490 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 5491 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 5492 5493 /* 5494 * the address should be Qword aligned if 64bit write, Dword 5495 * aligned if only send 32bit data low (discard data high) 5496 */ 5497 if (write64bit) 5498 BUG_ON(addr & 0x7); 5499 else 5500 BUG_ON(addr & 0x3); 5501 amdgpu_ring_write(ring, lower_32_bits(addr)); 5502 amdgpu_ring_write(ring, upper_32_bits(addr)); 5503 amdgpu_ring_write(ring, lower_32_bits(seq)); 5504 amdgpu_ring_write(ring, upper_32_bits(seq)); 5505 amdgpu_ring_write(ring, ring->is_mes_queue ? 5506 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 5507 } 5508 5509 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5510 { 5511 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5512 uint32_t seq = ring->fence_drv.sync_seq; 5513 uint64_t addr = ring->fence_drv.gpu_addr; 5514 5515 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 5516 upper_32_bits(addr), seq, 0xffffffff, 4); 5517 } 5518 5519 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 5520 uint16_t pasid, uint32_t flush_type, 5521 bool all_hub, uint8_t dst_sel) 5522 { 5523 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 5524 amdgpu_ring_write(ring, 5525 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 5526 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 5527 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 5528 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 5529 } 5530 5531 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5532 unsigned vmid, uint64_t pd_addr) 5533 { 5534 if (ring->is_mes_queue) 5535 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 5536 else 5537 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5538 5539 /* compute doesn't have PFP */ 5540 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5541 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5542 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5543 amdgpu_ring_write(ring, 0x0); 5544 } 5545 } 5546 5547 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5548 u64 seq, unsigned int flags) 5549 { 5550 struct amdgpu_device *adev = ring->adev; 5551 5552 /* we only allocate 32bit for each seq wb address */ 5553 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5554 5555 /* write fence seq to the "addr" */ 5556 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5557 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5558 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5559 amdgpu_ring_write(ring, lower_32_bits(addr)); 5560 amdgpu_ring_write(ring, upper_32_bits(addr)); 5561 amdgpu_ring_write(ring, lower_32_bits(seq)); 5562 5563 if (flags & AMDGPU_FENCE_FLAG_INT) { 5564 /* set register to trigger INT */ 5565 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5566 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5567 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5568 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 5569 amdgpu_ring_write(ring, 0); 5570 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5571 } 5572 } 5573 5574 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 5575 uint32_t flags) 5576 { 5577 uint32_t dw2 = 0; 5578 5579 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5580 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5581 /* set load_global_config & load_global_uconfig */ 5582 dw2 |= 0x8001; 5583 /* set load_cs_sh_regs */ 5584 dw2 |= 0x01000000; 5585 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5586 dw2 |= 0x10002; 5587 } 5588 5589 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5590 amdgpu_ring_write(ring, dw2); 5591 amdgpu_ring_write(ring, 0); 5592 } 5593 5594 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5595 { 5596 unsigned ret; 5597 5598 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5599 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5600 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5601 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5602 ret = ring->wptr & ring->buf_mask; 5603 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5604 5605 return ret; 5606 } 5607 5608 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5609 { 5610 unsigned cur; 5611 BUG_ON(offset > ring->buf_mask); 5612 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5613 5614 cur = (ring->wptr - 1) & ring->buf_mask; 5615 if (likely(cur > offset)) 5616 ring->ring[offset] = cur - offset; 5617 else 5618 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 5619 } 5620 5621 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) 5622 { 5623 int i, r = 0; 5624 struct amdgpu_device *adev = ring->adev; 5625 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5626 struct amdgpu_ring *kiq_ring = &kiq->ring; 5627 unsigned long flags; 5628 5629 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5630 return -EINVAL; 5631 5632 spin_lock_irqsave(&kiq->ring_lock, flags); 5633 5634 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5635 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5636 return -ENOMEM; 5637 } 5638 5639 /* assert preemption condition */ 5640 amdgpu_ring_set_preempt_cond_exec(ring, false); 5641 5642 /* assert IB preemption, emit the trailing fence */ 5643 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5644 ring->trail_fence_gpu_addr, 5645 ++ring->trail_seq); 5646 amdgpu_ring_commit(kiq_ring); 5647 5648 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5649 5650 /* poll the trailing fence */ 5651 for (i = 0; i < adev->usec_timeout; i++) { 5652 if (ring->trail_seq == 5653 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 5654 break; 5655 udelay(1); 5656 } 5657 5658 if (i >= adev->usec_timeout) { 5659 r = -EINVAL; 5660 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 5661 } 5662 5663 /* deassert preemption condition */ 5664 amdgpu_ring_set_preempt_cond_exec(ring, true); 5665 return r; 5666 } 5667 5668 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5669 { 5670 struct amdgpu_device *adev = ring->adev; 5671 struct v10_de_ib_state de_payload = {0}; 5672 uint64_t offset, gds_addr, de_payload_gpu_addr; 5673 void *de_payload_cpu_addr; 5674 int cnt; 5675 5676 if (ring->is_mes_queue) { 5677 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5678 gfx[0].gfx_meta_data) + 5679 offsetof(struct v10_gfx_meta_data, de_payload); 5680 de_payload_gpu_addr = 5681 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5682 de_payload_cpu_addr = 5683 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5684 5685 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5686 gfx[0].gds_backup) + 5687 offsetof(struct v10_gfx_meta_data, de_payload); 5688 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5689 } else { 5690 offset = offsetof(struct v10_gfx_meta_data, de_payload); 5691 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5692 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5693 5694 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5695 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5696 PAGE_SIZE); 5697 } 5698 5699 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5700 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5701 5702 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5703 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5704 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5705 WRITE_DATA_DST_SEL(8) | 5706 WR_CONFIRM) | 5707 WRITE_DATA_CACHE_POLICY(0)); 5708 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5709 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5710 5711 if (resume) 5712 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5713 sizeof(de_payload) >> 2); 5714 else 5715 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5716 sizeof(de_payload) >> 2); 5717 } 5718 5719 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5720 bool secure) 5721 { 5722 uint32_t v = secure ? FRAME_TMZ : 0; 5723 5724 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5725 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5726 } 5727 5728 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5729 uint32_t reg_val_offs) 5730 { 5731 struct amdgpu_device *adev = ring->adev; 5732 5733 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5734 amdgpu_ring_write(ring, 0 | /* src: register*/ 5735 (5 << 8) | /* dst: memory */ 5736 (1 << 20)); /* write confirm */ 5737 amdgpu_ring_write(ring, reg); 5738 amdgpu_ring_write(ring, 0); 5739 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5740 reg_val_offs * 4)); 5741 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5742 reg_val_offs * 4)); 5743 } 5744 5745 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5746 uint32_t val) 5747 { 5748 uint32_t cmd = 0; 5749 5750 switch (ring->funcs->type) { 5751 case AMDGPU_RING_TYPE_GFX: 5752 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5753 break; 5754 case AMDGPU_RING_TYPE_KIQ: 5755 cmd = (1 << 16); /* no inc addr */ 5756 break; 5757 default: 5758 cmd = WR_CONFIRM; 5759 break; 5760 } 5761 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5762 amdgpu_ring_write(ring, cmd); 5763 amdgpu_ring_write(ring, reg); 5764 amdgpu_ring_write(ring, 0); 5765 amdgpu_ring_write(ring, val); 5766 } 5767 5768 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5769 uint32_t val, uint32_t mask) 5770 { 5771 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5772 } 5773 5774 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5775 uint32_t reg0, uint32_t reg1, 5776 uint32_t ref, uint32_t mask) 5777 { 5778 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5779 5780 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5781 ref, mask, 0x20); 5782 } 5783 5784 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, 5785 unsigned vmid) 5786 { 5787 struct amdgpu_device *adev = ring->adev; 5788 uint32_t value = 0; 5789 5790 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5791 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5792 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5793 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5794 WREG32_SOC15(GC, 0, regSQ_CMD, value); 5795 } 5796 5797 static void 5798 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5799 uint32_t me, uint32_t pipe, 5800 enum amdgpu_interrupt_state state) 5801 { 5802 uint32_t cp_int_cntl, cp_int_cntl_reg; 5803 5804 if (!me) { 5805 switch (pipe) { 5806 case 0: 5807 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); 5808 break; 5809 case 1: 5810 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); 5811 break; 5812 default: 5813 DRM_DEBUG("invalid pipe %d\n", pipe); 5814 return; 5815 } 5816 } else { 5817 DRM_DEBUG("invalid me %d\n", me); 5818 return; 5819 } 5820 5821 switch (state) { 5822 case AMDGPU_IRQ_STATE_DISABLE: 5823 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5824 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5825 TIME_STAMP_INT_ENABLE, 0); 5826 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5827 GENERIC0_INT_ENABLE, 0); 5828 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5829 break; 5830 case AMDGPU_IRQ_STATE_ENABLE: 5831 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5832 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5833 TIME_STAMP_INT_ENABLE, 1); 5834 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5835 GENERIC0_INT_ENABLE, 1); 5836 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5837 break; 5838 default: 5839 break; 5840 } 5841 } 5842 5843 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5844 int me, int pipe, 5845 enum amdgpu_interrupt_state state) 5846 { 5847 u32 mec_int_cntl, mec_int_cntl_reg; 5848 5849 /* 5850 * amdgpu controls only the first MEC. That's why this function only 5851 * handles the setting of interrupts for this specific MEC. All other 5852 * pipes' interrupts are set by amdkfd. 5853 */ 5854 5855 if (me == 1) { 5856 switch (pipe) { 5857 case 0: 5858 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5859 break; 5860 case 1: 5861 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); 5862 break; 5863 case 2: 5864 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); 5865 break; 5866 case 3: 5867 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); 5868 break; 5869 default: 5870 DRM_DEBUG("invalid pipe %d\n", pipe); 5871 return; 5872 } 5873 } else { 5874 DRM_DEBUG("invalid me %d\n", me); 5875 return; 5876 } 5877 5878 switch (state) { 5879 case AMDGPU_IRQ_STATE_DISABLE: 5880 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5881 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5882 TIME_STAMP_INT_ENABLE, 0); 5883 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5884 GENERIC0_INT_ENABLE, 0); 5885 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5886 break; 5887 case AMDGPU_IRQ_STATE_ENABLE: 5888 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5889 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5890 TIME_STAMP_INT_ENABLE, 1); 5891 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5892 GENERIC0_INT_ENABLE, 1); 5893 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5894 break; 5895 default: 5896 break; 5897 } 5898 } 5899 5900 #define CP_ME1_PIPE_INST_ADDR_INTERVAL 0x1 5901 #define SET_ECC_ME_PIPE_STATE(reg_addr, state) \ 5902 do { \ 5903 uint32_t tmp = RREG32_SOC15_IP(GC, reg_addr); \ 5904 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, state); \ 5905 WREG32_SOC15_IP(GC, reg_addr, tmp); \ 5906 } while (0) 5907 5908 static int gfx_v11_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5909 struct amdgpu_irq_src *source, 5910 unsigned type, 5911 enum amdgpu_interrupt_state state) 5912 { 5913 uint32_t ecc_irq_state = 0; 5914 uint32_t pipe0_int_cntl_addr = 0; 5915 int i = 0; 5916 5917 ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0; 5918 5919 pipe0_int_cntl_addr = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5920 5921 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, ecc_irq_state); 5922 5923 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) 5924 SET_ECC_ME_PIPE_STATE(pipe0_int_cntl_addr + i * CP_ME1_PIPE_INST_ADDR_INTERVAL, 5925 ecc_irq_state); 5926 5927 return 0; 5928 } 5929 5930 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5931 struct amdgpu_irq_src *src, 5932 unsigned type, 5933 enum amdgpu_interrupt_state state) 5934 { 5935 switch (type) { 5936 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5937 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 5938 break; 5939 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 5940 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 5941 break; 5942 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5943 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5944 break; 5945 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5946 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5947 break; 5948 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5949 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5950 break; 5951 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5952 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5953 break; 5954 default: 5955 break; 5956 } 5957 return 0; 5958 } 5959 5960 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, 5961 struct amdgpu_irq_src *source, 5962 struct amdgpu_iv_entry *entry) 5963 { 5964 int i; 5965 u8 me_id, pipe_id, queue_id; 5966 struct amdgpu_ring *ring; 5967 uint32_t mes_queue_id = entry->src_data[0]; 5968 5969 DRM_DEBUG("IH: CP EOP\n"); 5970 5971 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 5972 struct amdgpu_mes_queue *queue; 5973 5974 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 5975 5976 spin_lock(&adev->mes.queue_id_lock); 5977 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 5978 if (queue) { 5979 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 5980 amdgpu_fence_process(queue->ring); 5981 } 5982 spin_unlock(&adev->mes.queue_id_lock); 5983 } else { 5984 me_id = (entry->ring_id & 0x0c) >> 2; 5985 pipe_id = (entry->ring_id & 0x03) >> 0; 5986 queue_id = (entry->ring_id & 0x70) >> 4; 5987 5988 switch (me_id) { 5989 case 0: 5990 if (pipe_id == 0) 5991 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5992 else 5993 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5994 break; 5995 case 1: 5996 case 2: 5997 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5998 ring = &adev->gfx.compute_ring[i]; 5999 /* Per-queue interrupt is supported for MEC starting from VI. 6000 * The interrupt can only be enabled/disabled per pipe instead 6001 * of per queue. 6002 */ 6003 if ((ring->me == me_id) && 6004 (ring->pipe == pipe_id) && 6005 (ring->queue == queue_id)) 6006 amdgpu_fence_process(ring); 6007 } 6008 break; 6009 } 6010 } 6011 6012 return 0; 6013 } 6014 6015 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6016 struct amdgpu_irq_src *source, 6017 unsigned type, 6018 enum amdgpu_interrupt_state state) 6019 { 6020 switch (state) { 6021 case AMDGPU_IRQ_STATE_DISABLE: 6022 case AMDGPU_IRQ_STATE_ENABLE: 6023 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 6024 PRIV_REG_INT_ENABLE, 6025 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6026 break; 6027 default: 6028 break; 6029 } 6030 6031 return 0; 6032 } 6033 6034 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6035 struct amdgpu_irq_src *source, 6036 unsigned type, 6037 enum amdgpu_interrupt_state state) 6038 { 6039 switch (state) { 6040 case AMDGPU_IRQ_STATE_DISABLE: 6041 case AMDGPU_IRQ_STATE_ENABLE: 6042 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, 6043 PRIV_INSTR_INT_ENABLE, 6044 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 6045 break; 6046 default: 6047 break; 6048 } 6049 6050 return 0; 6051 } 6052 6053 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev, 6054 struct amdgpu_iv_entry *entry) 6055 { 6056 u8 me_id, pipe_id, queue_id; 6057 struct amdgpu_ring *ring; 6058 int i; 6059 6060 me_id = (entry->ring_id & 0x0c) >> 2; 6061 pipe_id = (entry->ring_id & 0x03) >> 0; 6062 queue_id = (entry->ring_id & 0x70) >> 4; 6063 6064 switch (me_id) { 6065 case 0: 6066 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6067 ring = &adev->gfx.gfx_ring[i]; 6068 /* we only enabled 1 gfx queue per pipe for now */ 6069 if (ring->me == me_id && ring->pipe == pipe_id) 6070 drm_sched_fault(&ring->sched); 6071 } 6072 break; 6073 case 1: 6074 case 2: 6075 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6076 ring = &adev->gfx.compute_ring[i]; 6077 if (ring->me == me_id && ring->pipe == pipe_id && 6078 ring->queue == queue_id) 6079 drm_sched_fault(&ring->sched); 6080 } 6081 break; 6082 default: 6083 BUG(); 6084 break; 6085 } 6086 } 6087 6088 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev, 6089 struct amdgpu_irq_src *source, 6090 struct amdgpu_iv_entry *entry) 6091 { 6092 DRM_ERROR("Illegal register access in command stream\n"); 6093 gfx_v11_0_handle_priv_fault(adev, entry); 6094 return 0; 6095 } 6096 6097 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev, 6098 struct amdgpu_irq_src *source, 6099 struct amdgpu_iv_entry *entry) 6100 { 6101 DRM_ERROR("Illegal instruction in command stream\n"); 6102 gfx_v11_0_handle_priv_fault(adev, entry); 6103 return 0; 6104 } 6105 6106 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev, 6107 struct amdgpu_irq_src *source, 6108 struct amdgpu_iv_entry *entry) 6109 { 6110 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq) 6111 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry); 6112 6113 return 0; 6114 } 6115 6116 #if 0 6117 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6118 struct amdgpu_irq_src *src, 6119 unsigned int type, 6120 enum amdgpu_interrupt_state state) 6121 { 6122 uint32_t tmp, target; 6123 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 6124 6125 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 6126 target += ring->pipe; 6127 6128 switch (type) { 6129 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6130 if (state == AMDGPU_IRQ_STATE_DISABLE) { 6131 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6132 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6133 GENERIC2_INT_ENABLE, 0); 6134 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6135 6136 tmp = RREG32_SOC15_IP(GC, target); 6137 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6138 GENERIC2_INT_ENABLE, 0); 6139 WREG32_SOC15_IP(GC, target, tmp); 6140 } else { 6141 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL); 6142 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 6143 GENERIC2_INT_ENABLE, 1); 6144 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp); 6145 6146 tmp = RREG32_SOC15_IP(GC, target); 6147 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, 6148 GENERIC2_INT_ENABLE, 1); 6149 WREG32_SOC15_IP(GC, target, tmp); 6150 } 6151 break; 6152 default: 6153 BUG(); /* kiq only support GENERIC2_INT now */ 6154 break; 6155 } 6156 return 0; 6157 } 6158 #endif 6159 6160 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) 6161 { 6162 const unsigned int gcr_cntl = 6163 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 6164 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 6165 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 6166 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 6167 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 6168 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 6169 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 6170 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 6171 6172 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 6173 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 6174 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 6175 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6176 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6177 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6178 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6179 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6180 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 6181 } 6182 6183 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = { 6184 .name = "gfx_v11_0", 6185 .early_init = gfx_v11_0_early_init, 6186 .late_init = gfx_v11_0_late_init, 6187 .sw_init = gfx_v11_0_sw_init, 6188 .sw_fini = gfx_v11_0_sw_fini, 6189 .hw_init = gfx_v11_0_hw_init, 6190 .hw_fini = gfx_v11_0_hw_fini, 6191 .suspend = gfx_v11_0_suspend, 6192 .resume = gfx_v11_0_resume, 6193 .is_idle = gfx_v11_0_is_idle, 6194 .wait_for_idle = gfx_v11_0_wait_for_idle, 6195 .soft_reset = gfx_v11_0_soft_reset, 6196 .check_soft_reset = gfx_v11_0_check_soft_reset, 6197 .post_soft_reset = gfx_v11_0_post_soft_reset, 6198 .set_clockgating_state = gfx_v11_0_set_clockgating_state, 6199 .set_powergating_state = gfx_v11_0_set_powergating_state, 6200 .get_clockgating_state = gfx_v11_0_get_clockgating_state, 6201 }; 6202 6203 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 6204 .type = AMDGPU_RING_TYPE_GFX, 6205 .align_mask = 0xff, 6206 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6207 .support_64bit_ptrs = true, 6208 .secure_submission_supported = true, 6209 .get_rptr = gfx_v11_0_ring_get_rptr_gfx, 6210 .get_wptr = gfx_v11_0_ring_get_wptr_gfx, 6211 .set_wptr = gfx_v11_0_ring_set_wptr_gfx, 6212 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6213 5 + /* COND_EXEC */ 6214 7 + /* PIPELINE_SYNC */ 6215 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6216 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6217 2 + /* VM_FLUSH */ 6218 8 + /* FENCE for VM_FLUSH */ 6219 20 + /* GDS switch */ 6220 5 + /* COND_EXEC */ 6221 7 + /* HDP_flush */ 6222 4 + /* VGT_flush */ 6223 31 + /* DE_META */ 6224 3 + /* CNTX_CTRL */ 6225 5 + /* HDP_INVL */ 6226 8 + 8 + /* FENCE x2 */ 6227 8, /* gfx_v11_0_emit_mem_sync */ 6228 .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ 6229 .emit_ib = gfx_v11_0_ring_emit_ib_gfx, 6230 .emit_fence = gfx_v11_0_ring_emit_fence, 6231 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6232 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6233 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6234 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6235 .test_ring = gfx_v11_0_ring_test_ring, 6236 .test_ib = gfx_v11_0_ring_test_ib, 6237 .insert_nop = amdgpu_ring_insert_nop, 6238 .pad_ib = amdgpu_ring_generic_pad_ib, 6239 .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl, 6240 .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec, 6241 .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec, 6242 .preempt_ib = gfx_v11_0_ring_preempt_ib, 6243 .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl, 6244 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6245 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6246 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6247 .soft_recovery = gfx_v11_0_ring_soft_recovery, 6248 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6249 }; 6250 6251 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { 6252 .type = AMDGPU_RING_TYPE_COMPUTE, 6253 .align_mask = 0xff, 6254 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6255 .support_64bit_ptrs = true, 6256 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6257 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6258 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6259 .emit_frame_size = 6260 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6261 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6262 5 + /* hdp invalidate */ 6263 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6264 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6265 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6266 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6267 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ 6268 8, /* gfx_v11_0_emit_mem_sync */ 6269 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6270 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6271 .emit_fence = gfx_v11_0_ring_emit_fence, 6272 .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync, 6273 .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush, 6274 .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch, 6275 .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, 6276 .test_ring = gfx_v11_0_ring_test_ring, 6277 .test_ib = gfx_v11_0_ring_test_ib, 6278 .insert_nop = amdgpu_ring_insert_nop, 6279 .pad_ib = amdgpu_ring_generic_pad_ib, 6280 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6281 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6282 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6283 .emit_mem_sync = gfx_v11_0_emit_mem_sync, 6284 }; 6285 6286 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { 6287 .type = AMDGPU_RING_TYPE_KIQ, 6288 .align_mask = 0xff, 6289 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6290 .support_64bit_ptrs = true, 6291 .get_rptr = gfx_v11_0_ring_get_rptr_compute, 6292 .get_wptr = gfx_v11_0_ring_get_wptr_compute, 6293 .set_wptr = gfx_v11_0_ring_set_wptr_compute, 6294 .emit_frame_size = 6295 20 + /* gfx_v11_0_ring_emit_gds_switch */ 6296 7 + /* gfx_v11_0_ring_emit_hdp_flush */ 6297 5 + /*hdp invalidate */ 6298 7 + /* gfx_v11_0_ring_emit_pipeline_sync */ 6299 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6300 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6301 2 + /* gfx_v11_0_ring_emit_vm_flush */ 6302 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6303 .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ 6304 .emit_ib = gfx_v11_0_ring_emit_ib_compute, 6305 .emit_fence = gfx_v11_0_ring_emit_fence_kiq, 6306 .test_ring = gfx_v11_0_ring_test_ring, 6307 .test_ib = gfx_v11_0_ring_test_ib, 6308 .insert_nop = amdgpu_ring_insert_nop, 6309 .pad_ib = amdgpu_ring_generic_pad_ib, 6310 .emit_rreg = gfx_v11_0_ring_emit_rreg, 6311 .emit_wreg = gfx_v11_0_ring_emit_wreg, 6312 .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, 6313 .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, 6314 }; 6315 6316 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) 6317 { 6318 int i; 6319 6320 adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq; 6321 6322 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6323 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx; 6324 6325 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6326 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute; 6327 } 6328 6329 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = { 6330 .set = gfx_v11_0_set_eop_interrupt_state, 6331 .process = gfx_v11_0_eop_irq, 6332 }; 6333 6334 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = { 6335 .set = gfx_v11_0_set_priv_reg_fault_state, 6336 .process = gfx_v11_0_priv_reg_irq, 6337 }; 6338 6339 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 6340 .set = gfx_v11_0_set_priv_inst_fault_state, 6341 .process = gfx_v11_0_priv_inst_irq, 6342 }; 6343 6344 static const struct amdgpu_irq_src_funcs gfx_v11_0_cp_ecc_error_irq_funcs = { 6345 .set = gfx_v11_0_set_cp_ecc_error_state, 6346 .process = amdgpu_gfx_cp_ecc_error_irq, 6347 }; 6348 6349 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 6350 .process = gfx_v11_0_rlc_gc_fed_irq, 6351 }; 6352 6353 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 6354 { 6355 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6356 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs; 6357 6358 adev->gfx.priv_reg_irq.num_types = 1; 6359 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs; 6360 6361 adev->gfx.priv_inst_irq.num_types = 1; 6362 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6363 6364 adev->gfx.cp_ecc_error_irq.num_types = 1; /* CP ECC error */ 6365 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v11_0_cp_ecc_error_irq_funcs; 6366 6367 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 6368 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs; 6369 6370 } 6371 6372 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev) 6373 { 6374 if (adev->flags & AMD_IS_APU) 6375 adev->gfx.imu.mode = MISSION_MODE; 6376 else 6377 adev->gfx.imu.mode = DEBUG_MODE; 6378 6379 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs; 6380 } 6381 6382 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev) 6383 { 6384 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs; 6385 } 6386 6387 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev) 6388 { 6389 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 6390 adev->gfx.config.max_sh_per_se * 6391 adev->gfx.config.max_shader_engines; 6392 6393 adev->gds.gds_size = 0x1000; 6394 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 6395 adev->gds.gws_size = 64; 6396 adev->gds.oa_size = 16; 6397 } 6398 6399 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) 6400 { 6401 /* set gfx eng mqd */ 6402 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 6403 sizeof(struct v11_gfx_mqd); 6404 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 6405 gfx_v11_0_gfx_mqd_init; 6406 /* set compute eng mqd */ 6407 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 6408 sizeof(struct v11_compute_mqd); 6409 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 6410 gfx_v11_0_compute_mqd_init; 6411 } 6412 6413 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 6414 u32 bitmap) 6415 { 6416 u32 data; 6417 6418 if (!bitmap) 6419 return; 6420 6421 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6422 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6423 6424 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 6425 } 6426 6427 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 6428 { 6429 u32 data, wgp_bitmask; 6430 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 6431 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 6432 6433 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 6434 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 6435 6436 wgp_bitmask = 6437 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 6438 6439 return (~data) & wgp_bitmask; 6440 } 6441 6442 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 6443 { 6444 u32 wgp_idx, wgp_active_bitmap; 6445 u32 cu_bitmap_per_wgp, cu_active_bitmap; 6446 6447 wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev); 6448 cu_active_bitmap = 0; 6449 6450 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 6451 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 6452 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 6453 if (wgp_active_bitmap & (1 << wgp_idx)) 6454 cu_active_bitmap |= cu_bitmap_per_wgp; 6455 } 6456 6457 return cu_active_bitmap; 6458 } 6459 6460 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, 6461 struct amdgpu_cu_info *cu_info) 6462 { 6463 int i, j, k, counter, active_cu_number = 0; 6464 u32 mask, bitmap; 6465 unsigned disable_masks[8 * 2]; 6466 6467 if (!adev || !cu_info) 6468 return -EINVAL; 6469 6470 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 6471 6472 mutex_lock(&adev->grbm_idx_mutex); 6473 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6474 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6475 mask = 1; 6476 counter = 0; 6477 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 6478 if (i < 8 && j < 2) 6479 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6480 adev, disable_masks[i * 2 + j]); 6481 bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev); 6482 6483 /** 6484 * GFX11 could support more than 4 SEs, while the bitmap 6485 * in cu_info struct is 4x4 and ioctl interface struct 6486 * drm_amdgpu_info_device should keep stable. 6487 * So we use last two columns of bitmap to store cu mask for 6488 * SEs 4 to 7, the layout of the bitmap is as below: 6489 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} 6490 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} 6491 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} 6492 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} 6493 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} 6494 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]} 6495 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} 6496 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} 6497 */ 6498 cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; 6499 6500 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 6501 if (bitmap & mask) 6502 counter++; 6503 6504 mask <<= 1; 6505 } 6506 active_cu_number += counter; 6507 } 6508 } 6509 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6510 mutex_unlock(&adev->grbm_idx_mutex); 6511 6512 cu_info->number = active_cu_number; 6513 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6514 6515 return 0; 6516 } 6517 6518 const struct amdgpu_ip_block_version gfx_v11_0_ip_block = 6519 { 6520 .type = AMD_IP_BLOCK_TYPE_GFX, 6521 .major = 11, 6522 .minor = 0, 6523 .rev = 0, 6524 .funcs = &gfx_v11_0_ip_funcs, 6525 }; 6526