1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "navi10_enum.h" 39 #include "hdp/hdp_5_0_0_offset.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15_common.h" 44 #include "clearstate_gfx10.h" 45 #include "v10_structs.h" 46 #include "gfx_v10_0.h" 47 #include "nbio_v2_3.h" 48 49 /** 50 * Navi10 has two graphic rings to share each graphic pipe. 51 * 1. Primary ring 52 * 2. Async ring 53 * 54 * In bring-up phase, it just used primary ring so set gfx ring number as 1 at 55 * first. 56 */ 57 #define GFX10_NUM_GFX_RINGS 2 58 #define GFX10_MEC_HPD_SIZE 2048 59 60 #define F32_CE_PROGRAM_RAM_SIZE 65536 61 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 62 63 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 68 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 72 73 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 74 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 75 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 76 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 77 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 78 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 79 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 80 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 81 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 82 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 83 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 84 85 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 86 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 87 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 88 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 89 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 90 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 91 92 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 93 { 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 131 }; 132 133 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 134 { 135 /* Pending on emulation bring up */ 136 }; 137 138 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 139 { 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000), 175 }; 176 177 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 178 { 179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 219 }; 220 221 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 222 { 223 /* Pending on emulation bring up */ 224 }; 225 226 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 227 { 228 /* Pending on emulation bring up */ 229 }; 230 231 #define DEFAULT_SH_MEM_CONFIG \ 232 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 233 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 234 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 235 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 236 237 238 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 239 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 240 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 241 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 242 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 243 struct amdgpu_cu_info *cu_info); 244 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 245 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 246 u32 sh_num, u32 instance); 247 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 248 249 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 250 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 251 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 252 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 253 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 254 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 255 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start); 256 257 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 258 { 259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 260 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 261 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 262 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 263 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 264 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 265 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 266 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 267 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 268 } 269 270 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 271 struct amdgpu_ring *ring) 272 { 273 struct amdgpu_device *adev = kiq_ring->adev; 274 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 275 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 276 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 277 278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 279 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 280 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 281 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 282 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 283 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 284 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 285 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 286 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 287 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 288 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 289 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 290 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 291 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 292 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 293 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 294 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 295 } 296 297 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 298 struct amdgpu_ring *ring, 299 enum amdgpu_unmap_queues_action action, 300 u64 gpu_addr, u64 seq) 301 { 302 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 303 304 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 305 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 306 PACKET3_UNMAP_QUEUES_ACTION(action) | 307 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 308 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 309 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 310 amdgpu_ring_write(kiq_ring, 311 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 312 313 if (action == PREEMPT_QUEUES_NO_UNMAP) { 314 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 315 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 316 amdgpu_ring_write(kiq_ring, seq); 317 } else { 318 amdgpu_ring_write(kiq_ring, 0); 319 amdgpu_ring_write(kiq_ring, 0); 320 amdgpu_ring_write(kiq_ring, 0); 321 } 322 } 323 324 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 325 struct amdgpu_ring *ring, 326 u64 addr, 327 u64 seq) 328 { 329 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 330 331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 332 amdgpu_ring_write(kiq_ring, 333 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 334 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 335 PACKET3_QUERY_STATUS_COMMAND(2)); 336 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 337 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 338 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 339 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 340 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 341 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 342 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 343 } 344 345 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 346 .kiq_set_resources = gfx10_kiq_set_resources, 347 .kiq_map_queues = gfx10_kiq_map_queues, 348 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 349 .kiq_query_status = gfx10_kiq_query_status, 350 .set_resources_size = 8, 351 .map_queues_size = 7, 352 .unmap_queues_size = 6, 353 .query_status_size = 7, 354 }; 355 356 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 357 { 358 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 359 } 360 361 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 362 { 363 switch (adev->asic_type) { 364 case CHIP_NAVI10: 365 soc15_program_register_sequence(adev, 366 golden_settings_gc_10_1, 367 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 368 soc15_program_register_sequence(adev, 369 golden_settings_gc_10_0_nv10, 370 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 371 break; 372 case CHIP_NAVI14: 373 soc15_program_register_sequence(adev, 374 golden_settings_gc_10_1_1, 375 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 376 soc15_program_register_sequence(adev, 377 golden_settings_gc_10_1_nv14, 378 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 379 break; 380 case CHIP_NAVI12: 381 soc15_program_register_sequence(adev, 382 golden_settings_gc_10_1_2, 383 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 384 soc15_program_register_sequence(adev, 385 golden_settings_gc_10_1_2_nv12, 386 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 387 break; 388 default: 389 break; 390 } 391 } 392 393 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 394 { 395 adev->gfx.scratch.num_reg = 8; 396 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 397 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 398 } 399 400 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 401 bool wc, uint32_t reg, uint32_t val) 402 { 403 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 404 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 405 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 406 amdgpu_ring_write(ring, reg); 407 amdgpu_ring_write(ring, 0); 408 amdgpu_ring_write(ring, val); 409 } 410 411 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 412 int mem_space, int opt, uint32_t addr0, 413 uint32_t addr1, uint32_t ref, uint32_t mask, 414 uint32_t inv) 415 { 416 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 417 amdgpu_ring_write(ring, 418 /* memory (1) or register (0) */ 419 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 420 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 421 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 422 WAIT_REG_MEM_ENGINE(eng_sel))); 423 424 if (mem_space) 425 BUG_ON(addr0 & 0x3); /* Dword align */ 426 amdgpu_ring_write(ring, addr0); 427 amdgpu_ring_write(ring, addr1); 428 amdgpu_ring_write(ring, ref); 429 amdgpu_ring_write(ring, mask); 430 amdgpu_ring_write(ring, inv); /* poll interval */ 431 } 432 433 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 434 { 435 struct amdgpu_device *adev = ring->adev; 436 uint32_t scratch; 437 uint32_t tmp = 0; 438 unsigned i; 439 int r; 440 441 r = amdgpu_gfx_scratch_get(adev, &scratch); 442 if (r) { 443 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 444 return r; 445 } 446 447 WREG32(scratch, 0xCAFEDEAD); 448 449 r = amdgpu_ring_alloc(ring, 3); 450 if (r) { 451 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 452 ring->idx, r); 453 amdgpu_gfx_scratch_free(adev, scratch); 454 return r; 455 } 456 457 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 458 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 459 amdgpu_ring_write(ring, 0xDEADBEEF); 460 amdgpu_ring_commit(ring); 461 462 for (i = 0; i < adev->usec_timeout; i++) { 463 tmp = RREG32(scratch); 464 if (tmp == 0xDEADBEEF) 465 break; 466 if (amdgpu_emu_mode == 1) 467 msleep(1); 468 else 469 udelay(1); 470 } 471 if (i < adev->usec_timeout) { 472 if (amdgpu_emu_mode == 1) 473 DRM_INFO("ring test on %d succeeded in %d msecs\n", 474 ring->idx, i); 475 else 476 DRM_INFO("ring test on %d succeeded in %d usecs\n", 477 ring->idx, i); 478 } else { 479 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 480 ring->idx, scratch, tmp); 481 r = -EINVAL; 482 } 483 amdgpu_gfx_scratch_free(adev, scratch); 484 485 return r; 486 } 487 488 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 489 { 490 struct amdgpu_device *adev = ring->adev; 491 struct amdgpu_ib ib; 492 struct dma_fence *f = NULL; 493 uint32_t scratch; 494 uint32_t tmp = 0; 495 long r; 496 497 r = amdgpu_gfx_scratch_get(adev, &scratch); 498 if (r) { 499 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 500 return r; 501 } 502 503 WREG32(scratch, 0xCAFEDEAD); 504 505 memset(&ib, 0, sizeof(ib)); 506 r = amdgpu_ib_get(adev, NULL, 256, &ib); 507 if (r) { 508 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 509 goto err1; 510 } 511 512 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 513 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 514 ib.ptr[2] = 0xDEADBEEF; 515 ib.length_dw = 3; 516 517 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 518 if (r) 519 goto err2; 520 521 r = dma_fence_wait_timeout(f, false, timeout); 522 if (r == 0) { 523 DRM_ERROR("amdgpu: IB test timed out.\n"); 524 r = -ETIMEDOUT; 525 goto err2; 526 } else if (r < 0) { 527 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 528 goto err2; 529 } 530 531 tmp = RREG32(scratch); 532 if (tmp == 0xDEADBEEF) { 533 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 534 r = 0; 535 } else { 536 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 537 scratch, tmp); 538 r = -EINVAL; 539 } 540 err2: 541 amdgpu_ib_free(adev, &ib, NULL); 542 dma_fence_put(f); 543 err1: 544 amdgpu_gfx_scratch_free(adev, scratch); 545 546 return r; 547 } 548 549 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 550 { 551 release_firmware(adev->gfx.pfp_fw); 552 adev->gfx.pfp_fw = NULL; 553 release_firmware(adev->gfx.me_fw); 554 adev->gfx.me_fw = NULL; 555 release_firmware(adev->gfx.ce_fw); 556 adev->gfx.ce_fw = NULL; 557 release_firmware(adev->gfx.rlc_fw); 558 adev->gfx.rlc_fw = NULL; 559 release_firmware(adev->gfx.mec_fw); 560 adev->gfx.mec_fw = NULL; 561 release_firmware(adev->gfx.mec2_fw); 562 adev->gfx.mec2_fw = NULL; 563 564 kfree(adev->gfx.rlc.register_list_format); 565 } 566 567 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 568 { 569 const struct rlc_firmware_header_v2_1 *rlc_hdr; 570 571 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 572 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 573 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 574 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 575 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 576 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 577 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 578 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 579 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 580 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 581 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 582 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 583 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 584 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 585 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 586 } 587 588 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 589 { 590 switch (adev->asic_type) { 591 case CHIP_NAVI10: 592 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 593 break; 594 default: 595 break; 596 } 597 } 598 599 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 600 { 601 const char *chip_name; 602 char fw_name[40]; 603 char wks[10]; 604 int err; 605 struct amdgpu_firmware_info *info = NULL; 606 const struct common_firmware_header *header = NULL; 607 const struct gfx_firmware_header_v1_0 *cp_hdr; 608 const struct rlc_firmware_header_v2_0 *rlc_hdr; 609 unsigned int *tmp = NULL; 610 unsigned int i = 0; 611 uint16_t version_major; 612 uint16_t version_minor; 613 614 DRM_DEBUG("\n"); 615 616 memset(wks, 0, sizeof(wks)); 617 switch (adev->asic_type) { 618 case CHIP_NAVI10: 619 chip_name = "navi10"; 620 break; 621 case CHIP_NAVI14: 622 chip_name = "navi14"; 623 if (!(adev->pdev->device == 0x7340 && 624 adev->pdev->revision != 0x00)) 625 snprintf(wks, sizeof(wks), "_wks"); 626 break; 627 case CHIP_NAVI12: 628 chip_name = "navi12"; 629 break; 630 default: 631 BUG(); 632 } 633 634 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 635 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 636 if (err) 637 goto out; 638 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 639 if (err) 640 goto out; 641 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 642 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 643 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 644 645 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 646 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 647 if (err) 648 goto out; 649 err = amdgpu_ucode_validate(adev->gfx.me_fw); 650 if (err) 651 goto out; 652 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 653 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 654 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 655 656 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 657 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 658 if (err) 659 goto out; 660 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 661 if (err) 662 goto out; 663 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 664 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 665 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 666 667 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 668 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 669 if (err) 670 goto out; 671 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 672 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 673 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 674 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 675 if (version_major == 2 && version_minor == 1) 676 adev->gfx.rlc.is_rlc_v2_1 = true; 677 678 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 679 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 680 adev->gfx.rlc.save_and_restore_offset = 681 le32_to_cpu(rlc_hdr->save_and_restore_offset); 682 adev->gfx.rlc.clear_state_descriptor_offset = 683 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 684 adev->gfx.rlc.avail_scratch_ram_locations = 685 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 686 adev->gfx.rlc.reg_restore_list_size = 687 le32_to_cpu(rlc_hdr->reg_restore_list_size); 688 adev->gfx.rlc.reg_list_format_start = 689 le32_to_cpu(rlc_hdr->reg_list_format_start); 690 adev->gfx.rlc.reg_list_format_separate_start = 691 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 692 adev->gfx.rlc.starting_offsets_start = 693 le32_to_cpu(rlc_hdr->starting_offsets_start); 694 adev->gfx.rlc.reg_list_format_size_bytes = 695 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 696 adev->gfx.rlc.reg_list_size_bytes = 697 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 698 adev->gfx.rlc.register_list_format = 699 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 700 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 701 if (!adev->gfx.rlc.register_list_format) { 702 err = -ENOMEM; 703 goto out; 704 } 705 706 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 707 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 708 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 709 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 710 711 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 712 713 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 714 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 715 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 716 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 717 718 if (adev->gfx.rlc.is_rlc_v2_1) 719 gfx_v10_0_init_rlc_ext_microcode(adev); 720 721 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 722 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 723 if (err) 724 goto out; 725 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 726 if (err) 727 goto out; 728 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 729 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 730 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 731 732 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 733 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 734 if (!err) { 735 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 736 if (err) 737 goto out; 738 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 739 adev->gfx.mec2_fw->data; 740 adev->gfx.mec2_fw_version = 741 le32_to_cpu(cp_hdr->header.ucode_version); 742 adev->gfx.mec2_feature_version = 743 le32_to_cpu(cp_hdr->ucode_feature_version); 744 } else { 745 err = 0; 746 adev->gfx.mec2_fw = NULL; 747 } 748 749 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 750 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 751 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 752 info->fw = adev->gfx.pfp_fw; 753 header = (const struct common_firmware_header *)info->fw->data; 754 adev->firmware.fw_size += 755 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 756 757 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 758 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 759 info->fw = adev->gfx.me_fw; 760 header = (const struct common_firmware_header *)info->fw->data; 761 adev->firmware.fw_size += 762 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 763 764 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 765 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 766 info->fw = adev->gfx.ce_fw; 767 header = (const struct common_firmware_header *)info->fw->data; 768 adev->firmware.fw_size += 769 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 770 771 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 772 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 773 info->fw = adev->gfx.rlc_fw; 774 header = (const struct common_firmware_header *)info->fw->data; 775 adev->firmware.fw_size += 776 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 777 778 if (adev->gfx.rlc.is_rlc_v2_1 && 779 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 780 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 781 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 782 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 783 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 784 info->fw = adev->gfx.rlc_fw; 785 adev->firmware.fw_size += 786 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 787 788 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 789 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 790 info->fw = adev->gfx.rlc_fw; 791 adev->firmware.fw_size += 792 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 793 794 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 795 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 796 info->fw = adev->gfx.rlc_fw; 797 adev->firmware.fw_size += 798 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 799 } 800 801 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 802 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 803 info->fw = adev->gfx.mec_fw; 804 header = (const struct common_firmware_header *)info->fw->data; 805 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 806 adev->firmware.fw_size += 807 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 808 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 809 810 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 811 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 812 info->fw = adev->gfx.mec_fw; 813 adev->firmware.fw_size += 814 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 815 816 if (adev->gfx.mec2_fw) { 817 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 818 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 819 info->fw = adev->gfx.mec2_fw; 820 header = (const struct common_firmware_header *)info->fw->data; 821 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 822 adev->firmware.fw_size += 823 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 824 le32_to_cpu(cp_hdr->jt_size) * 4, 825 PAGE_SIZE); 826 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 827 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 828 info->fw = adev->gfx.mec2_fw; 829 adev->firmware.fw_size += 830 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 831 PAGE_SIZE); 832 } 833 } 834 835 out: 836 if (err) { 837 dev_err(adev->dev, 838 "gfx10: Failed to load firmware \"%s\"\n", 839 fw_name); 840 release_firmware(adev->gfx.pfp_fw); 841 adev->gfx.pfp_fw = NULL; 842 release_firmware(adev->gfx.me_fw); 843 adev->gfx.me_fw = NULL; 844 release_firmware(adev->gfx.ce_fw); 845 adev->gfx.ce_fw = NULL; 846 release_firmware(adev->gfx.rlc_fw); 847 adev->gfx.rlc_fw = NULL; 848 release_firmware(adev->gfx.mec_fw); 849 adev->gfx.mec_fw = NULL; 850 release_firmware(adev->gfx.mec2_fw); 851 adev->gfx.mec2_fw = NULL; 852 } 853 854 gfx_v10_0_check_gfxoff_flag(adev); 855 856 return err; 857 } 858 859 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 860 { 861 u32 count = 0; 862 const struct cs_section_def *sect = NULL; 863 const struct cs_extent_def *ext = NULL; 864 865 /* begin clear state */ 866 count += 2; 867 /* context control state */ 868 count += 3; 869 870 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 871 for (ext = sect->section; ext->extent != NULL; ++ext) { 872 if (sect->id == SECT_CONTEXT) 873 count += 2 + ext->reg_count; 874 else 875 return 0; 876 } 877 } 878 879 /* set PA_SC_TILE_STEERING_OVERRIDE */ 880 count += 3; 881 /* end clear state */ 882 count += 2; 883 /* clear state */ 884 count += 2; 885 886 return count; 887 } 888 889 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 890 volatile u32 *buffer) 891 { 892 u32 count = 0, i; 893 const struct cs_section_def *sect = NULL; 894 const struct cs_extent_def *ext = NULL; 895 int ctx_reg_offset; 896 897 if (adev->gfx.rlc.cs_data == NULL) 898 return; 899 if (buffer == NULL) 900 return; 901 902 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 903 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 904 905 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 906 buffer[count++] = cpu_to_le32(0x80000000); 907 buffer[count++] = cpu_to_le32(0x80000000); 908 909 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 910 for (ext = sect->section; ext->extent != NULL; ++ext) { 911 if (sect->id == SECT_CONTEXT) { 912 buffer[count++] = 913 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 914 buffer[count++] = cpu_to_le32(ext->reg_index - 915 PACKET3_SET_CONTEXT_REG_START); 916 for (i = 0; i < ext->reg_count; i++) 917 buffer[count++] = cpu_to_le32(ext->extent[i]); 918 } else { 919 return; 920 } 921 } 922 } 923 924 ctx_reg_offset = 925 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 926 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 927 buffer[count++] = cpu_to_le32(ctx_reg_offset); 928 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 929 930 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 931 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 932 933 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 934 buffer[count++] = cpu_to_le32(0); 935 } 936 937 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 938 { 939 /* clear state block */ 940 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 941 &adev->gfx.rlc.clear_state_gpu_addr, 942 (void **)&adev->gfx.rlc.cs_ptr); 943 944 /* jump table block */ 945 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 946 &adev->gfx.rlc.cp_table_gpu_addr, 947 (void **)&adev->gfx.rlc.cp_table_ptr); 948 } 949 950 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 951 { 952 const struct cs_section_def *cs_data; 953 int r; 954 955 adev->gfx.rlc.cs_data = gfx10_cs_data; 956 957 cs_data = adev->gfx.rlc.cs_data; 958 959 if (cs_data) { 960 /* init clear state block */ 961 r = amdgpu_gfx_rlc_init_csb(adev); 962 if (r) 963 return r; 964 } 965 966 return 0; 967 } 968 969 static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev) 970 { 971 int r; 972 973 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 974 if (unlikely(r != 0)) 975 return r; 976 977 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, 978 AMDGPU_GEM_DOMAIN_VRAM); 979 if (!r) 980 adev->gfx.rlc.clear_state_gpu_addr = 981 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); 982 983 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 984 985 return r; 986 } 987 988 static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev) 989 { 990 int r; 991 992 if (!adev->gfx.rlc.clear_state_obj) 993 return; 994 995 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); 996 if (likely(r == 0)) { 997 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 998 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 999 } 1000 } 1001 1002 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 1003 { 1004 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1005 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1006 } 1007 1008 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 1009 { 1010 int r; 1011 1012 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 1013 1014 amdgpu_gfx_graphics_queue_acquire(adev); 1015 1016 r = gfx_v10_0_init_microcode(adev); 1017 if (r) 1018 DRM_ERROR("Failed to load gfx firmware!\n"); 1019 1020 return r; 1021 } 1022 1023 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 1024 { 1025 int r; 1026 u32 *hpd; 1027 const __le32 *fw_data = NULL; 1028 unsigned fw_size; 1029 u32 *fw = NULL; 1030 size_t mec_hpd_size; 1031 1032 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 1033 1034 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1035 1036 /* take ownership of the relevant compute queues */ 1037 amdgpu_gfx_compute_queue_acquire(adev); 1038 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 1039 1040 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1041 AMDGPU_GEM_DOMAIN_GTT, 1042 &adev->gfx.mec.hpd_eop_obj, 1043 &adev->gfx.mec.hpd_eop_gpu_addr, 1044 (void **)&hpd); 1045 if (r) { 1046 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1047 gfx_v10_0_mec_fini(adev); 1048 return r; 1049 } 1050 1051 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 1052 1053 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1054 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1055 1056 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1057 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1058 1059 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1060 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1061 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1062 1063 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1064 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1065 &adev->gfx.mec.mec_fw_obj, 1066 &adev->gfx.mec.mec_fw_gpu_addr, 1067 (void **)&fw); 1068 if (r) { 1069 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 1070 gfx_v10_0_mec_fini(adev); 1071 return r; 1072 } 1073 1074 memcpy(fw, fw_data, fw_size); 1075 1076 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1077 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1078 } 1079 1080 return 0; 1081 } 1082 1083 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1084 { 1085 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1086 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1087 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1088 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1089 } 1090 1091 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1092 uint32_t thread, uint32_t regno, 1093 uint32_t num, uint32_t *out) 1094 { 1095 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1096 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1097 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1098 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1099 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1100 while (num--) 1101 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1102 } 1103 1104 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1105 { 1106 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 1107 * field when performing a select_se_sh so it should be 1108 * zero here */ 1109 WARN_ON(simd != 0); 1110 1111 /* type 2 wave data */ 1112 dst[(*no_fields)++] = 2; 1113 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1114 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1115 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1116 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1117 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1118 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1119 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1120 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 1121 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1122 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1123 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1124 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1125 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1126 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1127 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1128 } 1129 1130 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1131 uint32_t wave, uint32_t start, 1132 uint32_t size, uint32_t *dst) 1133 { 1134 WARN_ON(simd != 0); 1135 1136 wave_read_regs( 1137 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1138 dst); 1139 } 1140 1141 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1142 uint32_t wave, uint32_t thread, 1143 uint32_t start, uint32_t size, 1144 uint32_t *dst) 1145 { 1146 wave_read_regs( 1147 adev, wave, thread, 1148 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1149 } 1150 1151 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 1152 u32 me, u32 pipe, u32 q, u32 vm) 1153 { 1154 nv_grbm_select(adev, me, pipe, q, vm); 1155 } 1156 1157 1158 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 1159 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 1160 .select_se_sh = &gfx_v10_0_select_se_sh, 1161 .read_wave_data = &gfx_v10_0_read_wave_data, 1162 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 1163 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 1164 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 1165 }; 1166 1167 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 1168 { 1169 u32 gb_addr_config; 1170 1171 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 1172 1173 switch (adev->asic_type) { 1174 case CHIP_NAVI10: 1175 case CHIP_NAVI14: 1176 case CHIP_NAVI12: 1177 adev->gfx.config.max_hw_contexts = 8; 1178 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1179 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1180 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1181 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1182 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1183 break; 1184 default: 1185 BUG(); 1186 break; 1187 } 1188 1189 adev->gfx.config.gb_addr_config = gb_addr_config; 1190 1191 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1192 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1193 GB_ADDR_CONFIG, NUM_PIPES); 1194 1195 adev->gfx.config.max_tile_pipes = 1196 adev->gfx.config.gb_addr_config_fields.num_pipes; 1197 1198 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1199 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1200 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 1201 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1202 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1203 GB_ADDR_CONFIG, NUM_RB_PER_SE); 1204 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1205 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1206 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 1207 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1208 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1209 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 1210 } 1211 1212 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1213 int me, int pipe, int queue) 1214 { 1215 int r; 1216 struct amdgpu_ring *ring; 1217 unsigned int irq_type; 1218 1219 ring = &adev->gfx.gfx_ring[ring_id]; 1220 1221 ring->me = me; 1222 ring->pipe = pipe; 1223 ring->queue = queue; 1224 1225 ring->ring_obj = NULL; 1226 ring->use_doorbell = true; 1227 1228 if (!ring_id) 1229 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1230 else 1231 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1232 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1233 1234 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1235 r = amdgpu_ring_init(adev, ring, 1024, 1236 &adev->gfx.eop_irq, irq_type); 1237 if (r) 1238 return r; 1239 return 0; 1240 } 1241 1242 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1243 int mec, int pipe, int queue) 1244 { 1245 int r; 1246 unsigned irq_type; 1247 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1248 1249 ring = &adev->gfx.compute_ring[ring_id]; 1250 1251 /* mec0 is me1 */ 1252 ring->me = mec + 1; 1253 ring->pipe = pipe; 1254 ring->queue = queue; 1255 1256 ring->ring_obj = NULL; 1257 ring->use_doorbell = true; 1258 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1259 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1260 + (ring_id * GFX10_MEC_HPD_SIZE); 1261 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1262 1263 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1264 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1265 + ring->pipe; 1266 1267 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1268 r = amdgpu_ring_init(adev, ring, 1024, 1269 &adev->gfx.eop_irq, irq_type); 1270 if (r) 1271 return r; 1272 1273 return 0; 1274 } 1275 1276 static int gfx_v10_0_sw_init(void *handle) 1277 { 1278 int i, j, k, r, ring_id = 0; 1279 struct amdgpu_kiq *kiq; 1280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1281 1282 switch (adev->asic_type) { 1283 case CHIP_NAVI10: 1284 case CHIP_NAVI14: 1285 case CHIP_NAVI12: 1286 adev->gfx.me.num_me = 1; 1287 adev->gfx.me.num_pipe_per_me = 2; 1288 adev->gfx.me.num_queue_per_pipe = 1; 1289 adev->gfx.mec.num_mec = 2; 1290 adev->gfx.mec.num_pipe_per_mec = 4; 1291 adev->gfx.mec.num_queue_per_pipe = 8; 1292 break; 1293 default: 1294 adev->gfx.me.num_me = 1; 1295 adev->gfx.me.num_pipe_per_me = 1; 1296 adev->gfx.me.num_queue_per_pipe = 1; 1297 adev->gfx.mec.num_mec = 1; 1298 adev->gfx.mec.num_pipe_per_mec = 4; 1299 adev->gfx.mec.num_queue_per_pipe = 8; 1300 break; 1301 } 1302 1303 /* KIQ event */ 1304 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1305 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 1306 &adev->gfx.kiq.irq); 1307 if (r) 1308 return r; 1309 1310 /* EOP Event */ 1311 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1312 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 1313 &adev->gfx.eop_irq); 1314 if (r) 1315 return r; 1316 1317 /* Privileged reg */ 1318 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 1319 &adev->gfx.priv_reg_irq); 1320 if (r) 1321 return r; 1322 1323 /* Privileged inst */ 1324 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 1325 &adev->gfx.priv_inst_irq); 1326 if (r) 1327 return r; 1328 1329 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1330 1331 gfx_v10_0_scratch_init(adev); 1332 1333 r = gfx_v10_0_me_init(adev); 1334 if (r) 1335 return r; 1336 1337 r = gfx_v10_0_rlc_init(adev); 1338 if (r) { 1339 DRM_ERROR("Failed to init rlc BOs!\n"); 1340 return r; 1341 } 1342 1343 r = gfx_v10_0_mec_init(adev); 1344 if (r) { 1345 DRM_ERROR("Failed to init MEC BOs!\n"); 1346 return r; 1347 } 1348 1349 /* set up the gfx ring */ 1350 for (i = 0; i < adev->gfx.me.num_me; i++) { 1351 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1352 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1353 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1354 continue; 1355 1356 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 1357 i, k, j); 1358 if (r) 1359 return r; 1360 ring_id++; 1361 } 1362 } 1363 } 1364 1365 ring_id = 0; 1366 /* set up the compute queues - allocate horizontally across pipes */ 1367 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1368 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1369 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1370 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1371 j)) 1372 continue; 1373 1374 r = gfx_v10_0_compute_ring_init(adev, ring_id, 1375 i, k, j); 1376 if (r) 1377 return r; 1378 1379 ring_id++; 1380 } 1381 } 1382 } 1383 1384 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 1385 if (r) { 1386 DRM_ERROR("Failed to init KIQ BOs!\n"); 1387 return r; 1388 } 1389 1390 kiq = &adev->gfx.kiq; 1391 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1392 if (r) 1393 return r; 1394 1395 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 1396 if (r) 1397 return r; 1398 1399 /* allocate visible FB for rlc auto-loading fw */ 1400 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1401 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 1402 if (r) 1403 return r; 1404 } 1405 1406 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 1407 1408 gfx_v10_0_gpu_early_init(adev); 1409 1410 return 0; 1411 } 1412 1413 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 1414 { 1415 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1416 &adev->gfx.pfp.pfp_fw_gpu_addr, 1417 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1418 } 1419 1420 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 1421 { 1422 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 1423 &adev->gfx.ce.ce_fw_gpu_addr, 1424 (void **)&adev->gfx.ce.ce_fw_ptr); 1425 } 1426 1427 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 1428 { 1429 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1430 &adev->gfx.me.me_fw_gpu_addr, 1431 (void **)&adev->gfx.me.me_fw_ptr); 1432 } 1433 1434 static int gfx_v10_0_sw_fini(void *handle) 1435 { 1436 int i; 1437 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1438 1439 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1440 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1441 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1442 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1443 1444 amdgpu_gfx_mqd_sw_fini(adev); 1445 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1446 amdgpu_gfx_kiq_fini(adev); 1447 1448 gfx_v10_0_pfp_fini(adev); 1449 gfx_v10_0_ce_fini(adev); 1450 gfx_v10_0_me_fini(adev); 1451 gfx_v10_0_rlc_fini(adev); 1452 gfx_v10_0_mec_fini(adev); 1453 1454 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1455 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 1456 1457 gfx_v10_0_free_microcode(adev); 1458 1459 return 0; 1460 } 1461 1462 1463 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev) 1464 { 1465 /* TODO */ 1466 } 1467 1468 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1469 u32 sh_num, u32 instance) 1470 { 1471 u32 data; 1472 1473 if (instance == 0xffffffff) 1474 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1475 INSTANCE_BROADCAST_WRITES, 1); 1476 else 1477 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1478 instance); 1479 1480 if (se_num == 0xffffffff) 1481 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1482 1); 1483 else 1484 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1485 1486 if (sh_num == 0xffffffff) 1487 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1488 1); 1489 else 1490 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1491 1492 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1493 } 1494 1495 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1496 { 1497 u32 data, mask; 1498 1499 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1500 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1501 1502 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1503 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1504 1505 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1506 adev->gfx.config.max_sh_per_se); 1507 1508 return (~data) & mask; 1509 } 1510 1511 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 1512 { 1513 int i, j; 1514 u32 data; 1515 u32 active_rbs = 0; 1516 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1517 adev->gfx.config.max_sh_per_se; 1518 1519 mutex_lock(&adev->grbm_idx_mutex); 1520 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1521 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1522 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1523 data = gfx_v10_0_get_rb_active_bitmap(adev); 1524 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1525 rb_bitmap_width_per_sh); 1526 } 1527 } 1528 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1529 mutex_unlock(&adev->grbm_idx_mutex); 1530 1531 adev->gfx.config.backend_enable_mask = active_rbs; 1532 adev->gfx.config.num_rbs = hweight32(active_rbs); 1533 } 1534 1535 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 1536 { 1537 uint32_t num_sc; 1538 uint32_t enabled_rb_per_sh; 1539 uint32_t active_rb_bitmap; 1540 uint32_t num_rb_per_sc; 1541 uint32_t num_packer_per_sc; 1542 uint32_t pa_sc_tile_steering_override; 1543 1544 /* init num_sc */ 1545 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 1546 adev->gfx.config.num_sc_per_sh; 1547 /* init num_rb_per_sc */ 1548 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 1549 enabled_rb_per_sh = hweight32(active_rb_bitmap); 1550 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 1551 /* init num_packer_per_sc */ 1552 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 1553 1554 pa_sc_tile_steering_override = 0; 1555 pa_sc_tile_steering_override |= 1556 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 1557 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 1558 pa_sc_tile_steering_override |= 1559 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 1560 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 1561 pa_sc_tile_steering_override |= 1562 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 1563 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 1564 1565 return pa_sc_tile_steering_override; 1566 } 1567 1568 #define DEFAULT_SH_MEM_BASES (0x6000) 1569 #define FIRST_COMPUTE_VMID (8) 1570 #define LAST_COMPUTE_VMID (16) 1571 1572 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 1573 { 1574 int i; 1575 uint32_t sh_mem_bases; 1576 1577 /* 1578 * Configure apertures: 1579 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1580 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1581 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1582 */ 1583 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1584 1585 mutex_lock(&adev->srbm_mutex); 1586 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1587 nv_grbm_select(adev, 0, 0, 0, i); 1588 /* CP and shaders */ 1589 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1590 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1591 } 1592 nv_grbm_select(adev, 0, 0, 0, 0); 1593 mutex_unlock(&adev->srbm_mutex); 1594 1595 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1596 acccess. These should be enabled by FW for target VMIDs. */ 1597 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1598 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 1599 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 1600 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 1601 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 1602 } 1603 } 1604 1605 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 1606 { 1607 int vmid; 1608 1609 /* 1610 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1611 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1612 * the driver can enable them for graphics. VMID0 should maintain 1613 * access so that HWS firmware can save/restore entries. 1614 */ 1615 for (vmid = 1; vmid < 16; vmid++) { 1616 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 1617 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 1618 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 1619 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 1620 } 1621 } 1622 1623 1624 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 1625 { 1626 int i, j, k; 1627 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 1628 u32 tmp, wgp_active_bitmap = 0; 1629 u32 gcrd_targets_disable_tcp = 0; 1630 u32 utcl_invreq_disable = 0; 1631 /* 1632 * GCRD_TARGETS_DISABLE field contains 1633 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 1634 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 1635 */ 1636 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 1637 2 * max_wgp_per_sh + /* TCP */ 1638 max_wgp_per_sh + /* SQC */ 1639 4); /* GL1C */ 1640 /* 1641 * UTCL1_UTCL0_INVREQ_DISABLE field contains 1642 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 1643 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 1644 */ 1645 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 1646 2 * max_wgp_per_sh + /* TCP */ 1647 2 * max_wgp_per_sh + /* SQC */ 1648 4 + /* RMI */ 1649 1); /* SQG */ 1650 1651 if (adev->asic_type == CHIP_NAVI10 || 1652 adev->asic_type == CHIP_NAVI14 || 1653 adev->asic_type == CHIP_NAVI12) { 1654 mutex_lock(&adev->grbm_idx_mutex); 1655 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1656 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1657 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1658 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 1659 /* 1660 * Set corresponding TCP bits for the inactive WGPs in 1661 * GCRD_SA_TARGETS_DISABLE 1662 */ 1663 gcrd_targets_disable_tcp = 0; 1664 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 1665 utcl_invreq_disable = 0; 1666 1667 for (k = 0; k < max_wgp_per_sh; k++) { 1668 if (!(wgp_active_bitmap & (1 << k))) { 1669 gcrd_targets_disable_tcp |= 3 << (2 * k); 1670 utcl_invreq_disable |= (3 << (2 * k)) | 1671 (3 << (2 * (max_wgp_per_sh + k))); 1672 } 1673 } 1674 1675 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 1676 /* only override TCP & SQC bits */ 1677 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 1678 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 1679 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 1680 1681 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 1682 /* only override TCP bits */ 1683 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 1684 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 1685 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 1686 } 1687 } 1688 1689 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1690 mutex_unlock(&adev->grbm_idx_mutex); 1691 } 1692 } 1693 1694 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 1695 { 1696 /* TCCs are global (not instanced). */ 1697 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 1698 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 1699 1700 adev->gfx.config.tcc_disabled_mask = 1701 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1702 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1703 } 1704 1705 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 1706 { 1707 u32 tmp; 1708 int i; 1709 1710 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1711 1712 gfx_v10_0_tiling_mode_table_init(adev); 1713 1714 gfx_v10_0_setup_rb(adev); 1715 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 1716 gfx_v10_0_get_tcc_info(adev); 1717 adev->gfx.config.pa_sc_tile_steering_override = 1718 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 1719 1720 /* XXX SH_MEM regs */ 1721 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1722 mutex_lock(&adev->srbm_mutex); 1723 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1724 nv_grbm_select(adev, 0, 0, 0, i); 1725 /* CP and shaders */ 1726 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1727 if (i != 0) { 1728 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1729 (adev->gmc.private_aperture_start >> 48)); 1730 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1731 (adev->gmc.shared_aperture_start >> 48)); 1732 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1733 } 1734 } 1735 nv_grbm_select(adev, 0, 0, 0, 0); 1736 1737 mutex_unlock(&adev->srbm_mutex); 1738 1739 gfx_v10_0_init_compute_vmid(adev); 1740 gfx_v10_0_init_gds_vmid(adev); 1741 1742 } 1743 1744 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1745 bool enable) 1746 { 1747 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1748 1749 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1750 enable ? 1 : 0); 1751 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1752 enable ? 1 : 0); 1753 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1754 enable ? 1 : 0); 1755 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1756 enable ? 1 : 0); 1757 1758 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1759 } 1760 1761 static void gfx_v10_0_init_csb(struct amdgpu_device *adev) 1762 { 1763 /* csib */ 1764 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 1765 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1766 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 1767 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1768 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1769 } 1770 1771 static void gfx_v10_0_init_pg(struct amdgpu_device *adev) 1772 { 1773 int i; 1774 1775 gfx_v10_0_init_csb(adev); 1776 1777 for (i = 0; i < adev->num_vmhubs; i++) 1778 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 1779 1780 /* TODO: init power gating */ 1781 return; 1782 } 1783 1784 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 1785 { 1786 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 1787 1788 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1789 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 1790 } 1791 1792 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 1793 { 1794 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1795 udelay(50); 1796 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1797 udelay(50); 1798 } 1799 1800 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1801 bool enable) 1802 { 1803 uint32_t rlc_pg_cntl; 1804 1805 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 1806 1807 if (!enable) { 1808 /* RLC_PG_CNTL[23] = 0 (default) 1809 * RLC will wait for handshake acks with SMU 1810 * GFXOFF will be enabled 1811 * RLC_PG_CNTL[23] = 1 1812 * RLC will not issue any message to SMU 1813 * hence no handshake between SMU & RLC 1814 * GFXOFF will be disabled 1815 */ 1816 rlc_pg_cntl |= 0x800000; 1817 } else 1818 rlc_pg_cntl &= ~0x800000; 1819 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 1820 } 1821 1822 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 1823 { 1824 /* TODO: enable rlc & smu handshake until smu 1825 * and gfxoff feature works as expected */ 1826 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1827 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 1828 1829 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1830 udelay(50); 1831 } 1832 1833 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 1834 { 1835 uint32_t tmp; 1836 1837 /* enable Save Restore Machine */ 1838 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1839 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1840 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1841 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1842 } 1843 1844 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 1845 { 1846 const struct rlc_firmware_header_v2_0 *hdr; 1847 const __le32 *fw_data; 1848 unsigned i, fw_size; 1849 1850 if (!adev->gfx.rlc_fw) 1851 return -EINVAL; 1852 1853 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1854 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1855 1856 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1857 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1858 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1859 1860 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 1861 RLCG_UCODE_LOADING_START_ADDRESS); 1862 1863 for (i = 0; i < fw_size; i++) 1864 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 1865 le32_to_cpup(fw_data++)); 1866 1867 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1868 1869 return 0; 1870 } 1871 1872 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 1873 { 1874 int r; 1875 1876 if (amdgpu_sriov_vf(adev)) 1877 return 0; 1878 1879 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1880 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1881 if (r) 1882 return r; 1883 gfx_v10_0_init_pg(adev); 1884 1885 /* enable RLC SRM */ 1886 gfx_v10_0_rlc_enable_srm(adev); 1887 1888 } else { 1889 adev->gfx.rlc.funcs->stop(adev); 1890 1891 /* disable CG */ 1892 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 1893 1894 /* disable PG */ 1895 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 1896 1897 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1898 /* legacy rlc firmware loading */ 1899 r = gfx_v10_0_rlc_load_microcode(adev); 1900 if (r) 1901 return r; 1902 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1903 /* rlc backdoor autoload firmware */ 1904 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 1905 if (r) 1906 return r; 1907 } 1908 1909 gfx_v10_0_init_pg(adev); 1910 adev->gfx.rlc.funcs->start(adev); 1911 1912 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1913 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1914 if (r) 1915 return r; 1916 } 1917 } 1918 return 0; 1919 } 1920 1921 static struct { 1922 FIRMWARE_ID id; 1923 unsigned int offset; 1924 unsigned int size; 1925 } rlc_autoload_info[FIRMWARE_ID_MAX]; 1926 1927 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 1928 { 1929 int ret; 1930 RLC_TABLE_OF_CONTENT *rlc_toc; 1931 1932 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 1933 AMDGPU_GEM_DOMAIN_GTT, 1934 &adev->gfx.rlc.rlc_toc_bo, 1935 &adev->gfx.rlc.rlc_toc_gpu_addr, 1936 (void **)&adev->gfx.rlc.rlc_toc_buf); 1937 if (ret) { 1938 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 1939 return ret; 1940 } 1941 1942 /* Copy toc from psp sos fw to rlc toc buffer */ 1943 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 1944 1945 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 1946 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 1947 (rlc_toc->id < FIRMWARE_ID_MAX)) { 1948 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 1949 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 1950 /* Offset needs 4KB alignment */ 1951 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 1952 } 1953 1954 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 1955 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 1956 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 1957 1958 rlc_toc++; 1959 }; 1960 1961 return 0; 1962 } 1963 1964 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 1965 { 1966 uint32_t total_size = 0; 1967 FIRMWARE_ID id; 1968 int ret; 1969 1970 ret = gfx_v10_0_parse_rlc_toc(adev); 1971 if (ret) { 1972 dev_err(adev->dev, "failed to parse rlc toc\n"); 1973 return 0; 1974 } 1975 1976 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 1977 total_size += rlc_autoload_info[id].size; 1978 1979 /* In case the offset in rlc toc ucode is aligned */ 1980 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 1981 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 1982 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 1983 1984 return total_size; 1985 } 1986 1987 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 1988 { 1989 int r; 1990 uint32_t total_size; 1991 1992 total_size = gfx_v10_0_calc_toc_total_size(adev); 1993 1994 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 1995 AMDGPU_GEM_DOMAIN_GTT, 1996 &adev->gfx.rlc.rlc_autoload_bo, 1997 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1998 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1999 if (r) { 2000 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 2001 return r; 2002 } 2003 2004 return 0; 2005 } 2006 2007 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 2008 { 2009 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 2010 &adev->gfx.rlc.rlc_toc_gpu_addr, 2011 (void **)&adev->gfx.rlc.rlc_toc_buf); 2012 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 2013 &adev->gfx.rlc.rlc_autoload_gpu_addr, 2014 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 2015 } 2016 2017 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 2018 FIRMWARE_ID id, 2019 const void *fw_data, 2020 uint32_t fw_size) 2021 { 2022 uint32_t toc_offset; 2023 uint32_t toc_fw_size; 2024 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 2025 2026 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 2027 return; 2028 2029 toc_offset = rlc_autoload_info[id].offset; 2030 toc_fw_size = rlc_autoload_info[id].size; 2031 2032 if (fw_size == 0) 2033 fw_size = toc_fw_size; 2034 2035 if (fw_size > toc_fw_size) 2036 fw_size = toc_fw_size; 2037 2038 memcpy(ptr + toc_offset, fw_data, fw_size); 2039 2040 if (fw_size < toc_fw_size) 2041 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 2042 } 2043 2044 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 2045 { 2046 void *data; 2047 uint32_t size; 2048 2049 data = adev->gfx.rlc.rlc_toc_buf; 2050 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 2051 2052 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2053 FIRMWARE_ID_RLC_TOC, 2054 data, size); 2055 } 2056 2057 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 2058 { 2059 const __le32 *fw_data; 2060 uint32_t fw_size; 2061 const struct gfx_firmware_header_v1_0 *cp_hdr; 2062 const struct rlc_firmware_header_v2_0 *rlc_hdr; 2063 2064 /* pfp ucode */ 2065 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2066 adev->gfx.pfp_fw->data; 2067 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2068 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2069 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2070 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2071 FIRMWARE_ID_CP_PFP, 2072 fw_data, fw_size); 2073 2074 /* ce ucode */ 2075 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2076 adev->gfx.ce_fw->data; 2077 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2078 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2079 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2080 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2081 FIRMWARE_ID_CP_CE, 2082 fw_data, fw_size); 2083 2084 /* me ucode */ 2085 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2086 adev->gfx.me_fw->data; 2087 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2088 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2089 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2090 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2091 FIRMWARE_ID_CP_ME, 2092 fw_data, fw_size); 2093 2094 /* rlc ucode */ 2095 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 2096 adev->gfx.rlc_fw->data; 2097 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2098 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 2099 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 2100 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2101 FIRMWARE_ID_RLC_G_UCODE, 2102 fw_data, fw_size); 2103 2104 /* mec1 ucode */ 2105 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2106 adev->gfx.mec_fw->data; 2107 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2108 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2109 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 2110 cp_hdr->jt_size * 4; 2111 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2112 FIRMWARE_ID_CP_MEC, 2113 fw_data, fw_size); 2114 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 2115 } 2116 2117 /* Temporarily put sdma part here */ 2118 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 2119 { 2120 const __le32 *fw_data; 2121 uint32_t fw_size; 2122 const struct sdma_firmware_header_v1_0 *sdma_hdr; 2123 int i; 2124 2125 for (i = 0; i < adev->sdma.num_instances; i++) { 2126 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 2127 adev->sdma.instance[i].fw->data; 2128 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 2129 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 2130 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 2131 2132 if (i == 0) { 2133 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2134 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 2135 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2136 FIRMWARE_ID_SDMA0_JT, 2137 (uint32_t *)fw_data + 2138 sdma_hdr->jt_offset, 2139 sdma_hdr->jt_size * 4); 2140 } else if (i == 1) { 2141 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2142 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 2143 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2144 FIRMWARE_ID_SDMA1_JT, 2145 (uint32_t *)fw_data + 2146 sdma_hdr->jt_offset, 2147 sdma_hdr->jt_size * 4); 2148 } 2149 } 2150 } 2151 2152 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 2153 { 2154 uint32_t rlc_g_offset, rlc_g_size, tmp; 2155 uint64_t gpu_addr; 2156 2157 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 2158 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 2159 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 2160 2161 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 2162 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 2163 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 2164 2165 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 2166 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 2167 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 2168 2169 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 2170 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 2171 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 2172 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 2173 return -EINVAL; 2174 } 2175 2176 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 2177 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2178 DRM_ERROR("RLC ROM should halt itself\n"); 2179 return -EINVAL; 2180 } 2181 2182 return 0; 2183 } 2184 2185 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 2186 { 2187 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2188 uint32_t tmp; 2189 int i; 2190 uint64_t addr; 2191 2192 /* Trigger an invalidation of the L1 instruction caches */ 2193 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2194 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2195 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2196 2197 /* Wait for invalidation complete */ 2198 for (i = 0; i < usec_timeout; i++) { 2199 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2200 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2201 INVALIDATE_CACHE_COMPLETE)) 2202 break; 2203 udelay(1); 2204 } 2205 2206 if (i >= usec_timeout) { 2207 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2208 return -EINVAL; 2209 } 2210 2211 /* Program me ucode address into intruction cache address register */ 2212 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2213 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 2214 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2215 lower_32_bits(addr) & 0xFFFFF000); 2216 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2217 upper_32_bits(addr)); 2218 2219 return 0; 2220 } 2221 2222 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 2223 { 2224 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2225 uint32_t tmp; 2226 int i; 2227 uint64_t addr; 2228 2229 /* Trigger an invalidation of the L1 instruction caches */ 2230 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2231 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2232 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2233 2234 /* Wait for invalidation complete */ 2235 for (i = 0; i < usec_timeout; i++) { 2236 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2237 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2238 INVALIDATE_CACHE_COMPLETE)) 2239 break; 2240 udelay(1); 2241 } 2242 2243 if (i >= usec_timeout) { 2244 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2245 return -EINVAL; 2246 } 2247 2248 /* Program ce ucode address into intruction cache address register */ 2249 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2250 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 2251 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2252 lower_32_bits(addr) & 0xFFFFF000); 2253 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2254 upper_32_bits(addr)); 2255 2256 return 0; 2257 } 2258 2259 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 2260 { 2261 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2262 uint32_t tmp; 2263 int i; 2264 uint64_t addr; 2265 2266 /* Trigger an invalidation of the L1 instruction caches */ 2267 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2268 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2269 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2270 2271 /* Wait for invalidation complete */ 2272 for (i = 0; i < usec_timeout; i++) { 2273 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2274 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2275 INVALIDATE_CACHE_COMPLETE)) 2276 break; 2277 udelay(1); 2278 } 2279 2280 if (i >= usec_timeout) { 2281 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2282 return -EINVAL; 2283 } 2284 2285 /* Program pfp ucode address into intruction cache address register */ 2286 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2287 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 2288 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2289 lower_32_bits(addr) & 0xFFFFF000); 2290 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2291 upper_32_bits(addr)); 2292 2293 return 0; 2294 } 2295 2296 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 2297 { 2298 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2299 uint32_t tmp; 2300 int i; 2301 uint64_t addr; 2302 2303 /* Trigger an invalidation of the L1 instruction caches */ 2304 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2305 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2306 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2307 2308 /* Wait for invalidation complete */ 2309 for (i = 0; i < usec_timeout; i++) { 2310 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2311 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2312 INVALIDATE_CACHE_COMPLETE)) 2313 break; 2314 udelay(1); 2315 } 2316 2317 if (i >= usec_timeout) { 2318 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2319 return -EINVAL; 2320 } 2321 2322 /* Program mec1 ucode address into intruction cache address register */ 2323 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2324 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 2325 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2326 lower_32_bits(addr) & 0xFFFFF000); 2327 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2328 upper_32_bits(addr)); 2329 2330 return 0; 2331 } 2332 2333 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2334 { 2335 uint32_t cp_status; 2336 uint32_t bootload_status; 2337 int i, r; 2338 2339 for (i = 0; i < adev->usec_timeout; i++) { 2340 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 2341 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 2342 if ((cp_status == 0) && 2343 (REG_GET_FIELD(bootload_status, 2344 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2345 break; 2346 } 2347 udelay(1); 2348 } 2349 2350 if (i >= adev->usec_timeout) { 2351 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2352 return -ETIMEDOUT; 2353 } 2354 2355 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2356 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 2357 if (r) 2358 return r; 2359 2360 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 2361 if (r) 2362 return r; 2363 2364 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 2365 if (r) 2366 return r; 2367 2368 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 2369 if (r) 2370 return r; 2371 } 2372 2373 return 0; 2374 } 2375 2376 static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2377 { 2378 int i; 2379 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2380 2381 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2382 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2383 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2384 if (!enable) { 2385 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2386 adev->gfx.gfx_ring[i].sched.ready = false; 2387 } 2388 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2389 udelay(50); 2390 } 2391 2392 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2393 { 2394 int r; 2395 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2396 const __le32 *fw_data; 2397 unsigned i, fw_size; 2398 uint32_t tmp; 2399 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2400 2401 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2402 adev->gfx.pfp_fw->data; 2403 2404 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2405 2406 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2407 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2408 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2409 2410 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2411 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2412 &adev->gfx.pfp.pfp_fw_obj, 2413 &adev->gfx.pfp.pfp_fw_gpu_addr, 2414 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2415 if (r) { 2416 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2417 gfx_v10_0_pfp_fini(adev); 2418 return r; 2419 } 2420 2421 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2422 2423 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2424 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2425 2426 /* Trigger an invalidation of the L1 instruction caches */ 2427 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2428 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2429 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2430 2431 /* Wait for invalidation complete */ 2432 for (i = 0; i < usec_timeout; i++) { 2433 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2434 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2435 INVALIDATE_CACHE_COMPLETE)) 2436 break; 2437 udelay(1); 2438 } 2439 2440 if (i >= usec_timeout) { 2441 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2442 return -EINVAL; 2443 } 2444 2445 if (amdgpu_emu_mode == 1) 2446 adev->nbio_funcs->hdp_flush(adev, NULL); 2447 2448 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 2449 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2450 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2451 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2452 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2453 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 2454 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2455 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 2456 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2457 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2458 2459 return 0; 2460 } 2461 2462 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 2463 { 2464 int r; 2465 const struct gfx_firmware_header_v1_0 *ce_hdr; 2466 const __le32 *fw_data; 2467 unsigned i, fw_size; 2468 uint32_t tmp; 2469 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2470 2471 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2472 adev->gfx.ce_fw->data; 2473 2474 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2475 2476 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2477 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2478 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 2479 2480 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 2481 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2482 &adev->gfx.ce.ce_fw_obj, 2483 &adev->gfx.ce.ce_fw_gpu_addr, 2484 (void **)&adev->gfx.ce.ce_fw_ptr); 2485 if (r) { 2486 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 2487 gfx_v10_0_ce_fini(adev); 2488 return r; 2489 } 2490 2491 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 2492 2493 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 2494 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 2495 2496 /* Trigger an invalidation of the L1 instruction caches */ 2497 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2498 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2499 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2500 2501 /* Wait for invalidation complete */ 2502 for (i = 0; i < usec_timeout; i++) { 2503 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2504 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2505 INVALIDATE_CACHE_COMPLETE)) 2506 break; 2507 udelay(1); 2508 } 2509 2510 if (i >= usec_timeout) { 2511 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2512 return -EINVAL; 2513 } 2514 2515 if (amdgpu_emu_mode == 1) 2516 adev->nbio_funcs->hdp_flush(adev, NULL); 2517 2518 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 2519 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 2520 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 2521 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 2522 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2523 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2524 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 2525 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2526 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 2527 2528 return 0; 2529 } 2530 2531 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2532 { 2533 int r; 2534 const struct gfx_firmware_header_v1_0 *me_hdr; 2535 const __le32 *fw_data; 2536 unsigned i, fw_size; 2537 uint32_t tmp; 2538 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2539 2540 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2541 adev->gfx.me_fw->data; 2542 2543 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2544 2545 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2546 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2547 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2548 2549 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2550 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2551 &adev->gfx.me.me_fw_obj, 2552 &adev->gfx.me.me_fw_gpu_addr, 2553 (void **)&adev->gfx.me.me_fw_ptr); 2554 if (r) { 2555 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2556 gfx_v10_0_me_fini(adev); 2557 return r; 2558 } 2559 2560 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2561 2562 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2563 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2564 2565 /* Trigger an invalidation of the L1 instruction caches */ 2566 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2567 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2568 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2569 2570 /* Wait for invalidation complete */ 2571 for (i = 0; i < usec_timeout; i++) { 2572 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2573 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2574 INVALIDATE_CACHE_COMPLETE)) 2575 break; 2576 udelay(1); 2577 } 2578 2579 if (i >= usec_timeout) { 2580 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2581 return -EINVAL; 2582 } 2583 2584 if (amdgpu_emu_mode == 1) 2585 adev->nbio_funcs->hdp_flush(adev, NULL); 2586 2587 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 2588 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2589 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2590 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2591 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2592 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2593 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 2594 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2595 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2596 2597 return 0; 2598 } 2599 2600 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2601 { 2602 int r; 2603 2604 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2605 return -EINVAL; 2606 2607 gfx_v10_0_cp_gfx_enable(adev, false); 2608 2609 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 2610 if (r) { 2611 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2612 return r; 2613 } 2614 2615 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 2616 if (r) { 2617 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 2618 return r; 2619 } 2620 2621 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 2622 if (r) { 2623 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2624 return r; 2625 } 2626 2627 return 0; 2628 } 2629 2630 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 2631 { 2632 struct amdgpu_ring *ring; 2633 const struct cs_section_def *sect = NULL; 2634 const struct cs_extent_def *ext = NULL; 2635 int r, i; 2636 int ctx_reg_offset; 2637 2638 /* init the CP */ 2639 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 2640 adev->gfx.config.max_hw_contexts - 1); 2641 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2642 2643 gfx_v10_0_cp_gfx_enable(adev, true); 2644 2645 ring = &adev->gfx.gfx_ring[0]; 2646 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 2647 if (r) { 2648 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2649 return r; 2650 } 2651 2652 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2653 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2654 2655 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2656 amdgpu_ring_write(ring, 0x80000000); 2657 amdgpu_ring_write(ring, 0x80000000); 2658 2659 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 2660 for (ext = sect->section; ext->extent != NULL; ++ext) { 2661 if (sect->id == SECT_CONTEXT) { 2662 amdgpu_ring_write(ring, 2663 PACKET3(PACKET3_SET_CONTEXT_REG, 2664 ext->reg_count)); 2665 amdgpu_ring_write(ring, ext->reg_index - 2666 PACKET3_SET_CONTEXT_REG_START); 2667 for (i = 0; i < ext->reg_count; i++) 2668 amdgpu_ring_write(ring, ext->extent[i]); 2669 } 2670 } 2671 } 2672 2673 ctx_reg_offset = 2674 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 2675 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2676 amdgpu_ring_write(ring, ctx_reg_offset); 2677 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 2678 2679 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2680 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2681 2682 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2683 amdgpu_ring_write(ring, 0); 2684 2685 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2686 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2687 amdgpu_ring_write(ring, 0x8000); 2688 amdgpu_ring_write(ring, 0x8000); 2689 2690 amdgpu_ring_commit(ring); 2691 2692 /* submit cs packet to copy state 0 to next available state */ 2693 ring = &adev->gfx.gfx_ring[1]; 2694 r = amdgpu_ring_alloc(ring, 2); 2695 if (r) { 2696 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2697 return r; 2698 } 2699 2700 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2701 amdgpu_ring_write(ring, 0); 2702 2703 amdgpu_ring_commit(ring); 2704 2705 return 0; 2706 } 2707 2708 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2709 CP_PIPE_ID pipe) 2710 { 2711 u32 tmp; 2712 2713 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 2714 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2715 2716 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 2717 } 2718 2719 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2720 struct amdgpu_ring *ring) 2721 { 2722 u32 tmp; 2723 2724 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2725 if (ring->use_doorbell) { 2726 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2727 DOORBELL_OFFSET, ring->doorbell_index); 2728 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2729 DOORBELL_EN, 1); 2730 } else { 2731 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2732 DOORBELL_EN, 0); 2733 } 2734 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2735 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2736 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2737 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2738 2739 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2740 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2741 } 2742 2743 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 2744 { 2745 struct amdgpu_ring *ring; 2746 u32 tmp; 2747 u32 rb_bufsz; 2748 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2749 u32 i; 2750 2751 /* Set the write pointer delay */ 2752 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2753 2754 /* set the RB to use vmid 0 */ 2755 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2756 2757 /* Init gfx ring 0 for pipe 0 */ 2758 mutex_lock(&adev->srbm_mutex); 2759 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2760 mutex_unlock(&adev->srbm_mutex); 2761 /* Set ring buffer size */ 2762 ring = &adev->gfx.gfx_ring[0]; 2763 rb_bufsz = order_base_2(ring->ring_size / 8); 2764 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2765 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2766 #ifdef __BIG_ENDIAN 2767 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2768 #endif 2769 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2770 2771 /* Initialize the ring buffer's write pointers */ 2772 ring->wptr = 0; 2773 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2774 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2775 2776 /* set the wb address wether it's enabled or not */ 2777 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2778 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2779 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2780 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2781 2782 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2783 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2784 lower_32_bits(wptr_gpu_addr)); 2785 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2786 upper_32_bits(wptr_gpu_addr)); 2787 2788 mdelay(1); 2789 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2790 2791 rb_addr = ring->gpu_addr >> 8; 2792 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2793 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2794 2795 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 2796 2797 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2798 2799 /* Init gfx ring 1 for pipe 1 */ 2800 mutex_lock(&adev->srbm_mutex); 2801 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 2802 mutex_unlock(&adev->srbm_mutex); 2803 ring = &adev->gfx.gfx_ring[1]; 2804 rb_bufsz = order_base_2(ring->ring_size / 8); 2805 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 2806 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 2807 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2808 /* Initialize the ring buffer's write pointers */ 2809 ring->wptr = 0; 2810 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2811 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 2812 /* Set the wb address wether it's enabled or not */ 2813 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2814 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2815 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2816 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2817 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2818 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2819 lower_32_bits(wptr_gpu_addr)); 2820 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2821 upper_32_bits(wptr_gpu_addr)); 2822 2823 mdelay(1); 2824 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2825 2826 rb_addr = ring->gpu_addr >> 8; 2827 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 2828 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 2829 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 2830 2831 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2832 2833 /* Switch to pipe 0 */ 2834 mutex_lock(&adev->srbm_mutex); 2835 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2836 mutex_unlock(&adev->srbm_mutex); 2837 2838 /* start the ring */ 2839 gfx_v10_0_cp_gfx_start(adev); 2840 2841 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2842 ring = &adev->gfx.gfx_ring[i]; 2843 ring->sched.ready = true; 2844 } 2845 2846 return 0; 2847 } 2848 2849 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2850 { 2851 int i; 2852 2853 if (enable) { 2854 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2855 } else { 2856 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2857 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 2858 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2859 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2860 adev->gfx.compute_ring[i].sched.ready = false; 2861 adev->gfx.kiq.ring.sched.ready = false; 2862 } 2863 udelay(50); 2864 } 2865 2866 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2867 { 2868 const struct gfx_firmware_header_v1_0 *mec_hdr; 2869 const __le32 *fw_data; 2870 unsigned i; 2871 u32 tmp; 2872 u32 usec_timeout = 50000; /* Wait for 50 ms */ 2873 2874 if (!adev->gfx.mec_fw) 2875 return -EINVAL; 2876 2877 gfx_v10_0_cp_compute_enable(adev, false); 2878 2879 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2880 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2881 2882 fw_data = (const __le32 *) 2883 (adev->gfx.mec_fw->data + 2884 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2885 2886 /* Trigger an invalidation of the L1 instruction caches */ 2887 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2888 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2889 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2890 2891 /* Wait for invalidation complete */ 2892 for (i = 0; i < usec_timeout; i++) { 2893 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2894 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2895 INVALIDATE_CACHE_COMPLETE)) 2896 break; 2897 udelay(1); 2898 } 2899 2900 if (i >= usec_timeout) { 2901 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2902 return -EINVAL; 2903 } 2904 2905 if (amdgpu_emu_mode == 1) 2906 adev->nbio_funcs->hdp_flush(adev, NULL); 2907 2908 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 2909 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2910 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2911 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2912 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2913 2914 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 2915 0xFFFFF000); 2916 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2917 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2918 2919 /* MEC1 */ 2920 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 2921 2922 for (i = 0; i < mec_hdr->jt_size; i++) 2923 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2924 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2925 2926 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 2927 2928 /* 2929 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 2930 * different microcode than MEC1. 2931 */ 2932 2933 return 0; 2934 } 2935 2936 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 2937 { 2938 uint32_t tmp; 2939 struct amdgpu_device *adev = ring->adev; 2940 2941 /* tell RLC which is KIQ queue */ 2942 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2943 tmp &= 0xffffff00; 2944 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2945 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2946 tmp |= 0x80; 2947 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2948 } 2949 2950 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 2951 { 2952 struct amdgpu_device *adev = ring->adev; 2953 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 2954 uint64_t hqd_gpu_addr, wb_gpu_addr; 2955 uint32_t tmp; 2956 uint32_t rb_bufsz; 2957 2958 /* set up gfx hqd wptr */ 2959 mqd->cp_gfx_hqd_wptr = 0; 2960 mqd->cp_gfx_hqd_wptr_hi = 0; 2961 2962 /* set the pointer to the MQD */ 2963 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 2964 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2965 2966 /* set up mqd control */ 2967 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 2968 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2969 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2970 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2971 mqd->cp_gfx_mqd_control = tmp; 2972 2973 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2974 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 2975 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2976 mqd->cp_gfx_hqd_vmid = 0; 2977 2978 /* set up default queue priority level 2979 * 0x0 = low priority, 0x1 = high priority */ 2980 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 2981 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2982 mqd->cp_gfx_hqd_queue_priority = tmp; 2983 2984 /* set up time quantum */ 2985 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 2986 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2987 mqd->cp_gfx_hqd_quantum = tmp; 2988 2989 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2990 hqd_gpu_addr = ring->gpu_addr >> 8; 2991 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2992 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2993 2994 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2995 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2996 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2997 mqd->cp_gfx_hqd_rptr_addr_hi = 2998 upper_32_bits(wb_gpu_addr) & 0xffff; 2999 3000 /* set up rb_wptr_poll addr */ 3001 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3002 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3003 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3004 3005 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3006 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 3007 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 3008 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3009 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3010 #ifdef __BIG_ENDIAN 3011 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3012 #endif 3013 mqd->cp_gfx_hqd_cntl = tmp; 3014 3015 /* set up cp_doorbell_control */ 3016 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3017 if (ring->use_doorbell) { 3018 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3019 DOORBELL_OFFSET, ring->doorbell_index); 3020 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3021 DOORBELL_EN, 1); 3022 } else 3023 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3024 DOORBELL_EN, 0); 3025 mqd->cp_rb_doorbell_control = tmp; 3026 3027 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3028 ring->wptr = 0; 3029 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 3030 3031 /* active the queue */ 3032 mqd->cp_gfx_hqd_active = 1; 3033 3034 return 0; 3035 } 3036 3037 #ifdef BRING_UP_DEBUG 3038 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3039 { 3040 struct amdgpu_device *adev = ring->adev; 3041 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3042 3043 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3044 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3045 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3046 3047 /* set GFX_MQD_BASE */ 3048 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3049 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3050 3051 /* set GFX_MQD_CONTROL */ 3052 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3053 3054 /* set GFX_HQD_VMID to 0 */ 3055 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3056 3057 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 3058 mqd->cp_gfx_hqd_queue_priority); 3059 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3060 3061 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3062 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3063 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3064 3065 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3066 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3067 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3068 3069 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3070 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3071 3072 /* set RB_WPTR_POLL_ADDR */ 3073 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3074 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3075 3076 /* set RB_DOORBELL_CONTROL */ 3077 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3078 3079 /* active the queue */ 3080 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3081 3082 return 0; 3083 } 3084 #endif 3085 3086 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 3087 { 3088 struct amdgpu_device *adev = ring->adev; 3089 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3090 3091 if (!adev->in_gpu_reset && !adev->in_suspend) { 3092 memset((void *)mqd, 0, sizeof(*mqd)); 3093 mutex_lock(&adev->srbm_mutex); 3094 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3095 gfx_v10_0_gfx_mqd_init(ring); 3096 #ifdef BRING_UP_DEBUG 3097 gfx_v10_0_gfx_queue_init_register(ring); 3098 #endif 3099 nv_grbm_select(adev, 0, 0, 0, 0); 3100 mutex_unlock(&adev->srbm_mutex); 3101 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]) 3102 memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd)); 3103 } else if (adev->in_gpu_reset) { 3104 /* reset mqd with the backup copy */ 3105 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]) 3106 memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd)); 3107 /* reset the ring */ 3108 ring->wptr = 0; 3109 amdgpu_ring_clear_ring(ring); 3110 #ifdef BRING_UP_DEBUG 3111 mutex_lock(&adev->srbm_mutex); 3112 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3113 gfx_v10_0_gfx_queue_init_register(ring); 3114 nv_grbm_select(adev, 0, 0, 0, 0); 3115 mutex_unlock(&adev->srbm_mutex); 3116 #endif 3117 } else { 3118 amdgpu_ring_clear_ring(ring); 3119 } 3120 3121 return 0; 3122 } 3123 3124 #ifndef BRING_UP_DEBUG 3125 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 3126 { 3127 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3128 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3129 int r, i; 3130 3131 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3132 return -EINVAL; 3133 3134 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3135 adev->gfx.num_gfx_rings); 3136 if (r) { 3137 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3138 return r; 3139 } 3140 3141 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3142 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3143 3144 r = amdgpu_ring_test_ring(kiq_ring); 3145 if (r) { 3146 DRM_ERROR("kfq enable failed\n"); 3147 kiq_ring->sched.ready = false; 3148 } 3149 return r; 3150 } 3151 #endif 3152 3153 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3154 { 3155 int r, i; 3156 struct amdgpu_ring *ring; 3157 3158 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3159 ring = &adev->gfx.gfx_ring[i]; 3160 3161 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3162 if (unlikely(r != 0)) 3163 goto done; 3164 3165 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3166 if (!r) { 3167 r = gfx_v10_0_gfx_init_queue(ring); 3168 amdgpu_bo_kunmap(ring->mqd_obj); 3169 ring->mqd_ptr = NULL; 3170 } 3171 amdgpu_bo_unreserve(ring->mqd_obj); 3172 if (r) 3173 goto done; 3174 } 3175 #ifndef BRING_UP_DEBUG 3176 r = gfx_v10_0_kiq_enable_kgq(adev); 3177 if (r) 3178 goto done; 3179 #endif 3180 r = gfx_v10_0_cp_gfx_start(adev); 3181 if (r) 3182 goto done; 3183 3184 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3185 ring = &adev->gfx.gfx_ring[i]; 3186 ring->sched.ready = true; 3187 } 3188 done: 3189 return r; 3190 } 3191 3192 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 3193 { 3194 struct amdgpu_device *adev = ring->adev; 3195 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3196 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3197 uint32_t tmp; 3198 3199 mqd->header = 0xC0310800; 3200 mqd->compute_pipelinestat_enable = 0x00000001; 3201 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3202 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3203 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3204 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3205 mqd->compute_misc_reserved = 0x00000003; 3206 3207 eop_base_addr = ring->eop_gpu_addr >> 8; 3208 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3209 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3210 3211 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3212 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3213 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3214 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 3215 3216 mqd->cp_hqd_eop_control = tmp; 3217 3218 /* enable doorbell? */ 3219 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3220 3221 if (ring->use_doorbell) { 3222 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3223 DOORBELL_OFFSET, ring->doorbell_index); 3224 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3225 DOORBELL_EN, 1); 3226 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3227 DOORBELL_SOURCE, 0); 3228 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3229 DOORBELL_HIT, 0); 3230 } else { 3231 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3232 DOORBELL_EN, 0); 3233 } 3234 3235 mqd->cp_hqd_pq_doorbell_control = tmp; 3236 3237 /* disable the queue if it's active */ 3238 ring->wptr = 0; 3239 mqd->cp_hqd_dequeue_request = 0; 3240 mqd->cp_hqd_pq_rptr = 0; 3241 mqd->cp_hqd_pq_wptr_lo = 0; 3242 mqd->cp_hqd_pq_wptr_hi = 0; 3243 3244 /* set the pointer to the MQD */ 3245 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3246 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3247 3248 /* set MQD vmid to 0 */ 3249 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3250 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3251 mqd->cp_mqd_control = tmp; 3252 3253 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3254 hqd_gpu_addr = ring->gpu_addr >> 8; 3255 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3256 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3257 3258 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3259 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3260 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3261 (order_base_2(ring->ring_size / 4) - 1)); 3262 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3263 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3264 #ifdef __BIG_ENDIAN 3265 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3266 #endif 3267 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3268 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3269 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3270 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3271 mqd->cp_hqd_pq_control = tmp; 3272 3273 /* set the wb address whether it's enabled or not */ 3274 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3275 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3276 mqd->cp_hqd_pq_rptr_report_addr_hi = 3277 upper_32_bits(wb_gpu_addr) & 0xffff; 3278 3279 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3280 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3281 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3282 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3283 3284 tmp = 0; 3285 /* enable the doorbell if requested */ 3286 if (ring->use_doorbell) { 3287 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3288 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3289 DOORBELL_OFFSET, ring->doorbell_index); 3290 3291 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3292 DOORBELL_EN, 1); 3293 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3294 DOORBELL_SOURCE, 0); 3295 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3296 DOORBELL_HIT, 0); 3297 } 3298 3299 mqd->cp_hqd_pq_doorbell_control = tmp; 3300 3301 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3302 ring->wptr = 0; 3303 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3304 3305 /* set the vmid for the queue */ 3306 mqd->cp_hqd_vmid = 0; 3307 3308 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3309 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3310 mqd->cp_hqd_persistent_state = tmp; 3311 3312 /* set MIN_IB_AVAIL_SIZE */ 3313 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3314 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3315 mqd->cp_hqd_ib_control = tmp; 3316 3317 /* activate the queue */ 3318 mqd->cp_hqd_active = 1; 3319 3320 return 0; 3321 } 3322 3323 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 3324 { 3325 struct amdgpu_device *adev = ring->adev; 3326 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3327 int j; 3328 3329 /* disable wptr polling */ 3330 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3331 3332 /* write the EOP addr */ 3333 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3334 mqd->cp_hqd_eop_base_addr_lo); 3335 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3336 mqd->cp_hqd_eop_base_addr_hi); 3337 3338 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3339 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 3340 mqd->cp_hqd_eop_control); 3341 3342 /* enable doorbell? */ 3343 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3344 mqd->cp_hqd_pq_doorbell_control); 3345 3346 /* disable the queue if it's active */ 3347 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3348 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3349 for (j = 0; j < adev->usec_timeout; j++) { 3350 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3351 break; 3352 udelay(1); 3353 } 3354 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3355 mqd->cp_hqd_dequeue_request); 3356 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 3357 mqd->cp_hqd_pq_rptr); 3358 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3359 mqd->cp_hqd_pq_wptr_lo); 3360 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3361 mqd->cp_hqd_pq_wptr_hi); 3362 } 3363 3364 /* set the pointer to the MQD */ 3365 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 3366 mqd->cp_mqd_base_addr_lo); 3367 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3368 mqd->cp_mqd_base_addr_hi); 3369 3370 /* set MQD vmid to 0 */ 3371 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 3372 mqd->cp_mqd_control); 3373 3374 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3375 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 3376 mqd->cp_hqd_pq_base_lo); 3377 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 3378 mqd->cp_hqd_pq_base_hi); 3379 3380 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3381 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 3382 mqd->cp_hqd_pq_control); 3383 3384 /* set the wb address whether it's enabled or not */ 3385 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3386 mqd->cp_hqd_pq_rptr_report_addr_lo); 3387 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3388 mqd->cp_hqd_pq_rptr_report_addr_hi); 3389 3390 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3391 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3392 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3393 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3394 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3395 3396 /* enable the doorbell if requested */ 3397 if (ring->use_doorbell) { 3398 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3399 (adev->doorbell_index.kiq * 2) << 2); 3400 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3401 (adev->doorbell_index.userqueue_end * 2) << 2); 3402 } 3403 3404 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3405 mqd->cp_hqd_pq_doorbell_control); 3406 3407 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3408 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3409 mqd->cp_hqd_pq_wptr_lo); 3410 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3411 mqd->cp_hqd_pq_wptr_hi); 3412 3413 /* set the vmid for the queue */ 3414 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3415 3416 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3417 mqd->cp_hqd_persistent_state); 3418 3419 /* activate the queue */ 3420 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 3421 mqd->cp_hqd_active); 3422 3423 if (ring->use_doorbell) 3424 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3425 3426 return 0; 3427 } 3428 3429 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 3430 { 3431 struct amdgpu_device *adev = ring->adev; 3432 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3433 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3434 3435 gfx_v10_0_kiq_setting(ring); 3436 3437 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3438 /* reset MQD to a clean status */ 3439 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3440 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3441 3442 /* reset ring buffer */ 3443 ring->wptr = 0; 3444 amdgpu_ring_clear_ring(ring); 3445 3446 mutex_lock(&adev->srbm_mutex); 3447 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3448 gfx_v10_0_kiq_init_register(ring); 3449 nv_grbm_select(adev, 0, 0, 0, 0); 3450 mutex_unlock(&adev->srbm_mutex); 3451 } else { 3452 memset((void *)mqd, 0, sizeof(*mqd)); 3453 mutex_lock(&adev->srbm_mutex); 3454 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3455 gfx_v10_0_compute_mqd_init(ring); 3456 gfx_v10_0_kiq_init_register(ring); 3457 nv_grbm_select(adev, 0, 0, 0, 0); 3458 mutex_unlock(&adev->srbm_mutex); 3459 3460 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3461 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3462 } 3463 3464 return 0; 3465 } 3466 3467 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 3468 { 3469 struct amdgpu_device *adev = ring->adev; 3470 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3471 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3472 3473 if (!adev->in_gpu_reset && !adev->in_suspend) { 3474 memset((void *)mqd, 0, sizeof(*mqd)); 3475 mutex_lock(&adev->srbm_mutex); 3476 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3477 gfx_v10_0_compute_mqd_init(ring); 3478 nv_grbm_select(adev, 0, 0, 0, 0); 3479 mutex_unlock(&adev->srbm_mutex); 3480 3481 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3482 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3483 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3484 /* reset MQD to a clean status */ 3485 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3486 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3487 3488 /* reset ring buffer */ 3489 ring->wptr = 0; 3490 amdgpu_ring_clear_ring(ring); 3491 } else { 3492 amdgpu_ring_clear_ring(ring); 3493 } 3494 3495 return 0; 3496 } 3497 3498 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 3499 { 3500 struct amdgpu_ring *ring; 3501 int r; 3502 3503 ring = &adev->gfx.kiq.ring; 3504 3505 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3506 if (unlikely(r != 0)) 3507 return r; 3508 3509 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3510 if (unlikely(r != 0)) 3511 return r; 3512 3513 gfx_v10_0_kiq_init_queue(ring); 3514 amdgpu_bo_kunmap(ring->mqd_obj); 3515 ring->mqd_ptr = NULL; 3516 amdgpu_bo_unreserve(ring->mqd_obj); 3517 ring->sched.ready = true; 3518 return 0; 3519 } 3520 3521 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 3522 { 3523 struct amdgpu_ring *ring = NULL; 3524 int r = 0, i; 3525 3526 gfx_v10_0_cp_compute_enable(adev, true); 3527 3528 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3529 ring = &adev->gfx.compute_ring[i]; 3530 3531 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3532 if (unlikely(r != 0)) 3533 goto done; 3534 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3535 if (!r) { 3536 r = gfx_v10_0_kcq_init_queue(ring); 3537 amdgpu_bo_kunmap(ring->mqd_obj); 3538 ring->mqd_ptr = NULL; 3539 } 3540 amdgpu_bo_unreserve(ring->mqd_obj); 3541 if (r) 3542 goto done; 3543 } 3544 3545 r = amdgpu_gfx_enable_kcq(adev); 3546 done: 3547 return r; 3548 } 3549 3550 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 3551 { 3552 int r, i; 3553 struct amdgpu_ring *ring; 3554 3555 if (!(adev->flags & AMD_IS_APU)) 3556 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3557 3558 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3559 /* legacy firmware loading */ 3560 r = gfx_v10_0_cp_gfx_load_microcode(adev); 3561 if (r) 3562 return r; 3563 3564 r = gfx_v10_0_cp_compute_load_microcode(adev); 3565 if (r) 3566 return r; 3567 } 3568 3569 r = gfx_v10_0_kiq_resume(adev); 3570 if (r) 3571 return r; 3572 3573 r = gfx_v10_0_kcq_resume(adev); 3574 if (r) 3575 return r; 3576 3577 if (!amdgpu_async_gfx_ring) { 3578 r = gfx_v10_0_cp_gfx_resume(adev); 3579 if (r) 3580 return r; 3581 } else { 3582 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 3583 if (r) 3584 return r; 3585 } 3586 3587 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3588 ring = &adev->gfx.gfx_ring[i]; 3589 DRM_INFO("gfx %d ring me %d pipe %d q %d\n", 3590 i, ring->me, ring->pipe, ring->queue); 3591 r = amdgpu_ring_test_ring(ring); 3592 if (r) { 3593 ring->sched.ready = false; 3594 return r; 3595 } 3596 } 3597 3598 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3599 ring = &adev->gfx.compute_ring[i]; 3600 ring->sched.ready = true; 3601 DRM_INFO("compute ring %d mec %d pipe %d q %d\n", 3602 i, ring->me, ring->pipe, ring->queue); 3603 r = amdgpu_ring_test_ring(ring); 3604 if (r) 3605 ring->sched.ready = false; 3606 } 3607 3608 return 0; 3609 } 3610 3611 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 3612 { 3613 gfx_v10_0_cp_gfx_enable(adev, enable); 3614 gfx_v10_0_cp_compute_enable(adev, enable); 3615 } 3616 3617 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 3618 { 3619 uint32_t data, pattern = 0xDEADBEEF; 3620 3621 /* check if mmVGT_ESGS_RING_SIZE_UMD 3622 * has been remapped to mmVGT_ESGS_RING_SIZE */ 3623 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 3624 3625 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 3626 3627 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 3628 3629 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 3630 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 3631 return true; 3632 } else { 3633 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 3634 return false; 3635 } 3636 } 3637 3638 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 3639 { 3640 uint32_t data; 3641 3642 /* initialize cam_index to 0 3643 * index will auto-inc after each data writting */ 3644 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 3645 3646 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 3647 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 3648 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3649 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 3650 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3651 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3652 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3653 3654 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 3655 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 3656 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3657 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 3658 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3659 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3660 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3661 3662 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 3663 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 3664 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3665 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 3666 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3667 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3668 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3669 3670 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 3671 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 3672 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3673 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 3674 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3675 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3676 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3677 3678 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 3679 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 3680 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3681 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 3682 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3683 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3684 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3685 3686 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 3687 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 3688 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3689 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 3690 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3691 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3692 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3693 3694 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 3695 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 3696 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3697 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 3698 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3699 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3700 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3701 } 3702 3703 static int gfx_v10_0_hw_init(void *handle) 3704 { 3705 int r; 3706 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3707 3708 r = gfx_v10_0_csb_vram_pin(adev); 3709 if (r) 3710 return r; 3711 3712 if (!amdgpu_emu_mode) 3713 gfx_v10_0_init_golden_registers(adev); 3714 3715 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3716 /** 3717 * For gfx 10, rlc firmware loading relies on smu firmware is 3718 * loaded firstly, so in direct type, it has to load smc ucode 3719 * here before rlc. 3720 */ 3721 r = smu_load_microcode(&adev->smu); 3722 if (r) 3723 return r; 3724 3725 r = smu_check_fw_status(&adev->smu); 3726 if (r) { 3727 pr_err("SMC firmware status is not correct\n"); 3728 return r; 3729 } 3730 } 3731 3732 /* if GRBM CAM not remapped, set up the remapping */ 3733 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 3734 gfx_v10_0_setup_grbm_cam_remapping(adev); 3735 3736 gfx_v10_0_constants_init(adev); 3737 3738 r = gfx_v10_0_rlc_resume(adev); 3739 if (r) 3740 return r; 3741 3742 /* 3743 * init golden registers and rlc resume may override some registers, 3744 * reconfig them here 3745 */ 3746 gfx_v10_0_tcp_harvest(adev); 3747 3748 r = gfx_v10_0_cp_resume(adev); 3749 if (r) 3750 return r; 3751 3752 return r; 3753 } 3754 3755 #ifndef BRING_UP_DEBUG 3756 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 3757 { 3758 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3759 struct amdgpu_ring *kiq_ring = &kiq->ring; 3760 int i; 3761 3762 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3763 return -EINVAL; 3764 3765 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 3766 adev->gfx.num_gfx_rings)) 3767 return -ENOMEM; 3768 3769 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3770 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 3771 PREEMPT_QUEUES, 0, 0); 3772 3773 return amdgpu_ring_test_ring(kiq_ring); 3774 } 3775 #endif 3776 3777 static int gfx_v10_0_hw_fini(void *handle) 3778 { 3779 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3780 int r; 3781 3782 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3783 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3784 #ifndef BRING_UP_DEBUG 3785 if (amdgpu_async_gfx_ring) { 3786 r = gfx_v10_0_kiq_disable_kgq(adev); 3787 if (r) 3788 DRM_ERROR("KGQ disable failed\n"); 3789 } 3790 #endif 3791 if (amdgpu_gfx_disable_kcq(adev)) 3792 DRM_ERROR("KCQ disable failed\n"); 3793 if (amdgpu_sriov_vf(adev)) { 3794 pr_debug("For SRIOV client, shouldn't do anything.\n"); 3795 return 0; 3796 } 3797 gfx_v10_0_cp_enable(adev, false); 3798 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3799 gfx_v10_0_csb_vram_unpin(adev); 3800 3801 return 0; 3802 } 3803 3804 static int gfx_v10_0_suspend(void *handle) 3805 { 3806 return gfx_v10_0_hw_fini(handle); 3807 } 3808 3809 static int gfx_v10_0_resume(void *handle) 3810 { 3811 return gfx_v10_0_hw_init(handle); 3812 } 3813 3814 static bool gfx_v10_0_is_idle(void *handle) 3815 { 3816 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3817 3818 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3819 GRBM_STATUS, GUI_ACTIVE)) 3820 return false; 3821 else 3822 return true; 3823 } 3824 3825 static int gfx_v10_0_wait_for_idle(void *handle) 3826 { 3827 unsigned i; 3828 u32 tmp; 3829 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3830 3831 for (i = 0; i < adev->usec_timeout; i++) { 3832 /* read MC_STATUS */ 3833 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 3834 GRBM_STATUS__GUI_ACTIVE_MASK; 3835 3836 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3837 return 0; 3838 udelay(1); 3839 } 3840 return -ETIMEDOUT; 3841 } 3842 3843 static int gfx_v10_0_soft_reset(void *handle) 3844 { 3845 u32 grbm_soft_reset = 0; 3846 u32 tmp; 3847 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3848 3849 /* GRBM_STATUS */ 3850 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3851 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3852 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3853 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 3854 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 3855 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK 3856 | GRBM_STATUS__BCI_BUSY_MASK)) { 3857 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3858 GRBM_SOFT_RESET, SOFT_RESET_CP, 3859 1); 3860 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3861 GRBM_SOFT_RESET, SOFT_RESET_GFX, 3862 1); 3863 } 3864 3865 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3866 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3867 GRBM_SOFT_RESET, SOFT_RESET_CP, 3868 1); 3869 } 3870 3871 /* GRBM_STATUS2 */ 3872 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3873 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3874 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3875 GRBM_SOFT_RESET, SOFT_RESET_RLC, 3876 1); 3877 3878 if (grbm_soft_reset) { 3879 /* stop the rlc */ 3880 gfx_v10_0_rlc_stop(adev); 3881 3882 /* Disable GFX parsing/prefetching */ 3883 gfx_v10_0_cp_gfx_enable(adev, false); 3884 3885 /* Disable MEC parsing/prefetching */ 3886 gfx_v10_0_cp_compute_enable(adev, false); 3887 3888 if (grbm_soft_reset) { 3889 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3890 tmp |= grbm_soft_reset; 3891 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3892 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3893 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3894 3895 udelay(50); 3896 3897 tmp &= ~grbm_soft_reset; 3898 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3899 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3900 } 3901 3902 /* Wait a little for things to settle down */ 3903 udelay(50); 3904 } 3905 return 0; 3906 } 3907 3908 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3909 { 3910 uint64_t clock; 3911 3912 mutex_lock(&adev->gfx.gpu_clock_mutex); 3913 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3914 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3915 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3916 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3917 return clock; 3918 } 3919 3920 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3921 uint32_t vmid, 3922 uint32_t gds_base, uint32_t gds_size, 3923 uint32_t gws_base, uint32_t gws_size, 3924 uint32_t oa_base, uint32_t oa_size) 3925 { 3926 struct amdgpu_device *adev = ring->adev; 3927 3928 /* GDS Base */ 3929 gfx_v10_0_write_data_to_reg(ring, 0, false, 3930 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 3931 gds_base); 3932 3933 /* GDS Size */ 3934 gfx_v10_0_write_data_to_reg(ring, 0, false, 3935 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 3936 gds_size); 3937 3938 /* GWS */ 3939 gfx_v10_0_write_data_to_reg(ring, 0, false, 3940 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 3941 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3942 3943 /* OA */ 3944 gfx_v10_0_write_data_to_reg(ring, 0, false, 3945 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 3946 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3947 } 3948 3949 static int gfx_v10_0_early_init(void *handle) 3950 { 3951 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3952 3953 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS; 3954 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 3955 3956 gfx_v10_0_set_kiq_pm4_funcs(adev); 3957 gfx_v10_0_set_ring_funcs(adev); 3958 gfx_v10_0_set_irq_funcs(adev); 3959 gfx_v10_0_set_gds_init(adev); 3960 gfx_v10_0_set_rlc_funcs(adev); 3961 3962 return 0; 3963 } 3964 3965 static int gfx_v10_0_late_init(void *handle) 3966 { 3967 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3968 int r; 3969 3970 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3971 if (r) 3972 return r; 3973 3974 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3975 if (r) 3976 return r; 3977 3978 return 0; 3979 } 3980 3981 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 3982 { 3983 uint32_t rlc_cntl; 3984 3985 /* if RLC is not enabled, do nothing */ 3986 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3987 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3988 } 3989 3990 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 3991 { 3992 uint32_t data; 3993 unsigned i; 3994 3995 data = RLC_SAFE_MODE__CMD_MASK; 3996 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3997 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3998 3999 /* wait for RLC_SAFE_MODE */ 4000 for (i = 0; i < adev->usec_timeout; i++) { 4001 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4002 break; 4003 udelay(1); 4004 } 4005 } 4006 4007 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 4008 { 4009 uint32_t data; 4010 4011 data = RLC_SAFE_MODE__CMD_MASK; 4012 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4013 } 4014 4015 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4016 bool enable) 4017 { 4018 uint32_t data, def; 4019 4020 /* It is disabled by HW by default */ 4021 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4022 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4023 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4024 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4025 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4026 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4027 4028 /* only for Vega10 & Raven1 */ 4029 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4030 4031 if (def != data) 4032 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4033 4034 /* MGLS is a global flag to control all MGLS in GFX */ 4035 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4036 /* 2 - RLC memory Light sleep */ 4037 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4038 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4039 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4040 if (def != data) 4041 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4042 } 4043 /* 3 - CP memory Light sleep */ 4044 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4045 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4046 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4047 if (def != data) 4048 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4049 } 4050 } 4051 } else { 4052 /* 1 - MGCG_OVERRIDE */ 4053 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4054 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4055 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4056 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4057 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4058 if (def != data) 4059 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4060 4061 /* 2 - disable MGLS in RLC */ 4062 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4063 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4064 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4065 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4066 } 4067 4068 /* 3 - disable MGLS in CP */ 4069 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4070 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4071 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4072 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4073 } 4074 } 4075 } 4076 4077 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 4078 bool enable) 4079 { 4080 uint32_t data, def; 4081 4082 /* Enable 3D CGCG/CGLS */ 4083 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 4084 /* write cmd to clear cgcg/cgls ov */ 4085 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4086 /* unset CGCG override */ 4087 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4088 /* update CGCG and CGLS override bits */ 4089 if (def != data) 4090 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4091 /* enable 3Dcgcg FSM(0x0000363f) */ 4092 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4093 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4094 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4095 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4096 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4097 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4098 if (def != data) 4099 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4100 4101 /* set IDLE_POLL_COUNT(0x00900100) */ 4102 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4103 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4104 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4105 if (def != data) 4106 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4107 } else { 4108 /* Disable CGCG/CGLS */ 4109 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4110 /* disable cgcg, cgls should be disabled */ 4111 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4112 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4113 /* disable cgcg and cgls in FSM */ 4114 if (def != data) 4115 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4116 } 4117 } 4118 4119 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4120 bool enable) 4121 { 4122 uint32_t def, data; 4123 4124 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4125 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4126 /* unset CGCG override */ 4127 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4128 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4129 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4130 else 4131 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4132 /* update CGCG and CGLS override bits */ 4133 if (def != data) 4134 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4135 4136 /* enable cgcg FSM(0x0000363F) */ 4137 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4138 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4139 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4140 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4141 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4142 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4143 if (def != data) 4144 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4145 4146 /* set IDLE_POLL_COUNT(0x00900100) */ 4147 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4148 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4149 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4150 if (def != data) 4151 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4152 } else { 4153 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4154 /* reset CGCG/CGLS bits */ 4155 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4156 /* disable cgcg and cgls in FSM */ 4157 if (def != data) 4158 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4159 } 4160 } 4161 4162 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4163 bool enable) 4164 { 4165 amdgpu_gfx_rlc_enter_safe_mode(adev); 4166 4167 if (enable) { 4168 /* CGCG/CGLS should be enabled after MGCG/MGLS 4169 * === MGCG + MGLS === 4170 */ 4171 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4172 /* === CGCG /CGLS for GFX 3D Only === */ 4173 gfx_v10_0_update_3d_clock_gating(adev, enable); 4174 /* === CGCG + CGLS === */ 4175 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4176 } else { 4177 /* CGCG/CGLS should be disabled before MGCG/MGLS 4178 * === CGCG + CGLS === 4179 */ 4180 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4181 /* === CGCG /CGLS for GFX 3D Only === */ 4182 gfx_v10_0_update_3d_clock_gating(adev, enable); 4183 /* === MGCG + MGLS === */ 4184 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4185 } 4186 4187 if (adev->cg_flags & 4188 (AMD_CG_SUPPORT_GFX_MGCG | 4189 AMD_CG_SUPPORT_GFX_CGLS | 4190 AMD_CG_SUPPORT_GFX_CGCG | 4191 AMD_CG_SUPPORT_GFX_CGLS | 4192 AMD_CG_SUPPORT_GFX_3D_CGCG | 4193 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4194 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 4195 4196 amdgpu_gfx_rlc_exit_safe_mode(adev); 4197 4198 return 0; 4199 } 4200 4201 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 4202 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 4203 .set_safe_mode = gfx_v10_0_set_safe_mode, 4204 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 4205 .init = gfx_v10_0_rlc_init, 4206 .get_csb_size = gfx_v10_0_get_csb_size, 4207 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 4208 .resume = gfx_v10_0_rlc_resume, 4209 .stop = gfx_v10_0_rlc_stop, 4210 .reset = gfx_v10_0_rlc_reset, 4211 .start = gfx_v10_0_rlc_start 4212 }; 4213 4214 static int gfx_v10_0_set_powergating_state(void *handle, 4215 enum amd_powergating_state state) 4216 { 4217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4218 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 4219 switch (adev->asic_type) { 4220 case CHIP_NAVI10: 4221 case CHIP_NAVI14: 4222 if (!enable) { 4223 amdgpu_gfx_off_ctrl(adev, false); 4224 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 4225 } else 4226 amdgpu_gfx_off_ctrl(adev, true); 4227 break; 4228 default: 4229 break; 4230 } 4231 return 0; 4232 } 4233 4234 static int gfx_v10_0_set_clockgating_state(void *handle, 4235 enum amd_clockgating_state state) 4236 { 4237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4238 4239 switch (adev->asic_type) { 4240 case CHIP_NAVI10: 4241 case CHIP_NAVI14: 4242 case CHIP_NAVI12: 4243 gfx_v10_0_update_gfx_clock_gating(adev, 4244 state == AMD_CG_STATE_GATE ? true : false); 4245 break; 4246 default: 4247 break; 4248 } 4249 return 0; 4250 } 4251 4252 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 4253 { 4254 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4255 int data; 4256 4257 /* AMD_CG_SUPPORT_GFX_MGCG */ 4258 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4259 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4260 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4261 4262 /* AMD_CG_SUPPORT_GFX_CGCG */ 4263 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4264 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4265 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4266 4267 /* AMD_CG_SUPPORT_GFX_CGLS */ 4268 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4269 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4270 4271 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 4272 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4273 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 4274 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 4275 4276 /* AMD_CG_SUPPORT_GFX_CP_LS */ 4277 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4278 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 4279 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 4280 4281 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4282 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4283 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4284 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4285 4286 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4287 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4288 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4289 } 4290 4291 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4292 { 4293 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 4294 } 4295 4296 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4297 { 4298 struct amdgpu_device *adev = ring->adev; 4299 u64 wptr; 4300 4301 /* XXX check if swapping is necessary on BE */ 4302 if (ring->use_doorbell) { 4303 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 4304 } else { 4305 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 4306 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 4307 } 4308 4309 return wptr; 4310 } 4311 4312 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4313 { 4314 struct amdgpu_device *adev = ring->adev; 4315 4316 if (ring->use_doorbell) { 4317 /* XXX check if swapping is necessary on BE */ 4318 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4319 WDOORBELL64(ring->doorbell_index, ring->wptr); 4320 } else { 4321 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4322 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 4323 } 4324 } 4325 4326 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4327 { 4328 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 4329 } 4330 4331 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4332 { 4333 u64 wptr; 4334 4335 /* XXX check if swapping is necessary on BE */ 4336 if (ring->use_doorbell) 4337 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 4338 else 4339 BUG(); 4340 return wptr; 4341 } 4342 4343 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4344 { 4345 struct amdgpu_device *adev = ring->adev; 4346 4347 /* XXX check if swapping is necessary on BE */ 4348 if (ring->use_doorbell) { 4349 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4350 WDOORBELL64(ring->doorbell_index, ring->wptr); 4351 } else { 4352 BUG(); /* only DOORBELL method supported on gfx10 now */ 4353 } 4354 } 4355 4356 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4357 { 4358 struct amdgpu_device *adev = ring->adev; 4359 u32 ref_and_mask, reg_mem_engine; 4360 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 4361 4362 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4363 switch (ring->me) { 4364 case 1: 4365 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4366 break; 4367 case 2: 4368 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4369 break; 4370 default: 4371 return; 4372 } 4373 reg_mem_engine = 0; 4374 } else { 4375 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4376 reg_mem_engine = 1; /* pfp */ 4377 } 4378 4379 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4380 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 4381 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 4382 ref_and_mask, ref_and_mask, 0x20); 4383 } 4384 4385 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4386 struct amdgpu_job *job, 4387 struct amdgpu_ib *ib, 4388 uint32_t flags) 4389 { 4390 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4391 u32 header, control = 0; 4392 4393 if (ib->flags & AMDGPU_IB_FLAG_CE) 4394 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 4395 else 4396 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4397 4398 control |= ib->length_dw | (vmid << 24); 4399 4400 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 4401 control |= INDIRECT_BUFFER_PRE_ENB(1); 4402 4403 if (flags & AMDGPU_IB_PREEMPTED) 4404 control |= INDIRECT_BUFFER_PRE_RESUME(1); 4405 4406 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 4407 gfx_v10_0_ring_emit_de_meta(ring, 4408 flags & AMDGPU_IB_PREEMPTED ? true : false); 4409 } 4410 4411 amdgpu_ring_write(ring, header); 4412 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4413 amdgpu_ring_write(ring, 4414 #ifdef __BIG_ENDIAN 4415 (2 << 0) | 4416 #endif 4417 lower_32_bits(ib->gpu_addr)); 4418 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4419 amdgpu_ring_write(ring, control); 4420 } 4421 4422 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4423 struct amdgpu_job *job, 4424 struct amdgpu_ib *ib, 4425 uint32_t flags) 4426 { 4427 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4428 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4429 4430 /* Currently, there is a high possibility to get wave ID mismatch 4431 * between ME and GDS, leading to a hw deadlock, because ME generates 4432 * different wave IDs than the GDS expects. This situation happens 4433 * randomly when at least 5 compute pipes use GDS ordered append. 4434 * The wave IDs generated by ME are also wrong after suspend/resume. 4435 * Those are probably bugs somewhere else in the kernel driver. 4436 * 4437 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 4438 * GDS to 0 for this ring (me/pipe). 4439 */ 4440 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 4441 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4442 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 4443 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 4444 } 4445 4446 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4447 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4448 amdgpu_ring_write(ring, 4449 #ifdef __BIG_ENDIAN 4450 (2 << 0) | 4451 #endif 4452 lower_32_bits(ib->gpu_addr)); 4453 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4454 amdgpu_ring_write(ring, control); 4455 } 4456 4457 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4458 u64 seq, unsigned flags) 4459 { 4460 struct amdgpu_device *adev = ring->adev; 4461 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4462 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4463 4464 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 4465 if (adev->pdev->device == 0x50) 4466 int_sel = false; 4467 4468 /* RELEASE_MEM - flush caches, send int */ 4469 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4470 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4471 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4472 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 4473 PACKET3_RELEASE_MEM_GCR_GLM_WB | 4474 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4475 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4476 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4477 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4478 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4479 4480 /* 4481 * the address should be Qword aligned if 64bit write, Dword 4482 * aligned if only send 32bit data low (discard data high) 4483 */ 4484 if (write64bit) 4485 BUG_ON(addr & 0x7); 4486 else 4487 BUG_ON(addr & 0x3); 4488 amdgpu_ring_write(ring, lower_32_bits(addr)); 4489 amdgpu_ring_write(ring, upper_32_bits(addr)); 4490 amdgpu_ring_write(ring, lower_32_bits(seq)); 4491 amdgpu_ring_write(ring, upper_32_bits(seq)); 4492 amdgpu_ring_write(ring, 0); 4493 } 4494 4495 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4496 { 4497 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4498 uint32_t seq = ring->fence_drv.sync_seq; 4499 uint64_t addr = ring->fence_drv.gpu_addr; 4500 4501 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4502 upper_32_bits(addr), seq, 0xffffffff, 4); 4503 } 4504 4505 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4506 unsigned vmid, uint64_t pd_addr) 4507 { 4508 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4509 4510 /* compute doesn't have PFP */ 4511 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4512 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4513 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4514 amdgpu_ring_write(ring, 0x0); 4515 } 4516 } 4517 4518 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4519 u64 seq, unsigned int flags) 4520 { 4521 struct amdgpu_device *adev = ring->adev; 4522 4523 /* we only allocate 32bit for each seq wb address */ 4524 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4525 4526 /* write fence seq to the "addr" */ 4527 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4528 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4529 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4530 amdgpu_ring_write(ring, lower_32_bits(addr)); 4531 amdgpu_ring_write(ring, upper_32_bits(addr)); 4532 amdgpu_ring_write(ring, lower_32_bits(seq)); 4533 4534 if (flags & AMDGPU_FENCE_FLAG_INT) { 4535 /* set register to trigger INT */ 4536 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4537 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4538 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4539 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 4540 amdgpu_ring_write(ring, 0); 4541 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4542 } 4543 } 4544 4545 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 4546 { 4547 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4548 amdgpu_ring_write(ring, 0); 4549 } 4550 4551 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 4552 { 4553 uint32_t dw2 = 0; 4554 4555 if (amdgpu_mcbp) 4556 gfx_v10_0_ring_emit_ce_meta(ring, 4557 flags & AMDGPU_IB_PREEMPTED ? true : false); 4558 4559 gfx_v10_0_ring_emit_tmz(ring, true); 4560 4561 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4562 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4563 /* set load_global_config & load_global_uconfig */ 4564 dw2 |= 0x8001; 4565 /* set load_cs_sh_regs */ 4566 dw2 |= 0x01000000; 4567 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4568 dw2 |= 0x10002; 4569 4570 /* set load_ce_ram if preamble presented */ 4571 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 4572 dw2 |= 0x10000000; 4573 } else { 4574 /* still load_ce_ram if this is the first time preamble presented 4575 * although there is no context switch happens. 4576 */ 4577 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 4578 dw2 |= 0x10000000; 4579 } 4580 4581 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4582 amdgpu_ring_write(ring, dw2); 4583 amdgpu_ring_write(ring, 0); 4584 } 4585 4586 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 4587 { 4588 unsigned ret; 4589 4590 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4591 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 4592 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 4593 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 4594 ret = ring->wptr & ring->buf_mask; 4595 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 4596 4597 return ret; 4598 } 4599 4600 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 4601 { 4602 unsigned cur; 4603 BUG_ON(offset > ring->buf_mask); 4604 BUG_ON(ring->ring[offset] != 0x55aa55aa); 4605 4606 cur = (ring->wptr - 1) & ring->buf_mask; 4607 if (likely(cur > offset)) 4608 ring->ring[offset] = cur - offset; 4609 else 4610 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 4611 } 4612 4613 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 4614 { 4615 int i, r = 0; 4616 struct amdgpu_device *adev = ring->adev; 4617 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4618 struct amdgpu_ring *kiq_ring = &kiq->ring; 4619 4620 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4621 return -EINVAL; 4622 4623 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) 4624 return -ENOMEM; 4625 4626 /* assert preemption condition */ 4627 amdgpu_ring_set_preempt_cond_exec(ring, false); 4628 4629 /* assert IB preemption, emit the trailing fence */ 4630 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4631 ring->trail_fence_gpu_addr, 4632 ++ring->trail_seq); 4633 amdgpu_ring_commit(kiq_ring); 4634 4635 /* poll the trailing fence */ 4636 for (i = 0; i < adev->usec_timeout; i++) { 4637 if (ring->trail_seq == 4638 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4639 break; 4640 udelay(1); 4641 } 4642 4643 if (i >= adev->usec_timeout) { 4644 r = -EINVAL; 4645 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4646 } 4647 4648 /* deassert preemption condition */ 4649 amdgpu_ring_set_preempt_cond_exec(ring, true); 4650 return r; 4651 } 4652 4653 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 4654 { 4655 struct amdgpu_device *adev = ring->adev; 4656 struct v10_ce_ib_state ce_payload = {0}; 4657 uint64_t csa_addr; 4658 int cnt; 4659 4660 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 4661 csa_addr = amdgpu_csa_vaddr(ring->adev); 4662 4663 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4664 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 4665 WRITE_DATA_DST_SEL(8) | 4666 WR_CONFIRM) | 4667 WRITE_DATA_CACHE_POLICY(0)); 4668 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4669 offsetof(struct v10_gfx_meta_data, ce_payload))); 4670 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4671 offsetof(struct v10_gfx_meta_data, ce_payload))); 4672 4673 if (resume) 4674 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4675 offsetof(struct v10_gfx_meta_data, 4676 ce_payload), 4677 sizeof(ce_payload) >> 2); 4678 else 4679 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 4680 sizeof(ce_payload) >> 2); 4681 } 4682 4683 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 4684 { 4685 struct amdgpu_device *adev = ring->adev; 4686 struct v10_de_ib_state de_payload = {0}; 4687 uint64_t csa_addr, gds_addr; 4688 int cnt; 4689 4690 csa_addr = amdgpu_csa_vaddr(ring->adev); 4691 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 4692 PAGE_SIZE); 4693 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 4694 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 4695 4696 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 4697 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4698 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 4699 WRITE_DATA_DST_SEL(8) | 4700 WR_CONFIRM) | 4701 WRITE_DATA_CACHE_POLICY(0)); 4702 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4703 offsetof(struct v10_gfx_meta_data, de_payload))); 4704 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4705 offsetof(struct v10_gfx_meta_data, de_payload))); 4706 4707 if (resume) 4708 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4709 offsetof(struct v10_gfx_meta_data, 4710 de_payload), 4711 sizeof(de_payload) >> 2); 4712 else 4713 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 4714 sizeof(de_payload) >> 2); 4715 } 4716 4717 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 4718 { 4719 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4720 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 4721 } 4722 4723 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 4724 { 4725 struct amdgpu_device *adev = ring->adev; 4726 4727 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4728 amdgpu_ring_write(ring, 0 | /* src: register*/ 4729 (5 << 8) | /* dst: memory */ 4730 (1 << 20)); /* write confirm */ 4731 amdgpu_ring_write(ring, reg); 4732 amdgpu_ring_write(ring, 0); 4733 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4734 adev->virt.reg_val_offs * 4)); 4735 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4736 adev->virt.reg_val_offs * 4)); 4737 } 4738 4739 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 4740 uint32_t val) 4741 { 4742 uint32_t cmd = 0; 4743 4744 switch (ring->funcs->type) { 4745 case AMDGPU_RING_TYPE_GFX: 4746 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4747 break; 4748 case AMDGPU_RING_TYPE_KIQ: 4749 cmd = (1 << 16); /* no inc addr */ 4750 break; 4751 default: 4752 cmd = WR_CONFIRM; 4753 break; 4754 } 4755 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4756 amdgpu_ring_write(ring, cmd); 4757 amdgpu_ring_write(ring, reg); 4758 amdgpu_ring_write(ring, 0); 4759 amdgpu_ring_write(ring, val); 4760 } 4761 4762 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4763 uint32_t val, uint32_t mask) 4764 { 4765 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4766 } 4767 4768 static void 4769 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4770 uint32_t me, uint32_t pipe, 4771 enum amdgpu_interrupt_state state) 4772 { 4773 uint32_t cp_int_cntl, cp_int_cntl_reg; 4774 4775 if (!me) { 4776 switch (pipe) { 4777 case 0: 4778 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 4779 break; 4780 case 1: 4781 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 4782 break; 4783 default: 4784 DRM_DEBUG("invalid pipe %d\n", pipe); 4785 return; 4786 } 4787 } else { 4788 DRM_DEBUG("invalid me %d\n", me); 4789 return; 4790 } 4791 4792 switch (state) { 4793 case AMDGPU_IRQ_STATE_DISABLE: 4794 cp_int_cntl = RREG32(cp_int_cntl_reg); 4795 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4796 TIME_STAMP_INT_ENABLE, 0); 4797 WREG32(cp_int_cntl_reg, cp_int_cntl); 4798 break; 4799 case AMDGPU_IRQ_STATE_ENABLE: 4800 cp_int_cntl = RREG32(cp_int_cntl_reg); 4801 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4802 TIME_STAMP_INT_ENABLE, 1); 4803 WREG32(cp_int_cntl_reg, cp_int_cntl); 4804 break; 4805 default: 4806 break; 4807 } 4808 } 4809 4810 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4811 int me, int pipe, 4812 enum amdgpu_interrupt_state state) 4813 { 4814 u32 mec_int_cntl, mec_int_cntl_reg; 4815 4816 /* 4817 * amdgpu controls only the first MEC. That's why this function only 4818 * handles the setting of interrupts for this specific MEC. All other 4819 * pipes' interrupts are set by amdkfd. 4820 */ 4821 4822 if (me == 1) { 4823 switch (pipe) { 4824 case 0: 4825 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4826 break; 4827 case 1: 4828 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 4829 break; 4830 case 2: 4831 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 4832 break; 4833 case 3: 4834 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 4835 break; 4836 default: 4837 DRM_DEBUG("invalid pipe %d\n", pipe); 4838 return; 4839 } 4840 } else { 4841 DRM_DEBUG("invalid me %d\n", me); 4842 return; 4843 } 4844 4845 switch (state) { 4846 case AMDGPU_IRQ_STATE_DISABLE: 4847 mec_int_cntl = RREG32(mec_int_cntl_reg); 4848 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4849 TIME_STAMP_INT_ENABLE, 0); 4850 WREG32(mec_int_cntl_reg, mec_int_cntl); 4851 break; 4852 case AMDGPU_IRQ_STATE_ENABLE: 4853 mec_int_cntl = RREG32(mec_int_cntl_reg); 4854 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4855 TIME_STAMP_INT_ENABLE, 1); 4856 WREG32(mec_int_cntl_reg, mec_int_cntl); 4857 break; 4858 default: 4859 break; 4860 } 4861 } 4862 4863 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4864 struct amdgpu_irq_src *src, 4865 unsigned type, 4866 enum amdgpu_interrupt_state state) 4867 { 4868 switch (type) { 4869 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4870 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4871 break; 4872 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4873 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4874 break; 4875 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4876 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4877 break; 4878 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4879 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4880 break; 4881 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4882 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4883 break; 4884 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4885 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4886 break; 4887 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4888 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4889 break; 4890 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4891 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4892 break; 4893 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4894 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4895 break; 4896 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4897 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4898 break; 4899 default: 4900 break; 4901 } 4902 return 0; 4903 } 4904 4905 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 4906 struct amdgpu_irq_src *source, 4907 struct amdgpu_iv_entry *entry) 4908 { 4909 int i; 4910 u8 me_id, pipe_id, queue_id; 4911 struct amdgpu_ring *ring; 4912 4913 DRM_DEBUG("IH: CP EOP\n"); 4914 me_id = (entry->ring_id & 0x0c) >> 2; 4915 pipe_id = (entry->ring_id & 0x03) >> 0; 4916 queue_id = (entry->ring_id & 0x70) >> 4; 4917 4918 switch (me_id) { 4919 case 0: 4920 if (pipe_id == 0) 4921 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4922 else 4923 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4924 break; 4925 case 1: 4926 case 2: 4927 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4928 ring = &adev->gfx.compute_ring[i]; 4929 /* Per-queue interrupt is supported for MEC starting from VI. 4930 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4931 */ 4932 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4933 amdgpu_fence_process(ring); 4934 } 4935 break; 4936 } 4937 return 0; 4938 } 4939 4940 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4941 struct amdgpu_irq_src *source, 4942 unsigned type, 4943 enum amdgpu_interrupt_state state) 4944 { 4945 switch (state) { 4946 case AMDGPU_IRQ_STATE_DISABLE: 4947 case AMDGPU_IRQ_STATE_ENABLE: 4948 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4949 PRIV_REG_INT_ENABLE, 4950 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4951 break; 4952 default: 4953 break; 4954 } 4955 4956 return 0; 4957 } 4958 4959 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4960 struct amdgpu_irq_src *source, 4961 unsigned type, 4962 enum amdgpu_interrupt_state state) 4963 { 4964 switch (state) { 4965 case AMDGPU_IRQ_STATE_DISABLE: 4966 case AMDGPU_IRQ_STATE_ENABLE: 4967 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4968 PRIV_INSTR_INT_ENABLE, 4969 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4970 default: 4971 break; 4972 } 4973 4974 return 0; 4975 } 4976 4977 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 4978 struct amdgpu_iv_entry *entry) 4979 { 4980 u8 me_id, pipe_id, queue_id; 4981 struct amdgpu_ring *ring; 4982 int i; 4983 4984 me_id = (entry->ring_id & 0x0c) >> 2; 4985 pipe_id = (entry->ring_id & 0x03) >> 0; 4986 queue_id = (entry->ring_id & 0x70) >> 4; 4987 4988 switch (me_id) { 4989 case 0: 4990 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4991 ring = &adev->gfx.gfx_ring[i]; 4992 /* we only enabled 1 gfx queue per pipe for now */ 4993 if (ring->me == me_id && ring->pipe == pipe_id) 4994 drm_sched_fault(&ring->sched); 4995 } 4996 break; 4997 case 1: 4998 case 2: 4999 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5000 ring = &adev->gfx.compute_ring[i]; 5001 if (ring->me == me_id && ring->pipe == pipe_id && 5002 ring->queue == queue_id) 5003 drm_sched_fault(&ring->sched); 5004 } 5005 break; 5006 default: 5007 BUG(); 5008 } 5009 } 5010 5011 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 5012 struct amdgpu_irq_src *source, 5013 struct amdgpu_iv_entry *entry) 5014 { 5015 DRM_ERROR("Illegal register access in command stream\n"); 5016 gfx_v10_0_handle_priv_fault(adev, entry); 5017 return 0; 5018 } 5019 5020 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 5021 struct amdgpu_irq_src *source, 5022 struct amdgpu_iv_entry *entry) 5023 { 5024 DRM_ERROR("Illegal instruction in command stream\n"); 5025 gfx_v10_0_handle_priv_fault(adev, entry); 5026 return 0; 5027 } 5028 5029 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 5030 struct amdgpu_irq_src *src, 5031 unsigned int type, 5032 enum amdgpu_interrupt_state state) 5033 { 5034 uint32_t tmp, target; 5035 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5036 5037 if (ring->me == 1) 5038 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5039 else 5040 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 5041 target += ring->pipe; 5042 5043 switch (type) { 5044 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 5045 if (state == AMDGPU_IRQ_STATE_DISABLE) { 5046 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5047 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5048 GENERIC2_INT_ENABLE, 0); 5049 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5050 5051 tmp = RREG32(target); 5052 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 5053 GENERIC2_INT_ENABLE, 0); 5054 WREG32(target, tmp); 5055 } else { 5056 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5057 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5058 GENERIC2_INT_ENABLE, 1); 5059 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5060 5061 tmp = RREG32(target); 5062 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 5063 GENERIC2_INT_ENABLE, 1); 5064 WREG32(target, tmp); 5065 } 5066 break; 5067 default: 5068 BUG(); /* kiq only support GENERIC2_INT now */ 5069 break; 5070 } 5071 return 0; 5072 } 5073 5074 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 5075 struct amdgpu_irq_src *source, 5076 struct amdgpu_iv_entry *entry) 5077 { 5078 u8 me_id, pipe_id, queue_id; 5079 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5080 5081 me_id = (entry->ring_id & 0x0c) >> 2; 5082 pipe_id = (entry->ring_id & 0x03) >> 0; 5083 queue_id = (entry->ring_id & 0x70) >> 4; 5084 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 5085 me_id, pipe_id, queue_id); 5086 5087 amdgpu_fence_process(ring); 5088 return 0; 5089 } 5090 5091 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 5092 .name = "gfx_v10_0", 5093 .early_init = gfx_v10_0_early_init, 5094 .late_init = gfx_v10_0_late_init, 5095 .sw_init = gfx_v10_0_sw_init, 5096 .sw_fini = gfx_v10_0_sw_fini, 5097 .hw_init = gfx_v10_0_hw_init, 5098 .hw_fini = gfx_v10_0_hw_fini, 5099 .suspend = gfx_v10_0_suspend, 5100 .resume = gfx_v10_0_resume, 5101 .is_idle = gfx_v10_0_is_idle, 5102 .wait_for_idle = gfx_v10_0_wait_for_idle, 5103 .soft_reset = gfx_v10_0_soft_reset, 5104 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 5105 .set_powergating_state = gfx_v10_0_set_powergating_state, 5106 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 5107 }; 5108 5109 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 5110 .type = AMDGPU_RING_TYPE_GFX, 5111 .align_mask = 0xff, 5112 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5113 .support_64bit_ptrs = true, 5114 .vmhub = AMDGPU_GFXHUB_0, 5115 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 5116 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 5117 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 5118 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5119 5 + /* COND_EXEC */ 5120 7 + /* PIPELINE_SYNC */ 5121 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5122 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5123 2 + /* VM_FLUSH */ 5124 8 + /* FENCE for VM_FLUSH */ 5125 20 + /* GDS switch */ 5126 4 + /* double SWITCH_BUFFER, 5127 * the first COND_EXEC jump to the place 5128 * just prior to this double SWITCH_BUFFER 5129 */ 5130 5 + /* COND_EXEC */ 5131 7 + /* HDP_flush */ 5132 4 + /* VGT_flush */ 5133 14 + /* CE_META */ 5134 31 + /* DE_META */ 5135 3 + /* CNTX_CTRL */ 5136 5 + /* HDP_INVL */ 5137 8 + 8 + /* FENCE x2 */ 5138 2, /* SWITCH_BUFFER */ 5139 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 5140 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 5141 .emit_fence = gfx_v10_0_ring_emit_fence, 5142 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5143 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5144 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5145 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5146 .test_ring = gfx_v10_0_ring_test_ring, 5147 .test_ib = gfx_v10_0_ring_test_ib, 5148 .insert_nop = amdgpu_ring_insert_nop, 5149 .pad_ib = amdgpu_ring_generic_pad_ib, 5150 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 5151 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 5152 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 5153 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 5154 .preempt_ib = gfx_v10_0_ring_preempt_ib, 5155 .emit_tmz = gfx_v10_0_ring_emit_tmz, 5156 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5157 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5158 }; 5159 5160 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 5161 .type = AMDGPU_RING_TYPE_COMPUTE, 5162 .align_mask = 0xff, 5163 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5164 .support_64bit_ptrs = true, 5165 .vmhub = AMDGPU_GFXHUB_0, 5166 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5167 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5168 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5169 .emit_frame_size = 5170 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5171 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5172 5 + /* hdp invalidate */ 5173 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5174 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5175 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5176 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5177 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 5178 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5179 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5180 .emit_fence = gfx_v10_0_ring_emit_fence, 5181 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5182 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5183 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5184 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5185 .test_ring = gfx_v10_0_ring_test_ring, 5186 .test_ib = gfx_v10_0_ring_test_ib, 5187 .insert_nop = amdgpu_ring_insert_nop, 5188 .pad_ib = amdgpu_ring_generic_pad_ib, 5189 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5190 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5191 }; 5192 5193 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 5194 .type = AMDGPU_RING_TYPE_KIQ, 5195 .align_mask = 0xff, 5196 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5197 .support_64bit_ptrs = true, 5198 .vmhub = AMDGPU_GFXHUB_0, 5199 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5200 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5201 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5202 .emit_frame_size = 5203 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5204 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5205 5 + /*hdp invalidate */ 5206 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5207 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5208 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5209 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5210 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5211 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5212 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5213 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 5214 .test_ring = gfx_v10_0_ring_test_ring, 5215 .test_ib = gfx_v10_0_ring_test_ib, 5216 .insert_nop = amdgpu_ring_insert_nop, 5217 .pad_ib = amdgpu_ring_generic_pad_ib, 5218 .emit_rreg = gfx_v10_0_ring_emit_rreg, 5219 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5220 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5221 }; 5222 5223 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 5224 { 5225 int i; 5226 5227 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 5228 5229 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5230 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 5231 5232 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5233 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 5234 } 5235 5236 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 5237 .set = gfx_v10_0_set_eop_interrupt_state, 5238 .process = gfx_v10_0_eop_irq, 5239 }; 5240 5241 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 5242 .set = gfx_v10_0_set_priv_reg_fault_state, 5243 .process = gfx_v10_0_priv_reg_irq, 5244 }; 5245 5246 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 5247 .set = gfx_v10_0_set_priv_inst_fault_state, 5248 .process = gfx_v10_0_priv_inst_irq, 5249 }; 5250 5251 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 5252 .set = gfx_v10_0_kiq_set_interrupt_state, 5253 .process = gfx_v10_0_kiq_irq, 5254 }; 5255 5256 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 5257 { 5258 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5259 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 5260 5261 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 5262 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 5263 5264 adev->gfx.priv_reg_irq.num_types = 1; 5265 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 5266 5267 adev->gfx.priv_inst_irq.num_types = 1; 5268 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 5269 } 5270 5271 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 5272 { 5273 switch (adev->asic_type) { 5274 case CHIP_NAVI10: 5275 case CHIP_NAVI14: 5276 case CHIP_NAVI12: 5277 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 5278 break; 5279 default: 5280 break; 5281 } 5282 } 5283 5284 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 5285 { 5286 /* init asic gds info */ 5287 switch (adev->asic_type) { 5288 case CHIP_NAVI10: 5289 default: 5290 adev->gds.gds_size = 0x10000; 5291 adev->gds.gds_compute_max_wave_id = 0x4ff; 5292 break; 5293 } 5294 5295 adev->gds.gws_size = 64; 5296 adev->gds.oa_size = 16; 5297 } 5298 5299 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5300 u32 bitmap) 5301 { 5302 u32 data; 5303 5304 if (!bitmap) 5305 return; 5306 5307 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5308 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5309 5310 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 5311 } 5312 5313 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5314 { 5315 u32 data, wgp_bitmask; 5316 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 5317 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 5318 5319 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5320 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5321 5322 wgp_bitmask = 5323 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5324 5325 return (~data) & wgp_bitmask; 5326 } 5327 5328 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5329 { 5330 u32 wgp_idx, wgp_active_bitmap; 5331 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5332 5333 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5334 cu_active_bitmap = 0; 5335 5336 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5337 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5338 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5339 if (wgp_active_bitmap & (1 << wgp_idx)) 5340 cu_active_bitmap |= cu_bitmap_per_wgp; 5341 } 5342 5343 return cu_active_bitmap; 5344 } 5345 5346 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 5347 struct amdgpu_cu_info *cu_info) 5348 { 5349 int i, j, k, counter, active_cu_number = 0; 5350 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5351 unsigned disable_masks[4 * 2]; 5352 5353 if (!adev || !cu_info) 5354 return -EINVAL; 5355 5356 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5357 5358 mutex_lock(&adev->grbm_idx_mutex); 5359 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5360 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5361 mask = 1; 5362 ao_bitmap = 0; 5363 counter = 0; 5364 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5365 if (i < 4 && j < 2) 5366 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 5367 adev, disable_masks[i * 2 + j]); 5368 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 5369 cu_info->bitmap[i][j] = bitmap; 5370 5371 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5372 if (bitmap & mask) { 5373 if (counter < adev->gfx.config.max_cu_per_sh) 5374 ao_bitmap |= mask; 5375 counter++; 5376 } 5377 mask <<= 1; 5378 } 5379 active_cu_number += counter; 5380 if (i < 2 && j < 2) 5381 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5382 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5383 } 5384 } 5385 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5386 mutex_unlock(&adev->grbm_idx_mutex); 5387 5388 cu_info->number = active_cu_number; 5389 cu_info->ao_cu_mask = ao_cu_mask; 5390 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5391 5392 return 0; 5393 } 5394 5395 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 5396 { 5397 .type = AMD_IP_BLOCK_TYPE_GFX, 5398 .major = 10, 5399 .minor = 0, 5400 .rev = 0, 5401 .funcs = &gfx_v10_0_ip_funcs, 5402 }; 5403