1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 114 115 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 121 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 125 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 127 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 129 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 131 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 134 135 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 137 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 139 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 141 #define mmCP_HYP_CE_UCODE_DATA 0x5819 142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 143 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 145 #define mmCP_HYP_ME_UCODE_DATA 0x5817 146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 147 148 #define mmCPG_PSP_DEBUG 0x5c10 149 #define mmCPG_PSP_DEBUG_BASE_IDX 1 150 #define mmCPC_PSP_DEBUG 0x5c11 151 #define mmCPC_PSP_DEBUG_BASE_IDX 1 152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 154 155 //CC_GC_SA_UNIT_DISABLE 156 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 160 //GC_USER_SA_UNIT_DISABLE 161 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //PA_SC_ENHANCE_3 166 #define mmPA_SC_ENHANCE_3 0x1085 167 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 170 171 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 173 174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 178 179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 181 182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 184 185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 187 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 191 192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 203 204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 206 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 210 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 217 218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 224 225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 231 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 238 239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 245 246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 252 253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 259 260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 266 267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 273 274 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 275 { 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 316 }; 317 318 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 319 { 320 /* Pending on emulation bring up */ 321 }; 322 323 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 324 { 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1377 }; 1378 1379 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1380 { 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1419 }; 1420 1421 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1422 { 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1465 }; 1466 1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1468 { 1469 /* Pending on emulation bring up */ 1470 }; 1471 1472 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1473 { 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2094 }; 2095 2096 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2097 { 2098 /* Pending on emulation bring up */ 2099 }; 2100 2101 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2102 { 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3155 }; 3156 3157 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3158 { 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3202 }; 3203 3204 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3205 { 3206 /* Pending on emulation bring up */ 3207 }; 3208 3209 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3210 { 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3252 3253 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3255 }; 3256 3257 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3258 { 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3283 3284 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3286 }; 3287 3288 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = 3289 { 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3310 }; 3311 3312 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3313 { 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3350 }; 3351 3352 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3385 }; 3386 3387 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3422 }; 3423 3424 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = 3425 { 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3448 }; 3449 3450 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3473 }; 3474 3475 #define DEFAULT_SH_MEM_CONFIG \ 3476 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3477 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3478 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3479 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3480 3481 /* TODO: pending on golden setting value of gb address config */ 3482 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3483 3484 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3485 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3486 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3487 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3488 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3489 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3490 struct amdgpu_cu_info *cu_info); 3491 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3493 u32 sh_num, u32 instance, int xcc_id); 3494 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3495 3496 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3497 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3498 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3499 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3500 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3501 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3502 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3503 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3504 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3505 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3506 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3507 uint16_t pasid, uint32_t flush_type, 3508 bool all_hub, uint8_t dst_sel); 3509 3510 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3511 { 3512 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3513 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3514 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3515 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3516 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3517 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3518 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3519 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3520 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3521 } 3522 3523 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3524 struct amdgpu_ring *ring) 3525 { 3526 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3527 uint64_t wptr_addr = ring->wptr_gpu_addr; 3528 uint32_t eng_sel = 0; 3529 3530 switch (ring->funcs->type) { 3531 case AMDGPU_RING_TYPE_COMPUTE: 3532 eng_sel = 0; 3533 break; 3534 case AMDGPU_RING_TYPE_GFX: 3535 eng_sel = 4; 3536 break; 3537 case AMDGPU_RING_TYPE_MES: 3538 eng_sel = 5; 3539 break; 3540 default: 3541 WARN_ON(1); 3542 } 3543 3544 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3545 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3546 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3547 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3548 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3549 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3550 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3551 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3552 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3553 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3554 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3555 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3556 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3557 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3558 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3559 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3560 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3561 } 3562 3563 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3564 struct amdgpu_ring *ring, 3565 enum amdgpu_unmap_queues_action action, 3566 u64 gpu_addr, u64 seq) 3567 { 3568 struct amdgpu_device *adev = kiq_ring->adev; 3569 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3570 3571 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 3572 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 3573 return; 3574 } 3575 3576 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3577 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3578 PACKET3_UNMAP_QUEUES_ACTION(action) | 3579 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3580 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3581 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3582 amdgpu_ring_write(kiq_ring, 3583 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3584 3585 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3586 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3587 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3588 amdgpu_ring_write(kiq_ring, seq); 3589 } else { 3590 amdgpu_ring_write(kiq_ring, 0); 3591 amdgpu_ring_write(kiq_ring, 0); 3592 amdgpu_ring_write(kiq_ring, 0); 3593 } 3594 } 3595 3596 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3597 struct amdgpu_ring *ring, 3598 u64 addr, 3599 u64 seq) 3600 { 3601 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3602 3603 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3604 amdgpu_ring_write(kiq_ring, 3605 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3606 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3607 PACKET3_QUERY_STATUS_COMMAND(2)); 3608 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3609 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3610 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3611 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3612 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3613 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3614 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3615 } 3616 3617 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3618 uint16_t pasid, uint32_t flush_type, 3619 bool all_hub) 3620 { 3621 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3622 } 3623 3624 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3625 .kiq_set_resources = gfx10_kiq_set_resources, 3626 .kiq_map_queues = gfx10_kiq_map_queues, 3627 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3628 .kiq_query_status = gfx10_kiq_query_status, 3629 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3630 .set_resources_size = 8, 3631 .map_queues_size = 7, 3632 .unmap_queues_size = 6, 3633 .query_status_size = 7, 3634 .invalidate_tlbs_size = 2, 3635 }; 3636 3637 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3638 { 3639 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3640 } 3641 3642 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3643 { 3644 switch (adev->ip_versions[GC_HWIP][0]) { 3645 case IP_VERSION(10, 1, 10): 3646 soc15_program_register_sequence(adev, 3647 golden_settings_gc_rlc_spm_10_0_nv10, 3648 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3649 break; 3650 case IP_VERSION(10, 1, 1): 3651 soc15_program_register_sequence(adev, 3652 golden_settings_gc_rlc_spm_10_1_nv14, 3653 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3654 break; 3655 case IP_VERSION(10, 1, 2): 3656 soc15_program_register_sequence(adev, 3657 golden_settings_gc_rlc_spm_10_1_2_nv12, 3658 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3659 break; 3660 default: 3661 break; 3662 } 3663 } 3664 3665 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3666 { 3667 switch (adev->ip_versions[GC_HWIP][0]) { 3668 case IP_VERSION(10, 1, 10): 3669 soc15_program_register_sequence(adev, 3670 golden_settings_gc_10_1, 3671 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3672 soc15_program_register_sequence(adev, 3673 golden_settings_gc_10_0_nv10, 3674 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3675 break; 3676 case IP_VERSION(10, 1, 1): 3677 soc15_program_register_sequence(adev, 3678 golden_settings_gc_10_1_1, 3679 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3680 soc15_program_register_sequence(adev, 3681 golden_settings_gc_10_1_nv14, 3682 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3683 break; 3684 case IP_VERSION(10, 1, 2): 3685 soc15_program_register_sequence(adev, 3686 golden_settings_gc_10_1_2, 3687 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3688 soc15_program_register_sequence(adev, 3689 golden_settings_gc_10_1_2_nv12, 3690 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3691 break; 3692 case IP_VERSION(10, 3, 0): 3693 soc15_program_register_sequence(adev, 3694 golden_settings_gc_10_3, 3695 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3696 soc15_program_register_sequence(adev, 3697 golden_settings_gc_10_3_sienna_cichlid, 3698 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3699 break; 3700 case IP_VERSION(10, 3, 2): 3701 soc15_program_register_sequence(adev, 3702 golden_settings_gc_10_3_2, 3703 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3704 break; 3705 case IP_VERSION(10, 3, 1): 3706 soc15_program_register_sequence(adev, 3707 golden_settings_gc_10_3_vangogh, 3708 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3709 break; 3710 case IP_VERSION(10, 3, 3): 3711 soc15_program_register_sequence(adev, 3712 golden_settings_gc_10_3_3, 3713 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3714 break; 3715 case IP_VERSION(10, 3, 4): 3716 soc15_program_register_sequence(adev, 3717 golden_settings_gc_10_3_4, 3718 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3719 break; 3720 case IP_VERSION(10, 3, 5): 3721 soc15_program_register_sequence(adev, 3722 golden_settings_gc_10_3_5, 3723 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3724 break; 3725 case IP_VERSION(10, 1, 3): 3726 case IP_VERSION(10, 1, 4): 3727 soc15_program_register_sequence(adev, 3728 golden_settings_gc_10_0_cyan_skillfish, 3729 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3730 break; 3731 case IP_VERSION(10, 3, 6): 3732 soc15_program_register_sequence(adev, 3733 golden_settings_gc_10_3_6, 3734 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3735 break; 3736 case IP_VERSION(10, 3, 7): 3737 soc15_program_register_sequence(adev, 3738 golden_settings_gc_10_3_7, 3739 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3740 break; 3741 default: 3742 break; 3743 } 3744 gfx_v10_0_init_spm_golden_registers(adev); 3745 } 3746 3747 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3748 bool wc, uint32_t reg, uint32_t val) 3749 { 3750 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3751 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3752 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3753 amdgpu_ring_write(ring, reg); 3754 amdgpu_ring_write(ring, 0); 3755 amdgpu_ring_write(ring, val); 3756 } 3757 3758 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3759 int mem_space, int opt, uint32_t addr0, 3760 uint32_t addr1, uint32_t ref, uint32_t mask, 3761 uint32_t inv) 3762 { 3763 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3764 amdgpu_ring_write(ring, 3765 /* memory (1) or register (0) */ 3766 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3767 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3768 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3769 WAIT_REG_MEM_ENGINE(eng_sel))); 3770 3771 if (mem_space) 3772 BUG_ON(addr0 & 0x3); /* Dword align */ 3773 amdgpu_ring_write(ring, addr0); 3774 amdgpu_ring_write(ring, addr1); 3775 amdgpu_ring_write(ring, ref); 3776 amdgpu_ring_write(ring, mask); 3777 amdgpu_ring_write(ring, inv); /* poll interval */ 3778 } 3779 3780 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3781 { 3782 struct amdgpu_device *adev = ring->adev; 3783 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3784 uint32_t tmp = 0; 3785 unsigned i; 3786 int r; 3787 3788 WREG32(scratch, 0xCAFEDEAD); 3789 r = amdgpu_ring_alloc(ring, 3); 3790 if (r) { 3791 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3792 ring->idx, r); 3793 return r; 3794 } 3795 3796 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3797 amdgpu_ring_write(ring, scratch - 3798 PACKET3_SET_UCONFIG_REG_START); 3799 amdgpu_ring_write(ring, 0xDEADBEEF); 3800 amdgpu_ring_commit(ring); 3801 3802 for (i = 0; i < adev->usec_timeout; i++) { 3803 tmp = RREG32(scratch); 3804 if (tmp == 0xDEADBEEF) 3805 break; 3806 if (amdgpu_emu_mode == 1) 3807 msleep(1); 3808 else 3809 udelay(1); 3810 } 3811 3812 if (i >= adev->usec_timeout) 3813 r = -ETIMEDOUT; 3814 3815 return r; 3816 } 3817 3818 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3819 { 3820 struct amdgpu_device *adev = ring->adev; 3821 struct amdgpu_ib ib; 3822 struct dma_fence *f = NULL; 3823 unsigned index; 3824 uint64_t gpu_addr; 3825 volatile uint32_t *cpu_ptr; 3826 long r; 3827 3828 memset(&ib, 0, sizeof(ib)); 3829 3830 if (ring->is_mes_queue) { 3831 uint32_t padding, offset; 3832 3833 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 3834 padding = amdgpu_mes_ctx_get_offs(ring, 3835 AMDGPU_MES_CTX_PADDING_OFFS); 3836 3837 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 3838 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 3839 3840 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 3841 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 3842 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 3843 } else { 3844 r = amdgpu_device_wb_get(adev, &index); 3845 if (r) 3846 return r; 3847 3848 gpu_addr = adev->wb.gpu_addr + (index * 4); 3849 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3850 cpu_ptr = &adev->wb.wb[index]; 3851 3852 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 3853 if (r) { 3854 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 3855 goto err1; 3856 } 3857 } 3858 3859 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3860 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3861 ib.ptr[2] = lower_32_bits(gpu_addr); 3862 ib.ptr[3] = upper_32_bits(gpu_addr); 3863 ib.ptr[4] = 0xDEADBEEF; 3864 ib.length_dw = 5; 3865 3866 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3867 if (r) 3868 goto err2; 3869 3870 r = dma_fence_wait_timeout(f, false, timeout); 3871 if (r == 0) { 3872 r = -ETIMEDOUT; 3873 goto err2; 3874 } else if (r < 0) { 3875 goto err2; 3876 } 3877 3878 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 3879 r = 0; 3880 else 3881 r = -EINVAL; 3882 err2: 3883 if (!ring->is_mes_queue) 3884 amdgpu_ib_free(adev, &ib, NULL); 3885 dma_fence_put(f); 3886 err1: 3887 if (!ring->is_mes_queue) 3888 amdgpu_device_wb_free(adev, index); 3889 return r; 3890 } 3891 3892 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3893 { 3894 amdgpu_ucode_release(&adev->gfx.pfp_fw); 3895 amdgpu_ucode_release(&adev->gfx.me_fw); 3896 amdgpu_ucode_release(&adev->gfx.ce_fw); 3897 amdgpu_ucode_release(&adev->gfx.rlc_fw); 3898 amdgpu_ucode_release(&adev->gfx.mec_fw); 3899 amdgpu_ucode_release(&adev->gfx.mec2_fw); 3900 3901 kfree(adev->gfx.rlc.register_list_format); 3902 } 3903 3904 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3905 { 3906 adev->gfx.cp_fw_write_wait = false; 3907 3908 switch (adev->ip_versions[GC_HWIP][0]) { 3909 case IP_VERSION(10, 1, 10): 3910 case IP_VERSION(10, 1, 2): 3911 case IP_VERSION(10, 1, 1): 3912 case IP_VERSION(10, 1, 3): 3913 case IP_VERSION(10, 1, 4): 3914 if ((adev->gfx.me_fw_version >= 0x00000046) && 3915 (adev->gfx.me_feature_version >= 27) && 3916 (adev->gfx.pfp_fw_version >= 0x00000068) && 3917 (adev->gfx.pfp_feature_version >= 27) && 3918 (adev->gfx.mec_fw_version >= 0x0000005b) && 3919 (adev->gfx.mec_feature_version >= 27)) 3920 adev->gfx.cp_fw_write_wait = true; 3921 break; 3922 case IP_VERSION(10, 3, 0): 3923 case IP_VERSION(10, 3, 2): 3924 case IP_VERSION(10, 3, 1): 3925 case IP_VERSION(10, 3, 4): 3926 case IP_VERSION(10, 3, 5): 3927 case IP_VERSION(10, 3, 6): 3928 case IP_VERSION(10, 3, 3): 3929 case IP_VERSION(10, 3, 7): 3930 adev->gfx.cp_fw_write_wait = true; 3931 break; 3932 default: 3933 break; 3934 } 3935 3936 if (!adev->gfx.cp_fw_write_wait) 3937 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3938 } 3939 3940 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3941 { 3942 bool ret = false; 3943 3944 switch (adev->pdev->revision) { 3945 case 0xc2: 3946 case 0xc3: 3947 ret = true; 3948 break; 3949 default: 3950 ret = false; 3951 break; 3952 } 3953 3954 return ret ; 3955 } 3956 3957 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3958 { 3959 switch (adev->ip_versions[GC_HWIP][0]) { 3960 case IP_VERSION(10, 1, 10): 3961 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3962 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3963 break; 3964 default: 3965 break; 3966 } 3967 } 3968 3969 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3970 { 3971 char fw_name[40]; 3972 char ucode_prefix[30]; 3973 const char *wks = ""; 3974 int err; 3975 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3976 uint16_t version_major; 3977 uint16_t version_minor; 3978 3979 DRM_DEBUG("\n"); 3980 3981 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) && 3982 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 3983 wks = "_wks"; 3984 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 3985 3986 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 3987 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 3988 if (err) 3989 goto out; 3990 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 3991 3992 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks); 3993 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 3994 if (err) 3995 goto out; 3996 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 3997 3998 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 3999 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 4000 if (err) 4001 goto out; 4002 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4003 4004 if (!amdgpu_sriov_vf(adev)) { 4005 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 4006 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 4007 /* don't check this. There are apparently firmwares in the wild with 4008 * incorrect size in the header 4009 */ 4010 if (err == -ENODEV) 4011 goto out; 4012 if (err) 4013 dev_dbg(adev->dev, 4014 "gfx10: amdgpu_ucode_request() failed \"%s\"\n", 4015 fw_name); 4016 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4017 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4018 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4019 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4020 if (err) 4021 goto out; 4022 } 4023 4024 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4025 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 4026 if (err) 4027 goto out; 4028 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4029 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4030 4031 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4032 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 4033 if (!err) { 4034 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4035 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4036 } else { 4037 err = 0; 4038 adev->gfx.mec2_fw = NULL; 4039 } 4040 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4041 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4042 4043 gfx_v10_0_check_fw_write_wait(adev); 4044 out: 4045 if (err) { 4046 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4047 amdgpu_ucode_release(&adev->gfx.me_fw); 4048 amdgpu_ucode_release(&adev->gfx.ce_fw); 4049 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4050 amdgpu_ucode_release(&adev->gfx.mec_fw); 4051 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4052 } 4053 4054 gfx_v10_0_check_gfxoff_flag(adev); 4055 4056 return err; 4057 } 4058 4059 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4060 { 4061 u32 count = 0; 4062 const struct cs_section_def *sect = NULL; 4063 const struct cs_extent_def *ext = NULL; 4064 4065 /* begin clear state */ 4066 count += 2; 4067 /* context control state */ 4068 count += 3; 4069 4070 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4071 for (ext = sect->section; ext->extent != NULL; ++ext) { 4072 if (sect->id == SECT_CONTEXT) 4073 count += 2 + ext->reg_count; 4074 else 4075 return 0; 4076 } 4077 } 4078 4079 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4080 count += 3; 4081 /* end clear state */ 4082 count += 2; 4083 /* clear state */ 4084 count += 2; 4085 4086 return count; 4087 } 4088 4089 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4090 volatile u32 *buffer) 4091 { 4092 u32 count = 0, i; 4093 const struct cs_section_def *sect = NULL; 4094 const struct cs_extent_def *ext = NULL; 4095 int ctx_reg_offset; 4096 4097 if (adev->gfx.rlc.cs_data == NULL) 4098 return; 4099 if (buffer == NULL) 4100 return; 4101 4102 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4103 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4104 4105 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4106 buffer[count++] = cpu_to_le32(0x80000000); 4107 buffer[count++] = cpu_to_le32(0x80000000); 4108 4109 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4110 for (ext = sect->section; ext->extent != NULL; ++ext) { 4111 if (sect->id == SECT_CONTEXT) { 4112 buffer[count++] = 4113 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4114 buffer[count++] = cpu_to_le32(ext->reg_index - 4115 PACKET3_SET_CONTEXT_REG_START); 4116 for (i = 0; i < ext->reg_count; i++) 4117 buffer[count++] = cpu_to_le32(ext->extent[i]); 4118 } else { 4119 return; 4120 } 4121 } 4122 } 4123 4124 ctx_reg_offset = 4125 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4126 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4127 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4128 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4129 4130 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4131 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4132 4133 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4134 buffer[count++] = cpu_to_le32(0); 4135 } 4136 4137 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4138 { 4139 /* clear state block */ 4140 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4141 &adev->gfx.rlc.clear_state_gpu_addr, 4142 (void **)&adev->gfx.rlc.cs_ptr); 4143 4144 /* jump table block */ 4145 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4146 &adev->gfx.rlc.cp_table_gpu_addr, 4147 (void **)&adev->gfx.rlc.cp_table_ptr); 4148 } 4149 4150 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4151 { 4152 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4153 4154 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 4155 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4156 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4157 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4158 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4159 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4160 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4161 switch (adev->ip_versions[GC_HWIP][0]) { 4162 case IP_VERSION(10, 3, 0): 4163 reg_access_ctrl->spare_int = 4164 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4165 break; 4166 default: 4167 reg_access_ctrl->spare_int = 4168 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4169 break; 4170 } 4171 adev->gfx.rlc.rlcg_reg_access_supported = true; 4172 } 4173 4174 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4175 { 4176 const struct cs_section_def *cs_data; 4177 int r; 4178 4179 adev->gfx.rlc.cs_data = gfx10_cs_data; 4180 4181 cs_data = adev->gfx.rlc.cs_data; 4182 4183 if (cs_data) { 4184 /* init clear state block */ 4185 r = amdgpu_gfx_rlc_init_csb(adev); 4186 if (r) 4187 return r; 4188 } 4189 4190 /* init spm vmid with 0xf */ 4191 if (adev->gfx.rlc.funcs->update_spm_vmid) 4192 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4193 4194 4195 return 0; 4196 } 4197 4198 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4199 { 4200 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4201 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4202 } 4203 4204 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4205 { 4206 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4207 4208 amdgpu_gfx_graphics_queue_acquire(adev); 4209 } 4210 4211 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4212 { 4213 int r; 4214 u32 *hpd; 4215 const __le32 *fw_data = NULL; 4216 unsigned fw_size; 4217 u32 *fw = NULL; 4218 size_t mec_hpd_size; 4219 4220 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4221 4222 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4223 4224 /* take ownership of the relevant compute queues */ 4225 amdgpu_gfx_compute_queue_acquire(adev); 4226 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4227 4228 if (mec_hpd_size) { 4229 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4230 AMDGPU_GEM_DOMAIN_GTT, 4231 &adev->gfx.mec.hpd_eop_obj, 4232 &adev->gfx.mec.hpd_eop_gpu_addr, 4233 (void **)&hpd); 4234 if (r) { 4235 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4236 gfx_v10_0_mec_fini(adev); 4237 return r; 4238 } 4239 4240 memset(hpd, 0, mec_hpd_size); 4241 4242 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4243 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4244 } 4245 4246 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4247 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4248 4249 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4250 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4251 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4252 4253 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4254 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4255 &adev->gfx.mec.mec_fw_obj, 4256 &adev->gfx.mec.mec_fw_gpu_addr, 4257 (void **)&fw); 4258 if (r) { 4259 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4260 gfx_v10_0_mec_fini(adev); 4261 return r; 4262 } 4263 4264 memcpy(fw, fw_data, fw_size); 4265 4266 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4267 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4268 } 4269 4270 return 0; 4271 } 4272 4273 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4274 { 4275 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4276 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4277 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4278 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4279 } 4280 4281 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4282 uint32_t thread, uint32_t regno, 4283 uint32_t num, uint32_t *out) 4284 { 4285 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4286 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4287 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4288 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4289 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4290 while (num--) 4291 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4292 } 4293 4294 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4295 { 4296 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4297 * field when performing a select_se_sh so it should be 4298 * zero here */ 4299 WARN_ON(simd != 0); 4300 4301 /* type 2 wave data */ 4302 dst[(*no_fields)++] = 2; 4303 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4304 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4305 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4306 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4307 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4308 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4309 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4310 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4311 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4312 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4313 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4314 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4315 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4316 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4317 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4318 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4319 } 4320 4321 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4322 uint32_t wave, uint32_t start, 4323 uint32_t size, uint32_t *dst) 4324 { 4325 WARN_ON(simd != 0); 4326 4327 wave_read_regs( 4328 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4329 dst); 4330 } 4331 4332 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4333 uint32_t wave, uint32_t thread, 4334 uint32_t start, uint32_t size, 4335 uint32_t *dst) 4336 { 4337 wave_read_regs( 4338 adev, wave, thread, 4339 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4340 } 4341 4342 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4343 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4344 { 4345 nv_grbm_select(adev, me, pipe, q, vm); 4346 } 4347 4348 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4349 bool enable) 4350 { 4351 uint32_t data, def; 4352 4353 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4354 4355 if (enable) 4356 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4357 else 4358 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4359 4360 if (data != def) 4361 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4362 } 4363 4364 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4365 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4366 .select_se_sh = &gfx_v10_0_select_se_sh, 4367 .read_wave_data = &gfx_v10_0_read_wave_data, 4368 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4369 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4370 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4371 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4372 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4373 }; 4374 4375 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4376 { 4377 u32 gb_addr_config; 4378 4379 switch (adev->ip_versions[GC_HWIP][0]) { 4380 case IP_VERSION(10, 1, 10): 4381 case IP_VERSION(10, 1, 1): 4382 case IP_VERSION(10, 1, 2): 4383 adev->gfx.config.max_hw_contexts = 8; 4384 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4385 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4386 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4387 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4388 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4389 break; 4390 case IP_VERSION(10, 3, 0): 4391 case IP_VERSION(10, 3, 2): 4392 case IP_VERSION(10, 3, 1): 4393 case IP_VERSION(10, 3, 4): 4394 case IP_VERSION(10, 3, 5): 4395 case IP_VERSION(10, 3, 6): 4396 case IP_VERSION(10, 3, 3): 4397 case IP_VERSION(10, 3, 7): 4398 adev->gfx.config.max_hw_contexts = 8; 4399 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4400 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4401 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4402 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4403 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4404 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4405 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4406 break; 4407 case IP_VERSION(10, 1, 3): 4408 case IP_VERSION(10, 1, 4): 4409 adev->gfx.config.max_hw_contexts = 8; 4410 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4411 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4412 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4413 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4414 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4415 break; 4416 default: 4417 BUG(); 4418 break; 4419 } 4420 4421 adev->gfx.config.gb_addr_config = gb_addr_config; 4422 4423 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4424 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4425 GB_ADDR_CONFIG, NUM_PIPES); 4426 4427 adev->gfx.config.max_tile_pipes = 4428 adev->gfx.config.gb_addr_config_fields.num_pipes; 4429 4430 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4431 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4432 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4433 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4434 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4435 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4436 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4437 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4438 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4439 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4440 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4441 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4442 } 4443 4444 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4445 int me, int pipe, int queue) 4446 { 4447 struct amdgpu_ring *ring; 4448 unsigned int irq_type; 4449 unsigned int hw_prio; 4450 4451 ring = &adev->gfx.gfx_ring[ring_id]; 4452 4453 ring->me = me; 4454 ring->pipe = pipe; 4455 ring->queue = queue; 4456 4457 ring->ring_obj = NULL; 4458 ring->use_doorbell = true; 4459 4460 if (!ring_id) 4461 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4462 else 4463 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4464 ring->vm_hub = AMDGPU_GFXHUB(0); 4465 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4466 4467 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4468 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4469 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4470 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4471 hw_prio, NULL); 4472 } 4473 4474 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4475 int mec, int pipe, int queue) 4476 { 4477 unsigned irq_type; 4478 struct amdgpu_ring *ring; 4479 unsigned int hw_prio; 4480 4481 ring = &adev->gfx.compute_ring[ring_id]; 4482 4483 /* mec0 is me1 */ 4484 ring->me = mec + 1; 4485 ring->pipe = pipe; 4486 ring->queue = queue; 4487 4488 ring->ring_obj = NULL; 4489 ring->use_doorbell = true; 4490 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4491 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4492 + (ring_id * GFX10_MEC_HPD_SIZE); 4493 ring->vm_hub = AMDGPU_GFXHUB(0); 4494 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4495 4496 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4497 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4498 + ring->pipe; 4499 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4500 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4501 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4502 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4503 hw_prio, NULL); 4504 } 4505 4506 static int gfx_v10_0_sw_init(void *handle) 4507 { 4508 int i, j, k, r, ring_id = 0; 4509 struct amdgpu_kiq *kiq; 4510 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4511 4512 switch (adev->ip_versions[GC_HWIP][0]) { 4513 case IP_VERSION(10, 1, 10): 4514 case IP_VERSION(10, 1, 1): 4515 case IP_VERSION(10, 1, 2): 4516 case IP_VERSION(10, 1, 3): 4517 case IP_VERSION(10, 1, 4): 4518 adev->gfx.me.num_me = 1; 4519 adev->gfx.me.num_pipe_per_me = 1; 4520 adev->gfx.me.num_queue_per_pipe = 1; 4521 adev->gfx.mec.num_mec = 2; 4522 adev->gfx.mec.num_pipe_per_mec = 4; 4523 adev->gfx.mec.num_queue_per_pipe = 8; 4524 break; 4525 case IP_VERSION(10, 3, 0): 4526 case IP_VERSION(10, 3, 2): 4527 case IP_VERSION(10, 3, 1): 4528 case IP_VERSION(10, 3, 4): 4529 case IP_VERSION(10, 3, 5): 4530 case IP_VERSION(10, 3, 6): 4531 case IP_VERSION(10, 3, 3): 4532 case IP_VERSION(10, 3, 7): 4533 adev->gfx.me.num_me = 1; 4534 adev->gfx.me.num_pipe_per_me = 1; 4535 adev->gfx.me.num_queue_per_pipe = 1; 4536 adev->gfx.mec.num_mec = 2; 4537 adev->gfx.mec.num_pipe_per_mec = 4; 4538 adev->gfx.mec.num_queue_per_pipe = 4; 4539 break; 4540 default: 4541 adev->gfx.me.num_me = 1; 4542 adev->gfx.me.num_pipe_per_me = 1; 4543 adev->gfx.me.num_queue_per_pipe = 1; 4544 adev->gfx.mec.num_mec = 1; 4545 adev->gfx.mec.num_pipe_per_mec = 4; 4546 adev->gfx.mec.num_queue_per_pipe = 8; 4547 break; 4548 } 4549 4550 /* KIQ event */ 4551 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4552 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4553 &adev->gfx.kiq[0].irq); 4554 if (r) 4555 return r; 4556 4557 /* EOP Event */ 4558 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4559 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4560 &adev->gfx.eop_irq); 4561 if (r) 4562 return r; 4563 4564 /* Privileged reg */ 4565 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4566 &adev->gfx.priv_reg_irq); 4567 if (r) 4568 return r; 4569 4570 /* Privileged inst */ 4571 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4572 &adev->gfx.priv_inst_irq); 4573 if (r) 4574 return r; 4575 4576 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4577 4578 gfx_v10_0_me_init(adev); 4579 4580 if (adev->gfx.rlc.funcs) { 4581 if (adev->gfx.rlc.funcs->init) { 4582 r = adev->gfx.rlc.funcs->init(adev); 4583 if (r) { 4584 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4585 return r; 4586 } 4587 } 4588 } 4589 4590 r = gfx_v10_0_mec_init(adev); 4591 if (r) { 4592 DRM_ERROR("Failed to init MEC BOs!\n"); 4593 return r; 4594 } 4595 4596 /* set up the gfx ring */ 4597 for (i = 0; i < adev->gfx.me.num_me; i++) { 4598 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4599 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4600 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4601 continue; 4602 4603 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4604 i, k, j); 4605 if (r) 4606 return r; 4607 ring_id++; 4608 } 4609 } 4610 } 4611 4612 ring_id = 0; 4613 /* set up the compute queues - allocate horizontally across pipes */ 4614 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4615 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4616 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4617 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4618 k, j)) 4619 continue; 4620 4621 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4622 i, k, j); 4623 if (r) 4624 return r; 4625 4626 ring_id++; 4627 } 4628 } 4629 } 4630 4631 if (!adev->enable_mes_kiq) { 4632 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4633 if (r) { 4634 DRM_ERROR("Failed to init KIQ BOs!\n"); 4635 return r; 4636 } 4637 4638 kiq = &adev->gfx.kiq[0]; 4639 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 4640 if (r) 4641 return r; 4642 } 4643 4644 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4645 if (r) 4646 return r; 4647 4648 /* allocate visible FB for rlc auto-loading fw */ 4649 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4650 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4651 if (r) 4652 return r; 4653 } 4654 4655 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4656 4657 gfx_v10_0_gpu_early_init(adev); 4658 4659 return 0; 4660 } 4661 4662 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4663 { 4664 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4665 &adev->gfx.pfp.pfp_fw_gpu_addr, 4666 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4667 } 4668 4669 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4670 { 4671 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4672 &adev->gfx.ce.ce_fw_gpu_addr, 4673 (void **)&adev->gfx.ce.ce_fw_ptr); 4674 } 4675 4676 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4677 { 4678 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4679 &adev->gfx.me.me_fw_gpu_addr, 4680 (void **)&adev->gfx.me.me_fw_ptr); 4681 } 4682 4683 static int gfx_v10_0_sw_fini(void *handle) 4684 { 4685 int i; 4686 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4687 4688 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4689 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4690 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4691 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4692 4693 amdgpu_gfx_mqd_sw_fini(adev, 0); 4694 4695 if (!adev->enable_mes_kiq) { 4696 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4697 amdgpu_gfx_kiq_fini(adev, 0); 4698 } 4699 4700 gfx_v10_0_pfp_fini(adev); 4701 gfx_v10_0_ce_fini(adev); 4702 gfx_v10_0_me_fini(adev); 4703 gfx_v10_0_rlc_fini(adev); 4704 gfx_v10_0_mec_fini(adev); 4705 4706 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4707 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4708 4709 gfx_v10_0_free_microcode(adev); 4710 4711 return 0; 4712 } 4713 4714 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4715 u32 sh_num, u32 instance, int xcc_id) 4716 { 4717 u32 data; 4718 4719 if (instance == 0xffffffff) 4720 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4721 INSTANCE_BROADCAST_WRITES, 1); 4722 else 4723 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4724 instance); 4725 4726 if (se_num == 0xffffffff) 4727 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4728 1); 4729 else 4730 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4731 4732 if (sh_num == 0xffffffff) 4733 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4734 1); 4735 else 4736 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4737 4738 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4739 } 4740 4741 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4742 { 4743 u32 data, mask; 4744 4745 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4746 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4747 4748 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4749 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4750 4751 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4752 adev->gfx.config.max_sh_per_se); 4753 4754 return (~data) & mask; 4755 } 4756 4757 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4758 { 4759 int i, j; 4760 u32 data; 4761 u32 active_rbs = 0; 4762 u32 bitmap; 4763 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4764 adev->gfx.config.max_sh_per_se; 4765 4766 mutex_lock(&adev->grbm_idx_mutex); 4767 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4768 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4769 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4770 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 4771 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 4772 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) && 4773 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4774 continue; 4775 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4776 data = gfx_v10_0_get_rb_active_bitmap(adev); 4777 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4778 rb_bitmap_width_per_sh); 4779 } 4780 } 4781 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4782 mutex_unlock(&adev->grbm_idx_mutex); 4783 4784 adev->gfx.config.backend_enable_mask = active_rbs; 4785 adev->gfx.config.num_rbs = hweight32(active_rbs); 4786 } 4787 4788 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4789 { 4790 uint32_t num_sc; 4791 uint32_t enabled_rb_per_sh; 4792 uint32_t active_rb_bitmap; 4793 uint32_t num_rb_per_sc; 4794 uint32_t num_packer_per_sc; 4795 uint32_t pa_sc_tile_steering_override; 4796 4797 /* for ASICs that integrates GFX v10.3 4798 * pa_sc_tile_steering_override should be set to 0 */ 4799 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 4800 return 0; 4801 4802 /* init num_sc */ 4803 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4804 adev->gfx.config.num_sc_per_sh; 4805 /* init num_rb_per_sc */ 4806 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4807 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4808 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4809 /* init num_packer_per_sc */ 4810 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4811 4812 pa_sc_tile_steering_override = 0; 4813 pa_sc_tile_steering_override |= 4814 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4815 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4816 pa_sc_tile_steering_override |= 4817 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4818 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4819 pa_sc_tile_steering_override |= 4820 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4821 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4822 4823 return pa_sc_tile_steering_override; 4824 } 4825 4826 #define DEFAULT_SH_MEM_BASES (0x6000) 4827 4828 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 4829 uint32_t first_vmid, 4830 uint32_t last_vmid) 4831 { 4832 uint32_t data; 4833 uint32_t trap_config_vmid_mask = 0; 4834 int i; 4835 4836 /* Calculate trap config vmid mask */ 4837 for (i = first_vmid; i < last_vmid; i++) 4838 trap_config_vmid_mask |= (1 << i); 4839 4840 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 4841 VMID_SEL, trap_config_vmid_mask); 4842 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 4843 TRAP_EN, 1); 4844 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 4845 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 4846 4847 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 4848 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 4849 } 4850 4851 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4852 { 4853 int i; 4854 uint32_t sh_mem_bases; 4855 4856 /* 4857 * Configure apertures: 4858 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4859 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4860 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4861 */ 4862 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4863 4864 mutex_lock(&adev->srbm_mutex); 4865 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4866 nv_grbm_select(adev, 0, 0, 0, i); 4867 /* CP and shaders */ 4868 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4869 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4870 } 4871 nv_grbm_select(adev, 0, 0, 0, 0); 4872 mutex_unlock(&adev->srbm_mutex); 4873 4874 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4875 access. These should be enabled by FW for target VMIDs. */ 4876 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4877 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4878 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4879 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4880 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4881 } 4882 4883 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 4884 AMDGPU_NUM_VMID); 4885 } 4886 4887 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4888 { 4889 int vmid; 4890 4891 /* 4892 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4893 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4894 * the driver can enable them for graphics. VMID0 should maintain 4895 * access so that HWS firmware can save/restore entries. 4896 */ 4897 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4898 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4899 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4900 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4901 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4902 } 4903 } 4904 4905 4906 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4907 { 4908 int i, j, k; 4909 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4910 u32 tmp, wgp_active_bitmap = 0; 4911 u32 gcrd_targets_disable_tcp = 0; 4912 u32 utcl_invreq_disable = 0; 4913 /* 4914 * GCRD_TARGETS_DISABLE field contains 4915 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4916 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4917 */ 4918 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4919 2 * max_wgp_per_sh + /* TCP */ 4920 max_wgp_per_sh + /* SQC */ 4921 4); /* GL1C */ 4922 /* 4923 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4924 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4925 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4926 */ 4927 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4928 2 * max_wgp_per_sh + /* TCP */ 4929 2 * max_wgp_per_sh + /* SQC */ 4930 4 + /* RMI */ 4931 1); /* SQG */ 4932 4933 mutex_lock(&adev->grbm_idx_mutex); 4934 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4935 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4936 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4937 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4938 /* 4939 * Set corresponding TCP bits for the inactive WGPs in 4940 * GCRD_SA_TARGETS_DISABLE 4941 */ 4942 gcrd_targets_disable_tcp = 0; 4943 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4944 utcl_invreq_disable = 0; 4945 4946 for (k = 0; k < max_wgp_per_sh; k++) { 4947 if (!(wgp_active_bitmap & (1 << k))) { 4948 gcrd_targets_disable_tcp |= 3 << (2 * k); 4949 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 4950 utcl_invreq_disable |= (3 << (2 * k)) | 4951 (3 << (2 * (max_wgp_per_sh + k))); 4952 } 4953 } 4954 4955 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4956 /* only override TCP & SQC bits */ 4957 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 4958 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4959 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4960 4961 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4962 /* only override TCP & SQC bits */ 4963 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 4964 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4965 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4966 } 4967 } 4968 4969 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4970 mutex_unlock(&adev->grbm_idx_mutex); 4971 } 4972 4973 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4974 { 4975 /* TCCs are global (not instanced). */ 4976 uint32_t tcc_disable; 4977 4978 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 4979 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 4980 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 4981 } else { 4982 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4983 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4984 } 4985 4986 adev->gfx.config.tcc_disabled_mask = 4987 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4988 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4989 } 4990 4991 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4992 { 4993 u32 tmp; 4994 int i; 4995 4996 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4997 4998 gfx_v10_0_setup_rb(adev); 4999 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5000 gfx_v10_0_get_tcc_info(adev); 5001 adev->gfx.config.pa_sc_tile_steering_override = 5002 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5003 5004 /* XXX SH_MEM regs */ 5005 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5006 mutex_lock(&adev->srbm_mutex); 5007 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 5008 nv_grbm_select(adev, 0, 0, 0, i); 5009 /* CP and shaders */ 5010 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5011 if (i != 0) { 5012 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5013 (adev->gmc.private_aperture_start >> 48)); 5014 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5015 (adev->gmc.shared_aperture_start >> 48)); 5016 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5017 } 5018 } 5019 nv_grbm_select(adev, 0, 0, 0, 0); 5020 5021 mutex_unlock(&adev->srbm_mutex); 5022 5023 gfx_v10_0_init_compute_vmid(adev); 5024 gfx_v10_0_init_gds_vmid(adev); 5025 5026 } 5027 5028 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5029 bool enable) 5030 { 5031 u32 tmp; 5032 5033 if (amdgpu_sriov_vf(adev)) 5034 return; 5035 5036 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5037 5038 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5039 enable ? 1 : 0); 5040 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5041 enable ? 1 : 0); 5042 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5043 enable ? 1 : 0); 5044 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5045 enable ? 1 : 0); 5046 5047 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5048 } 5049 5050 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5051 { 5052 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5053 5054 /* csib */ 5055 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5056 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5057 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5058 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5059 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5060 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5061 } else { 5062 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5063 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5064 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5065 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5066 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5067 } 5068 return 0; 5069 } 5070 5071 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5072 { 5073 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5074 5075 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5076 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5077 } 5078 5079 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5080 { 5081 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5082 udelay(50); 5083 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5084 udelay(50); 5085 } 5086 5087 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5088 bool enable) 5089 { 5090 uint32_t rlc_pg_cntl; 5091 5092 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5093 5094 if (!enable) { 5095 /* RLC_PG_CNTL[23] = 0 (default) 5096 * RLC will wait for handshake acks with SMU 5097 * GFXOFF will be enabled 5098 * RLC_PG_CNTL[23] = 1 5099 * RLC will not issue any message to SMU 5100 * hence no handshake between SMU & RLC 5101 * GFXOFF will be disabled 5102 */ 5103 rlc_pg_cntl |= 0x800000; 5104 } else 5105 rlc_pg_cntl &= ~0x800000; 5106 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5107 } 5108 5109 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5110 { 5111 /* TODO: enable rlc & smu handshake until smu 5112 * and gfxoff feature works as expected */ 5113 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5114 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5115 5116 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5117 udelay(50); 5118 } 5119 5120 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5121 { 5122 uint32_t tmp; 5123 5124 /* enable Save Restore Machine */ 5125 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5126 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5127 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5128 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5129 } 5130 5131 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5132 { 5133 const struct rlc_firmware_header_v2_0 *hdr; 5134 const __le32 *fw_data; 5135 unsigned i, fw_size; 5136 5137 if (!adev->gfx.rlc_fw) 5138 return -EINVAL; 5139 5140 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5141 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5142 5143 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5144 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5145 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5146 5147 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5148 RLCG_UCODE_LOADING_START_ADDRESS); 5149 5150 for (i = 0; i < fw_size; i++) 5151 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5152 le32_to_cpup(fw_data++)); 5153 5154 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5155 5156 return 0; 5157 } 5158 5159 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5160 { 5161 int r; 5162 5163 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5164 adev->psp.autoload_supported) { 5165 5166 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5167 if (r) 5168 return r; 5169 5170 gfx_v10_0_init_csb(adev); 5171 5172 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5173 gfx_v10_0_rlc_enable_srm(adev); 5174 } else { 5175 if (amdgpu_sriov_vf(adev)) { 5176 gfx_v10_0_init_csb(adev); 5177 return 0; 5178 } 5179 5180 adev->gfx.rlc.funcs->stop(adev); 5181 5182 /* disable CG */ 5183 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5184 5185 /* disable PG */ 5186 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5187 5188 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5189 /* legacy rlc firmware loading */ 5190 r = gfx_v10_0_rlc_load_microcode(adev); 5191 if (r) 5192 return r; 5193 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5194 /* rlc backdoor autoload firmware */ 5195 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5196 if (r) 5197 return r; 5198 } 5199 5200 gfx_v10_0_init_csb(adev); 5201 5202 adev->gfx.rlc.funcs->start(adev); 5203 5204 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5205 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5206 if (r) 5207 return r; 5208 } 5209 } 5210 return 0; 5211 } 5212 5213 static struct { 5214 FIRMWARE_ID id; 5215 unsigned int offset; 5216 unsigned int size; 5217 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5218 5219 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5220 { 5221 int ret; 5222 RLC_TABLE_OF_CONTENT *rlc_toc; 5223 5224 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5225 AMDGPU_GEM_DOMAIN_GTT, 5226 &adev->gfx.rlc.rlc_toc_bo, 5227 &adev->gfx.rlc.rlc_toc_gpu_addr, 5228 (void **)&adev->gfx.rlc.rlc_toc_buf); 5229 if (ret) { 5230 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5231 return ret; 5232 } 5233 5234 /* Copy toc from psp sos fw to rlc toc buffer */ 5235 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5236 5237 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5238 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5239 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5240 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5241 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5242 /* Offset needs 4KB alignment */ 5243 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5244 } 5245 5246 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5247 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5248 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5249 5250 rlc_toc++; 5251 } 5252 5253 return 0; 5254 } 5255 5256 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5257 { 5258 uint32_t total_size = 0; 5259 FIRMWARE_ID id; 5260 int ret; 5261 5262 ret = gfx_v10_0_parse_rlc_toc(adev); 5263 if (ret) { 5264 dev_err(adev->dev, "failed to parse rlc toc\n"); 5265 return 0; 5266 } 5267 5268 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5269 total_size += rlc_autoload_info[id].size; 5270 5271 /* In case the offset in rlc toc ucode is aligned */ 5272 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5273 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5274 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5275 5276 return total_size; 5277 } 5278 5279 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5280 { 5281 int r; 5282 uint32_t total_size; 5283 5284 total_size = gfx_v10_0_calc_toc_total_size(adev); 5285 5286 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5287 AMDGPU_GEM_DOMAIN_GTT, 5288 &adev->gfx.rlc.rlc_autoload_bo, 5289 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5290 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5291 if (r) { 5292 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5293 return r; 5294 } 5295 5296 return 0; 5297 } 5298 5299 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5300 { 5301 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5302 &adev->gfx.rlc.rlc_toc_gpu_addr, 5303 (void **)&adev->gfx.rlc.rlc_toc_buf); 5304 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5305 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5306 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5307 } 5308 5309 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5310 FIRMWARE_ID id, 5311 const void *fw_data, 5312 uint32_t fw_size) 5313 { 5314 uint32_t toc_offset; 5315 uint32_t toc_fw_size; 5316 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5317 5318 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5319 return; 5320 5321 toc_offset = rlc_autoload_info[id].offset; 5322 toc_fw_size = rlc_autoload_info[id].size; 5323 5324 if (fw_size == 0) 5325 fw_size = toc_fw_size; 5326 5327 if (fw_size > toc_fw_size) 5328 fw_size = toc_fw_size; 5329 5330 memcpy(ptr + toc_offset, fw_data, fw_size); 5331 5332 if (fw_size < toc_fw_size) 5333 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5334 } 5335 5336 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5337 { 5338 void *data; 5339 uint32_t size; 5340 5341 data = adev->gfx.rlc.rlc_toc_buf; 5342 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5343 5344 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5345 FIRMWARE_ID_RLC_TOC, 5346 data, size); 5347 } 5348 5349 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5350 { 5351 const __le32 *fw_data; 5352 uint32_t fw_size; 5353 const struct gfx_firmware_header_v1_0 *cp_hdr; 5354 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5355 5356 /* pfp ucode */ 5357 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5358 adev->gfx.pfp_fw->data; 5359 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5360 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5361 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5362 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5363 FIRMWARE_ID_CP_PFP, 5364 fw_data, fw_size); 5365 5366 /* ce ucode */ 5367 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5368 adev->gfx.ce_fw->data; 5369 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5370 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5371 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5372 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5373 FIRMWARE_ID_CP_CE, 5374 fw_data, fw_size); 5375 5376 /* me ucode */ 5377 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5378 adev->gfx.me_fw->data; 5379 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5380 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5381 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5382 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5383 FIRMWARE_ID_CP_ME, 5384 fw_data, fw_size); 5385 5386 /* rlc ucode */ 5387 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5388 adev->gfx.rlc_fw->data; 5389 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5390 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5391 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5392 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5393 FIRMWARE_ID_RLC_G_UCODE, 5394 fw_data, fw_size); 5395 5396 /* mec1 ucode */ 5397 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5398 adev->gfx.mec_fw->data; 5399 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5400 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5401 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5402 cp_hdr->jt_size * 4; 5403 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5404 FIRMWARE_ID_CP_MEC, 5405 fw_data, fw_size); 5406 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5407 } 5408 5409 /* Temporarily put sdma part here */ 5410 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5411 { 5412 const __le32 *fw_data; 5413 uint32_t fw_size; 5414 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5415 int i; 5416 5417 for (i = 0; i < adev->sdma.num_instances; i++) { 5418 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5419 adev->sdma.instance[i].fw->data; 5420 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5421 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5422 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5423 5424 if (i == 0) { 5425 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5426 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5427 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5428 FIRMWARE_ID_SDMA0_JT, 5429 (uint32_t *)fw_data + 5430 sdma_hdr->jt_offset, 5431 sdma_hdr->jt_size * 4); 5432 } else if (i == 1) { 5433 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5434 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5435 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5436 FIRMWARE_ID_SDMA1_JT, 5437 (uint32_t *)fw_data + 5438 sdma_hdr->jt_offset, 5439 sdma_hdr->jt_size * 4); 5440 } 5441 } 5442 } 5443 5444 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5445 { 5446 uint32_t rlc_g_offset, rlc_g_size, tmp; 5447 uint64_t gpu_addr; 5448 5449 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5450 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5451 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5452 5453 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5454 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5455 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5456 5457 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5458 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5459 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5460 5461 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5462 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5463 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5464 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5465 return -EINVAL; 5466 } 5467 5468 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5469 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5470 DRM_ERROR("RLC ROM should halt itself\n"); 5471 return -EINVAL; 5472 } 5473 5474 return 0; 5475 } 5476 5477 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5478 { 5479 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5480 uint32_t tmp; 5481 int i; 5482 uint64_t addr; 5483 5484 /* Trigger an invalidation of the L1 instruction caches */ 5485 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5486 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5487 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5488 5489 /* Wait for invalidation complete */ 5490 for (i = 0; i < usec_timeout; i++) { 5491 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5492 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5493 INVALIDATE_CACHE_COMPLETE)) 5494 break; 5495 udelay(1); 5496 } 5497 5498 if (i >= usec_timeout) { 5499 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5500 return -EINVAL; 5501 } 5502 5503 /* Program me ucode address into intruction cache address register */ 5504 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5505 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5506 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5507 lower_32_bits(addr) & 0xFFFFF000); 5508 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5509 upper_32_bits(addr)); 5510 5511 return 0; 5512 } 5513 5514 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5515 { 5516 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5517 uint32_t tmp; 5518 int i; 5519 uint64_t addr; 5520 5521 /* Trigger an invalidation of the L1 instruction caches */ 5522 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5523 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5524 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5525 5526 /* Wait for invalidation complete */ 5527 for (i = 0; i < usec_timeout; i++) { 5528 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5529 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5530 INVALIDATE_CACHE_COMPLETE)) 5531 break; 5532 udelay(1); 5533 } 5534 5535 if (i >= usec_timeout) { 5536 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5537 return -EINVAL; 5538 } 5539 5540 /* Program ce ucode address into intruction cache address register */ 5541 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5542 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5543 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5544 lower_32_bits(addr) & 0xFFFFF000); 5545 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5546 upper_32_bits(addr)); 5547 5548 return 0; 5549 } 5550 5551 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5552 { 5553 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5554 uint32_t tmp; 5555 int i; 5556 uint64_t addr; 5557 5558 /* Trigger an invalidation of the L1 instruction caches */ 5559 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5560 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5561 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5562 5563 /* Wait for invalidation complete */ 5564 for (i = 0; i < usec_timeout; i++) { 5565 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5566 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5567 INVALIDATE_CACHE_COMPLETE)) 5568 break; 5569 udelay(1); 5570 } 5571 5572 if (i >= usec_timeout) { 5573 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5574 return -EINVAL; 5575 } 5576 5577 /* Program pfp ucode address into intruction cache address register */ 5578 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5579 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5580 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5581 lower_32_bits(addr) & 0xFFFFF000); 5582 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5583 upper_32_bits(addr)); 5584 5585 return 0; 5586 } 5587 5588 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5589 { 5590 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5591 uint32_t tmp; 5592 int i; 5593 uint64_t addr; 5594 5595 /* Trigger an invalidation of the L1 instruction caches */ 5596 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5597 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5598 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5599 5600 /* Wait for invalidation complete */ 5601 for (i = 0; i < usec_timeout; i++) { 5602 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5603 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5604 INVALIDATE_CACHE_COMPLETE)) 5605 break; 5606 udelay(1); 5607 } 5608 5609 if (i >= usec_timeout) { 5610 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5611 return -EINVAL; 5612 } 5613 5614 /* Program mec1 ucode address into intruction cache address register */ 5615 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5616 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5617 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5618 lower_32_bits(addr) & 0xFFFFF000); 5619 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5620 upper_32_bits(addr)); 5621 5622 return 0; 5623 } 5624 5625 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5626 { 5627 uint32_t cp_status; 5628 uint32_t bootload_status; 5629 int i, r; 5630 5631 for (i = 0; i < adev->usec_timeout; i++) { 5632 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5633 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5634 if ((cp_status == 0) && 5635 (REG_GET_FIELD(bootload_status, 5636 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5637 break; 5638 } 5639 udelay(1); 5640 } 5641 5642 if (i >= adev->usec_timeout) { 5643 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5644 return -ETIMEDOUT; 5645 } 5646 5647 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5648 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5649 if (r) 5650 return r; 5651 5652 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5653 if (r) 5654 return r; 5655 5656 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5657 if (r) 5658 return r; 5659 5660 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5661 if (r) 5662 return r; 5663 } 5664 5665 return 0; 5666 } 5667 5668 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5669 { 5670 int i; 5671 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5672 5673 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5674 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5675 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5676 5677 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5678 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5679 } else { 5680 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5681 } 5682 5683 if (adev->job_hang && !enable) 5684 return 0; 5685 5686 for (i = 0; i < adev->usec_timeout; i++) { 5687 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5688 break; 5689 udelay(1); 5690 } 5691 5692 if (i >= adev->usec_timeout) 5693 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5694 5695 return 0; 5696 } 5697 5698 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5699 { 5700 int r; 5701 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5702 const __le32 *fw_data; 5703 unsigned i, fw_size; 5704 uint32_t tmp; 5705 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5706 5707 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5708 adev->gfx.pfp_fw->data; 5709 5710 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5711 5712 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5713 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5714 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5715 5716 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5717 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5718 &adev->gfx.pfp.pfp_fw_obj, 5719 &adev->gfx.pfp.pfp_fw_gpu_addr, 5720 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5721 if (r) { 5722 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5723 gfx_v10_0_pfp_fini(adev); 5724 return r; 5725 } 5726 5727 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5728 5729 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5730 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5731 5732 /* Trigger an invalidation of the L1 instruction caches */ 5733 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5734 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5735 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5736 5737 /* Wait for invalidation complete */ 5738 for (i = 0; i < usec_timeout; i++) { 5739 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5740 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5741 INVALIDATE_CACHE_COMPLETE)) 5742 break; 5743 udelay(1); 5744 } 5745 5746 if (i >= usec_timeout) { 5747 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5748 return -EINVAL; 5749 } 5750 5751 if (amdgpu_emu_mode == 1) 5752 adev->hdp.funcs->flush_hdp(adev, NULL); 5753 5754 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5755 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5756 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5757 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5758 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5759 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5760 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5761 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5762 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5763 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5764 5765 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5766 5767 for (i = 0; i < pfp_hdr->jt_size; i++) 5768 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5769 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5770 5771 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5772 5773 return 0; 5774 } 5775 5776 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5777 { 5778 int r; 5779 const struct gfx_firmware_header_v1_0 *ce_hdr; 5780 const __le32 *fw_data; 5781 unsigned i, fw_size; 5782 uint32_t tmp; 5783 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5784 5785 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5786 adev->gfx.ce_fw->data; 5787 5788 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5789 5790 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5791 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5792 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5793 5794 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5795 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5796 &adev->gfx.ce.ce_fw_obj, 5797 &adev->gfx.ce.ce_fw_gpu_addr, 5798 (void **)&adev->gfx.ce.ce_fw_ptr); 5799 if (r) { 5800 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5801 gfx_v10_0_ce_fini(adev); 5802 return r; 5803 } 5804 5805 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5806 5807 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5808 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5809 5810 /* Trigger an invalidation of the L1 instruction caches */ 5811 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5812 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5813 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5814 5815 /* Wait for invalidation complete */ 5816 for (i = 0; i < usec_timeout; i++) { 5817 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5818 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5819 INVALIDATE_CACHE_COMPLETE)) 5820 break; 5821 udelay(1); 5822 } 5823 5824 if (i >= usec_timeout) { 5825 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5826 return -EINVAL; 5827 } 5828 5829 if (amdgpu_emu_mode == 1) 5830 adev->hdp.funcs->flush_hdp(adev, NULL); 5831 5832 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5833 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5834 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5835 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5836 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5837 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5838 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5839 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5840 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5841 5842 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5843 5844 for (i = 0; i < ce_hdr->jt_size; i++) 5845 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5846 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5847 5848 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5849 5850 return 0; 5851 } 5852 5853 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5854 { 5855 int r; 5856 const struct gfx_firmware_header_v1_0 *me_hdr; 5857 const __le32 *fw_data; 5858 unsigned i, fw_size; 5859 uint32_t tmp; 5860 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5861 5862 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5863 adev->gfx.me_fw->data; 5864 5865 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5866 5867 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5868 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5869 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5870 5871 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5872 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5873 &adev->gfx.me.me_fw_obj, 5874 &adev->gfx.me.me_fw_gpu_addr, 5875 (void **)&adev->gfx.me.me_fw_ptr); 5876 if (r) { 5877 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5878 gfx_v10_0_me_fini(adev); 5879 return r; 5880 } 5881 5882 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5883 5884 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5885 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5886 5887 /* Trigger an invalidation of the L1 instruction caches */ 5888 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5889 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5890 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5891 5892 /* Wait for invalidation complete */ 5893 for (i = 0; i < usec_timeout; i++) { 5894 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5895 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5896 INVALIDATE_CACHE_COMPLETE)) 5897 break; 5898 udelay(1); 5899 } 5900 5901 if (i >= usec_timeout) { 5902 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5903 return -EINVAL; 5904 } 5905 5906 if (amdgpu_emu_mode == 1) 5907 adev->hdp.funcs->flush_hdp(adev, NULL); 5908 5909 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5910 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5911 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5912 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5913 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5914 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5915 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5916 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5917 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5918 5919 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5920 5921 for (i = 0; i < me_hdr->jt_size; i++) 5922 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5923 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5924 5925 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5926 5927 return 0; 5928 } 5929 5930 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5931 { 5932 int r; 5933 5934 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5935 return -EINVAL; 5936 5937 gfx_v10_0_cp_gfx_enable(adev, false); 5938 5939 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5940 if (r) { 5941 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5942 return r; 5943 } 5944 5945 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5946 if (r) { 5947 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5948 return r; 5949 } 5950 5951 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5952 if (r) { 5953 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5954 return r; 5955 } 5956 5957 return 0; 5958 } 5959 5960 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5961 { 5962 struct amdgpu_ring *ring; 5963 const struct cs_section_def *sect = NULL; 5964 const struct cs_extent_def *ext = NULL; 5965 int r, i; 5966 int ctx_reg_offset; 5967 5968 /* init the CP */ 5969 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5970 adev->gfx.config.max_hw_contexts - 1); 5971 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5972 5973 gfx_v10_0_cp_gfx_enable(adev, true); 5974 5975 ring = &adev->gfx.gfx_ring[0]; 5976 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5977 if (r) { 5978 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5979 return r; 5980 } 5981 5982 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5983 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5984 5985 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5986 amdgpu_ring_write(ring, 0x80000000); 5987 amdgpu_ring_write(ring, 0x80000000); 5988 5989 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5990 for (ext = sect->section; ext->extent != NULL; ++ext) { 5991 if (sect->id == SECT_CONTEXT) { 5992 amdgpu_ring_write(ring, 5993 PACKET3(PACKET3_SET_CONTEXT_REG, 5994 ext->reg_count)); 5995 amdgpu_ring_write(ring, ext->reg_index - 5996 PACKET3_SET_CONTEXT_REG_START); 5997 for (i = 0; i < ext->reg_count; i++) 5998 amdgpu_ring_write(ring, ext->extent[i]); 5999 } 6000 } 6001 } 6002 6003 ctx_reg_offset = 6004 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6005 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6006 amdgpu_ring_write(ring, ctx_reg_offset); 6007 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6008 6009 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6010 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6011 6012 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6013 amdgpu_ring_write(ring, 0); 6014 6015 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6016 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6017 amdgpu_ring_write(ring, 0x8000); 6018 amdgpu_ring_write(ring, 0x8000); 6019 6020 amdgpu_ring_commit(ring); 6021 6022 /* submit cs packet to copy state 0 to next available state */ 6023 if (adev->gfx.num_gfx_rings > 1) { 6024 /* maximum supported gfx ring is 2 */ 6025 ring = &adev->gfx.gfx_ring[1]; 6026 r = amdgpu_ring_alloc(ring, 2); 6027 if (r) { 6028 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6029 return r; 6030 } 6031 6032 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6033 amdgpu_ring_write(ring, 0); 6034 6035 amdgpu_ring_commit(ring); 6036 } 6037 return 0; 6038 } 6039 6040 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6041 CP_PIPE_ID pipe) 6042 { 6043 u32 tmp; 6044 6045 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6046 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6047 6048 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6049 } 6050 6051 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6052 struct amdgpu_ring *ring) 6053 { 6054 u32 tmp; 6055 6056 if (!amdgpu_async_gfx_ring) { 6057 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6058 if (ring->use_doorbell) { 6059 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6060 DOORBELL_OFFSET, ring->doorbell_index); 6061 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6062 DOORBELL_EN, 1); 6063 } else { 6064 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6065 DOORBELL_EN, 0); 6066 } 6067 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6068 } 6069 switch (adev->ip_versions[GC_HWIP][0]) { 6070 case IP_VERSION(10, 3, 0): 6071 case IP_VERSION(10, 3, 2): 6072 case IP_VERSION(10, 3, 1): 6073 case IP_VERSION(10, 3, 4): 6074 case IP_VERSION(10, 3, 5): 6075 case IP_VERSION(10, 3, 6): 6076 case IP_VERSION(10, 3, 3): 6077 case IP_VERSION(10, 3, 7): 6078 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6079 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6080 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6081 6082 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6083 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6084 break; 6085 default: 6086 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6087 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6088 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6089 6090 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6091 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6092 break; 6093 } 6094 } 6095 6096 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6097 { 6098 struct amdgpu_ring *ring; 6099 u32 tmp; 6100 u32 rb_bufsz; 6101 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6102 6103 /* Set the write pointer delay */ 6104 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6105 6106 /* set the RB to use vmid 0 */ 6107 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6108 6109 /* Init gfx ring 0 for pipe 0 */ 6110 mutex_lock(&adev->srbm_mutex); 6111 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6112 6113 /* Set ring buffer size */ 6114 ring = &adev->gfx.gfx_ring[0]; 6115 rb_bufsz = order_base_2(ring->ring_size / 8); 6116 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6117 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6118 #ifdef __BIG_ENDIAN 6119 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6120 #endif 6121 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6122 6123 /* Initialize the ring buffer's write pointers */ 6124 ring->wptr = 0; 6125 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6126 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6127 6128 /* set the wb address wether it's enabled or not */ 6129 rptr_addr = ring->rptr_gpu_addr; 6130 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6131 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6132 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6133 6134 wptr_gpu_addr = ring->wptr_gpu_addr; 6135 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6136 lower_32_bits(wptr_gpu_addr)); 6137 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6138 upper_32_bits(wptr_gpu_addr)); 6139 6140 mdelay(1); 6141 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6142 6143 rb_addr = ring->gpu_addr >> 8; 6144 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6145 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6146 6147 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6148 6149 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6150 mutex_unlock(&adev->srbm_mutex); 6151 6152 /* Init gfx ring 1 for pipe 1 */ 6153 if (adev->gfx.num_gfx_rings > 1) { 6154 mutex_lock(&adev->srbm_mutex); 6155 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6156 /* maximum supported gfx ring is 2 */ 6157 ring = &adev->gfx.gfx_ring[1]; 6158 rb_bufsz = order_base_2(ring->ring_size / 8); 6159 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6160 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6161 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6162 /* Initialize the ring buffer's write pointers */ 6163 ring->wptr = 0; 6164 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6165 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6166 /* Set the wb address wether it's enabled or not */ 6167 rptr_addr = ring->rptr_gpu_addr; 6168 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6169 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6170 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6171 wptr_gpu_addr = ring->wptr_gpu_addr; 6172 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6173 lower_32_bits(wptr_gpu_addr)); 6174 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6175 upper_32_bits(wptr_gpu_addr)); 6176 6177 mdelay(1); 6178 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6179 6180 rb_addr = ring->gpu_addr >> 8; 6181 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6182 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6183 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6184 6185 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6186 mutex_unlock(&adev->srbm_mutex); 6187 } 6188 /* Switch to pipe 0 */ 6189 mutex_lock(&adev->srbm_mutex); 6190 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6191 mutex_unlock(&adev->srbm_mutex); 6192 6193 /* start the ring */ 6194 gfx_v10_0_cp_gfx_start(adev); 6195 6196 return 0; 6197 } 6198 6199 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6200 { 6201 if (enable) { 6202 switch (adev->ip_versions[GC_HWIP][0]) { 6203 case IP_VERSION(10, 3, 0): 6204 case IP_VERSION(10, 3, 2): 6205 case IP_VERSION(10, 3, 1): 6206 case IP_VERSION(10, 3, 4): 6207 case IP_VERSION(10, 3, 5): 6208 case IP_VERSION(10, 3, 6): 6209 case IP_VERSION(10, 3, 3): 6210 case IP_VERSION(10, 3, 7): 6211 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6212 break; 6213 default: 6214 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6215 break; 6216 } 6217 } else { 6218 switch (adev->ip_versions[GC_HWIP][0]) { 6219 case IP_VERSION(10, 3, 0): 6220 case IP_VERSION(10, 3, 2): 6221 case IP_VERSION(10, 3, 1): 6222 case IP_VERSION(10, 3, 4): 6223 case IP_VERSION(10, 3, 5): 6224 case IP_VERSION(10, 3, 6): 6225 case IP_VERSION(10, 3, 3): 6226 case IP_VERSION(10, 3, 7): 6227 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6228 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6229 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6230 break; 6231 default: 6232 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6233 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6234 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6235 break; 6236 } 6237 adev->gfx.kiq[0].ring.sched.ready = false; 6238 } 6239 udelay(50); 6240 } 6241 6242 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6243 { 6244 const struct gfx_firmware_header_v1_0 *mec_hdr; 6245 const __le32 *fw_data; 6246 unsigned i; 6247 u32 tmp; 6248 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6249 6250 if (!adev->gfx.mec_fw) 6251 return -EINVAL; 6252 6253 gfx_v10_0_cp_compute_enable(adev, false); 6254 6255 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6256 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6257 6258 fw_data = (const __le32 *) 6259 (adev->gfx.mec_fw->data + 6260 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6261 6262 /* Trigger an invalidation of the L1 instruction caches */ 6263 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6264 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6265 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6266 6267 /* Wait for invalidation complete */ 6268 for (i = 0; i < usec_timeout; i++) { 6269 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6270 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6271 INVALIDATE_CACHE_COMPLETE)) 6272 break; 6273 udelay(1); 6274 } 6275 6276 if (i >= usec_timeout) { 6277 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6278 return -EINVAL; 6279 } 6280 6281 if (amdgpu_emu_mode == 1) 6282 adev->hdp.funcs->flush_hdp(adev, NULL); 6283 6284 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6285 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6286 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6287 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6288 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6289 6290 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6291 0xFFFFF000); 6292 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6293 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6294 6295 /* MEC1 */ 6296 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6297 6298 for (i = 0; i < mec_hdr->jt_size; i++) 6299 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6300 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6301 6302 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6303 6304 /* 6305 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6306 * different microcode than MEC1. 6307 */ 6308 6309 return 0; 6310 } 6311 6312 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6313 { 6314 uint32_t tmp; 6315 struct amdgpu_device *adev = ring->adev; 6316 6317 /* tell RLC which is KIQ queue */ 6318 switch (adev->ip_versions[GC_HWIP][0]) { 6319 case IP_VERSION(10, 3, 0): 6320 case IP_VERSION(10, 3, 2): 6321 case IP_VERSION(10, 3, 1): 6322 case IP_VERSION(10, 3, 4): 6323 case IP_VERSION(10, 3, 5): 6324 case IP_VERSION(10, 3, 6): 6325 case IP_VERSION(10, 3, 3): 6326 case IP_VERSION(10, 3, 7): 6327 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6328 tmp &= 0xffffff00; 6329 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6330 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6331 tmp |= 0x80; 6332 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6333 break; 6334 default: 6335 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6336 tmp &= 0xffffff00; 6337 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6338 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6339 tmp |= 0x80; 6340 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6341 break; 6342 } 6343 } 6344 6345 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6346 struct v10_gfx_mqd *mqd, 6347 struct amdgpu_mqd_prop *prop) 6348 { 6349 bool priority = 0; 6350 u32 tmp; 6351 6352 /* set up default queue priority level 6353 * 0x0 = low priority, 0x1 = high priority 6354 */ 6355 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6356 priority = 1; 6357 6358 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6359 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6360 mqd->cp_gfx_hqd_queue_priority = tmp; 6361 } 6362 6363 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6364 struct amdgpu_mqd_prop *prop) 6365 { 6366 struct v10_gfx_mqd *mqd = m; 6367 uint64_t hqd_gpu_addr, wb_gpu_addr; 6368 uint32_t tmp; 6369 uint32_t rb_bufsz; 6370 6371 /* set up gfx hqd wptr */ 6372 mqd->cp_gfx_hqd_wptr = 0; 6373 mqd->cp_gfx_hqd_wptr_hi = 0; 6374 6375 /* set the pointer to the MQD */ 6376 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6377 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6378 6379 /* set up mqd control */ 6380 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6381 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6382 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6383 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6384 mqd->cp_gfx_mqd_control = tmp; 6385 6386 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6387 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6388 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6389 mqd->cp_gfx_hqd_vmid = 0; 6390 6391 /* set up gfx queue priority */ 6392 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6393 6394 /* set up time quantum */ 6395 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6396 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6397 mqd->cp_gfx_hqd_quantum = tmp; 6398 6399 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6400 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6401 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6402 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6403 6404 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6405 wb_gpu_addr = prop->rptr_gpu_addr; 6406 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6407 mqd->cp_gfx_hqd_rptr_addr_hi = 6408 upper_32_bits(wb_gpu_addr) & 0xffff; 6409 6410 /* set up rb_wptr_poll addr */ 6411 wb_gpu_addr = prop->wptr_gpu_addr; 6412 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6413 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6414 6415 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6416 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6417 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6418 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6419 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6420 #ifdef __BIG_ENDIAN 6421 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6422 #endif 6423 mqd->cp_gfx_hqd_cntl = tmp; 6424 6425 /* set up cp_doorbell_control */ 6426 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6427 if (prop->use_doorbell) { 6428 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6429 DOORBELL_OFFSET, prop->doorbell_index); 6430 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6431 DOORBELL_EN, 1); 6432 } else 6433 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6434 DOORBELL_EN, 0); 6435 mqd->cp_rb_doorbell_control = tmp; 6436 6437 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6438 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6439 6440 /* active the queue */ 6441 mqd->cp_gfx_hqd_active = 1; 6442 6443 return 0; 6444 } 6445 6446 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6447 { 6448 struct amdgpu_device *adev = ring->adev; 6449 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6450 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6451 6452 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6453 memset((void *)mqd, 0, sizeof(*mqd)); 6454 mutex_lock(&adev->srbm_mutex); 6455 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6456 amdgpu_ring_init_mqd(ring); 6457 6458 /* 6459 * if there are 2 gfx rings, set the lower doorbell 6460 * range of the first ring, otherwise the range of 6461 * the second ring will override the first ring 6462 */ 6463 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6464 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6465 6466 nv_grbm_select(adev, 0, 0, 0, 0); 6467 mutex_unlock(&adev->srbm_mutex); 6468 if (adev->gfx.me.mqd_backup[mqd_idx]) 6469 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6470 } else { 6471 /* restore mqd with the backup copy */ 6472 if (adev->gfx.me.mqd_backup[mqd_idx]) 6473 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6474 /* reset the ring */ 6475 ring->wptr = 0; 6476 *ring->wptr_cpu_addr = 0; 6477 amdgpu_ring_clear_ring(ring); 6478 } 6479 6480 return 0; 6481 } 6482 6483 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6484 { 6485 int r, i; 6486 struct amdgpu_ring *ring; 6487 6488 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6489 ring = &adev->gfx.gfx_ring[i]; 6490 6491 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6492 if (unlikely(r != 0)) 6493 return r; 6494 6495 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6496 if (!r) { 6497 r = gfx_v10_0_gfx_init_queue(ring); 6498 amdgpu_bo_kunmap(ring->mqd_obj); 6499 ring->mqd_ptr = NULL; 6500 } 6501 amdgpu_bo_unreserve(ring->mqd_obj); 6502 if (r) 6503 return r; 6504 } 6505 6506 r = amdgpu_gfx_enable_kgq(adev, 0); 6507 if (r) 6508 return r; 6509 6510 return gfx_v10_0_cp_gfx_start(adev); 6511 } 6512 6513 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6514 struct amdgpu_mqd_prop *prop) 6515 { 6516 struct v10_compute_mqd *mqd = m; 6517 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6518 uint32_t tmp; 6519 6520 mqd->header = 0xC0310800; 6521 mqd->compute_pipelinestat_enable = 0x00000001; 6522 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6523 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6524 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6525 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6526 mqd->compute_misc_reserved = 0x00000003; 6527 6528 eop_base_addr = prop->eop_gpu_addr >> 8; 6529 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6530 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6531 6532 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6533 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6534 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6535 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6536 6537 mqd->cp_hqd_eop_control = tmp; 6538 6539 /* enable doorbell? */ 6540 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6541 6542 if (prop->use_doorbell) { 6543 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6544 DOORBELL_OFFSET, prop->doorbell_index); 6545 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6546 DOORBELL_EN, 1); 6547 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6548 DOORBELL_SOURCE, 0); 6549 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6550 DOORBELL_HIT, 0); 6551 } else { 6552 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6553 DOORBELL_EN, 0); 6554 } 6555 6556 mqd->cp_hqd_pq_doorbell_control = tmp; 6557 6558 /* disable the queue if it's active */ 6559 mqd->cp_hqd_dequeue_request = 0; 6560 mqd->cp_hqd_pq_rptr = 0; 6561 mqd->cp_hqd_pq_wptr_lo = 0; 6562 mqd->cp_hqd_pq_wptr_hi = 0; 6563 6564 /* set the pointer to the MQD */ 6565 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6566 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6567 6568 /* set MQD vmid to 0 */ 6569 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6570 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6571 mqd->cp_mqd_control = tmp; 6572 6573 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6574 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6575 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6576 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6577 6578 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6579 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6580 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6581 (order_base_2(prop->queue_size / 4) - 1)); 6582 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6583 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6584 #ifdef __BIG_ENDIAN 6585 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6586 #endif 6587 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6588 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6589 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6590 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6591 mqd->cp_hqd_pq_control = tmp; 6592 6593 /* set the wb address whether it's enabled or not */ 6594 wb_gpu_addr = prop->rptr_gpu_addr; 6595 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6596 mqd->cp_hqd_pq_rptr_report_addr_hi = 6597 upper_32_bits(wb_gpu_addr) & 0xffff; 6598 6599 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6600 wb_gpu_addr = prop->wptr_gpu_addr; 6601 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6602 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6603 6604 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6605 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6606 6607 /* set the vmid for the queue */ 6608 mqd->cp_hqd_vmid = 0; 6609 6610 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6611 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6612 mqd->cp_hqd_persistent_state = tmp; 6613 6614 /* set MIN_IB_AVAIL_SIZE */ 6615 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6616 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6617 mqd->cp_hqd_ib_control = tmp; 6618 6619 /* set static priority for a compute queue/ring */ 6620 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6621 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6622 6623 mqd->cp_hqd_active = prop->hqd_active; 6624 6625 return 0; 6626 } 6627 6628 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6629 { 6630 struct amdgpu_device *adev = ring->adev; 6631 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6632 int j; 6633 6634 /* inactivate the queue */ 6635 if (amdgpu_sriov_vf(adev)) 6636 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6637 6638 /* disable wptr polling */ 6639 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6640 6641 /* disable the queue if it's active */ 6642 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6643 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6644 for (j = 0; j < adev->usec_timeout; j++) { 6645 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6646 break; 6647 udelay(1); 6648 } 6649 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6650 mqd->cp_hqd_dequeue_request); 6651 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6652 mqd->cp_hqd_pq_rptr); 6653 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6654 mqd->cp_hqd_pq_wptr_lo); 6655 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6656 mqd->cp_hqd_pq_wptr_hi); 6657 } 6658 6659 /* disable doorbells */ 6660 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6661 6662 /* write the EOP addr */ 6663 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6664 mqd->cp_hqd_eop_base_addr_lo); 6665 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6666 mqd->cp_hqd_eop_base_addr_hi); 6667 6668 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6669 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6670 mqd->cp_hqd_eop_control); 6671 6672 /* set the pointer to the MQD */ 6673 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6674 mqd->cp_mqd_base_addr_lo); 6675 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6676 mqd->cp_mqd_base_addr_hi); 6677 6678 /* set MQD vmid to 0 */ 6679 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6680 mqd->cp_mqd_control); 6681 6682 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6683 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6684 mqd->cp_hqd_pq_base_lo); 6685 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6686 mqd->cp_hqd_pq_base_hi); 6687 6688 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6689 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6690 mqd->cp_hqd_pq_control); 6691 6692 /* set the wb address whether it's enabled or not */ 6693 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6694 mqd->cp_hqd_pq_rptr_report_addr_lo); 6695 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6696 mqd->cp_hqd_pq_rptr_report_addr_hi); 6697 6698 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6699 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6700 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6701 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6702 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6703 6704 /* enable the doorbell if requested */ 6705 if (ring->use_doorbell) { 6706 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6707 (adev->doorbell_index.kiq * 2) << 2); 6708 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6709 (adev->doorbell_index.userqueue_end * 2) << 2); 6710 } 6711 6712 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6713 mqd->cp_hqd_pq_doorbell_control); 6714 6715 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6716 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6717 mqd->cp_hqd_pq_wptr_lo); 6718 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6719 mqd->cp_hqd_pq_wptr_hi); 6720 6721 /* set the vmid for the queue */ 6722 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6723 6724 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6725 mqd->cp_hqd_persistent_state); 6726 6727 /* activate the queue */ 6728 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6729 mqd->cp_hqd_active); 6730 6731 if (ring->use_doorbell) 6732 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6733 6734 return 0; 6735 } 6736 6737 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6738 { 6739 struct amdgpu_device *adev = ring->adev; 6740 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6741 6742 gfx_v10_0_kiq_setting(ring); 6743 6744 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6745 /* reset MQD to a clean status */ 6746 if (adev->gfx.kiq[0].mqd_backup) 6747 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 6748 6749 /* reset ring buffer */ 6750 ring->wptr = 0; 6751 amdgpu_ring_clear_ring(ring); 6752 6753 mutex_lock(&adev->srbm_mutex); 6754 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6755 gfx_v10_0_kiq_init_register(ring); 6756 nv_grbm_select(adev, 0, 0, 0, 0); 6757 mutex_unlock(&adev->srbm_mutex); 6758 } else { 6759 memset((void *)mqd, 0, sizeof(*mqd)); 6760 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 6761 amdgpu_ring_clear_ring(ring); 6762 mutex_lock(&adev->srbm_mutex); 6763 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6764 amdgpu_ring_init_mqd(ring); 6765 gfx_v10_0_kiq_init_register(ring); 6766 nv_grbm_select(adev, 0, 0, 0, 0); 6767 mutex_unlock(&adev->srbm_mutex); 6768 6769 if (adev->gfx.kiq[0].mqd_backup) 6770 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 6771 } 6772 6773 return 0; 6774 } 6775 6776 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6777 { 6778 struct amdgpu_device *adev = ring->adev; 6779 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6780 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6781 6782 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6783 memset((void *)mqd, 0, sizeof(*mqd)); 6784 mutex_lock(&adev->srbm_mutex); 6785 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6786 amdgpu_ring_init_mqd(ring); 6787 nv_grbm_select(adev, 0, 0, 0, 0); 6788 mutex_unlock(&adev->srbm_mutex); 6789 6790 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6791 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6792 } else { 6793 /* restore MQD to a clean status */ 6794 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6795 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6796 /* reset ring buffer */ 6797 ring->wptr = 0; 6798 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6799 amdgpu_ring_clear_ring(ring); 6800 } 6801 6802 return 0; 6803 } 6804 6805 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6806 { 6807 struct amdgpu_ring *ring; 6808 int r; 6809 6810 ring = &adev->gfx.kiq[0].ring; 6811 6812 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6813 if (unlikely(r != 0)) 6814 return r; 6815 6816 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6817 if (unlikely(r != 0)) { 6818 amdgpu_bo_unreserve(ring->mqd_obj); 6819 return r; 6820 } 6821 6822 gfx_v10_0_kiq_init_queue(ring); 6823 amdgpu_bo_kunmap(ring->mqd_obj); 6824 ring->mqd_ptr = NULL; 6825 amdgpu_bo_unreserve(ring->mqd_obj); 6826 return 0; 6827 } 6828 6829 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6830 { 6831 struct amdgpu_ring *ring = NULL; 6832 int r = 0, i; 6833 6834 gfx_v10_0_cp_compute_enable(adev, true); 6835 6836 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6837 ring = &adev->gfx.compute_ring[i]; 6838 6839 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6840 if (unlikely(r != 0)) 6841 goto done; 6842 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6843 if (!r) { 6844 r = gfx_v10_0_kcq_init_queue(ring); 6845 amdgpu_bo_kunmap(ring->mqd_obj); 6846 ring->mqd_ptr = NULL; 6847 } 6848 amdgpu_bo_unreserve(ring->mqd_obj); 6849 if (r) 6850 goto done; 6851 } 6852 6853 r = amdgpu_gfx_enable_kcq(adev, 0); 6854 done: 6855 return r; 6856 } 6857 6858 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6859 { 6860 int r, i; 6861 struct amdgpu_ring *ring; 6862 6863 if (!(adev->flags & AMD_IS_APU)) 6864 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6865 6866 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6867 /* legacy firmware loading */ 6868 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6869 if (r) 6870 return r; 6871 6872 r = gfx_v10_0_cp_compute_load_microcode(adev); 6873 if (r) 6874 return r; 6875 } 6876 6877 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 6878 r = amdgpu_mes_kiq_hw_init(adev); 6879 else 6880 r = gfx_v10_0_kiq_resume(adev); 6881 if (r) 6882 return r; 6883 6884 r = gfx_v10_0_kcq_resume(adev); 6885 if (r) 6886 return r; 6887 6888 if (!amdgpu_async_gfx_ring) { 6889 r = gfx_v10_0_cp_gfx_resume(adev); 6890 if (r) 6891 return r; 6892 } else { 6893 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6894 if (r) 6895 return r; 6896 } 6897 6898 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6899 ring = &adev->gfx.gfx_ring[i]; 6900 r = amdgpu_ring_test_helper(ring); 6901 if (r) 6902 return r; 6903 } 6904 6905 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6906 ring = &adev->gfx.compute_ring[i]; 6907 r = amdgpu_ring_test_helper(ring); 6908 if (r) 6909 return r; 6910 } 6911 6912 return 0; 6913 } 6914 6915 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6916 { 6917 gfx_v10_0_cp_gfx_enable(adev, enable); 6918 gfx_v10_0_cp_compute_enable(adev, enable); 6919 } 6920 6921 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6922 { 6923 uint32_t data, pattern = 0xDEADBEEF; 6924 6925 /* check if mmVGT_ESGS_RING_SIZE_UMD 6926 * has been remapped to mmVGT_ESGS_RING_SIZE */ 6927 switch (adev->ip_versions[GC_HWIP][0]) { 6928 case IP_VERSION(10, 3, 0): 6929 case IP_VERSION(10, 3, 2): 6930 case IP_VERSION(10, 3, 4): 6931 case IP_VERSION(10, 3, 5): 6932 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6933 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6934 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6935 6936 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6937 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 6938 return true; 6939 } else { 6940 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6941 return false; 6942 } 6943 break; 6944 case IP_VERSION(10, 3, 1): 6945 case IP_VERSION(10, 3, 3): 6946 case IP_VERSION(10, 3, 6): 6947 case IP_VERSION(10, 3, 7): 6948 return true; 6949 default: 6950 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6951 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 6952 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6953 6954 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 6955 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6956 return true; 6957 } else { 6958 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 6959 return false; 6960 } 6961 break; 6962 } 6963 } 6964 6965 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 6966 { 6967 uint32_t data; 6968 6969 if (amdgpu_sriov_vf(adev)) 6970 return; 6971 6972 /* initialize cam_index to 0 6973 * index will auto-inc after each data writting */ 6974 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 6975 6976 switch (adev->ip_versions[GC_HWIP][0]) { 6977 case IP_VERSION(10, 3, 0): 6978 case IP_VERSION(10, 3, 2): 6979 case IP_VERSION(10, 3, 1): 6980 case IP_VERSION(10, 3, 4): 6981 case IP_VERSION(10, 3, 5): 6982 case IP_VERSION(10, 3, 6): 6983 case IP_VERSION(10, 3, 3): 6984 case IP_VERSION(10, 3, 7): 6985 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 6986 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 6987 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6988 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 6989 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6990 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6991 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 6992 6993 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 6994 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 6995 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6996 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 6997 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6998 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6999 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7000 7001 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7002 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7003 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7004 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7005 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7006 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7007 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7008 7009 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7010 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7011 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7012 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7013 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7014 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7015 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7016 7017 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7018 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7019 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7020 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7021 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7022 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7023 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7024 7025 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7026 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7027 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7028 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7029 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7030 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7031 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7032 7033 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7034 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7035 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7036 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7037 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7038 break; 7039 default: 7040 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7041 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7042 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7043 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7044 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7045 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7046 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7047 7048 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7049 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7050 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7051 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7052 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7053 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7054 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7055 7056 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7057 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7058 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7059 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7060 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7061 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7062 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7063 7064 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7065 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7066 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7067 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7068 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7069 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7070 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7071 7072 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7073 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7074 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7075 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7076 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7077 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7078 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7079 7080 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7081 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7082 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7083 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7084 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7085 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7086 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7087 7088 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7089 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7090 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7091 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7092 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7093 break; 7094 } 7095 7096 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7097 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7098 } 7099 7100 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7101 { 7102 uint32_t data; 7103 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7104 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7105 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7106 7107 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7108 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7109 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7110 } 7111 7112 static int gfx_v10_0_hw_init(void *handle) 7113 { 7114 int r; 7115 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7116 7117 if (!amdgpu_emu_mode) 7118 gfx_v10_0_init_golden_registers(adev); 7119 7120 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7121 /** 7122 * For gfx 10, rlc firmware loading relies on smu firmware is 7123 * loaded firstly, so in direct type, it has to load smc ucode 7124 * here before rlc. 7125 */ 7126 if (!(adev->flags & AMD_IS_APU)) { 7127 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7128 if (r) 7129 return r; 7130 } 7131 gfx_v10_0_disable_gpa_mode(adev); 7132 } 7133 7134 /* if GRBM CAM not remapped, set up the remapping */ 7135 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7136 gfx_v10_0_setup_grbm_cam_remapping(adev); 7137 7138 gfx_v10_0_constants_init(adev); 7139 7140 r = gfx_v10_0_rlc_resume(adev); 7141 if (r) 7142 return r; 7143 7144 /* 7145 * init golden registers and rlc resume may override some registers, 7146 * reconfig them here 7147 */ 7148 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) || 7149 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) || 7150 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 7151 gfx_v10_0_tcp_harvest(adev); 7152 7153 r = gfx_v10_0_cp_resume(adev); 7154 if (r) 7155 return r; 7156 7157 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 7158 gfx_v10_3_program_pbb_mode(adev); 7159 7160 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 7161 gfx_v10_3_set_power_brake_sequence(adev); 7162 7163 return r; 7164 } 7165 7166 static int gfx_v10_0_hw_fini(void *handle) 7167 { 7168 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7169 7170 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7171 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7172 7173 if (!adev->no_hw_access) { 7174 if (amdgpu_async_gfx_ring) { 7175 if (amdgpu_gfx_disable_kgq(adev, 0)) 7176 DRM_ERROR("KGQ disable failed\n"); 7177 } 7178 7179 if (amdgpu_gfx_disable_kcq(adev, 0)) 7180 DRM_ERROR("KCQ disable failed\n"); 7181 } 7182 7183 if (amdgpu_sriov_vf(adev)) { 7184 gfx_v10_0_cp_gfx_enable(adev, false); 7185 /* Remove the steps of clearing KIQ position. 7186 * It causes GFX hang when another Win guest is rendering. 7187 */ 7188 return 0; 7189 } 7190 gfx_v10_0_cp_enable(adev, false); 7191 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7192 7193 return 0; 7194 } 7195 7196 static int gfx_v10_0_suspend(void *handle) 7197 { 7198 return gfx_v10_0_hw_fini(handle); 7199 } 7200 7201 static int gfx_v10_0_resume(void *handle) 7202 { 7203 return gfx_v10_0_hw_init(handle); 7204 } 7205 7206 static bool gfx_v10_0_is_idle(void *handle) 7207 { 7208 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7209 7210 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7211 GRBM_STATUS, GUI_ACTIVE)) 7212 return false; 7213 else 7214 return true; 7215 } 7216 7217 static int gfx_v10_0_wait_for_idle(void *handle) 7218 { 7219 unsigned i; 7220 u32 tmp; 7221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7222 7223 for (i = 0; i < adev->usec_timeout; i++) { 7224 /* read MC_STATUS */ 7225 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7226 GRBM_STATUS__GUI_ACTIVE_MASK; 7227 7228 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7229 return 0; 7230 udelay(1); 7231 } 7232 return -ETIMEDOUT; 7233 } 7234 7235 static int gfx_v10_0_soft_reset(void *handle) 7236 { 7237 u32 grbm_soft_reset = 0; 7238 u32 tmp; 7239 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7240 7241 /* GRBM_STATUS */ 7242 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7243 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7244 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7245 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7246 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7247 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7248 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7249 GRBM_SOFT_RESET, SOFT_RESET_CP, 7250 1); 7251 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7252 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7253 1); 7254 } 7255 7256 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7257 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7258 GRBM_SOFT_RESET, SOFT_RESET_CP, 7259 1); 7260 } 7261 7262 /* GRBM_STATUS2 */ 7263 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7264 switch (adev->ip_versions[GC_HWIP][0]) { 7265 case IP_VERSION(10, 3, 0): 7266 case IP_VERSION(10, 3, 2): 7267 case IP_VERSION(10, 3, 1): 7268 case IP_VERSION(10, 3, 4): 7269 case IP_VERSION(10, 3, 5): 7270 case IP_VERSION(10, 3, 6): 7271 case IP_VERSION(10, 3, 3): 7272 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7273 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7274 GRBM_SOFT_RESET, 7275 SOFT_RESET_RLC, 7276 1); 7277 break; 7278 default: 7279 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7280 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7281 GRBM_SOFT_RESET, 7282 SOFT_RESET_RLC, 7283 1); 7284 break; 7285 } 7286 7287 if (grbm_soft_reset) { 7288 /* stop the rlc */ 7289 gfx_v10_0_rlc_stop(adev); 7290 7291 /* Disable GFX parsing/prefetching */ 7292 gfx_v10_0_cp_gfx_enable(adev, false); 7293 7294 /* Disable MEC parsing/prefetching */ 7295 gfx_v10_0_cp_compute_enable(adev, false); 7296 7297 if (grbm_soft_reset) { 7298 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7299 tmp |= grbm_soft_reset; 7300 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7301 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7302 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7303 7304 udelay(50); 7305 7306 tmp &= ~grbm_soft_reset; 7307 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7308 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7309 } 7310 7311 /* Wait a little for things to settle down */ 7312 udelay(50); 7313 } 7314 return 0; 7315 } 7316 7317 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7318 { 7319 uint64_t clock, clock_lo, clock_hi, hi_check; 7320 7321 switch (adev->ip_versions[GC_HWIP][0]) { 7322 case IP_VERSION(10, 3, 1): 7323 case IP_VERSION(10, 3, 3): 7324 case IP_VERSION(10, 3, 7): 7325 preempt_disable(); 7326 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7327 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7328 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7329 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7330 * roughly every 42 seconds. 7331 */ 7332 if (hi_check != clock_hi) { 7333 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7334 clock_hi = hi_check; 7335 } 7336 preempt_enable(); 7337 clock = clock_lo | (clock_hi << 32ULL); 7338 break; 7339 case IP_VERSION(10, 3, 6): 7340 preempt_disable(); 7341 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7342 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7343 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7344 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7345 * roughly every 42 seconds. 7346 */ 7347 if (hi_check != clock_hi) { 7348 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7349 clock_hi = hi_check; 7350 } 7351 preempt_enable(); 7352 clock = clock_lo | (clock_hi << 32ULL); 7353 break; 7354 default: 7355 preempt_disable(); 7356 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7357 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7358 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7359 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7360 * roughly every 42 seconds. 7361 */ 7362 if (hi_check != clock_hi) { 7363 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7364 clock_hi = hi_check; 7365 } 7366 preempt_enable(); 7367 clock = clock_lo | (clock_hi << 32ULL); 7368 break; 7369 } 7370 return clock; 7371 } 7372 7373 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7374 uint32_t vmid, 7375 uint32_t gds_base, uint32_t gds_size, 7376 uint32_t gws_base, uint32_t gws_size, 7377 uint32_t oa_base, uint32_t oa_size) 7378 { 7379 struct amdgpu_device *adev = ring->adev; 7380 7381 /* GDS Base */ 7382 gfx_v10_0_write_data_to_reg(ring, 0, false, 7383 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7384 gds_base); 7385 7386 /* GDS Size */ 7387 gfx_v10_0_write_data_to_reg(ring, 0, false, 7388 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7389 gds_size); 7390 7391 /* GWS */ 7392 gfx_v10_0_write_data_to_reg(ring, 0, false, 7393 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7394 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7395 7396 /* OA */ 7397 gfx_v10_0_write_data_to_reg(ring, 0, false, 7398 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7399 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7400 } 7401 7402 static int gfx_v10_0_early_init(void *handle) 7403 { 7404 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7405 7406 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7407 7408 switch (adev->ip_versions[GC_HWIP][0]) { 7409 case IP_VERSION(10, 1, 10): 7410 case IP_VERSION(10, 1, 1): 7411 case IP_VERSION(10, 1, 2): 7412 case IP_VERSION(10, 1, 3): 7413 case IP_VERSION(10, 1, 4): 7414 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7415 break; 7416 case IP_VERSION(10, 3, 0): 7417 case IP_VERSION(10, 3, 2): 7418 case IP_VERSION(10, 3, 1): 7419 case IP_VERSION(10, 3, 4): 7420 case IP_VERSION(10, 3, 5): 7421 case IP_VERSION(10, 3, 6): 7422 case IP_VERSION(10, 3, 3): 7423 case IP_VERSION(10, 3, 7): 7424 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7425 break; 7426 default: 7427 break; 7428 } 7429 7430 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7431 AMDGPU_MAX_COMPUTE_RINGS); 7432 7433 gfx_v10_0_set_kiq_pm4_funcs(adev); 7434 gfx_v10_0_set_ring_funcs(adev); 7435 gfx_v10_0_set_irq_funcs(adev); 7436 gfx_v10_0_set_gds_init(adev); 7437 gfx_v10_0_set_rlc_funcs(adev); 7438 gfx_v10_0_set_mqd_funcs(adev); 7439 7440 /* init rlcg reg access ctrl */ 7441 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7442 7443 return gfx_v10_0_init_microcode(adev); 7444 } 7445 7446 static int gfx_v10_0_late_init(void *handle) 7447 { 7448 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7449 int r; 7450 7451 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7452 if (r) 7453 return r; 7454 7455 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7456 if (r) 7457 return r; 7458 7459 return 0; 7460 } 7461 7462 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7463 { 7464 uint32_t rlc_cntl; 7465 7466 /* if RLC is not enabled, do nothing */ 7467 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7468 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7469 } 7470 7471 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7472 { 7473 uint32_t data; 7474 unsigned i; 7475 7476 data = RLC_SAFE_MODE__CMD_MASK; 7477 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7478 7479 switch (adev->ip_versions[GC_HWIP][0]) { 7480 case IP_VERSION(10, 3, 0): 7481 case IP_VERSION(10, 3, 2): 7482 case IP_VERSION(10, 3, 1): 7483 case IP_VERSION(10, 3, 4): 7484 case IP_VERSION(10, 3, 5): 7485 case IP_VERSION(10, 3, 6): 7486 case IP_VERSION(10, 3, 3): 7487 case IP_VERSION(10, 3, 7): 7488 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7489 7490 /* wait for RLC_SAFE_MODE */ 7491 for (i = 0; i < adev->usec_timeout; i++) { 7492 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7493 RLC_SAFE_MODE, CMD)) 7494 break; 7495 udelay(1); 7496 } 7497 break; 7498 default: 7499 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7500 7501 /* wait for RLC_SAFE_MODE */ 7502 for (i = 0; i < adev->usec_timeout; i++) { 7503 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7504 RLC_SAFE_MODE, CMD)) 7505 break; 7506 udelay(1); 7507 } 7508 break; 7509 } 7510 } 7511 7512 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7513 { 7514 uint32_t data; 7515 7516 data = RLC_SAFE_MODE__CMD_MASK; 7517 switch (adev->ip_versions[GC_HWIP][0]) { 7518 case IP_VERSION(10, 3, 0): 7519 case IP_VERSION(10, 3, 2): 7520 case IP_VERSION(10, 3, 1): 7521 case IP_VERSION(10, 3, 4): 7522 case IP_VERSION(10, 3, 5): 7523 case IP_VERSION(10, 3, 6): 7524 case IP_VERSION(10, 3, 3): 7525 case IP_VERSION(10, 3, 7): 7526 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7527 break; 7528 default: 7529 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7530 break; 7531 } 7532 } 7533 7534 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7535 bool enable) 7536 { 7537 uint32_t data, def; 7538 7539 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7540 return; 7541 7542 /* It is disabled by HW by default */ 7543 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7544 /* 0 - Disable some blocks' MGCG */ 7545 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7546 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7547 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7548 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7549 7550 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7551 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7552 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7553 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7554 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7555 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7556 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7557 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7558 7559 if (def != data) 7560 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7561 7562 /* MGLS is a global flag to control all MGLS in GFX */ 7563 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7564 /* 2 - RLC memory Light sleep */ 7565 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7566 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7567 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7568 if (def != data) 7569 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7570 } 7571 /* 3 - CP memory Light sleep */ 7572 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7573 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7574 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7575 if (def != data) 7576 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7577 } 7578 } 7579 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7580 /* 1 - MGCG_OVERRIDE */ 7581 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7582 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7583 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7584 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7585 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7586 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7587 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7588 if (def != data) 7589 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7590 7591 /* 2 - disable MGLS in CP */ 7592 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7593 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7594 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7595 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7596 } 7597 7598 /* 3 - disable MGLS in RLC */ 7599 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7600 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7601 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7602 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7603 } 7604 7605 } 7606 } 7607 7608 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7609 bool enable) 7610 { 7611 uint32_t data, def; 7612 7613 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7614 return; 7615 7616 /* Enable 3D CGCG/CGLS */ 7617 if (enable) { 7618 /* write cmd to clear cgcg/cgls ov */ 7619 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7620 7621 /* unset CGCG override */ 7622 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7623 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7624 7625 /* update CGCG and CGLS override bits */ 7626 if (def != data) 7627 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7628 7629 /* enable 3Dcgcg FSM(0x0000363f) */ 7630 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7631 data = 0; 7632 7633 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7634 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7635 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7636 7637 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7638 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7639 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7640 7641 if (def != data) 7642 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7643 7644 /* set IDLE_POLL_COUNT(0x00900100) */ 7645 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7646 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7647 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7648 if (def != data) 7649 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7650 } else { 7651 /* Disable CGCG/CGLS */ 7652 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7653 7654 /* disable cgcg, cgls should be disabled */ 7655 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7656 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7657 7658 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7659 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7660 7661 /* disable cgcg and cgls in FSM */ 7662 if (def != data) 7663 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7664 } 7665 } 7666 7667 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7668 bool enable) 7669 { 7670 uint32_t def, data; 7671 7672 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7673 return; 7674 7675 if (enable) { 7676 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7677 7678 /* unset CGCG override */ 7679 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7680 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7681 7682 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7683 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7684 7685 /* update CGCG and CGLS override bits */ 7686 if (def != data) 7687 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7688 7689 /* enable cgcg FSM(0x0000363F) */ 7690 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7691 data = 0; 7692 7693 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7694 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7695 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7696 7697 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7698 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7699 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7700 7701 if (def != data) 7702 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7703 7704 /* set IDLE_POLL_COUNT(0x00900100) */ 7705 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7706 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7707 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7708 if (def != data) 7709 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7710 } else { 7711 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7712 7713 /* reset CGCG/CGLS bits */ 7714 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7715 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7716 7717 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7718 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7719 7720 /* disable cgcg and cgls in FSM */ 7721 if (def != data) 7722 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7723 } 7724 } 7725 7726 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7727 bool enable) 7728 { 7729 uint32_t def, data; 7730 7731 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 7732 return; 7733 7734 if (enable) { 7735 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7736 /* unset FGCG override */ 7737 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7738 /* update FGCG override bits */ 7739 if (def != data) 7740 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7741 7742 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7743 /* unset RLC SRAM CLK GATER override */ 7744 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7745 /* update RLC SRAM CLK GATER override bits */ 7746 if (def != data) 7747 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7748 } else { 7749 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7750 /* reset FGCG bits */ 7751 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7752 /* disable FGCG*/ 7753 if (def != data) 7754 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7755 7756 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7757 /* reset RLC SRAM CLK GATER bits */ 7758 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7759 /* disable RLC SRAM CLK*/ 7760 if (def != data) 7761 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7762 } 7763 } 7764 7765 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 7766 { 7767 uint32_t reg_data = 0; 7768 uint32_t reg_idx = 0; 7769 uint32_t i; 7770 7771 const uint32_t tcp_ctrl_regs[] = { 7772 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7773 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7774 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7775 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7776 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7777 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7778 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7779 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7780 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7781 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7782 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 7783 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 7784 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7785 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7786 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7787 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7788 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7789 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7790 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7791 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7792 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7793 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7794 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 7795 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 7796 }; 7797 7798 const uint32_t tcp_ctrl_regs_nv12[] = { 7799 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7800 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7801 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7802 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7803 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7804 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7805 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7806 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7807 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7808 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7809 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7810 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7811 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7812 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7813 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7814 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7815 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7816 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7817 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7818 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7819 }; 7820 7821 const uint32_t sm_ctlr_regs[] = { 7822 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 7823 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 7824 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 7825 mmCGTS_SA1_QUAD1_SM_CTRL_REG 7826 }; 7827 7828 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 7829 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 7830 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7831 tcp_ctrl_regs_nv12[i]; 7832 reg_data = RREG32(reg_idx); 7833 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7834 WREG32(reg_idx, reg_data); 7835 } 7836 } else { 7837 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 7838 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7839 tcp_ctrl_regs[i]; 7840 reg_data = RREG32(reg_idx); 7841 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7842 WREG32(reg_idx, reg_data); 7843 } 7844 } 7845 7846 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 7847 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 7848 sm_ctlr_regs[i]; 7849 reg_data = RREG32(reg_idx); 7850 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 7851 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 7852 WREG32(reg_idx, reg_data); 7853 } 7854 } 7855 7856 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7857 bool enable) 7858 { 7859 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 7860 7861 if (enable) { 7862 /* enable FGCG firstly*/ 7863 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7864 /* CGCG/CGLS should be enabled after MGCG/MGLS 7865 * === MGCG + MGLS === 7866 */ 7867 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7868 /* === CGCG /CGLS for GFX 3D Only === */ 7869 gfx_v10_0_update_3d_clock_gating(adev, enable); 7870 /* === CGCG + CGLS === */ 7871 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7872 7873 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) || 7874 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) || 7875 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))) 7876 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 7877 } else { 7878 /* CGCG/CGLS should be disabled before MGCG/MGLS 7879 * === CGCG + CGLS === 7880 */ 7881 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7882 /* === CGCG /CGLS for GFX 3D Only === */ 7883 gfx_v10_0_update_3d_clock_gating(adev, enable); 7884 /* === MGCG + MGLS === */ 7885 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7886 /* disable fgcg at last*/ 7887 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7888 } 7889 7890 if (adev->cg_flags & 7891 (AMD_CG_SUPPORT_GFX_MGCG | 7892 AMD_CG_SUPPORT_GFX_CGLS | 7893 AMD_CG_SUPPORT_GFX_CGCG | 7894 AMD_CG_SUPPORT_GFX_3D_CGCG | 7895 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7896 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7897 7898 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 7899 7900 return 0; 7901 } 7902 7903 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 7904 { 7905 u32 reg, data; 7906 7907 amdgpu_gfx_off_ctrl(adev, false); 7908 7909 /* not for *_SOC15 */ 7910 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7911 if (amdgpu_sriov_is_pp_one_vf(adev)) 7912 data = RREG32_NO_KIQ(reg); 7913 else 7914 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 7915 7916 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7917 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7918 7919 if (amdgpu_sriov_is_pp_one_vf(adev)) 7920 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7921 else 7922 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7923 7924 amdgpu_gfx_off_ctrl(adev, true); 7925 } 7926 7927 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7928 uint32_t offset, 7929 struct soc15_reg_rlcg *entries, int arr_size) 7930 { 7931 int i; 7932 uint32_t reg; 7933 7934 if (!entries) 7935 return false; 7936 7937 for (i = 0; i < arr_size; i++) { 7938 const struct soc15_reg_rlcg *entry; 7939 7940 entry = &entries[i]; 7941 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7942 if (offset == reg) 7943 return true; 7944 } 7945 7946 return false; 7947 } 7948 7949 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7950 { 7951 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7952 } 7953 7954 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7955 { 7956 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7957 7958 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7959 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7960 else 7961 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7962 7963 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7964 7965 /* 7966 * CGPG enablement required and the register to program the hysteresis value 7967 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 7968 * in refclk count. Note that RLC FW is modified to take 16 bits from 7969 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 7970 * 7971 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 7972 * of CGPG enablement starting point. 7973 * Power/performance team will optimize it and might give a new value later. 7974 */ 7975 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 7976 switch (adev->ip_versions[GC_HWIP][0]) { 7977 case IP_VERSION(10, 3, 1): 7978 case IP_VERSION(10, 3, 3): 7979 case IP_VERSION(10, 3, 6): 7980 case IP_VERSION(10, 3, 7): 7981 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 7982 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 7983 break; 7984 default: 7985 break; 7986 } 7987 } 7988 } 7989 7990 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7991 { 7992 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 7993 7994 gfx_v10_cntl_power_gating(adev, enable); 7995 7996 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 7997 } 7998 7999 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8000 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8001 .set_safe_mode = gfx_v10_0_set_safe_mode, 8002 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8003 .init = gfx_v10_0_rlc_init, 8004 .get_csb_size = gfx_v10_0_get_csb_size, 8005 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8006 .resume = gfx_v10_0_rlc_resume, 8007 .stop = gfx_v10_0_rlc_stop, 8008 .reset = gfx_v10_0_rlc_reset, 8009 .start = gfx_v10_0_rlc_start, 8010 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8011 }; 8012 8013 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8014 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8015 .set_safe_mode = gfx_v10_0_set_safe_mode, 8016 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8017 .init = gfx_v10_0_rlc_init, 8018 .get_csb_size = gfx_v10_0_get_csb_size, 8019 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8020 .resume = gfx_v10_0_rlc_resume, 8021 .stop = gfx_v10_0_rlc_stop, 8022 .reset = gfx_v10_0_rlc_reset, 8023 .start = gfx_v10_0_rlc_start, 8024 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8025 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8026 }; 8027 8028 static int gfx_v10_0_set_powergating_state(void *handle, 8029 enum amd_powergating_state state) 8030 { 8031 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8032 bool enable = (state == AMD_PG_STATE_GATE); 8033 8034 if (amdgpu_sriov_vf(adev)) 8035 return 0; 8036 8037 switch (adev->ip_versions[GC_HWIP][0]) { 8038 case IP_VERSION(10, 1, 10): 8039 case IP_VERSION(10, 1, 1): 8040 case IP_VERSION(10, 1, 2): 8041 case IP_VERSION(10, 3, 0): 8042 case IP_VERSION(10, 3, 2): 8043 case IP_VERSION(10, 3, 4): 8044 case IP_VERSION(10, 3, 5): 8045 amdgpu_gfx_off_ctrl(adev, enable); 8046 break; 8047 case IP_VERSION(10, 3, 1): 8048 case IP_VERSION(10, 3, 3): 8049 case IP_VERSION(10, 3, 6): 8050 case IP_VERSION(10, 3, 7): 8051 if (!enable) 8052 amdgpu_gfx_off_ctrl(adev, false); 8053 8054 gfx_v10_cntl_pg(adev, enable); 8055 8056 if (enable) 8057 amdgpu_gfx_off_ctrl(adev, true); 8058 8059 break; 8060 default: 8061 break; 8062 } 8063 return 0; 8064 } 8065 8066 static int gfx_v10_0_set_clockgating_state(void *handle, 8067 enum amd_clockgating_state state) 8068 { 8069 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8070 8071 if (amdgpu_sriov_vf(adev)) 8072 return 0; 8073 8074 switch (adev->ip_versions[GC_HWIP][0]) { 8075 case IP_VERSION(10, 1, 10): 8076 case IP_VERSION(10, 1, 1): 8077 case IP_VERSION(10, 1, 2): 8078 case IP_VERSION(10, 3, 0): 8079 case IP_VERSION(10, 3, 2): 8080 case IP_VERSION(10, 3, 1): 8081 case IP_VERSION(10, 3, 4): 8082 case IP_VERSION(10, 3, 5): 8083 case IP_VERSION(10, 3, 6): 8084 case IP_VERSION(10, 3, 3): 8085 case IP_VERSION(10, 3, 7): 8086 gfx_v10_0_update_gfx_clock_gating(adev, 8087 state == AMD_CG_STATE_GATE); 8088 break; 8089 default: 8090 break; 8091 } 8092 return 0; 8093 } 8094 8095 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8096 { 8097 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8098 int data; 8099 8100 /* AMD_CG_SUPPORT_GFX_FGCG */ 8101 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8102 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8103 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8104 8105 /* AMD_CG_SUPPORT_GFX_MGCG */ 8106 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8107 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8108 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8109 8110 /* AMD_CG_SUPPORT_GFX_CGCG */ 8111 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8112 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8113 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8114 8115 /* AMD_CG_SUPPORT_GFX_CGLS */ 8116 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8117 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8118 8119 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8120 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8121 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8122 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8123 8124 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8125 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8126 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8127 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8128 8129 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8130 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8131 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8132 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8133 8134 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8135 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8136 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8137 } 8138 8139 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8140 { 8141 /* gfx10 is 32bit rptr*/ 8142 return *(uint32_t *)ring->rptr_cpu_addr; 8143 } 8144 8145 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8146 { 8147 struct amdgpu_device *adev = ring->adev; 8148 u64 wptr; 8149 8150 /* XXX check if swapping is necessary on BE */ 8151 if (ring->use_doorbell) { 8152 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8153 } else { 8154 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8155 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8156 } 8157 8158 return wptr; 8159 } 8160 8161 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8162 { 8163 struct amdgpu_device *adev = ring->adev; 8164 uint32_t *wptr_saved; 8165 uint32_t *is_queue_unmap; 8166 uint64_t aggregated_db_index; 8167 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 8168 uint64_t wptr_tmp; 8169 8170 if (ring->is_mes_queue) { 8171 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8172 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8173 sizeof(uint32_t)); 8174 aggregated_db_index = 8175 amdgpu_mes_get_aggregated_doorbell_index(adev, 8176 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8177 8178 wptr_tmp = ring->wptr & ring->buf_mask; 8179 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8180 *wptr_saved = wptr_tmp; 8181 /* assume doorbell always being used by mes mapped queue */ 8182 if (*is_queue_unmap) { 8183 WDOORBELL64(aggregated_db_index, wptr_tmp); 8184 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8185 } else { 8186 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8187 8188 if (*is_queue_unmap) 8189 WDOORBELL64(aggregated_db_index, wptr_tmp); 8190 } 8191 } else { 8192 if (ring->use_doorbell) { 8193 /* XXX check if swapping is necessary on BE */ 8194 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8195 ring->wptr); 8196 WDOORBELL64(ring->doorbell_index, ring->wptr); 8197 } else { 8198 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8199 lower_32_bits(ring->wptr)); 8200 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8201 upper_32_bits(ring->wptr)); 8202 } 8203 } 8204 } 8205 8206 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8207 { 8208 /* gfx10 hardware is 32bit rptr */ 8209 return *(uint32_t *)ring->rptr_cpu_addr; 8210 } 8211 8212 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8213 { 8214 u64 wptr; 8215 8216 /* XXX check if swapping is necessary on BE */ 8217 if (ring->use_doorbell) 8218 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8219 else 8220 BUG(); 8221 return wptr; 8222 } 8223 8224 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8225 { 8226 struct amdgpu_device *adev = ring->adev; 8227 uint32_t *wptr_saved; 8228 uint32_t *is_queue_unmap; 8229 uint64_t aggregated_db_index; 8230 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 8231 uint64_t wptr_tmp; 8232 8233 if (ring->is_mes_queue) { 8234 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8235 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8236 sizeof(uint32_t)); 8237 aggregated_db_index = 8238 amdgpu_mes_get_aggregated_doorbell_index(adev, 8239 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8240 8241 wptr_tmp = ring->wptr & ring->buf_mask; 8242 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8243 *wptr_saved = wptr_tmp; 8244 /* assume doorbell always used by mes mapped queue */ 8245 if (*is_queue_unmap) { 8246 WDOORBELL64(aggregated_db_index, wptr_tmp); 8247 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8248 } else { 8249 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8250 8251 if (*is_queue_unmap) 8252 WDOORBELL64(aggregated_db_index, wptr_tmp); 8253 } 8254 } else { 8255 /* XXX check if swapping is necessary on BE */ 8256 if (ring->use_doorbell) { 8257 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8258 ring->wptr); 8259 WDOORBELL64(ring->doorbell_index, ring->wptr); 8260 } else { 8261 BUG(); /* only DOORBELL method supported on gfx10 now */ 8262 } 8263 } 8264 } 8265 8266 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8267 { 8268 struct amdgpu_device *adev = ring->adev; 8269 u32 ref_and_mask, reg_mem_engine; 8270 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8271 8272 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8273 switch (ring->me) { 8274 case 1: 8275 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8276 break; 8277 case 2: 8278 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8279 break; 8280 default: 8281 return; 8282 } 8283 reg_mem_engine = 0; 8284 } else { 8285 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8286 reg_mem_engine = 1; /* pfp */ 8287 } 8288 8289 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8290 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8291 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8292 ref_and_mask, ref_and_mask, 0x20); 8293 } 8294 8295 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8296 struct amdgpu_job *job, 8297 struct amdgpu_ib *ib, 8298 uint32_t flags) 8299 { 8300 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8301 u32 header, control = 0; 8302 8303 if (ib->flags & AMDGPU_IB_FLAG_CE) 8304 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8305 else 8306 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8307 8308 control |= ib->length_dw | (vmid << 24); 8309 8310 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8311 control |= INDIRECT_BUFFER_PRE_ENB(1); 8312 8313 if (flags & AMDGPU_IB_PREEMPTED) 8314 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8315 8316 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8317 gfx_v10_0_ring_emit_de_meta(ring, 8318 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8319 } 8320 8321 if (ring->is_mes_queue) 8322 /* inherit vmid from mqd */ 8323 control |= 0x400000; 8324 8325 amdgpu_ring_write(ring, header); 8326 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8327 amdgpu_ring_write(ring, 8328 #ifdef __BIG_ENDIAN 8329 (2 << 0) | 8330 #endif 8331 lower_32_bits(ib->gpu_addr)); 8332 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8333 amdgpu_ring_write(ring, control); 8334 } 8335 8336 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8337 struct amdgpu_job *job, 8338 struct amdgpu_ib *ib, 8339 uint32_t flags) 8340 { 8341 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8342 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8343 8344 if (ring->is_mes_queue) 8345 /* inherit vmid from mqd */ 8346 control |= 0x40000000; 8347 8348 /* Currently, there is a high possibility to get wave ID mismatch 8349 * between ME and GDS, leading to a hw deadlock, because ME generates 8350 * different wave IDs than the GDS expects. This situation happens 8351 * randomly when at least 5 compute pipes use GDS ordered append. 8352 * The wave IDs generated by ME are also wrong after suspend/resume. 8353 * Those are probably bugs somewhere else in the kernel driver. 8354 * 8355 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8356 * GDS to 0 for this ring (me/pipe). 8357 */ 8358 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8359 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8360 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8361 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8362 } 8363 8364 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8365 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8366 amdgpu_ring_write(ring, 8367 #ifdef __BIG_ENDIAN 8368 (2 << 0) | 8369 #endif 8370 lower_32_bits(ib->gpu_addr)); 8371 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8372 amdgpu_ring_write(ring, control); 8373 } 8374 8375 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8376 u64 seq, unsigned flags) 8377 { 8378 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8379 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8380 8381 /* RELEASE_MEM - flush caches, send int */ 8382 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8383 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8384 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8385 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8386 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8387 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8388 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8389 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8390 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8391 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8392 8393 /* 8394 * the address should be Qword aligned if 64bit write, Dword 8395 * aligned if only send 32bit data low (discard data high) 8396 */ 8397 if (write64bit) 8398 BUG_ON(addr & 0x7); 8399 else 8400 BUG_ON(addr & 0x3); 8401 amdgpu_ring_write(ring, lower_32_bits(addr)); 8402 amdgpu_ring_write(ring, upper_32_bits(addr)); 8403 amdgpu_ring_write(ring, lower_32_bits(seq)); 8404 amdgpu_ring_write(ring, upper_32_bits(seq)); 8405 amdgpu_ring_write(ring, ring->is_mes_queue ? 8406 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 8407 } 8408 8409 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8410 { 8411 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8412 uint32_t seq = ring->fence_drv.sync_seq; 8413 uint64_t addr = ring->fence_drv.gpu_addr; 8414 8415 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8416 upper_32_bits(addr), seq, 0xffffffff, 4); 8417 } 8418 8419 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8420 uint16_t pasid, uint32_t flush_type, 8421 bool all_hub, uint8_t dst_sel) 8422 { 8423 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8424 amdgpu_ring_write(ring, 8425 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8426 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8427 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8428 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8429 } 8430 8431 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8432 unsigned vmid, uint64_t pd_addr) 8433 { 8434 if (ring->is_mes_queue) 8435 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 8436 else 8437 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8438 8439 /* compute doesn't have PFP */ 8440 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8441 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8442 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8443 amdgpu_ring_write(ring, 0x0); 8444 } 8445 } 8446 8447 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8448 u64 seq, unsigned int flags) 8449 { 8450 struct amdgpu_device *adev = ring->adev; 8451 8452 /* we only allocate 32bit for each seq wb address */ 8453 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8454 8455 /* write fence seq to the "addr" */ 8456 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8457 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8458 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8459 amdgpu_ring_write(ring, lower_32_bits(addr)); 8460 amdgpu_ring_write(ring, upper_32_bits(addr)); 8461 amdgpu_ring_write(ring, lower_32_bits(seq)); 8462 8463 if (flags & AMDGPU_FENCE_FLAG_INT) { 8464 /* set register to trigger INT */ 8465 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8466 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8467 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8468 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8469 amdgpu_ring_write(ring, 0); 8470 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8471 } 8472 } 8473 8474 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8475 { 8476 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8477 amdgpu_ring_write(ring, 0); 8478 } 8479 8480 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8481 uint32_t flags) 8482 { 8483 uint32_t dw2 = 0; 8484 8485 if (ring->adev->gfx.mcbp) 8486 gfx_v10_0_ring_emit_ce_meta(ring, 8487 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8488 8489 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8490 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8491 /* set load_global_config & load_global_uconfig */ 8492 dw2 |= 0x8001; 8493 /* set load_cs_sh_regs */ 8494 dw2 |= 0x01000000; 8495 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8496 dw2 |= 0x10002; 8497 8498 /* set load_ce_ram if preamble presented */ 8499 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8500 dw2 |= 0x10000000; 8501 } else { 8502 /* still load_ce_ram if this is the first time preamble presented 8503 * although there is no context switch happens. 8504 */ 8505 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8506 dw2 |= 0x10000000; 8507 } 8508 8509 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8510 amdgpu_ring_write(ring, dw2); 8511 amdgpu_ring_write(ring, 0); 8512 } 8513 8514 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8515 { 8516 unsigned ret; 8517 8518 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8519 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8520 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8521 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8522 ret = ring->wptr & ring->buf_mask; 8523 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8524 8525 return ret; 8526 } 8527 8528 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8529 { 8530 unsigned cur; 8531 BUG_ON(offset > ring->buf_mask); 8532 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8533 8534 cur = (ring->wptr - 1) & ring->buf_mask; 8535 if (likely(cur > offset)) 8536 ring->ring[offset] = cur - offset; 8537 else 8538 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8539 } 8540 8541 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8542 { 8543 int i, r = 0; 8544 struct amdgpu_device *adev = ring->adev; 8545 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8546 struct amdgpu_ring *kiq_ring = &kiq->ring; 8547 unsigned long flags; 8548 8549 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8550 return -EINVAL; 8551 8552 spin_lock_irqsave(&kiq->ring_lock, flags); 8553 8554 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8555 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8556 return -ENOMEM; 8557 } 8558 8559 /* assert preemption condition */ 8560 amdgpu_ring_set_preempt_cond_exec(ring, false); 8561 8562 /* assert IB preemption, emit the trailing fence */ 8563 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8564 ring->trail_fence_gpu_addr, 8565 ++ring->trail_seq); 8566 amdgpu_ring_commit(kiq_ring); 8567 8568 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8569 8570 /* poll the trailing fence */ 8571 for (i = 0; i < adev->usec_timeout; i++) { 8572 if (ring->trail_seq == 8573 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8574 break; 8575 udelay(1); 8576 } 8577 8578 if (i >= adev->usec_timeout) { 8579 r = -EINVAL; 8580 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8581 } 8582 8583 /* deassert preemption condition */ 8584 amdgpu_ring_set_preempt_cond_exec(ring, true); 8585 return r; 8586 } 8587 8588 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8589 { 8590 struct amdgpu_device *adev = ring->adev; 8591 struct v10_ce_ib_state ce_payload = {0}; 8592 uint64_t offset, ce_payload_gpu_addr; 8593 void *ce_payload_cpu_addr; 8594 int cnt; 8595 8596 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8597 8598 if (ring->is_mes_queue) { 8599 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8600 gfx[0].gfx_meta_data) + 8601 offsetof(struct v10_gfx_meta_data, ce_payload); 8602 ce_payload_gpu_addr = 8603 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8604 ce_payload_cpu_addr = 8605 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8606 } else { 8607 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8608 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8609 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8610 } 8611 8612 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8613 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8614 WRITE_DATA_DST_SEL(8) | 8615 WR_CONFIRM) | 8616 WRITE_DATA_CACHE_POLICY(0)); 8617 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8618 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8619 8620 if (resume) 8621 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8622 sizeof(ce_payload) >> 2); 8623 else 8624 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8625 sizeof(ce_payload) >> 2); 8626 } 8627 8628 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8629 { 8630 struct amdgpu_device *adev = ring->adev; 8631 struct v10_de_ib_state de_payload = {0}; 8632 uint64_t offset, gds_addr, de_payload_gpu_addr; 8633 void *de_payload_cpu_addr; 8634 int cnt; 8635 8636 if (ring->is_mes_queue) { 8637 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8638 gfx[0].gfx_meta_data) + 8639 offsetof(struct v10_gfx_meta_data, de_payload); 8640 de_payload_gpu_addr = 8641 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8642 de_payload_cpu_addr = 8643 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8644 8645 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8646 gfx[0].gds_backup) + 8647 offsetof(struct v10_gfx_meta_data, de_payload); 8648 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8649 } else { 8650 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8651 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8652 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8653 8654 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8655 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8656 PAGE_SIZE); 8657 } 8658 8659 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8660 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8661 8662 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8663 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8664 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8665 WRITE_DATA_DST_SEL(8) | 8666 WR_CONFIRM) | 8667 WRITE_DATA_CACHE_POLICY(0)); 8668 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8669 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8670 8671 if (resume) 8672 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8673 sizeof(de_payload) >> 2); 8674 else 8675 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8676 sizeof(de_payload) >> 2); 8677 } 8678 8679 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8680 bool secure) 8681 { 8682 uint32_t v = secure ? FRAME_TMZ : 0; 8683 8684 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8685 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8686 } 8687 8688 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8689 uint32_t reg_val_offs) 8690 { 8691 struct amdgpu_device *adev = ring->adev; 8692 8693 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8694 amdgpu_ring_write(ring, 0 | /* src: register*/ 8695 (5 << 8) | /* dst: memory */ 8696 (1 << 20)); /* write confirm */ 8697 amdgpu_ring_write(ring, reg); 8698 amdgpu_ring_write(ring, 0); 8699 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8700 reg_val_offs * 4)); 8701 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8702 reg_val_offs * 4)); 8703 } 8704 8705 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8706 uint32_t val) 8707 { 8708 uint32_t cmd = 0; 8709 8710 switch (ring->funcs->type) { 8711 case AMDGPU_RING_TYPE_GFX: 8712 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8713 break; 8714 case AMDGPU_RING_TYPE_KIQ: 8715 cmd = (1 << 16); /* no inc addr */ 8716 break; 8717 default: 8718 cmd = WR_CONFIRM; 8719 break; 8720 } 8721 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8722 amdgpu_ring_write(ring, cmd); 8723 amdgpu_ring_write(ring, reg); 8724 amdgpu_ring_write(ring, 0); 8725 amdgpu_ring_write(ring, val); 8726 } 8727 8728 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8729 uint32_t val, uint32_t mask) 8730 { 8731 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8732 } 8733 8734 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8735 uint32_t reg0, uint32_t reg1, 8736 uint32_t ref, uint32_t mask) 8737 { 8738 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8739 struct amdgpu_device *adev = ring->adev; 8740 bool fw_version_ok = false; 8741 8742 fw_version_ok = adev->gfx.cp_fw_write_wait; 8743 8744 if (fw_version_ok) 8745 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8746 ref, mask, 0x20); 8747 else 8748 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8749 ref, mask); 8750 } 8751 8752 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8753 unsigned vmid) 8754 { 8755 struct amdgpu_device *adev = ring->adev; 8756 uint32_t value = 0; 8757 8758 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8759 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8760 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8761 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8762 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8763 } 8764 8765 static void 8766 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8767 uint32_t me, uint32_t pipe, 8768 enum amdgpu_interrupt_state state) 8769 { 8770 uint32_t cp_int_cntl, cp_int_cntl_reg; 8771 8772 if (!me) { 8773 switch (pipe) { 8774 case 0: 8775 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8776 break; 8777 case 1: 8778 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8779 break; 8780 default: 8781 DRM_DEBUG("invalid pipe %d\n", pipe); 8782 return; 8783 } 8784 } else { 8785 DRM_DEBUG("invalid me %d\n", me); 8786 return; 8787 } 8788 8789 switch (state) { 8790 case AMDGPU_IRQ_STATE_DISABLE: 8791 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8792 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8793 TIME_STAMP_INT_ENABLE, 0); 8794 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8795 break; 8796 case AMDGPU_IRQ_STATE_ENABLE: 8797 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8798 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8799 TIME_STAMP_INT_ENABLE, 1); 8800 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8801 break; 8802 default: 8803 break; 8804 } 8805 } 8806 8807 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8808 int me, int pipe, 8809 enum amdgpu_interrupt_state state) 8810 { 8811 u32 mec_int_cntl, mec_int_cntl_reg; 8812 8813 /* 8814 * amdgpu controls only the first MEC. That's why this function only 8815 * handles the setting of interrupts for this specific MEC. All other 8816 * pipes' interrupts are set by amdkfd. 8817 */ 8818 8819 if (me == 1) { 8820 switch (pipe) { 8821 case 0: 8822 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8823 break; 8824 case 1: 8825 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8826 break; 8827 case 2: 8828 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8829 break; 8830 case 3: 8831 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8832 break; 8833 default: 8834 DRM_DEBUG("invalid pipe %d\n", pipe); 8835 return; 8836 } 8837 } else { 8838 DRM_DEBUG("invalid me %d\n", me); 8839 return; 8840 } 8841 8842 switch (state) { 8843 case AMDGPU_IRQ_STATE_DISABLE: 8844 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8845 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8846 TIME_STAMP_INT_ENABLE, 0); 8847 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8848 break; 8849 case AMDGPU_IRQ_STATE_ENABLE: 8850 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8851 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8852 TIME_STAMP_INT_ENABLE, 1); 8853 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8854 break; 8855 default: 8856 break; 8857 } 8858 } 8859 8860 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8861 struct amdgpu_irq_src *src, 8862 unsigned type, 8863 enum amdgpu_interrupt_state state) 8864 { 8865 switch (type) { 8866 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8867 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8868 break; 8869 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8870 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8871 break; 8872 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8873 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8874 break; 8875 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8876 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8877 break; 8878 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8879 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8880 break; 8881 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8882 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8883 break; 8884 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8885 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8886 break; 8887 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8888 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8889 break; 8890 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8891 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8892 break; 8893 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8894 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8895 break; 8896 default: 8897 break; 8898 } 8899 return 0; 8900 } 8901 8902 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8903 struct amdgpu_irq_src *source, 8904 struct amdgpu_iv_entry *entry) 8905 { 8906 int i; 8907 u8 me_id, pipe_id, queue_id; 8908 struct amdgpu_ring *ring; 8909 uint32_t mes_queue_id = entry->src_data[0]; 8910 8911 DRM_DEBUG("IH: CP EOP\n"); 8912 8913 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 8914 struct amdgpu_mes_queue *queue; 8915 8916 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 8917 8918 spin_lock(&adev->mes.queue_id_lock); 8919 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 8920 if (queue) { 8921 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 8922 amdgpu_fence_process(queue->ring); 8923 } 8924 spin_unlock(&adev->mes.queue_id_lock); 8925 } else { 8926 me_id = (entry->ring_id & 0x0c) >> 2; 8927 pipe_id = (entry->ring_id & 0x03) >> 0; 8928 queue_id = (entry->ring_id & 0x70) >> 4; 8929 8930 switch (me_id) { 8931 case 0: 8932 if (pipe_id == 0) 8933 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8934 else 8935 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8936 break; 8937 case 1: 8938 case 2: 8939 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8940 ring = &adev->gfx.compute_ring[i]; 8941 /* Per-queue interrupt is supported for MEC starting from VI. 8942 * The interrupt can only be enabled/disabled per pipe instead 8943 * of per queue. 8944 */ 8945 if ((ring->me == me_id) && 8946 (ring->pipe == pipe_id) && 8947 (ring->queue == queue_id)) 8948 amdgpu_fence_process(ring); 8949 } 8950 break; 8951 } 8952 } 8953 8954 return 0; 8955 } 8956 8957 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8958 struct amdgpu_irq_src *source, 8959 unsigned type, 8960 enum amdgpu_interrupt_state state) 8961 { 8962 switch (state) { 8963 case AMDGPU_IRQ_STATE_DISABLE: 8964 case AMDGPU_IRQ_STATE_ENABLE: 8965 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8966 PRIV_REG_INT_ENABLE, 8967 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8968 break; 8969 default: 8970 break; 8971 } 8972 8973 return 0; 8974 } 8975 8976 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8977 struct amdgpu_irq_src *source, 8978 unsigned type, 8979 enum amdgpu_interrupt_state state) 8980 { 8981 switch (state) { 8982 case AMDGPU_IRQ_STATE_DISABLE: 8983 case AMDGPU_IRQ_STATE_ENABLE: 8984 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8985 PRIV_INSTR_INT_ENABLE, 8986 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8987 break; 8988 default: 8989 break; 8990 } 8991 8992 return 0; 8993 } 8994 8995 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8996 struct amdgpu_iv_entry *entry) 8997 { 8998 u8 me_id, pipe_id, queue_id; 8999 struct amdgpu_ring *ring; 9000 int i; 9001 9002 me_id = (entry->ring_id & 0x0c) >> 2; 9003 pipe_id = (entry->ring_id & 0x03) >> 0; 9004 queue_id = (entry->ring_id & 0x70) >> 4; 9005 9006 switch (me_id) { 9007 case 0: 9008 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9009 ring = &adev->gfx.gfx_ring[i]; 9010 /* we only enabled 1 gfx queue per pipe for now */ 9011 if (ring->me == me_id && ring->pipe == pipe_id) 9012 drm_sched_fault(&ring->sched); 9013 } 9014 break; 9015 case 1: 9016 case 2: 9017 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9018 ring = &adev->gfx.compute_ring[i]; 9019 if (ring->me == me_id && ring->pipe == pipe_id && 9020 ring->queue == queue_id) 9021 drm_sched_fault(&ring->sched); 9022 } 9023 break; 9024 default: 9025 BUG(); 9026 } 9027 } 9028 9029 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9030 struct amdgpu_irq_src *source, 9031 struct amdgpu_iv_entry *entry) 9032 { 9033 DRM_ERROR("Illegal register access in command stream\n"); 9034 gfx_v10_0_handle_priv_fault(adev, entry); 9035 return 0; 9036 } 9037 9038 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9039 struct amdgpu_irq_src *source, 9040 struct amdgpu_iv_entry *entry) 9041 { 9042 DRM_ERROR("Illegal instruction in command stream\n"); 9043 gfx_v10_0_handle_priv_fault(adev, entry); 9044 return 0; 9045 } 9046 9047 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9048 struct amdgpu_irq_src *src, 9049 unsigned int type, 9050 enum amdgpu_interrupt_state state) 9051 { 9052 uint32_t tmp, target; 9053 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9054 9055 if (ring->me == 1) 9056 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9057 else 9058 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9059 target += ring->pipe; 9060 9061 switch (type) { 9062 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9063 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9064 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9065 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9066 GENERIC2_INT_ENABLE, 0); 9067 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9068 9069 tmp = RREG32_SOC15_IP(GC, target); 9070 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9071 GENERIC2_INT_ENABLE, 0); 9072 WREG32_SOC15_IP(GC, target, tmp); 9073 } else { 9074 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9075 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9076 GENERIC2_INT_ENABLE, 1); 9077 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9078 9079 tmp = RREG32_SOC15_IP(GC, target); 9080 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9081 GENERIC2_INT_ENABLE, 1); 9082 WREG32_SOC15_IP(GC, target, tmp); 9083 } 9084 break; 9085 default: 9086 BUG(); /* kiq only support GENERIC2_INT now */ 9087 break; 9088 } 9089 return 0; 9090 } 9091 9092 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9093 struct amdgpu_irq_src *source, 9094 struct amdgpu_iv_entry *entry) 9095 { 9096 u8 me_id, pipe_id, queue_id; 9097 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9098 9099 me_id = (entry->ring_id & 0x0c) >> 2; 9100 pipe_id = (entry->ring_id & 0x03) >> 0; 9101 queue_id = (entry->ring_id & 0x70) >> 4; 9102 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9103 me_id, pipe_id, queue_id); 9104 9105 amdgpu_fence_process(ring); 9106 return 0; 9107 } 9108 9109 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9110 { 9111 const unsigned int gcr_cntl = 9112 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9113 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9114 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9115 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9116 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9117 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9118 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9119 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9120 9121 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9122 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9123 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9124 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9125 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9126 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9127 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9128 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9129 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9130 } 9131 9132 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9133 .name = "gfx_v10_0", 9134 .early_init = gfx_v10_0_early_init, 9135 .late_init = gfx_v10_0_late_init, 9136 .sw_init = gfx_v10_0_sw_init, 9137 .sw_fini = gfx_v10_0_sw_fini, 9138 .hw_init = gfx_v10_0_hw_init, 9139 .hw_fini = gfx_v10_0_hw_fini, 9140 .suspend = gfx_v10_0_suspend, 9141 .resume = gfx_v10_0_resume, 9142 .is_idle = gfx_v10_0_is_idle, 9143 .wait_for_idle = gfx_v10_0_wait_for_idle, 9144 .soft_reset = gfx_v10_0_soft_reset, 9145 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9146 .set_powergating_state = gfx_v10_0_set_powergating_state, 9147 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9148 }; 9149 9150 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9151 .type = AMDGPU_RING_TYPE_GFX, 9152 .align_mask = 0xff, 9153 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9154 .support_64bit_ptrs = true, 9155 .secure_submission_supported = true, 9156 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9157 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9158 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9159 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9160 5 + /* COND_EXEC */ 9161 7 + /* PIPELINE_SYNC */ 9162 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9163 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9164 2 + /* VM_FLUSH */ 9165 8 + /* FENCE for VM_FLUSH */ 9166 20 + /* GDS switch */ 9167 4 + /* double SWITCH_BUFFER, 9168 * the first COND_EXEC jump to the place 9169 * just prior to this double SWITCH_BUFFER 9170 */ 9171 5 + /* COND_EXEC */ 9172 7 + /* HDP_flush */ 9173 4 + /* VGT_flush */ 9174 14 + /* CE_META */ 9175 31 + /* DE_META */ 9176 3 + /* CNTX_CTRL */ 9177 5 + /* HDP_INVL */ 9178 8 + 8 + /* FENCE x2 */ 9179 2 + /* SWITCH_BUFFER */ 9180 8, /* gfx_v10_0_emit_mem_sync */ 9181 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9182 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9183 .emit_fence = gfx_v10_0_ring_emit_fence, 9184 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9185 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9186 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9187 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9188 .test_ring = gfx_v10_0_ring_test_ring, 9189 .test_ib = gfx_v10_0_ring_test_ib, 9190 .insert_nop = amdgpu_ring_insert_nop, 9191 .pad_ib = amdgpu_ring_generic_pad_ib, 9192 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9193 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9194 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9195 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9196 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9197 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9198 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9199 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9200 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9201 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9202 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9203 }; 9204 9205 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9206 .type = AMDGPU_RING_TYPE_COMPUTE, 9207 .align_mask = 0xff, 9208 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9209 .support_64bit_ptrs = true, 9210 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9211 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9212 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9213 .emit_frame_size = 9214 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9215 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9216 5 + /* hdp invalidate */ 9217 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9218 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9219 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9220 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9221 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9222 8, /* gfx_v10_0_emit_mem_sync */ 9223 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9224 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9225 .emit_fence = gfx_v10_0_ring_emit_fence, 9226 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9227 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9228 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9229 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9230 .test_ring = gfx_v10_0_ring_test_ring, 9231 .test_ib = gfx_v10_0_ring_test_ib, 9232 .insert_nop = amdgpu_ring_insert_nop, 9233 .pad_ib = amdgpu_ring_generic_pad_ib, 9234 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9235 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9236 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9237 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9238 }; 9239 9240 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9241 .type = AMDGPU_RING_TYPE_KIQ, 9242 .align_mask = 0xff, 9243 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9244 .support_64bit_ptrs = true, 9245 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9246 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9247 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9248 .emit_frame_size = 9249 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9250 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9251 5 + /*hdp invalidate */ 9252 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9253 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9254 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9255 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9256 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9257 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9258 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9259 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9260 .test_ring = gfx_v10_0_ring_test_ring, 9261 .test_ib = gfx_v10_0_ring_test_ib, 9262 .insert_nop = amdgpu_ring_insert_nop, 9263 .pad_ib = amdgpu_ring_generic_pad_ib, 9264 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9265 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9266 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9267 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9268 }; 9269 9270 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9271 { 9272 int i; 9273 9274 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9275 9276 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9277 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9278 9279 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9280 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9281 } 9282 9283 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9284 .set = gfx_v10_0_set_eop_interrupt_state, 9285 .process = gfx_v10_0_eop_irq, 9286 }; 9287 9288 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9289 .set = gfx_v10_0_set_priv_reg_fault_state, 9290 .process = gfx_v10_0_priv_reg_irq, 9291 }; 9292 9293 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9294 .set = gfx_v10_0_set_priv_inst_fault_state, 9295 .process = gfx_v10_0_priv_inst_irq, 9296 }; 9297 9298 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9299 .set = gfx_v10_0_kiq_set_interrupt_state, 9300 .process = gfx_v10_0_kiq_irq, 9301 }; 9302 9303 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9304 { 9305 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9306 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9307 9308 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9309 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9310 9311 adev->gfx.priv_reg_irq.num_types = 1; 9312 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9313 9314 adev->gfx.priv_inst_irq.num_types = 1; 9315 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9316 } 9317 9318 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9319 { 9320 switch (adev->ip_versions[GC_HWIP][0]) { 9321 case IP_VERSION(10, 1, 10): 9322 case IP_VERSION(10, 1, 1): 9323 case IP_VERSION(10, 1, 3): 9324 case IP_VERSION(10, 1, 4): 9325 case IP_VERSION(10, 3, 2): 9326 case IP_VERSION(10, 3, 1): 9327 case IP_VERSION(10, 3, 4): 9328 case IP_VERSION(10, 3, 5): 9329 case IP_VERSION(10, 3, 6): 9330 case IP_VERSION(10, 3, 3): 9331 case IP_VERSION(10, 3, 7): 9332 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9333 break; 9334 case IP_VERSION(10, 1, 2): 9335 case IP_VERSION(10, 3, 0): 9336 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9337 break; 9338 default: 9339 break; 9340 } 9341 } 9342 9343 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9344 { 9345 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9346 adev->gfx.config.max_sh_per_se * 9347 adev->gfx.config.max_shader_engines; 9348 9349 adev->gds.gds_size = 0x10000; 9350 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9351 adev->gds.gws_size = 64; 9352 adev->gds.oa_size = 16; 9353 } 9354 9355 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9356 { 9357 /* set gfx eng mqd */ 9358 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9359 sizeof(struct v10_gfx_mqd); 9360 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9361 gfx_v10_0_gfx_mqd_init; 9362 /* set compute eng mqd */ 9363 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9364 sizeof(struct v10_compute_mqd); 9365 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9366 gfx_v10_0_compute_mqd_init; 9367 } 9368 9369 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9370 u32 bitmap) 9371 { 9372 u32 data; 9373 9374 if (!bitmap) 9375 return; 9376 9377 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9378 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9379 9380 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9381 } 9382 9383 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9384 { 9385 u32 disabled_mask = 9386 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9387 u32 efuse_setting = 0; 9388 u32 vbios_setting = 0; 9389 9390 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9391 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9392 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9393 9394 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9395 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9396 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9397 9398 disabled_mask |= efuse_setting | vbios_setting; 9399 9400 return (~disabled_mask); 9401 } 9402 9403 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9404 { 9405 u32 wgp_idx, wgp_active_bitmap; 9406 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9407 9408 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9409 cu_active_bitmap = 0; 9410 9411 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9412 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9413 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9414 if (wgp_active_bitmap & (1 << wgp_idx)) 9415 cu_active_bitmap |= cu_bitmap_per_wgp; 9416 } 9417 9418 return cu_active_bitmap; 9419 } 9420 9421 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9422 struct amdgpu_cu_info *cu_info) 9423 { 9424 int i, j, k, counter, active_cu_number = 0; 9425 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9426 unsigned disable_masks[4 * 2]; 9427 9428 if (!adev || !cu_info) 9429 return -EINVAL; 9430 9431 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9432 9433 mutex_lock(&adev->grbm_idx_mutex); 9434 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9435 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9436 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9437 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 9438 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 9439 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) || 9440 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) && 9441 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9442 continue; 9443 mask = 1; 9444 ao_bitmap = 0; 9445 counter = 0; 9446 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 9447 if (i < 4 && j < 2) 9448 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9449 adev, disable_masks[i * 2 + j]); 9450 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9451 cu_info->bitmap[i][j] = bitmap; 9452 9453 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9454 if (bitmap & mask) { 9455 if (counter < adev->gfx.config.max_cu_per_sh) 9456 ao_bitmap |= mask; 9457 counter++; 9458 } 9459 mask <<= 1; 9460 } 9461 active_cu_number += counter; 9462 if (i < 2 && j < 2) 9463 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9464 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9465 } 9466 } 9467 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 9468 mutex_unlock(&adev->grbm_idx_mutex); 9469 9470 cu_info->number = active_cu_number; 9471 cu_info->ao_cu_mask = ao_cu_mask; 9472 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9473 9474 return 0; 9475 } 9476 9477 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9478 { 9479 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9480 9481 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9482 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9483 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9484 9485 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9486 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9487 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9488 9489 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9490 adev->gfx.config.max_shader_engines); 9491 disabled_sa = efuse_setting | vbios_setting; 9492 disabled_sa &= max_sa_mask; 9493 9494 return disabled_sa; 9495 } 9496 9497 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9498 { 9499 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9500 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9501 9502 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9503 9504 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9505 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9506 max_shader_engines = adev->gfx.config.max_shader_engines; 9507 9508 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9509 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9510 disabled_sa_per_se &= max_sa_per_se_mask; 9511 if (disabled_sa_per_se == max_sa_per_se_mask) { 9512 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9513 break; 9514 } 9515 } 9516 } 9517 9518 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9519 { 9520 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9521 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9522 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9523 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9524 9525 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9526 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9527 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9528 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9529 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9530 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9531 9532 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9533 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9534 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9535 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9536 9537 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9538 9539 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9540 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9541 } 9542 9543 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9544 { 9545 .type = AMD_IP_BLOCK_TYPE_GFX, 9546 .major = 10, 9547 .minor = 0, 9548 .rev = 0, 9549 .funcs = &gfx_v10_0_ip_funcs, 9550 }; 9551