1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "smuio/smuio_11_0_0_offset.h" 39 #include "smuio/smuio_11_0_0_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "soc15_common.h" 47 #include "clearstate_gfx10.h" 48 #include "v10_structs.h" 49 #include "gfx_v10_0.h" 50 #include "nbio_v2_3.h" 51 52 /** 53 * Navi10 has two graphic rings to share each graphic pipe. 54 * 1. Primary ring 55 * 2. Async ring 56 */ 57 #define GFX10_NUM_GFX_RINGS_NV1X 1 58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 59 #define GFX10_MEC_HPD_SIZE 2048 60 61 #define F32_CE_PROGRAM_RAM_SIZE 65536 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 64 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 70 71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 73 74 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 76 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 101 102 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 103 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 104 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 105 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 106 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 107 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 108 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 109 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 110 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 111 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 112 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 113 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 114 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 115 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 116 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 117 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 118 119 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 120 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 121 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 122 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 123 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 124 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 125 #define mmCP_HYP_CE_UCODE_DATA 0x5819 126 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 127 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 128 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 129 #define mmCP_HYP_ME_UCODE_DATA 0x5817 130 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 131 132 #define mmCPG_PSP_DEBUG 0x5c10 133 #define mmCPG_PSP_DEBUG_BASE_IDX 1 134 #define mmCPC_PSP_DEBUG 0x5c11 135 #define mmCPC_PSP_DEBUG_BASE_IDX 1 136 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 137 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 138 139 //CC_GC_SA_UNIT_DISABLE 140 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 141 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 142 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 143 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 144 //GC_USER_SA_UNIT_DISABLE 145 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 146 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 147 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 148 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 149 //PA_SC_ENHANCE_3 150 #define mmPA_SC_ENHANCE_3 0x1085 151 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 152 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 153 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 154 155 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 156 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 157 158 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 159 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 160 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 161 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 162 163 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 164 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 165 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 166 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 167 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 168 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 169 170 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 171 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 172 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 173 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 174 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 175 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 176 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 177 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 178 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 179 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 180 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 181 182 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 183 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 184 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 185 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 186 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 187 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 188 189 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 190 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 191 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 192 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 193 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 194 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 195 196 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 197 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 198 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 199 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 200 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 201 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 202 203 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 204 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 205 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 206 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 207 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 208 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 209 210 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 211 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 212 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 213 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 214 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 215 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 216 217 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 218 { 219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 259 }; 260 261 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 262 { 263 /* Pending on emulation bring up */ 264 }; 265 266 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 267 { 268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1320 }; 1321 1322 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1323 { 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1362 }; 1363 1364 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1365 { 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 1406 }; 1407 1408 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 1409 { 1410 static void *scratch_reg0; 1411 static void *scratch_reg1; 1412 static void *scratch_reg2; 1413 static void *scratch_reg3; 1414 static void *spare_int; 1415 static uint32_t grbm_cntl; 1416 static uint32_t grbm_idx; 1417 uint32_t i = 0; 1418 uint32_t retries = 50000; 1419 1420 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 1421 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 1422 scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4; 1423 scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4; 1424 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 1425 1426 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 1427 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; 1428 1429 if (amdgpu_sriov_runtime(adev)) { 1430 pr_err("shouldn't call rlcg write register during runtime\n"); 1431 return; 1432 } 1433 1434 writel(v, scratch_reg0); 1435 writel(offset | 0x80000000, scratch_reg1); 1436 writel(1, spare_int); 1437 for (i = 0; i < retries; i++) { 1438 u32 tmp; 1439 1440 tmp = readl(scratch_reg1); 1441 if (!(tmp & 0x80000000)) 1442 break; 1443 1444 udelay(10); 1445 } 1446 1447 if (i >= retries) 1448 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 1449 } 1450 1451 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1452 { 1453 /* Pending on emulation bring up */ 1454 }; 1455 1456 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1457 { 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2078 }; 2079 2080 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2081 { 2082 /* Pending on emulation bring up */ 2083 }; 2084 2085 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2086 { 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3139 }; 3140 3141 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3142 { 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3185 }; 3186 3187 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3188 { 3189 /* Pending on emulation bring up */ 3190 }; 3191 3192 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3193 { 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3235 3236 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3238 }; 3239 3240 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3241 { 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3265 3266 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3268 }; 3269 3270 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3271 { 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3307 }; 3308 3309 #define DEFAULT_SH_MEM_CONFIG \ 3310 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3311 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3312 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3313 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3314 3315 3316 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3317 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3318 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3319 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3320 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3321 struct amdgpu_cu_info *cu_info); 3322 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3323 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3324 u32 sh_num, u32 instance); 3325 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3326 3327 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3328 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3329 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3330 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3331 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3332 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3333 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3334 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3335 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3336 3337 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3338 { 3339 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3340 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3341 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3342 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3343 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3344 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3345 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3346 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3347 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3348 } 3349 3350 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3351 struct amdgpu_ring *ring) 3352 { 3353 struct amdgpu_device *adev = kiq_ring->adev; 3354 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3355 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3356 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3357 3358 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3359 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3360 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3361 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3362 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3363 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3364 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3365 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3366 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3367 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3368 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3369 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3370 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3371 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3372 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3373 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3374 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3375 } 3376 3377 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3378 struct amdgpu_ring *ring, 3379 enum amdgpu_unmap_queues_action action, 3380 u64 gpu_addr, u64 seq) 3381 { 3382 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3383 3384 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3385 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3386 PACKET3_UNMAP_QUEUES_ACTION(action) | 3387 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3388 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3389 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3390 amdgpu_ring_write(kiq_ring, 3391 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3392 3393 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3394 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3395 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3396 amdgpu_ring_write(kiq_ring, seq); 3397 } else { 3398 amdgpu_ring_write(kiq_ring, 0); 3399 amdgpu_ring_write(kiq_ring, 0); 3400 amdgpu_ring_write(kiq_ring, 0); 3401 } 3402 } 3403 3404 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3405 struct amdgpu_ring *ring, 3406 u64 addr, 3407 u64 seq) 3408 { 3409 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3410 3411 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3412 amdgpu_ring_write(kiq_ring, 3413 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3414 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3415 PACKET3_QUERY_STATUS_COMMAND(2)); 3416 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3417 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3418 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3419 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3420 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3421 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3422 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3423 } 3424 3425 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3426 uint16_t pasid, uint32_t flush_type, 3427 bool all_hub) 3428 { 3429 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3430 amdgpu_ring_write(kiq_ring, 3431 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3432 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3433 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3434 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3435 } 3436 3437 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3438 .kiq_set_resources = gfx10_kiq_set_resources, 3439 .kiq_map_queues = gfx10_kiq_map_queues, 3440 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3441 .kiq_query_status = gfx10_kiq_query_status, 3442 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3443 .set_resources_size = 8, 3444 .map_queues_size = 7, 3445 .unmap_queues_size = 6, 3446 .query_status_size = 7, 3447 .invalidate_tlbs_size = 2, 3448 }; 3449 3450 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3451 { 3452 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3453 } 3454 3455 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3456 { 3457 switch (adev->asic_type) { 3458 case CHIP_NAVI10: 3459 soc15_program_register_sequence(adev, 3460 golden_settings_gc_rlc_spm_10_0_nv10, 3461 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3462 break; 3463 case CHIP_NAVI14: 3464 soc15_program_register_sequence(adev, 3465 golden_settings_gc_rlc_spm_10_1_nv14, 3466 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3467 break; 3468 case CHIP_NAVI12: 3469 soc15_program_register_sequence(adev, 3470 golden_settings_gc_rlc_spm_10_1_2_nv12, 3471 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3472 break; 3473 default: 3474 break; 3475 } 3476 } 3477 3478 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3479 { 3480 switch (adev->asic_type) { 3481 case CHIP_NAVI10: 3482 soc15_program_register_sequence(adev, 3483 golden_settings_gc_10_1, 3484 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3485 soc15_program_register_sequence(adev, 3486 golden_settings_gc_10_0_nv10, 3487 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3488 break; 3489 case CHIP_NAVI14: 3490 soc15_program_register_sequence(adev, 3491 golden_settings_gc_10_1_1, 3492 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3493 soc15_program_register_sequence(adev, 3494 golden_settings_gc_10_1_nv14, 3495 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3496 break; 3497 case CHIP_NAVI12: 3498 soc15_program_register_sequence(adev, 3499 golden_settings_gc_10_1_2, 3500 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3501 soc15_program_register_sequence(adev, 3502 golden_settings_gc_10_1_2_nv12, 3503 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3504 break; 3505 case CHIP_SIENNA_CICHLID: 3506 soc15_program_register_sequence(adev, 3507 golden_settings_gc_10_3, 3508 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3509 soc15_program_register_sequence(adev, 3510 golden_settings_gc_10_3_sienna_cichlid, 3511 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3512 break; 3513 case CHIP_NAVY_FLOUNDER: 3514 soc15_program_register_sequence(adev, 3515 golden_settings_gc_10_3_2, 3516 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3517 break; 3518 case CHIP_VANGOGH: 3519 soc15_program_register_sequence(adev, 3520 golden_settings_gc_10_3_vangogh, 3521 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3522 break; 3523 case CHIP_DIMGREY_CAVEFISH: 3524 soc15_program_register_sequence(adev, 3525 golden_settings_gc_10_3_4, 3526 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3527 break; 3528 default: 3529 break; 3530 } 3531 gfx_v10_0_init_spm_golden_registers(adev); 3532 } 3533 3534 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3535 { 3536 adev->gfx.scratch.num_reg = 8; 3537 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3538 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3539 } 3540 3541 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3542 bool wc, uint32_t reg, uint32_t val) 3543 { 3544 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3545 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3546 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3547 amdgpu_ring_write(ring, reg); 3548 amdgpu_ring_write(ring, 0); 3549 amdgpu_ring_write(ring, val); 3550 } 3551 3552 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3553 int mem_space, int opt, uint32_t addr0, 3554 uint32_t addr1, uint32_t ref, uint32_t mask, 3555 uint32_t inv) 3556 { 3557 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3558 amdgpu_ring_write(ring, 3559 /* memory (1) or register (0) */ 3560 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3561 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3562 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3563 WAIT_REG_MEM_ENGINE(eng_sel))); 3564 3565 if (mem_space) 3566 BUG_ON(addr0 & 0x3); /* Dword align */ 3567 amdgpu_ring_write(ring, addr0); 3568 amdgpu_ring_write(ring, addr1); 3569 amdgpu_ring_write(ring, ref); 3570 amdgpu_ring_write(ring, mask); 3571 amdgpu_ring_write(ring, inv); /* poll interval */ 3572 } 3573 3574 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3575 { 3576 struct amdgpu_device *adev = ring->adev; 3577 uint32_t scratch; 3578 uint32_t tmp = 0; 3579 unsigned i; 3580 int r; 3581 3582 r = amdgpu_gfx_scratch_get(adev, &scratch); 3583 if (r) { 3584 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3585 return r; 3586 } 3587 3588 WREG32(scratch, 0xCAFEDEAD); 3589 3590 r = amdgpu_ring_alloc(ring, 3); 3591 if (r) { 3592 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3593 ring->idx, r); 3594 amdgpu_gfx_scratch_free(adev, scratch); 3595 return r; 3596 } 3597 3598 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3599 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3600 amdgpu_ring_write(ring, 0xDEADBEEF); 3601 amdgpu_ring_commit(ring); 3602 3603 for (i = 0; i < adev->usec_timeout; i++) { 3604 tmp = RREG32(scratch); 3605 if (tmp == 0xDEADBEEF) 3606 break; 3607 if (amdgpu_emu_mode == 1) 3608 msleep(1); 3609 else 3610 udelay(1); 3611 } 3612 3613 if (i >= adev->usec_timeout) 3614 r = -ETIMEDOUT; 3615 3616 amdgpu_gfx_scratch_free(adev, scratch); 3617 3618 return r; 3619 } 3620 3621 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3622 { 3623 struct amdgpu_device *adev = ring->adev; 3624 struct amdgpu_ib ib; 3625 struct dma_fence *f = NULL; 3626 unsigned index; 3627 uint64_t gpu_addr; 3628 uint32_t tmp; 3629 long r; 3630 3631 r = amdgpu_device_wb_get(adev, &index); 3632 if (r) 3633 return r; 3634 3635 gpu_addr = adev->wb.gpu_addr + (index * 4); 3636 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3637 memset(&ib, 0, sizeof(ib)); 3638 r = amdgpu_ib_get(adev, NULL, 16, 3639 AMDGPU_IB_POOL_DIRECT, &ib); 3640 if (r) 3641 goto err1; 3642 3643 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3644 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3645 ib.ptr[2] = lower_32_bits(gpu_addr); 3646 ib.ptr[3] = upper_32_bits(gpu_addr); 3647 ib.ptr[4] = 0xDEADBEEF; 3648 ib.length_dw = 5; 3649 3650 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3651 if (r) 3652 goto err2; 3653 3654 r = dma_fence_wait_timeout(f, false, timeout); 3655 if (r == 0) { 3656 r = -ETIMEDOUT; 3657 goto err2; 3658 } else if (r < 0) { 3659 goto err2; 3660 } 3661 3662 tmp = adev->wb.wb[index]; 3663 if (tmp == 0xDEADBEEF) 3664 r = 0; 3665 else 3666 r = -EINVAL; 3667 err2: 3668 amdgpu_ib_free(adev, &ib, NULL); 3669 dma_fence_put(f); 3670 err1: 3671 amdgpu_device_wb_free(adev, index); 3672 return r; 3673 } 3674 3675 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3676 { 3677 release_firmware(adev->gfx.pfp_fw); 3678 adev->gfx.pfp_fw = NULL; 3679 release_firmware(adev->gfx.me_fw); 3680 adev->gfx.me_fw = NULL; 3681 release_firmware(adev->gfx.ce_fw); 3682 adev->gfx.ce_fw = NULL; 3683 release_firmware(adev->gfx.rlc_fw); 3684 adev->gfx.rlc_fw = NULL; 3685 release_firmware(adev->gfx.mec_fw); 3686 adev->gfx.mec_fw = NULL; 3687 release_firmware(adev->gfx.mec2_fw); 3688 adev->gfx.mec2_fw = NULL; 3689 3690 kfree(adev->gfx.rlc.register_list_format); 3691 } 3692 3693 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3694 { 3695 adev->gfx.cp_fw_write_wait = false; 3696 3697 switch (adev->asic_type) { 3698 case CHIP_NAVI10: 3699 case CHIP_NAVI12: 3700 case CHIP_NAVI14: 3701 if ((adev->gfx.me_fw_version >= 0x00000046) && 3702 (adev->gfx.me_feature_version >= 27) && 3703 (adev->gfx.pfp_fw_version >= 0x00000068) && 3704 (adev->gfx.pfp_feature_version >= 27) && 3705 (adev->gfx.mec_fw_version >= 0x0000005b) && 3706 (adev->gfx.mec_feature_version >= 27)) 3707 adev->gfx.cp_fw_write_wait = true; 3708 break; 3709 case CHIP_SIENNA_CICHLID: 3710 case CHIP_NAVY_FLOUNDER: 3711 case CHIP_VANGOGH: 3712 case CHIP_DIMGREY_CAVEFISH: 3713 adev->gfx.cp_fw_write_wait = true; 3714 break; 3715 default: 3716 break; 3717 } 3718 3719 if (!adev->gfx.cp_fw_write_wait) 3720 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3721 } 3722 3723 3724 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3725 { 3726 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3727 3728 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 3729 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 3730 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 3731 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 3732 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 3733 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 3734 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 3735 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 3736 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 3737 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 3738 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 3739 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 3740 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 3741 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 3742 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 3743 } 3744 3745 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 3746 { 3747 const struct rlc_firmware_header_v2_2 *rlc_hdr; 3748 3749 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 3750 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 3751 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 3752 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 3753 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 3754 } 3755 3756 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3757 { 3758 bool ret = false; 3759 3760 switch (adev->pdev->revision) { 3761 case 0xc2: 3762 case 0xc3: 3763 ret = true; 3764 break; 3765 default: 3766 ret = false; 3767 break; 3768 } 3769 3770 return ret ; 3771 } 3772 3773 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3774 { 3775 switch (adev->asic_type) { 3776 case CHIP_NAVI10: 3777 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3778 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3779 break; 3780 case CHIP_VANGOGH: 3781 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3782 break; 3783 default: 3784 break; 3785 } 3786 } 3787 3788 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3789 { 3790 const char *chip_name; 3791 char fw_name[40]; 3792 char wks[10]; 3793 int err; 3794 struct amdgpu_firmware_info *info = NULL; 3795 const struct common_firmware_header *header = NULL; 3796 const struct gfx_firmware_header_v1_0 *cp_hdr; 3797 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3798 unsigned int *tmp = NULL; 3799 unsigned int i = 0; 3800 uint16_t version_major; 3801 uint16_t version_minor; 3802 3803 DRM_DEBUG("\n"); 3804 3805 memset(wks, 0, sizeof(wks)); 3806 switch (adev->asic_type) { 3807 case CHIP_NAVI10: 3808 chip_name = "navi10"; 3809 break; 3810 case CHIP_NAVI14: 3811 chip_name = "navi14"; 3812 if (!(adev->pdev->device == 0x7340 && 3813 adev->pdev->revision != 0x00)) 3814 snprintf(wks, sizeof(wks), "_wks"); 3815 break; 3816 case CHIP_NAVI12: 3817 chip_name = "navi12"; 3818 break; 3819 case CHIP_SIENNA_CICHLID: 3820 chip_name = "sienna_cichlid"; 3821 break; 3822 case CHIP_NAVY_FLOUNDER: 3823 chip_name = "navy_flounder"; 3824 break; 3825 case CHIP_VANGOGH: 3826 chip_name = "vangogh"; 3827 break; 3828 case CHIP_DIMGREY_CAVEFISH: 3829 chip_name = "dimgrey_cavefish"; 3830 break; 3831 default: 3832 BUG(); 3833 } 3834 3835 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 3836 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 3837 if (err) 3838 goto out; 3839 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 3840 if (err) 3841 goto out; 3842 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3843 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3844 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3845 3846 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 3847 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 3848 if (err) 3849 goto out; 3850 err = amdgpu_ucode_validate(adev->gfx.me_fw); 3851 if (err) 3852 goto out; 3853 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3854 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3855 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3856 3857 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 3858 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 3859 if (err) 3860 goto out; 3861 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 3862 if (err) 3863 goto out; 3864 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3865 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3866 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3867 3868 if (!amdgpu_sriov_vf(adev)) { 3869 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 3870 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 3871 if (err) 3872 goto out; 3873 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 3874 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3875 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 3876 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 3877 3878 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 3879 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 3880 adev->gfx.rlc.save_and_restore_offset = 3881 le32_to_cpu(rlc_hdr->save_and_restore_offset); 3882 adev->gfx.rlc.clear_state_descriptor_offset = 3883 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 3884 adev->gfx.rlc.avail_scratch_ram_locations = 3885 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 3886 adev->gfx.rlc.reg_restore_list_size = 3887 le32_to_cpu(rlc_hdr->reg_restore_list_size); 3888 adev->gfx.rlc.reg_list_format_start = 3889 le32_to_cpu(rlc_hdr->reg_list_format_start); 3890 adev->gfx.rlc.reg_list_format_separate_start = 3891 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 3892 adev->gfx.rlc.starting_offsets_start = 3893 le32_to_cpu(rlc_hdr->starting_offsets_start); 3894 adev->gfx.rlc.reg_list_format_size_bytes = 3895 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 3896 adev->gfx.rlc.reg_list_size_bytes = 3897 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 3898 adev->gfx.rlc.register_list_format = 3899 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 3900 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 3901 if (!adev->gfx.rlc.register_list_format) { 3902 err = -ENOMEM; 3903 goto out; 3904 } 3905 3906 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3907 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 3908 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 3909 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 3910 3911 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 3912 3913 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3914 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 3915 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 3916 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 3917 3918 if (version_major == 2) { 3919 if (version_minor >= 1) 3920 gfx_v10_0_init_rlc_ext_microcode(adev); 3921 if (version_minor == 2) 3922 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 3923 } 3924 } 3925 3926 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 3927 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 3928 if (err) 3929 goto out; 3930 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 3931 if (err) 3932 goto out; 3933 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3934 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3935 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3936 3937 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 3938 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 3939 if (!err) { 3940 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 3941 if (err) 3942 goto out; 3943 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 3944 adev->gfx.mec2_fw->data; 3945 adev->gfx.mec2_fw_version = 3946 le32_to_cpu(cp_hdr->header.ucode_version); 3947 adev->gfx.mec2_feature_version = 3948 le32_to_cpu(cp_hdr->ucode_feature_version); 3949 } else { 3950 err = 0; 3951 adev->gfx.mec2_fw = NULL; 3952 } 3953 3954 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 3955 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 3956 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 3957 info->fw = adev->gfx.pfp_fw; 3958 header = (const struct common_firmware_header *)info->fw->data; 3959 adev->firmware.fw_size += 3960 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3961 3962 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 3963 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 3964 info->fw = adev->gfx.me_fw; 3965 header = (const struct common_firmware_header *)info->fw->data; 3966 adev->firmware.fw_size += 3967 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3968 3969 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 3970 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 3971 info->fw = adev->gfx.ce_fw; 3972 header = (const struct common_firmware_header *)info->fw->data; 3973 adev->firmware.fw_size += 3974 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3975 3976 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 3977 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 3978 info->fw = adev->gfx.rlc_fw; 3979 if (info->fw) { 3980 header = (const struct common_firmware_header *)info->fw->data; 3981 adev->firmware.fw_size += 3982 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3983 } 3984 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 3985 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 3986 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 3987 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 3988 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 3989 info->fw = adev->gfx.rlc_fw; 3990 adev->firmware.fw_size += 3991 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 3992 3993 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 3994 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 3995 info->fw = adev->gfx.rlc_fw; 3996 adev->firmware.fw_size += 3997 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 3998 3999 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 4000 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 4001 info->fw = adev->gfx.rlc_fw; 4002 adev->firmware.fw_size += 4003 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 4004 4005 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 4006 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 4007 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 4008 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 4009 info->fw = adev->gfx.rlc_fw; 4010 adev->firmware.fw_size += 4011 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4012 4013 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4014 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4015 info->fw = adev->gfx.rlc_fw; 4016 adev->firmware.fw_size += 4017 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4018 } 4019 } 4020 4021 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4022 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4023 info->fw = adev->gfx.mec_fw; 4024 header = (const struct common_firmware_header *)info->fw->data; 4025 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4026 adev->firmware.fw_size += 4027 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4028 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4029 4030 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4031 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4032 info->fw = adev->gfx.mec_fw; 4033 adev->firmware.fw_size += 4034 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4035 4036 if (adev->gfx.mec2_fw) { 4037 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4038 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4039 info->fw = adev->gfx.mec2_fw; 4040 header = (const struct common_firmware_header *)info->fw->data; 4041 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4042 adev->firmware.fw_size += 4043 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4044 le32_to_cpu(cp_hdr->jt_size) * 4, 4045 PAGE_SIZE); 4046 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4047 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4048 info->fw = adev->gfx.mec2_fw; 4049 adev->firmware.fw_size += 4050 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4051 PAGE_SIZE); 4052 } 4053 } 4054 4055 gfx_v10_0_check_fw_write_wait(adev); 4056 out: 4057 if (err) { 4058 dev_err(adev->dev, 4059 "gfx10: Failed to load firmware \"%s\"\n", 4060 fw_name); 4061 release_firmware(adev->gfx.pfp_fw); 4062 adev->gfx.pfp_fw = NULL; 4063 release_firmware(adev->gfx.me_fw); 4064 adev->gfx.me_fw = NULL; 4065 release_firmware(adev->gfx.ce_fw); 4066 adev->gfx.ce_fw = NULL; 4067 release_firmware(adev->gfx.rlc_fw); 4068 adev->gfx.rlc_fw = NULL; 4069 release_firmware(adev->gfx.mec_fw); 4070 adev->gfx.mec_fw = NULL; 4071 release_firmware(adev->gfx.mec2_fw); 4072 adev->gfx.mec2_fw = NULL; 4073 } 4074 4075 gfx_v10_0_check_gfxoff_flag(adev); 4076 4077 return err; 4078 } 4079 4080 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4081 { 4082 u32 count = 0; 4083 const struct cs_section_def *sect = NULL; 4084 const struct cs_extent_def *ext = NULL; 4085 4086 /* begin clear state */ 4087 count += 2; 4088 /* context control state */ 4089 count += 3; 4090 4091 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4092 for (ext = sect->section; ext->extent != NULL; ++ext) { 4093 if (sect->id == SECT_CONTEXT) 4094 count += 2 + ext->reg_count; 4095 else 4096 return 0; 4097 } 4098 } 4099 4100 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4101 count += 3; 4102 /* end clear state */ 4103 count += 2; 4104 /* clear state */ 4105 count += 2; 4106 4107 return count; 4108 } 4109 4110 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4111 volatile u32 *buffer) 4112 { 4113 u32 count = 0, i; 4114 const struct cs_section_def *sect = NULL; 4115 const struct cs_extent_def *ext = NULL; 4116 int ctx_reg_offset; 4117 4118 if (adev->gfx.rlc.cs_data == NULL) 4119 return; 4120 if (buffer == NULL) 4121 return; 4122 4123 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4124 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4125 4126 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4127 buffer[count++] = cpu_to_le32(0x80000000); 4128 buffer[count++] = cpu_to_le32(0x80000000); 4129 4130 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4131 for (ext = sect->section; ext->extent != NULL; ++ext) { 4132 if (sect->id == SECT_CONTEXT) { 4133 buffer[count++] = 4134 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4135 buffer[count++] = cpu_to_le32(ext->reg_index - 4136 PACKET3_SET_CONTEXT_REG_START); 4137 for (i = 0; i < ext->reg_count; i++) 4138 buffer[count++] = cpu_to_le32(ext->extent[i]); 4139 } else { 4140 return; 4141 } 4142 } 4143 } 4144 4145 ctx_reg_offset = 4146 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4147 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4148 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4149 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4150 4151 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4152 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4153 4154 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4155 buffer[count++] = cpu_to_le32(0); 4156 } 4157 4158 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4159 { 4160 /* clear state block */ 4161 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4162 &adev->gfx.rlc.clear_state_gpu_addr, 4163 (void **)&adev->gfx.rlc.cs_ptr); 4164 4165 /* jump table block */ 4166 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4167 &adev->gfx.rlc.cp_table_gpu_addr, 4168 (void **)&adev->gfx.rlc.cp_table_ptr); 4169 } 4170 4171 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4172 { 4173 const struct cs_section_def *cs_data; 4174 int r; 4175 4176 adev->gfx.rlc.cs_data = gfx10_cs_data; 4177 4178 cs_data = adev->gfx.rlc.cs_data; 4179 4180 if (cs_data) { 4181 /* init clear state block */ 4182 r = amdgpu_gfx_rlc_init_csb(adev); 4183 if (r) 4184 return r; 4185 } 4186 4187 /* init spm vmid with 0xf */ 4188 if (adev->gfx.rlc.funcs->update_spm_vmid) 4189 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4190 4191 return 0; 4192 } 4193 4194 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4195 { 4196 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4197 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4198 } 4199 4200 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4201 { 4202 int r; 4203 4204 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4205 4206 amdgpu_gfx_graphics_queue_acquire(adev); 4207 4208 r = gfx_v10_0_init_microcode(adev); 4209 if (r) 4210 DRM_ERROR("Failed to load gfx firmware!\n"); 4211 4212 return r; 4213 } 4214 4215 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4216 { 4217 int r; 4218 u32 *hpd; 4219 const __le32 *fw_data = NULL; 4220 unsigned fw_size; 4221 u32 *fw = NULL; 4222 size_t mec_hpd_size; 4223 4224 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4225 4226 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4227 4228 /* take ownership of the relevant compute queues */ 4229 amdgpu_gfx_compute_queue_acquire(adev); 4230 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4231 4232 if (mec_hpd_size) { 4233 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4234 AMDGPU_GEM_DOMAIN_GTT, 4235 &adev->gfx.mec.hpd_eop_obj, 4236 &adev->gfx.mec.hpd_eop_gpu_addr, 4237 (void **)&hpd); 4238 if (r) { 4239 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4240 gfx_v10_0_mec_fini(adev); 4241 return r; 4242 } 4243 4244 memset(hpd, 0, mec_hpd_size); 4245 4246 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4247 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4248 } 4249 4250 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4251 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4252 4253 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4254 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4255 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4256 4257 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4258 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4259 &adev->gfx.mec.mec_fw_obj, 4260 &adev->gfx.mec.mec_fw_gpu_addr, 4261 (void **)&fw); 4262 if (r) { 4263 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4264 gfx_v10_0_mec_fini(adev); 4265 return r; 4266 } 4267 4268 memcpy(fw, fw_data, fw_size); 4269 4270 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4271 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4272 } 4273 4274 return 0; 4275 } 4276 4277 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4278 { 4279 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4280 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4281 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4282 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4283 } 4284 4285 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4286 uint32_t thread, uint32_t regno, 4287 uint32_t num, uint32_t *out) 4288 { 4289 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4290 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4291 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4292 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4293 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4294 while (num--) 4295 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4296 } 4297 4298 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4299 { 4300 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4301 * field when performing a select_se_sh so it should be 4302 * zero here */ 4303 WARN_ON(simd != 0); 4304 4305 /* type 2 wave data */ 4306 dst[(*no_fields)++] = 2; 4307 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4308 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4309 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4310 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4311 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4312 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4313 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4314 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4315 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4316 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4317 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4318 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4319 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4320 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4321 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4322 } 4323 4324 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4325 uint32_t wave, uint32_t start, 4326 uint32_t size, uint32_t *dst) 4327 { 4328 WARN_ON(simd != 0); 4329 4330 wave_read_regs( 4331 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4332 dst); 4333 } 4334 4335 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4336 uint32_t wave, uint32_t thread, 4337 uint32_t start, uint32_t size, 4338 uint32_t *dst) 4339 { 4340 wave_read_regs( 4341 adev, wave, thread, 4342 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4343 } 4344 4345 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4346 u32 me, u32 pipe, u32 q, u32 vm) 4347 { 4348 nv_grbm_select(adev, me, pipe, q, vm); 4349 } 4350 4351 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4352 bool enable) 4353 { 4354 uint32_t data, def; 4355 4356 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4357 4358 if (enable) 4359 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4360 else 4361 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4362 4363 if (data != def) 4364 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4365 } 4366 4367 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4368 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4369 .select_se_sh = &gfx_v10_0_select_se_sh, 4370 .read_wave_data = &gfx_v10_0_read_wave_data, 4371 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4372 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4373 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4374 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4375 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4376 }; 4377 4378 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4379 { 4380 u32 gb_addr_config; 4381 4382 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4383 4384 switch (adev->asic_type) { 4385 case CHIP_NAVI10: 4386 case CHIP_NAVI14: 4387 case CHIP_NAVI12: 4388 adev->gfx.config.max_hw_contexts = 8; 4389 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4390 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4391 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4392 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4393 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4394 break; 4395 case CHIP_SIENNA_CICHLID: 4396 case CHIP_NAVY_FLOUNDER: 4397 case CHIP_VANGOGH: 4398 case CHIP_DIMGREY_CAVEFISH: 4399 adev->gfx.config.max_hw_contexts = 8; 4400 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4401 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4402 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4403 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4404 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4405 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4406 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4407 break; 4408 default: 4409 BUG(); 4410 break; 4411 } 4412 4413 adev->gfx.config.gb_addr_config = gb_addr_config; 4414 4415 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4416 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4417 GB_ADDR_CONFIG, NUM_PIPES); 4418 4419 adev->gfx.config.max_tile_pipes = 4420 adev->gfx.config.gb_addr_config_fields.num_pipes; 4421 4422 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4423 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4424 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4425 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4426 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4427 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4428 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4429 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4430 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4431 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4432 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4433 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4434 } 4435 4436 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4437 int me, int pipe, int queue) 4438 { 4439 int r; 4440 struct amdgpu_ring *ring; 4441 unsigned int irq_type; 4442 4443 ring = &adev->gfx.gfx_ring[ring_id]; 4444 4445 ring->me = me; 4446 ring->pipe = pipe; 4447 ring->queue = queue; 4448 4449 ring->ring_obj = NULL; 4450 ring->use_doorbell = true; 4451 4452 if (!ring_id) 4453 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4454 else 4455 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4456 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4457 4458 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4459 r = amdgpu_ring_init(adev, ring, 1024, 4460 &adev->gfx.eop_irq, irq_type, 4461 AMDGPU_RING_PRIO_DEFAULT); 4462 if (r) 4463 return r; 4464 return 0; 4465 } 4466 4467 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4468 int mec, int pipe, int queue) 4469 { 4470 int r; 4471 unsigned irq_type; 4472 struct amdgpu_ring *ring; 4473 unsigned int hw_prio; 4474 4475 ring = &adev->gfx.compute_ring[ring_id]; 4476 4477 /* mec0 is me1 */ 4478 ring->me = mec + 1; 4479 ring->pipe = pipe; 4480 ring->queue = queue; 4481 4482 ring->ring_obj = NULL; 4483 ring->use_doorbell = true; 4484 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4485 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4486 + (ring_id * GFX10_MEC_HPD_SIZE); 4487 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4488 4489 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4490 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4491 + ring->pipe; 4492 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 4493 ring->queue) ? 4494 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4495 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4496 r = amdgpu_ring_init(adev, ring, 1024, 4497 &adev->gfx.eop_irq, irq_type, hw_prio); 4498 if (r) 4499 return r; 4500 4501 return 0; 4502 } 4503 4504 static int gfx_v10_0_sw_init(void *handle) 4505 { 4506 int i, j, k, r, ring_id = 0; 4507 struct amdgpu_kiq *kiq; 4508 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4509 4510 switch (adev->asic_type) { 4511 case CHIP_NAVI10: 4512 case CHIP_NAVI14: 4513 case CHIP_NAVI12: 4514 adev->gfx.me.num_me = 1; 4515 adev->gfx.me.num_pipe_per_me = 1; 4516 adev->gfx.me.num_queue_per_pipe = 1; 4517 adev->gfx.mec.num_mec = 2; 4518 adev->gfx.mec.num_pipe_per_mec = 4; 4519 adev->gfx.mec.num_queue_per_pipe = 8; 4520 break; 4521 case CHIP_SIENNA_CICHLID: 4522 case CHIP_NAVY_FLOUNDER: 4523 case CHIP_VANGOGH: 4524 case CHIP_DIMGREY_CAVEFISH: 4525 adev->gfx.me.num_me = 1; 4526 adev->gfx.me.num_pipe_per_me = 1; 4527 adev->gfx.me.num_queue_per_pipe = 1; 4528 adev->gfx.mec.num_mec = 2; 4529 adev->gfx.mec.num_pipe_per_mec = 4; 4530 adev->gfx.mec.num_queue_per_pipe = 4; 4531 break; 4532 default: 4533 adev->gfx.me.num_me = 1; 4534 adev->gfx.me.num_pipe_per_me = 1; 4535 adev->gfx.me.num_queue_per_pipe = 1; 4536 adev->gfx.mec.num_mec = 1; 4537 adev->gfx.mec.num_pipe_per_mec = 4; 4538 adev->gfx.mec.num_queue_per_pipe = 8; 4539 break; 4540 } 4541 4542 /* KIQ event */ 4543 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4544 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4545 &adev->gfx.kiq.irq); 4546 if (r) 4547 return r; 4548 4549 /* EOP Event */ 4550 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4551 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4552 &adev->gfx.eop_irq); 4553 if (r) 4554 return r; 4555 4556 /* Privileged reg */ 4557 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4558 &adev->gfx.priv_reg_irq); 4559 if (r) 4560 return r; 4561 4562 /* Privileged inst */ 4563 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4564 &adev->gfx.priv_inst_irq); 4565 if (r) 4566 return r; 4567 4568 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4569 4570 gfx_v10_0_scratch_init(adev); 4571 4572 r = gfx_v10_0_me_init(adev); 4573 if (r) 4574 return r; 4575 4576 r = gfx_v10_0_rlc_init(adev); 4577 if (r) { 4578 DRM_ERROR("Failed to init rlc BOs!\n"); 4579 return r; 4580 } 4581 4582 r = gfx_v10_0_mec_init(adev); 4583 if (r) { 4584 DRM_ERROR("Failed to init MEC BOs!\n"); 4585 return r; 4586 } 4587 4588 /* set up the gfx ring */ 4589 for (i = 0; i < adev->gfx.me.num_me; i++) { 4590 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4591 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4592 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4593 continue; 4594 4595 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4596 i, k, j); 4597 if (r) 4598 return r; 4599 ring_id++; 4600 } 4601 } 4602 } 4603 4604 ring_id = 0; 4605 /* set up the compute queues - allocate horizontally across pipes */ 4606 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4607 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4608 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4609 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4610 j)) 4611 continue; 4612 4613 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4614 i, k, j); 4615 if (r) 4616 return r; 4617 4618 ring_id++; 4619 } 4620 } 4621 } 4622 4623 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4624 if (r) { 4625 DRM_ERROR("Failed to init KIQ BOs!\n"); 4626 return r; 4627 } 4628 4629 kiq = &adev->gfx.kiq; 4630 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4631 if (r) 4632 return r; 4633 4634 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4635 if (r) 4636 return r; 4637 4638 /* allocate visible FB for rlc auto-loading fw */ 4639 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4640 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4641 if (r) 4642 return r; 4643 } 4644 4645 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4646 4647 gfx_v10_0_gpu_early_init(adev); 4648 4649 return 0; 4650 } 4651 4652 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4653 { 4654 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4655 &adev->gfx.pfp.pfp_fw_gpu_addr, 4656 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4657 } 4658 4659 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4660 { 4661 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4662 &adev->gfx.ce.ce_fw_gpu_addr, 4663 (void **)&adev->gfx.ce.ce_fw_ptr); 4664 } 4665 4666 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4667 { 4668 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4669 &adev->gfx.me.me_fw_gpu_addr, 4670 (void **)&adev->gfx.me.me_fw_ptr); 4671 } 4672 4673 static int gfx_v10_0_sw_fini(void *handle) 4674 { 4675 int i; 4676 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4677 4678 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4679 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4680 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4681 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4682 4683 amdgpu_gfx_mqd_sw_fini(adev); 4684 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4685 amdgpu_gfx_kiq_fini(adev); 4686 4687 gfx_v10_0_pfp_fini(adev); 4688 gfx_v10_0_ce_fini(adev); 4689 gfx_v10_0_me_fini(adev); 4690 gfx_v10_0_rlc_fini(adev); 4691 gfx_v10_0_mec_fini(adev); 4692 4693 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4694 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4695 4696 gfx_v10_0_free_microcode(adev); 4697 4698 return 0; 4699 } 4700 4701 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4702 u32 sh_num, u32 instance) 4703 { 4704 u32 data; 4705 4706 if (instance == 0xffffffff) 4707 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4708 INSTANCE_BROADCAST_WRITES, 1); 4709 else 4710 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4711 instance); 4712 4713 if (se_num == 0xffffffff) 4714 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4715 1); 4716 else 4717 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4718 4719 if (sh_num == 0xffffffff) 4720 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4721 1); 4722 else 4723 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4724 4725 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4726 } 4727 4728 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4729 { 4730 u32 data, mask; 4731 4732 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4733 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4734 4735 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4736 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4737 4738 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4739 adev->gfx.config.max_sh_per_se); 4740 4741 return (~data) & mask; 4742 } 4743 4744 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4745 { 4746 int i, j; 4747 u32 data; 4748 u32 active_rbs = 0; 4749 u32 bitmap; 4750 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4751 adev->gfx.config.max_sh_per_se; 4752 4753 mutex_lock(&adev->grbm_idx_mutex); 4754 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4755 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4756 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4757 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 4758 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4759 continue; 4760 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4761 data = gfx_v10_0_get_rb_active_bitmap(adev); 4762 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4763 rb_bitmap_width_per_sh); 4764 } 4765 } 4766 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4767 mutex_unlock(&adev->grbm_idx_mutex); 4768 4769 adev->gfx.config.backend_enable_mask = active_rbs; 4770 adev->gfx.config.num_rbs = hweight32(active_rbs); 4771 } 4772 4773 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4774 { 4775 uint32_t num_sc; 4776 uint32_t enabled_rb_per_sh; 4777 uint32_t active_rb_bitmap; 4778 uint32_t num_rb_per_sc; 4779 uint32_t num_packer_per_sc; 4780 uint32_t pa_sc_tile_steering_override; 4781 4782 /* for ASICs that integrates GFX v10.3 4783 * pa_sc_tile_steering_override should be set to 0 */ 4784 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 4785 return 0; 4786 4787 /* init num_sc */ 4788 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4789 adev->gfx.config.num_sc_per_sh; 4790 /* init num_rb_per_sc */ 4791 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4792 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4793 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4794 /* init num_packer_per_sc */ 4795 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4796 4797 pa_sc_tile_steering_override = 0; 4798 pa_sc_tile_steering_override |= 4799 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4800 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4801 pa_sc_tile_steering_override |= 4802 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4803 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4804 pa_sc_tile_steering_override |= 4805 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4806 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4807 4808 return pa_sc_tile_steering_override; 4809 } 4810 4811 #define DEFAULT_SH_MEM_BASES (0x6000) 4812 4813 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4814 { 4815 int i; 4816 uint32_t sh_mem_bases; 4817 4818 /* 4819 * Configure apertures: 4820 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4821 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4822 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4823 */ 4824 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4825 4826 mutex_lock(&adev->srbm_mutex); 4827 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4828 nv_grbm_select(adev, 0, 0, 0, i); 4829 /* CP and shaders */ 4830 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4831 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4832 } 4833 nv_grbm_select(adev, 0, 0, 0, 0); 4834 mutex_unlock(&adev->srbm_mutex); 4835 4836 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4837 acccess. These should be enabled by FW for target VMIDs. */ 4838 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4839 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4840 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4841 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4842 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4843 } 4844 } 4845 4846 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4847 { 4848 int vmid; 4849 4850 /* 4851 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4852 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4853 * the driver can enable them for graphics. VMID0 should maintain 4854 * access so that HWS firmware can save/restore entries. 4855 */ 4856 for (vmid = 1; vmid < 16; vmid++) { 4857 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4858 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4859 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4860 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4861 } 4862 } 4863 4864 4865 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4866 { 4867 int i, j, k; 4868 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4869 u32 tmp, wgp_active_bitmap = 0; 4870 u32 gcrd_targets_disable_tcp = 0; 4871 u32 utcl_invreq_disable = 0; 4872 /* 4873 * GCRD_TARGETS_DISABLE field contains 4874 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4875 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4876 */ 4877 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4878 2 * max_wgp_per_sh + /* TCP */ 4879 max_wgp_per_sh + /* SQC */ 4880 4); /* GL1C */ 4881 /* 4882 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4883 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4884 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4885 */ 4886 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4887 2 * max_wgp_per_sh + /* TCP */ 4888 2 * max_wgp_per_sh + /* SQC */ 4889 4 + /* RMI */ 4890 1); /* SQG */ 4891 4892 if (adev->asic_type == CHIP_NAVI10 || 4893 adev->asic_type == CHIP_NAVI14 || 4894 adev->asic_type == CHIP_NAVI12) { 4895 mutex_lock(&adev->grbm_idx_mutex); 4896 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4897 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4898 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4899 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4900 /* 4901 * Set corresponding TCP bits for the inactive WGPs in 4902 * GCRD_SA_TARGETS_DISABLE 4903 */ 4904 gcrd_targets_disable_tcp = 0; 4905 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4906 utcl_invreq_disable = 0; 4907 4908 for (k = 0; k < max_wgp_per_sh; k++) { 4909 if (!(wgp_active_bitmap & (1 << k))) { 4910 gcrd_targets_disable_tcp |= 3 << (2 * k); 4911 utcl_invreq_disable |= (3 << (2 * k)) | 4912 (3 << (2 * (max_wgp_per_sh + k))); 4913 } 4914 } 4915 4916 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4917 /* only override TCP & SQC bits */ 4918 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 4919 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4920 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4921 4922 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4923 /* only override TCP bits */ 4924 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 4925 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4926 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4927 } 4928 } 4929 4930 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4931 mutex_unlock(&adev->grbm_idx_mutex); 4932 } 4933 } 4934 4935 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4936 { 4937 /* TCCs are global (not instanced). */ 4938 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4939 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4940 4941 adev->gfx.config.tcc_disabled_mask = 4942 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4943 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4944 } 4945 4946 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4947 { 4948 u32 tmp; 4949 int i; 4950 4951 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4952 4953 gfx_v10_0_setup_rb(adev); 4954 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4955 gfx_v10_0_get_tcc_info(adev); 4956 adev->gfx.config.pa_sc_tile_steering_override = 4957 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4958 4959 /* XXX SH_MEM regs */ 4960 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4961 mutex_lock(&adev->srbm_mutex); 4962 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 4963 nv_grbm_select(adev, 0, 0, 0, i); 4964 /* CP and shaders */ 4965 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4966 if (i != 0) { 4967 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4968 (adev->gmc.private_aperture_start >> 48)); 4969 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4970 (adev->gmc.shared_aperture_start >> 48)); 4971 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4972 } 4973 } 4974 nv_grbm_select(adev, 0, 0, 0, 0); 4975 4976 mutex_unlock(&adev->srbm_mutex); 4977 4978 gfx_v10_0_init_compute_vmid(adev); 4979 gfx_v10_0_init_gds_vmid(adev); 4980 4981 } 4982 4983 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 4984 bool enable) 4985 { 4986 u32 tmp; 4987 4988 if (amdgpu_sriov_vf(adev)) 4989 return; 4990 4991 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 4992 4993 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 4994 enable ? 1 : 0); 4995 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 4996 enable ? 1 : 0); 4997 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 4998 enable ? 1 : 0); 4999 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5000 enable ? 1 : 0); 5001 5002 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5003 } 5004 5005 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5006 { 5007 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5008 5009 /* csib */ 5010 if (adev->asic_type == CHIP_NAVI12) { 5011 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5012 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5013 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5014 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5015 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5016 } else { 5017 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5018 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5019 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5020 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5021 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5022 } 5023 return 0; 5024 } 5025 5026 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5027 { 5028 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5029 5030 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5031 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5032 } 5033 5034 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5035 { 5036 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5037 udelay(50); 5038 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5039 udelay(50); 5040 } 5041 5042 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5043 bool enable) 5044 { 5045 uint32_t rlc_pg_cntl; 5046 5047 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5048 5049 if (!enable) { 5050 /* RLC_PG_CNTL[23] = 0 (default) 5051 * RLC will wait for handshake acks with SMU 5052 * GFXOFF will be enabled 5053 * RLC_PG_CNTL[23] = 1 5054 * RLC will not issue any message to SMU 5055 * hence no handshake between SMU & RLC 5056 * GFXOFF will be disabled 5057 */ 5058 rlc_pg_cntl |= 0x800000; 5059 } else 5060 rlc_pg_cntl &= ~0x800000; 5061 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5062 } 5063 5064 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5065 { 5066 /* TODO: enable rlc & smu handshake until smu 5067 * and gfxoff feature works as expected */ 5068 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5069 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5070 5071 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5072 udelay(50); 5073 } 5074 5075 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5076 { 5077 uint32_t tmp; 5078 5079 /* enable Save Restore Machine */ 5080 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 5081 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5082 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5083 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 5084 } 5085 5086 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5087 { 5088 const struct rlc_firmware_header_v2_0 *hdr; 5089 const __le32 *fw_data; 5090 unsigned i, fw_size; 5091 5092 if (!adev->gfx.rlc_fw) 5093 return -EINVAL; 5094 5095 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5096 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5097 5098 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5099 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5100 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5101 5102 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5103 RLCG_UCODE_LOADING_START_ADDRESS); 5104 5105 for (i = 0; i < fw_size; i++) 5106 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5107 le32_to_cpup(fw_data++)); 5108 5109 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5110 5111 return 0; 5112 } 5113 5114 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5115 { 5116 int r; 5117 5118 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 5119 5120 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5121 if (r) 5122 return r; 5123 5124 gfx_v10_0_init_csb(adev); 5125 5126 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5127 gfx_v10_0_rlc_enable_srm(adev); 5128 } else { 5129 if (amdgpu_sriov_vf(adev)) { 5130 gfx_v10_0_init_csb(adev); 5131 return 0; 5132 } 5133 5134 adev->gfx.rlc.funcs->stop(adev); 5135 5136 /* disable CG */ 5137 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5138 5139 /* disable PG */ 5140 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5141 5142 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5143 /* legacy rlc firmware loading */ 5144 r = gfx_v10_0_rlc_load_microcode(adev); 5145 if (r) 5146 return r; 5147 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5148 /* rlc backdoor autoload firmware */ 5149 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5150 if (r) 5151 return r; 5152 } 5153 5154 gfx_v10_0_init_csb(adev); 5155 5156 adev->gfx.rlc.funcs->start(adev); 5157 5158 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5159 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5160 if (r) 5161 return r; 5162 } 5163 } 5164 return 0; 5165 } 5166 5167 static struct { 5168 FIRMWARE_ID id; 5169 unsigned int offset; 5170 unsigned int size; 5171 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5172 5173 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5174 { 5175 int ret; 5176 RLC_TABLE_OF_CONTENT *rlc_toc; 5177 5178 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 5179 AMDGPU_GEM_DOMAIN_GTT, 5180 &adev->gfx.rlc.rlc_toc_bo, 5181 &adev->gfx.rlc.rlc_toc_gpu_addr, 5182 (void **)&adev->gfx.rlc.rlc_toc_buf); 5183 if (ret) { 5184 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5185 return ret; 5186 } 5187 5188 /* Copy toc from psp sos fw to rlc toc buffer */ 5189 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 5190 5191 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5192 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5193 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5194 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5195 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5196 /* Offset needs 4KB alignment */ 5197 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5198 } 5199 5200 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5201 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5202 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5203 5204 rlc_toc++; 5205 } 5206 5207 return 0; 5208 } 5209 5210 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5211 { 5212 uint32_t total_size = 0; 5213 FIRMWARE_ID id; 5214 int ret; 5215 5216 ret = gfx_v10_0_parse_rlc_toc(adev); 5217 if (ret) { 5218 dev_err(adev->dev, "failed to parse rlc toc\n"); 5219 return 0; 5220 } 5221 5222 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5223 total_size += rlc_autoload_info[id].size; 5224 5225 /* In case the offset in rlc toc ucode is aligned */ 5226 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5227 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5228 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5229 5230 return total_size; 5231 } 5232 5233 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5234 { 5235 int r; 5236 uint32_t total_size; 5237 5238 total_size = gfx_v10_0_calc_toc_total_size(adev); 5239 5240 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5241 AMDGPU_GEM_DOMAIN_GTT, 5242 &adev->gfx.rlc.rlc_autoload_bo, 5243 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5244 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5245 if (r) { 5246 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5247 return r; 5248 } 5249 5250 return 0; 5251 } 5252 5253 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5254 { 5255 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5256 &adev->gfx.rlc.rlc_toc_gpu_addr, 5257 (void **)&adev->gfx.rlc.rlc_toc_buf); 5258 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5259 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5260 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5261 } 5262 5263 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5264 FIRMWARE_ID id, 5265 const void *fw_data, 5266 uint32_t fw_size) 5267 { 5268 uint32_t toc_offset; 5269 uint32_t toc_fw_size; 5270 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5271 5272 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5273 return; 5274 5275 toc_offset = rlc_autoload_info[id].offset; 5276 toc_fw_size = rlc_autoload_info[id].size; 5277 5278 if (fw_size == 0) 5279 fw_size = toc_fw_size; 5280 5281 if (fw_size > toc_fw_size) 5282 fw_size = toc_fw_size; 5283 5284 memcpy(ptr + toc_offset, fw_data, fw_size); 5285 5286 if (fw_size < toc_fw_size) 5287 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5288 } 5289 5290 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5291 { 5292 void *data; 5293 uint32_t size; 5294 5295 data = adev->gfx.rlc.rlc_toc_buf; 5296 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5297 5298 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5299 FIRMWARE_ID_RLC_TOC, 5300 data, size); 5301 } 5302 5303 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5304 { 5305 const __le32 *fw_data; 5306 uint32_t fw_size; 5307 const struct gfx_firmware_header_v1_0 *cp_hdr; 5308 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5309 5310 /* pfp ucode */ 5311 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5312 adev->gfx.pfp_fw->data; 5313 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5314 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5315 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5316 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5317 FIRMWARE_ID_CP_PFP, 5318 fw_data, fw_size); 5319 5320 /* ce ucode */ 5321 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5322 adev->gfx.ce_fw->data; 5323 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5324 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5325 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5326 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5327 FIRMWARE_ID_CP_CE, 5328 fw_data, fw_size); 5329 5330 /* me ucode */ 5331 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5332 adev->gfx.me_fw->data; 5333 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5334 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5335 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5336 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5337 FIRMWARE_ID_CP_ME, 5338 fw_data, fw_size); 5339 5340 /* rlc ucode */ 5341 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5342 adev->gfx.rlc_fw->data; 5343 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5344 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5345 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5346 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5347 FIRMWARE_ID_RLC_G_UCODE, 5348 fw_data, fw_size); 5349 5350 /* mec1 ucode */ 5351 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5352 adev->gfx.mec_fw->data; 5353 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5354 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5355 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5356 cp_hdr->jt_size * 4; 5357 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5358 FIRMWARE_ID_CP_MEC, 5359 fw_data, fw_size); 5360 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5361 } 5362 5363 /* Temporarily put sdma part here */ 5364 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5365 { 5366 const __le32 *fw_data; 5367 uint32_t fw_size; 5368 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5369 int i; 5370 5371 for (i = 0; i < adev->sdma.num_instances; i++) { 5372 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5373 adev->sdma.instance[i].fw->data; 5374 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5375 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5376 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5377 5378 if (i == 0) { 5379 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5380 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5381 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5382 FIRMWARE_ID_SDMA0_JT, 5383 (uint32_t *)fw_data + 5384 sdma_hdr->jt_offset, 5385 sdma_hdr->jt_size * 4); 5386 } else if (i == 1) { 5387 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5388 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5389 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5390 FIRMWARE_ID_SDMA1_JT, 5391 (uint32_t *)fw_data + 5392 sdma_hdr->jt_offset, 5393 sdma_hdr->jt_size * 4); 5394 } 5395 } 5396 } 5397 5398 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5399 { 5400 uint32_t rlc_g_offset, rlc_g_size, tmp; 5401 uint64_t gpu_addr; 5402 5403 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5404 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5405 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5406 5407 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5408 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5409 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5410 5411 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5412 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5413 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5414 5415 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5416 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5417 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5418 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5419 return -EINVAL; 5420 } 5421 5422 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5423 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5424 DRM_ERROR("RLC ROM should halt itself\n"); 5425 return -EINVAL; 5426 } 5427 5428 return 0; 5429 } 5430 5431 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5432 { 5433 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5434 uint32_t tmp; 5435 int i; 5436 uint64_t addr; 5437 5438 /* Trigger an invalidation of the L1 instruction caches */ 5439 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5440 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5441 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5442 5443 /* Wait for invalidation complete */ 5444 for (i = 0; i < usec_timeout; i++) { 5445 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5446 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5447 INVALIDATE_CACHE_COMPLETE)) 5448 break; 5449 udelay(1); 5450 } 5451 5452 if (i >= usec_timeout) { 5453 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5454 return -EINVAL; 5455 } 5456 5457 /* Program me ucode address into intruction cache address register */ 5458 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5459 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5460 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5461 lower_32_bits(addr) & 0xFFFFF000); 5462 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5463 upper_32_bits(addr)); 5464 5465 return 0; 5466 } 5467 5468 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5469 { 5470 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5471 uint32_t tmp; 5472 int i; 5473 uint64_t addr; 5474 5475 /* Trigger an invalidation of the L1 instruction caches */ 5476 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5477 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5478 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5479 5480 /* Wait for invalidation complete */ 5481 for (i = 0; i < usec_timeout; i++) { 5482 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5483 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5484 INVALIDATE_CACHE_COMPLETE)) 5485 break; 5486 udelay(1); 5487 } 5488 5489 if (i >= usec_timeout) { 5490 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5491 return -EINVAL; 5492 } 5493 5494 /* Program ce ucode address into intruction cache address register */ 5495 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5496 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5497 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5498 lower_32_bits(addr) & 0xFFFFF000); 5499 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5500 upper_32_bits(addr)); 5501 5502 return 0; 5503 } 5504 5505 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5506 { 5507 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5508 uint32_t tmp; 5509 int i; 5510 uint64_t addr; 5511 5512 /* Trigger an invalidation of the L1 instruction caches */ 5513 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5514 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5515 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5516 5517 /* Wait for invalidation complete */ 5518 for (i = 0; i < usec_timeout; i++) { 5519 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5520 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5521 INVALIDATE_CACHE_COMPLETE)) 5522 break; 5523 udelay(1); 5524 } 5525 5526 if (i >= usec_timeout) { 5527 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5528 return -EINVAL; 5529 } 5530 5531 /* Program pfp ucode address into intruction cache address register */ 5532 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5533 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5534 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5535 lower_32_bits(addr) & 0xFFFFF000); 5536 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5537 upper_32_bits(addr)); 5538 5539 return 0; 5540 } 5541 5542 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5543 { 5544 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5545 uint32_t tmp; 5546 int i; 5547 uint64_t addr; 5548 5549 /* Trigger an invalidation of the L1 instruction caches */ 5550 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5551 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5552 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5553 5554 /* Wait for invalidation complete */ 5555 for (i = 0; i < usec_timeout; i++) { 5556 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5557 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5558 INVALIDATE_CACHE_COMPLETE)) 5559 break; 5560 udelay(1); 5561 } 5562 5563 if (i >= usec_timeout) { 5564 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5565 return -EINVAL; 5566 } 5567 5568 /* Program mec1 ucode address into intruction cache address register */ 5569 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5570 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5571 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5572 lower_32_bits(addr) & 0xFFFFF000); 5573 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5574 upper_32_bits(addr)); 5575 5576 return 0; 5577 } 5578 5579 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5580 { 5581 uint32_t cp_status; 5582 uint32_t bootload_status; 5583 int i, r; 5584 5585 for (i = 0; i < adev->usec_timeout; i++) { 5586 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5587 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5588 if ((cp_status == 0) && 5589 (REG_GET_FIELD(bootload_status, 5590 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5591 break; 5592 } 5593 udelay(1); 5594 } 5595 5596 if (i >= adev->usec_timeout) { 5597 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5598 return -ETIMEDOUT; 5599 } 5600 5601 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5602 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5603 if (r) 5604 return r; 5605 5606 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5607 if (r) 5608 return r; 5609 5610 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5611 if (r) 5612 return r; 5613 5614 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5615 if (r) 5616 return r; 5617 } 5618 5619 return 0; 5620 } 5621 5622 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5623 { 5624 int i; 5625 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5626 5627 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5628 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5629 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5630 5631 if (adev->asic_type == CHIP_NAVI12) { 5632 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5633 } else { 5634 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5635 } 5636 5637 for (i = 0; i < adev->usec_timeout; i++) { 5638 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5639 break; 5640 udelay(1); 5641 } 5642 5643 if (i >= adev->usec_timeout) 5644 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5645 5646 return 0; 5647 } 5648 5649 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5650 { 5651 int r; 5652 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5653 const __le32 *fw_data; 5654 unsigned i, fw_size; 5655 uint32_t tmp; 5656 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5657 5658 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5659 adev->gfx.pfp_fw->data; 5660 5661 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5662 5663 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5664 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5665 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5666 5667 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5668 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5669 &adev->gfx.pfp.pfp_fw_obj, 5670 &adev->gfx.pfp.pfp_fw_gpu_addr, 5671 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5672 if (r) { 5673 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5674 gfx_v10_0_pfp_fini(adev); 5675 return r; 5676 } 5677 5678 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5679 5680 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5681 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5682 5683 /* Trigger an invalidation of the L1 instruction caches */ 5684 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5685 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5686 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5687 5688 /* Wait for invalidation complete */ 5689 for (i = 0; i < usec_timeout; i++) { 5690 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5691 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5692 INVALIDATE_CACHE_COMPLETE)) 5693 break; 5694 udelay(1); 5695 } 5696 5697 if (i >= usec_timeout) { 5698 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5699 return -EINVAL; 5700 } 5701 5702 if (amdgpu_emu_mode == 1) 5703 adev->nbio.funcs->hdp_flush(adev, NULL); 5704 5705 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5706 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5707 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5708 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5709 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5710 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5711 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5712 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5713 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5714 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5715 5716 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5717 5718 for (i = 0; i < pfp_hdr->jt_size; i++) 5719 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5720 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5721 5722 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5723 5724 return 0; 5725 } 5726 5727 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5728 { 5729 int r; 5730 const struct gfx_firmware_header_v1_0 *ce_hdr; 5731 const __le32 *fw_data; 5732 unsigned i, fw_size; 5733 uint32_t tmp; 5734 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5735 5736 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5737 adev->gfx.ce_fw->data; 5738 5739 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5740 5741 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5742 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5743 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5744 5745 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5746 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5747 &adev->gfx.ce.ce_fw_obj, 5748 &adev->gfx.ce.ce_fw_gpu_addr, 5749 (void **)&adev->gfx.ce.ce_fw_ptr); 5750 if (r) { 5751 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5752 gfx_v10_0_ce_fini(adev); 5753 return r; 5754 } 5755 5756 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5757 5758 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5759 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5760 5761 /* Trigger an invalidation of the L1 instruction caches */ 5762 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5763 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5764 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5765 5766 /* Wait for invalidation complete */ 5767 for (i = 0; i < usec_timeout; i++) { 5768 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5769 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5770 INVALIDATE_CACHE_COMPLETE)) 5771 break; 5772 udelay(1); 5773 } 5774 5775 if (i >= usec_timeout) { 5776 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5777 return -EINVAL; 5778 } 5779 5780 if (amdgpu_emu_mode == 1) 5781 adev->nbio.funcs->hdp_flush(adev, NULL); 5782 5783 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5784 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5785 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5786 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5787 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5788 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5789 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5790 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5791 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5792 5793 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5794 5795 for (i = 0; i < ce_hdr->jt_size; i++) 5796 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5797 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5798 5799 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5800 5801 return 0; 5802 } 5803 5804 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5805 { 5806 int r; 5807 const struct gfx_firmware_header_v1_0 *me_hdr; 5808 const __le32 *fw_data; 5809 unsigned i, fw_size; 5810 uint32_t tmp; 5811 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5812 5813 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5814 adev->gfx.me_fw->data; 5815 5816 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5817 5818 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5819 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5820 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5821 5822 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5823 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5824 &adev->gfx.me.me_fw_obj, 5825 &adev->gfx.me.me_fw_gpu_addr, 5826 (void **)&adev->gfx.me.me_fw_ptr); 5827 if (r) { 5828 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5829 gfx_v10_0_me_fini(adev); 5830 return r; 5831 } 5832 5833 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5834 5835 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5836 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5837 5838 /* Trigger an invalidation of the L1 instruction caches */ 5839 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5840 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5841 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5842 5843 /* Wait for invalidation complete */ 5844 for (i = 0; i < usec_timeout; i++) { 5845 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5846 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5847 INVALIDATE_CACHE_COMPLETE)) 5848 break; 5849 udelay(1); 5850 } 5851 5852 if (i >= usec_timeout) { 5853 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5854 return -EINVAL; 5855 } 5856 5857 if (amdgpu_emu_mode == 1) 5858 adev->nbio.funcs->hdp_flush(adev, NULL); 5859 5860 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5861 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5862 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5863 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5864 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5865 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5866 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5867 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5868 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5869 5870 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5871 5872 for (i = 0; i < me_hdr->jt_size; i++) 5873 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5874 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5875 5876 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5877 5878 return 0; 5879 } 5880 5881 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5882 { 5883 int r; 5884 5885 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5886 return -EINVAL; 5887 5888 gfx_v10_0_cp_gfx_enable(adev, false); 5889 5890 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5891 if (r) { 5892 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5893 return r; 5894 } 5895 5896 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5897 if (r) { 5898 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5899 return r; 5900 } 5901 5902 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5903 if (r) { 5904 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5905 return r; 5906 } 5907 5908 return 0; 5909 } 5910 5911 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5912 { 5913 struct amdgpu_ring *ring; 5914 const struct cs_section_def *sect = NULL; 5915 const struct cs_extent_def *ext = NULL; 5916 int r, i; 5917 int ctx_reg_offset; 5918 5919 /* init the CP */ 5920 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5921 adev->gfx.config.max_hw_contexts - 1); 5922 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5923 5924 gfx_v10_0_cp_gfx_enable(adev, true); 5925 5926 ring = &adev->gfx.gfx_ring[0]; 5927 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5928 if (r) { 5929 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5930 return r; 5931 } 5932 5933 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5934 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5935 5936 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5937 amdgpu_ring_write(ring, 0x80000000); 5938 amdgpu_ring_write(ring, 0x80000000); 5939 5940 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5941 for (ext = sect->section; ext->extent != NULL; ++ext) { 5942 if (sect->id == SECT_CONTEXT) { 5943 amdgpu_ring_write(ring, 5944 PACKET3(PACKET3_SET_CONTEXT_REG, 5945 ext->reg_count)); 5946 amdgpu_ring_write(ring, ext->reg_index - 5947 PACKET3_SET_CONTEXT_REG_START); 5948 for (i = 0; i < ext->reg_count; i++) 5949 amdgpu_ring_write(ring, ext->extent[i]); 5950 } 5951 } 5952 } 5953 5954 ctx_reg_offset = 5955 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5956 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5957 amdgpu_ring_write(ring, ctx_reg_offset); 5958 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5959 5960 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5961 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5962 5963 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5964 amdgpu_ring_write(ring, 0); 5965 5966 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 5967 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 5968 amdgpu_ring_write(ring, 0x8000); 5969 amdgpu_ring_write(ring, 0x8000); 5970 5971 amdgpu_ring_commit(ring); 5972 5973 /* submit cs packet to copy state 0 to next available state */ 5974 if (adev->gfx.num_gfx_rings > 1) { 5975 /* maximum supported gfx ring is 2 */ 5976 ring = &adev->gfx.gfx_ring[1]; 5977 r = amdgpu_ring_alloc(ring, 2); 5978 if (r) { 5979 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5980 return r; 5981 } 5982 5983 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5984 amdgpu_ring_write(ring, 0); 5985 5986 amdgpu_ring_commit(ring); 5987 } 5988 return 0; 5989 } 5990 5991 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 5992 CP_PIPE_ID pipe) 5993 { 5994 u32 tmp; 5995 5996 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 5997 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 5998 5999 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6000 } 6001 6002 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6003 struct amdgpu_ring *ring) 6004 { 6005 u32 tmp; 6006 6007 if (!amdgpu_async_gfx_ring) { 6008 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6009 if (ring->use_doorbell) { 6010 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6011 DOORBELL_OFFSET, ring->doorbell_index); 6012 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6013 DOORBELL_EN, 1); 6014 } else { 6015 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6016 DOORBELL_EN, 0); 6017 } 6018 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6019 } 6020 switch (adev->asic_type) { 6021 case CHIP_SIENNA_CICHLID: 6022 case CHIP_NAVY_FLOUNDER: 6023 case CHIP_VANGOGH: 6024 case CHIP_DIMGREY_CAVEFISH: 6025 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6026 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6027 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6028 6029 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6030 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6031 break; 6032 default: 6033 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6034 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6035 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6036 6037 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6038 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6039 break; 6040 } 6041 } 6042 6043 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6044 { 6045 struct amdgpu_ring *ring; 6046 u32 tmp; 6047 u32 rb_bufsz; 6048 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6049 u32 i; 6050 6051 /* Set the write pointer delay */ 6052 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6053 6054 /* set the RB to use vmid 0 */ 6055 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6056 6057 /* Init gfx ring 0 for pipe 0 */ 6058 mutex_lock(&adev->srbm_mutex); 6059 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6060 6061 /* Set ring buffer size */ 6062 ring = &adev->gfx.gfx_ring[0]; 6063 rb_bufsz = order_base_2(ring->ring_size / 8); 6064 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6065 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6066 #ifdef __BIG_ENDIAN 6067 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6068 #endif 6069 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6070 6071 /* Initialize the ring buffer's write pointers */ 6072 ring->wptr = 0; 6073 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6074 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6075 6076 /* set the wb address wether it's enabled or not */ 6077 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6078 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6079 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6080 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6081 6082 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6083 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6084 lower_32_bits(wptr_gpu_addr)); 6085 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6086 upper_32_bits(wptr_gpu_addr)); 6087 6088 mdelay(1); 6089 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6090 6091 rb_addr = ring->gpu_addr >> 8; 6092 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6093 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6094 6095 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6096 6097 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6098 mutex_unlock(&adev->srbm_mutex); 6099 6100 /* Init gfx ring 1 for pipe 1 */ 6101 if (adev->gfx.num_gfx_rings > 1) { 6102 mutex_lock(&adev->srbm_mutex); 6103 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6104 /* maximum supported gfx ring is 2 */ 6105 ring = &adev->gfx.gfx_ring[1]; 6106 rb_bufsz = order_base_2(ring->ring_size / 8); 6107 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6108 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6109 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6110 /* Initialize the ring buffer's write pointers */ 6111 ring->wptr = 0; 6112 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6113 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6114 /* Set the wb address wether it's enabled or not */ 6115 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6116 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6117 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6118 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6119 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6120 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6121 lower_32_bits(wptr_gpu_addr)); 6122 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6123 upper_32_bits(wptr_gpu_addr)); 6124 6125 mdelay(1); 6126 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6127 6128 rb_addr = ring->gpu_addr >> 8; 6129 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6130 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6131 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6132 6133 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6134 mutex_unlock(&adev->srbm_mutex); 6135 } 6136 /* Switch to pipe 0 */ 6137 mutex_lock(&adev->srbm_mutex); 6138 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6139 mutex_unlock(&adev->srbm_mutex); 6140 6141 /* start the ring */ 6142 gfx_v10_0_cp_gfx_start(adev); 6143 6144 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6145 ring = &adev->gfx.gfx_ring[i]; 6146 ring->sched.ready = true; 6147 } 6148 6149 return 0; 6150 } 6151 6152 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6153 { 6154 if (enable) { 6155 switch (adev->asic_type) { 6156 case CHIP_SIENNA_CICHLID: 6157 case CHIP_NAVY_FLOUNDER: 6158 case CHIP_VANGOGH: 6159 case CHIP_DIMGREY_CAVEFISH: 6160 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6161 break; 6162 default: 6163 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6164 break; 6165 } 6166 } else { 6167 switch (adev->asic_type) { 6168 case CHIP_SIENNA_CICHLID: 6169 case CHIP_NAVY_FLOUNDER: 6170 case CHIP_VANGOGH: 6171 case CHIP_DIMGREY_CAVEFISH: 6172 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6173 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6174 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6175 break; 6176 default: 6177 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6178 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6179 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6180 break; 6181 } 6182 adev->gfx.kiq.ring.sched.ready = false; 6183 } 6184 udelay(50); 6185 } 6186 6187 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6188 { 6189 const struct gfx_firmware_header_v1_0 *mec_hdr; 6190 const __le32 *fw_data; 6191 unsigned i; 6192 u32 tmp; 6193 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6194 6195 if (!adev->gfx.mec_fw) 6196 return -EINVAL; 6197 6198 gfx_v10_0_cp_compute_enable(adev, false); 6199 6200 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6201 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6202 6203 fw_data = (const __le32 *) 6204 (adev->gfx.mec_fw->data + 6205 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6206 6207 /* Trigger an invalidation of the L1 instruction caches */ 6208 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6209 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6210 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6211 6212 /* Wait for invalidation complete */ 6213 for (i = 0; i < usec_timeout; i++) { 6214 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6215 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6216 INVALIDATE_CACHE_COMPLETE)) 6217 break; 6218 udelay(1); 6219 } 6220 6221 if (i >= usec_timeout) { 6222 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6223 return -EINVAL; 6224 } 6225 6226 if (amdgpu_emu_mode == 1) 6227 adev->nbio.funcs->hdp_flush(adev, NULL); 6228 6229 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6230 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6231 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6232 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6233 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6234 6235 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6236 0xFFFFF000); 6237 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6238 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6239 6240 /* MEC1 */ 6241 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6242 6243 for (i = 0; i < mec_hdr->jt_size; i++) 6244 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6245 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6246 6247 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6248 6249 /* 6250 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6251 * different microcode than MEC1. 6252 */ 6253 6254 return 0; 6255 } 6256 6257 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6258 { 6259 uint32_t tmp; 6260 struct amdgpu_device *adev = ring->adev; 6261 6262 /* tell RLC which is KIQ queue */ 6263 switch (adev->asic_type) { 6264 case CHIP_SIENNA_CICHLID: 6265 case CHIP_NAVY_FLOUNDER: 6266 case CHIP_VANGOGH: 6267 case CHIP_DIMGREY_CAVEFISH: 6268 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6269 tmp &= 0xffffff00; 6270 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6271 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6272 tmp |= 0x80; 6273 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6274 break; 6275 default: 6276 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6277 tmp &= 0xffffff00; 6278 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6279 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6280 tmp |= 0x80; 6281 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6282 break; 6283 } 6284 } 6285 6286 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6287 { 6288 struct amdgpu_device *adev = ring->adev; 6289 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6290 uint64_t hqd_gpu_addr, wb_gpu_addr; 6291 uint32_t tmp; 6292 uint32_t rb_bufsz; 6293 6294 /* set up gfx hqd wptr */ 6295 mqd->cp_gfx_hqd_wptr = 0; 6296 mqd->cp_gfx_hqd_wptr_hi = 0; 6297 6298 /* set the pointer to the MQD */ 6299 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6300 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6301 6302 /* set up mqd control */ 6303 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6304 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6305 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6306 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6307 mqd->cp_gfx_mqd_control = tmp; 6308 6309 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6310 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6311 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6312 mqd->cp_gfx_hqd_vmid = 0; 6313 6314 /* set up default queue priority level 6315 * 0x0 = low priority, 0x1 = high priority */ 6316 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6317 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6318 mqd->cp_gfx_hqd_queue_priority = tmp; 6319 6320 /* set up time quantum */ 6321 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6322 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6323 mqd->cp_gfx_hqd_quantum = tmp; 6324 6325 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6326 hqd_gpu_addr = ring->gpu_addr >> 8; 6327 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6328 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6329 6330 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6331 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6332 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6333 mqd->cp_gfx_hqd_rptr_addr_hi = 6334 upper_32_bits(wb_gpu_addr) & 0xffff; 6335 6336 /* set up rb_wptr_poll addr */ 6337 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6338 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6339 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6340 6341 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6342 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6343 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6344 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6345 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6346 #ifdef __BIG_ENDIAN 6347 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6348 #endif 6349 mqd->cp_gfx_hqd_cntl = tmp; 6350 6351 /* set up cp_doorbell_control */ 6352 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6353 if (ring->use_doorbell) { 6354 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6355 DOORBELL_OFFSET, ring->doorbell_index); 6356 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6357 DOORBELL_EN, 1); 6358 } else 6359 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6360 DOORBELL_EN, 0); 6361 mqd->cp_rb_doorbell_control = tmp; 6362 6363 /*if there are 2 gfx rings, set the lower doorbell range of the first ring, 6364 *otherwise the range of the second ring will override the first ring */ 6365 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6366 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6367 6368 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6369 ring->wptr = 0; 6370 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6371 6372 /* active the queue */ 6373 mqd->cp_gfx_hqd_active = 1; 6374 6375 return 0; 6376 } 6377 6378 #ifdef BRING_UP_DEBUG 6379 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6380 { 6381 struct amdgpu_device *adev = ring->adev; 6382 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6383 6384 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6385 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6386 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6387 6388 /* set GFX_MQD_BASE */ 6389 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6390 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6391 6392 /* set GFX_MQD_CONTROL */ 6393 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6394 6395 /* set GFX_HQD_VMID to 0 */ 6396 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6397 6398 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6399 mqd->cp_gfx_hqd_queue_priority); 6400 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6401 6402 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6403 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6404 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6405 6406 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6407 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6408 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6409 6410 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6411 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6412 6413 /* set RB_WPTR_POLL_ADDR */ 6414 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6415 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6416 6417 /* set RB_DOORBELL_CONTROL */ 6418 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6419 6420 /* active the queue */ 6421 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6422 6423 return 0; 6424 } 6425 #endif 6426 6427 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6428 { 6429 struct amdgpu_device *adev = ring->adev; 6430 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6431 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6432 6433 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6434 memset((void *)mqd, 0, sizeof(*mqd)); 6435 mutex_lock(&adev->srbm_mutex); 6436 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6437 gfx_v10_0_gfx_mqd_init(ring); 6438 #ifdef BRING_UP_DEBUG 6439 gfx_v10_0_gfx_queue_init_register(ring); 6440 #endif 6441 nv_grbm_select(adev, 0, 0, 0, 0); 6442 mutex_unlock(&adev->srbm_mutex); 6443 if (adev->gfx.me.mqd_backup[mqd_idx]) 6444 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6445 } else if (amdgpu_in_reset(adev)) { 6446 /* reset mqd with the backup copy */ 6447 if (adev->gfx.me.mqd_backup[mqd_idx]) 6448 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6449 /* reset the ring */ 6450 ring->wptr = 0; 6451 adev->wb.wb[ring->wptr_offs] = 0; 6452 amdgpu_ring_clear_ring(ring); 6453 #ifdef BRING_UP_DEBUG 6454 mutex_lock(&adev->srbm_mutex); 6455 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6456 gfx_v10_0_gfx_queue_init_register(ring); 6457 nv_grbm_select(adev, 0, 0, 0, 0); 6458 mutex_unlock(&adev->srbm_mutex); 6459 #endif 6460 } else { 6461 amdgpu_ring_clear_ring(ring); 6462 } 6463 6464 return 0; 6465 } 6466 6467 #ifndef BRING_UP_DEBUG 6468 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6469 { 6470 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6471 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6472 int r, i; 6473 6474 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6475 return -EINVAL; 6476 6477 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6478 adev->gfx.num_gfx_rings); 6479 if (r) { 6480 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6481 return r; 6482 } 6483 6484 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6485 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6486 6487 return amdgpu_ring_test_helper(kiq_ring); 6488 } 6489 #endif 6490 6491 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6492 { 6493 int r, i; 6494 struct amdgpu_ring *ring; 6495 6496 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6497 ring = &adev->gfx.gfx_ring[i]; 6498 6499 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6500 if (unlikely(r != 0)) 6501 goto done; 6502 6503 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6504 if (!r) { 6505 r = gfx_v10_0_gfx_init_queue(ring); 6506 amdgpu_bo_kunmap(ring->mqd_obj); 6507 ring->mqd_ptr = NULL; 6508 } 6509 amdgpu_bo_unreserve(ring->mqd_obj); 6510 if (r) 6511 goto done; 6512 } 6513 #ifndef BRING_UP_DEBUG 6514 r = gfx_v10_0_kiq_enable_kgq(adev); 6515 if (r) 6516 goto done; 6517 #endif 6518 r = gfx_v10_0_cp_gfx_start(adev); 6519 if (r) 6520 goto done; 6521 6522 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6523 ring = &adev->gfx.gfx_ring[i]; 6524 ring->sched.ready = true; 6525 } 6526 done: 6527 return r; 6528 } 6529 6530 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6531 { 6532 struct amdgpu_device *adev = ring->adev; 6533 6534 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6535 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 6536 ring->queue)) { 6537 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6538 mqd->cp_hqd_queue_priority = 6539 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6540 } 6541 } 6542 } 6543 6544 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6545 { 6546 struct amdgpu_device *adev = ring->adev; 6547 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6548 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6549 uint32_t tmp; 6550 6551 mqd->header = 0xC0310800; 6552 mqd->compute_pipelinestat_enable = 0x00000001; 6553 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6554 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6555 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6556 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6557 mqd->compute_misc_reserved = 0x00000003; 6558 6559 eop_base_addr = ring->eop_gpu_addr >> 8; 6560 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6561 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6562 6563 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6564 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6565 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6566 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6567 6568 mqd->cp_hqd_eop_control = tmp; 6569 6570 /* enable doorbell? */ 6571 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6572 6573 if (ring->use_doorbell) { 6574 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6575 DOORBELL_OFFSET, ring->doorbell_index); 6576 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6577 DOORBELL_EN, 1); 6578 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6579 DOORBELL_SOURCE, 0); 6580 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6581 DOORBELL_HIT, 0); 6582 } else { 6583 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6584 DOORBELL_EN, 0); 6585 } 6586 6587 mqd->cp_hqd_pq_doorbell_control = tmp; 6588 6589 /* disable the queue if it's active */ 6590 ring->wptr = 0; 6591 mqd->cp_hqd_dequeue_request = 0; 6592 mqd->cp_hqd_pq_rptr = 0; 6593 mqd->cp_hqd_pq_wptr_lo = 0; 6594 mqd->cp_hqd_pq_wptr_hi = 0; 6595 6596 /* set the pointer to the MQD */ 6597 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6598 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6599 6600 /* set MQD vmid to 0 */ 6601 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6602 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6603 mqd->cp_mqd_control = tmp; 6604 6605 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6606 hqd_gpu_addr = ring->gpu_addr >> 8; 6607 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6608 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6609 6610 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6611 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6612 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6613 (order_base_2(ring->ring_size / 4) - 1)); 6614 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6615 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6616 #ifdef __BIG_ENDIAN 6617 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6618 #endif 6619 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6620 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6621 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6622 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6623 mqd->cp_hqd_pq_control = tmp; 6624 6625 /* set the wb address whether it's enabled or not */ 6626 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6627 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6628 mqd->cp_hqd_pq_rptr_report_addr_hi = 6629 upper_32_bits(wb_gpu_addr) & 0xffff; 6630 6631 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6632 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6633 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6634 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6635 6636 tmp = 0; 6637 /* enable the doorbell if requested */ 6638 if (ring->use_doorbell) { 6639 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6640 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6641 DOORBELL_OFFSET, ring->doorbell_index); 6642 6643 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6644 DOORBELL_EN, 1); 6645 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6646 DOORBELL_SOURCE, 0); 6647 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6648 DOORBELL_HIT, 0); 6649 } 6650 6651 mqd->cp_hqd_pq_doorbell_control = tmp; 6652 6653 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6654 ring->wptr = 0; 6655 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6656 6657 /* set the vmid for the queue */ 6658 mqd->cp_hqd_vmid = 0; 6659 6660 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6661 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6662 mqd->cp_hqd_persistent_state = tmp; 6663 6664 /* set MIN_IB_AVAIL_SIZE */ 6665 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6666 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6667 mqd->cp_hqd_ib_control = tmp; 6668 6669 /* set static priority for a compute queue/ring */ 6670 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6671 6672 /* map_queues packet doesn't need activate the queue, 6673 * so only kiq need set this field. 6674 */ 6675 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6676 mqd->cp_hqd_active = 1; 6677 6678 return 0; 6679 } 6680 6681 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6682 { 6683 struct amdgpu_device *adev = ring->adev; 6684 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6685 int j; 6686 6687 /* inactivate the queue */ 6688 if (amdgpu_sriov_vf(adev)) 6689 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6690 6691 /* disable wptr polling */ 6692 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6693 6694 /* write the EOP addr */ 6695 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6696 mqd->cp_hqd_eop_base_addr_lo); 6697 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6698 mqd->cp_hqd_eop_base_addr_hi); 6699 6700 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6701 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6702 mqd->cp_hqd_eop_control); 6703 6704 /* enable doorbell? */ 6705 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6706 mqd->cp_hqd_pq_doorbell_control); 6707 6708 /* disable the queue if it's active */ 6709 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6710 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6711 for (j = 0; j < adev->usec_timeout; j++) { 6712 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6713 break; 6714 udelay(1); 6715 } 6716 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6717 mqd->cp_hqd_dequeue_request); 6718 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6719 mqd->cp_hqd_pq_rptr); 6720 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6721 mqd->cp_hqd_pq_wptr_lo); 6722 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6723 mqd->cp_hqd_pq_wptr_hi); 6724 } 6725 6726 /* set the pointer to the MQD */ 6727 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6728 mqd->cp_mqd_base_addr_lo); 6729 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6730 mqd->cp_mqd_base_addr_hi); 6731 6732 /* set MQD vmid to 0 */ 6733 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6734 mqd->cp_mqd_control); 6735 6736 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6737 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6738 mqd->cp_hqd_pq_base_lo); 6739 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6740 mqd->cp_hqd_pq_base_hi); 6741 6742 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6743 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6744 mqd->cp_hqd_pq_control); 6745 6746 /* set the wb address whether it's enabled or not */ 6747 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6748 mqd->cp_hqd_pq_rptr_report_addr_lo); 6749 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6750 mqd->cp_hqd_pq_rptr_report_addr_hi); 6751 6752 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6753 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6754 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6755 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6756 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6757 6758 /* enable the doorbell if requested */ 6759 if (ring->use_doorbell) { 6760 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6761 (adev->doorbell_index.kiq * 2) << 2); 6762 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6763 (adev->doorbell_index.userqueue_end * 2) << 2); 6764 } 6765 6766 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6767 mqd->cp_hqd_pq_doorbell_control); 6768 6769 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6770 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6771 mqd->cp_hqd_pq_wptr_lo); 6772 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6773 mqd->cp_hqd_pq_wptr_hi); 6774 6775 /* set the vmid for the queue */ 6776 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6777 6778 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6779 mqd->cp_hqd_persistent_state); 6780 6781 /* activate the queue */ 6782 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6783 mqd->cp_hqd_active); 6784 6785 if (ring->use_doorbell) 6786 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6787 6788 return 0; 6789 } 6790 6791 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6792 { 6793 struct amdgpu_device *adev = ring->adev; 6794 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6795 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6796 6797 gfx_v10_0_kiq_setting(ring); 6798 6799 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6800 /* reset MQD to a clean status */ 6801 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6802 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6803 6804 /* reset ring buffer */ 6805 ring->wptr = 0; 6806 amdgpu_ring_clear_ring(ring); 6807 6808 mutex_lock(&adev->srbm_mutex); 6809 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6810 gfx_v10_0_kiq_init_register(ring); 6811 nv_grbm_select(adev, 0, 0, 0, 0); 6812 mutex_unlock(&adev->srbm_mutex); 6813 } else { 6814 memset((void *)mqd, 0, sizeof(*mqd)); 6815 mutex_lock(&adev->srbm_mutex); 6816 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6817 gfx_v10_0_compute_mqd_init(ring); 6818 gfx_v10_0_kiq_init_register(ring); 6819 nv_grbm_select(adev, 0, 0, 0, 0); 6820 mutex_unlock(&adev->srbm_mutex); 6821 6822 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6823 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6824 } 6825 6826 return 0; 6827 } 6828 6829 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6830 { 6831 struct amdgpu_device *adev = ring->adev; 6832 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6833 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6834 6835 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6836 memset((void *)mqd, 0, sizeof(*mqd)); 6837 mutex_lock(&adev->srbm_mutex); 6838 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6839 gfx_v10_0_compute_mqd_init(ring); 6840 nv_grbm_select(adev, 0, 0, 0, 0); 6841 mutex_unlock(&adev->srbm_mutex); 6842 6843 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6844 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6845 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6846 /* reset MQD to a clean status */ 6847 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6848 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6849 6850 /* reset ring buffer */ 6851 ring->wptr = 0; 6852 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 6853 amdgpu_ring_clear_ring(ring); 6854 } else { 6855 amdgpu_ring_clear_ring(ring); 6856 } 6857 6858 return 0; 6859 } 6860 6861 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6862 { 6863 struct amdgpu_ring *ring; 6864 int r; 6865 6866 ring = &adev->gfx.kiq.ring; 6867 6868 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6869 if (unlikely(r != 0)) 6870 return r; 6871 6872 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6873 if (unlikely(r != 0)) 6874 return r; 6875 6876 gfx_v10_0_kiq_init_queue(ring); 6877 amdgpu_bo_kunmap(ring->mqd_obj); 6878 ring->mqd_ptr = NULL; 6879 amdgpu_bo_unreserve(ring->mqd_obj); 6880 ring->sched.ready = true; 6881 return 0; 6882 } 6883 6884 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6885 { 6886 struct amdgpu_ring *ring = NULL; 6887 int r = 0, i; 6888 6889 gfx_v10_0_cp_compute_enable(adev, true); 6890 6891 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6892 ring = &adev->gfx.compute_ring[i]; 6893 6894 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6895 if (unlikely(r != 0)) 6896 goto done; 6897 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6898 if (!r) { 6899 r = gfx_v10_0_kcq_init_queue(ring); 6900 amdgpu_bo_kunmap(ring->mqd_obj); 6901 ring->mqd_ptr = NULL; 6902 } 6903 amdgpu_bo_unreserve(ring->mqd_obj); 6904 if (r) 6905 goto done; 6906 } 6907 6908 r = amdgpu_gfx_enable_kcq(adev); 6909 done: 6910 return r; 6911 } 6912 6913 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6914 { 6915 int r, i; 6916 struct amdgpu_ring *ring; 6917 6918 if (!(adev->flags & AMD_IS_APU)) 6919 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6920 6921 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6922 /* legacy firmware loading */ 6923 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6924 if (r) 6925 return r; 6926 6927 r = gfx_v10_0_cp_compute_load_microcode(adev); 6928 if (r) 6929 return r; 6930 } 6931 6932 r = gfx_v10_0_kiq_resume(adev); 6933 if (r) 6934 return r; 6935 6936 r = gfx_v10_0_kcq_resume(adev); 6937 if (r) 6938 return r; 6939 6940 if (!amdgpu_async_gfx_ring) { 6941 r = gfx_v10_0_cp_gfx_resume(adev); 6942 if (r) 6943 return r; 6944 } else { 6945 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6946 if (r) 6947 return r; 6948 } 6949 6950 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6951 ring = &adev->gfx.gfx_ring[i]; 6952 r = amdgpu_ring_test_helper(ring); 6953 if (r) 6954 return r; 6955 } 6956 6957 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6958 ring = &adev->gfx.compute_ring[i]; 6959 r = amdgpu_ring_test_helper(ring); 6960 if (r) 6961 return r; 6962 } 6963 6964 return 0; 6965 } 6966 6967 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6968 { 6969 gfx_v10_0_cp_gfx_enable(adev, enable); 6970 gfx_v10_0_cp_compute_enable(adev, enable); 6971 } 6972 6973 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6974 { 6975 uint32_t data, pattern = 0xDEADBEEF; 6976 6977 /* check if mmVGT_ESGS_RING_SIZE_UMD 6978 * has been remapped to mmVGT_ESGS_RING_SIZE */ 6979 switch (adev->asic_type) { 6980 case CHIP_SIENNA_CICHLID: 6981 case CHIP_NAVY_FLOUNDER: 6982 case CHIP_DIMGREY_CAVEFISH: 6983 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6984 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6985 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6986 6987 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6988 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 6989 return true; 6990 } else { 6991 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6992 return false; 6993 } 6994 break; 6995 case CHIP_VANGOGH: 6996 return true; 6997 default: 6998 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6999 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7000 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7001 7002 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7003 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7004 return true; 7005 } else { 7006 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7007 return false; 7008 } 7009 break; 7010 } 7011 } 7012 7013 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7014 { 7015 uint32_t data; 7016 7017 /* initialize cam_index to 0 7018 * index will auto-inc after each data writting */ 7019 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7020 7021 switch (adev->asic_type) { 7022 case CHIP_SIENNA_CICHLID: 7023 case CHIP_NAVY_FLOUNDER: 7024 case CHIP_VANGOGH: 7025 case CHIP_DIMGREY_CAVEFISH: 7026 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7027 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7028 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7029 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7030 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7031 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7032 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7033 7034 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7035 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7036 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7037 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7038 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7039 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7040 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7041 7042 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7043 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7044 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7045 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7046 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7047 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7048 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7049 7050 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7051 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7052 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7053 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7054 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7055 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7056 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7057 7058 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7059 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7060 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7061 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7062 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7063 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7064 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7065 7066 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7067 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7068 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7069 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7070 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7071 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7072 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7073 7074 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7075 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7076 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7077 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7078 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7079 break; 7080 default: 7081 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7082 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7083 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7084 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7085 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7086 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7087 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7088 7089 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7090 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7091 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7092 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7093 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7094 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7095 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7096 7097 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7098 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7099 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7100 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7101 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7102 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7103 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7104 7105 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7106 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7107 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7108 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7109 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7110 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7111 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7112 7113 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7114 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7115 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7116 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7117 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7118 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7119 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7120 7121 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7122 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7123 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7124 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7125 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7126 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7127 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7128 7129 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7130 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7131 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7132 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7133 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7134 break; 7135 } 7136 7137 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7138 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7139 } 7140 7141 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7142 { 7143 uint32_t data; 7144 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7145 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7146 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7147 7148 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7149 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7150 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7151 } 7152 7153 static int gfx_v10_0_hw_init(void *handle) 7154 { 7155 int r; 7156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7157 7158 if (!amdgpu_emu_mode) 7159 gfx_v10_0_init_golden_registers(adev); 7160 7161 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7162 /** 7163 * For gfx 10, rlc firmware loading relies on smu firmware is 7164 * loaded firstly, so in direct type, it has to load smc ucode 7165 * here before rlc. 7166 */ 7167 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) { 7168 r = smu_load_microcode(&adev->smu); 7169 if (r) 7170 return r; 7171 7172 r = smu_check_fw_status(&adev->smu); 7173 if (r) { 7174 pr_err("SMC firmware status is not correct\n"); 7175 return r; 7176 } 7177 } 7178 gfx_v10_0_disable_gpa_mode(adev); 7179 } 7180 7181 /* if GRBM CAM not remapped, set up the remapping */ 7182 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7183 gfx_v10_0_setup_grbm_cam_remapping(adev); 7184 7185 gfx_v10_0_constants_init(adev); 7186 7187 r = gfx_v10_0_rlc_resume(adev); 7188 if (r) 7189 return r; 7190 7191 /* 7192 * init golden registers and rlc resume may override some registers, 7193 * reconfig them here 7194 */ 7195 gfx_v10_0_tcp_harvest(adev); 7196 7197 r = gfx_v10_0_cp_resume(adev); 7198 if (r) 7199 return r; 7200 7201 if (adev->asic_type == CHIP_SIENNA_CICHLID) 7202 gfx_v10_3_program_pbb_mode(adev); 7203 7204 return r; 7205 } 7206 7207 #ifndef BRING_UP_DEBUG 7208 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7209 { 7210 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7211 struct amdgpu_ring *kiq_ring = &kiq->ring; 7212 int i; 7213 7214 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7215 return -EINVAL; 7216 7217 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7218 adev->gfx.num_gfx_rings)) 7219 return -ENOMEM; 7220 7221 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7222 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7223 PREEMPT_QUEUES, 0, 0); 7224 7225 return amdgpu_ring_test_helper(kiq_ring); 7226 } 7227 #endif 7228 7229 static int gfx_v10_0_hw_fini(void *handle) 7230 { 7231 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7232 int r; 7233 uint32_t tmp; 7234 7235 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7236 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7237 7238 if (!adev->in_pci_err_recovery) { 7239 #ifndef BRING_UP_DEBUG 7240 if (amdgpu_async_gfx_ring) { 7241 r = gfx_v10_0_kiq_disable_kgq(adev); 7242 if (r) 7243 DRM_ERROR("KGQ disable failed\n"); 7244 } 7245 #endif 7246 if (amdgpu_gfx_disable_kcq(adev)) 7247 DRM_ERROR("KCQ disable failed\n"); 7248 } 7249 7250 if (amdgpu_sriov_vf(adev)) { 7251 gfx_v10_0_cp_gfx_enable(adev, false); 7252 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7253 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7254 tmp &= 0xffffff00; 7255 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7256 7257 return 0; 7258 } 7259 gfx_v10_0_cp_enable(adev, false); 7260 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7261 7262 return 0; 7263 } 7264 7265 static int gfx_v10_0_suspend(void *handle) 7266 { 7267 return gfx_v10_0_hw_fini(handle); 7268 } 7269 7270 static int gfx_v10_0_resume(void *handle) 7271 { 7272 return gfx_v10_0_hw_init(handle); 7273 } 7274 7275 static bool gfx_v10_0_is_idle(void *handle) 7276 { 7277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7278 7279 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7280 GRBM_STATUS, GUI_ACTIVE)) 7281 return false; 7282 else 7283 return true; 7284 } 7285 7286 static int gfx_v10_0_wait_for_idle(void *handle) 7287 { 7288 unsigned i; 7289 u32 tmp; 7290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7291 7292 for (i = 0; i < adev->usec_timeout; i++) { 7293 /* read MC_STATUS */ 7294 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7295 GRBM_STATUS__GUI_ACTIVE_MASK; 7296 7297 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7298 return 0; 7299 udelay(1); 7300 } 7301 return -ETIMEDOUT; 7302 } 7303 7304 static int gfx_v10_0_soft_reset(void *handle) 7305 { 7306 u32 grbm_soft_reset = 0; 7307 u32 tmp; 7308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7309 7310 /* GRBM_STATUS */ 7311 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7312 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7313 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7314 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7315 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7316 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7317 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7318 GRBM_SOFT_RESET, SOFT_RESET_CP, 7319 1); 7320 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7321 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7322 1); 7323 } 7324 7325 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7326 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7327 GRBM_SOFT_RESET, SOFT_RESET_CP, 7328 1); 7329 } 7330 7331 /* GRBM_STATUS2 */ 7332 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7333 switch (adev->asic_type) { 7334 case CHIP_SIENNA_CICHLID: 7335 case CHIP_NAVY_FLOUNDER: 7336 case CHIP_VANGOGH: 7337 case CHIP_DIMGREY_CAVEFISH: 7338 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7339 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7340 GRBM_SOFT_RESET, 7341 SOFT_RESET_RLC, 7342 1); 7343 break; 7344 default: 7345 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7346 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7347 GRBM_SOFT_RESET, 7348 SOFT_RESET_RLC, 7349 1); 7350 break; 7351 } 7352 7353 if (grbm_soft_reset) { 7354 /* stop the rlc */ 7355 gfx_v10_0_rlc_stop(adev); 7356 7357 /* Disable GFX parsing/prefetching */ 7358 gfx_v10_0_cp_gfx_enable(adev, false); 7359 7360 /* Disable MEC parsing/prefetching */ 7361 gfx_v10_0_cp_compute_enable(adev, false); 7362 7363 if (grbm_soft_reset) { 7364 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7365 tmp |= grbm_soft_reset; 7366 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7367 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7368 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7369 7370 udelay(50); 7371 7372 tmp &= ~grbm_soft_reset; 7373 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7374 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7375 } 7376 7377 /* Wait a little for things to settle down */ 7378 udelay(50); 7379 } 7380 return 0; 7381 } 7382 7383 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7384 { 7385 uint64_t clock; 7386 7387 amdgpu_gfx_off_ctrl(adev, false); 7388 mutex_lock(&adev->gfx.gpu_clock_mutex); 7389 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 7390 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 7391 mutex_unlock(&adev->gfx.gpu_clock_mutex); 7392 amdgpu_gfx_off_ctrl(adev, true); 7393 return clock; 7394 } 7395 7396 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7397 uint32_t vmid, 7398 uint32_t gds_base, uint32_t gds_size, 7399 uint32_t gws_base, uint32_t gws_size, 7400 uint32_t oa_base, uint32_t oa_size) 7401 { 7402 struct amdgpu_device *adev = ring->adev; 7403 7404 /* GDS Base */ 7405 gfx_v10_0_write_data_to_reg(ring, 0, false, 7406 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7407 gds_base); 7408 7409 /* GDS Size */ 7410 gfx_v10_0_write_data_to_reg(ring, 0, false, 7411 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7412 gds_size); 7413 7414 /* GWS */ 7415 gfx_v10_0_write_data_to_reg(ring, 0, false, 7416 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7417 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7418 7419 /* OA */ 7420 gfx_v10_0_write_data_to_reg(ring, 0, false, 7421 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7422 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7423 } 7424 7425 static int gfx_v10_0_early_init(void *handle) 7426 { 7427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7428 7429 switch (adev->asic_type) { 7430 case CHIP_NAVI10: 7431 case CHIP_NAVI14: 7432 case CHIP_NAVI12: 7433 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7434 break; 7435 case CHIP_SIENNA_CICHLID: 7436 case CHIP_NAVY_FLOUNDER: 7437 case CHIP_VANGOGH: 7438 case CHIP_DIMGREY_CAVEFISH: 7439 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7440 break; 7441 default: 7442 break; 7443 } 7444 7445 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7446 AMDGPU_MAX_COMPUTE_RINGS); 7447 7448 gfx_v10_0_set_kiq_pm4_funcs(adev); 7449 gfx_v10_0_set_ring_funcs(adev); 7450 gfx_v10_0_set_irq_funcs(adev); 7451 gfx_v10_0_set_gds_init(adev); 7452 gfx_v10_0_set_rlc_funcs(adev); 7453 7454 return 0; 7455 } 7456 7457 static int gfx_v10_0_late_init(void *handle) 7458 { 7459 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7460 int r; 7461 7462 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7463 if (r) 7464 return r; 7465 7466 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7467 if (r) 7468 return r; 7469 7470 return 0; 7471 } 7472 7473 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7474 { 7475 uint32_t rlc_cntl; 7476 7477 /* if RLC is not enabled, do nothing */ 7478 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7479 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7480 } 7481 7482 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7483 { 7484 uint32_t data; 7485 unsigned i; 7486 7487 data = RLC_SAFE_MODE__CMD_MASK; 7488 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7489 7490 switch (adev->asic_type) { 7491 case CHIP_SIENNA_CICHLID: 7492 case CHIP_NAVY_FLOUNDER: 7493 case CHIP_VANGOGH: 7494 case CHIP_DIMGREY_CAVEFISH: 7495 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7496 7497 /* wait for RLC_SAFE_MODE */ 7498 for (i = 0; i < adev->usec_timeout; i++) { 7499 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7500 RLC_SAFE_MODE, CMD)) 7501 break; 7502 udelay(1); 7503 } 7504 break; 7505 default: 7506 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7507 7508 /* wait for RLC_SAFE_MODE */ 7509 for (i = 0; i < adev->usec_timeout; i++) { 7510 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7511 RLC_SAFE_MODE, CMD)) 7512 break; 7513 udelay(1); 7514 } 7515 break; 7516 } 7517 } 7518 7519 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7520 { 7521 uint32_t data; 7522 7523 data = RLC_SAFE_MODE__CMD_MASK; 7524 switch (adev->asic_type) { 7525 case CHIP_SIENNA_CICHLID: 7526 case CHIP_NAVY_FLOUNDER: 7527 case CHIP_VANGOGH: 7528 case CHIP_DIMGREY_CAVEFISH: 7529 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7530 break; 7531 default: 7532 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7533 break; 7534 } 7535 } 7536 7537 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7538 bool enable) 7539 { 7540 uint32_t data, def; 7541 7542 /* It is disabled by HW by default */ 7543 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7544 /* 0 - Disable some blocks' MGCG */ 7545 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7546 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7547 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7548 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7549 7550 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7551 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7552 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7553 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7554 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7555 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7556 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7557 7558 if (def != data) 7559 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7560 7561 /* MGLS is a global flag to control all MGLS in GFX */ 7562 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7563 /* 2 - RLC memory Light sleep */ 7564 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7565 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7566 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7567 if (def != data) 7568 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7569 } 7570 /* 3 - CP memory Light sleep */ 7571 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7572 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7573 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7574 if (def != data) 7575 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7576 } 7577 } 7578 } else { 7579 /* 1 - MGCG_OVERRIDE */ 7580 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7581 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7582 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7583 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7584 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 7585 if (def != data) 7586 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7587 7588 /* 2 - disable MGLS in CP */ 7589 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7590 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7591 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7592 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7593 } 7594 7595 /* 3 - disable MGLS in RLC */ 7596 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7597 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7598 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7599 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7600 } 7601 7602 } 7603 } 7604 7605 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7606 bool enable) 7607 { 7608 uint32_t data, def; 7609 7610 /* Enable 3D CGCG/CGLS */ 7611 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 7612 /* write cmd to clear cgcg/cgls ov */ 7613 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7614 /* unset CGCG override */ 7615 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7616 /* update CGCG and CGLS override bits */ 7617 if (def != data) 7618 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7619 /* enable 3Dcgcg FSM(0x0000363f) */ 7620 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7621 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7622 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7623 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7624 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7625 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7626 if (def != data) 7627 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7628 7629 /* set IDLE_POLL_COUNT(0x00900100) */ 7630 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7631 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7632 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7633 if (def != data) 7634 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7635 } else { 7636 /* Disable CGCG/CGLS */ 7637 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7638 /* disable cgcg, cgls should be disabled */ 7639 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 7640 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 7641 /* disable cgcg and cgls in FSM */ 7642 if (def != data) 7643 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7644 } 7645 } 7646 7647 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7648 bool enable) 7649 { 7650 uint32_t def, data; 7651 7652 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 7653 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7654 /* unset CGCG override */ 7655 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7656 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7657 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7658 else 7659 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7660 /* update CGCG and CGLS override bits */ 7661 if (def != data) 7662 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7663 7664 /* enable cgcg FSM(0x0000363F) */ 7665 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7666 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7667 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7668 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7669 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7670 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7671 if (def != data) 7672 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7673 7674 /* set IDLE_POLL_COUNT(0x00900100) */ 7675 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7676 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7677 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7678 if (def != data) 7679 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7680 } else { 7681 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7682 /* reset CGCG/CGLS bits */ 7683 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 7684 /* disable cgcg and cgls in FSM */ 7685 if (def != data) 7686 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7687 } 7688 } 7689 7690 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7691 bool enable) 7692 { 7693 uint32_t def, data; 7694 7695 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) { 7696 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7697 /* unset FGCG override */ 7698 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7699 /* update FGCG override bits */ 7700 if (def != data) 7701 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7702 7703 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7704 /* unset RLC SRAM CLK GATER override */ 7705 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7706 /* update RLC SRAM CLK GATER override bits */ 7707 if (def != data) 7708 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7709 } else { 7710 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7711 /* reset FGCG bits */ 7712 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7713 /* disable FGCG*/ 7714 if (def != data) 7715 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7716 7717 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7718 /* reset RLC SRAM CLK GATER bits */ 7719 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7720 /* disable RLC SRAM CLK*/ 7721 if (def != data) 7722 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7723 } 7724 } 7725 7726 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7727 bool enable) 7728 { 7729 amdgpu_gfx_rlc_enter_safe_mode(adev); 7730 7731 if (enable) { 7732 /* enable FGCG firstly*/ 7733 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7734 /* CGCG/CGLS should be enabled after MGCG/MGLS 7735 * === MGCG + MGLS === 7736 */ 7737 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7738 /* === CGCG /CGLS for GFX 3D Only === */ 7739 gfx_v10_0_update_3d_clock_gating(adev, enable); 7740 /* === CGCG + CGLS === */ 7741 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7742 } else { 7743 /* CGCG/CGLS should be disabled before MGCG/MGLS 7744 * === CGCG + CGLS === 7745 */ 7746 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7747 /* === CGCG /CGLS for GFX 3D Only === */ 7748 gfx_v10_0_update_3d_clock_gating(adev, enable); 7749 /* === MGCG + MGLS === */ 7750 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7751 /* disable fgcg at last*/ 7752 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7753 } 7754 7755 if (adev->cg_flags & 7756 (AMD_CG_SUPPORT_GFX_MGCG | 7757 AMD_CG_SUPPORT_GFX_CGLS | 7758 AMD_CG_SUPPORT_GFX_CGCG | 7759 AMD_CG_SUPPORT_GFX_3D_CGCG | 7760 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7761 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7762 7763 amdgpu_gfx_rlc_exit_safe_mode(adev); 7764 7765 return 0; 7766 } 7767 7768 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 7769 { 7770 u32 reg, data; 7771 7772 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7773 if (amdgpu_sriov_is_pp_one_vf(adev)) 7774 data = RREG32_NO_KIQ(reg); 7775 else 7776 data = RREG32(reg); 7777 7778 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7779 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7780 7781 if (amdgpu_sriov_is_pp_one_vf(adev)) 7782 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7783 else 7784 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7785 } 7786 7787 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7788 uint32_t offset, 7789 struct soc15_reg_rlcg *entries, int arr_size) 7790 { 7791 int i; 7792 uint32_t reg; 7793 7794 if (!entries) 7795 return false; 7796 7797 for (i = 0; i < arr_size; i++) { 7798 const struct soc15_reg_rlcg *entry; 7799 7800 entry = &entries[i]; 7801 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7802 if (offset == reg) 7803 return true; 7804 } 7805 7806 return false; 7807 } 7808 7809 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7810 { 7811 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7812 } 7813 7814 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7815 { 7816 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7817 7818 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7819 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7820 else 7821 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7822 7823 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7824 } 7825 7826 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7827 { 7828 amdgpu_gfx_rlc_enter_safe_mode(adev); 7829 7830 gfx_v10_cntl_power_gating(adev, enable); 7831 7832 amdgpu_gfx_rlc_exit_safe_mode(adev); 7833 } 7834 7835 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 7836 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7837 .set_safe_mode = gfx_v10_0_set_safe_mode, 7838 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7839 .init = gfx_v10_0_rlc_init, 7840 .get_csb_size = gfx_v10_0_get_csb_size, 7841 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7842 .resume = gfx_v10_0_rlc_resume, 7843 .stop = gfx_v10_0_rlc_stop, 7844 .reset = gfx_v10_0_rlc_reset, 7845 .start = gfx_v10_0_rlc_start, 7846 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7847 }; 7848 7849 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 7850 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7851 .set_safe_mode = gfx_v10_0_set_safe_mode, 7852 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7853 .init = gfx_v10_0_rlc_init, 7854 .get_csb_size = gfx_v10_0_get_csb_size, 7855 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7856 .resume = gfx_v10_0_rlc_resume, 7857 .stop = gfx_v10_0_rlc_stop, 7858 .reset = gfx_v10_0_rlc_reset, 7859 .start = gfx_v10_0_rlc_start, 7860 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7861 .rlcg_wreg = gfx_v10_rlcg_wreg, 7862 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 7863 }; 7864 7865 static int gfx_v10_0_set_powergating_state(void *handle, 7866 enum amd_powergating_state state) 7867 { 7868 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7869 bool enable = (state == AMD_PG_STATE_GATE); 7870 7871 if (amdgpu_sriov_vf(adev)) 7872 return 0; 7873 7874 switch (adev->asic_type) { 7875 case CHIP_NAVI10: 7876 case CHIP_NAVI14: 7877 case CHIP_NAVI12: 7878 case CHIP_SIENNA_CICHLID: 7879 case CHIP_NAVY_FLOUNDER: 7880 case CHIP_DIMGREY_CAVEFISH: 7881 amdgpu_gfx_off_ctrl(adev, enable); 7882 break; 7883 case CHIP_VANGOGH: 7884 gfx_v10_cntl_pg(adev, enable); 7885 break; 7886 default: 7887 break; 7888 } 7889 return 0; 7890 } 7891 7892 static int gfx_v10_0_set_clockgating_state(void *handle, 7893 enum amd_clockgating_state state) 7894 { 7895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7896 7897 if (amdgpu_sriov_vf(adev)) 7898 return 0; 7899 7900 switch (adev->asic_type) { 7901 case CHIP_NAVI10: 7902 case CHIP_NAVI14: 7903 case CHIP_NAVI12: 7904 case CHIP_SIENNA_CICHLID: 7905 case CHIP_NAVY_FLOUNDER: 7906 case CHIP_VANGOGH: 7907 case CHIP_DIMGREY_CAVEFISH: 7908 gfx_v10_0_update_gfx_clock_gating(adev, 7909 state == AMD_CG_STATE_GATE); 7910 break; 7911 default: 7912 break; 7913 } 7914 return 0; 7915 } 7916 7917 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 7918 { 7919 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7920 int data; 7921 7922 /* AMD_CG_SUPPORT_GFX_FGCG */ 7923 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7924 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 7925 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 7926 7927 /* AMD_CG_SUPPORT_GFX_MGCG */ 7928 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7929 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 7930 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 7931 7932 /* AMD_CG_SUPPORT_GFX_CGCG */ 7933 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 7934 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 7935 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 7936 7937 /* AMD_CG_SUPPORT_GFX_CGLS */ 7938 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 7939 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 7940 7941 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 7942 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 7943 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 7944 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 7945 7946 /* AMD_CG_SUPPORT_GFX_CP_LS */ 7947 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 7948 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 7949 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 7950 7951 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 7952 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 7953 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 7954 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 7955 7956 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 7957 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 7958 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 7959 } 7960 7961 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 7962 { 7963 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 7964 } 7965 7966 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 7967 { 7968 struct amdgpu_device *adev = ring->adev; 7969 u64 wptr; 7970 7971 /* XXX check if swapping is necessary on BE */ 7972 if (ring->use_doorbell) { 7973 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 7974 } else { 7975 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 7976 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 7977 } 7978 7979 return wptr; 7980 } 7981 7982 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 7983 { 7984 struct amdgpu_device *adev = ring->adev; 7985 7986 if (ring->use_doorbell) { 7987 /* XXX check if swapping is necessary on BE */ 7988 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 7989 WDOORBELL64(ring->doorbell_index, ring->wptr); 7990 } else { 7991 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 7992 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 7993 } 7994 } 7995 7996 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 7997 { 7998 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 7999 } 8000 8001 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8002 { 8003 u64 wptr; 8004 8005 /* XXX check if swapping is necessary on BE */ 8006 if (ring->use_doorbell) 8007 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 8008 else 8009 BUG(); 8010 return wptr; 8011 } 8012 8013 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8014 { 8015 struct amdgpu_device *adev = ring->adev; 8016 8017 /* XXX check if swapping is necessary on BE */ 8018 if (ring->use_doorbell) { 8019 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8020 WDOORBELL64(ring->doorbell_index, ring->wptr); 8021 } else { 8022 BUG(); /* only DOORBELL method supported on gfx10 now */ 8023 } 8024 } 8025 8026 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8027 { 8028 struct amdgpu_device *adev = ring->adev; 8029 u32 ref_and_mask, reg_mem_engine; 8030 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8031 8032 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8033 switch (ring->me) { 8034 case 1: 8035 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8036 break; 8037 case 2: 8038 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8039 break; 8040 default: 8041 return; 8042 } 8043 reg_mem_engine = 0; 8044 } else { 8045 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8046 reg_mem_engine = 1; /* pfp */ 8047 } 8048 8049 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8050 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8051 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8052 ref_and_mask, ref_and_mask, 0x20); 8053 } 8054 8055 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8056 struct amdgpu_job *job, 8057 struct amdgpu_ib *ib, 8058 uint32_t flags) 8059 { 8060 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8061 u32 header, control = 0; 8062 8063 if (ib->flags & AMDGPU_IB_FLAG_CE) 8064 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8065 else 8066 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8067 8068 control |= ib->length_dw | (vmid << 24); 8069 8070 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8071 control |= INDIRECT_BUFFER_PRE_ENB(1); 8072 8073 if (flags & AMDGPU_IB_PREEMPTED) 8074 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8075 8076 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8077 gfx_v10_0_ring_emit_de_meta(ring, 8078 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8079 } 8080 8081 amdgpu_ring_write(ring, header); 8082 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8083 amdgpu_ring_write(ring, 8084 #ifdef __BIG_ENDIAN 8085 (2 << 0) | 8086 #endif 8087 lower_32_bits(ib->gpu_addr)); 8088 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8089 amdgpu_ring_write(ring, control); 8090 } 8091 8092 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8093 struct amdgpu_job *job, 8094 struct amdgpu_ib *ib, 8095 uint32_t flags) 8096 { 8097 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8098 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8099 8100 /* Currently, there is a high possibility to get wave ID mismatch 8101 * between ME and GDS, leading to a hw deadlock, because ME generates 8102 * different wave IDs than the GDS expects. This situation happens 8103 * randomly when at least 5 compute pipes use GDS ordered append. 8104 * The wave IDs generated by ME are also wrong after suspend/resume. 8105 * Those are probably bugs somewhere else in the kernel driver. 8106 * 8107 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8108 * GDS to 0 for this ring (me/pipe). 8109 */ 8110 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8111 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8112 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8113 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8114 } 8115 8116 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8117 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8118 amdgpu_ring_write(ring, 8119 #ifdef __BIG_ENDIAN 8120 (2 << 0) | 8121 #endif 8122 lower_32_bits(ib->gpu_addr)); 8123 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8124 amdgpu_ring_write(ring, control); 8125 } 8126 8127 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8128 u64 seq, unsigned flags) 8129 { 8130 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8131 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8132 8133 /* RELEASE_MEM - flush caches, send int */ 8134 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8135 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8136 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8137 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8138 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8139 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8140 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8141 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8142 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8143 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8144 8145 /* 8146 * the address should be Qword aligned if 64bit write, Dword 8147 * aligned if only send 32bit data low (discard data high) 8148 */ 8149 if (write64bit) 8150 BUG_ON(addr & 0x7); 8151 else 8152 BUG_ON(addr & 0x3); 8153 amdgpu_ring_write(ring, lower_32_bits(addr)); 8154 amdgpu_ring_write(ring, upper_32_bits(addr)); 8155 amdgpu_ring_write(ring, lower_32_bits(seq)); 8156 amdgpu_ring_write(ring, upper_32_bits(seq)); 8157 amdgpu_ring_write(ring, 0); 8158 } 8159 8160 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8161 { 8162 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8163 uint32_t seq = ring->fence_drv.sync_seq; 8164 uint64_t addr = ring->fence_drv.gpu_addr; 8165 8166 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8167 upper_32_bits(addr), seq, 0xffffffff, 4); 8168 } 8169 8170 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8171 unsigned vmid, uint64_t pd_addr) 8172 { 8173 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8174 8175 /* compute doesn't have PFP */ 8176 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8177 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8178 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8179 amdgpu_ring_write(ring, 0x0); 8180 } 8181 } 8182 8183 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8184 u64 seq, unsigned int flags) 8185 { 8186 struct amdgpu_device *adev = ring->adev; 8187 8188 /* we only allocate 32bit for each seq wb address */ 8189 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8190 8191 /* write fence seq to the "addr" */ 8192 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8193 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8194 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8195 amdgpu_ring_write(ring, lower_32_bits(addr)); 8196 amdgpu_ring_write(ring, upper_32_bits(addr)); 8197 amdgpu_ring_write(ring, lower_32_bits(seq)); 8198 8199 if (flags & AMDGPU_FENCE_FLAG_INT) { 8200 /* set register to trigger INT */ 8201 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8202 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8203 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8204 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8205 amdgpu_ring_write(ring, 0); 8206 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8207 } 8208 } 8209 8210 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8211 { 8212 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8213 amdgpu_ring_write(ring, 0); 8214 } 8215 8216 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8217 uint32_t flags) 8218 { 8219 uint32_t dw2 = 0; 8220 8221 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8222 gfx_v10_0_ring_emit_ce_meta(ring, 8223 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8224 8225 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8226 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8227 /* set load_global_config & load_global_uconfig */ 8228 dw2 |= 0x8001; 8229 /* set load_cs_sh_regs */ 8230 dw2 |= 0x01000000; 8231 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8232 dw2 |= 0x10002; 8233 8234 /* set load_ce_ram if preamble presented */ 8235 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8236 dw2 |= 0x10000000; 8237 } else { 8238 /* still load_ce_ram if this is the first time preamble presented 8239 * although there is no context switch happens. 8240 */ 8241 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8242 dw2 |= 0x10000000; 8243 } 8244 8245 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8246 amdgpu_ring_write(ring, dw2); 8247 amdgpu_ring_write(ring, 0); 8248 } 8249 8250 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8251 { 8252 unsigned ret; 8253 8254 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8255 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8256 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8257 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8258 ret = ring->wptr & ring->buf_mask; 8259 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8260 8261 return ret; 8262 } 8263 8264 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8265 { 8266 unsigned cur; 8267 BUG_ON(offset > ring->buf_mask); 8268 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8269 8270 cur = (ring->wptr - 1) & ring->buf_mask; 8271 if (likely(cur > offset)) 8272 ring->ring[offset] = cur - offset; 8273 else 8274 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8275 } 8276 8277 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8278 { 8279 int i, r = 0; 8280 struct amdgpu_device *adev = ring->adev; 8281 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8282 struct amdgpu_ring *kiq_ring = &kiq->ring; 8283 unsigned long flags; 8284 8285 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8286 return -EINVAL; 8287 8288 spin_lock_irqsave(&kiq->ring_lock, flags); 8289 8290 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8291 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8292 return -ENOMEM; 8293 } 8294 8295 /* assert preemption condition */ 8296 amdgpu_ring_set_preempt_cond_exec(ring, false); 8297 8298 /* assert IB preemption, emit the trailing fence */ 8299 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8300 ring->trail_fence_gpu_addr, 8301 ++ring->trail_seq); 8302 amdgpu_ring_commit(kiq_ring); 8303 8304 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8305 8306 /* poll the trailing fence */ 8307 for (i = 0; i < adev->usec_timeout; i++) { 8308 if (ring->trail_seq == 8309 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8310 break; 8311 udelay(1); 8312 } 8313 8314 if (i >= adev->usec_timeout) { 8315 r = -EINVAL; 8316 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8317 } 8318 8319 /* deassert preemption condition */ 8320 amdgpu_ring_set_preempt_cond_exec(ring, true); 8321 return r; 8322 } 8323 8324 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8325 { 8326 struct amdgpu_device *adev = ring->adev; 8327 struct v10_ce_ib_state ce_payload = {0}; 8328 uint64_t csa_addr; 8329 int cnt; 8330 8331 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8332 csa_addr = amdgpu_csa_vaddr(ring->adev); 8333 8334 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8335 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8336 WRITE_DATA_DST_SEL(8) | 8337 WR_CONFIRM) | 8338 WRITE_DATA_CACHE_POLICY(0)); 8339 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8340 offsetof(struct v10_gfx_meta_data, ce_payload))); 8341 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8342 offsetof(struct v10_gfx_meta_data, ce_payload))); 8343 8344 if (resume) 8345 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8346 offsetof(struct v10_gfx_meta_data, 8347 ce_payload), 8348 sizeof(ce_payload) >> 2); 8349 else 8350 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8351 sizeof(ce_payload) >> 2); 8352 } 8353 8354 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8355 { 8356 struct amdgpu_device *adev = ring->adev; 8357 struct v10_de_ib_state de_payload = {0}; 8358 uint64_t csa_addr, gds_addr; 8359 int cnt; 8360 8361 csa_addr = amdgpu_csa_vaddr(ring->adev); 8362 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8363 PAGE_SIZE); 8364 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8365 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8366 8367 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8368 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8369 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8370 WRITE_DATA_DST_SEL(8) | 8371 WR_CONFIRM) | 8372 WRITE_DATA_CACHE_POLICY(0)); 8373 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8374 offsetof(struct v10_gfx_meta_data, de_payload))); 8375 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8376 offsetof(struct v10_gfx_meta_data, de_payload))); 8377 8378 if (resume) 8379 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8380 offsetof(struct v10_gfx_meta_data, 8381 de_payload), 8382 sizeof(de_payload) >> 2); 8383 else 8384 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8385 sizeof(de_payload) >> 2); 8386 } 8387 8388 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8389 bool secure) 8390 { 8391 uint32_t v = secure ? FRAME_TMZ : 0; 8392 8393 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8394 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8395 } 8396 8397 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8398 uint32_t reg_val_offs) 8399 { 8400 struct amdgpu_device *adev = ring->adev; 8401 8402 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8403 amdgpu_ring_write(ring, 0 | /* src: register*/ 8404 (5 << 8) | /* dst: memory */ 8405 (1 << 20)); /* write confirm */ 8406 amdgpu_ring_write(ring, reg); 8407 amdgpu_ring_write(ring, 0); 8408 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8409 reg_val_offs * 4)); 8410 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8411 reg_val_offs * 4)); 8412 } 8413 8414 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8415 uint32_t val) 8416 { 8417 uint32_t cmd = 0; 8418 8419 switch (ring->funcs->type) { 8420 case AMDGPU_RING_TYPE_GFX: 8421 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8422 break; 8423 case AMDGPU_RING_TYPE_KIQ: 8424 cmd = (1 << 16); /* no inc addr */ 8425 break; 8426 default: 8427 cmd = WR_CONFIRM; 8428 break; 8429 } 8430 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8431 amdgpu_ring_write(ring, cmd); 8432 amdgpu_ring_write(ring, reg); 8433 amdgpu_ring_write(ring, 0); 8434 amdgpu_ring_write(ring, val); 8435 } 8436 8437 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8438 uint32_t val, uint32_t mask) 8439 { 8440 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8441 } 8442 8443 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8444 uint32_t reg0, uint32_t reg1, 8445 uint32_t ref, uint32_t mask) 8446 { 8447 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8448 struct amdgpu_device *adev = ring->adev; 8449 bool fw_version_ok = false; 8450 8451 fw_version_ok = adev->gfx.cp_fw_write_wait; 8452 8453 if (fw_version_ok) 8454 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8455 ref, mask, 0x20); 8456 else 8457 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8458 ref, mask); 8459 } 8460 8461 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8462 unsigned vmid) 8463 { 8464 struct amdgpu_device *adev = ring->adev; 8465 uint32_t value = 0; 8466 8467 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8468 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8469 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8470 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8471 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8472 } 8473 8474 static void 8475 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8476 uint32_t me, uint32_t pipe, 8477 enum amdgpu_interrupt_state state) 8478 { 8479 uint32_t cp_int_cntl, cp_int_cntl_reg; 8480 8481 if (!me) { 8482 switch (pipe) { 8483 case 0: 8484 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8485 break; 8486 case 1: 8487 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8488 break; 8489 default: 8490 DRM_DEBUG("invalid pipe %d\n", pipe); 8491 return; 8492 } 8493 } else { 8494 DRM_DEBUG("invalid me %d\n", me); 8495 return; 8496 } 8497 8498 switch (state) { 8499 case AMDGPU_IRQ_STATE_DISABLE: 8500 cp_int_cntl = RREG32(cp_int_cntl_reg); 8501 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8502 TIME_STAMP_INT_ENABLE, 0); 8503 WREG32(cp_int_cntl_reg, cp_int_cntl); 8504 break; 8505 case AMDGPU_IRQ_STATE_ENABLE: 8506 cp_int_cntl = RREG32(cp_int_cntl_reg); 8507 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8508 TIME_STAMP_INT_ENABLE, 1); 8509 WREG32(cp_int_cntl_reg, cp_int_cntl); 8510 break; 8511 default: 8512 break; 8513 } 8514 } 8515 8516 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8517 int me, int pipe, 8518 enum amdgpu_interrupt_state state) 8519 { 8520 u32 mec_int_cntl, mec_int_cntl_reg; 8521 8522 /* 8523 * amdgpu controls only the first MEC. That's why this function only 8524 * handles the setting of interrupts for this specific MEC. All other 8525 * pipes' interrupts are set by amdkfd. 8526 */ 8527 8528 if (me == 1) { 8529 switch (pipe) { 8530 case 0: 8531 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8532 break; 8533 case 1: 8534 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8535 break; 8536 case 2: 8537 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8538 break; 8539 case 3: 8540 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8541 break; 8542 default: 8543 DRM_DEBUG("invalid pipe %d\n", pipe); 8544 return; 8545 } 8546 } else { 8547 DRM_DEBUG("invalid me %d\n", me); 8548 return; 8549 } 8550 8551 switch (state) { 8552 case AMDGPU_IRQ_STATE_DISABLE: 8553 mec_int_cntl = RREG32(mec_int_cntl_reg); 8554 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8555 TIME_STAMP_INT_ENABLE, 0); 8556 WREG32(mec_int_cntl_reg, mec_int_cntl); 8557 break; 8558 case AMDGPU_IRQ_STATE_ENABLE: 8559 mec_int_cntl = RREG32(mec_int_cntl_reg); 8560 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8561 TIME_STAMP_INT_ENABLE, 1); 8562 WREG32(mec_int_cntl_reg, mec_int_cntl); 8563 break; 8564 default: 8565 break; 8566 } 8567 } 8568 8569 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8570 struct amdgpu_irq_src *src, 8571 unsigned type, 8572 enum amdgpu_interrupt_state state) 8573 { 8574 switch (type) { 8575 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8576 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8577 break; 8578 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8579 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8580 break; 8581 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8582 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8583 break; 8584 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8585 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8586 break; 8587 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8588 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8589 break; 8590 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8591 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8592 break; 8593 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8594 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8595 break; 8596 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8597 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8598 break; 8599 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8600 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8601 break; 8602 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8603 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8604 break; 8605 default: 8606 break; 8607 } 8608 return 0; 8609 } 8610 8611 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8612 struct amdgpu_irq_src *source, 8613 struct amdgpu_iv_entry *entry) 8614 { 8615 int i; 8616 u8 me_id, pipe_id, queue_id; 8617 struct amdgpu_ring *ring; 8618 8619 DRM_DEBUG("IH: CP EOP\n"); 8620 me_id = (entry->ring_id & 0x0c) >> 2; 8621 pipe_id = (entry->ring_id & 0x03) >> 0; 8622 queue_id = (entry->ring_id & 0x70) >> 4; 8623 8624 switch (me_id) { 8625 case 0: 8626 if (pipe_id == 0) 8627 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8628 else 8629 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8630 break; 8631 case 1: 8632 case 2: 8633 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8634 ring = &adev->gfx.compute_ring[i]; 8635 /* Per-queue interrupt is supported for MEC starting from VI. 8636 * The interrupt can only be enabled/disabled per pipe instead of per queue. 8637 */ 8638 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 8639 amdgpu_fence_process(ring); 8640 } 8641 break; 8642 } 8643 return 0; 8644 } 8645 8646 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8647 struct amdgpu_irq_src *source, 8648 unsigned type, 8649 enum amdgpu_interrupt_state state) 8650 { 8651 switch (state) { 8652 case AMDGPU_IRQ_STATE_DISABLE: 8653 case AMDGPU_IRQ_STATE_ENABLE: 8654 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8655 PRIV_REG_INT_ENABLE, 8656 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8657 break; 8658 default: 8659 break; 8660 } 8661 8662 return 0; 8663 } 8664 8665 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8666 struct amdgpu_irq_src *source, 8667 unsigned type, 8668 enum amdgpu_interrupt_state state) 8669 { 8670 switch (state) { 8671 case AMDGPU_IRQ_STATE_DISABLE: 8672 case AMDGPU_IRQ_STATE_ENABLE: 8673 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8674 PRIV_INSTR_INT_ENABLE, 8675 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8676 break; 8677 default: 8678 break; 8679 } 8680 8681 return 0; 8682 } 8683 8684 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8685 struct amdgpu_iv_entry *entry) 8686 { 8687 u8 me_id, pipe_id, queue_id; 8688 struct amdgpu_ring *ring; 8689 int i; 8690 8691 me_id = (entry->ring_id & 0x0c) >> 2; 8692 pipe_id = (entry->ring_id & 0x03) >> 0; 8693 queue_id = (entry->ring_id & 0x70) >> 4; 8694 8695 switch (me_id) { 8696 case 0: 8697 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 8698 ring = &adev->gfx.gfx_ring[i]; 8699 /* we only enabled 1 gfx queue per pipe for now */ 8700 if (ring->me == me_id && ring->pipe == pipe_id) 8701 drm_sched_fault(&ring->sched); 8702 } 8703 break; 8704 case 1: 8705 case 2: 8706 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8707 ring = &adev->gfx.compute_ring[i]; 8708 if (ring->me == me_id && ring->pipe == pipe_id && 8709 ring->queue == queue_id) 8710 drm_sched_fault(&ring->sched); 8711 } 8712 break; 8713 default: 8714 BUG(); 8715 } 8716 } 8717 8718 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 8719 struct amdgpu_irq_src *source, 8720 struct amdgpu_iv_entry *entry) 8721 { 8722 DRM_ERROR("Illegal register access in command stream\n"); 8723 gfx_v10_0_handle_priv_fault(adev, entry); 8724 return 0; 8725 } 8726 8727 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 8728 struct amdgpu_irq_src *source, 8729 struct amdgpu_iv_entry *entry) 8730 { 8731 DRM_ERROR("Illegal instruction in command stream\n"); 8732 gfx_v10_0_handle_priv_fault(adev, entry); 8733 return 0; 8734 } 8735 8736 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 8737 struct amdgpu_irq_src *src, 8738 unsigned int type, 8739 enum amdgpu_interrupt_state state) 8740 { 8741 uint32_t tmp, target; 8742 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8743 8744 if (ring->me == 1) 8745 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8746 else 8747 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 8748 target += ring->pipe; 8749 8750 switch (type) { 8751 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 8752 if (state == AMDGPU_IRQ_STATE_DISABLE) { 8753 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8754 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8755 GENERIC2_INT_ENABLE, 0); 8756 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8757 8758 tmp = RREG32(target); 8759 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8760 GENERIC2_INT_ENABLE, 0); 8761 WREG32(target, tmp); 8762 } else { 8763 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8764 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8765 GENERIC2_INT_ENABLE, 1); 8766 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8767 8768 tmp = RREG32(target); 8769 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8770 GENERIC2_INT_ENABLE, 1); 8771 WREG32(target, tmp); 8772 } 8773 break; 8774 default: 8775 BUG(); /* kiq only support GENERIC2_INT now */ 8776 break; 8777 } 8778 return 0; 8779 } 8780 8781 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 8782 struct amdgpu_irq_src *source, 8783 struct amdgpu_iv_entry *entry) 8784 { 8785 u8 me_id, pipe_id, queue_id; 8786 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8787 8788 me_id = (entry->ring_id & 0x0c) >> 2; 8789 pipe_id = (entry->ring_id & 0x03) >> 0; 8790 queue_id = (entry->ring_id & 0x70) >> 4; 8791 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 8792 me_id, pipe_id, queue_id); 8793 8794 amdgpu_fence_process(ring); 8795 return 0; 8796 } 8797 8798 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 8799 { 8800 const unsigned int gcr_cntl = 8801 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 8802 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 8803 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 8804 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 8805 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 8806 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 8807 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 8808 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 8809 8810 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 8811 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 8812 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 8813 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 8814 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 8815 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 8816 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 8817 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 8818 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 8819 } 8820 8821 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 8822 .name = "gfx_v10_0", 8823 .early_init = gfx_v10_0_early_init, 8824 .late_init = gfx_v10_0_late_init, 8825 .sw_init = gfx_v10_0_sw_init, 8826 .sw_fini = gfx_v10_0_sw_fini, 8827 .hw_init = gfx_v10_0_hw_init, 8828 .hw_fini = gfx_v10_0_hw_fini, 8829 .suspend = gfx_v10_0_suspend, 8830 .resume = gfx_v10_0_resume, 8831 .is_idle = gfx_v10_0_is_idle, 8832 .wait_for_idle = gfx_v10_0_wait_for_idle, 8833 .soft_reset = gfx_v10_0_soft_reset, 8834 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 8835 .set_powergating_state = gfx_v10_0_set_powergating_state, 8836 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 8837 }; 8838 8839 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 8840 .type = AMDGPU_RING_TYPE_GFX, 8841 .align_mask = 0xff, 8842 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8843 .support_64bit_ptrs = true, 8844 .vmhub = AMDGPU_GFXHUB_0, 8845 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 8846 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 8847 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 8848 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 8849 5 + /* COND_EXEC */ 8850 7 + /* PIPELINE_SYNC */ 8851 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8852 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8853 2 + /* VM_FLUSH */ 8854 8 + /* FENCE for VM_FLUSH */ 8855 20 + /* GDS switch */ 8856 4 + /* double SWITCH_BUFFER, 8857 * the first COND_EXEC jump to the place 8858 * just prior to this double SWITCH_BUFFER 8859 */ 8860 5 + /* COND_EXEC */ 8861 7 + /* HDP_flush */ 8862 4 + /* VGT_flush */ 8863 14 + /* CE_META */ 8864 31 + /* DE_META */ 8865 3 + /* CNTX_CTRL */ 8866 5 + /* HDP_INVL */ 8867 8 + 8 + /* FENCE x2 */ 8868 2 + /* SWITCH_BUFFER */ 8869 8, /* gfx_v10_0_emit_mem_sync */ 8870 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 8871 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 8872 .emit_fence = gfx_v10_0_ring_emit_fence, 8873 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8874 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8875 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8876 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8877 .test_ring = gfx_v10_0_ring_test_ring, 8878 .test_ib = gfx_v10_0_ring_test_ib, 8879 .insert_nop = amdgpu_ring_insert_nop, 8880 .pad_ib = amdgpu_ring_generic_pad_ib, 8881 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 8882 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 8883 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 8884 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 8885 .preempt_ib = gfx_v10_0_ring_preempt_ib, 8886 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 8887 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8888 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8889 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8890 .soft_recovery = gfx_v10_0_ring_soft_recovery, 8891 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8892 }; 8893 8894 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 8895 .type = AMDGPU_RING_TYPE_COMPUTE, 8896 .align_mask = 0xff, 8897 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8898 .support_64bit_ptrs = true, 8899 .vmhub = AMDGPU_GFXHUB_0, 8900 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8901 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8902 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8903 .emit_frame_size = 8904 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8905 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8906 5 + /* hdp invalidate */ 8907 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8908 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8909 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8910 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8911 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 8912 8, /* gfx_v10_0_emit_mem_sync */ 8913 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8914 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8915 .emit_fence = gfx_v10_0_ring_emit_fence, 8916 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8917 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8918 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8919 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8920 .test_ring = gfx_v10_0_ring_test_ring, 8921 .test_ib = gfx_v10_0_ring_test_ib, 8922 .insert_nop = amdgpu_ring_insert_nop, 8923 .pad_ib = amdgpu_ring_generic_pad_ib, 8924 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8925 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8926 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8927 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8928 }; 8929 8930 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 8931 .type = AMDGPU_RING_TYPE_KIQ, 8932 .align_mask = 0xff, 8933 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8934 .support_64bit_ptrs = true, 8935 .vmhub = AMDGPU_GFXHUB_0, 8936 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8937 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8938 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8939 .emit_frame_size = 8940 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8941 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8942 5 + /*hdp invalidate */ 8943 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8944 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8945 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8946 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8947 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 8948 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8949 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8950 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 8951 .test_ring = gfx_v10_0_ring_test_ring, 8952 .test_ib = gfx_v10_0_ring_test_ib, 8953 .insert_nop = amdgpu_ring_insert_nop, 8954 .pad_ib = amdgpu_ring_generic_pad_ib, 8955 .emit_rreg = gfx_v10_0_ring_emit_rreg, 8956 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8957 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8958 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8959 }; 8960 8961 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 8962 { 8963 int i; 8964 8965 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 8966 8967 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 8968 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 8969 8970 for (i = 0; i < adev->gfx.num_compute_rings; i++) 8971 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 8972 } 8973 8974 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 8975 .set = gfx_v10_0_set_eop_interrupt_state, 8976 .process = gfx_v10_0_eop_irq, 8977 }; 8978 8979 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 8980 .set = gfx_v10_0_set_priv_reg_fault_state, 8981 .process = gfx_v10_0_priv_reg_irq, 8982 }; 8983 8984 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 8985 .set = gfx_v10_0_set_priv_inst_fault_state, 8986 .process = gfx_v10_0_priv_inst_irq, 8987 }; 8988 8989 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 8990 .set = gfx_v10_0_kiq_set_interrupt_state, 8991 .process = gfx_v10_0_kiq_irq, 8992 }; 8993 8994 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 8995 { 8996 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 8997 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 8998 8999 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9000 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9001 9002 adev->gfx.priv_reg_irq.num_types = 1; 9003 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9004 9005 adev->gfx.priv_inst_irq.num_types = 1; 9006 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9007 } 9008 9009 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9010 { 9011 switch (adev->asic_type) { 9012 case CHIP_NAVI10: 9013 case CHIP_NAVI14: 9014 case CHIP_SIENNA_CICHLID: 9015 case CHIP_NAVY_FLOUNDER: 9016 case CHIP_VANGOGH: 9017 case CHIP_DIMGREY_CAVEFISH: 9018 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9019 break; 9020 case CHIP_NAVI12: 9021 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9022 break; 9023 default: 9024 break; 9025 } 9026 } 9027 9028 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9029 { 9030 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9031 adev->gfx.config.max_sh_per_se * 9032 adev->gfx.config.max_shader_engines; 9033 9034 adev->gds.gds_size = 0x10000; 9035 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9036 adev->gds.gws_size = 64; 9037 adev->gds.oa_size = 16; 9038 } 9039 9040 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9041 u32 bitmap) 9042 { 9043 u32 data; 9044 9045 if (!bitmap) 9046 return; 9047 9048 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9049 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9050 9051 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9052 } 9053 9054 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9055 { 9056 u32 data, wgp_bitmask; 9057 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9058 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9059 9060 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9061 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9062 9063 wgp_bitmask = 9064 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9065 9066 return (~data) & wgp_bitmask; 9067 } 9068 9069 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9070 { 9071 u32 wgp_idx, wgp_active_bitmap; 9072 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9073 9074 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9075 cu_active_bitmap = 0; 9076 9077 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9078 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9079 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9080 if (wgp_active_bitmap & (1 << wgp_idx)) 9081 cu_active_bitmap |= cu_bitmap_per_wgp; 9082 } 9083 9084 return cu_active_bitmap; 9085 } 9086 9087 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9088 struct amdgpu_cu_info *cu_info) 9089 { 9090 int i, j, k, counter, active_cu_number = 0; 9091 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9092 unsigned disable_masks[4 * 2]; 9093 9094 if (!adev || !cu_info) 9095 return -EINVAL; 9096 9097 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9098 9099 mutex_lock(&adev->grbm_idx_mutex); 9100 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9101 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9102 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9103 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 9104 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9105 continue; 9106 mask = 1; 9107 ao_bitmap = 0; 9108 counter = 0; 9109 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9110 if (i < 4 && j < 2) 9111 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9112 adev, disable_masks[i * 2 + j]); 9113 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9114 cu_info->bitmap[i][j] = bitmap; 9115 9116 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9117 if (bitmap & mask) { 9118 if (counter < adev->gfx.config.max_cu_per_sh) 9119 ao_bitmap |= mask; 9120 counter++; 9121 } 9122 mask <<= 1; 9123 } 9124 active_cu_number += counter; 9125 if (i < 2 && j < 2) 9126 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9127 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9128 } 9129 } 9130 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9131 mutex_unlock(&adev->grbm_idx_mutex); 9132 9133 cu_info->number = active_cu_number; 9134 cu_info->ao_cu_mask = ao_cu_mask; 9135 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9136 9137 return 0; 9138 } 9139 9140 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9141 { 9142 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9143 9144 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9145 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9146 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9147 9148 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9149 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9150 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9151 9152 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9153 adev->gfx.config.max_shader_engines); 9154 disabled_sa = efuse_setting | vbios_setting; 9155 disabled_sa &= max_sa_mask; 9156 9157 return disabled_sa; 9158 } 9159 9160 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9161 { 9162 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9163 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9164 9165 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9166 9167 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9168 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9169 max_shader_engines = adev->gfx.config.max_shader_engines; 9170 9171 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9172 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9173 disabled_sa_per_se &= max_sa_per_se_mask; 9174 if (disabled_sa_per_se == max_sa_per_se_mask) { 9175 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9176 break; 9177 } 9178 } 9179 } 9180 9181 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9182 { 9183 .type = AMD_IP_BLOCK_TYPE_GFX, 9184 .major = 10, 9185 .minor = 0, 9186 .rev = 0, 9187 .funcs = &gfx_v10_0_ip_funcs, 9188 }; 9189