1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "smuio/smuio_11_0_0_offset.h" 39 #include "smuio/smuio_11_0_0_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "soc15_common.h" 47 #include "clearstate_gfx10.h" 48 #include "v10_structs.h" 49 #include "gfx_v10_0.h" 50 #include "nbio_v2_3.h" 51 52 /** 53 * Navi10 has two graphic rings to share each graphic pipe. 54 * 1. Primary ring 55 * 2. Async ring 56 */ 57 #define GFX10_NUM_GFX_RINGS_NV1X 1 58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 59 #define GFX10_MEC_HPD_SIZE 2048 60 61 #define F32_CE_PROGRAM_RAM_SIZE 65536 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 64 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 70 71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 73 74 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 76 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 101 102 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 103 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 104 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 105 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 106 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 107 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 108 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 109 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 110 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 111 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 112 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 113 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 114 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 115 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 116 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 117 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 118 119 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 120 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 121 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 122 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 123 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 124 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 125 #define mmCP_HYP_CE_UCODE_DATA 0x5819 126 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 127 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 128 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 129 #define mmCP_HYP_ME_UCODE_DATA 0x5817 130 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 131 132 #define mmCPG_PSP_DEBUG 0x5c10 133 #define mmCPG_PSP_DEBUG_BASE_IDX 1 134 #define mmCPC_PSP_DEBUG 0x5c11 135 #define mmCPC_PSP_DEBUG_BASE_IDX 1 136 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 137 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 138 139 //CC_GC_SA_UNIT_DISABLE 140 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 141 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 142 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 143 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 144 //GC_USER_SA_UNIT_DISABLE 145 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 146 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 147 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 148 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 149 //PA_SC_ENHANCE_3 150 #define mmPA_SC_ENHANCE_3 0x1085 151 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 152 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 153 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 154 155 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 156 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 157 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 158 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 159 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 160 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 161 162 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 163 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 164 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 165 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 166 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 167 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 168 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 169 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 170 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 171 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 172 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 173 174 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 175 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 176 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 177 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 178 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 179 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 180 181 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 182 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 183 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 184 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 185 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 186 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 187 188 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 189 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 190 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 191 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 192 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 193 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 194 195 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 196 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 197 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 198 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 199 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 200 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 201 202 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 205 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 208 209 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 210 { 211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 251 }; 252 253 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 254 { 255 /* Pending on emulation bring up */ 256 }; 257 258 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 259 { 260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1312 }; 1313 1314 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1315 { 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1354 }; 1355 1356 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1357 { 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 1398 }; 1399 1400 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 1401 { 1402 static void *scratch_reg0; 1403 static void *scratch_reg1; 1404 static void *scratch_reg2; 1405 static void *scratch_reg3; 1406 static void *spare_int; 1407 static uint32_t grbm_cntl; 1408 static uint32_t grbm_idx; 1409 uint32_t i = 0; 1410 uint32_t retries = 50000; 1411 1412 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 1413 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 1414 scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4; 1415 scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4; 1416 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 1417 1418 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 1419 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; 1420 1421 if (amdgpu_sriov_runtime(adev)) { 1422 pr_err("shouldn't call rlcg write register during runtime\n"); 1423 return; 1424 } 1425 1426 writel(v, scratch_reg0); 1427 writel(offset | 0x80000000, scratch_reg1); 1428 writel(1, spare_int); 1429 for (i = 0; i < retries; i++) { 1430 u32 tmp; 1431 1432 tmp = readl(scratch_reg1); 1433 if (!(tmp & 0x80000000)) 1434 break; 1435 1436 udelay(10); 1437 } 1438 1439 if (i >= retries) 1440 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 1441 } 1442 1443 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1444 { 1445 /* Pending on emulation bring up */ 1446 }; 1447 1448 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1449 { 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2070 }; 2071 2072 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2073 { 2074 /* Pending on emulation bring up */ 2075 }; 2076 2077 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2078 { 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3131 }; 3132 3133 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3134 { 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3172 }; 3173 3174 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3175 { 3176 /* Pending on emulation bring up */ 3177 }; 3178 3179 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3180 { 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 3219 }; 3220 3221 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3222 { 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3246 }; 3247 3248 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3249 { 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000) 3283 }; 3284 3285 #define DEFAULT_SH_MEM_CONFIG \ 3286 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3287 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3288 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3289 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3290 3291 3292 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3293 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3294 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3295 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3296 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3297 struct amdgpu_cu_info *cu_info); 3298 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3299 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3300 u32 sh_num, u32 instance); 3301 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3302 3303 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3304 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3305 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3306 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3307 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3308 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3309 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3310 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3311 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3312 3313 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3314 { 3315 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3316 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3317 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3318 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3319 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3320 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3321 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3322 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3323 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3324 } 3325 3326 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3327 struct amdgpu_ring *ring) 3328 { 3329 struct amdgpu_device *adev = kiq_ring->adev; 3330 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3331 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3332 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3333 3334 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3335 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3336 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3337 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3338 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3339 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3340 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3341 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3342 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3343 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3344 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3345 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3346 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3347 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3348 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3349 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3350 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3351 } 3352 3353 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3354 struct amdgpu_ring *ring, 3355 enum amdgpu_unmap_queues_action action, 3356 u64 gpu_addr, u64 seq) 3357 { 3358 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3359 3360 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3361 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3362 PACKET3_UNMAP_QUEUES_ACTION(action) | 3363 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3364 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3365 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3366 amdgpu_ring_write(kiq_ring, 3367 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3368 3369 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3370 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3371 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3372 amdgpu_ring_write(kiq_ring, seq); 3373 } else { 3374 amdgpu_ring_write(kiq_ring, 0); 3375 amdgpu_ring_write(kiq_ring, 0); 3376 amdgpu_ring_write(kiq_ring, 0); 3377 } 3378 } 3379 3380 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3381 struct amdgpu_ring *ring, 3382 u64 addr, 3383 u64 seq) 3384 { 3385 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3386 3387 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3388 amdgpu_ring_write(kiq_ring, 3389 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3390 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3391 PACKET3_QUERY_STATUS_COMMAND(2)); 3392 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3393 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3394 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3395 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3396 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3397 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3398 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3399 } 3400 3401 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3402 uint16_t pasid, uint32_t flush_type, 3403 bool all_hub) 3404 { 3405 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3406 amdgpu_ring_write(kiq_ring, 3407 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3408 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3409 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3410 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3411 } 3412 3413 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3414 .kiq_set_resources = gfx10_kiq_set_resources, 3415 .kiq_map_queues = gfx10_kiq_map_queues, 3416 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3417 .kiq_query_status = gfx10_kiq_query_status, 3418 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3419 .set_resources_size = 8, 3420 .map_queues_size = 7, 3421 .unmap_queues_size = 6, 3422 .query_status_size = 7, 3423 .invalidate_tlbs_size = 2, 3424 }; 3425 3426 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3427 { 3428 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3429 } 3430 3431 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3432 { 3433 switch (adev->asic_type) { 3434 case CHIP_NAVI10: 3435 soc15_program_register_sequence(adev, 3436 golden_settings_gc_rlc_spm_10_0_nv10, 3437 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3438 break; 3439 case CHIP_NAVI14: 3440 soc15_program_register_sequence(adev, 3441 golden_settings_gc_rlc_spm_10_1_nv14, 3442 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3443 break; 3444 case CHIP_NAVI12: 3445 soc15_program_register_sequence(adev, 3446 golden_settings_gc_rlc_spm_10_1_2_nv12, 3447 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3448 break; 3449 default: 3450 break; 3451 } 3452 } 3453 3454 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3455 { 3456 switch (adev->asic_type) { 3457 case CHIP_NAVI10: 3458 soc15_program_register_sequence(adev, 3459 golden_settings_gc_10_1, 3460 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3461 soc15_program_register_sequence(adev, 3462 golden_settings_gc_10_0_nv10, 3463 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3464 break; 3465 case CHIP_NAVI14: 3466 soc15_program_register_sequence(adev, 3467 golden_settings_gc_10_1_1, 3468 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3469 soc15_program_register_sequence(adev, 3470 golden_settings_gc_10_1_nv14, 3471 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3472 break; 3473 case CHIP_NAVI12: 3474 soc15_program_register_sequence(adev, 3475 golden_settings_gc_10_1_2, 3476 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3477 soc15_program_register_sequence(adev, 3478 golden_settings_gc_10_1_2_nv12, 3479 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3480 break; 3481 case CHIP_SIENNA_CICHLID: 3482 soc15_program_register_sequence(adev, 3483 golden_settings_gc_10_3, 3484 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3485 soc15_program_register_sequence(adev, 3486 golden_settings_gc_10_3_sienna_cichlid, 3487 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3488 break; 3489 case CHIP_NAVY_FLOUNDER: 3490 soc15_program_register_sequence(adev, 3491 golden_settings_gc_10_3_2, 3492 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3493 break; 3494 case CHIP_VANGOGH: 3495 soc15_program_register_sequence(adev, 3496 golden_settings_gc_10_3_vangogh, 3497 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3498 break; 3499 case CHIP_DIMGREY_CAVEFISH: 3500 soc15_program_register_sequence(adev, 3501 golden_settings_gc_10_3_4, 3502 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3503 break; 3504 default: 3505 break; 3506 } 3507 gfx_v10_0_init_spm_golden_registers(adev); 3508 } 3509 3510 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3511 { 3512 adev->gfx.scratch.num_reg = 8; 3513 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3514 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3515 } 3516 3517 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3518 bool wc, uint32_t reg, uint32_t val) 3519 { 3520 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3521 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3522 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3523 amdgpu_ring_write(ring, reg); 3524 amdgpu_ring_write(ring, 0); 3525 amdgpu_ring_write(ring, val); 3526 } 3527 3528 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3529 int mem_space, int opt, uint32_t addr0, 3530 uint32_t addr1, uint32_t ref, uint32_t mask, 3531 uint32_t inv) 3532 { 3533 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3534 amdgpu_ring_write(ring, 3535 /* memory (1) or register (0) */ 3536 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3537 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3538 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3539 WAIT_REG_MEM_ENGINE(eng_sel))); 3540 3541 if (mem_space) 3542 BUG_ON(addr0 & 0x3); /* Dword align */ 3543 amdgpu_ring_write(ring, addr0); 3544 amdgpu_ring_write(ring, addr1); 3545 amdgpu_ring_write(ring, ref); 3546 amdgpu_ring_write(ring, mask); 3547 amdgpu_ring_write(ring, inv); /* poll interval */ 3548 } 3549 3550 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3551 { 3552 struct amdgpu_device *adev = ring->adev; 3553 uint32_t scratch; 3554 uint32_t tmp = 0; 3555 unsigned i; 3556 int r; 3557 3558 r = amdgpu_gfx_scratch_get(adev, &scratch); 3559 if (r) { 3560 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3561 return r; 3562 } 3563 3564 WREG32(scratch, 0xCAFEDEAD); 3565 3566 r = amdgpu_ring_alloc(ring, 3); 3567 if (r) { 3568 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3569 ring->idx, r); 3570 amdgpu_gfx_scratch_free(adev, scratch); 3571 return r; 3572 } 3573 3574 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3575 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3576 amdgpu_ring_write(ring, 0xDEADBEEF); 3577 amdgpu_ring_commit(ring); 3578 3579 for (i = 0; i < adev->usec_timeout; i++) { 3580 tmp = RREG32(scratch); 3581 if (tmp == 0xDEADBEEF) 3582 break; 3583 if (amdgpu_emu_mode == 1) 3584 msleep(1); 3585 else 3586 udelay(1); 3587 } 3588 3589 if (i >= adev->usec_timeout) 3590 r = -ETIMEDOUT; 3591 3592 amdgpu_gfx_scratch_free(adev, scratch); 3593 3594 return r; 3595 } 3596 3597 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3598 { 3599 struct amdgpu_device *adev = ring->adev; 3600 struct amdgpu_ib ib; 3601 struct dma_fence *f = NULL; 3602 unsigned index; 3603 uint64_t gpu_addr; 3604 uint32_t tmp; 3605 long r; 3606 3607 r = amdgpu_device_wb_get(adev, &index); 3608 if (r) 3609 return r; 3610 3611 gpu_addr = adev->wb.gpu_addr + (index * 4); 3612 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3613 memset(&ib, 0, sizeof(ib)); 3614 r = amdgpu_ib_get(adev, NULL, 16, 3615 AMDGPU_IB_POOL_DIRECT, &ib); 3616 if (r) 3617 goto err1; 3618 3619 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3620 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3621 ib.ptr[2] = lower_32_bits(gpu_addr); 3622 ib.ptr[3] = upper_32_bits(gpu_addr); 3623 ib.ptr[4] = 0xDEADBEEF; 3624 ib.length_dw = 5; 3625 3626 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3627 if (r) 3628 goto err2; 3629 3630 r = dma_fence_wait_timeout(f, false, timeout); 3631 if (r == 0) { 3632 r = -ETIMEDOUT; 3633 goto err2; 3634 } else if (r < 0) { 3635 goto err2; 3636 } 3637 3638 tmp = adev->wb.wb[index]; 3639 if (tmp == 0xDEADBEEF) 3640 r = 0; 3641 else 3642 r = -EINVAL; 3643 err2: 3644 amdgpu_ib_free(adev, &ib, NULL); 3645 dma_fence_put(f); 3646 err1: 3647 amdgpu_device_wb_free(adev, index); 3648 return r; 3649 } 3650 3651 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3652 { 3653 release_firmware(adev->gfx.pfp_fw); 3654 adev->gfx.pfp_fw = NULL; 3655 release_firmware(adev->gfx.me_fw); 3656 adev->gfx.me_fw = NULL; 3657 release_firmware(adev->gfx.ce_fw); 3658 adev->gfx.ce_fw = NULL; 3659 release_firmware(adev->gfx.rlc_fw); 3660 adev->gfx.rlc_fw = NULL; 3661 release_firmware(adev->gfx.mec_fw); 3662 adev->gfx.mec_fw = NULL; 3663 release_firmware(adev->gfx.mec2_fw); 3664 adev->gfx.mec2_fw = NULL; 3665 3666 kfree(adev->gfx.rlc.register_list_format); 3667 } 3668 3669 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3670 { 3671 adev->gfx.cp_fw_write_wait = false; 3672 3673 switch (adev->asic_type) { 3674 case CHIP_NAVI10: 3675 case CHIP_NAVI12: 3676 case CHIP_NAVI14: 3677 if ((adev->gfx.me_fw_version >= 0x00000046) && 3678 (adev->gfx.me_feature_version >= 27) && 3679 (adev->gfx.pfp_fw_version >= 0x00000068) && 3680 (adev->gfx.pfp_feature_version >= 27) && 3681 (adev->gfx.mec_fw_version >= 0x0000005b) && 3682 (adev->gfx.mec_feature_version >= 27)) 3683 adev->gfx.cp_fw_write_wait = true; 3684 break; 3685 case CHIP_SIENNA_CICHLID: 3686 case CHIP_NAVY_FLOUNDER: 3687 case CHIP_VANGOGH: 3688 case CHIP_DIMGREY_CAVEFISH: 3689 adev->gfx.cp_fw_write_wait = true; 3690 break; 3691 default: 3692 break; 3693 } 3694 3695 if (!adev->gfx.cp_fw_write_wait) 3696 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3697 } 3698 3699 3700 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3701 { 3702 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3703 3704 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 3705 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 3706 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 3707 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 3708 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 3709 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 3710 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 3711 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 3712 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 3713 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 3714 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 3715 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 3716 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 3717 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 3718 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 3719 } 3720 3721 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 3722 { 3723 const struct rlc_firmware_header_v2_2 *rlc_hdr; 3724 3725 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 3726 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 3727 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 3728 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 3729 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 3730 } 3731 3732 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3733 { 3734 bool ret = false; 3735 3736 switch (adev->pdev->revision) { 3737 case 0xc2: 3738 case 0xc3: 3739 ret = true; 3740 break; 3741 default: 3742 ret = false; 3743 break; 3744 } 3745 3746 return ret ; 3747 } 3748 3749 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3750 { 3751 switch (adev->asic_type) { 3752 case CHIP_NAVI10: 3753 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3754 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3755 break; 3756 case CHIP_VANGOGH: 3757 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3758 break; 3759 default: 3760 break; 3761 } 3762 } 3763 3764 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3765 { 3766 const char *chip_name; 3767 char fw_name[40]; 3768 char wks[10]; 3769 int err; 3770 struct amdgpu_firmware_info *info = NULL; 3771 const struct common_firmware_header *header = NULL; 3772 const struct gfx_firmware_header_v1_0 *cp_hdr; 3773 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3774 unsigned int *tmp = NULL; 3775 unsigned int i = 0; 3776 uint16_t version_major; 3777 uint16_t version_minor; 3778 3779 DRM_DEBUG("\n"); 3780 3781 memset(wks, 0, sizeof(wks)); 3782 switch (adev->asic_type) { 3783 case CHIP_NAVI10: 3784 chip_name = "navi10"; 3785 break; 3786 case CHIP_NAVI14: 3787 chip_name = "navi14"; 3788 if (!(adev->pdev->device == 0x7340 && 3789 adev->pdev->revision != 0x00)) 3790 snprintf(wks, sizeof(wks), "_wks"); 3791 break; 3792 case CHIP_NAVI12: 3793 chip_name = "navi12"; 3794 break; 3795 case CHIP_SIENNA_CICHLID: 3796 chip_name = "sienna_cichlid"; 3797 break; 3798 case CHIP_NAVY_FLOUNDER: 3799 chip_name = "navy_flounder"; 3800 break; 3801 case CHIP_VANGOGH: 3802 chip_name = "vangogh"; 3803 break; 3804 case CHIP_DIMGREY_CAVEFISH: 3805 chip_name = "dimgrey_cavefish"; 3806 break; 3807 default: 3808 BUG(); 3809 } 3810 3811 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 3812 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 3813 if (err) 3814 goto out; 3815 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 3816 if (err) 3817 goto out; 3818 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3819 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3820 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3821 3822 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 3823 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 3824 if (err) 3825 goto out; 3826 err = amdgpu_ucode_validate(adev->gfx.me_fw); 3827 if (err) 3828 goto out; 3829 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3830 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3831 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3832 3833 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 3834 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 3835 if (err) 3836 goto out; 3837 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 3838 if (err) 3839 goto out; 3840 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3841 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3842 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3843 3844 if (!amdgpu_sriov_vf(adev)) { 3845 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 3846 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 3847 if (err) 3848 goto out; 3849 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 3850 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3851 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 3852 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 3853 3854 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 3855 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 3856 adev->gfx.rlc.save_and_restore_offset = 3857 le32_to_cpu(rlc_hdr->save_and_restore_offset); 3858 adev->gfx.rlc.clear_state_descriptor_offset = 3859 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 3860 adev->gfx.rlc.avail_scratch_ram_locations = 3861 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 3862 adev->gfx.rlc.reg_restore_list_size = 3863 le32_to_cpu(rlc_hdr->reg_restore_list_size); 3864 adev->gfx.rlc.reg_list_format_start = 3865 le32_to_cpu(rlc_hdr->reg_list_format_start); 3866 adev->gfx.rlc.reg_list_format_separate_start = 3867 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 3868 adev->gfx.rlc.starting_offsets_start = 3869 le32_to_cpu(rlc_hdr->starting_offsets_start); 3870 adev->gfx.rlc.reg_list_format_size_bytes = 3871 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 3872 adev->gfx.rlc.reg_list_size_bytes = 3873 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 3874 adev->gfx.rlc.register_list_format = 3875 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 3876 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 3877 if (!adev->gfx.rlc.register_list_format) { 3878 err = -ENOMEM; 3879 goto out; 3880 } 3881 3882 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3883 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 3884 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 3885 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 3886 3887 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 3888 3889 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3890 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 3891 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 3892 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 3893 3894 if (version_major == 2) { 3895 if (version_minor >= 1) 3896 gfx_v10_0_init_rlc_ext_microcode(adev); 3897 if (version_minor == 2) 3898 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 3899 } 3900 } 3901 3902 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 3903 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 3904 if (err) 3905 goto out; 3906 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 3907 if (err) 3908 goto out; 3909 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3910 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3911 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3912 3913 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 3914 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 3915 if (!err) { 3916 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 3917 if (err) 3918 goto out; 3919 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 3920 adev->gfx.mec2_fw->data; 3921 adev->gfx.mec2_fw_version = 3922 le32_to_cpu(cp_hdr->header.ucode_version); 3923 adev->gfx.mec2_feature_version = 3924 le32_to_cpu(cp_hdr->ucode_feature_version); 3925 } else { 3926 err = 0; 3927 adev->gfx.mec2_fw = NULL; 3928 } 3929 3930 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 3931 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 3932 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 3933 info->fw = adev->gfx.pfp_fw; 3934 header = (const struct common_firmware_header *)info->fw->data; 3935 adev->firmware.fw_size += 3936 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3937 3938 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 3939 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 3940 info->fw = adev->gfx.me_fw; 3941 header = (const struct common_firmware_header *)info->fw->data; 3942 adev->firmware.fw_size += 3943 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3944 3945 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 3946 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 3947 info->fw = adev->gfx.ce_fw; 3948 header = (const struct common_firmware_header *)info->fw->data; 3949 adev->firmware.fw_size += 3950 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3951 3952 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 3953 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 3954 info->fw = adev->gfx.rlc_fw; 3955 if (info->fw) { 3956 header = (const struct common_firmware_header *)info->fw->data; 3957 adev->firmware.fw_size += 3958 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3959 } 3960 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 3961 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 3962 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 3963 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 3964 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 3965 info->fw = adev->gfx.rlc_fw; 3966 adev->firmware.fw_size += 3967 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 3968 3969 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 3970 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 3971 info->fw = adev->gfx.rlc_fw; 3972 adev->firmware.fw_size += 3973 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 3974 3975 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 3976 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 3977 info->fw = adev->gfx.rlc_fw; 3978 adev->firmware.fw_size += 3979 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 3980 3981 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 3982 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 3983 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 3984 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 3985 info->fw = adev->gfx.rlc_fw; 3986 adev->firmware.fw_size += 3987 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 3988 3989 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 3990 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 3991 info->fw = adev->gfx.rlc_fw; 3992 adev->firmware.fw_size += 3993 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 3994 } 3995 } 3996 3997 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 3998 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 3999 info->fw = adev->gfx.mec_fw; 4000 header = (const struct common_firmware_header *)info->fw->data; 4001 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4002 adev->firmware.fw_size += 4003 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4004 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4005 4006 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4007 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4008 info->fw = adev->gfx.mec_fw; 4009 adev->firmware.fw_size += 4010 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4011 4012 if (adev->gfx.mec2_fw) { 4013 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4014 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4015 info->fw = adev->gfx.mec2_fw; 4016 header = (const struct common_firmware_header *)info->fw->data; 4017 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4018 adev->firmware.fw_size += 4019 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4020 le32_to_cpu(cp_hdr->jt_size) * 4, 4021 PAGE_SIZE); 4022 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4023 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4024 info->fw = adev->gfx.mec2_fw; 4025 adev->firmware.fw_size += 4026 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4027 PAGE_SIZE); 4028 } 4029 } 4030 4031 gfx_v10_0_check_fw_write_wait(adev); 4032 out: 4033 if (err) { 4034 dev_err(adev->dev, 4035 "gfx10: Failed to load firmware \"%s\"\n", 4036 fw_name); 4037 release_firmware(adev->gfx.pfp_fw); 4038 adev->gfx.pfp_fw = NULL; 4039 release_firmware(adev->gfx.me_fw); 4040 adev->gfx.me_fw = NULL; 4041 release_firmware(adev->gfx.ce_fw); 4042 adev->gfx.ce_fw = NULL; 4043 release_firmware(adev->gfx.rlc_fw); 4044 adev->gfx.rlc_fw = NULL; 4045 release_firmware(adev->gfx.mec_fw); 4046 adev->gfx.mec_fw = NULL; 4047 release_firmware(adev->gfx.mec2_fw); 4048 adev->gfx.mec2_fw = NULL; 4049 } 4050 4051 gfx_v10_0_check_gfxoff_flag(adev); 4052 4053 return err; 4054 } 4055 4056 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4057 { 4058 u32 count = 0; 4059 const struct cs_section_def *sect = NULL; 4060 const struct cs_extent_def *ext = NULL; 4061 4062 /* begin clear state */ 4063 count += 2; 4064 /* context control state */ 4065 count += 3; 4066 4067 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4068 for (ext = sect->section; ext->extent != NULL; ++ext) { 4069 if (sect->id == SECT_CONTEXT) 4070 count += 2 + ext->reg_count; 4071 else 4072 return 0; 4073 } 4074 } 4075 4076 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4077 count += 3; 4078 /* end clear state */ 4079 count += 2; 4080 /* clear state */ 4081 count += 2; 4082 4083 return count; 4084 } 4085 4086 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4087 volatile u32 *buffer) 4088 { 4089 u32 count = 0, i; 4090 const struct cs_section_def *sect = NULL; 4091 const struct cs_extent_def *ext = NULL; 4092 int ctx_reg_offset; 4093 4094 if (adev->gfx.rlc.cs_data == NULL) 4095 return; 4096 if (buffer == NULL) 4097 return; 4098 4099 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4100 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4101 4102 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4103 buffer[count++] = cpu_to_le32(0x80000000); 4104 buffer[count++] = cpu_to_le32(0x80000000); 4105 4106 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4107 for (ext = sect->section; ext->extent != NULL; ++ext) { 4108 if (sect->id == SECT_CONTEXT) { 4109 buffer[count++] = 4110 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4111 buffer[count++] = cpu_to_le32(ext->reg_index - 4112 PACKET3_SET_CONTEXT_REG_START); 4113 for (i = 0; i < ext->reg_count; i++) 4114 buffer[count++] = cpu_to_le32(ext->extent[i]); 4115 } else { 4116 return; 4117 } 4118 } 4119 } 4120 4121 ctx_reg_offset = 4122 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4123 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4124 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4125 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4126 4127 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4128 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4129 4130 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4131 buffer[count++] = cpu_to_le32(0); 4132 } 4133 4134 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4135 { 4136 /* clear state block */ 4137 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4138 &adev->gfx.rlc.clear_state_gpu_addr, 4139 (void **)&adev->gfx.rlc.cs_ptr); 4140 4141 /* jump table block */ 4142 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4143 &adev->gfx.rlc.cp_table_gpu_addr, 4144 (void **)&adev->gfx.rlc.cp_table_ptr); 4145 } 4146 4147 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4148 { 4149 const struct cs_section_def *cs_data; 4150 int r; 4151 4152 adev->gfx.rlc.cs_data = gfx10_cs_data; 4153 4154 cs_data = adev->gfx.rlc.cs_data; 4155 4156 if (cs_data) { 4157 /* init clear state block */ 4158 r = amdgpu_gfx_rlc_init_csb(adev); 4159 if (r) 4160 return r; 4161 } 4162 4163 /* init spm vmid with 0xf */ 4164 if (adev->gfx.rlc.funcs->update_spm_vmid) 4165 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4166 4167 return 0; 4168 } 4169 4170 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4171 { 4172 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4173 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4174 } 4175 4176 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4177 { 4178 int r; 4179 4180 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4181 4182 amdgpu_gfx_graphics_queue_acquire(adev); 4183 4184 r = gfx_v10_0_init_microcode(adev); 4185 if (r) 4186 DRM_ERROR("Failed to load gfx firmware!\n"); 4187 4188 return r; 4189 } 4190 4191 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4192 { 4193 int r; 4194 u32 *hpd; 4195 const __le32 *fw_data = NULL; 4196 unsigned fw_size; 4197 u32 *fw = NULL; 4198 size_t mec_hpd_size; 4199 4200 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4201 4202 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4203 4204 /* take ownership of the relevant compute queues */ 4205 amdgpu_gfx_compute_queue_acquire(adev); 4206 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4207 4208 if (mec_hpd_size) { 4209 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4210 AMDGPU_GEM_DOMAIN_GTT, 4211 &adev->gfx.mec.hpd_eop_obj, 4212 &adev->gfx.mec.hpd_eop_gpu_addr, 4213 (void **)&hpd); 4214 if (r) { 4215 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4216 gfx_v10_0_mec_fini(adev); 4217 return r; 4218 } 4219 4220 memset(hpd, 0, mec_hpd_size); 4221 4222 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4223 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4224 } 4225 4226 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4227 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4228 4229 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4230 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4231 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4232 4233 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4234 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4235 &adev->gfx.mec.mec_fw_obj, 4236 &adev->gfx.mec.mec_fw_gpu_addr, 4237 (void **)&fw); 4238 if (r) { 4239 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4240 gfx_v10_0_mec_fini(adev); 4241 return r; 4242 } 4243 4244 memcpy(fw, fw_data, fw_size); 4245 4246 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4247 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4248 } 4249 4250 return 0; 4251 } 4252 4253 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4254 { 4255 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4256 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4257 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4258 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4259 } 4260 4261 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4262 uint32_t thread, uint32_t regno, 4263 uint32_t num, uint32_t *out) 4264 { 4265 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4266 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4267 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4268 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4269 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4270 while (num--) 4271 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4272 } 4273 4274 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4275 { 4276 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4277 * field when performing a select_se_sh so it should be 4278 * zero here */ 4279 WARN_ON(simd != 0); 4280 4281 /* type 2 wave data */ 4282 dst[(*no_fields)++] = 2; 4283 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4284 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4285 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4286 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4287 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4288 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4289 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4290 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4291 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4292 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4293 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4294 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4295 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4296 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4297 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4298 } 4299 4300 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4301 uint32_t wave, uint32_t start, 4302 uint32_t size, uint32_t *dst) 4303 { 4304 WARN_ON(simd != 0); 4305 4306 wave_read_regs( 4307 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4308 dst); 4309 } 4310 4311 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4312 uint32_t wave, uint32_t thread, 4313 uint32_t start, uint32_t size, 4314 uint32_t *dst) 4315 { 4316 wave_read_regs( 4317 adev, wave, thread, 4318 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4319 } 4320 4321 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4322 u32 me, u32 pipe, u32 q, u32 vm) 4323 { 4324 nv_grbm_select(adev, me, pipe, q, vm); 4325 } 4326 4327 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4328 bool enable) 4329 { 4330 uint32_t data, def; 4331 4332 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4333 4334 if (enable) 4335 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4336 else 4337 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4338 4339 if (data != def) 4340 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4341 } 4342 4343 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4344 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4345 .select_se_sh = &gfx_v10_0_select_se_sh, 4346 .read_wave_data = &gfx_v10_0_read_wave_data, 4347 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4348 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4349 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4350 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4351 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4352 }; 4353 4354 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4355 { 4356 u32 gb_addr_config; 4357 4358 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4359 4360 switch (adev->asic_type) { 4361 case CHIP_NAVI10: 4362 case CHIP_NAVI14: 4363 case CHIP_NAVI12: 4364 adev->gfx.config.max_hw_contexts = 8; 4365 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4366 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4367 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4368 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4369 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4370 break; 4371 case CHIP_SIENNA_CICHLID: 4372 case CHIP_NAVY_FLOUNDER: 4373 case CHIP_VANGOGH: 4374 case CHIP_DIMGREY_CAVEFISH: 4375 adev->gfx.config.max_hw_contexts = 8; 4376 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4377 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4378 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4379 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4380 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4381 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4382 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4383 break; 4384 default: 4385 BUG(); 4386 break; 4387 } 4388 4389 adev->gfx.config.gb_addr_config = gb_addr_config; 4390 4391 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4392 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4393 GB_ADDR_CONFIG, NUM_PIPES); 4394 4395 adev->gfx.config.max_tile_pipes = 4396 adev->gfx.config.gb_addr_config_fields.num_pipes; 4397 4398 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4399 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4400 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4401 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4402 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4403 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4404 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4405 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4406 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4407 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4408 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4409 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4410 } 4411 4412 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4413 int me, int pipe, int queue) 4414 { 4415 int r; 4416 struct amdgpu_ring *ring; 4417 unsigned int irq_type; 4418 4419 ring = &adev->gfx.gfx_ring[ring_id]; 4420 4421 ring->me = me; 4422 ring->pipe = pipe; 4423 ring->queue = queue; 4424 4425 ring->ring_obj = NULL; 4426 ring->use_doorbell = true; 4427 4428 if (!ring_id) 4429 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4430 else 4431 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4432 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4433 4434 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4435 r = amdgpu_ring_init(adev, ring, 1024, 4436 &adev->gfx.eop_irq, irq_type, 4437 AMDGPU_RING_PRIO_DEFAULT); 4438 if (r) 4439 return r; 4440 return 0; 4441 } 4442 4443 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4444 int mec, int pipe, int queue) 4445 { 4446 int r; 4447 unsigned irq_type; 4448 struct amdgpu_ring *ring; 4449 unsigned int hw_prio; 4450 4451 ring = &adev->gfx.compute_ring[ring_id]; 4452 4453 /* mec0 is me1 */ 4454 ring->me = mec + 1; 4455 ring->pipe = pipe; 4456 ring->queue = queue; 4457 4458 ring->ring_obj = NULL; 4459 ring->use_doorbell = true; 4460 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4461 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4462 + (ring_id * GFX10_MEC_HPD_SIZE); 4463 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4464 4465 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4466 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4467 + ring->pipe; 4468 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ? 4469 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4470 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4471 r = amdgpu_ring_init(adev, ring, 1024, 4472 &adev->gfx.eop_irq, irq_type, hw_prio); 4473 if (r) 4474 return r; 4475 4476 return 0; 4477 } 4478 4479 static int gfx_v10_0_sw_init(void *handle) 4480 { 4481 int i, j, k, r, ring_id = 0; 4482 struct amdgpu_kiq *kiq; 4483 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4484 4485 switch (adev->asic_type) { 4486 case CHIP_NAVI10: 4487 case CHIP_NAVI14: 4488 case CHIP_NAVI12: 4489 adev->gfx.me.num_me = 1; 4490 adev->gfx.me.num_pipe_per_me = 1; 4491 adev->gfx.me.num_queue_per_pipe = 1; 4492 adev->gfx.mec.num_mec = 2; 4493 adev->gfx.mec.num_pipe_per_mec = 4; 4494 adev->gfx.mec.num_queue_per_pipe = 8; 4495 break; 4496 case CHIP_SIENNA_CICHLID: 4497 case CHIP_NAVY_FLOUNDER: 4498 case CHIP_VANGOGH: 4499 case CHIP_DIMGREY_CAVEFISH: 4500 adev->gfx.me.num_me = 1; 4501 adev->gfx.me.num_pipe_per_me = 1; 4502 adev->gfx.me.num_queue_per_pipe = 1; 4503 adev->gfx.mec.num_mec = 2; 4504 adev->gfx.mec.num_pipe_per_mec = 4; 4505 adev->gfx.mec.num_queue_per_pipe = 4; 4506 break; 4507 default: 4508 adev->gfx.me.num_me = 1; 4509 adev->gfx.me.num_pipe_per_me = 1; 4510 adev->gfx.me.num_queue_per_pipe = 1; 4511 adev->gfx.mec.num_mec = 1; 4512 adev->gfx.mec.num_pipe_per_mec = 4; 4513 adev->gfx.mec.num_queue_per_pipe = 8; 4514 break; 4515 } 4516 4517 /* KIQ event */ 4518 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4519 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4520 &adev->gfx.kiq.irq); 4521 if (r) 4522 return r; 4523 4524 /* EOP Event */ 4525 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4526 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4527 &adev->gfx.eop_irq); 4528 if (r) 4529 return r; 4530 4531 /* Privileged reg */ 4532 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4533 &adev->gfx.priv_reg_irq); 4534 if (r) 4535 return r; 4536 4537 /* Privileged inst */ 4538 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4539 &adev->gfx.priv_inst_irq); 4540 if (r) 4541 return r; 4542 4543 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4544 4545 gfx_v10_0_scratch_init(adev); 4546 4547 r = gfx_v10_0_me_init(adev); 4548 if (r) 4549 return r; 4550 4551 r = gfx_v10_0_rlc_init(adev); 4552 if (r) { 4553 DRM_ERROR("Failed to init rlc BOs!\n"); 4554 return r; 4555 } 4556 4557 r = gfx_v10_0_mec_init(adev); 4558 if (r) { 4559 DRM_ERROR("Failed to init MEC BOs!\n"); 4560 return r; 4561 } 4562 4563 /* set up the gfx ring */ 4564 for (i = 0; i < adev->gfx.me.num_me; i++) { 4565 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4566 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4567 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4568 continue; 4569 4570 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4571 i, k, j); 4572 if (r) 4573 return r; 4574 ring_id++; 4575 } 4576 } 4577 } 4578 4579 ring_id = 0; 4580 /* set up the compute queues - allocate horizontally across pipes */ 4581 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4582 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4583 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4584 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4585 j)) 4586 continue; 4587 4588 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4589 i, k, j); 4590 if (r) 4591 return r; 4592 4593 ring_id++; 4594 } 4595 } 4596 } 4597 4598 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4599 if (r) { 4600 DRM_ERROR("Failed to init KIQ BOs!\n"); 4601 return r; 4602 } 4603 4604 kiq = &adev->gfx.kiq; 4605 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4606 if (r) 4607 return r; 4608 4609 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4610 if (r) 4611 return r; 4612 4613 /* allocate visible FB for rlc auto-loading fw */ 4614 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4615 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4616 if (r) 4617 return r; 4618 } 4619 4620 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4621 4622 gfx_v10_0_gpu_early_init(adev); 4623 4624 return 0; 4625 } 4626 4627 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4628 { 4629 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4630 &adev->gfx.pfp.pfp_fw_gpu_addr, 4631 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4632 } 4633 4634 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4635 { 4636 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4637 &adev->gfx.ce.ce_fw_gpu_addr, 4638 (void **)&adev->gfx.ce.ce_fw_ptr); 4639 } 4640 4641 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4642 { 4643 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4644 &adev->gfx.me.me_fw_gpu_addr, 4645 (void **)&adev->gfx.me.me_fw_ptr); 4646 } 4647 4648 static int gfx_v10_0_sw_fini(void *handle) 4649 { 4650 int i; 4651 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4652 4653 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4654 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4655 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4656 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4657 4658 amdgpu_gfx_mqd_sw_fini(adev); 4659 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4660 amdgpu_gfx_kiq_fini(adev); 4661 4662 gfx_v10_0_pfp_fini(adev); 4663 gfx_v10_0_ce_fini(adev); 4664 gfx_v10_0_me_fini(adev); 4665 gfx_v10_0_rlc_fini(adev); 4666 gfx_v10_0_mec_fini(adev); 4667 4668 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4669 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4670 4671 gfx_v10_0_free_microcode(adev); 4672 4673 return 0; 4674 } 4675 4676 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4677 u32 sh_num, u32 instance) 4678 { 4679 u32 data; 4680 4681 if (instance == 0xffffffff) 4682 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4683 INSTANCE_BROADCAST_WRITES, 1); 4684 else 4685 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4686 instance); 4687 4688 if (se_num == 0xffffffff) 4689 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4690 1); 4691 else 4692 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4693 4694 if (sh_num == 0xffffffff) 4695 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4696 1); 4697 else 4698 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4699 4700 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4701 } 4702 4703 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4704 { 4705 u32 data, mask; 4706 4707 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4708 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4709 4710 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4711 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4712 4713 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4714 adev->gfx.config.max_sh_per_se); 4715 4716 return (~data) & mask; 4717 } 4718 4719 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4720 { 4721 int i, j; 4722 u32 data; 4723 u32 active_rbs = 0; 4724 u32 bitmap; 4725 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4726 adev->gfx.config.max_sh_per_se; 4727 4728 mutex_lock(&adev->grbm_idx_mutex); 4729 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4730 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4731 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4732 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 4733 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4734 continue; 4735 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4736 data = gfx_v10_0_get_rb_active_bitmap(adev); 4737 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4738 rb_bitmap_width_per_sh); 4739 } 4740 } 4741 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4742 mutex_unlock(&adev->grbm_idx_mutex); 4743 4744 adev->gfx.config.backend_enable_mask = active_rbs; 4745 adev->gfx.config.num_rbs = hweight32(active_rbs); 4746 } 4747 4748 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4749 { 4750 uint32_t num_sc; 4751 uint32_t enabled_rb_per_sh; 4752 uint32_t active_rb_bitmap; 4753 uint32_t num_rb_per_sc; 4754 uint32_t num_packer_per_sc; 4755 uint32_t pa_sc_tile_steering_override; 4756 4757 /* for ASICs that integrates GFX v10.3 4758 * pa_sc_tile_steering_override should be set to 0 */ 4759 if (adev->asic_type == CHIP_SIENNA_CICHLID || 4760 adev->asic_type == CHIP_NAVY_FLOUNDER || 4761 adev->asic_type == CHIP_DIMGREY_CAVEFISH || 4762 adev->asic_type == CHIP_VANGOGH) 4763 return 0; 4764 4765 /* init num_sc */ 4766 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4767 adev->gfx.config.num_sc_per_sh; 4768 /* init num_rb_per_sc */ 4769 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4770 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4771 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4772 /* init num_packer_per_sc */ 4773 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4774 4775 pa_sc_tile_steering_override = 0; 4776 pa_sc_tile_steering_override |= 4777 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4778 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4779 pa_sc_tile_steering_override |= 4780 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4781 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4782 pa_sc_tile_steering_override |= 4783 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4784 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4785 4786 return pa_sc_tile_steering_override; 4787 } 4788 4789 #define DEFAULT_SH_MEM_BASES (0x6000) 4790 4791 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4792 { 4793 int i; 4794 uint32_t sh_mem_bases; 4795 4796 /* 4797 * Configure apertures: 4798 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4799 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4800 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4801 */ 4802 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4803 4804 mutex_lock(&adev->srbm_mutex); 4805 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4806 nv_grbm_select(adev, 0, 0, 0, i); 4807 /* CP and shaders */ 4808 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4809 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4810 } 4811 nv_grbm_select(adev, 0, 0, 0, 0); 4812 mutex_unlock(&adev->srbm_mutex); 4813 4814 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4815 acccess. These should be enabled by FW for target VMIDs. */ 4816 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4817 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4818 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4819 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4820 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4821 } 4822 } 4823 4824 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4825 { 4826 int vmid; 4827 4828 /* 4829 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4830 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4831 * the driver can enable them for graphics. VMID0 should maintain 4832 * access so that HWS firmware can save/restore entries. 4833 */ 4834 for (vmid = 1; vmid < 16; vmid++) { 4835 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4836 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4837 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4838 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4839 } 4840 } 4841 4842 4843 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4844 { 4845 int i, j, k; 4846 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4847 u32 tmp, wgp_active_bitmap = 0; 4848 u32 gcrd_targets_disable_tcp = 0; 4849 u32 utcl_invreq_disable = 0; 4850 /* 4851 * GCRD_TARGETS_DISABLE field contains 4852 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4853 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4854 */ 4855 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4856 2 * max_wgp_per_sh + /* TCP */ 4857 max_wgp_per_sh + /* SQC */ 4858 4); /* GL1C */ 4859 /* 4860 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4861 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4862 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4863 */ 4864 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4865 2 * max_wgp_per_sh + /* TCP */ 4866 2 * max_wgp_per_sh + /* SQC */ 4867 4 + /* RMI */ 4868 1); /* SQG */ 4869 4870 if (adev->asic_type == CHIP_NAVI10 || 4871 adev->asic_type == CHIP_NAVI14 || 4872 adev->asic_type == CHIP_NAVI12) { 4873 mutex_lock(&adev->grbm_idx_mutex); 4874 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4875 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4876 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4877 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4878 /* 4879 * Set corresponding TCP bits for the inactive WGPs in 4880 * GCRD_SA_TARGETS_DISABLE 4881 */ 4882 gcrd_targets_disable_tcp = 0; 4883 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4884 utcl_invreq_disable = 0; 4885 4886 for (k = 0; k < max_wgp_per_sh; k++) { 4887 if (!(wgp_active_bitmap & (1 << k))) { 4888 gcrd_targets_disable_tcp |= 3 << (2 * k); 4889 utcl_invreq_disable |= (3 << (2 * k)) | 4890 (3 << (2 * (max_wgp_per_sh + k))); 4891 } 4892 } 4893 4894 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4895 /* only override TCP & SQC bits */ 4896 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 4897 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4898 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4899 4900 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4901 /* only override TCP bits */ 4902 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 4903 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4904 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4905 } 4906 } 4907 4908 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4909 mutex_unlock(&adev->grbm_idx_mutex); 4910 } 4911 } 4912 4913 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4914 { 4915 /* TCCs are global (not instanced). */ 4916 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4917 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4918 4919 adev->gfx.config.tcc_disabled_mask = 4920 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4921 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4922 } 4923 4924 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4925 { 4926 u32 tmp; 4927 int i; 4928 4929 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4930 4931 gfx_v10_0_setup_rb(adev); 4932 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4933 gfx_v10_0_get_tcc_info(adev); 4934 adev->gfx.config.pa_sc_tile_steering_override = 4935 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4936 4937 /* XXX SH_MEM regs */ 4938 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4939 mutex_lock(&adev->srbm_mutex); 4940 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 4941 nv_grbm_select(adev, 0, 0, 0, i); 4942 /* CP and shaders */ 4943 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4944 if (i != 0) { 4945 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4946 (adev->gmc.private_aperture_start >> 48)); 4947 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4948 (adev->gmc.shared_aperture_start >> 48)); 4949 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4950 } 4951 } 4952 nv_grbm_select(adev, 0, 0, 0, 0); 4953 4954 mutex_unlock(&adev->srbm_mutex); 4955 4956 gfx_v10_0_init_compute_vmid(adev); 4957 gfx_v10_0_init_gds_vmid(adev); 4958 4959 } 4960 4961 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 4962 bool enable) 4963 { 4964 u32 tmp; 4965 4966 if (amdgpu_sriov_vf(adev)) 4967 return; 4968 4969 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 4970 4971 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 4972 enable ? 1 : 0); 4973 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 4974 enable ? 1 : 0); 4975 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 4976 enable ? 1 : 0); 4977 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 4978 enable ? 1 : 0); 4979 4980 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 4981 } 4982 4983 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 4984 { 4985 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 4986 4987 /* csib */ 4988 if (adev->asic_type == CHIP_NAVI12) { 4989 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 4990 adev->gfx.rlc.clear_state_gpu_addr >> 32); 4991 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 4992 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 4993 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 4994 } else { 4995 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 4996 adev->gfx.rlc.clear_state_gpu_addr >> 32); 4997 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 4998 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 4999 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5000 } 5001 return 0; 5002 } 5003 5004 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5005 { 5006 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5007 5008 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5009 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5010 } 5011 5012 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5013 { 5014 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5015 udelay(50); 5016 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5017 udelay(50); 5018 } 5019 5020 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5021 bool enable) 5022 { 5023 uint32_t rlc_pg_cntl; 5024 5025 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5026 5027 if (!enable) { 5028 /* RLC_PG_CNTL[23] = 0 (default) 5029 * RLC will wait for handshake acks with SMU 5030 * GFXOFF will be enabled 5031 * RLC_PG_CNTL[23] = 1 5032 * RLC will not issue any message to SMU 5033 * hence no handshake between SMU & RLC 5034 * GFXOFF will be disabled 5035 */ 5036 rlc_pg_cntl |= 0x800000; 5037 } else 5038 rlc_pg_cntl &= ~0x800000; 5039 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5040 } 5041 5042 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5043 { 5044 /* TODO: enable rlc & smu handshake until smu 5045 * and gfxoff feature works as expected */ 5046 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5047 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5048 5049 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5050 udelay(50); 5051 } 5052 5053 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5054 { 5055 uint32_t tmp; 5056 5057 /* enable Save Restore Machine */ 5058 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 5059 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5060 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5061 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 5062 } 5063 5064 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5065 { 5066 const struct rlc_firmware_header_v2_0 *hdr; 5067 const __le32 *fw_data; 5068 unsigned i, fw_size; 5069 5070 if (!adev->gfx.rlc_fw) 5071 return -EINVAL; 5072 5073 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5074 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5075 5076 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5077 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5078 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5079 5080 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5081 RLCG_UCODE_LOADING_START_ADDRESS); 5082 5083 for (i = 0; i < fw_size; i++) 5084 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5085 le32_to_cpup(fw_data++)); 5086 5087 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5088 5089 return 0; 5090 } 5091 5092 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5093 { 5094 int r; 5095 5096 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 5097 5098 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5099 if (r) 5100 return r; 5101 5102 gfx_v10_0_init_csb(adev); 5103 5104 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5105 gfx_v10_0_rlc_enable_srm(adev); 5106 } else { 5107 if (amdgpu_sriov_vf(adev)) { 5108 gfx_v10_0_init_csb(adev); 5109 return 0; 5110 } 5111 5112 adev->gfx.rlc.funcs->stop(adev); 5113 5114 /* disable CG */ 5115 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5116 5117 /* disable PG */ 5118 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5119 5120 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5121 /* legacy rlc firmware loading */ 5122 r = gfx_v10_0_rlc_load_microcode(adev); 5123 if (r) 5124 return r; 5125 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5126 /* rlc backdoor autoload firmware */ 5127 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5128 if (r) 5129 return r; 5130 } 5131 5132 gfx_v10_0_init_csb(adev); 5133 5134 adev->gfx.rlc.funcs->start(adev); 5135 5136 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5137 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5138 if (r) 5139 return r; 5140 } 5141 } 5142 return 0; 5143 } 5144 5145 static struct { 5146 FIRMWARE_ID id; 5147 unsigned int offset; 5148 unsigned int size; 5149 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5150 5151 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5152 { 5153 int ret; 5154 RLC_TABLE_OF_CONTENT *rlc_toc; 5155 5156 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 5157 AMDGPU_GEM_DOMAIN_GTT, 5158 &adev->gfx.rlc.rlc_toc_bo, 5159 &adev->gfx.rlc.rlc_toc_gpu_addr, 5160 (void **)&adev->gfx.rlc.rlc_toc_buf); 5161 if (ret) { 5162 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5163 return ret; 5164 } 5165 5166 /* Copy toc from psp sos fw to rlc toc buffer */ 5167 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 5168 5169 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5170 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5171 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5172 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5173 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5174 /* Offset needs 4KB alignment */ 5175 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5176 } 5177 5178 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5179 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5180 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5181 5182 rlc_toc++; 5183 } 5184 5185 return 0; 5186 } 5187 5188 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5189 { 5190 uint32_t total_size = 0; 5191 FIRMWARE_ID id; 5192 int ret; 5193 5194 ret = gfx_v10_0_parse_rlc_toc(adev); 5195 if (ret) { 5196 dev_err(adev->dev, "failed to parse rlc toc\n"); 5197 return 0; 5198 } 5199 5200 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5201 total_size += rlc_autoload_info[id].size; 5202 5203 /* In case the offset in rlc toc ucode is aligned */ 5204 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5205 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5206 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5207 5208 return total_size; 5209 } 5210 5211 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5212 { 5213 int r; 5214 uint32_t total_size; 5215 5216 total_size = gfx_v10_0_calc_toc_total_size(adev); 5217 5218 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5219 AMDGPU_GEM_DOMAIN_GTT, 5220 &adev->gfx.rlc.rlc_autoload_bo, 5221 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5222 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5223 if (r) { 5224 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5225 return r; 5226 } 5227 5228 return 0; 5229 } 5230 5231 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5232 { 5233 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5234 &adev->gfx.rlc.rlc_toc_gpu_addr, 5235 (void **)&adev->gfx.rlc.rlc_toc_buf); 5236 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5237 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5238 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5239 } 5240 5241 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5242 FIRMWARE_ID id, 5243 const void *fw_data, 5244 uint32_t fw_size) 5245 { 5246 uint32_t toc_offset; 5247 uint32_t toc_fw_size; 5248 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5249 5250 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5251 return; 5252 5253 toc_offset = rlc_autoload_info[id].offset; 5254 toc_fw_size = rlc_autoload_info[id].size; 5255 5256 if (fw_size == 0) 5257 fw_size = toc_fw_size; 5258 5259 if (fw_size > toc_fw_size) 5260 fw_size = toc_fw_size; 5261 5262 memcpy(ptr + toc_offset, fw_data, fw_size); 5263 5264 if (fw_size < toc_fw_size) 5265 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5266 } 5267 5268 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5269 { 5270 void *data; 5271 uint32_t size; 5272 5273 data = adev->gfx.rlc.rlc_toc_buf; 5274 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5275 5276 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5277 FIRMWARE_ID_RLC_TOC, 5278 data, size); 5279 } 5280 5281 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5282 { 5283 const __le32 *fw_data; 5284 uint32_t fw_size; 5285 const struct gfx_firmware_header_v1_0 *cp_hdr; 5286 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5287 5288 /* pfp ucode */ 5289 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5290 adev->gfx.pfp_fw->data; 5291 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5292 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5293 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5294 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5295 FIRMWARE_ID_CP_PFP, 5296 fw_data, fw_size); 5297 5298 /* ce ucode */ 5299 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5300 adev->gfx.ce_fw->data; 5301 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5302 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5303 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5304 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5305 FIRMWARE_ID_CP_CE, 5306 fw_data, fw_size); 5307 5308 /* me ucode */ 5309 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5310 adev->gfx.me_fw->data; 5311 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5312 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5313 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5314 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5315 FIRMWARE_ID_CP_ME, 5316 fw_data, fw_size); 5317 5318 /* rlc ucode */ 5319 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5320 adev->gfx.rlc_fw->data; 5321 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5322 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5323 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5324 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5325 FIRMWARE_ID_RLC_G_UCODE, 5326 fw_data, fw_size); 5327 5328 /* mec1 ucode */ 5329 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5330 adev->gfx.mec_fw->data; 5331 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5332 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5333 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5334 cp_hdr->jt_size * 4; 5335 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5336 FIRMWARE_ID_CP_MEC, 5337 fw_data, fw_size); 5338 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5339 } 5340 5341 /* Temporarily put sdma part here */ 5342 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5343 { 5344 const __le32 *fw_data; 5345 uint32_t fw_size; 5346 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5347 int i; 5348 5349 for (i = 0; i < adev->sdma.num_instances; i++) { 5350 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5351 adev->sdma.instance[i].fw->data; 5352 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5353 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5354 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5355 5356 if (i == 0) { 5357 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5358 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5359 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5360 FIRMWARE_ID_SDMA0_JT, 5361 (uint32_t *)fw_data + 5362 sdma_hdr->jt_offset, 5363 sdma_hdr->jt_size * 4); 5364 } else if (i == 1) { 5365 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5366 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5367 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5368 FIRMWARE_ID_SDMA1_JT, 5369 (uint32_t *)fw_data + 5370 sdma_hdr->jt_offset, 5371 sdma_hdr->jt_size * 4); 5372 } 5373 } 5374 } 5375 5376 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5377 { 5378 uint32_t rlc_g_offset, rlc_g_size, tmp; 5379 uint64_t gpu_addr; 5380 5381 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5382 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5383 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5384 5385 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5386 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5387 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5388 5389 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5390 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5391 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5392 5393 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5394 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5395 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5396 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5397 return -EINVAL; 5398 } 5399 5400 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5401 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5402 DRM_ERROR("RLC ROM should halt itself\n"); 5403 return -EINVAL; 5404 } 5405 5406 return 0; 5407 } 5408 5409 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5410 { 5411 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5412 uint32_t tmp; 5413 int i; 5414 uint64_t addr; 5415 5416 /* Trigger an invalidation of the L1 instruction caches */ 5417 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5418 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5419 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5420 5421 /* Wait for invalidation complete */ 5422 for (i = 0; i < usec_timeout; i++) { 5423 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5424 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5425 INVALIDATE_CACHE_COMPLETE)) 5426 break; 5427 udelay(1); 5428 } 5429 5430 if (i >= usec_timeout) { 5431 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5432 return -EINVAL; 5433 } 5434 5435 /* Program me ucode address into intruction cache address register */ 5436 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5437 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5438 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5439 lower_32_bits(addr) & 0xFFFFF000); 5440 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5441 upper_32_bits(addr)); 5442 5443 return 0; 5444 } 5445 5446 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5447 { 5448 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5449 uint32_t tmp; 5450 int i; 5451 uint64_t addr; 5452 5453 /* Trigger an invalidation of the L1 instruction caches */ 5454 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5455 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5456 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5457 5458 /* Wait for invalidation complete */ 5459 for (i = 0; i < usec_timeout; i++) { 5460 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5461 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5462 INVALIDATE_CACHE_COMPLETE)) 5463 break; 5464 udelay(1); 5465 } 5466 5467 if (i >= usec_timeout) { 5468 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5469 return -EINVAL; 5470 } 5471 5472 /* Program ce ucode address into intruction cache address register */ 5473 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5474 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5475 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5476 lower_32_bits(addr) & 0xFFFFF000); 5477 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5478 upper_32_bits(addr)); 5479 5480 return 0; 5481 } 5482 5483 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5484 { 5485 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5486 uint32_t tmp; 5487 int i; 5488 uint64_t addr; 5489 5490 /* Trigger an invalidation of the L1 instruction caches */ 5491 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5492 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5493 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5494 5495 /* Wait for invalidation complete */ 5496 for (i = 0; i < usec_timeout; i++) { 5497 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5498 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5499 INVALIDATE_CACHE_COMPLETE)) 5500 break; 5501 udelay(1); 5502 } 5503 5504 if (i >= usec_timeout) { 5505 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5506 return -EINVAL; 5507 } 5508 5509 /* Program pfp ucode address into intruction cache address register */ 5510 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5511 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5512 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5513 lower_32_bits(addr) & 0xFFFFF000); 5514 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5515 upper_32_bits(addr)); 5516 5517 return 0; 5518 } 5519 5520 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5521 { 5522 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5523 uint32_t tmp; 5524 int i; 5525 uint64_t addr; 5526 5527 /* Trigger an invalidation of the L1 instruction caches */ 5528 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5529 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5530 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5531 5532 /* Wait for invalidation complete */ 5533 for (i = 0; i < usec_timeout; i++) { 5534 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5535 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5536 INVALIDATE_CACHE_COMPLETE)) 5537 break; 5538 udelay(1); 5539 } 5540 5541 if (i >= usec_timeout) { 5542 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5543 return -EINVAL; 5544 } 5545 5546 /* Program mec1 ucode address into intruction cache address register */ 5547 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5548 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5549 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5550 lower_32_bits(addr) & 0xFFFFF000); 5551 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5552 upper_32_bits(addr)); 5553 5554 return 0; 5555 } 5556 5557 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5558 { 5559 uint32_t cp_status; 5560 uint32_t bootload_status; 5561 int i, r; 5562 5563 for (i = 0; i < adev->usec_timeout; i++) { 5564 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5565 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5566 if ((cp_status == 0) && 5567 (REG_GET_FIELD(bootload_status, 5568 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5569 break; 5570 } 5571 udelay(1); 5572 } 5573 5574 if (i >= adev->usec_timeout) { 5575 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5576 return -ETIMEDOUT; 5577 } 5578 5579 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5580 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5581 if (r) 5582 return r; 5583 5584 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5585 if (r) 5586 return r; 5587 5588 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5589 if (r) 5590 return r; 5591 5592 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5593 if (r) 5594 return r; 5595 } 5596 5597 return 0; 5598 } 5599 5600 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5601 { 5602 int i; 5603 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5604 5605 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5606 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5607 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5608 5609 if (adev->asic_type == CHIP_NAVI12) { 5610 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5611 } else { 5612 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5613 } 5614 5615 for (i = 0; i < adev->usec_timeout; i++) { 5616 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5617 break; 5618 udelay(1); 5619 } 5620 5621 if (i >= adev->usec_timeout) 5622 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5623 5624 return 0; 5625 } 5626 5627 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5628 { 5629 int r; 5630 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5631 const __le32 *fw_data; 5632 unsigned i, fw_size; 5633 uint32_t tmp; 5634 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5635 5636 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5637 adev->gfx.pfp_fw->data; 5638 5639 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5640 5641 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5642 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5643 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5644 5645 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5646 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5647 &adev->gfx.pfp.pfp_fw_obj, 5648 &adev->gfx.pfp.pfp_fw_gpu_addr, 5649 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5650 if (r) { 5651 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5652 gfx_v10_0_pfp_fini(adev); 5653 return r; 5654 } 5655 5656 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5657 5658 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5659 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5660 5661 /* Trigger an invalidation of the L1 instruction caches */ 5662 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5663 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5664 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5665 5666 /* Wait for invalidation complete */ 5667 for (i = 0; i < usec_timeout; i++) { 5668 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5669 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5670 INVALIDATE_CACHE_COMPLETE)) 5671 break; 5672 udelay(1); 5673 } 5674 5675 if (i >= usec_timeout) { 5676 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5677 return -EINVAL; 5678 } 5679 5680 if (amdgpu_emu_mode == 1) 5681 adev->nbio.funcs->hdp_flush(adev, NULL); 5682 5683 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5684 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5685 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5686 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5687 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5688 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5689 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5690 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5691 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5692 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5693 5694 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5695 5696 for (i = 0; i < pfp_hdr->jt_size; i++) 5697 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5698 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5699 5700 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5701 5702 return 0; 5703 } 5704 5705 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5706 { 5707 int r; 5708 const struct gfx_firmware_header_v1_0 *ce_hdr; 5709 const __le32 *fw_data; 5710 unsigned i, fw_size; 5711 uint32_t tmp; 5712 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5713 5714 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5715 adev->gfx.ce_fw->data; 5716 5717 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5718 5719 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5720 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5721 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5722 5723 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5724 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5725 &adev->gfx.ce.ce_fw_obj, 5726 &adev->gfx.ce.ce_fw_gpu_addr, 5727 (void **)&adev->gfx.ce.ce_fw_ptr); 5728 if (r) { 5729 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5730 gfx_v10_0_ce_fini(adev); 5731 return r; 5732 } 5733 5734 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5735 5736 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5737 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5738 5739 /* Trigger an invalidation of the L1 instruction caches */ 5740 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5741 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5742 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5743 5744 /* Wait for invalidation complete */ 5745 for (i = 0; i < usec_timeout; i++) { 5746 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5747 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5748 INVALIDATE_CACHE_COMPLETE)) 5749 break; 5750 udelay(1); 5751 } 5752 5753 if (i >= usec_timeout) { 5754 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5755 return -EINVAL; 5756 } 5757 5758 if (amdgpu_emu_mode == 1) 5759 adev->nbio.funcs->hdp_flush(adev, NULL); 5760 5761 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5762 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5763 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5764 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5765 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5766 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5767 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5768 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5769 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5770 5771 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5772 5773 for (i = 0; i < ce_hdr->jt_size; i++) 5774 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5775 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5776 5777 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5778 5779 return 0; 5780 } 5781 5782 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5783 { 5784 int r; 5785 const struct gfx_firmware_header_v1_0 *me_hdr; 5786 const __le32 *fw_data; 5787 unsigned i, fw_size; 5788 uint32_t tmp; 5789 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5790 5791 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5792 adev->gfx.me_fw->data; 5793 5794 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5795 5796 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5797 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5798 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5799 5800 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5801 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5802 &adev->gfx.me.me_fw_obj, 5803 &adev->gfx.me.me_fw_gpu_addr, 5804 (void **)&adev->gfx.me.me_fw_ptr); 5805 if (r) { 5806 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5807 gfx_v10_0_me_fini(adev); 5808 return r; 5809 } 5810 5811 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5812 5813 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5814 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5815 5816 /* Trigger an invalidation of the L1 instruction caches */ 5817 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5818 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5819 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5820 5821 /* Wait for invalidation complete */ 5822 for (i = 0; i < usec_timeout; i++) { 5823 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5824 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5825 INVALIDATE_CACHE_COMPLETE)) 5826 break; 5827 udelay(1); 5828 } 5829 5830 if (i >= usec_timeout) { 5831 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5832 return -EINVAL; 5833 } 5834 5835 if (amdgpu_emu_mode == 1) 5836 adev->nbio.funcs->hdp_flush(adev, NULL); 5837 5838 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5839 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5840 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5841 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5842 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5843 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5844 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5845 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5846 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5847 5848 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5849 5850 for (i = 0; i < me_hdr->jt_size; i++) 5851 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5852 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5853 5854 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5855 5856 return 0; 5857 } 5858 5859 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5860 { 5861 int r; 5862 5863 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5864 return -EINVAL; 5865 5866 gfx_v10_0_cp_gfx_enable(adev, false); 5867 5868 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5869 if (r) { 5870 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5871 return r; 5872 } 5873 5874 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5875 if (r) { 5876 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5877 return r; 5878 } 5879 5880 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5881 if (r) { 5882 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5883 return r; 5884 } 5885 5886 return 0; 5887 } 5888 5889 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5890 { 5891 struct amdgpu_ring *ring; 5892 const struct cs_section_def *sect = NULL; 5893 const struct cs_extent_def *ext = NULL; 5894 int r, i; 5895 int ctx_reg_offset; 5896 5897 /* init the CP */ 5898 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5899 adev->gfx.config.max_hw_contexts - 1); 5900 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5901 5902 gfx_v10_0_cp_gfx_enable(adev, true); 5903 5904 ring = &adev->gfx.gfx_ring[0]; 5905 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5906 if (r) { 5907 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5908 return r; 5909 } 5910 5911 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5912 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5913 5914 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5915 amdgpu_ring_write(ring, 0x80000000); 5916 amdgpu_ring_write(ring, 0x80000000); 5917 5918 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5919 for (ext = sect->section; ext->extent != NULL; ++ext) { 5920 if (sect->id == SECT_CONTEXT) { 5921 amdgpu_ring_write(ring, 5922 PACKET3(PACKET3_SET_CONTEXT_REG, 5923 ext->reg_count)); 5924 amdgpu_ring_write(ring, ext->reg_index - 5925 PACKET3_SET_CONTEXT_REG_START); 5926 for (i = 0; i < ext->reg_count; i++) 5927 amdgpu_ring_write(ring, ext->extent[i]); 5928 } 5929 } 5930 } 5931 5932 ctx_reg_offset = 5933 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5934 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5935 amdgpu_ring_write(ring, ctx_reg_offset); 5936 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5937 5938 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5939 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5940 5941 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5942 amdgpu_ring_write(ring, 0); 5943 5944 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 5945 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 5946 amdgpu_ring_write(ring, 0x8000); 5947 amdgpu_ring_write(ring, 0x8000); 5948 5949 amdgpu_ring_commit(ring); 5950 5951 /* submit cs packet to copy state 0 to next available state */ 5952 if (adev->gfx.num_gfx_rings > 1) { 5953 /* maximum supported gfx ring is 2 */ 5954 ring = &adev->gfx.gfx_ring[1]; 5955 r = amdgpu_ring_alloc(ring, 2); 5956 if (r) { 5957 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5958 return r; 5959 } 5960 5961 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5962 amdgpu_ring_write(ring, 0); 5963 5964 amdgpu_ring_commit(ring); 5965 } 5966 return 0; 5967 } 5968 5969 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 5970 CP_PIPE_ID pipe) 5971 { 5972 u32 tmp; 5973 5974 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 5975 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 5976 5977 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 5978 } 5979 5980 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 5981 struct amdgpu_ring *ring) 5982 { 5983 u32 tmp; 5984 5985 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 5986 if (ring->use_doorbell) { 5987 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 5988 DOORBELL_OFFSET, ring->doorbell_index); 5989 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 5990 DOORBELL_EN, 1); 5991 } else { 5992 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 5993 DOORBELL_EN, 0); 5994 } 5995 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 5996 switch (adev->asic_type) { 5997 case CHIP_SIENNA_CICHLID: 5998 case CHIP_NAVY_FLOUNDER: 5999 case CHIP_VANGOGH: 6000 case CHIP_DIMGREY_CAVEFISH: 6001 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6002 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6003 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6004 6005 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6006 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6007 break; 6008 default: 6009 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6010 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6011 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6012 6013 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6014 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6015 break; 6016 } 6017 } 6018 6019 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6020 { 6021 struct amdgpu_ring *ring; 6022 u32 tmp; 6023 u32 rb_bufsz; 6024 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6025 u32 i; 6026 6027 /* Set the write pointer delay */ 6028 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6029 6030 /* set the RB to use vmid 0 */ 6031 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6032 6033 /* Init gfx ring 0 for pipe 0 */ 6034 mutex_lock(&adev->srbm_mutex); 6035 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6036 6037 /* Set ring buffer size */ 6038 ring = &adev->gfx.gfx_ring[0]; 6039 rb_bufsz = order_base_2(ring->ring_size / 8); 6040 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6041 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6042 #ifdef __BIG_ENDIAN 6043 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6044 #endif 6045 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6046 6047 /* Initialize the ring buffer's write pointers */ 6048 ring->wptr = 0; 6049 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6050 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6051 6052 /* set the wb address wether it's enabled or not */ 6053 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6054 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6055 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6056 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6057 6058 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6059 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6060 lower_32_bits(wptr_gpu_addr)); 6061 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6062 upper_32_bits(wptr_gpu_addr)); 6063 6064 mdelay(1); 6065 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6066 6067 rb_addr = ring->gpu_addr >> 8; 6068 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6069 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6070 6071 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6072 6073 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6074 mutex_unlock(&adev->srbm_mutex); 6075 6076 /* Init gfx ring 1 for pipe 1 */ 6077 if (adev->gfx.num_gfx_rings > 1) { 6078 mutex_lock(&adev->srbm_mutex); 6079 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6080 /* maximum supported gfx ring is 2 */ 6081 ring = &adev->gfx.gfx_ring[1]; 6082 rb_bufsz = order_base_2(ring->ring_size / 8); 6083 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6084 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6085 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6086 /* Initialize the ring buffer's write pointers */ 6087 ring->wptr = 0; 6088 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6089 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6090 /* Set the wb address wether it's enabled or not */ 6091 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6092 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6093 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6094 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6095 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6096 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6097 lower_32_bits(wptr_gpu_addr)); 6098 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6099 upper_32_bits(wptr_gpu_addr)); 6100 6101 mdelay(1); 6102 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6103 6104 rb_addr = ring->gpu_addr >> 8; 6105 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6106 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6107 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6108 6109 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6110 mutex_unlock(&adev->srbm_mutex); 6111 } 6112 /* Switch to pipe 0 */ 6113 mutex_lock(&adev->srbm_mutex); 6114 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6115 mutex_unlock(&adev->srbm_mutex); 6116 6117 /* start the ring */ 6118 gfx_v10_0_cp_gfx_start(adev); 6119 6120 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6121 ring = &adev->gfx.gfx_ring[i]; 6122 ring->sched.ready = true; 6123 } 6124 6125 return 0; 6126 } 6127 6128 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6129 { 6130 if (enable) { 6131 switch (adev->asic_type) { 6132 case CHIP_SIENNA_CICHLID: 6133 case CHIP_NAVY_FLOUNDER: 6134 case CHIP_VANGOGH: 6135 case CHIP_DIMGREY_CAVEFISH: 6136 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6137 break; 6138 default: 6139 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6140 break; 6141 } 6142 } else { 6143 switch (adev->asic_type) { 6144 case CHIP_SIENNA_CICHLID: 6145 case CHIP_NAVY_FLOUNDER: 6146 case CHIP_VANGOGH: 6147 case CHIP_DIMGREY_CAVEFISH: 6148 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6149 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6150 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6151 break; 6152 default: 6153 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6154 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6155 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6156 break; 6157 } 6158 adev->gfx.kiq.ring.sched.ready = false; 6159 } 6160 udelay(50); 6161 } 6162 6163 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6164 { 6165 const struct gfx_firmware_header_v1_0 *mec_hdr; 6166 const __le32 *fw_data; 6167 unsigned i; 6168 u32 tmp; 6169 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6170 6171 if (!adev->gfx.mec_fw) 6172 return -EINVAL; 6173 6174 gfx_v10_0_cp_compute_enable(adev, false); 6175 6176 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6177 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6178 6179 fw_data = (const __le32 *) 6180 (adev->gfx.mec_fw->data + 6181 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6182 6183 /* Trigger an invalidation of the L1 instruction caches */ 6184 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6185 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6186 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6187 6188 /* Wait for invalidation complete */ 6189 for (i = 0; i < usec_timeout; i++) { 6190 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6191 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6192 INVALIDATE_CACHE_COMPLETE)) 6193 break; 6194 udelay(1); 6195 } 6196 6197 if (i >= usec_timeout) { 6198 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6199 return -EINVAL; 6200 } 6201 6202 if (amdgpu_emu_mode == 1) 6203 adev->nbio.funcs->hdp_flush(adev, NULL); 6204 6205 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6206 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6207 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6208 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6209 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6210 6211 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6212 0xFFFFF000); 6213 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6214 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6215 6216 /* MEC1 */ 6217 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6218 6219 for (i = 0; i < mec_hdr->jt_size; i++) 6220 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6221 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6222 6223 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6224 6225 /* 6226 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6227 * different microcode than MEC1. 6228 */ 6229 6230 return 0; 6231 } 6232 6233 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6234 { 6235 uint32_t tmp; 6236 struct amdgpu_device *adev = ring->adev; 6237 6238 /* tell RLC which is KIQ queue */ 6239 switch (adev->asic_type) { 6240 case CHIP_SIENNA_CICHLID: 6241 case CHIP_NAVY_FLOUNDER: 6242 case CHIP_VANGOGH: 6243 case CHIP_DIMGREY_CAVEFISH: 6244 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6245 tmp &= 0xffffff00; 6246 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6247 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6248 tmp |= 0x80; 6249 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6250 break; 6251 default: 6252 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6253 tmp &= 0xffffff00; 6254 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6255 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6256 tmp |= 0x80; 6257 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6258 break; 6259 } 6260 } 6261 6262 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6263 { 6264 struct amdgpu_device *adev = ring->adev; 6265 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6266 uint64_t hqd_gpu_addr, wb_gpu_addr; 6267 uint32_t tmp; 6268 uint32_t rb_bufsz; 6269 6270 /* set up gfx hqd wptr */ 6271 mqd->cp_gfx_hqd_wptr = 0; 6272 mqd->cp_gfx_hqd_wptr_hi = 0; 6273 6274 /* set the pointer to the MQD */ 6275 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6276 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6277 6278 /* set up mqd control */ 6279 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6280 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6281 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6282 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6283 mqd->cp_gfx_mqd_control = tmp; 6284 6285 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6286 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6287 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6288 mqd->cp_gfx_hqd_vmid = 0; 6289 6290 /* set up default queue priority level 6291 * 0x0 = low priority, 0x1 = high priority */ 6292 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6293 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6294 mqd->cp_gfx_hqd_queue_priority = tmp; 6295 6296 /* set up time quantum */ 6297 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6298 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6299 mqd->cp_gfx_hqd_quantum = tmp; 6300 6301 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6302 hqd_gpu_addr = ring->gpu_addr >> 8; 6303 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6304 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6305 6306 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6307 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6308 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6309 mqd->cp_gfx_hqd_rptr_addr_hi = 6310 upper_32_bits(wb_gpu_addr) & 0xffff; 6311 6312 /* set up rb_wptr_poll addr */ 6313 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6314 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6315 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6316 6317 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6318 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6319 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6320 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6321 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6322 #ifdef __BIG_ENDIAN 6323 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6324 #endif 6325 mqd->cp_gfx_hqd_cntl = tmp; 6326 6327 /* set up cp_doorbell_control */ 6328 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6329 if (ring->use_doorbell) { 6330 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6331 DOORBELL_OFFSET, ring->doorbell_index); 6332 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6333 DOORBELL_EN, 1); 6334 } else 6335 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6336 DOORBELL_EN, 0); 6337 mqd->cp_rb_doorbell_control = tmp; 6338 6339 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6340 ring->wptr = 0; 6341 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6342 6343 /* active the queue */ 6344 mqd->cp_gfx_hqd_active = 1; 6345 6346 return 0; 6347 } 6348 6349 #ifdef BRING_UP_DEBUG 6350 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6351 { 6352 struct amdgpu_device *adev = ring->adev; 6353 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6354 6355 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6356 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6357 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6358 6359 /* set GFX_MQD_BASE */ 6360 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6361 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6362 6363 /* set GFX_MQD_CONTROL */ 6364 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6365 6366 /* set GFX_HQD_VMID to 0 */ 6367 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6368 6369 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6370 mqd->cp_gfx_hqd_queue_priority); 6371 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6372 6373 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6374 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6375 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6376 6377 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6378 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6379 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6380 6381 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6382 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6383 6384 /* set RB_WPTR_POLL_ADDR */ 6385 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6386 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6387 6388 /* set RB_DOORBELL_CONTROL */ 6389 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6390 6391 /* active the queue */ 6392 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6393 6394 return 0; 6395 } 6396 #endif 6397 6398 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6399 { 6400 struct amdgpu_device *adev = ring->adev; 6401 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6402 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6403 6404 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6405 memset((void *)mqd, 0, sizeof(*mqd)); 6406 mutex_lock(&adev->srbm_mutex); 6407 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6408 gfx_v10_0_gfx_mqd_init(ring); 6409 #ifdef BRING_UP_DEBUG 6410 gfx_v10_0_gfx_queue_init_register(ring); 6411 #endif 6412 nv_grbm_select(adev, 0, 0, 0, 0); 6413 mutex_unlock(&adev->srbm_mutex); 6414 if (adev->gfx.me.mqd_backup[mqd_idx]) 6415 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6416 } else if (amdgpu_in_reset(adev)) { 6417 /* reset mqd with the backup copy */ 6418 if (adev->gfx.me.mqd_backup[mqd_idx]) 6419 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6420 /* reset the ring */ 6421 ring->wptr = 0; 6422 adev->wb.wb[ring->wptr_offs] = 0; 6423 amdgpu_ring_clear_ring(ring); 6424 #ifdef BRING_UP_DEBUG 6425 mutex_lock(&adev->srbm_mutex); 6426 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6427 gfx_v10_0_gfx_queue_init_register(ring); 6428 nv_grbm_select(adev, 0, 0, 0, 0); 6429 mutex_unlock(&adev->srbm_mutex); 6430 #endif 6431 } else { 6432 amdgpu_ring_clear_ring(ring); 6433 } 6434 6435 return 0; 6436 } 6437 6438 #ifndef BRING_UP_DEBUG 6439 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6440 { 6441 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6442 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6443 int r, i; 6444 6445 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6446 return -EINVAL; 6447 6448 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6449 adev->gfx.num_gfx_rings); 6450 if (r) { 6451 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6452 return r; 6453 } 6454 6455 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6456 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6457 6458 return amdgpu_ring_test_helper(kiq_ring); 6459 } 6460 #endif 6461 6462 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6463 { 6464 int r, i; 6465 struct amdgpu_ring *ring; 6466 6467 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6468 ring = &adev->gfx.gfx_ring[i]; 6469 6470 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6471 if (unlikely(r != 0)) 6472 goto done; 6473 6474 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6475 if (!r) { 6476 r = gfx_v10_0_gfx_init_queue(ring); 6477 amdgpu_bo_kunmap(ring->mqd_obj); 6478 ring->mqd_ptr = NULL; 6479 } 6480 amdgpu_bo_unreserve(ring->mqd_obj); 6481 if (r) 6482 goto done; 6483 } 6484 #ifndef BRING_UP_DEBUG 6485 r = gfx_v10_0_kiq_enable_kgq(adev); 6486 if (r) 6487 goto done; 6488 #endif 6489 r = gfx_v10_0_cp_gfx_start(adev); 6490 if (r) 6491 goto done; 6492 6493 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6494 ring = &adev->gfx.gfx_ring[i]; 6495 ring->sched.ready = true; 6496 } 6497 done: 6498 return r; 6499 } 6500 6501 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6502 { 6503 struct amdgpu_device *adev = ring->adev; 6504 6505 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6506 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) { 6507 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6508 mqd->cp_hqd_queue_priority = 6509 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6510 } 6511 } 6512 } 6513 6514 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6515 { 6516 struct amdgpu_device *adev = ring->adev; 6517 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6518 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6519 uint32_t tmp; 6520 6521 mqd->header = 0xC0310800; 6522 mqd->compute_pipelinestat_enable = 0x00000001; 6523 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6524 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6525 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6526 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6527 mqd->compute_misc_reserved = 0x00000003; 6528 6529 eop_base_addr = ring->eop_gpu_addr >> 8; 6530 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6531 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6532 6533 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6534 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6535 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6536 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6537 6538 mqd->cp_hqd_eop_control = tmp; 6539 6540 /* enable doorbell? */ 6541 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6542 6543 if (ring->use_doorbell) { 6544 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6545 DOORBELL_OFFSET, ring->doorbell_index); 6546 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6547 DOORBELL_EN, 1); 6548 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6549 DOORBELL_SOURCE, 0); 6550 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6551 DOORBELL_HIT, 0); 6552 } else { 6553 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6554 DOORBELL_EN, 0); 6555 } 6556 6557 mqd->cp_hqd_pq_doorbell_control = tmp; 6558 6559 /* disable the queue if it's active */ 6560 ring->wptr = 0; 6561 mqd->cp_hqd_dequeue_request = 0; 6562 mqd->cp_hqd_pq_rptr = 0; 6563 mqd->cp_hqd_pq_wptr_lo = 0; 6564 mqd->cp_hqd_pq_wptr_hi = 0; 6565 6566 /* set the pointer to the MQD */ 6567 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6568 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6569 6570 /* set MQD vmid to 0 */ 6571 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6572 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6573 mqd->cp_mqd_control = tmp; 6574 6575 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6576 hqd_gpu_addr = ring->gpu_addr >> 8; 6577 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6578 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6579 6580 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6581 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6582 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6583 (order_base_2(ring->ring_size / 4) - 1)); 6584 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6585 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6586 #ifdef __BIG_ENDIAN 6587 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6588 #endif 6589 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6590 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6591 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6592 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6593 mqd->cp_hqd_pq_control = tmp; 6594 6595 /* set the wb address whether it's enabled or not */ 6596 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6597 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6598 mqd->cp_hqd_pq_rptr_report_addr_hi = 6599 upper_32_bits(wb_gpu_addr) & 0xffff; 6600 6601 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6602 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6603 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6604 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6605 6606 tmp = 0; 6607 /* enable the doorbell if requested */ 6608 if (ring->use_doorbell) { 6609 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6610 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6611 DOORBELL_OFFSET, ring->doorbell_index); 6612 6613 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6614 DOORBELL_EN, 1); 6615 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6616 DOORBELL_SOURCE, 0); 6617 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6618 DOORBELL_HIT, 0); 6619 } 6620 6621 mqd->cp_hqd_pq_doorbell_control = tmp; 6622 6623 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6624 ring->wptr = 0; 6625 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6626 6627 /* set the vmid for the queue */ 6628 mqd->cp_hqd_vmid = 0; 6629 6630 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6631 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6632 mqd->cp_hqd_persistent_state = tmp; 6633 6634 /* set MIN_IB_AVAIL_SIZE */ 6635 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6636 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6637 mqd->cp_hqd_ib_control = tmp; 6638 6639 /* set static priority for a compute queue/ring */ 6640 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6641 6642 /* map_queues packet doesn't need activate the queue, 6643 * so only kiq need set this field. 6644 */ 6645 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6646 mqd->cp_hqd_active = 1; 6647 6648 return 0; 6649 } 6650 6651 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6652 { 6653 struct amdgpu_device *adev = ring->adev; 6654 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6655 int j; 6656 6657 /* inactivate the queue */ 6658 if (amdgpu_sriov_vf(adev)) 6659 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6660 6661 /* disable wptr polling */ 6662 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6663 6664 /* write the EOP addr */ 6665 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6666 mqd->cp_hqd_eop_base_addr_lo); 6667 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6668 mqd->cp_hqd_eop_base_addr_hi); 6669 6670 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6671 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6672 mqd->cp_hqd_eop_control); 6673 6674 /* enable doorbell? */ 6675 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6676 mqd->cp_hqd_pq_doorbell_control); 6677 6678 /* disable the queue if it's active */ 6679 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6680 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6681 for (j = 0; j < adev->usec_timeout; j++) { 6682 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6683 break; 6684 udelay(1); 6685 } 6686 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6687 mqd->cp_hqd_dequeue_request); 6688 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6689 mqd->cp_hqd_pq_rptr); 6690 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6691 mqd->cp_hqd_pq_wptr_lo); 6692 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6693 mqd->cp_hqd_pq_wptr_hi); 6694 } 6695 6696 /* set the pointer to the MQD */ 6697 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6698 mqd->cp_mqd_base_addr_lo); 6699 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6700 mqd->cp_mqd_base_addr_hi); 6701 6702 /* set MQD vmid to 0 */ 6703 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6704 mqd->cp_mqd_control); 6705 6706 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6707 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6708 mqd->cp_hqd_pq_base_lo); 6709 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6710 mqd->cp_hqd_pq_base_hi); 6711 6712 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6713 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6714 mqd->cp_hqd_pq_control); 6715 6716 /* set the wb address whether it's enabled or not */ 6717 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6718 mqd->cp_hqd_pq_rptr_report_addr_lo); 6719 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6720 mqd->cp_hqd_pq_rptr_report_addr_hi); 6721 6722 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6723 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6724 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6725 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6726 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6727 6728 /* enable the doorbell if requested */ 6729 if (ring->use_doorbell) { 6730 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6731 (adev->doorbell_index.kiq * 2) << 2); 6732 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6733 (adev->doorbell_index.userqueue_end * 2) << 2); 6734 } 6735 6736 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6737 mqd->cp_hqd_pq_doorbell_control); 6738 6739 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6740 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6741 mqd->cp_hqd_pq_wptr_lo); 6742 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6743 mqd->cp_hqd_pq_wptr_hi); 6744 6745 /* set the vmid for the queue */ 6746 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6747 6748 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6749 mqd->cp_hqd_persistent_state); 6750 6751 /* activate the queue */ 6752 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6753 mqd->cp_hqd_active); 6754 6755 if (ring->use_doorbell) 6756 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6757 6758 return 0; 6759 } 6760 6761 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6762 { 6763 struct amdgpu_device *adev = ring->adev; 6764 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6765 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6766 6767 gfx_v10_0_kiq_setting(ring); 6768 6769 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6770 /* reset MQD to a clean status */ 6771 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6772 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6773 6774 /* reset ring buffer */ 6775 ring->wptr = 0; 6776 amdgpu_ring_clear_ring(ring); 6777 6778 mutex_lock(&adev->srbm_mutex); 6779 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6780 gfx_v10_0_kiq_init_register(ring); 6781 nv_grbm_select(adev, 0, 0, 0, 0); 6782 mutex_unlock(&adev->srbm_mutex); 6783 } else { 6784 memset((void *)mqd, 0, sizeof(*mqd)); 6785 mutex_lock(&adev->srbm_mutex); 6786 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6787 gfx_v10_0_compute_mqd_init(ring); 6788 gfx_v10_0_kiq_init_register(ring); 6789 nv_grbm_select(adev, 0, 0, 0, 0); 6790 mutex_unlock(&adev->srbm_mutex); 6791 6792 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6793 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6794 } 6795 6796 return 0; 6797 } 6798 6799 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6800 { 6801 struct amdgpu_device *adev = ring->adev; 6802 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6803 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6804 6805 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6806 memset((void *)mqd, 0, sizeof(*mqd)); 6807 mutex_lock(&adev->srbm_mutex); 6808 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6809 gfx_v10_0_compute_mqd_init(ring); 6810 nv_grbm_select(adev, 0, 0, 0, 0); 6811 mutex_unlock(&adev->srbm_mutex); 6812 6813 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6814 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6815 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6816 /* reset MQD to a clean status */ 6817 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6818 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6819 6820 /* reset ring buffer */ 6821 ring->wptr = 0; 6822 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 6823 amdgpu_ring_clear_ring(ring); 6824 } else { 6825 amdgpu_ring_clear_ring(ring); 6826 } 6827 6828 return 0; 6829 } 6830 6831 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6832 { 6833 struct amdgpu_ring *ring; 6834 int r; 6835 6836 ring = &adev->gfx.kiq.ring; 6837 6838 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6839 if (unlikely(r != 0)) 6840 return r; 6841 6842 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6843 if (unlikely(r != 0)) 6844 return r; 6845 6846 gfx_v10_0_kiq_init_queue(ring); 6847 amdgpu_bo_kunmap(ring->mqd_obj); 6848 ring->mqd_ptr = NULL; 6849 amdgpu_bo_unreserve(ring->mqd_obj); 6850 ring->sched.ready = true; 6851 return 0; 6852 } 6853 6854 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6855 { 6856 struct amdgpu_ring *ring = NULL; 6857 int r = 0, i; 6858 6859 gfx_v10_0_cp_compute_enable(adev, true); 6860 6861 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6862 ring = &adev->gfx.compute_ring[i]; 6863 6864 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6865 if (unlikely(r != 0)) 6866 goto done; 6867 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6868 if (!r) { 6869 r = gfx_v10_0_kcq_init_queue(ring); 6870 amdgpu_bo_kunmap(ring->mqd_obj); 6871 ring->mqd_ptr = NULL; 6872 } 6873 amdgpu_bo_unreserve(ring->mqd_obj); 6874 if (r) 6875 goto done; 6876 } 6877 6878 r = amdgpu_gfx_enable_kcq(adev); 6879 done: 6880 return r; 6881 } 6882 6883 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6884 { 6885 int r, i; 6886 struct amdgpu_ring *ring; 6887 6888 if (!(adev->flags & AMD_IS_APU)) 6889 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6890 6891 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6892 /* legacy firmware loading */ 6893 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6894 if (r) 6895 return r; 6896 6897 r = gfx_v10_0_cp_compute_load_microcode(adev); 6898 if (r) 6899 return r; 6900 } 6901 6902 r = gfx_v10_0_kiq_resume(adev); 6903 if (r) 6904 return r; 6905 6906 r = gfx_v10_0_kcq_resume(adev); 6907 if (r) 6908 return r; 6909 6910 if (!amdgpu_async_gfx_ring) { 6911 r = gfx_v10_0_cp_gfx_resume(adev); 6912 if (r) 6913 return r; 6914 } else { 6915 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6916 if (r) 6917 return r; 6918 } 6919 6920 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6921 ring = &adev->gfx.gfx_ring[i]; 6922 r = amdgpu_ring_test_helper(ring); 6923 if (r) 6924 return r; 6925 } 6926 6927 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6928 ring = &adev->gfx.compute_ring[i]; 6929 r = amdgpu_ring_test_helper(ring); 6930 if (r) 6931 return r; 6932 } 6933 6934 return 0; 6935 } 6936 6937 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6938 { 6939 gfx_v10_0_cp_gfx_enable(adev, enable); 6940 gfx_v10_0_cp_compute_enable(adev, enable); 6941 } 6942 6943 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6944 { 6945 uint32_t data, pattern = 0xDEADBEEF; 6946 6947 /* check if mmVGT_ESGS_RING_SIZE_UMD 6948 * has been remapped to mmVGT_ESGS_RING_SIZE */ 6949 switch (adev->asic_type) { 6950 case CHIP_SIENNA_CICHLID: 6951 case CHIP_NAVY_FLOUNDER: 6952 case CHIP_DIMGREY_CAVEFISH: 6953 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6954 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6955 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6956 6957 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6958 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 6959 return true; 6960 } else { 6961 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6962 return false; 6963 } 6964 break; 6965 case CHIP_VANGOGH: 6966 return true; 6967 default: 6968 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6969 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 6970 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6971 6972 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 6973 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6974 return true; 6975 } else { 6976 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 6977 return false; 6978 } 6979 break; 6980 } 6981 } 6982 6983 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 6984 { 6985 uint32_t data; 6986 6987 /* initialize cam_index to 0 6988 * index will auto-inc after each data writting */ 6989 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 6990 6991 switch (adev->asic_type) { 6992 case CHIP_SIENNA_CICHLID: 6993 case CHIP_NAVY_FLOUNDER: 6994 case CHIP_VANGOGH: 6995 case CHIP_DIMGREY_CAVEFISH: 6996 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 6997 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 6998 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6999 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7000 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7001 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7002 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7003 7004 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7005 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7006 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7007 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7008 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7009 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7010 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7011 7012 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7013 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7014 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7015 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7016 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7017 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7018 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7019 7020 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7021 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7022 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7023 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7024 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7025 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7026 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7027 7028 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7029 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7030 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7031 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7032 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7033 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7034 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7035 7036 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7037 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7038 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7039 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7040 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7041 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7042 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7043 7044 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7045 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7046 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7047 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7048 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7049 break; 7050 default: 7051 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7052 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7053 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7054 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7055 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7056 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7057 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7058 7059 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7060 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7061 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7062 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7063 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7064 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7065 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7066 7067 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7068 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7069 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7070 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7071 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7072 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7073 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7074 7075 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7076 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7077 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7078 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7079 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7080 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7081 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7082 7083 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7084 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7085 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7086 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7087 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7088 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7089 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7090 7091 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7092 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7093 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7094 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7095 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7096 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7097 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7098 7099 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7100 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7101 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7102 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7103 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7104 break; 7105 } 7106 7107 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7108 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7109 } 7110 7111 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7112 { 7113 uint32_t data; 7114 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7115 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7116 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7117 7118 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7119 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7120 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7121 } 7122 7123 static int gfx_v10_0_hw_init(void *handle) 7124 { 7125 int r; 7126 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7127 7128 if (!amdgpu_emu_mode) 7129 gfx_v10_0_init_golden_registers(adev); 7130 7131 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7132 /** 7133 * For gfx 10, rlc firmware loading relies on smu firmware is 7134 * loaded firstly, so in direct type, it has to load smc ucode 7135 * here before rlc. 7136 */ 7137 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) { 7138 r = smu_load_microcode(&adev->smu); 7139 if (r) 7140 return r; 7141 7142 r = smu_check_fw_status(&adev->smu); 7143 if (r) { 7144 pr_err("SMC firmware status is not correct\n"); 7145 return r; 7146 } 7147 } 7148 gfx_v10_0_disable_gpa_mode(adev); 7149 } 7150 7151 /* if GRBM CAM not remapped, set up the remapping */ 7152 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7153 gfx_v10_0_setup_grbm_cam_remapping(adev); 7154 7155 gfx_v10_0_constants_init(adev); 7156 7157 r = gfx_v10_0_rlc_resume(adev); 7158 if (r) 7159 return r; 7160 7161 /* 7162 * init golden registers and rlc resume may override some registers, 7163 * reconfig them here 7164 */ 7165 gfx_v10_0_tcp_harvest(adev); 7166 7167 r = gfx_v10_0_cp_resume(adev); 7168 if (r) 7169 return r; 7170 7171 if (adev->asic_type == CHIP_SIENNA_CICHLID) 7172 gfx_v10_3_program_pbb_mode(adev); 7173 7174 return r; 7175 } 7176 7177 #ifndef BRING_UP_DEBUG 7178 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7179 { 7180 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7181 struct amdgpu_ring *kiq_ring = &kiq->ring; 7182 int i; 7183 7184 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7185 return -EINVAL; 7186 7187 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7188 adev->gfx.num_gfx_rings)) 7189 return -ENOMEM; 7190 7191 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7192 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7193 PREEMPT_QUEUES, 0, 0); 7194 7195 return amdgpu_ring_test_helper(kiq_ring); 7196 } 7197 #endif 7198 7199 static int gfx_v10_0_hw_fini(void *handle) 7200 { 7201 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7202 int r; 7203 uint32_t tmp; 7204 7205 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7206 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7207 7208 if (!adev->in_pci_err_recovery) { 7209 #ifndef BRING_UP_DEBUG 7210 if (amdgpu_async_gfx_ring) { 7211 r = gfx_v10_0_kiq_disable_kgq(adev); 7212 if (r) 7213 DRM_ERROR("KGQ disable failed\n"); 7214 } 7215 #endif 7216 if (amdgpu_gfx_disable_kcq(adev)) 7217 DRM_ERROR("KCQ disable failed\n"); 7218 } 7219 7220 if (amdgpu_sriov_vf(adev)) { 7221 gfx_v10_0_cp_gfx_enable(adev, false); 7222 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7223 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7224 tmp &= 0xffffff00; 7225 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7226 7227 return 0; 7228 } 7229 gfx_v10_0_cp_enable(adev, false); 7230 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7231 7232 return 0; 7233 } 7234 7235 static int gfx_v10_0_suspend(void *handle) 7236 { 7237 return gfx_v10_0_hw_fini(handle); 7238 } 7239 7240 static int gfx_v10_0_resume(void *handle) 7241 { 7242 return gfx_v10_0_hw_init(handle); 7243 } 7244 7245 static bool gfx_v10_0_is_idle(void *handle) 7246 { 7247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7248 7249 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7250 GRBM_STATUS, GUI_ACTIVE)) 7251 return false; 7252 else 7253 return true; 7254 } 7255 7256 static int gfx_v10_0_wait_for_idle(void *handle) 7257 { 7258 unsigned i; 7259 u32 tmp; 7260 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7261 7262 for (i = 0; i < adev->usec_timeout; i++) { 7263 /* read MC_STATUS */ 7264 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7265 GRBM_STATUS__GUI_ACTIVE_MASK; 7266 7267 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7268 return 0; 7269 udelay(1); 7270 } 7271 return -ETIMEDOUT; 7272 } 7273 7274 static int gfx_v10_0_soft_reset(void *handle) 7275 { 7276 u32 grbm_soft_reset = 0; 7277 u32 tmp; 7278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7279 7280 /* GRBM_STATUS */ 7281 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7282 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7283 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7284 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7285 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7286 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7287 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7288 GRBM_SOFT_RESET, SOFT_RESET_CP, 7289 1); 7290 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7291 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7292 1); 7293 } 7294 7295 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7296 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7297 GRBM_SOFT_RESET, SOFT_RESET_CP, 7298 1); 7299 } 7300 7301 /* GRBM_STATUS2 */ 7302 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7303 switch (adev->asic_type) { 7304 case CHIP_SIENNA_CICHLID: 7305 case CHIP_NAVY_FLOUNDER: 7306 case CHIP_VANGOGH: 7307 case CHIP_DIMGREY_CAVEFISH: 7308 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7309 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7310 GRBM_SOFT_RESET, 7311 SOFT_RESET_RLC, 7312 1); 7313 break; 7314 default: 7315 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7316 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7317 GRBM_SOFT_RESET, 7318 SOFT_RESET_RLC, 7319 1); 7320 break; 7321 } 7322 7323 if (grbm_soft_reset) { 7324 /* stop the rlc */ 7325 gfx_v10_0_rlc_stop(adev); 7326 7327 /* Disable GFX parsing/prefetching */ 7328 gfx_v10_0_cp_gfx_enable(adev, false); 7329 7330 /* Disable MEC parsing/prefetching */ 7331 gfx_v10_0_cp_compute_enable(adev, false); 7332 7333 if (grbm_soft_reset) { 7334 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7335 tmp |= grbm_soft_reset; 7336 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7337 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7338 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7339 7340 udelay(50); 7341 7342 tmp &= ~grbm_soft_reset; 7343 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7344 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7345 } 7346 7347 /* Wait a little for things to settle down */ 7348 udelay(50); 7349 } 7350 return 0; 7351 } 7352 7353 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7354 { 7355 uint64_t clock; 7356 7357 amdgpu_gfx_off_ctrl(adev, false); 7358 mutex_lock(&adev->gfx.gpu_clock_mutex); 7359 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 7360 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 7361 mutex_unlock(&adev->gfx.gpu_clock_mutex); 7362 amdgpu_gfx_off_ctrl(adev, true); 7363 return clock; 7364 } 7365 7366 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7367 uint32_t vmid, 7368 uint32_t gds_base, uint32_t gds_size, 7369 uint32_t gws_base, uint32_t gws_size, 7370 uint32_t oa_base, uint32_t oa_size) 7371 { 7372 struct amdgpu_device *adev = ring->adev; 7373 7374 /* GDS Base */ 7375 gfx_v10_0_write_data_to_reg(ring, 0, false, 7376 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7377 gds_base); 7378 7379 /* GDS Size */ 7380 gfx_v10_0_write_data_to_reg(ring, 0, false, 7381 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7382 gds_size); 7383 7384 /* GWS */ 7385 gfx_v10_0_write_data_to_reg(ring, 0, false, 7386 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7387 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7388 7389 /* OA */ 7390 gfx_v10_0_write_data_to_reg(ring, 0, false, 7391 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7392 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7393 } 7394 7395 static int gfx_v10_0_early_init(void *handle) 7396 { 7397 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7398 7399 switch (adev->asic_type) { 7400 case CHIP_NAVI10: 7401 case CHIP_NAVI14: 7402 case CHIP_NAVI12: 7403 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7404 break; 7405 case CHIP_SIENNA_CICHLID: 7406 case CHIP_NAVY_FLOUNDER: 7407 case CHIP_VANGOGH: 7408 case CHIP_DIMGREY_CAVEFISH: 7409 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7410 break; 7411 default: 7412 break; 7413 } 7414 7415 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7416 AMDGPU_MAX_COMPUTE_RINGS); 7417 7418 gfx_v10_0_set_kiq_pm4_funcs(adev); 7419 gfx_v10_0_set_ring_funcs(adev); 7420 gfx_v10_0_set_irq_funcs(adev); 7421 gfx_v10_0_set_gds_init(adev); 7422 gfx_v10_0_set_rlc_funcs(adev); 7423 7424 return 0; 7425 } 7426 7427 static int gfx_v10_0_late_init(void *handle) 7428 { 7429 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7430 int r; 7431 7432 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7433 if (r) 7434 return r; 7435 7436 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7437 if (r) 7438 return r; 7439 7440 return 0; 7441 } 7442 7443 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7444 { 7445 uint32_t rlc_cntl; 7446 7447 /* if RLC is not enabled, do nothing */ 7448 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7449 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7450 } 7451 7452 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7453 { 7454 uint32_t data; 7455 unsigned i; 7456 7457 data = RLC_SAFE_MODE__CMD_MASK; 7458 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7459 7460 switch (adev->asic_type) { 7461 case CHIP_SIENNA_CICHLID: 7462 case CHIP_NAVY_FLOUNDER: 7463 case CHIP_VANGOGH: 7464 case CHIP_DIMGREY_CAVEFISH: 7465 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7466 7467 /* wait for RLC_SAFE_MODE */ 7468 for (i = 0; i < adev->usec_timeout; i++) { 7469 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7470 RLC_SAFE_MODE, CMD)) 7471 break; 7472 udelay(1); 7473 } 7474 break; 7475 default: 7476 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7477 7478 /* wait for RLC_SAFE_MODE */ 7479 for (i = 0; i < adev->usec_timeout; i++) { 7480 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7481 RLC_SAFE_MODE, CMD)) 7482 break; 7483 udelay(1); 7484 } 7485 break; 7486 } 7487 } 7488 7489 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7490 { 7491 uint32_t data; 7492 7493 data = RLC_SAFE_MODE__CMD_MASK; 7494 switch (adev->asic_type) { 7495 case CHIP_SIENNA_CICHLID: 7496 case CHIP_NAVY_FLOUNDER: 7497 case CHIP_VANGOGH: 7498 case CHIP_DIMGREY_CAVEFISH: 7499 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7500 break; 7501 default: 7502 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7503 break; 7504 } 7505 } 7506 7507 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7508 bool enable) 7509 { 7510 uint32_t data, def; 7511 7512 /* It is disabled by HW by default */ 7513 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7514 /* 0 - Disable some blocks' MGCG */ 7515 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7516 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7517 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7518 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7519 7520 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7521 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7522 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7523 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7524 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7525 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7526 7527 if (def != data) 7528 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7529 7530 /* MGLS is a global flag to control all MGLS in GFX */ 7531 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7532 /* 2 - RLC memory Light sleep */ 7533 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7534 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7535 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7536 if (def != data) 7537 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7538 } 7539 /* 3 - CP memory Light sleep */ 7540 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7541 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7542 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7543 if (def != data) 7544 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7545 } 7546 } 7547 } else { 7548 /* 1 - MGCG_OVERRIDE */ 7549 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7550 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7551 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7552 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7553 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 7554 if (def != data) 7555 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7556 7557 /* 2 - disable MGLS in CP */ 7558 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7559 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7560 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7561 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7562 } 7563 7564 /* 3 - disable MGLS in RLC */ 7565 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7566 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7567 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7568 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7569 } 7570 7571 } 7572 } 7573 7574 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7575 bool enable) 7576 { 7577 uint32_t data, def; 7578 7579 /* Enable 3D CGCG/CGLS */ 7580 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 7581 /* write cmd to clear cgcg/cgls ov */ 7582 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7583 /* unset CGCG override */ 7584 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7585 /* update CGCG and CGLS override bits */ 7586 if (def != data) 7587 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7588 /* enable 3Dcgcg FSM(0x0000363f) */ 7589 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7590 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7591 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7592 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7593 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7594 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7595 if (def != data) 7596 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7597 7598 /* set IDLE_POLL_COUNT(0x00900100) */ 7599 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7600 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7601 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7602 if (def != data) 7603 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7604 } else { 7605 /* Disable CGCG/CGLS */ 7606 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7607 /* disable cgcg, cgls should be disabled */ 7608 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 7609 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 7610 /* disable cgcg and cgls in FSM */ 7611 if (def != data) 7612 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7613 } 7614 } 7615 7616 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7617 bool enable) 7618 { 7619 uint32_t def, data; 7620 7621 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 7622 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7623 /* unset CGCG override */ 7624 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7625 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7626 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7627 else 7628 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7629 /* update CGCG and CGLS override bits */ 7630 if (def != data) 7631 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7632 7633 /* enable cgcg FSM(0x0000363F) */ 7634 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7635 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7636 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7637 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7638 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7639 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7640 if (def != data) 7641 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7642 7643 /* set IDLE_POLL_COUNT(0x00900100) */ 7644 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7645 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7646 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7647 if (def != data) 7648 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7649 } else { 7650 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7651 /* reset CGCG/CGLS bits */ 7652 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 7653 /* disable cgcg and cgls in FSM */ 7654 if (def != data) 7655 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7656 } 7657 } 7658 7659 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7660 bool enable) 7661 { 7662 amdgpu_gfx_rlc_enter_safe_mode(adev); 7663 7664 if (enable) { 7665 /* CGCG/CGLS should be enabled after MGCG/MGLS 7666 * === MGCG + MGLS === 7667 */ 7668 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7669 /* === CGCG /CGLS for GFX 3D Only === */ 7670 gfx_v10_0_update_3d_clock_gating(adev, enable); 7671 /* === CGCG + CGLS === */ 7672 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7673 } else { 7674 /* CGCG/CGLS should be disabled before MGCG/MGLS 7675 * === CGCG + CGLS === 7676 */ 7677 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7678 /* === CGCG /CGLS for GFX 3D Only === */ 7679 gfx_v10_0_update_3d_clock_gating(adev, enable); 7680 /* === MGCG + MGLS === */ 7681 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7682 } 7683 7684 if (adev->cg_flags & 7685 (AMD_CG_SUPPORT_GFX_MGCG | 7686 AMD_CG_SUPPORT_GFX_CGLS | 7687 AMD_CG_SUPPORT_GFX_CGCG | 7688 AMD_CG_SUPPORT_GFX_3D_CGCG | 7689 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7690 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7691 7692 amdgpu_gfx_rlc_exit_safe_mode(adev); 7693 7694 return 0; 7695 } 7696 7697 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 7698 { 7699 u32 reg, data; 7700 7701 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7702 if (amdgpu_sriov_is_pp_one_vf(adev)) 7703 data = RREG32_NO_KIQ(reg); 7704 else 7705 data = RREG32(reg); 7706 7707 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7708 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7709 7710 if (amdgpu_sriov_is_pp_one_vf(adev)) 7711 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7712 else 7713 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7714 } 7715 7716 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7717 uint32_t offset, 7718 struct soc15_reg_rlcg *entries, int arr_size) 7719 { 7720 int i; 7721 uint32_t reg; 7722 7723 if (!entries) 7724 return false; 7725 7726 for (i = 0; i < arr_size; i++) { 7727 const struct soc15_reg_rlcg *entry; 7728 7729 entry = &entries[i]; 7730 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7731 if (offset == reg) 7732 return true; 7733 } 7734 7735 return false; 7736 } 7737 7738 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7739 { 7740 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7741 } 7742 7743 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7744 { 7745 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7746 7747 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7748 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7749 else 7750 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7751 7752 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7753 } 7754 7755 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7756 { 7757 amdgpu_gfx_rlc_enter_safe_mode(adev); 7758 7759 gfx_v10_cntl_power_gating(adev, enable); 7760 7761 amdgpu_gfx_rlc_exit_safe_mode(adev); 7762 } 7763 7764 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 7765 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7766 .set_safe_mode = gfx_v10_0_set_safe_mode, 7767 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7768 .init = gfx_v10_0_rlc_init, 7769 .get_csb_size = gfx_v10_0_get_csb_size, 7770 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7771 .resume = gfx_v10_0_rlc_resume, 7772 .stop = gfx_v10_0_rlc_stop, 7773 .reset = gfx_v10_0_rlc_reset, 7774 .start = gfx_v10_0_rlc_start, 7775 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7776 }; 7777 7778 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 7779 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7780 .set_safe_mode = gfx_v10_0_set_safe_mode, 7781 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7782 .init = gfx_v10_0_rlc_init, 7783 .get_csb_size = gfx_v10_0_get_csb_size, 7784 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7785 .resume = gfx_v10_0_rlc_resume, 7786 .stop = gfx_v10_0_rlc_stop, 7787 .reset = gfx_v10_0_rlc_reset, 7788 .start = gfx_v10_0_rlc_start, 7789 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7790 .rlcg_wreg = gfx_v10_rlcg_wreg, 7791 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 7792 }; 7793 7794 static int gfx_v10_0_set_powergating_state(void *handle, 7795 enum amd_powergating_state state) 7796 { 7797 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7798 bool enable = (state == AMD_PG_STATE_GATE); 7799 7800 if (amdgpu_sriov_vf(adev)) 7801 return 0; 7802 7803 switch (adev->asic_type) { 7804 case CHIP_NAVI10: 7805 case CHIP_NAVI14: 7806 case CHIP_NAVI12: 7807 case CHIP_SIENNA_CICHLID: 7808 case CHIP_NAVY_FLOUNDER: 7809 amdgpu_gfx_off_ctrl(adev, enable); 7810 break; 7811 case CHIP_VANGOGH: 7812 gfx_v10_cntl_pg(adev, enable); 7813 break; 7814 default: 7815 break; 7816 } 7817 return 0; 7818 } 7819 7820 static int gfx_v10_0_set_clockgating_state(void *handle, 7821 enum amd_clockgating_state state) 7822 { 7823 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7824 7825 if (amdgpu_sriov_vf(adev)) 7826 return 0; 7827 7828 switch (adev->asic_type) { 7829 case CHIP_NAVI10: 7830 case CHIP_NAVI14: 7831 case CHIP_NAVI12: 7832 case CHIP_SIENNA_CICHLID: 7833 case CHIP_NAVY_FLOUNDER: 7834 case CHIP_VANGOGH: 7835 case CHIP_DIMGREY_CAVEFISH: 7836 gfx_v10_0_update_gfx_clock_gating(adev, 7837 state == AMD_CG_STATE_GATE); 7838 break; 7839 default: 7840 break; 7841 } 7842 return 0; 7843 } 7844 7845 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 7846 { 7847 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7848 int data; 7849 7850 /* AMD_CG_SUPPORT_GFX_MGCG */ 7851 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7852 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 7853 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 7854 7855 /* AMD_CG_SUPPORT_GFX_CGCG */ 7856 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 7857 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 7858 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 7859 7860 /* AMD_CG_SUPPORT_GFX_CGLS */ 7861 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 7862 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 7863 7864 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 7865 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 7866 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 7867 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 7868 7869 /* AMD_CG_SUPPORT_GFX_CP_LS */ 7870 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 7871 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 7872 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 7873 7874 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 7875 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 7876 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 7877 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 7878 7879 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 7880 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 7881 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 7882 } 7883 7884 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 7885 { 7886 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 7887 } 7888 7889 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 7890 { 7891 struct amdgpu_device *adev = ring->adev; 7892 u64 wptr; 7893 7894 /* XXX check if swapping is necessary on BE */ 7895 if (ring->use_doorbell) { 7896 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 7897 } else { 7898 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 7899 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 7900 } 7901 7902 return wptr; 7903 } 7904 7905 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 7906 { 7907 struct amdgpu_device *adev = ring->adev; 7908 7909 if (ring->use_doorbell) { 7910 /* XXX check if swapping is necessary on BE */ 7911 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 7912 WDOORBELL64(ring->doorbell_index, ring->wptr); 7913 } else { 7914 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 7915 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 7916 } 7917 } 7918 7919 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 7920 { 7921 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 7922 } 7923 7924 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 7925 { 7926 u64 wptr; 7927 7928 /* XXX check if swapping is necessary on BE */ 7929 if (ring->use_doorbell) 7930 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 7931 else 7932 BUG(); 7933 return wptr; 7934 } 7935 7936 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 7937 { 7938 struct amdgpu_device *adev = ring->adev; 7939 7940 /* XXX check if swapping is necessary on BE */ 7941 if (ring->use_doorbell) { 7942 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 7943 WDOORBELL64(ring->doorbell_index, ring->wptr); 7944 } else { 7945 BUG(); /* only DOORBELL method supported on gfx10 now */ 7946 } 7947 } 7948 7949 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 7950 { 7951 struct amdgpu_device *adev = ring->adev; 7952 u32 ref_and_mask, reg_mem_engine; 7953 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 7954 7955 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 7956 switch (ring->me) { 7957 case 1: 7958 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 7959 break; 7960 case 2: 7961 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 7962 break; 7963 default: 7964 return; 7965 } 7966 reg_mem_engine = 0; 7967 } else { 7968 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 7969 reg_mem_engine = 1; /* pfp */ 7970 } 7971 7972 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 7973 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 7974 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 7975 ref_and_mask, ref_and_mask, 0x20); 7976 } 7977 7978 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 7979 struct amdgpu_job *job, 7980 struct amdgpu_ib *ib, 7981 uint32_t flags) 7982 { 7983 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 7984 u32 header, control = 0; 7985 7986 if (ib->flags & AMDGPU_IB_FLAG_CE) 7987 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 7988 else 7989 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 7990 7991 control |= ib->length_dw | (vmid << 24); 7992 7993 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 7994 control |= INDIRECT_BUFFER_PRE_ENB(1); 7995 7996 if (flags & AMDGPU_IB_PREEMPTED) 7997 control |= INDIRECT_BUFFER_PRE_RESUME(1); 7998 7999 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8000 gfx_v10_0_ring_emit_de_meta(ring, 8001 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8002 } 8003 8004 amdgpu_ring_write(ring, header); 8005 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8006 amdgpu_ring_write(ring, 8007 #ifdef __BIG_ENDIAN 8008 (2 << 0) | 8009 #endif 8010 lower_32_bits(ib->gpu_addr)); 8011 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8012 amdgpu_ring_write(ring, control); 8013 } 8014 8015 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8016 struct amdgpu_job *job, 8017 struct amdgpu_ib *ib, 8018 uint32_t flags) 8019 { 8020 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8021 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8022 8023 /* Currently, there is a high possibility to get wave ID mismatch 8024 * between ME and GDS, leading to a hw deadlock, because ME generates 8025 * different wave IDs than the GDS expects. This situation happens 8026 * randomly when at least 5 compute pipes use GDS ordered append. 8027 * The wave IDs generated by ME are also wrong after suspend/resume. 8028 * Those are probably bugs somewhere else in the kernel driver. 8029 * 8030 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8031 * GDS to 0 for this ring (me/pipe). 8032 */ 8033 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8034 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8035 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8036 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8037 } 8038 8039 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8040 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8041 amdgpu_ring_write(ring, 8042 #ifdef __BIG_ENDIAN 8043 (2 << 0) | 8044 #endif 8045 lower_32_bits(ib->gpu_addr)); 8046 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8047 amdgpu_ring_write(ring, control); 8048 } 8049 8050 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8051 u64 seq, unsigned flags) 8052 { 8053 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8054 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8055 8056 /* RELEASE_MEM - flush caches, send int */ 8057 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8058 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8059 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8060 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8061 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8062 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8063 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8064 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8065 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8066 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8067 8068 /* 8069 * the address should be Qword aligned if 64bit write, Dword 8070 * aligned if only send 32bit data low (discard data high) 8071 */ 8072 if (write64bit) 8073 BUG_ON(addr & 0x7); 8074 else 8075 BUG_ON(addr & 0x3); 8076 amdgpu_ring_write(ring, lower_32_bits(addr)); 8077 amdgpu_ring_write(ring, upper_32_bits(addr)); 8078 amdgpu_ring_write(ring, lower_32_bits(seq)); 8079 amdgpu_ring_write(ring, upper_32_bits(seq)); 8080 amdgpu_ring_write(ring, 0); 8081 } 8082 8083 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8084 { 8085 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8086 uint32_t seq = ring->fence_drv.sync_seq; 8087 uint64_t addr = ring->fence_drv.gpu_addr; 8088 8089 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8090 upper_32_bits(addr), seq, 0xffffffff, 4); 8091 } 8092 8093 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8094 unsigned vmid, uint64_t pd_addr) 8095 { 8096 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8097 8098 /* compute doesn't have PFP */ 8099 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8100 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8101 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8102 amdgpu_ring_write(ring, 0x0); 8103 } 8104 } 8105 8106 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8107 u64 seq, unsigned int flags) 8108 { 8109 struct amdgpu_device *adev = ring->adev; 8110 8111 /* we only allocate 32bit for each seq wb address */ 8112 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8113 8114 /* write fence seq to the "addr" */ 8115 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8116 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8117 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8118 amdgpu_ring_write(ring, lower_32_bits(addr)); 8119 amdgpu_ring_write(ring, upper_32_bits(addr)); 8120 amdgpu_ring_write(ring, lower_32_bits(seq)); 8121 8122 if (flags & AMDGPU_FENCE_FLAG_INT) { 8123 /* set register to trigger INT */ 8124 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8125 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8126 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8127 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8128 amdgpu_ring_write(ring, 0); 8129 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8130 } 8131 } 8132 8133 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8134 { 8135 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8136 amdgpu_ring_write(ring, 0); 8137 } 8138 8139 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8140 uint32_t flags) 8141 { 8142 uint32_t dw2 = 0; 8143 8144 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8145 gfx_v10_0_ring_emit_ce_meta(ring, 8146 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8147 8148 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8149 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8150 /* set load_global_config & load_global_uconfig */ 8151 dw2 |= 0x8001; 8152 /* set load_cs_sh_regs */ 8153 dw2 |= 0x01000000; 8154 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8155 dw2 |= 0x10002; 8156 8157 /* set load_ce_ram if preamble presented */ 8158 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8159 dw2 |= 0x10000000; 8160 } else { 8161 /* still load_ce_ram if this is the first time preamble presented 8162 * although there is no context switch happens. 8163 */ 8164 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8165 dw2 |= 0x10000000; 8166 } 8167 8168 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8169 amdgpu_ring_write(ring, dw2); 8170 amdgpu_ring_write(ring, 0); 8171 } 8172 8173 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8174 { 8175 unsigned ret; 8176 8177 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8178 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8179 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8180 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8181 ret = ring->wptr & ring->buf_mask; 8182 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8183 8184 return ret; 8185 } 8186 8187 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8188 { 8189 unsigned cur; 8190 BUG_ON(offset > ring->buf_mask); 8191 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8192 8193 cur = (ring->wptr - 1) & ring->buf_mask; 8194 if (likely(cur > offset)) 8195 ring->ring[offset] = cur - offset; 8196 else 8197 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8198 } 8199 8200 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8201 { 8202 int i, r = 0; 8203 struct amdgpu_device *adev = ring->adev; 8204 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8205 struct amdgpu_ring *kiq_ring = &kiq->ring; 8206 unsigned long flags; 8207 8208 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8209 return -EINVAL; 8210 8211 spin_lock_irqsave(&kiq->ring_lock, flags); 8212 8213 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8214 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8215 return -ENOMEM; 8216 } 8217 8218 /* assert preemption condition */ 8219 amdgpu_ring_set_preempt_cond_exec(ring, false); 8220 8221 /* assert IB preemption, emit the trailing fence */ 8222 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8223 ring->trail_fence_gpu_addr, 8224 ++ring->trail_seq); 8225 amdgpu_ring_commit(kiq_ring); 8226 8227 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8228 8229 /* poll the trailing fence */ 8230 for (i = 0; i < adev->usec_timeout; i++) { 8231 if (ring->trail_seq == 8232 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8233 break; 8234 udelay(1); 8235 } 8236 8237 if (i >= adev->usec_timeout) { 8238 r = -EINVAL; 8239 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8240 } 8241 8242 /* deassert preemption condition */ 8243 amdgpu_ring_set_preempt_cond_exec(ring, true); 8244 return r; 8245 } 8246 8247 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8248 { 8249 struct amdgpu_device *adev = ring->adev; 8250 struct v10_ce_ib_state ce_payload = {0}; 8251 uint64_t csa_addr; 8252 int cnt; 8253 8254 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8255 csa_addr = amdgpu_csa_vaddr(ring->adev); 8256 8257 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8258 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8259 WRITE_DATA_DST_SEL(8) | 8260 WR_CONFIRM) | 8261 WRITE_DATA_CACHE_POLICY(0)); 8262 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8263 offsetof(struct v10_gfx_meta_data, ce_payload))); 8264 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8265 offsetof(struct v10_gfx_meta_data, ce_payload))); 8266 8267 if (resume) 8268 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8269 offsetof(struct v10_gfx_meta_data, 8270 ce_payload), 8271 sizeof(ce_payload) >> 2); 8272 else 8273 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8274 sizeof(ce_payload) >> 2); 8275 } 8276 8277 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8278 { 8279 struct amdgpu_device *adev = ring->adev; 8280 struct v10_de_ib_state de_payload = {0}; 8281 uint64_t csa_addr, gds_addr; 8282 int cnt; 8283 8284 csa_addr = amdgpu_csa_vaddr(ring->adev); 8285 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8286 PAGE_SIZE); 8287 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8288 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8289 8290 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8291 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8292 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8293 WRITE_DATA_DST_SEL(8) | 8294 WR_CONFIRM) | 8295 WRITE_DATA_CACHE_POLICY(0)); 8296 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8297 offsetof(struct v10_gfx_meta_data, de_payload))); 8298 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8299 offsetof(struct v10_gfx_meta_data, de_payload))); 8300 8301 if (resume) 8302 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8303 offsetof(struct v10_gfx_meta_data, 8304 de_payload), 8305 sizeof(de_payload) >> 2); 8306 else 8307 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8308 sizeof(de_payload) >> 2); 8309 } 8310 8311 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8312 bool secure) 8313 { 8314 uint32_t v = secure ? FRAME_TMZ : 0; 8315 8316 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8317 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8318 } 8319 8320 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8321 uint32_t reg_val_offs) 8322 { 8323 struct amdgpu_device *adev = ring->adev; 8324 8325 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8326 amdgpu_ring_write(ring, 0 | /* src: register*/ 8327 (5 << 8) | /* dst: memory */ 8328 (1 << 20)); /* write confirm */ 8329 amdgpu_ring_write(ring, reg); 8330 amdgpu_ring_write(ring, 0); 8331 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8332 reg_val_offs * 4)); 8333 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8334 reg_val_offs * 4)); 8335 } 8336 8337 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8338 uint32_t val) 8339 { 8340 uint32_t cmd = 0; 8341 8342 switch (ring->funcs->type) { 8343 case AMDGPU_RING_TYPE_GFX: 8344 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8345 break; 8346 case AMDGPU_RING_TYPE_KIQ: 8347 cmd = (1 << 16); /* no inc addr */ 8348 break; 8349 default: 8350 cmd = WR_CONFIRM; 8351 break; 8352 } 8353 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8354 amdgpu_ring_write(ring, cmd); 8355 amdgpu_ring_write(ring, reg); 8356 amdgpu_ring_write(ring, 0); 8357 amdgpu_ring_write(ring, val); 8358 } 8359 8360 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8361 uint32_t val, uint32_t mask) 8362 { 8363 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8364 } 8365 8366 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8367 uint32_t reg0, uint32_t reg1, 8368 uint32_t ref, uint32_t mask) 8369 { 8370 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8371 struct amdgpu_device *adev = ring->adev; 8372 bool fw_version_ok = false; 8373 8374 fw_version_ok = adev->gfx.cp_fw_write_wait; 8375 8376 if (fw_version_ok) 8377 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8378 ref, mask, 0x20); 8379 else 8380 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8381 ref, mask); 8382 } 8383 8384 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8385 unsigned vmid) 8386 { 8387 struct amdgpu_device *adev = ring->adev; 8388 uint32_t value = 0; 8389 8390 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8391 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8392 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8393 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8394 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8395 } 8396 8397 static void 8398 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8399 uint32_t me, uint32_t pipe, 8400 enum amdgpu_interrupt_state state) 8401 { 8402 uint32_t cp_int_cntl, cp_int_cntl_reg; 8403 8404 if (!me) { 8405 switch (pipe) { 8406 case 0: 8407 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8408 break; 8409 case 1: 8410 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8411 break; 8412 default: 8413 DRM_DEBUG("invalid pipe %d\n", pipe); 8414 return; 8415 } 8416 } else { 8417 DRM_DEBUG("invalid me %d\n", me); 8418 return; 8419 } 8420 8421 switch (state) { 8422 case AMDGPU_IRQ_STATE_DISABLE: 8423 cp_int_cntl = RREG32(cp_int_cntl_reg); 8424 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8425 TIME_STAMP_INT_ENABLE, 0); 8426 WREG32(cp_int_cntl_reg, cp_int_cntl); 8427 break; 8428 case AMDGPU_IRQ_STATE_ENABLE: 8429 cp_int_cntl = RREG32(cp_int_cntl_reg); 8430 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8431 TIME_STAMP_INT_ENABLE, 1); 8432 WREG32(cp_int_cntl_reg, cp_int_cntl); 8433 break; 8434 default: 8435 break; 8436 } 8437 } 8438 8439 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8440 int me, int pipe, 8441 enum amdgpu_interrupt_state state) 8442 { 8443 u32 mec_int_cntl, mec_int_cntl_reg; 8444 8445 /* 8446 * amdgpu controls only the first MEC. That's why this function only 8447 * handles the setting of interrupts for this specific MEC. All other 8448 * pipes' interrupts are set by amdkfd. 8449 */ 8450 8451 if (me == 1) { 8452 switch (pipe) { 8453 case 0: 8454 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8455 break; 8456 case 1: 8457 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8458 break; 8459 case 2: 8460 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8461 break; 8462 case 3: 8463 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8464 break; 8465 default: 8466 DRM_DEBUG("invalid pipe %d\n", pipe); 8467 return; 8468 } 8469 } else { 8470 DRM_DEBUG("invalid me %d\n", me); 8471 return; 8472 } 8473 8474 switch (state) { 8475 case AMDGPU_IRQ_STATE_DISABLE: 8476 mec_int_cntl = RREG32(mec_int_cntl_reg); 8477 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8478 TIME_STAMP_INT_ENABLE, 0); 8479 WREG32(mec_int_cntl_reg, mec_int_cntl); 8480 break; 8481 case AMDGPU_IRQ_STATE_ENABLE: 8482 mec_int_cntl = RREG32(mec_int_cntl_reg); 8483 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8484 TIME_STAMP_INT_ENABLE, 1); 8485 WREG32(mec_int_cntl_reg, mec_int_cntl); 8486 break; 8487 default: 8488 break; 8489 } 8490 } 8491 8492 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8493 struct amdgpu_irq_src *src, 8494 unsigned type, 8495 enum amdgpu_interrupt_state state) 8496 { 8497 switch (type) { 8498 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8499 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8500 break; 8501 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8502 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8503 break; 8504 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8505 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8506 break; 8507 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8508 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8509 break; 8510 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8511 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8512 break; 8513 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8514 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8515 break; 8516 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8517 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8518 break; 8519 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8520 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8521 break; 8522 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8523 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8524 break; 8525 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8526 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8527 break; 8528 default: 8529 break; 8530 } 8531 return 0; 8532 } 8533 8534 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8535 struct amdgpu_irq_src *source, 8536 struct amdgpu_iv_entry *entry) 8537 { 8538 int i; 8539 u8 me_id, pipe_id, queue_id; 8540 struct amdgpu_ring *ring; 8541 8542 DRM_DEBUG("IH: CP EOP\n"); 8543 me_id = (entry->ring_id & 0x0c) >> 2; 8544 pipe_id = (entry->ring_id & 0x03) >> 0; 8545 queue_id = (entry->ring_id & 0x70) >> 4; 8546 8547 switch (me_id) { 8548 case 0: 8549 if (pipe_id == 0) 8550 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8551 else 8552 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8553 break; 8554 case 1: 8555 case 2: 8556 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8557 ring = &adev->gfx.compute_ring[i]; 8558 /* Per-queue interrupt is supported for MEC starting from VI. 8559 * The interrupt can only be enabled/disabled per pipe instead of per queue. 8560 */ 8561 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 8562 amdgpu_fence_process(ring); 8563 } 8564 break; 8565 } 8566 return 0; 8567 } 8568 8569 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8570 struct amdgpu_irq_src *source, 8571 unsigned type, 8572 enum amdgpu_interrupt_state state) 8573 { 8574 switch (state) { 8575 case AMDGPU_IRQ_STATE_DISABLE: 8576 case AMDGPU_IRQ_STATE_ENABLE: 8577 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8578 PRIV_REG_INT_ENABLE, 8579 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8580 break; 8581 default: 8582 break; 8583 } 8584 8585 return 0; 8586 } 8587 8588 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8589 struct amdgpu_irq_src *source, 8590 unsigned type, 8591 enum amdgpu_interrupt_state state) 8592 { 8593 switch (state) { 8594 case AMDGPU_IRQ_STATE_DISABLE: 8595 case AMDGPU_IRQ_STATE_ENABLE: 8596 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8597 PRIV_INSTR_INT_ENABLE, 8598 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8599 default: 8600 break; 8601 } 8602 8603 return 0; 8604 } 8605 8606 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8607 struct amdgpu_iv_entry *entry) 8608 { 8609 u8 me_id, pipe_id, queue_id; 8610 struct amdgpu_ring *ring; 8611 int i; 8612 8613 me_id = (entry->ring_id & 0x0c) >> 2; 8614 pipe_id = (entry->ring_id & 0x03) >> 0; 8615 queue_id = (entry->ring_id & 0x70) >> 4; 8616 8617 switch (me_id) { 8618 case 0: 8619 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 8620 ring = &adev->gfx.gfx_ring[i]; 8621 /* we only enabled 1 gfx queue per pipe for now */ 8622 if (ring->me == me_id && ring->pipe == pipe_id) 8623 drm_sched_fault(&ring->sched); 8624 } 8625 break; 8626 case 1: 8627 case 2: 8628 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8629 ring = &adev->gfx.compute_ring[i]; 8630 if (ring->me == me_id && ring->pipe == pipe_id && 8631 ring->queue == queue_id) 8632 drm_sched_fault(&ring->sched); 8633 } 8634 break; 8635 default: 8636 BUG(); 8637 } 8638 } 8639 8640 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 8641 struct amdgpu_irq_src *source, 8642 struct amdgpu_iv_entry *entry) 8643 { 8644 DRM_ERROR("Illegal register access in command stream\n"); 8645 gfx_v10_0_handle_priv_fault(adev, entry); 8646 return 0; 8647 } 8648 8649 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 8650 struct amdgpu_irq_src *source, 8651 struct amdgpu_iv_entry *entry) 8652 { 8653 DRM_ERROR("Illegal instruction in command stream\n"); 8654 gfx_v10_0_handle_priv_fault(adev, entry); 8655 return 0; 8656 } 8657 8658 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 8659 struct amdgpu_irq_src *src, 8660 unsigned int type, 8661 enum amdgpu_interrupt_state state) 8662 { 8663 uint32_t tmp, target; 8664 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8665 8666 if (ring->me == 1) 8667 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8668 else 8669 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 8670 target += ring->pipe; 8671 8672 switch (type) { 8673 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 8674 if (state == AMDGPU_IRQ_STATE_DISABLE) { 8675 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8676 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8677 GENERIC2_INT_ENABLE, 0); 8678 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8679 8680 tmp = RREG32(target); 8681 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8682 GENERIC2_INT_ENABLE, 0); 8683 WREG32(target, tmp); 8684 } else { 8685 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8686 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8687 GENERIC2_INT_ENABLE, 1); 8688 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8689 8690 tmp = RREG32(target); 8691 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8692 GENERIC2_INT_ENABLE, 1); 8693 WREG32(target, tmp); 8694 } 8695 break; 8696 default: 8697 BUG(); /* kiq only support GENERIC2_INT now */ 8698 break; 8699 } 8700 return 0; 8701 } 8702 8703 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 8704 struct amdgpu_irq_src *source, 8705 struct amdgpu_iv_entry *entry) 8706 { 8707 u8 me_id, pipe_id, queue_id; 8708 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8709 8710 me_id = (entry->ring_id & 0x0c) >> 2; 8711 pipe_id = (entry->ring_id & 0x03) >> 0; 8712 queue_id = (entry->ring_id & 0x70) >> 4; 8713 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 8714 me_id, pipe_id, queue_id); 8715 8716 amdgpu_fence_process(ring); 8717 return 0; 8718 } 8719 8720 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 8721 { 8722 const unsigned int gcr_cntl = 8723 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 8724 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 8725 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 8726 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 8727 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 8728 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 8729 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 8730 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 8731 8732 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 8733 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 8734 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 8735 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 8736 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 8737 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 8738 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 8739 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 8740 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 8741 } 8742 8743 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 8744 .name = "gfx_v10_0", 8745 .early_init = gfx_v10_0_early_init, 8746 .late_init = gfx_v10_0_late_init, 8747 .sw_init = gfx_v10_0_sw_init, 8748 .sw_fini = gfx_v10_0_sw_fini, 8749 .hw_init = gfx_v10_0_hw_init, 8750 .hw_fini = gfx_v10_0_hw_fini, 8751 .suspend = gfx_v10_0_suspend, 8752 .resume = gfx_v10_0_resume, 8753 .is_idle = gfx_v10_0_is_idle, 8754 .wait_for_idle = gfx_v10_0_wait_for_idle, 8755 .soft_reset = gfx_v10_0_soft_reset, 8756 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 8757 .set_powergating_state = gfx_v10_0_set_powergating_state, 8758 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 8759 }; 8760 8761 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 8762 .type = AMDGPU_RING_TYPE_GFX, 8763 .align_mask = 0xff, 8764 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8765 .support_64bit_ptrs = true, 8766 .vmhub = AMDGPU_GFXHUB_0, 8767 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 8768 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 8769 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 8770 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 8771 5 + /* COND_EXEC */ 8772 7 + /* PIPELINE_SYNC */ 8773 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8774 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8775 2 + /* VM_FLUSH */ 8776 8 + /* FENCE for VM_FLUSH */ 8777 20 + /* GDS switch */ 8778 4 + /* double SWITCH_BUFFER, 8779 * the first COND_EXEC jump to the place 8780 * just prior to this double SWITCH_BUFFER 8781 */ 8782 5 + /* COND_EXEC */ 8783 7 + /* HDP_flush */ 8784 4 + /* VGT_flush */ 8785 14 + /* CE_META */ 8786 31 + /* DE_META */ 8787 3 + /* CNTX_CTRL */ 8788 5 + /* HDP_INVL */ 8789 8 + 8 + /* FENCE x2 */ 8790 2 + /* SWITCH_BUFFER */ 8791 8, /* gfx_v10_0_emit_mem_sync */ 8792 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 8793 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 8794 .emit_fence = gfx_v10_0_ring_emit_fence, 8795 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8796 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8797 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8798 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8799 .test_ring = gfx_v10_0_ring_test_ring, 8800 .test_ib = gfx_v10_0_ring_test_ib, 8801 .insert_nop = amdgpu_ring_insert_nop, 8802 .pad_ib = amdgpu_ring_generic_pad_ib, 8803 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 8804 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 8805 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 8806 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 8807 .preempt_ib = gfx_v10_0_ring_preempt_ib, 8808 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 8809 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8810 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8811 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8812 .soft_recovery = gfx_v10_0_ring_soft_recovery, 8813 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8814 }; 8815 8816 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 8817 .type = AMDGPU_RING_TYPE_COMPUTE, 8818 .align_mask = 0xff, 8819 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8820 .support_64bit_ptrs = true, 8821 .vmhub = AMDGPU_GFXHUB_0, 8822 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8823 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8824 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8825 .emit_frame_size = 8826 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8827 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8828 5 + /* hdp invalidate */ 8829 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8830 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8831 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8832 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8833 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 8834 8, /* gfx_v10_0_emit_mem_sync */ 8835 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8836 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8837 .emit_fence = gfx_v10_0_ring_emit_fence, 8838 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8839 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8840 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8841 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8842 .test_ring = gfx_v10_0_ring_test_ring, 8843 .test_ib = gfx_v10_0_ring_test_ib, 8844 .insert_nop = amdgpu_ring_insert_nop, 8845 .pad_ib = amdgpu_ring_generic_pad_ib, 8846 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8847 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8848 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8849 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8850 }; 8851 8852 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 8853 .type = AMDGPU_RING_TYPE_KIQ, 8854 .align_mask = 0xff, 8855 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8856 .support_64bit_ptrs = true, 8857 .vmhub = AMDGPU_GFXHUB_0, 8858 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8859 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8860 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8861 .emit_frame_size = 8862 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8863 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8864 5 + /*hdp invalidate */ 8865 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8866 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8867 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8868 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8869 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 8870 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8871 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8872 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 8873 .test_ring = gfx_v10_0_ring_test_ring, 8874 .test_ib = gfx_v10_0_ring_test_ib, 8875 .insert_nop = amdgpu_ring_insert_nop, 8876 .pad_ib = amdgpu_ring_generic_pad_ib, 8877 .emit_rreg = gfx_v10_0_ring_emit_rreg, 8878 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8879 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8880 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8881 }; 8882 8883 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 8884 { 8885 int i; 8886 8887 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 8888 8889 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 8890 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 8891 8892 for (i = 0; i < adev->gfx.num_compute_rings; i++) 8893 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 8894 } 8895 8896 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 8897 .set = gfx_v10_0_set_eop_interrupt_state, 8898 .process = gfx_v10_0_eop_irq, 8899 }; 8900 8901 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 8902 .set = gfx_v10_0_set_priv_reg_fault_state, 8903 .process = gfx_v10_0_priv_reg_irq, 8904 }; 8905 8906 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 8907 .set = gfx_v10_0_set_priv_inst_fault_state, 8908 .process = gfx_v10_0_priv_inst_irq, 8909 }; 8910 8911 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 8912 .set = gfx_v10_0_kiq_set_interrupt_state, 8913 .process = gfx_v10_0_kiq_irq, 8914 }; 8915 8916 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 8917 { 8918 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 8919 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 8920 8921 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 8922 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 8923 8924 adev->gfx.priv_reg_irq.num_types = 1; 8925 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 8926 8927 adev->gfx.priv_inst_irq.num_types = 1; 8928 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 8929 } 8930 8931 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 8932 { 8933 switch (adev->asic_type) { 8934 case CHIP_NAVI10: 8935 case CHIP_NAVI14: 8936 case CHIP_SIENNA_CICHLID: 8937 case CHIP_NAVY_FLOUNDER: 8938 case CHIP_VANGOGH: 8939 case CHIP_DIMGREY_CAVEFISH: 8940 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 8941 break; 8942 case CHIP_NAVI12: 8943 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 8944 break; 8945 default: 8946 break; 8947 } 8948 } 8949 8950 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 8951 { 8952 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 8953 adev->gfx.config.max_sh_per_se * 8954 adev->gfx.config.max_shader_engines; 8955 8956 adev->gds.gds_size = 0x10000; 8957 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 8958 adev->gds.gws_size = 64; 8959 adev->gds.oa_size = 16; 8960 } 8961 8962 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 8963 u32 bitmap) 8964 { 8965 u32 data; 8966 8967 if (!bitmap) 8968 return; 8969 8970 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 8971 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 8972 8973 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 8974 } 8975 8976 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 8977 { 8978 u32 data, wgp_bitmask; 8979 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 8980 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 8981 8982 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 8983 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 8984 8985 wgp_bitmask = 8986 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 8987 8988 return (~data) & wgp_bitmask; 8989 } 8990 8991 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 8992 { 8993 u32 wgp_idx, wgp_active_bitmap; 8994 u32 cu_bitmap_per_wgp, cu_active_bitmap; 8995 8996 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 8997 cu_active_bitmap = 0; 8998 8999 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9000 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9001 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9002 if (wgp_active_bitmap & (1 << wgp_idx)) 9003 cu_active_bitmap |= cu_bitmap_per_wgp; 9004 } 9005 9006 return cu_active_bitmap; 9007 } 9008 9009 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9010 struct amdgpu_cu_info *cu_info) 9011 { 9012 int i, j, k, counter, active_cu_number = 0; 9013 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9014 unsigned disable_masks[4 * 2]; 9015 9016 if (!adev || !cu_info) 9017 return -EINVAL; 9018 9019 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9020 9021 mutex_lock(&adev->grbm_idx_mutex); 9022 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9023 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9024 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9025 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 9026 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9027 continue; 9028 mask = 1; 9029 ao_bitmap = 0; 9030 counter = 0; 9031 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9032 if (i < 4 && j < 2) 9033 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9034 adev, disable_masks[i * 2 + j]); 9035 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9036 cu_info->bitmap[i][j] = bitmap; 9037 9038 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9039 if (bitmap & mask) { 9040 if (counter < adev->gfx.config.max_cu_per_sh) 9041 ao_bitmap |= mask; 9042 counter++; 9043 } 9044 mask <<= 1; 9045 } 9046 active_cu_number += counter; 9047 if (i < 2 && j < 2) 9048 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9049 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9050 } 9051 } 9052 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9053 mutex_unlock(&adev->grbm_idx_mutex); 9054 9055 cu_info->number = active_cu_number; 9056 cu_info->ao_cu_mask = ao_cu_mask; 9057 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9058 9059 return 0; 9060 } 9061 9062 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9063 { 9064 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9065 9066 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9067 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9068 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9069 9070 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9071 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9072 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9073 9074 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9075 adev->gfx.config.max_shader_engines); 9076 disabled_sa = efuse_setting | vbios_setting; 9077 disabled_sa &= max_sa_mask; 9078 9079 return disabled_sa; 9080 } 9081 9082 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9083 { 9084 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9085 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9086 9087 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9088 9089 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9090 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9091 max_shader_engines = adev->gfx.config.max_shader_engines; 9092 9093 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9094 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9095 disabled_sa_per_se &= max_sa_per_se_mask; 9096 if (disabled_sa_per_se == max_sa_per_se_mask) { 9097 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9098 break; 9099 } 9100 } 9101 } 9102 9103 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9104 { 9105 .type = AMD_IP_BLOCK_TYPE_GFX, 9106 .major = 10, 9107 .minor = 0, 9108 .rev = 0, 9109 .funcs = &gfx_v10_0_ip_funcs, 9110 }; 9111