1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 114 115 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 121 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 125 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 127 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 129 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 131 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 134 135 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 137 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 139 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 141 #define mmCP_HYP_CE_UCODE_DATA 0x5819 142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 143 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 145 #define mmCP_HYP_ME_UCODE_DATA 0x5817 146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 147 148 #define mmCPG_PSP_DEBUG 0x5c10 149 #define mmCPG_PSP_DEBUG_BASE_IDX 1 150 #define mmCPC_PSP_DEBUG 0x5c11 151 #define mmCPC_PSP_DEBUG_BASE_IDX 1 152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 154 155 //CC_GC_SA_UNIT_DISABLE 156 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 160 //GC_USER_SA_UNIT_DISABLE 161 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //PA_SC_ENHANCE_3 166 #define mmPA_SC_ENHANCE_3 0x1085 167 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 170 171 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 173 174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 178 179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 181 182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 184 185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 187 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 191 192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 203 204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 206 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 210 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 217 218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 224 225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 231 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 238 239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 245 246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 252 253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 259 260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 266 267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 273 274 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 275 { 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 316 }; 317 318 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 319 { 320 /* Pending on emulation bring up */ 321 }; 322 323 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 324 { 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1377 }; 1378 1379 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1380 { 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1419 }; 1420 1421 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1422 { 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1465 }; 1466 1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1468 { 1469 /* Pending on emulation bring up */ 1470 }; 1471 1472 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1473 { 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2094 }; 2095 2096 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2097 { 2098 /* Pending on emulation bring up */ 2099 }; 2100 2101 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2102 { 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3155 }; 3156 3157 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3158 { 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3202 }; 3203 3204 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3205 { 3206 /* Pending on emulation bring up */ 3207 }; 3208 3209 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3210 { 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3252 3253 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3255 }; 3256 3257 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3258 { 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3283 3284 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3286 }; 3287 3288 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = 3289 { 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3310 }; 3311 3312 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3313 { 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3350 }; 3351 3352 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3385 }; 3386 3387 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3422 }; 3423 3424 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = 3425 { 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3448 }; 3449 3450 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3473 }; 3474 3475 #define DEFAULT_SH_MEM_CONFIG \ 3476 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3477 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3478 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3479 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3480 3481 /* TODO: pending on golden setting value of gb address config */ 3482 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3483 3484 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3485 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3486 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3487 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3488 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3489 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3490 struct amdgpu_cu_info *cu_info); 3491 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3493 u32 sh_num, u32 instance); 3494 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3495 3496 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3497 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3498 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3499 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3500 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3501 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3502 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3503 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3504 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3505 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3506 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3507 uint16_t pasid, uint32_t flush_type, 3508 bool all_hub, uint8_t dst_sel); 3509 3510 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3511 { 3512 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3513 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3514 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3515 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3516 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3517 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3518 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3519 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3520 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3521 } 3522 3523 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3524 struct amdgpu_ring *ring) 3525 { 3526 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3527 uint64_t wptr_addr = ring->wptr_gpu_addr; 3528 uint32_t eng_sel = 0; 3529 3530 switch (ring->funcs->type) { 3531 case AMDGPU_RING_TYPE_COMPUTE: 3532 eng_sel = 0; 3533 break; 3534 case AMDGPU_RING_TYPE_GFX: 3535 eng_sel = 4; 3536 break; 3537 case AMDGPU_RING_TYPE_MES: 3538 eng_sel = 5; 3539 break; 3540 default: 3541 WARN_ON(1); 3542 } 3543 3544 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3545 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3546 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3547 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3548 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3549 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3550 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3551 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3552 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3553 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3554 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3555 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3556 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3557 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3558 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3559 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3560 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3561 } 3562 3563 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3564 struct amdgpu_ring *ring, 3565 enum amdgpu_unmap_queues_action action, 3566 u64 gpu_addr, u64 seq) 3567 { 3568 struct amdgpu_device *adev = kiq_ring->adev; 3569 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3570 3571 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { 3572 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 3573 return; 3574 } 3575 3576 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3577 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3578 PACKET3_UNMAP_QUEUES_ACTION(action) | 3579 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3580 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3581 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3582 amdgpu_ring_write(kiq_ring, 3583 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3584 3585 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3586 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3587 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3588 amdgpu_ring_write(kiq_ring, seq); 3589 } else { 3590 amdgpu_ring_write(kiq_ring, 0); 3591 amdgpu_ring_write(kiq_ring, 0); 3592 amdgpu_ring_write(kiq_ring, 0); 3593 } 3594 } 3595 3596 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3597 struct amdgpu_ring *ring, 3598 u64 addr, 3599 u64 seq) 3600 { 3601 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3602 3603 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3604 amdgpu_ring_write(kiq_ring, 3605 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3606 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3607 PACKET3_QUERY_STATUS_COMMAND(2)); 3608 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3609 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3610 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3611 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3612 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3613 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3614 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3615 } 3616 3617 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3618 uint16_t pasid, uint32_t flush_type, 3619 bool all_hub) 3620 { 3621 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3622 } 3623 3624 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3625 .kiq_set_resources = gfx10_kiq_set_resources, 3626 .kiq_map_queues = gfx10_kiq_map_queues, 3627 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3628 .kiq_query_status = gfx10_kiq_query_status, 3629 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3630 .set_resources_size = 8, 3631 .map_queues_size = 7, 3632 .unmap_queues_size = 6, 3633 .query_status_size = 7, 3634 .invalidate_tlbs_size = 2, 3635 }; 3636 3637 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3638 { 3639 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3640 } 3641 3642 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3643 { 3644 switch (adev->ip_versions[GC_HWIP][0]) { 3645 case IP_VERSION(10, 1, 10): 3646 soc15_program_register_sequence(adev, 3647 golden_settings_gc_rlc_spm_10_0_nv10, 3648 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3649 break; 3650 case IP_VERSION(10, 1, 1): 3651 soc15_program_register_sequence(adev, 3652 golden_settings_gc_rlc_spm_10_1_nv14, 3653 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3654 break; 3655 case IP_VERSION(10, 1, 2): 3656 soc15_program_register_sequence(adev, 3657 golden_settings_gc_rlc_spm_10_1_2_nv12, 3658 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3659 break; 3660 default: 3661 break; 3662 } 3663 } 3664 3665 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3666 { 3667 switch (adev->ip_versions[GC_HWIP][0]) { 3668 case IP_VERSION(10, 1, 10): 3669 soc15_program_register_sequence(adev, 3670 golden_settings_gc_10_1, 3671 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3672 soc15_program_register_sequence(adev, 3673 golden_settings_gc_10_0_nv10, 3674 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3675 break; 3676 case IP_VERSION(10, 1, 1): 3677 soc15_program_register_sequence(adev, 3678 golden_settings_gc_10_1_1, 3679 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3680 soc15_program_register_sequence(adev, 3681 golden_settings_gc_10_1_nv14, 3682 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3683 break; 3684 case IP_VERSION(10, 1, 2): 3685 soc15_program_register_sequence(adev, 3686 golden_settings_gc_10_1_2, 3687 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3688 soc15_program_register_sequence(adev, 3689 golden_settings_gc_10_1_2_nv12, 3690 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3691 break; 3692 case IP_VERSION(10, 3, 0): 3693 soc15_program_register_sequence(adev, 3694 golden_settings_gc_10_3, 3695 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3696 soc15_program_register_sequence(adev, 3697 golden_settings_gc_10_3_sienna_cichlid, 3698 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3699 break; 3700 case IP_VERSION(10, 3, 2): 3701 soc15_program_register_sequence(adev, 3702 golden_settings_gc_10_3_2, 3703 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3704 break; 3705 case IP_VERSION(10, 3, 1): 3706 soc15_program_register_sequence(adev, 3707 golden_settings_gc_10_3_vangogh, 3708 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3709 break; 3710 case IP_VERSION(10, 3, 3): 3711 soc15_program_register_sequence(adev, 3712 golden_settings_gc_10_3_3, 3713 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3714 break; 3715 case IP_VERSION(10, 3, 4): 3716 soc15_program_register_sequence(adev, 3717 golden_settings_gc_10_3_4, 3718 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3719 break; 3720 case IP_VERSION(10, 3, 5): 3721 soc15_program_register_sequence(adev, 3722 golden_settings_gc_10_3_5, 3723 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3724 break; 3725 case IP_VERSION(10, 1, 3): 3726 case IP_VERSION(10, 1, 4): 3727 soc15_program_register_sequence(adev, 3728 golden_settings_gc_10_0_cyan_skillfish, 3729 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3730 break; 3731 case IP_VERSION(10, 3, 6): 3732 soc15_program_register_sequence(adev, 3733 golden_settings_gc_10_3_6, 3734 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3735 break; 3736 case IP_VERSION(10, 3, 7): 3737 soc15_program_register_sequence(adev, 3738 golden_settings_gc_10_3_7, 3739 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3740 break; 3741 default: 3742 break; 3743 } 3744 gfx_v10_0_init_spm_golden_registers(adev); 3745 } 3746 3747 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3748 bool wc, uint32_t reg, uint32_t val) 3749 { 3750 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3751 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3752 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3753 amdgpu_ring_write(ring, reg); 3754 amdgpu_ring_write(ring, 0); 3755 amdgpu_ring_write(ring, val); 3756 } 3757 3758 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3759 int mem_space, int opt, uint32_t addr0, 3760 uint32_t addr1, uint32_t ref, uint32_t mask, 3761 uint32_t inv) 3762 { 3763 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3764 amdgpu_ring_write(ring, 3765 /* memory (1) or register (0) */ 3766 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3767 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3768 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3769 WAIT_REG_MEM_ENGINE(eng_sel))); 3770 3771 if (mem_space) 3772 BUG_ON(addr0 & 0x3); /* Dword align */ 3773 amdgpu_ring_write(ring, addr0); 3774 amdgpu_ring_write(ring, addr1); 3775 amdgpu_ring_write(ring, ref); 3776 amdgpu_ring_write(ring, mask); 3777 amdgpu_ring_write(ring, inv); /* poll interval */ 3778 } 3779 3780 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3781 { 3782 struct amdgpu_device *adev = ring->adev; 3783 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3784 uint32_t tmp = 0; 3785 unsigned i; 3786 int r; 3787 3788 WREG32(scratch, 0xCAFEDEAD); 3789 r = amdgpu_ring_alloc(ring, 3); 3790 if (r) { 3791 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3792 ring->idx, r); 3793 return r; 3794 } 3795 3796 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3797 amdgpu_ring_write(ring, scratch - 3798 PACKET3_SET_UCONFIG_REG_START); 3799 amdgpu_ring_write(ring, 0xDEADBEEF); 3800 amdgpu_ring_commit(ring); 3801 3802 for (i = 0; i < adev->usec_timeout; i++) { 3803 tmp = RREG32(scratch); 3804 if (tmp == 0xDEADBEEF) 3805 break; 3806 if (amdgpu_emu_mode == 1) 3807 msleep(1); 3808 else 3809 udelay(1); 3810 } 3811 3812 if (i >= adev->usec_timeout) 3813 r = -ETIMEDOUT; 3814 3815 return r; 3816 } 3817 3818 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3819 { 3820 struct amdgpu_device *adev = ring->adev; 3821 struct amdgpu_ib ib; 3822 struct dma_fence *f = NULL; 3823 unsigned index; 3824 uint64_t gpu_addr; 3825 volatile uint32_t *cpu_ptr; 3826 long r; 3827 3828 memset(&ib, 0, sizeof(ib)); 3829 3830 if (ring->is_mes_queue) { 3831 uint32_t padding, offset; 3832 3833 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 3834 padding = amdgpu_mes_ctx_get_offs(ring, 3835 AMDGPU_MES_CTX_PADDING_OFFS); 3836 3837 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 3838 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 3839 3840 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 3841 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 3842 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 3843 } else { 3844 r = amdgpu_device_wb_get(adev, &index); 3845 if (r) 3846 return r; 3847 3848 gpu_addr = adev->wb.gpu_addr + (index * 4); 3849 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3850 cpu_ptr = &adev->wb.wb[index]; 3851 3852 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 3853 if (r) { 3854 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 3855 goto err1; 3856 } 3857 } 3858 3859 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3860 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3861 ib.ptr[2] = lower_32_bits(gpu_addr); 3862 ib.ptr[3] = upper_32_bits(gpu_addr); 3863 ib.ptr[4] = 0xDEADBEEF; 3864 ib.length_dw = 5; 3865 3866 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3867 if (r) 3868 goto err2; 3869 3870 r = dma_fence_wait_timeout(f, false, timeout); 3871 if (r == 0) { 3872 r = -ETIMEDOUT; 3873 goto err2; 3874 } else if (r < 0) { 3875 goto err2; 3876 } 3877 3878 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 3879 r = 0; 3880 else 3881 r = -EINVAL; 3882 err2: 3883 if (!ring->is_mes_queue) 3884 amdgpu_ib_free(adev, &ib, NULL); 3885 dma_fence_put(f); 3886 err1: 3887 if (!ring->is_mes_queue) 3888 amdgpu_device_wb_free(adev, index); 3889 return r; 3890 } 3891 3892 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3893 { 3894 amdgpu_ucode_release(&adev->gfx.pfp_fw); 3895 amdgpu_ucode_release(&adev->gfx.me_fw); 3896 amdgpu_ucode_release(&adev->gfx.ce_fw); 3897 amdgpu_ucode_release(&adev->gfx.rlc_fw); 3898 amdgpu_ucode_release(&adev->gfx.mec_fw); 3899 amdgpu_ucode_release(&adev->gfx.mec2_fw); 3900 3901 kfree(adev->gfx.rlc.register_list_format); 3902 } 3903 3904 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3905 { 3906 adev->gfx.cp_fw_write_wait = false; 3907 3908 switch (adev->ip_versions[GC_HWIP][0]) { 3909 case IP_VERSION(10, 1, 10): 3910 case IP_VERSION(10, 1, 2): 3911 case IP_VERSION(10, 1, 1): 3912 case IP_VERSION(10, 1, 3): 3913 case IP_VERSION(10, 1, 4): 3914 if ((adev->gfx.me_fw_version >= 0x00000046) && 3915 (adev->gfx.me_feature_version >= 27) && 3916 (adev->gfx.pfp_fw_version >= 0x00000068) && 3917 (adev->gfx.pfp_feature_version >= 27) && 3918 (adev->gfx.mec_fw_version >= 0x0000005b) && 3919 (adev->gfx.mec_feature_version >= 27)) 3920 adev->gfx.cp_fw_write_wait = true; 3921 break; 3922 case IP_VERSION(10, 3, 0): 3923 case IP_VERSION(10, 3, 2): 3924 case IP_VERSION(10, 3, 1): 3925 case IP_VERSION(10, 3, 4): 3926 case IP_VERSION(10, 3, 5): 3927 case IP_VERSION(10, 3, 6): 3928 case IP_VERSION(10, 3, 3): 3929 case IP_VERSION(10, 3, 7): 3930 adev->gfx.cp_fw_write_wait = true; 3931 break; 3932 default: 3933 break; 3934 } 3935 3936 if (!adev->gfx.cp_fw_write_wait) 3937 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3938 } 3939 3940 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3941 { 3942 bool ret = false; 3943 3944 switch (adev->pdev->revision) { 3945 case 0xc2: 3946 case 0xc3: 3947 ret = true; 3948 break; 3949 default: 3950 ret = false; 3951 break; 3952 } 3953 3954 return ret ; 3955 } 3956 3957 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3958 { 3959 switch (adev->ip_versions[GC_HWIP][0]) { 3960 case IP_VERSION(10, 1, 10): 3961 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3962 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3963 break; 3964 default: 3965 break; 3966 } 3967 } 3968 3969 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3970 { 3971 char fw_name[40]; 3972 char ucode_prefix[30]; 3973 const char *wks = ""; 3974 int err; 3975 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3976 uint16_t version_major; 3977 uint16_t version_minor; 3978 3979 DRM_DEBUG("\n"); 3980 3981 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) && 3982 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 3983 wks = "_wks"; 3984 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 3985 3986 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 3987 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 3988 if (err) 3989 goto out; 3990 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 3991 3992 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks); 3993 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 3994 if (err) 3995 goto out; 3996 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 3997 3998 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 3999 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 4000 if (err) 4001 goto out; 4002 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4003 4004 if (!amdgpu_sriov_vf(adev)) { 4005 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 4006 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 4007 /* don't check this. There are apparently firmwares in the wild with 4008 * incorrect size in the header 4009 */ 4010 if (err == -ENODEV) 4011 goto out; 4012 if (err) 4013 dev_dbg(adev->dev, 4014 "gfx10: amdgpu_ucode_request() failed \"%s\"\n", 4015 fw_name); 4016 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4017 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4018 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4019 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4020 if (err) 4021 goto out; 4022 } 4023 4024 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4025 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 4026 if (err) 4027 goto out; 4028 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4029 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4030 4031 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4032 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 4033 if (!err) { 4034 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4035 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4036 } else { 4037 err = 0; 4038 adev->gfx.mec2_fw = NULL; 4039 } 4040 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4041 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4042 4043 gfx_v10_0_check_fw_write_wait(adev); 4044 out: 4045 if (err) { 4046 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4047 amdgpu_ucode_release(&adev->gfx.me_fw); 4048 amdgpu_ucode_release(&adev->gfx.ce_fw); 4049 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4050 amdgpu_ucode_release(&adev->gfx.mec_fw); 4051 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4052 } 4053 4054 gfx_v10_0_check_gfxoff_flag(adev); 4055 4056 return err; 4057 } 4058 4059 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4060 { 4061 u32 count = 0; 4062 const struct cs_section_def *sect = NULL; 4063 const struct cs_extent_def *ext = NULL; 4064 4065 /* begin clear state */ 4066 count += 2; 4067 /* context control state */ 4068 count += 3; 4069 4070 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4071 for (ext = sect->section; ext->extent != NULL; ++ext) { 4072 if (sect->id == SECT_CONTEXT) 4073 count += 2 + ext->reg_count; 4074 else 4075 return 0; 4076 } 4077 } 4078 4079 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4080 count += 3; 4081 /* end clear state */ 4082 count += 2; 4083 /* clear state */ 4084 count += 2; 4085 4086 return count; 4087 } 4088 4089 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4090 volatile u32 *buffer) 4091 { 4092 u32 count = 0, i; 4093 const struct cs_section_def *sect = NULL; 4094 const struct cs_extent_def *ext = NULL; 4095 int ctx_reg_offset; 4096 4097 if (adev->gfx.rlc.cs_data == NULL) 4098 return; 4099 if (buffer == NULL) 4100 return; 4101 4102 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4103 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4104 4105 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4106 buffer[count++] = cpu_to_le32(0x80000000); 4107 buffer[count++] = cpu_to_le32(0x80000000); 4108 4109 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4110 for (ext = sect->section; ext->extent != NULL; ++ext) { 4111 if (sect->id == SECT_CONTEXT) { 4112 buffer[count++] = 4113 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4114 buffer[count++] = cpu_to_le32(ext->reg_index - 4115 PACKET3_SET_CONTEXT_REG_START); 4116 for (i = 0; i < ext->reg_count; i++) 4117 buffer[count++] = cpu_to_le32(ext->extent[i]); 4118 } else { 4119 return; 4120 } 4121 } 4122 } 4123 4124 ctx_reg_offset = 4125 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4126 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4127 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4128 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4129 4130 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4131 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4132 4133 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4134 buffer[count++] = cpu_to_le32(0); 4135 } 4136 4137 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4138 { 4139 /* clear state block */ 4140 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4141 &adev->gfx.rlc.clear_state_gpu_addr, 4142 (void **)&adev->gfx.rlc.cs_ptr); 4143 4144 /* jump table block */ 4145 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4146 &adev->gfx.rlc.cp_table_gpu_addr, 4147 (void **)&adev->gfx.rlc.cp_table_ptr); 4148 } 4149 4150 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4151 { 4152 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4153 4154 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 4155 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4156 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4157 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4158 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4159 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4160 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4161 switch (adev->ip_versions[GC_HWIP][0]) { 4162 case IP_VERSION(10, 3, 0): 4163 reg_access_ctrl->spare_int = 4164 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4165 break; 4166 default: 4167 reg_access_ctrl->spare_int = 4168 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4169 break; 4170 } 4171 adev->gfx.rlc.rlcg_reg_access_supported = true; 4172 } 4173 4174 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4175 { 4176 const struct cs_section_def *cs_data; 4177 int r; 4178 4179 adev->gfx.rlc.cs_data = gfx10_cs_data; 4180 4181 cs_data = adev->gfx.rlc.cs_data; 4182 4183 if (cs_data) { 4184 /* init clear state block */ 4185 r = amdgpu_gfx_rlc_init_csb(adev); 4186 if (r) 4187 return r; 4188 } 4189 4190 /* init spm vmid with 0xf */ 4191 if (adev->gfx.rlc.funcs->update_spm_vmid) 4192 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4193 4194 4195 return 0; 4196 } 4197 4198 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4199 { 4200 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4201 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4202 } 4203 4204 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4205 { 4206 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4207 4208 amdgpu_gfx_graphics_queue_acquire(adev); 4209 } 4210 4211 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4212 { 4213 int r; 4214 u32 *hpd; 4215 const __le32 *fw_data = NULL; 4216 unsigned fw_size; 4217 u32 *fw = NULL; 4218 size_t mec_hpd_size; 4219 4220 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4221 4222 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4223 4224 /* take ownership of the relevant compute queues */ 4225 amdgpu_gfx_compute_queue_acquire(adev); 4226 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4227 4228 if (mec_hpd_size) { 4229 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4230 AMDGPU_GEM_DOMAIN_GTT, 4231 &adev->gfx.mec.hpd_eop_obj, 4232 &adev->gfx.mec.hpd_eop_gpu_addr, 4233 (void **)&hpd); 4234 if (r) { 4235 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4236 gfx_v10_0_mec_fini(adev); 4237 return r; 4238 } 4239 4240 memset(hpd, 0, mec_hpd_size); 4241 4242 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4243 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4244 } 4245 4246 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4247 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4248 4249 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4250 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4251 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4252 4253 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4254 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4255 &adev->gfx.mec.mec_fw_obj, 4256 &adev->gfx.mec.mec_fw_gpu_addr, 4257 (void **)&fw); 4258 if (r) { 4259 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4260 gfx_v10_0_mec_fini(adev); 4261 return r; 4262 } 4263 4264 memcpy(fw, fw_data, fw_size); 4265 4266 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4267 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4268 } 4269 4270 return 0; 4271 } 4272 4273 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4274 { 4275 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4276 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4277 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4278 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4279 } 4280 4281 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4282 uint32_t thread, uint32_t regno, 4283 uint32_t num, uint32_t *out) 4284 { 4285 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4286 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4287 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4288 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4289 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4290 while (num--) 4291 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4292 } 4293 4294 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4295 { 4296 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4297 * field when performing a select_se_sh so it should be 4298 * zero here */ 4299 WARN_ON(simd != 0); 4300 4301 /* type 2 wave data */ 4302 dst[(*no_fields)++] = 2; 4303 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4304 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4305 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4306 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4307 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4308 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4309 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4310 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4311 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4312 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4313 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4314 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4315 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4316 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4317 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4318 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4319 } 4320 4321 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4322 uint32_t wave, uint32_t start, 4323 uint32_t size, uint32_t *dst) 4324 { 4325 WARN_ON(simd != 0); 4326 4327 wave_read_regs( 4328 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4329 dst); 4330 } 4331 4332 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4333 uint32_t wave, uint32_t thread, 4334 uint32_t start, uint32_t size, 4335 uint32_t *dst) 4336 { 4337 wave_read_regs( 4338 adev, wave, thread, 4339 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4340 } 4341 4342 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4343 u32 me, u32 pipe, u32 q, u32 vm) 4344 { 4345 nv_grbm_select(adev, me, pipe, q, vm); 4346 } 4347 4348 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4349 bool enable) 4350 { 4351 uint32_t data, def; 4352 4353 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4354 4355 if (enable) 4356 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4357 else 4358 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4359 4360 if (data != def) 4361 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4362 } 4363 4364 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4365 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4366 .select_se_sh = &gfx_v10_0_select_se_sh, 4367 .read_wave_data = &gfx_v10_0_read_wave_data, 4368 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4369 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4370 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4371 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4372 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4373 }; 4374 4375 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4376 { 4377 u32 gb_addr_config; 4378 4379 switch (adev->ip_versions[GC_HWIP][0]) { 4380 case IP_VERSION(10, 1, 10): 4381 case IP_VERSION(10, 1, 1): 4382 case IP_VERSION(10, 1, 2): 4383 adev->gfx.config.max_hw_contexts = 8; 4384 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4385 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4386 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4387 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4388 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4389 break; 4390 case IP_VERSION(10, 3, 0): 4391 case IP_VERSION(10, 3, 2): 4392 case IP_VERSION(10, 3, 1): 4393 case IP_VERSION(10, 3, 4): 4394 case IP_VERSION(10, 3, 5): 4395 case IP_VERSION(10, 3, 6): 4396 case IP_VERSION(10, 3, 3): 4397 case IP_VERSION(10, 3, 7): 4398 adev->gfx.config.max_hw_contexts = 8; 4399 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4400 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4401 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4402 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4403 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4404 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4405 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4406 break; 4407 case IP_VERSION(10, 1, 3): 4408 case IP_VERSION(10, 1, 4): 4409 adev->gfx.config.max_hw_contexts = 8; 4410 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4411 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4412 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4413 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4414 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4415 break; 4416 default: 4417 BUG(); 4418 break; 4419 } 4420 4421 adev->gfx.config.gb_addr_config = gb_addr_config; 4422 4423 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4424 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4425 GB_ADDR_CONFIG, NUM_PIPES); 4426 4427 adev->gfx.config.max_tile_pipes = 4428 adev->gfx.config.gb_addr_config_fields.num_pipes; 4429 4430 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4431 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4432 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4433 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4434 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4435 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4436 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4437 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4438 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4439 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4440 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4441 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4442 } 4443 4444 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4445 int me, int pipe, int queue) 4446 { 4447 struct amdgpu_ring *ring; 4448 unsigned int irq_type; 4449 unsigned int hw_prio; 4450 4451 ring = &adev->gfx.gfx_ring[ring_id]; 4452 4453 ring->me = me; 4454 ring->pipe = pipe; 4455 ring->queue = queue; 4456 4457 ring->ring_obj = NULL; 4458 ring->use_doorbell = true; 4459 4460 if (!ring_id) 4461 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4462 else 4463 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4464 ring->vm_hub = AMDGPU_GFXHUB_0; 4465 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4466 4467 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4468 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4469 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4470 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4471 hw_prio, NULL); 4472 } 4473 4474 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4475 int mec, int pipe, int queue) 4476 { 4477 unsigned irq_type; 4478 struct amdgpu_ring *ring; 4479 unsigned int hw_prio; 4480 4481 ring = &adev->gfx.compute_ring[ring_id]; 4482 4483 /* mec0 is me1 */ 4484 ring->me = mec + 1; 4485 ring->pipe = pipe; 4486 ring->queue = queue; 4487 4488 ring->ring_obj = NULL; 4489 ring->use_doorbell = true; 4490 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4491 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4492 + (ring_id * GFX10_MEC_HPD_SIZE); 4493 ring->vm_hub = AMDGPU_GFXHUB_0; 4494 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4495 4496 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4497 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4498 + ring->pipe; 4499 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4500 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4501 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4502 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4503 hw_prio, NULL); 4504 } 4505 4506 static int gfx_v10_0_sw_init(void *handle) 4507 { 4508 int i, j, k, r, ring_id = 0; 4509 struct amdgpu_kiq *kiq; 4510 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4511 4512 switch (adev->ip_versions[GC_HWIP][0]) { 4513 case IP_VERSION(10, 1, 10): 4514 case IP_VERSION(10, 1, 1): 4515 case IP_VERSION(10, 1, 2): 4516 case IP_VERSION(10, 1, 3): 4517 case IP_VERSION(10, 1, 4): 4518 adev->gfx.me.num_me = 1; 4519 adev->gfx.me.num_pipe_per_me = 1; 4520 adev->gfx.me.num_queue_per_pipe = 1; 4521 adev->gfx.mec.num_mec = 2; 4522 adev->gfx.mec.num_pipe_per_mec = 4; 4523 adev->gfx.mec.num_queue_per_pipe = 8; 4524 break; 4525 case IP_VERSION(10, 3, 0): 4526 case IP_VERSION(10, 3, 2): 4527 case IP_VERSION(10, 3, 1): 4528 case IP_VERSION(10, 3, 4): 4529 case IP_VERSION(10, 3, 5): 4530 case IP_VERSION(10, 3, 6): 4531 case IP_VERSION(10, 3, 3): 4532 case IP_VERSION(10, 3, 7): 4533 adev->gfx.me.num_me = 1; 4534 adev->gfx.me.num_pipe_per_me = 1; 4535 adev->gfx.me.num_queue_per_pipe = 1; 4536 adev->gfx.mec.num_mec = 2; 4537 adev->gfx.mec.num_pipe_per_mec = 4; 4538 adev->gfx.mec.num_queue_per_pipe = 4; 4539 break; 4540 default: 4541 adev->gfx.me.num_me = 1; 4542 adev->gfx.me.num_pipe_per_me = 1; 4543 adev->gfx.me.num_queue_per_pipe = 1; 4544 adev->gfx.mec.num_mec = 1; 4545 adev->gfx.mec.num_pipe_per_mec = 4; 4546 adev->gfx.mec.num_queue_per_pipe = 8; 4547 break; 4548 } 4549 4550 /* KIQ event */ 4551 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4552 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4553 &adev->gfx.kiq.irq); 4554 if (r) 4555 return r; 4556 4557 /* EOP Event */ 4558 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4559 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4560 &adev->gfx.eop_irq); 4561 if (r) 4562 return r; 4563 4564 /* Privileged reg */ 4565 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4566 &adev->gfx.priv_reg_irq); 4567 if (r) 4568 return r; 4569 4570 /* Privileged inst */ 4571 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4572 &adev->gfx.priv_inst_irq); 4573 if (r) 4574 return r; 4575 4576 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4577 4578 gfx_v10_0_me_init(adev); 4579 4580 if (adev->gfx.rlc.funcs) { 4581 if (adev->gfx.rlc.funcs->init) { 4582 r = adev->gfx.rlc.funcs->init(adev); 4583 if (r) { 4584 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4585 return r; 4586 } 4587 } 4588 } 4589 4590 r = gfx_v10_0_mec_init(adev); 4591 if (r) { 4592 DRM_ERROR("Failed to init MEC BOs!\n"); 4593 return r; 4594 } 4595 4596 /* set up the gfx ring */ 4597 for (i = 0; i < adev->gfx.me.num_me; i++) { 4598 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4599 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4600 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4601 continue; 4602 4603 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4604 i, k, j); 4605 if (r) 4606 return r; 4607 ring_id++; 4608 } 4609 } 4610 } 4611 4612 ring_id = 0; 4613 /* set up the compute queues - allocate horizontally across pipes */ 4614 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4615 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4616 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4617 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4618 j)) 4619 continue; 4620 4621 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4622 i, k, j); 4623 if (r) 4624 return r; 4625 4626 ring_id++; 4627 } 4628 } 4629 } 4630 4631 if (!adev->enable_mes_kiq) { 4632 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4633 if (r) { 4634 DRM_ERROR("Failed to init KIQ BOs!\n"); 4635 return r; 4636 } 4637 4638 kiq = &adev->gfx.kiq; 4639 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4640 if (r) 4641 return r; 4642 } 4643 4644 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4645 if (r) 4646 return r; 4647 4648 /* allocate visible FB for rlc auto-loading fw */ 4649 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4650 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4651 if (r) 4652 return r; 4653 } 4654 4655 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4656 4657 gfx_v10_0_gpu_early_init(adev); 4658 4659 return 0; 4660 } 4661 4662 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4663 { 4664 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4665 &adev->gfx.pfp.pfp_fw_gpu_addr, 4666 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4667 } 4668 4669 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4670 { 4671 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4672 &adev->gfx.ce.ce_fw_gpu_addr, 4673 (void **)&adev->gfx.ce.ce_fw_ptr); 4674 } 4675 4676 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4677 { 4678 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4679 &adev->gfx.me.me_fw_gpu_addr, 4680 (void **)&adev->gfx.me.me_fw_ptr); 4681 } 4682 4683 static int gfx_v10_0_sw_fini(void *handle) 4684 { 4685 int i; 4686 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4687 4688 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4689 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4690 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4691 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4692 4693 amdgpu_gfx_mqd_sw_fini(adev); 4694 4695 if (!adev->enable_mes_kiq) { 4696 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4697 amdgpu_gfx_kiq_fini(adev); 4698 } 4699 4700 gfx_v10_0_pfp_fini(adev); 4701 gfx_v10_0_ce_fini(adev); 4702 gfx_v10_0_me_fini(adev); 4703 gfx_v10_0_rlc_fini(adev); 4704 gfx_v10_0_mec_fini(adev); 4705 4706 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4707 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4708 4709 gfx_v10_0_free_microcode(adev); 4710 4711 return 0; 4712 } 4713 4714 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4715 u32 sh_num, u32 instance) 4716 { 4717 u32 data; 4718 4719 if (instance == 0xffffffff) 4720 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4721 INSTANCE_BROADCAST_WRITES, 1); 4722 else 4723 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4724 instance); 4725 4726 if (se_num == 0xffffffff) 4727 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4728 1); 4729 else 4730 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4731 4732 if (sh_num == 0xffffffff) 4733 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4734 1); 4735 else 4736 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4737 4738 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4739 } 4740 4741 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4742 { 4743 u32 data, mask; 4744 4745 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4746 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4747 4748 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4749 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4750 4751 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4752 adev->gfx.config.max_sh_per_se); 4753 4754 return (~data) & mask; 4755 } 4756 4757 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4758 { 4759 int i, j; 4760 u32 data; 4761 u32 active_rbs = 0; 4762 u32 bitmap; 4763 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4764 adev->gfx.config.max_sh_per_se; 4765 4766 mutex_lock(&adev->grbm_idx_mutex); 4767 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4768 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4769 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4770 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 4771 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 4772 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) && 4773 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4774 continue; 4775 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4776 data = gfx_v10_0_get_rb_active_bitmap(adev); 4777 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4778 rb_bitmap_width_per_sh); 4779 } 4780 } 4781 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4782 mutex_unlock(&adev->grbm_idx_mutex); 4783 4784 adev->gfx.config.backend_enable_mask = active_rbs; 4785 adev->gfx.config.num_rbs = hweight32(active_rbs); 4786 } 4787 4788 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4789 { 4790 uint32_t num_sc; 4791 uint32_t enabled_rb_per_sh; 4792 uint32_t active_rb_bitmap; 4793 uint32_t num_rb_per_sc; 4794 uint32_t num_packer_per_sc; 4795 uint32_t pa_sc_tile_steering_override; 4796 4797 /* for ASICs that integrates GFX v10.3 4798 * pa_sc_tile_steering_override should be set to 0 */ 4799 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 4800 return 0; 4801 4802 /* init num_sc */ 4803 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4804 adev->gfx.config.num_sc_per_sh; 4805 /* init num_rb_per_sc */ 4806 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4807 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4808 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4809 /* init num_packer_per_sc */ 4810 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4811 4812 pa_sc_tile_steering_override = 0; 4813 pa_sc_tile_steering_override |= 4814 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4815 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4816 pa_sc_tile_steering_override |= 4817 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4818 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4819 pa_sc_tile_steering_override |= 4820 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4821 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4822 4823 return pa_sc_tile_steering_override; 4824 } 4825 4826 #define DEFAULT_SH_MEM_BASES (0x6000) 4827 4828 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4829 { 4830 int i; 4831 uint32_t sh_mem_bases; 4832 4833 /* 4834 * Configure apertures: 4835 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4836 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4837 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4838 */ 4839 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4840 4841 mutex_lock(&adev->srbm_mutex); 4842 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4843 nv_grbm_select(adev, 0, 0, 0, i); 4844 /* CP and shaders */ 4845 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4846 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4847 } 4848 nv_grbm_select(adev, 0, 0, 0, 0); 4849 mutex_unlock(&adev->srbm_mutex); 4850 4851 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4852 access. These should be enabled by FW for target VMIDs. */ 4853 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4854 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4855 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4856 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4857 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4858 } 4859 } 4860 4861 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4862 { 4863 int vmid; 4864 4865 /* 4866 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4867 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4868 * the driver can enable them for graphics. VMID0 should maintain 4869 * access so that HWS firmware can save/restore entries. 4870 */ 4871 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4872 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4873 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4874 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4875 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4876 } 4877 } 4878 4879 4880 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4881 { 4882 int i, j, k; 4883 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4884 u32 tmp, wgp_active_bitmap = 0; 4885 u32 gcrd_targets_disable_tcp = 0; 4886 u32 utcl_invreq_disable = 0; 4887 /* 4888 * GCRD_TARGETS_DISABLE field contains 4889 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4890 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4891 */ 4892 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4893 2 * max_wgp_per_sh + /* TCP */ 4894 max_wgp_per_sh + /* SQC */ 4895 4); /* GL1C */ 4896 /* 4897 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4898 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4899 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4900 */ 4901 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4902 2 * max_wgp_per_sh + /* TCP */ 4903 2 * max_wgp_per_sh + /* SQC */ 4904 4 + /* RMI */ 4905 1); /* SQG */ 4906 4907 mutex_lock(&adev->grbm_idx_mutex); 4908 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4909 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4910 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4911 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4912 /* 4913 * Set corresponding TCP bits for the inactive WGPs in 4914 * GCRD_SA_TARGETS_DISABLE 4915 */ 4916 gcrd_targets_disable_tcp = 0; 4917 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4918 utcl_invreq_disable = 0; 4919 4920 for (k = 0; k < max_wgp_per_sh; k++) { 4921 if (!(wgp_active_bitmap & (1 << k))) { 4922 gcrd_targets_disable_tcp |= 3 << (2 * k); 4923 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 4924 utcl_invreq_disable |= (3 << (2 * k)) | 4925 (3 << (2 * (max_wgp_per_sh + k))); 4926 } 4927 } 4928 4929 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4930 /* only override TCP & SQC bits */ 4931 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 4932 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4933 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4934 4935 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4936 /* only override TCP & SQC bits */ 4937 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 4938 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4939 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4940 } 4941 } 4942 4943 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4944 mutex_unlock(&adev->grbm_idx_mutex); 4945 } 4946 4947 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4948 { 4949 /* TCCs are global (not instanced). */ 4950 uint32_t tcc_disable; 4951 4952 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 4953 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 4954 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 4955 } else { 4956 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4957 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4958 } 4959 4960 adev->gfx.config.tcc_disabled_mask = 4961 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4962 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4963 } 4964 4965 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4966 { 4967 u32 tmp; 4968 int i; 4969 4970 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4971 4972 gfx_v10_0_setup_rb(adev); 4973 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4974 gfx_v10_0_get_tcc_info(adev); 4975 adev->gfx.config.pa_sc_tile_steering_override = 4976 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4977 4978 /* XXX SH_MEM regs */ 4979 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4980 mutex_lock(&adev->srbm_mutex); 4981 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 4982 nv_grbm_select(adev, 0, 0, 0, i); 4983 /* CP and shaders */ 4984 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4985 if (i != 0) { 4986 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4987 (adev->gmc.private_aperture_start >> 48)); 4988 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4989 (adev->gmc.shared_aperture_start >> 48)); 4990 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4991 } 4992 } 4993 nv_grbm_select(adev, 0, 0, 0, 0); 4994 4995 mutex_unlock(&adev->srbm_mutex); 4996 4997 gfx_v10_0_init_compute_vmid(adev); 4998 gfx_v10_0_init_gds_vmid(adev); 4999 5000 } 5001 5002 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5003 bool enable) 5004 { 5005 u32 tmp; 5006 5007 if (amdgpu_sriov_vf(adev)) 5008 return; 5009 5010 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5011 5012 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5013 enable ? 1 : 0); 5014 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5015 enable ? 1 : 0); 5016 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5017 enable ? 1 : 0); 5018 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5019 enable ? 1 : 0); 5020 5021 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5022 } 5023 5024 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5025 { 5026 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5027 5028 /* csib */ 5029 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5030 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5031 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5032 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5033 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5034 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5035 } else { 5036 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5037 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5038 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5039 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5040 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5041 } 5042 return 0; 5043 } 5044 5045 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5046 { 5047 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5048 5049 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5050 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5051 } 5052 5053 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5054 { 5055 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5056 udelay(50); 5057 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5058 udelay(50); 5059 } 5060 5061 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5062 bool enable) 5063 { 5064 uint32_t rlc_pg_cntl; 5065 5066 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5067 5068 if (!enable) { 5069 /* RLC_PG_CNTL[23] = 0 (default) 5070 * RLC will wait for handshake acks with SMU 5071 * GFXOFF will be enabled 5072 * RLC_PG_CNTL[23] = 1 5073 * RLC will not issue any message to SMU 5074 * hence no handshake between SMU & RLC 5075 * GFXOFF will be disabled 5076 */ 5077 rlc_pg_cntl |= 0x800000; 5078 } else 5079 rlc_pg_cntl &= ~0x800000; 5080 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5081 } 5082 5083 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5084 { 5085 /* TODO: enable rlc & smu handshake until smu 5086 * and gfxoff feature works as expected */ 5087 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5088 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5089 5090 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5091 udelay(50); 5092 } 5093 5094 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5095 { 5096 uint32_t tmp; 5097 5098 /* enable Save Restore Machine */ 5099 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5100 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5101 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5102 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5103 } 5104 5105 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5106 { 5107 const struct rlc_firmware_header_v2_0 *hdr; 5108 const __le32 *fw_data; 5109 unsigned i, fw_size; 5110 5111 if (!adev->gfx.rlc_fw) 5112 return -EINVAL; 5113 5114 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5115 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5116 5117 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5118 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5119 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5120 5121 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5122 RLCG_UCODE_LOADING_START_ADDRESS); 5123 5124 for (i = 0; i < fw_size; i++) 5125 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5126 le32_to_cpup(fw_data++)); 5127 5128 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5129 5130 return 0; 5131 } 5132 5133 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5134 { 5135 int r; 5136 5137 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5138 adev->psp.autoload_supported) { 5139 5140 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5141 if (r) 5142 return r; 5143 5144 gfx_v10_0_init_csb(adev); 5145 5146 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5147 gfx_v10_0_rlc_enable_srm(adev); 5148 } else { 5149 if (amdgpu_sriov_vf(adev)) { 5150 gfx_v10_0_init_csb(adev); 5151 return 0; 5152 } 5153 5154 adev->gfx.rlc.funcs->stop(adev); 5155 5156 /* disable CG */ 5157 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5158 5159 /* disable PG */ 5160 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5161 5162 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5163 /* legacy rlc firmware loading */ 5164 r = gfx_v10_0_rlc_load_microcode(adev); 5165 if (r) 5166 return r; 5167 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5168 /* rlc backdoor autoload firmware */ 5169 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5170 if (r) 5171 return r; 5172 } 5173 5174 gfx_v10_0_init_csb(adev); 5175 5176 adev->gfx.rlc.funcs->start(adev); 5177 5178 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5179 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5180 if (r) 5181 return r; 5182 } 5183 } 5184 return 0; 5185 } 5186 5187 static struct { 5188 FIRMWARE_ID id; 5189 unsigned int offset; 5190 unsigned int size; 5191 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5192 5193 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5194 { 5195 int ret; 5196 RLC_TABLE_OF_CONTENT *rlc_toc; 5197 5198 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5199 AMDGPU_GEM_DOMAIN_GTT, 5200 &adev->gfx.rlc.rlc_toc_bo, 5201 &adev->gfx.rlc.rlc_toc_gpu_addr, 5202 (void **)&adev->gfx.rlc.rlc_toc_buf); 5203 if (ret) { 5204 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5205 return ret; 5206 } 5207 5208 /* Copy toc from psp sos fw to rlc toc buffer */ 5209 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5210 5211 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5212 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5213 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5214 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5215 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5216 /* Offset needs 4KB alignment */ 5217 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5218 } 5219 5220 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5221 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5222 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5223 5224 rlc_toc++; 5225 } 5226 5227 return 0; 5228 } 5229 5230 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5231 { 5232 uint32_t total_size = 0; 5233 FIRMWARE_ID id; 5234 int ret; 5235 5236 ret = gfx_v10_0_parse_rlc_toc(adev); 5237 if (ret) { 5238 dev_err(adev->dev, "failed to parse rlc toc\n"); 5239 return 0; 5240 } 5241 5242 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5243 total_size += rlc_autoload_info[id].size; 5244 5245 /* In case the offset in rlc toc ucode is aligned */ 5246 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5247 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5248 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5249 5250 return total_size; 5251 } 5252 5253 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5254 { 5255 int r; 5256 uint32_t total_size; 5257 5258 total_size = gfx_v10_0_calc_toc_total_size(adev); 5259 5260 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5261 AMDGPU_GEM_DOMAIN_GTT, 5262 &adev->gfx.rlc.rlc_autoload_bo, 5263 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5264 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5265 if (r) { 5266 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5267 return r; 5268 } 5269 5270 return 0; 5271 } 5272 5273 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5274 { 5275 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5276 &adev->gfx.rlc.rlc_toc_gpu_addr, 5277 (void **)&adev->gfx.rlc.rlc_toc_buf); 5278 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5279 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5280 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5281 } 5282 5283 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5284 FIRMWARE_ID id, 5285 const void *fw_data, 5286 uint32_t fw_size) 5287 { 5288 uint32_t toc_offset; 5289 uint32_t toc_fw_size; 5290 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5291 5292 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5293 return; 5294 5295 toc_offset = rlc_autoload_info[id].offset; 5296 toc_fw_size = rlc_autoload_info[id].size; 5297 5298 if (fw_size == 0) 5299 fw_size = toc_fw_size; 5300 5301 if (fw_size > toc_fw_size) 5302 fw_size = toc_fw_size; 5303 5304 memcpy(ptr + toc_offset, fw_data, fw_size); 5305 5306 if (fw_size < toc_fw_size) 5307 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5308 } 5309 5310 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5311 { 5312 void *data; 5313 uint32_t size; 5314 5315 data = adev->gfx.rlc.rlc_toc_buf; 5316 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5317 5318 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5319 FIRMWARE_ID_RLC_TOC, 5320 data, size); 5321 } 5322 5323 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5324 { 5325 const __le32 *fw_data; 5326 uint32_t fw_size; 5327 const struct gfx_firmware_header_v1_0 *cp_hdr; 5328 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5329 5330 /* pfp ucode */ 5331 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5332 adev->gfx.pfp_fw->data; 5333 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5334 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5335 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5336 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5337 FIRMWARE_ID_CP_PFP, 5338 fw_data, fw_size); 5339 5340 /* ce ucode */ 5341 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5342 adev->gfx.ce_fw->data; 5343 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5344 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5345 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5346 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5347 FIRMWARE_ID_CP_CE, 5348 fw_data, fw_size); 5349 5350 /* me ucode */ 5351 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5352 adev->gfx.me_fw->data; 5353 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5354 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5355 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5356 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5357 FIRMWARE_ID_CP_ME, 5358 fw_data, fw_size); 5359 5360 /* rlc ucode */ 5361 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5362 adev->gfx.rlc_fw->data; 5363 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5364 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5365 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5366 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5367 FIRMWARE_ID_RLC_G_UCODE, 5368 fw_data, fw_size); 5369 5370 /* mec1 ucode */ 5371 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5372 adev->gfx.mec_fw->data; 5373 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5374 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5375 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5376 cp_hdr->jt_size * 4; 5377 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5378 FIRMWARE_ID_CP_MEC, 5379 fw_data, fw_size); 5380 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5381 } 5382 5383 /* Temporarily put sdma part here */ 5384 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5385 { 5386 const __le32 *fw_data; 5387 uint32_t fw_size; 5388 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5389 int i; 5390 5391 for (i = 0; i < adev->sdma.num_instances; i++) { 5392 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5393 adev->sdma.instance[i].fw->data; 5394 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5395 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5396 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5397 5398 if (i == 0) { 5399 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5400 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5401 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5402 FIRMWARE_ID_SDMA0_JT, 5403 (uint32_t *)fw_data + 5404 sdma_hdr->jt_offset, 5405 sdma_hdr->jt_size * 4); 5406 } else if (i == 1) { 5407 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5408 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5409 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5410 FIRMWARE_ID_SDMA1_JT, 5411 (uint32_t *)fw_data + 5412 sdma_hdr->jt_offset, 5413 sdma_hdr->jt_size * 4); 5414 } 5415 } 5416 } 5417 5418 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5419 { 5420 uint32_t rlc_g_offset, rlc_g_size, tmp; 5421 uint64_t gpu_addr; 5422 5423 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5424 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5425 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5426 5427 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5428 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5429 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5430 5431 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5432 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5433 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5434 5435 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5436 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5437 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5438 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5439 return -EINVAL; 5440 } 5441 5442 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5443 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5444 DRM_ERROR("RLC ROM should halt itself\n"); 5445 return -EINVAL; 5446 } 5447 5448 return 0; 5449 } 5450 5451 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5452 { 5453 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5454 uint32_t tmp; 5455 int i; 5456 uint64_t addr; 5457 5458 /* Trigger an invalidation of the L1 instruction caches */ 5459 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5460 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5461 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5462 5463 /* Wait for invalidation complete */ 5464 for (i = 0; i < usec_timeout; i++) { 5465 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5466 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5467 INVALIDATE_CACHE_COMPLETE)) 5468 break; 5469 udelay(1); 5470 } 5471 5472 if (i >= usec_timeout) { 5473 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5474 return -EINVAL; 5475 } 5476 5477 /* Program me ucode address into intruction cache address register */ 5478 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5479 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5480 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5481 lower_32_bits(addr) & 0xFFFFF000); 5482 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5483 upper_32_bits(addr)); 5484 5485 return 0; 5486 } 5487 5488 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5489 { 5490 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5491 uint32_t tmp; 5492 int i; 5493 uint64_t addr; 5494 5495 /* Trigger an invalidation of the L1 instruction caches */ 5496 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5497 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5498 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5499 5500 /* Wait for invalidation complete */ 5501 for (i = 0; i < usec_timeout; i++) { 5502 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5503 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5504 INVALIDATE_CACHE_COMPLETE)) 5505 break; 5506 udelay(1); 5507 } 5508 5509 if (i >= usec_timeout) { 5510 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5511 return -EINVAL; 5512 } 5513 5514 /* Program ce ucode address into intruction cache address register */ 5515 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5516 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5517 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5518 lower_32_bits(addr) & 0xFFFFF000); 5519 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5520 upper_32_bits(addr)); 5521 5522 return 0; 5523 } 5524 5525 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5526 { 5527 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5528 uint32_t tmp; 5529 int i; 5530 uint64_t addr; 5531 5532 /* Trigger an invalidation of the L1 instruction caches */ 5533 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5534 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5535 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5536 5537 /* Wait for invalidation complete */ 5538 for (i = 0; i < usec_timeout; i++) { 5539 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5540 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5541 INVALIDATE_CACHE_COMPLETE)) 5542 break; 5543 udelay(1); 5544 } 5545 5546 if (i >= usec_timeout) { 5547 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5548 return -EINVAL; 5549 } 5550 5551 /* Program pfp ucode address into intruction cache address register */ 5552 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5553 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5554 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5555 lower_32_bits(addr) & 0xFFFFF000); 5556 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5557 upper_32_bits(addr)); 5558 5559 return 0; 5560 } 5561 5562 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5563 { 5564 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5565 uint32_t tmp; 5566 int i; 5567 uint64_t addr; 5568 5569 /* Trigger an invalidation of the L1 instruction caches */ 5570 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5571 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5572 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5573 5574 /* Wait for invalidation complete */ 5575 for (i = 0; i < usec_timeout; i++) { 5576 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5577 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5578 INVALIDATE_CACHE_COMPLETE)) 5579 break; 5580 udelay(1); 5581 } 5582 5583 if (i >= usec_timeout) { 5584 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5585 return -EINVAL; 5586 } 5587 5588 /* Program mec1 ucode address into intruction cache address register */ 5589 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5590 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5591 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5592 lower_32_bits(addr) & 0xFFFFF000); 5593 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5594 upper_32_bits(addr)); 5595 5596 return 0; 5597 } 5598 5599 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5600 { 5601 uint32_t cp_status; 5602 uint32_t bootload_status; 5603 int i, r; 5604 5605 for (i = 0; i < adev->usec_timeout; i++) { 5606 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5607 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5608 if ((cp_status == 0) && 5609 (REG_GET_FIELD(bootload_status, 5610 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5611 break; 5612 } 5613 udelay(1); 5614 } 5615 5616 if (i >= adev->usec_timeout) { 5617 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5618 return -ETIMEDOUT; 5619 } 5620 5621 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5622 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5623 if (r) 5624 return r; 5625 5626 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5627 if (r) 5628 return r; 5629 5630 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5631 if (r) 5632 return r; 5633 5634 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5635 if (r) 5636 return r; 5637 } 5638 5639 return 0; 5640 } 5641 5642 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5643 { 5644 int i; 5645 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5646 5647 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5648 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5649 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5650 5651 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5652 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5653 } else { 5654 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5655 } 5656 5657 if (adev->job_hang && !enable) 5658 return 0; 5659 5660 for (i = 0; i < adev->usec_timeout; i++) { 5661 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5662 break; 5663 udelay(1); 5664 } 5665 5666 if (i >= adev->usec_timeout) 5667 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5668 5669 return 0; 5670 } 5671 5672 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5673 { 5674 int r; 5675 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5676 const __le32 *fw_data; 5677 unsigned i, fw_size; 5678 uint32_t tmp; 5679 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5680 5681 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5682 adev->gfx.pfp_fw->data; 5683 5684 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5685 5686 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5687 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5688 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5689 5690 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5691 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5692 &adev->gfx.pfp.pfp_fw_obj, 5693 &adev->gfx.pfp.pfp_fw_gpu_addr, 5694 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5695 if (r) { 5696 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5697 gfx_v10_0_pfp_fini(adev); 5698 return r; 5699 } 5700 5701 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5702 5703 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5704 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5705 5706 /* Trigger an invalidation of the L1 instruction caches */ 5707 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5708 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5709 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5710 5711 /* Wait for invalidation complete */ 5712 for (i = 0; i < usec_timeout; i++) { 5713 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5714 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5715 INVALIDATE_CACHE_COMPLETE)) 5716 break; 5717 udelay(1); 5718 } 5719 5720 if (i >= usec_timeout) { 5721 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5722 return -EINVAL; 5723 } 5724 5725 if (amdgpu_emu_mode == 1) 5726 adev->hdp.funcs->flush_hdp(adev, NULL); 5727 5728 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5729 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5730 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5731 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5732 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5733 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5734 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5735 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5736 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5737 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5738 5739 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5740 5741 for (i = 0; i < pfp_hdr->jt_size; i++) 5742 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5743 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5744 5745 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5746 5747 return 0; 5748 } 5749 5750 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5751 { 5752 int r; 5753 const struct gfx_firmware_header_v1_0 *ce_hdr; 5754 const __le32 *fw_data; 5755 unsigned i, fw_size; 5756 uint32_t tmp; 5757 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5758 5759 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5760 adev->gfx.ce_fw->data; 5761 5762 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5763 5764 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5765 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5766 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5767 5768 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5769 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5770 &adev->gfx.ce.ce_fw_obj, 5771 &adev->gfx.ce.ce_fw_gpu_addr, 5772 (void **)&adev->gfx.ce.ce_fw_ptr); 5773 if (r) { 5774 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5775 gfx_v10_0_ce_fini(adev); 5776 return r; 5777 } 5778 5779 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5780 5781 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5782 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5783 5784 /* Trigger an invalidation of the L1 instruction caches */ 5785 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5786 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5787 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5788 5789 /* Wait for invalidation complete */ 5790 for (i = 0; i < usec_timeout; i++) { 5791 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5792 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5793 INVALIDATE_CACHE_COMPLETE)) 5794 break; 5795 udelay(1); 5796 } 5797 5798 if (i >= usec_timeout) { 5799 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5800 return -EINVAL; 5801 } 5802 5803 if (amdgpu_emu_mode == 1) 5804 adev->hdp.funcs->flush_hdp(adev, NULL); 5805 5806 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5807 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5808 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5809 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5810 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5811 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5812 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5813 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5814 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5815 5816 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5817 5818 for (i = 0; i < ce_hdr->jt_size; i++) 5819 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5820 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5821 5822 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5823 5824 return 0; 5825 } 5826 5827 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5828 { 5829 int r; 5830 const struct gfx_firmware_header_v1_0 *me_hdr; 5831 const __le32 *fw_data; 5832 unsigned i, fw_size; 5833 uint32_t tmp; 5834 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5835 5836 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5837 adev->gfx.me_fw->data; 5838 5839 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5840 5841 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5842 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5843 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5844 5845 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5846 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5847 &adev->gfx.me.me_fw_obj, 5848 &adev->gfx.me.me_fw_gpu_addr, 5849 (void **)&adev->gfx.me.me_fw_ptr); 5850 if (r) { 5851 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5852 gfx_v10_0_me_fini(adev); 5853 return r; 5854 } 5855 5856 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5857 5858 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5859 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5860 5861 /* Trigger an invalidation of the L1 instruction caches */ 5862 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5863 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5864 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5865 5866 /* Wait for invalidation complete */ 5867 for (i = 0; i < usec_timeout; i++) { 5868 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5869 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5870 INVALIDATE_CACHE_COMPLETE)) 5871 break; 5872 udelay(1); 5873 } 5874 5875 if (i >= usec_timeout) { 5876 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5877 return -EINVAL; 5878 } 5879 5880 if (amdgpu_emu_mode == 1) 5881 adev->hdp.funcs->flush_hdp(adev, NULL); 5882 5883 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5884 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5885 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5886 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5887 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5888 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5889 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5890 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5891 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5892 5893 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5894 5895 for (i = 0; i < me_hdr->jt_size; i++) 5896 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5897 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5898 5899 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5900 5901 return 0; 5902 } 5903 5904 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5905 { 5906 int r; 5907 5908 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5909 return -EINVAL; 5910 5911 gfx_v10_0_cp_gfx_enable(adev, false); 5912 5913 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5914 if (r) { 5915 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5916 return r; 5917 } 5918 5919 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5920 if (r) { 5921 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5922 return r; 5923 } 5924 5925 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5926 if (r) { 5927 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5928 return r; 5929 } 5930 5931 return 0; 5932 } 5933 5934 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5935 { 5936 struct amdgpu_ring *ring; 5937 const struct cs_section_def *sect = NULL; 5938 const struct cs_extent_def *ext = NULL; 5939 int r, i; 5940 int ctx_reg_offset; 5941 5942 /* init the CP */ 5943 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5944 adev->gfx.config.max_hw_contexts - 1); 5945 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5946 5947 gfx_v10_0_cp_gfx_enable(adev, true); 5948 5949 ring = &adev->gfx.gfx_ring[0]; 5950 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5951 if (r) { 5952 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5953 return r; 5954 } 5955 5956 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5957 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5958 5959 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5960 amdgpu_ring_write(ring, 0x80000000); 5961 amdgpu_ring_write(ring, 0x80000000); 5962 5963 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5964 for (ext = sect->section; ext->extent != NULL; ++ext) { 5965 if (sect->id == SECT_CONTEXT) { 5966 amdgpu_ring_write(ring, 5967 PACKET3(PACKET3_SET_CONTEXT_REG, 5968 ext->reg_count)); 5969 amdgpu_ring_write(ring, ext->reg_index - 5970 PACKET3_SET_CONTEXT_REG_START); 5971 for (i = 0; i < ext->reg_count; i++) 5972 amdgpu_ring_write(ring, ext->extent[i]); 5973 } 5974 } 5975 } 5976 5977 ctx_reg_offset = 5978 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5979 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5980 amdgpu_ring_write(ring, ctx_reg_offset); 5981 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5982 5983 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5984 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5985 5986 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5987 amdgpu_ring_write(ring, 0); 5988 5989 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 5990 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 5991 amdgpu_ring_write(ring, 0x8000); 5992 amdgpu_ring_write(ring, 0x8000); 5993 5994 amdgpu_ring_commit(ring); 5995 5996 /* submit cs packet to copy state 0 to next available state */ 5997 if (adev->gfx.num_gfx_rings > 1) { 5998 /* maximum supported gfx ring is 2 */ 5999 ring = &adev->gfx.gfx_ring[1]; 6000 r = amdgpu_ring_alloc(ring, 2); 6001 if (r) { 6002 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6003 return r; 6004 } 6005 6006 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6007 amdgpu_ring_write(ring, 0); 6008 6009 amdgpu_ring_commit(ring); 6010 } 6011 return 0; 6012 } 6013 6014 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6015 CP_PIPE_ID pipe) 6016 { 6017 u32 tmp; 6018 6019 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6020 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6021 6022 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6023 } 6024 6025 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6026 struct amdgpu_ring *ring) 6027 { 6028 u32 tmp; 6029 6030 if (!amdgpu_async_gfx_ring) { 6031 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6032 if (ring->use_doorbell) { 6033 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6034 DOORBELL_OFFSET, ring->doorbell_index); 6035 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6036 DOORBELL_EN, 1); 6037 } else { 6038 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6039 DOORBELL_EN, 0); 6040 } 6041 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6042 } 6043 switch (adev->ip_versions[GC_HWIP][0]) { 6044 case IP_VERSION(10, 3, 0): 6045 case IP_VERSION(10, 3, 2): 6046 case IP_VERSION(10, 3, 1): 6047 case IP_VERSION(10, 3, 4): 6048 case IP_VERSION(10, 3, 5): 6049 case IP_VERSION(10, 3, 6): 6050 case IP_VERSION(10, 3, 3): 6051 case IP_VERSION(10, 3, 7): 6052 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6053 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6054 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6055 6056 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6057 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6058 break; 6059 default: 6060 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6061 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6062 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6063 6064 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6065 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6066 break; 6067 } 6068 } 6069 6070 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6071 { 6072 struct amdgpu_ring *ring; 6073 u32 tmp; 6074 u32 rb_bufsz; 6075 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6076 u32 i; 6077 6078 /* Set the write pointer delay */ 6079 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6080 6081 /* set the RB to use vmid 0 */ 6082 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6083 6084 /* Init gfx ring 0 for pipe 0 */ 6085 mutex_lock(&adev->srbm_mutex); 6086 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6087 6088 /* Set ring buffer size */ 6089 ring = &adev->gfx.gfx_ring[0]; 6090 rb_bufsz = order_base_2(ring->ring_size / 8); 6091 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6092 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6093 #ifdef __BIG_ENDIAN 6094 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6095 #endif 6096 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6097 6098 /* Initialize the ring buffer's write pointers */ 6099 ring->wptr = 0; 6100 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6101 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6102 6103 /* set the wb address wether it's enabled or not */ 6104 rptr_addr = ring->rptr_gpu_addr; 6105 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6106 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6107 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6108 6109 wptr_gpu_addr = ring->wptr_gpu_addr; 6110 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6111 lower_32_bits(wptr_gpu_addr)); 6112 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6113 upper_32_bits(wptr_gpu_addr)); 6114 6115 mdelay(1); 6116 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6117 6118 rb_addr = ring->gpu_addr >> 8; 6119 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6120 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6121 6122 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6123 6124 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6125 mutex_unlock(&adev->srbm_mutex); 6126 6127 /* Init gfx ring 1 for pipe 1 */ 6128 if (adev->gfx.num_gfx_rings > 1) { 6129 mutex_lock(&adev->srbm_mutex); 6130 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6131 /* maximum supported gfx ring is 2 */ 6132 ring = &adev->gfx.gfx_ring[1]; 6133 rb_bufsz = order_base_2(ring->ring_size / 8); 6134 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6135 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6136 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6137 /* Initialize the ring buffer's write pointers */ 6138 ring->wptr = 0; 6139 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6140 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6141 /* Set the wb address wether it's enabled or not */ 6142 rptr_addr = ring->rptr_gpu_addr; 6143 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6144 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6145 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6146 wptr_gpu_addr = ring->wptr_gpu_addr; 6147 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6148 lower_32_bits(wptr_gpu_addr)); 6149 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6150 upper_32_bits(wptr_gpu_addr)); 6151 6152 mdelay(1); 6153 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6154 6155 rb_addr = ring->gpu_addr >> 8; 6156 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6157 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6158 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6159 6160 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6161 mutex_unlock(&adev->srbm_mutex); 6162 } 6163 /* Switch to pipe 0 */ 6164 mutex_lock(&adev->srbm_mutex); 6165 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6166 mutex_unlock(&adev->srbm_mutex); 6167 6168 /* start the ring */ 6169 gfx_v10_0_cp_gfx_start(adev); 6170 6171 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6172 ring = &adev->gfx.gfx_ring[i]; 6173 ring->sched.ready = true; 6174 } 6175 6176 return 0; 6177 } 6178 6179 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6180 { 6181 if (enable) { 6182 switch (adev->ip_versions[GC_HWIP][0]) { 6183 case IP_VERSION(10, 3, 0): 6184 case IP_VERSION(10, 3, 2): 6185 case IP_VERSION(10, 3, 1): 6186 case IP_VERSION(10, 3, 4): 6187 case IP_VERSION(10, 3, 5): 6188 case IP_VERSION(10, 3, 6): 6189 case IP_VERSION(10, 3, 3): 6190 case IP_VERSION(10, 3, 7): 6191 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6192 break; 6193 default: 6194 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6195 break; 6196 } 6197 } else { 6198 switch (adev->ip_versions[GC_HWIP][0]) { 6199 case IP_VERSION(10, 3, 0): 6200 case IP_VERSION(10, 3, 2): 6201 case IP_VERSION(10, 3, 1): 6202 case IP_VERSION(10, 3, 4): 6203 case IP_VERSION(10, 3, 5): 6204 case IP_VERSION(10, 3, 6): 6205 case IP_VERSION(10, 3, 3): 6206 case IP_VERSION(10, 3, 7): 6207 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6208 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6209 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6210 break; 6211 default: 6212 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6213 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6214 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6215 break; 6216 } 6217 adev->gfx.kiq.ring.sched.ready = false; 6218 } 6219 udelay(50); 6220 } 6221 6222 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6223 { 6224 const struct gfx_firmware_header_v1_0 *mec_hdr; 6225 const __le32 *fw_data; 6226 unsigned i; 6227 u32 tmp; 6228 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6229 6230 if (!adev->gfx.mec_fw) 6231 return -EINVAL; 6232 6233 gfx_v10_0_cp_compute_enable(adev, false); 6234 6235 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6236 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6237 6238 fw_data = (const __le32 *) 6239 (adev->gfx.mec_fw->data + 6240 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6241 6242 /* Trigger an invalidation of the L1 instruction caches */ 6243 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6244 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6245 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6246 6247 /* Wait for invalidation complete */ 6248 for (i = 0; i < usec_timeout; i++) { 6249 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6250 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6251 INVALIDATE_CACHE_COMPLETE)) 6252 break; 6253 udelay(1); 6254 } 6255 6256 if (i >= usec_timeout) { 6257 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6258 return -EINVAL; 6259 } 6260 6261 if (amdgpu_emu_mode == 1) 6262 adev->hdp.funcs->flush_hdp(adev, NULL); 6263 6264 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6265 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6266 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6267 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6268 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6269 6270 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6271 0xFFFFF000); 6272 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6273 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6274 6275 /* MEC1 */ 6276 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6277 6278 for (i = 0; i < mec_hdr->jt_size; i++) 6279 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6280 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6281 6282 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6283 6284 /* 6285 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6286 * different microcode than MEC1. 6287 */ 6288 6289 return 0; 6290 } 6291 6292 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6293 { 6294 uint32_t tmp; 6295 struct amdgpu_device *adev = ring->adev; 6296 6297 /* tell RLC which is KIQ queue */ 6298 switch (adev->ip_versions[GC_HWIP][0]) { 6299 case IP_VERSION(10, 3, 0): 6300 case IP_VERSION(10, 3, 2): 6301 case IP_VERSION(10, 3, 1): 6302 case IP_VERSION(10, 3, 4): 6303 case IP_VERSION(10, 3, 5): 6304 case IP_VERSION(10, 3, 6): 6305 case IP_VERSION(10, 3, 3): 6306 case IP_VERSION(10, 3, 7): 6307 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6308 tmp &= 0xffffff00; 6309 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6310 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6311 tmp |= 0x80; 6312 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6313 break; 6314 default: 6315 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6316 tmp &= 0xffffff00; 6317 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6318 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6319 tmp |= 0x80; 6320 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6321 break; 6322 } 6323 } 6324 6325 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6326 struct v10_gfx_mqd *mqd, 6327 struct amdgpu_mqd_prop *prop) 6328 { 6329 bool priority = 0; 6330 u32 tmp; 6331 6332 /* set up default queue priority level 6333 * 0x0 = low priority, 0x1 = high priority 6334 */ 6335 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6336 priority = 1; 6337 6338 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6339 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6340 mqd->cp_gfx_hqd_queue_priority = tmp; 6341 } 6342 6343 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6344 struct amdgpu_mqd_prop *prop) 6345 { 6346 struct v10_gfx_mqd *mqd = m; 6347 uint64_t hqd_gpu_addr, wb_gpu_addr; 6348 uint32_t tmp; 6349 uint32_t rb_bufsz; 6350 6351 /* set up gfx hqd wptr */ 6352 mqd->cp_gfx_hqd_wptr = 0; 6353 mqd->cp_gfx_hqd_wptr_hi = 0; 6354 6355 /* set the pointer to the MQD */ 6356 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6357 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6358 6359 /* set up mqd control */ 6360 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6361 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6362 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6363 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6364 mqd->cp_gfx_mqd_control = tmp; 6365 6366 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6367 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6368 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6369 mqd->cp_gfx_hqd_vmid = 0; 6370 6371 /* set up gfx queue priority */ 6372 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6373 6374 /* set up time quantum */ 6375 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6376 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6377 mqd->cp_gfx_hqd_quantum = tmp; 6378 6379 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6380 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6381 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6382 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6383 6384 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6385 wb_gpu_addr = prop->rptr_gpu_addr; 6386 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6387 mqd->cp_gfx_hqd_rptr_addr_hi = 6388 upper_32_bits(wb_gpu_addr) & 0xffff; 6389 6390 /* set up rb_wptr_poll addr */ 6391 wb_gpu_addr = prop->wptr_gpu_addr; 6392 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6393 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6394 6395 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6396 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6397 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6398 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6399 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6400 #ifdef __BIG_ENDIAN 6401 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6402 #endif 6403 mqd->cp_gfx_hqd_cntl = tmp; 6404 6405 /* set up cp_doorbell_control */ 6406 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6407 if (prop->use_doorbell) { 6408 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6409 DOORBELL_OFFSET, prop->doorbell_index); 6410 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6411 DOORBELL_EN, 1); 6412 } else 6413 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6414 DOORBELL_EN, 0); 6415 mqd->cp_rb_doorbell_control = tmp; 6416 6417 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6418 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6419 6420 /* active the queue */ 6421 mqd->cp_gfx_hqd_active = 1; 6422 6423 return 0; 6424 } 6425 6426 #ifdef BRING_UP_DEBUG 6427 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6428 { 6429 struct amdgpu_device *adev = ring->adev; 6430 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6431 6432 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6433 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6434 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6435 6436 /* set GFX_MQD_BASE */ 6437 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6438 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6439 6440 /* set GFX_MQD_CONTROL */ 6441 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6442 6443 /* set GFX_HQD_VMID to 0 */ 6444 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6445 6446 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6447 mqd->cp_gfx_hqd_queue_priority); 6448 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6449 6450 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6451 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6452 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6453 6454 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6455 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6456 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6457 6458 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6459 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6460 6461 /* set RB_WPTR_POLL_ADDR */ 6462 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6463 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6464 6465 /* set RB_DOORBELL_CONTROL */ 6466 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6467 6468 /* active the queue */ 6469 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6470 6471 return 0; 6472 } 6473 #endif 6474 6475 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6476 { 6477 struct amdgpu_device *adev = ring->adev; 6478 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6479 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6480 6481 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6482 memset((void *)mqd, 0, sizeof(*mqd)); 6483 mutex_lock(&adev->srbm_mutex); 6484 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6485 amdgpu_ring_init_mqd(ring); 6486 6487 /* 6488 * if there are 2 gfx rings, set the lower doorbell 6489 * range of the first ring, otherwise the range of 6490 * the second ring will override the first ring 6491 */ 6492 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6493 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6494 6495 #ifdef BRING_UP_DEBUG 6496 gfx_v10_0_gfx_queue_init_register(ring); 6497 #endif 6498 nv_grbm_select(adev, 0, 0, 0, 0); 6499 mutex_unlock(&adev->srbm_mutex); 6500 if (adev->gfx.me.mqd_backup[mqd_idx]) 6501 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6502 } else if (amdgpu_in_reset(adev)) { 6503 /* reset mqd with the backup copy */ 6504 if (adev->gfx.me.mqd_backup[mqd_idx]) 6505 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6506 /* reset the ring */ 6507 ring->wptr = 0; 6508 *ring->wptr_cpu_addr = 0; 6509 amdgpu_ring_clear_ring(ring); 6510 #ifdef BRING_UP_DEBUG 6511 mutex_lock(&adev->srbm_mutex); 6512 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6513 gfx_v10_0_gfx_queue_init_register(ring); 6514 nv_grbm_select(adev, 0, 0, 0, 0); 6515 mutex_unlock(&adev->srbm_mutex); 6516 #endif 6517 } else { 6518 amdgpu_ring_clear_ring(ring); 6519 } 6520 6521 return 0; 6522 } 6523 6524 #ifndef BRING_UP_DEBUG 6525 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6526 { 6527 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6528 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6529 int r, i; 6530 6531 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6532 return -EINVAL; 6533 6534 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6535 adev->gfx.num_gfx_rings); 6536 if (r) { 6537 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6538 return r; 6539 } 6540 6541 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6542 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6543 6544 return amdgpu_ring_test_helper(kiq_ring); 6545 } 6546 #endif 6547 6548 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6549 { 6550 int r, i; 6551 struct amdgpu_ring *ring; 6552 6553 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6554 ring = &adev->gfx.gfx_ring[i]; 6555 6556 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6557 if (unlikely(r != 0)) 6558 goto done; 6559 6560 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6561 if (!r) { 6562 r = gfx_v10_0_gfx_init_queue(ring); 6563 amdgpu_bo_kunmap(ring->mqd_obj); 6564 ring->mqd_ptr = NULL; 6565 } 6566 amdgpu_bo_unreserve(ring->mqd_obj); 6567 if (r) 6568 goto done; 6569 } 6570 #ifndef BRING_UP_DEBUG 6571 r = gfx_v10_0_kiq_enable_kgq(adev); 6572 if (r) 6573 goto done; 6574 #endif 6575 r = gfx_v10_0_cp_gfx_start(adev); 6576 if (r) 6577 goto done; 6578 6579 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6580 ring = &adev->gfx.gfx_ring[i]; 6581 ring->sched.ready = true; 6582 } 6583 done: 6584 return r; 6585 } 6586 6587 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6588 struct amdgpu_mqd_prop *prop) 6589 { 6590 struct v10_compute_mqd *mqd = m; 6591 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6592 uint32_t tmp; 6593 6594 mqd->header = 0xC0310800; 6595 mqd->compute_pipelinestat_enable = 0x00000001; 6596 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6597 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6598 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6599 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6600 mqd->compute_misc_reserved = 0x00000003; 6601 6602 eop_base_addr = prop->eop_gpu_addr >> 8; 6603 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6604 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6605 6606 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6607 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6608 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6609 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6610 6611 mqd->cp_hqd_eop_control = tmp; 6612 6613 /* enable doorbell? */ 6614 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6615 6616 if (prop->use_doorbell) { 6617 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6618 DOORBELL_OFFSET, prop->doorbell_index); 6619 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6620 DOORBELL_EN, 1); 6621 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6622 DOORBELL_SOURCE, 0); 6623 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6624 DOORBELL_HIT, 0); 6625 } else { 6626 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6627 DOORBELL_EN, 0); 6628 } 6629 6630 mqd->cp_hqd_pq_doorbell_control = tmp; 6631 6632 /* disable the queue if it's active */ 6633 mqd->cp_hqd_dequeue_request = 0; 6634 mqd->cp_hqd_pq_rptr = 0; 6635 mqd->cp_hqd_pq_wptr_lo = 0; 6636 mqd->cp_hqd_pq_wptr_hi = 0; 6637 6638 /* set the pointer to the MQD */ 6639 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6640 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6641 6642 /* set MQD vmid to 0 */ 6643 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6644 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6645 mqd->cp_mqd_control = tmp; 6646 6647 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6648 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6649 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6650 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6651 6652 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6653 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6654 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6655 (order_base_2(prop->queue_size / 4) - 1)); 6656 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6657 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6658 #ifdef __BIG_ENDIAN 6659 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6660 #endif 6661 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6662 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6663 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6664 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6665 mqd->cp_hqd_pq_control = tmp; 6666 6667 /* set the wb address whether it's enabled or not */ 6668 wb_gpu_addr = prop->rptr_gpu_addr; 6669 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6670 mqd->cp_hqd_pq_rptr_report_addr_hi = 6671 upper_32_bits(wb_gpu_addr) & 0xffff; 6672 6673 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6674 wb_gpu_addr = prop->wptr_gpu_addr; 6675 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6676 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6677 6678 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6679 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6680 6681 /* set the vmid for the queue */ 6682 mqd->cp_hqd_vmid = 0; 6683 6684 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6685 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6686 mqd->cp_hqd_persistent_state = tmp; 6687 6688 /* set MIN_IB_AVAIL_SIZE */ 6689 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6690 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6691 mqd->cp_hqd_ib_control = tmp; 6692 6693 /* set static priority for a compute queue/ring */ 6694 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6695 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6696 6697 mqd->cp_hqd_active = prop->hqd_active; 6698 6699 return 0; 6700 } 6701 6702 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6703 { 6704 struct amdgpu_device *adev = ring->adev; 6705 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6706 int j; 6707 6708 /* inactivate the queue */ 6709 if (amdgpu_sriov_vf(adev)) 6710 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6711 6712 /* disable wptr polling */ 6713 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6714 6715 /* disable the queue if it's active */ 6716 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6717 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6718 for (j = 0; j < adev->usec_timeout; j++) { 6719 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6720 break; 6721 udelay(1); 6722 } 6723 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6724 mqd->cp_hqd_dequeue_request); 6725 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6726 mqd->cp_hqd_pq_rptr); 6727 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6728 mqd->cp_hqd_pq_wptr_lo); 6729 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6730 mqd->cp_hqd_pq_wptr_hi); 6731 } 6732 6733 /* disable doorbells */ 6734 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6735 6736 /* write the EOP addr */ 6737 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6738 mqd->cp_hqd_eop_base_addr_lo); 6739 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6740 mqd->cp_hqd_eop_base_addr_hi); 6741 6742 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6743 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6744 mqd->cp_hqd_eop_control); 6745 6746 /* set the pointer to the MQD */ 6747 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6748 mqd->cp_mqd_base_addr_lo); 6749 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6750 mqd->cp_mqd_base_addr_hi); 6751 6752 /* set MQD vmid to 0 */ 6753 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6754 mqd->cp_mqd_control); 6755 6756 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6757 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6758 mqd->cp_hqd_pq_base_lo); 6759 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6760 mqd->cp_hqd_pq_base_hi); 6761 6762 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6763 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6764 mqd->cp_hqd_pq_control); 6765 6766 /* set the wb address whether it's enabled or not */ 6767 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6768 mqd->cp_hqd_pq_rptr_report_addr_lo); 6769 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6770 mqd->cp_hqd_pq_rptr_report_addr_hi); 6771 6772 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6773 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6774 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6775 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6776 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6777 6778 /* enable the doorbell if requested */ 6779 if (ring->use_doorbell) { 6780 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6781 (adev->doorbell_index.kiq * 2) << 2); 6782 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6783 (adev->doorbell_index.userqueue_end * 2) << 2); 6784 } 6785 6786 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6787 mqd->cp_hqd_pq_doorbell_control); 6788 6789 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6790 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6791 mqd->cp_hqd_pq_wptr_lo); 6792 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6793 mqd->cp_hqd_pq_wptr_hi); 6794 6795 /* set the vmid for the queue */ 6796 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6797 6798 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6799 mqd->cp_hqd_persistent_state); 6800 6801 /* activate the queue */ 6802 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6803 mqd->cp_hqd_active); 6804 6805 if (ring->use_doorbell) 6806 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6807 6808 return 0; 6809 } 6810 6811 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6812 { 6813 struct amdgpu_device *adev = ring->adev; 6814 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6815 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6816 6817 gfx_v10_0_kiq_setting(ring); 6818 6819 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6820 /* reset MQD to a clean status */ 6821 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6822 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6823 6824 /* reset ring buffer */ 6825 ring->wptr = 0; 6826 amdgpu_ring_clear_ring(ring); 6827 6828 mutex_lock(&adev->srbm_mutex); 6829 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6830 gfx_v10_0_kiq_init_register(ring); 6831 nv_grbm_select(adev, 0, 0, 0, 0); 6832 mutex_unlock(&adev->srbm_mutex); 6833 } else { 6834 memset((void *)mqd, 0, sizeof(*mqd)); 6835 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 6836 amdgpu_ring_clear_ring(ring); 6837 mutex_lock(&adev->srbm_mutex); 6838 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6839 amdgpu_ring_init_mqd(ring); 6840 gfx_v10_0_kiq_init_register(ring); 6841 nv_grbm_select(adev, 0, 0, 0, 0); 6842 mutex_unlock(&adev->srbm_mutex); 6843 6844 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6845 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6846 } 6847 6848 return 0; 6849 } 6850 6851 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6852 { 6853 struct amdgpu_device *adev = ring->adev; 6854 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6855 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6856 6857 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6858 memset((void *)mqd, 0, sizeof(*mqd)); 6859 mutex_lock(&adev->srbm_mutex); 6860 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6861 amdgpu_ring_init_mqd(ring); 6862 nv_grbm_select(adev, 0, 0, 0, 0); 6863 mutex_unlock(&adev->srbm_mutex); 6864 6865 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6866 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6867 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6868 /* reset MQD to a clean status */ 6869 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6870 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6871 6872 /* reset ring buffer */ 6873 ring->wptr = 0; 6874 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6875 amdgpu_ring_clear_ring(ring); 6876 } else { 6877 amdgpu_ring_clear_ring(ring); 6878 } 6879 6880 return 0; 6881 } 6882 6883 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6884 { 6885 struct amdgpu_ring *ring; 6886 int r; 6887 6888 ring = &adev->gfx.kiq.ring; 6889 6890 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6891 if (unlikely(r != 0)) 6892 return r; 6893 6894 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6895 if (unlikely(r != 0)) 6896 return r; 6897 6898 gfx_v10_0_kiq_init_queue(ring); 6899 amdgpu_bo_kunmap(ring->mqd_obj); 6900 ring->mqd_ptr = NULL; 6901 amdgpu_bo_unreserve(ring->mqd_obj); 6902 ring->sched.ready = true; 6903 return 0; 6904 } 6905 6906 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6907 { 6908 struct amdgpu_ring *ring = NULL; 6909 int r = 0, i; 6910 6911 gfx_v10_0_cp_compute_enable(adev, true); 6912 6913 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6914 ring = &adev->gfx.compute_ring[i]; 6915 6916 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6917 if (unlikely(r != 0)) 6918 goto done; 6919 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6920 if (!r) { 6921 r = gfx_v10_0_kcq_init_queue(ring); 6922 amdgpu_bo_kunmap(ring->mqd_obj); 6923 ring->mqd_ptr = NULL; 6924 } 6925 amdgpu_bo_unreserve(ring->mqd_obj); 6926 if (r) 6927 goto done; 6928 } 6929 6930 r = amdgpu_gfx_enable_kcq(adev); 6931 done: 6932 return r; 6933 } 6934 6935 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6936 { 6937 int r, i; 6938 struct amdgpu_ring *ring; 6939 6940 if (!(adev->flags & AMD_IS_APU)) 6941 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6942 6943 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6944 /* legacy firmware loading */ 6945 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6946 if (r) 6947 return r; 6948 6949 r = gfx_v10_0_cp_compute_load_microcode(adev); 6950 if (r) 6951 return r; 6952 } 6953 6954 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 6955 r = amdgpu_mes_kiq_hw_init(adev); 6956 else 6957 r = gfx_v10_0_kiq_resume(adev); 6958 if (r) 6959 return r; 6960 6961 r = gfx_v10_0_kcq_resume(adev); 6962 if (r) 6963 return r; 6964 6965 if (!amdgpu_async_gfx_ring) { 6966 r = gfx_v10_0_cp_gfx_resume(adev); 6967 if (r) 6968 return r; 6969 } else { 6970 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6971 if (r) 6972 return r; 6973 } 6974 6975 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6976 ring = &adev->gfx.gfx_ring[i]; 6977 r = amdgpu_ring_test_helper(ring); 6978 if (r) 6979 return r; 6980 } 6981 6982 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6983 ring = &adev->gfx.compute_ring[i]; 6984 r = amdgpu_ring_test_helper(ring); 6985 if (r) 6986 return r; 6987 } 6988 6989 return 0; 6990 } 6991 6992 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6993 { 6994 gfx_v10_0_cp_gfx_enable(adev, enable); 6995 gfx_v10_0_cp_compute_enable(adev, enable); 6996 } 6997 6998 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6999 { 7000 uint32_t data, pattern = 0xDEADBEEF; 7001 7002 /* check if mmVGT_ESGS_RING_SIZE_UMD 7003 * has been remapped to mmVGT_ESGS_RING_SIZE */ 7004 switch (adev->ip_versions[GC_HWIP][0]) { 7005 case IP_VERSION(10, 3, 0): 7006 case IP_VERSION(10, 3, 2): 7007 case IP_VERSION(10, 3, 4): 7008 case IP_VERSION(10, 3, 5): 7009 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7010 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7011 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7012 7013 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7014 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 7015 return true; 7016 } else { 7017 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7018 return false; 7019 } 7020 break; 7021 case IP_VERSION(10, 3, 1): 7022 case IP_VERSION(10, 3, 3): 7023 case IP_VERSION(10, 3, 6): 7024 case IP_VERSION(10, 3, 7): 7025 return true; 7026 default: 7027 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7028 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7029 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7030 7031 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7032 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7033 return true; 7034 } else { 7035 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7036 return false; 7037 } 7038 break; 7039 } 7040 } 7041 7042 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7043 { 7044 uint32_t data; 7045 7046 if (amdgpu_sriov_vf(adev)) 7047 return; 7048 7049 /* initialize cam_index to 0 7050 * index will auto-inc after each data writting */ 7051 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7052 7053 switch (adev->ip_versions[GC_HWIP][0]) { 7054 case IP_VERSION(10, 3, 0): 7055 case IP_VERSION(10, 3, 2): 7056 case IP_VERSION(10, 3, 1): 7057 case IP_VERSION(10, 3, 4): 7058 case IP_VERSION(10, 3, 5): 7059 case IP_VERSION(10, 3, 6): 7060 case IP_VERSION(10, 3, 3): 7061 case IP_VERSION(10, 3, 7): 7062 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7063 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7064 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7065 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7066 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7067 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7068 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7069 7070 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7071 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7072 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7073 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7074 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7075 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7076 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7077 7078 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7079 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7080 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7081 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7082 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7083 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7084 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7085 7086 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7087 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7088 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7089 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7090 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7091 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7092 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7093 7094 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7095 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7096 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7097 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7098 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7099 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7100 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7101 7102 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7103 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7104 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7105 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7106 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7107 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7108 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7109 7110 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7111 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7112 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7113 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7114 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7115 break; 7116 default: 7117 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7118 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7119 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7120 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7121 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7122 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7123 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7124 7125 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7126 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7127 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7128 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7129 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7130 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7131 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7132 7133 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7134 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7135 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7136 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7137 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7138 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7139 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7140 7141 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7142 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7143 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7144 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7145 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7146 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7147 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7148 7149 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7150 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7151 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7152 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7153 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7154 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7155 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7156 7157 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7158 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7159 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7160 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7161 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7162 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7163 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7164 7165 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7166 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7167 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7168 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7169 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7170 break; 7171 } 7172 7173 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7174 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7175 } 7176 7177 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7178 { 7179 uint32_t data; 7180 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7181 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7182 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7183 7184 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7185 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7186 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7187 } 7188 7189 static int gfx_v10_0_hw_init(void *handle) 7190 { 7191 int r; 7192 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7193 7194 if (!amdgpu_emu_mode) 7195 gfx_v10_0_init_golden_registers(adev); 7196 7197 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7198 /** 7199 * For gfx 10, rlc firmware loading relies on smu firmware is 7200 * loaded firstly, so in direct type, it has to load smc ucode 7201 * here before rlc. 7202 */ 7203 if (!(adev->flags & AMD_IS_APU)) { 7204 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7205 if (r) 7206 return r; 7207 } 7208 gfx_v10_0_disable_gpa_mode(adev); 7209 } 7210 7211 /* if GRBM CAM not remapped, set up the remapping */ 7212 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7213 gfx_v10_0_setup_grbm_cam_remapping(adev); 7214 7215 gfx_v10_0_constants_init(adev); 7216 7217 r = gfx_v10_0_rlc_resume(adev); 7218 if (r) 7219 return r; 7220 7221 /* 7222 * init golden registers and rlc resume may override some registers, 7223 * reconfig them here 7224 */ 7225 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) || 7226 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) || 7227 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 7228 gfx_v10_0_tcp_harvest(adev); 7229 7230 r = gfx_v10_0_cp_resume(adev); 7231 if (r) 7232 return r; 7233 7234 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 7235 gfx_v10_3_program_pbb_mode(adev); 7236 7237 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 7238 gfx_v10_3_set_power_brake_sequence(adev); 7239 7240 return r; 7241 } 7242 7243 #ifndef BRING_UP_DEBUG 7244 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7245 { 7246 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7247 struct amdgpu_ring *kiq_ring = &kiq->ring; 7248 int i; 7249 7250 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7251 return -EINVAL; 7252 7253 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7254 adev->gfx.num_gfx_rings)) 7255 return -ENOMEM; 7256 7257 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7258 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7259 PREEMPT_QUEUES, 0, 0); 7260 if (!adev->job_hang) 7261 return amdgpu_ring_test_helper(kiq_ring); 7262 else 7263 return 0; 7264 } 7265 #endif 7266 7267 static int gfx_v10_0_hw_fini(void *handle) 7268 { 7269 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7270 int r; 7271 7272 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7273 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7274 7275 if (!adev->no_hw_access) { 7276 #ifndef BRING_UP_DEBUG 7277 if (amdgpu_async_gfx_ring) { 7278 r = gfx_v10_0_kiq_disable_kgq(adev); 7279 if (r) 7280 DRM_ERROR("KGQ disable failed\n"); 7281 } 7282 #endif 7283 if (amdgpu_gfx_disable_kcq(adev)) 7284 DRM_ERROR("KCQ disable failed\n"); 7285 } 7286 7287 if (amdgpu_sriov_vf(adev)) { 7288 gfx_v10_0_cp_gfx_enable(adev, false); 7289 /* Remove the steps of clearing KIQ position. 7290 * It causes GFX hang when another Win guest is rendering. 7291 */ 7292 return 0; 7293 } 7294 gfx_v10_0_cp_enable(adev, false); 7295 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7296 7297 return 0; 7298 } 7299 7300 static int gfx_v10_0_suspend(void *handle) 7301 { 7302 return gfx_v10_0_hw_fini(handle); 7303 } 7304 7305 static int gfx_v10_0_resume(void *handle) 7306 { 7307 return gfx_v10_0_hw_init(handle); 7308 } 7309 7310 static bool gfx_v10_0_is_idle(void *handle) 7311 { 7312 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7313 7314 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7315 GRBM_STATUS, GUI_ACTIVE)) 7316 return false; 7317 else 7318 return true; 7319 } 7320 7321 static int gfx_v10_0_wait_for_idle(void *handle) 7322 { 7323 unsigned i; 7324 u32 tmp; 7325 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7326 7327 for (i = 0; i < adev->usec_timeout; i++) { 7328 /* read MC_STATUS */ 7329 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7330 GRBM_STATUS__GUI_ACTIVE_MASK; 7331 7332 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7333 return 0; 7334 udelay(1); 7335 } 7336 return -ETIMEDOUT; 7337 } 7338 7339 static int gfx_v10_0_soft_reset(void *handle) 7340 { 7341 u32 grbm_soft_reset = 0; 7342 u32 tmp; 7343 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7344 7345 /* GRBM_STATUS */ 7346 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7347 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7348 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7349 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7350 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7351 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7352 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7353 GRBM_SOFT_RESET, SOFT_RESET_CP, 7354 1); 7355 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7356 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7357 1); 7358 } 7359 7360 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7361 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7362 GRBM_SOFT_RESET, SOFT_RESET_CP, 7363 1); 7364 } 7365 7366 /* GRBM_STATUS2 */ 7367 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7368 switch (adev->ip_versions[GC_HWIP][0]) { 7369 case IP_VERSION(10, 3, 0): 7370 case IP_VERSION(10, 3, 2): 7371 case IP_VERSION(10, 3, 1): 7372 case IP_VERSION(10, 3, 4): 7373 case IP_VERSION(10, 3, 5): 7374 case IP_VERSION(10, 3, 6): 7375 case IP_VERSION(10, 3, 3): 7376 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7377 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7378 GRBM_SOFT_RESET, 7379 SOFT_RESET_RLC, 7380 1); 7381 break; 7382 default: 7383 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7384 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7385 GRBM_SOFT_RESET, 7386 SOFT_RESET_RLC, 7387 1); 7388 break; 7389 } 7390 7391 if (grbm_soft_reset) { 7392 /* stop the rlc */ 7393 gfx_v10_0_rlc_stop(adev); 7394 7395 /* Disable GFX parsing/prefetching */ 7396 gfx_v10_0_cp_gfx_enable(adev, false); 7397 7398 /* Disable MEC parsing/prefetching */ 7399 gfx_v10_0_cp_compute_enable(adev, false); 7400 7401 if (grbm_soft_reset) { 7402 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7403 tmp |= grbm_soft_reset; 7404 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7405 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7406 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7407 7408 udelay(50); 7409 7410 tmp &= ~grbm_soft_reset; 7411 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7412 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7413 } 7414 7415 /* Wait a little for things to settle down */ 7416 udelay(50); 7417 } 7418 return 0; 7419 } 7420 7421 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7422 { 7423 uint64_t clock, clock_lo, clock_hi, hi_check; 7424 7425 switch (adev->ip_versions[GC_HWIP][0]) { 7426 case IP_VERSION(10, 3, 1): 7427 case IP_VERSION(10, 3, 3): 7428 case IP_VERSION(10, 3, 7): 7429 preempt_disable(); 7430 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7431 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7432 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7433 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7434 * roughly every 42 seconds. 7435 */ 7436 if (hi_check != clock_hi) { 7437 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7438 clock_hi = hi_check; 7439 } 7440 preempt_enable(); 7441 clock = clock_lo | (clock_hi << 32ULL); 7442 break; 7443 case IP_VERSION(10, 3, 6): 7444 preempt_disable(); 7445 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7446 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7447 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7448 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7449 * roughly every 42 seconds. 7450 */ 7451 if (hi_check != clock_hi) { 7452 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7453 clock_hi = hi_check; 7454 } 7455 preempt_enable(); 7456 clock = clock_lo | (clock_hi << 32ULL); 7457 break; 7458 default: 7459 preempt_disable(); 7460 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7461 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7462 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7463 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7464 * roughly every 42 seconds. 7465 */ 7466 if (hi_check != clock_hi) { 7467 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7468 clock_hi = hi_check; 7469 } 7470 preempt_enable(); 7471 clock = clock_lo | (clock_hi << 32ULL); 7472 break; 7473 } 7474 return clock; 7475 } 7476 7477 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7478 uint32_t vmid, 7479 uint32_t gds_base, uint32_t gds_size, 7480 uint32_t gws_base, uint32_t gws_size, 7481 uint32_t oa_base, uint32_t oa_size) 7482 { 7483 struct amdgpu_device *adev = ring->adev; 7484 7485 /* GDS Base */ 7486 gfx_v10_0_write_data_to_reg(ring, 0, false, 7487 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7488 gds_base); 7489 7490 /* GDS Size */ 7491 gfx_v10_0_write_data_to_reg(ring, 0, false, 7492 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7493 gds_size); 7494 7495 /* GWS */ 7496 gfx_v10_0_write_data_to_reg(ring, 0, false, 7497 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7498 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7499 7500 /* OA */ 7501 gfx_v10_0_write_data_to_reg(ring, 0, false, 7502 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7503 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7504 } 7505 7506 static int gfx_v10_0_early_init(void *handle) 7507 { 7508 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7509 7510 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7511 7512 switch (adev->ip_versions[GC_HWIP][0]) { 7513 case IP_VERSION(10, 1, 10): 7514 case IP_VERSION(10, 1, 1): 7515 case IP_VERSION(10, 1, 2): 7516 case IP_VERSION(10, 1, 3): 7517 case IP_VERSION(10, 1, 4): 7518 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7519 break; 7520 case IP_VERSION(10, 3, 0): 7521 case IP_VERSION(10, 3, 2): 7522 case IP_VERSION(10, 3, 1): 7523 case IP_VERSION(10, 3, 4): 7524 case IP_VERSION(10, 3, 5): 7525 case IP_VERSION(10, 3, 6): 7526 case IP_VERSION(10, 3, 3): 7527 case IP_VERSION(10, 3, 7): 7528 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7529 break; 7530 default: 7531 break; 7532 } 7533 7534 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7535 AMDGPU_MAX_COMPUTE_RINGS); 7536 7537 gfx_v10_0_set_kiq_pm4_funcs(adev); 7538 gfx_v10_0_set_ring_funcs(adev); 7539 gfx_v10_0_set_irq_funcs(adev); 7540 gfx_v10_0_set_gds_init(adev); 7541 gfx_v10_0_set_rlc_funcs(adev); 7542 gfx_v10_0_set_mqd_funcs(adev); 7543 7544 /* init rlcg reg access ctrl */ 7545 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7546 7547 return gfx_v10_0_init_microcode(adev); 7548 } 7549 7550 static int gfx_v10_0_late_init(void *handle) 7551 { 7552 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7553 int r; 7554 7555 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7556 if (r) 7557 return r; 7558 7559 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7560 if (r) 7561 return r; 7562 7563 return 0; 7564 } 7565 7566 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7567 { 7568 uint32_t rlc_cntl; 7569 7570 /* if RLC is not enabled, do nothing */ 7571 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7572 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7573 } 7574 7575 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7576 { 7577 uint32_t data; 7578 unsigned i; 7579 7580 data = RLC_SAFE_MODE__CMD_MASK; 7581 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7582 7583 switch (adev->ip_versions[GC_HWIP][0]) { 7584 case IP_VERSION(10, 3, 0): 7585 case IP_VERSION(10, 3, 2): 7586 case IP_VERSION(10, 3, 1): 7587 case IP_VERSION(10, 3, 4): 7588 case IP_VERSION(10, 3, 5): 7589 case IP_VERSION(10, 3, 6): 7590 case IP_VERSION(10, 3, 3): 7591 case IP_VERSION(10, 3, 7): 7592 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7593 7594 /* wait for RLC_SAFE_MODE */ 7595 for (i = 0; i < adev->usec_timeout; i++) { 7596 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7597 RLC_SAFE_MODE, CMD)) 7598 break; 7599 udelay(1); 7600 } 7601 break; 7602 default: 7603 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7604 7605 /* wait for RLC_SAFE_MODE */ 7606 for (i = 0; i < adev->usec_timeout; i++) { 7607 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7608 RLC_SAFE_MODE, CMD)) 7609 break; 7610 udelay(1); 7611 } 7612 break; 7613 } 7614 } 7615 7616 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7617 { 7618 uint32_t data; 7619 7620 data = RLC_SAFE_MODE__CMD_MASK; 7621 switch (adev->ip_versions[GC_HWIP][0]) { 7622 case IP_VERSION(10, 3, 0): 7623 case IP_VERSION(10, 3, 2): 7624 case IP_VERSION(10, 3, 1): 7625 case IP_VERSION(10, 3, 4): 7626 case IP_VERSION(10, 3, 5): 7627 case IP_VERSION(10, 3, 6): 7628 case IP_VERSION(10, 3, 3): 7629 case IP_VERSION(10, 3, 7): 7630 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7631 break; 7632 default: 7633 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7634 break; 7635 } 7636 } 7637 7638 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7639 bool enable) 7640 { 7641 uint32_t data, def; 7642 7643 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7644 return; 7645 7646 /* It is disabled by HW by default */ 7647 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7648 /* 0 - Disable some blocks' MGCG */ 7649 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7650 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7651 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7652 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7653 7654 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7655 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7656 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7657 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7658 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7659 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7660 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7661 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7662 7663 if (def != data) 7664 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7665 7666 /* MGLS is a global flag to control all MGLS in GFX */ 7667 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7668 /* 2 - RLC memory Light sleep */ 7669 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7670 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7671 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7672 if (def != data) 7673 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7674 } 7675 /* 3 - CP memory Light sleep */ 7676 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7677 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7678 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7679 if (def != data) 7680 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7681 } 7682 } 7683 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7684 /* 1 - MGCG_OVERRIDE */ 7685 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7686 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7687 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7688 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7689 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7690 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7691 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7692 if (def != data) 7693 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7694 7695 /* 2 - disable MGLS in CP */ 7696 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7697 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7698 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7699 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7700 } 7701 7702 /* 3 - disable MGLS in RLC */ 7703 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7704 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7705 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7706 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7707 } 7708 7709 } 7710 } 7711 7712 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7713 bool enable) 7714 { 7715 uint32_t data, def; 7716 7717 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7718 return; 7719 7720 /* Enable 3D CGCG/CGLS */ 7721 if (enable) { 7722 /* write cmd to clear cgcg/cgls ov */ 7723 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7724 7725 /* unset CGCG override */ 7726 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7727 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7728 7729 /* update CGCG and CGLS override bits */ 7730 if (def != data) 7731 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7732 7733 /* enable 3Dcgcg FSM(0x0000363f) */ 7734 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7735 data = 0; 7736 7737 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7738 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7739 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7740 7741 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7742 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7743 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7744 7745 if (def != data) 7746 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7747 7748 /* set IDLE_POLL_COUNT(0x00900100) */ 7749 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7750 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7751 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7752 if (def != data) 7753 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7754 } else { 7755 /* Disable CGCG/CGLS */ 7756 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7757 7758 /* disable cgcg, cgls should be disabled */ 7759 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7760 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7761 7762 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7763 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7764 7765 /* disable cgcg and cgls in FSM */ 7766 if (def != data) 7767 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7768 } 7769 } 7770 7771 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7772 bool enable) 7773 { 7774 uint32_t def, data; 7775 7776 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7777 return; 7778 7779 if (enable) { 7780 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7781 7782 /* unset CGCG override */ 7783 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7784 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7785 7786 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7787 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7788 7789 /* update CGCG and CGLS override bits */ 7790 if (def != data) 7791 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7792 7793 /* enable cgcg FSM(0x0000363F) */ 7794 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7795 data = 0; 7796 7797 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7798 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7799 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7800 7801 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7802 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7803 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7804 7805 if (def != data) 7806 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7807 7808 /* set IDLE_POLL_COUNT(0x00900100) */ 7809 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7810 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7811 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7812 if (def != data) 7813 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7814 } else { 7815 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7816 7817 /* reset CGCG/CGLS bits */ 7818 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7819 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7820 7821 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7822 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7823 7824 /* disable cgcg and cgls in FSM */ 7825 if (def != data) 7826 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7827 } 7828 } 7829 7830 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7831 bool enable) 7832 { 7833 uint32_t def, data; 7834 7835 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 7836 return; 7837 7838 if (enable) { 7839 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7840 /* unset FGCG override */ 7841 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7842 /* update FGCG override bits */ 7843 if (def != data) 7844 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7845 7846 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7847 /* unset RLC SRAM CLK GATER override */ 7848 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7849 /* update RLC SRAM CLK GATER override bits */ 7850 if (def != data) 7851 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7852 } else { 7853 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7854 /* reset FGCG bits */ 7855 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7856 /* disable FGCG*/ 7857 if (def != data) 7858 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7859 7860 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7861 /* reset RLC SRAM CLK GATER bits */ 7862 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7863 /* disable RLC SRAM CLK*/ 7864 if (def != data) 7865 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7866 } 7867 } 7868 7869 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 7870 { 7871 uint32_t reg_data = 0; 7872 uint32_t reg_idx = 0; 7873 uint32_t i; 7874 7875 const uint32_t tcp_ctrl_regs[] = { 7876 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7877 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7878 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7879 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7880 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7881 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7882 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7883 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7884 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7885 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7886 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 7887 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 7888 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7889 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7890 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7891 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7892 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7893 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7894 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7895 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7896 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7897 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7898 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 7899 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 7900 }; 7901 7902 const uint32_t tcp_ctrl_regs_nv12[] = { 7903 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7904 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7905 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7906 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7907 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7908 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7909 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7910 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7911 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7912 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7913 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7914 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7915 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7916 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7917 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7918 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7919 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7920 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7921 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7922 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7923 }; 7924 7925 const uint32_t sm_ctlr_regs[] = { 7926 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 7927 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 7928 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 7929 mmCGTS_SA1_QUAD1_SM_CTRL_REG 7930 }; 7931 7932 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 7933 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 7934 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7935 tcp_ctrl_regs_nv12[i]; 7936 reg_data = RREG32(reg_idx); 7937 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7938 WREG32(reg_idx, reg_data); 7939 } 7940 } else { 7941 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 7942 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7943 tcp_ctrl_regs[i]; 7944 reg_data = RREG32(reg_idx); 7945 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7946 WREG32(reg_idx, reg_data); 7947 } 7948 } 7949 7950 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 7951 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 7952 sm_ctlr_regs[i]; 7953 reg_data = RREG32(reg_idx); 7954 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 7955 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 7956 WREG32(reg_idx, reg_data); 7957 } 7958 } 7959 7960 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7961 bool enable) 7962 { 7963 amdgpu_gfx_rlc_enter_safe_mode(adev); 7964 7965 if (enable) { 7966 /* enable FGCG firstly*/ 7967 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7968 /* CGCG/CGLS should be enabled after MGCG/MGLS 7969 * === MGCG + MGLS === 7970 */ 7971 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7972 /* === CGCG /CGLS for GFX 3D Only === */ 7973 gfx_v10_0_update_3d_clock_gating(adev, enable); 7974 /* === CGCG + CGLS === */ 7975 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7976 7977 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) || 7978 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) || 7979 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))) 7980 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 7981 } else { 7982 /* CGCG/CGLS should be disabled before MGCG/MGLS 7983 * === CGCG + CGLS === 7984 */ 7985 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7986 /* === CGCG /CGLS for GFX 3D Only === */ 7987 gfx_v10_0_update_3d_clock_gating(adev, enable); 7988 /* === MGCG + MGLS === */ 7989 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7990 /* disable fgcg at last*/ 7991 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7992 } 7993 7994 if (adev->cg_flags & 7995 (AMD_CG_SUPPORT_GFX_MGCG | 7996 AMD_CG_SUPPORT_GFX_CGLS | 7997 AMD_CG_SUPPORT_GFX_CGCG | 7998 AMD_CG_SUPPORT_GFX_3D_CGCG | 7999 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8000 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8001 8002 amdgpu_gfx_rlc_exit_safe_mode(adev); 8003 8004 return 0; 8005 } 8006 8007 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 8008 { 8009 u32 reg, data; 8010 8011 amdgpu_gfx_off_ctrl(adev, false); 8012 8013 /* not for *_SOC15 */ 8014 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8015 if (amdgpu_sriov_is_pp_one_vf(adev)) 8016 data = RREG32_NO_KIQ(reg); 8017 else 8018 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 8019 8020 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 8021 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8022 8023 if (amdgpu_sriov_is_pp_one_vf(adev)) 8024 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8025 else 8026 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8027 8028 amdgpu_gfx_off_ctrl(adev, true); 8029 } 8030 8031 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8032 uint32_t offset, 8033 struct soc15_reg_rlcg *entries, int arr_size) 8034 { 8035 int i; 8036 uint32_t reg; 8037 8038 if (!entries) 8039 return false; 8040 8041 for (i = 0; i < arr_size; i++) { 8042 const struct soc15_reg_rlcg *entry; 8043 8044 entry = &entries[i]; 8045 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8046 if (offset == reg) 8047 return true; 8048 } 8049 8050 return false; 8051 } 8052 8053 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8054 { 8055 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8056 } 8057 8058 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8059 { 8060 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8061 8062 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8063 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8064 else 8065 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8066 8067 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8068 8069 /* 8070 * CGPG enablement required and the register to program the hysteresis value 8071 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8072 * in refclk count. Note that RLC FW is modified to take 16 bits from 8073 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8074 * 8075 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8076 * of CGPG enablement starting point. 8077 * Power/performance team will optimize it and might give a new value later. 8078 */ 8079 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8080 switch (adev->ip_versions[GC_HWIP][0]) { 8081 case IP_VERSION(10, 3, 1): 8082 case IP_VERSION(10, 3, 3): 8083 case IP_VERSION(10, 3, 6): 8084 case IP_VERSION(10, 3, 7): 8085 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8086 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8087 break; 8088 default: 8089 break; 8090 } 8091 } 8092 } 8093 8094 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8095 { 8096 amdgpu_gfx_rlc_enter_safe_mode(adev); 8097 8098 gfx_v10_cntl_power_gating(adev, enable); 8099 8100 amdgpu_gfx_rlc_exit_safe_mode(adev); 8101 } 8102 8103 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8104 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8105 .set_safe_mode = gfx_v10_0_set_safe_mode, 8106 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8107 .init = gfx_v10_0_rlc_init, 8108 .get_csb_size = gfx_v10_0_get_csb_size, 8109 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8110 .resume = gfx_v10_0_rlc_resume, 8111 .stop = gfx_v10_0_rlc_stop, 8112 .reset = gfx_v10_0_rlc_reset, 8113 .start = gfx_v10_0_rlc_start, 8114 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8115 }; 8116 8117 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8118 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8119 .set_safe_mode = gfx_v10_0_set_safe_mode, 8120 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8121 .init = gfx_v10_0_rlc_init, 8122 .get_csb_size = gfx_v10_0_get_csb_size, 8123 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8124 .resume = gfx_v10_0_rlc_resume, 8125 .stop = gfx_v10_0_rlc_stop, 8126 .reset = gfx_v10_0_rlc_reset, 8127 .start = gfx_v10_0_rlc_start, 8128 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8129 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8130 }; 8131 8132 static int gfx_v10_0_set_powergating_state(void *handle, 8133 enum amd_powergating_state state) 8134 { 8135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8136 bool enable = (state == AMD_PG_STATE_GATE); 8137 8138 if (amdgpu_sriov_vf(adev)) 8139 return 0; 8140 8141 switch (adev->ip_versions[GC_HWIP][0]) { 8142 case IP_VERSION(10, 1, 10): 8143 case IP_VERSION(10, 1, 1): 8144 case IP_VERSION(10, 1, 2): 8145 case IP_VERSION(10, 3, 0): 8146 case IP_VERSION(10, 3, 2): 8147 case IP_VERSION(10, 3, 4): 8148 case IP_VERSION(10, 3, 5): 8149 amdgpu_gfx_off_ctrl(adev, enable); 8150 break; 8151 case IP_VERSION(10, 3, 1): 8152 case IP_VERSION(10, 3, 3): 8153 case IP_VERSION(10, 3, 6): 8154 case IP_VERSION(10, 3, 7): 8155 gfx_v10_cntl_pg(adev, enable); 8156 amdgpu_gfx_off_ctrl(adev, enable); 8157 break; 8158 default: 8159 break; 8160 } 8161 return 0; 8162 } 8163 8164 static int gfx_v10_0_set_clockgating_state(void *handle, 8165 enum amd_clockgating_state state) 8166 { 8167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8168 8169 if (amdgpu_sriov_vf(adev)) 8170 return 0; 8171 8172 switch (adev->ip_versions[GC_HWIP][0]) { 8173 case IP_VERSION(10, 1, 10): 8174 case IP_VERSION(10, 1, 1): 8175 case IP_VERSION(10, 1, 2): 8176 case IP_VERSION(10, 3, 0): 8177 case IP_VERSION(10, 3, 2): 8178 case IP_VERSION(10, 3, 1): 8179 case IP_VERSION(10, 3, 4): 8180 case IP_VERSION(10, 3, 5): 8181 case IP_VERSION(10, 3, 6): 8182 case IP_VERSION(10, 3, 3): 8183 case IP_VERSION(10, 3, 7): 8184 gfx_v10_0_update_gfx_clock_gating(adev, 8185 state == AMD_CG_STATE_GATE); 8186 break; 8187 default: 8188 break; 8189 } 8190 return 0; 8191 } 8192 8193 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8194 { 8195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8196 int data; 8197 8198 /* AMD_CG_SUPPORT_GFX_FGCG */ 8199 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8200 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8201 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8202 8203 /* AMD_CG_SUPPORT_GFX_MGCG */ 8204 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8205 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8206 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8207 8208 /* AMD_CG_SUPPORT_GFX_CGCG */ 8209 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8210 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8211 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8212 8213 /* AMD_CG_SUPPORT_GFX_CGLS */ 8214 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8215 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8216 8217 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8218 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8219 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8220 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8221 8222 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8223 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8224 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8225 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8226 8227 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8228 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8229 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8230 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8231 8232 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8233 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8234 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8235 } 8236 8237 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8238 { 8239 /* gfx10 is 32bit rptr*/ 8240 return *(uint32_t *)ring->rptr_cpu_addr; 8241 } 8242 8243 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8244 { 8245 struct amdgpu_device *adev = ring->adev; 8246 u64 wptr; 8247 8248 /* XXX check if swapping is necessary on BE */ 8249 if (ring->use_doorbell) { 8250 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8251 } else { 8252 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8253 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8254 } 8255 8256 return wptr; 8257 } 8258 8259 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8260 { 8261 struct amdgpu_device *adev = ring->adev; 8262 uint32_t *wptr_saved; 8263 uint32_t *is_queue_unmap; 8264 uint64_t aggregated_db_index; 8265 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 8266 uint64_t wptr_tmp; 8267 8268 if (ring->is_mes_queue) { 8269 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8270 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8271 sizeof(uint32_t)); 8272 aggregated_db_index = 8273 amdgpu_mes_get_aggregated_doorbell_index(adev, 8274 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8275 8276 wptr_tmp = ring->wptr & ring->buf_mask; 8277 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8278 *wptr_saved = wptr_tmp; 8279 /* assume doorbell always being used by mes mapped queue */ 8280 if (*is_queue_unmap) { 8281 WDOORBELL64(aggregated_db_index, wptr_tmp); 8282 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8283 } else { 8284 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8285 8286 if (*is_queue_unmap) 8287 WDOORBELL64(aggregated_db_index, wptr_tmp); 8288 } 8289 } else { 8290 if (ring->use_doorbell) { 8291 /* XXX check if swapping is necessary on BE */ 8292 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8293 ring->wptr); 8294 WDOORBELL64(ring->doorbell_index, ring->wptr); 8295 } else { 8296 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8297 lower_32_bits(ring->wptr)); 8298 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8299 upper_32_bits(ring->wptr)); 8300 } 8301 } 8302 } 8303 8304 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8305 { 8306 /* gfx10 hardware is 32bit rptr */ 8307 return *(uint32_t *)ring->rptr_cpu_addr; 8308 } 8309 8310 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8311 { 8312 u64 wptr; 8313 8314 /* XXX check if swapping is necessary on BE */ 8315 if (ring->use_doorbell) 8316 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8317 else 8318 BUG(); 8319 return wptr; 8320 } 8321 8322 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8323 { 8324 struct amdgpu_device *adev = ring->adev; 8325 uint32_t *wptr_saved; 8326 uint32_t *is_queue_unmap; 8327 uint64_t aggregated_db_index; 8328 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 8329 uint64_t wptr_tmp; 8330 8331 if (ring->is_mes_queue) { 8332 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8333 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8334 sizeof(uint32_t)); 8335 aggregated_db_index = 8336 amdgpu_mes_get_aggregated_doorbell_index(adev, 8337 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8338 8339 wptr_tmp = ring->wptr & ring->buf_mask; 8340 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8341 *wptr_saved = wptr_tmp; 8342 /* assume doorbell always used by mes mapped queue */ 8343 if (*is_queue_unmap) { 8344 WDOORBELL64(aggregated_db_index, wptr_tmp); 8345 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8346 } else { 8347 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8348 8349 if (*is_queue_unmap) 8350 WDOORBELL64(aggregated_db_index, wptr_tmp); 8351 } 8352 } else { 8353 /* XXX check if swapping is necessary on BE */ 8354 if (ring->use_doorbell) { 8355 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8356 ring->wptr); 8357 WDOORBELL64(ring->doorbell_index, ring->wptr); 8358 } else { 8359 BUG(); /* only DOORBELL method supported on gfx10 now */ 8360 } 8361 } 8362 } 8363 8364 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8365 { 8366 struct amdgpu_device *adev = ring->adev; 8367 u32 ref_and_mask, reg_mem_engine; 8368 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8369 8370 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8371 switch (ring->me) { 8372 case 1: 8373 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8374 break; 8375 case 2: 8376 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8377 break; 8378 default: 8379 return; 8380 } 8381 reg_mem_engine = 0; 8382 } else { 8383 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8384 reg_mem_engine = 1; /* pfp */ 8385 } 8386 8387 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8388 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8389 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8390 ref_and_mask, ref_and_mask, 0x20); 8391 } 8392 8393 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8394 struct amdgpu_job *job, 8395 struct amdgpu_ib *ib, 8396 uint32_t flags) 8397 { 8398 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8399 u32 header, control = 0; 8400 8401 if (ib->flags & AMDGPU_IB_FLAG_CE) 8402 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8403 else 8404 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8405 8406 control |= ib->length_dw | (vmid << 24); 8407 8408 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8409 control |= INDIRECT_BUFFER_PRE_ENB(1); 8410 8411 if (flags & AMDGPU_IB_PREEMPTED) 8412 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8413 8414 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8415 gfx_v10_0_ring_emit_de_meta(ring, 8416 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8417 } 8418 8419 if (ring->is_mes_queue) 8420 /* inherit vmid from mqd */ 8421 control |= 0x400000; 8422 8423 amdgpu_ring_write(ring, header); 8424 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8425 amdgpu_ring_write(ring, 8426 #ifdef __BIG_ENDIAN 8427 (2 << 0) | 8428 #endif 8429 lower_32_bits(ib->gpu_addr)); 8430 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8431 amdgpu_ring_write(ring, control); 8432 } 8433 8434 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8435 struct amdgpu_job *job, 8436 struct amdgpu_ib *ib, 8437 uint32_t flags) 8438 { 8439 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8440 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8441 8442 if (ring->is_mes_queue) 8443 /* inherit vmid from mqd */ 8444 control |= 0x40000000; 8445 8446 /* Currently, there is a high possibility to get wave ID mismatch 8447 * between ME and GDS, leading to a hw deadlock, because ME generates 8448 * different wave IDs than the GDS expects. This situation happens 8449 * randomly when at least 5 compute pipes use GDS ordered append. 8450 * The wave IDs generated by ME are also wrong after suspend/resume. 8451 * Those are probably bugs somewhere else in the kernel driver. 8452 * 8453 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8454 * GDS to 0 for this ring (me/pipe). 8455 */ 8456 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8457 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8458 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8459 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8460 } 8461 8462 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8463 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8464 amdgpu_ring_write(ring, 8465 #ifdef __BIG_ENDIAN 8466 (2 << 0) | 8467 #endif 8468 lower_32_bits(ib->gpu_addr)); 8469 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8470 amdgpu_ring_write(ring, control); 8471 } 8472 8473 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8474 u64 seq, unsigned flags) 8475 { 8476 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8477 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8478 8479 /* RELEASE_MEM - flush caches, send int */ 8480 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8481 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8482 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8483 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8484 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8485 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8486 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8487 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8488 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8489 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8490 8491 /* 8492 * the address should be Qword aligned if 64bit write, Dword 8493 * aligned if only send 32bit data low (discard data high) 8494 */ 8495 if (write64bit) 8496 BUG_ON(addr & 0x7); 8497 else 8498 BUG_ON(addr & 0x3); 8499 amdgpu_ring_write(ring, lower_32_bits(addr)); 8500 amdgpu_ring_write(ring, upper_32_bits(addr)); 8501 amdgpu_ring_write(ring, lower_32_bits(seq)); 8502 amdgpu_ring_write(ring, upper_32_bits(seq)); 8503 amdgpu_ring_write(ring, ring->is_mes_queue ? 8504 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 8505 } 8506 8507 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8508 { 8509 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8510 uint32_t seq = ring->fence_drv.sync_seq; 8511 uint64_t addr = ring->fence_drv.gpu_addr; 8512 8513 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8514 upper_32_bits(addr), seq, 0xffffffff, 4); 8515 } 8516 8517 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8518 uint16_t pasid, uint32_t flush_type, 8519 bool all_hub, uint8_t dst_sel) 8520 { 8521 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8522 amdgpu_ring_write(ring, 8523 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8524 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8525 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8526 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8527 } 8528 8529 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8530 unsigned vmid, uint64_t pd_addr) 8531 { 8532 if (ring->is_mes_queue) 8533 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 8534 else 8535 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8536 8537 /* compute doesn't have PFP */ 8538 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8539 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8540 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8541 amdgpu_ring_write(ring, 0x0); 8542 } 8543 } 8544 8545 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8546 u64 seq, unsigned int flags) 8547 { 8548 struct amdgpu_device *adev = ring->adev; 8549 8550 /* we only allocate 32bit for each seq wb address */ 8551 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8552 8553 /* write fence seq to the "addr" */ 8554 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8555 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8556 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8557 amdgpu_ring_write(ring, lower_32_bits(addr)); 8558 amdgpu_ring_write(ring, upper_32_bits(addr)); 8559 amdgpu_ring_write(ring, lower_32_bits(seq)); 8560 8561 if (flags & AMDGPU_FENCE_FLAG_INT) { 8562 /* set register to trigger INT */ 8563 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8564 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8565 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8566 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8567 amdgpu_ring_write(ring, 0); 8568 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8569 } 8570 } 8571 8572 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8573 { 8574 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8575 amdgpu_ring_write(ring, 0); 8576 } 8577 8578 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8579 uint32_t flags) 8580 { 8581 uint32_t dw2 = 0; 8582 8583 if (amdgpu_mcbp) 8584 gfx_v10_0_ring_emit_ce_meta(ring, 8585 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8586 8587 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8588 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8589 /* set load_global_config & load_global_uconfig */ 8590 dw2 |= 0x8001; 8591 /* set load_cs_sh_regs */ 8592 dw2 |= 0x01000000; 8593 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8594 dw2 |= 0x10002; 8595 8596 /* set load_ce_ram if preamble presented */ 8597 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8598 dw2 |= 0x10000000; 8599 } else { 8600 /* still load_ce_ram if this is the first time preamble presented 8601 * although there is no context switch happens. 8602 */ 8603 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8604 dw2 |= 0x10000000; 8605 } 8606 8607 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8608 amdgpu_ring_write(ring, dw2); 8609 amdgpu_ring_write(ring, 0); 8610 } 8611 8612 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8613 { 8614 unsigned ret; 8615 8616 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8617 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8618 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8619 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8620 ret = ring->wptr & ring->buf_mask; 8621 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8622 8623 return ret; 8624 } 8625 8626 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8627 { 8628 unsigned cur; 8629 BUG_ON(offset > ring->buf_mask); 8630 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8631 8632 cur = (ring->wptr - 1) & ring->buf_mask; 8633 if (likely(cur > offset)) 8634 ring->ring[offset] = cur - offset; 8635 else 8636 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8637 } 8638 8639 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8640 { 8641 int i, r = 0; 8642 struct amdgpu_device *adev = ring->adev; 8643 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8644 struct amdgpu_ring *kiq_ring = &kiq->ring; 8645 unsigned long flags; 8646 8647 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8648 return -EINVAL; 8649 8650 spin_lock_irqsave(&kiq->ring_lock, flags); 8651 8652 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8653 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8654 return -ENOMEM; 8655 } 8656 8657 /* assert preemption condition */ 8658 amdgpu_ring_set_preempt_cond_exec(ring, false); 8659 8660 /* assert IB preemption, emit the trailing fence */ 8661 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8662 ring->trail_fence_gpu_addr, 8663 ++ring->trail_seq); 8664 amdgpu_ring_commit(kiq_ring); 8665 8666 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8667 8668 /* poll the trailing fence */ 8669 for (i = 0; i < adev->usec_timeout; i++) { 8670 if (ring->trail_seq == 8671 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8672 break; 8673 udelay(1); 8674 } 8675 8676 if (i >= adev->usec_timeout) { 8677 r = -EINVAL; 8678 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8679 } 8680 8681 /* deassert preemption condition */ 8682 amdgpu_ring_set_preempt_cond_exec(ring, true); 8683 return r; 8684 } 8685 8686 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8687 { 8688 struct amdgpu_device *adev = ring->adev; 8689 struct v10_ce_ib_state ce_payload = {0}; 8690 uint64_t offset, ce_payload_gpu_addr; 8691 void *ce_payload_cpu_addr; 8692 int cnt; 8693 8694 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8695 8696 if (ring->is_mes_queue) { 8697 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8698 gfx[0].gfx_meta_data) + 8699 offsetof(struct v10_gfx_meta_data, ce_payload); 8700 ce_payload_gpu_addr = 8701 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8702 ce_payload_cpu_addr = 8703 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8704 } else { 8705 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8706 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8707 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8708 } 8709 8710 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8711 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8712 WRITE_DATA_DST_SEL(8) | 8713 WR_CONFIRM) | 8714 WRITE_DATA_CACHE_POLICY(0)); 8715 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8716 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8717 8718 if (resume) 8719 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8720 sizeof(ce_payload) >> 2); 8721 else 8722 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8723 sizeof(ce_payload) >> 2); 8724 } 8725 8726 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8727 { 8728 struct amdgpu_device *adev = ring->adev; 8729 struct v10_de_ib_state de_payload = {0}; 8730 uint64_t offset, gds_addr, de_payload_gpu_addr; 8731 void *de_payload_cpu_addr; 8732 int cnt; 8733 8734 if (ring->is_mes_queue) { 8735 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8736 gfx[0].gfx_meta_data) + 8737 offsetof(struct v10_gfx_meta_data, de_payload); 8738 de_payload_gpu_addr = 8739 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8740 de_payload_cpu_addr = 8741 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8742 8743 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8744 gfx[0].gds_backup) + 8745 offsetof(struct v10_gfx_meta_data, de_payload); 8746 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8747 } else { 8748 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8749 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8750 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8751 8752 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8753 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8754 PAGE_SIZE); 8755 } 8756 8757 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8758 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8759 8760 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8761 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8762 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8763 WRITE_DATA_DST_SEL(8) | 8764 WR_CONFIRM) | 8765 WRITE_DATA_CACHE_POLICY(0)); 8766 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8767 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8768 8769 if (resume) 8770 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8771 sizeof(de_payload) >> 2); 8772 else 8773 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8774 sizeof(de_payload) >> 2); 8775 } 8776 8777 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8778 bool secure) 8779 { 8780 uint32_t v = secure ? FRAME_TMZ : 0; 8781 8782 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8783 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8784 } 8785 8786 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8787 uint32_t reg_val_offs) 8788 { 8789 struct amdgpu_device *adev = ring->adev; 8790 8791 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8792 amdgpu_ring_write(ring, 0 | /* src: register*/ 8793 (5 << 8) | /* dst: memory */ 8794 (1 << 20)); /* write confirm */ 8795 amdgpu_ring_write(ring, reg); 8796 amdgpu_ring_write(ring, 0); 8797 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8798 reg_val_offs * 4)); 8799 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8800 reg_val_offs * 4)); 8801 } 8802 8803 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8804 uint32_t val) 8805 { 8806 uint32_t cmd = 0; 8807 8808 switch (ring->funcs->type) { 8809 case AMDGPU_RING_TYPE_GFX: 8810 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8811 break; 8812 case AMDGPU_RING_TYPE_KIQ: 8813 cmd = (1 << 16); /* no inc addr */ 8814 break; 8815 default: 8816 cmd = WR_CONFIRM; 8817 break; 8818 } 8819 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8820 amdgpu_ring_write(ring, cmd); 8821 amdgpu_ring_write(ring, reg); 8822 amdgpu_ring_write(ring, 0); 8823 amdgpu_ring_write(ring, val); 8824 } 8825 8826 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8827 uint32_t val, uint32_t mask) 8828 { 8829 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8830 } 8831 8832 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8833 uint32_t reg0, uint32_t reg1, 8834 uint32_t ref, uint32_t mask) 8835 { 8836 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8837 struct amdgpu_device *adev = ring->adev; 8838 bool fw_version_ok = false; 8839 8840 fw_version_ok = adev->gfx.cp_fw_write_wait; 8841 8842 if (fw_version_ok) 8843 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8844 ref, mask, 0x20); 8845 else 8846 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8847 ref, mask); 8848 } 8849 8850 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8851 unsigned vmid) 8852 { 8853 struct amdgpu_device *adev = ring->adev; 8854 uint32_t value = 0; 8855 8856 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8857 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8858 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8859 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8860 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8861 } 8862 8863 static void 8864 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8865 uint32_t me, uint32_t pipe, 8866 enum amdgpu_interrupt_state state) 8867 { 8868 uint32_t cp_int_cntl, cp_int_cntl_reg; 8869 8870 if (!me) { 8871 switch (pipe) { 8872 case 0: 8873 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8874 break; 8875 case 1: 8876 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8877 break; 8878 default: 8879 DRM_DEBUG("invalid pipe %d\n", pipe); 8880 return; 8881 } 8882 } else { 8883 DRM_DEBUG("invalid me %d\n", me); 8884 return; 8885 } 8886 8887 switch (state) { 8888 case AMDGPU_IRQ_STATE_DISABLE: 8889 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8890 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8891 TIME_STAMP_INT_ENABLE, 0); 8892 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8893 break; 8894 case AMDGPU_IRQ_STATE_ENABLE: 8895 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8896 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8897 TIME_STAMP_INT_ENABLE, 1); 8898 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8899 break; 8900 default: 8901 break; 8902 } 8903 } 8904 8905 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8906 int me, int pipe, 8907 enum amdgpu_interrupt_state state) 8908 { 8909 u32 mec_int_cntl, mec_int_cntl_reg; 8910 8911 /* 8912 * amdgpu controls only the first MEC. That's why this function only 8913 * handles the setting of interrupts for this specific MEC. All other 8914 * pipes' interrupts are set by amdkfd. 8915 */ 8916 8917 if (me == 1) { 8918 switch (pipe) { 8919 case 0: 8920 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8921 break; 8922 case 1: 8923 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8924 break; 8925 case 2: 8926 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8927 break; 8928 case 3: 8929 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8930 break; 8931 default: 8932 DRM_DEBUG("invalid pipe %d\n", pipe); 8933 return; 8934 } 8935 } else { 8936 DRM_DEBUG("invalid me %d\n", me); 8937 return; 8938 } 8939 8940 switch (state) { 8941 case AMDGPU_IRQ_STATE_DISABLE: 8942 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8943 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8944 TIME_STAMP_INT_ENABLE, 0); 8945 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8946 break; 8947 case AMDGPU_IRQ_STATE_ENABLE: 8948 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8949 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8950 TIME_STAMP_INT_ENABLE, 1); 8951 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8952 break; 8953 default: 8954 break; 8955 } 8956 } 8957 8958 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8959 struct amdgpu_irq_src *src, 8960 unsigned type, 8961 enum amdgpu_interrupt_state state) 8962 { 8963 switch (type) { 8964 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8965 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8966 break; 8967 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8968 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8969 break; 8970 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8971 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8972 break; 8973 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8974 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8975 break; 8976 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8977 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8978 break; 8979 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8980 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8981 break; 8982 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8983 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8984 break; 8985 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8986 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8987 break; 8988 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8989 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8990 break; 8991 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8992 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8993 break; 8994 default: 8995 break; 8996 } 8997 return 0; 8998 } 8999 9000 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9001 struct amdgpu_irq_src *source, 9002 struct amdgpu_iv_entry *entry) 9003 { 9004 int i; 9005 u8 me_id, pipe_id, queue_id; 9006 struct amdgpu_ring *ring; 9007 uint32_t mes_queue_id = entry->src_data[0]; 9008 9009 DRM_DEBUG("IH: CP EOP\n"); 9010 9011 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 9012 struct amdgpu_mes_queue *queue; 9013 9014 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 9015 9016 spin_lock(&adev->mes.queue_id_lock); 9017 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 9018 if (queue) { 9019 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 9020 amdgpu_fence_process(queue->ring); 9021 } 9022 spin_unlock(&adev->mes.queue_id_lock); 9023 } else { 9024 me_id = (entry->ring_id & 0x0c) >> 2; 9025 pipe_id = (entry->ring_id & 0x03) >> 0; 9026 queue_id = (entry->ring_id & 0x70) >> 4; 9027 9028 switch (me_id) { 9029 case 0: 9030 if (pipe_id == 0) 9031 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9032 else 9033 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9034 break; 9035 case 1: 9036 case 2: 9037 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9038 ring = &adev->gfx.compute_ring[i]; 9039 /* Per-queue interrupt is supported for MEC starting from VI. 9040 * The interrupt can only be enabled/disabled per pipe instead 9041 * of per queue. 9042 */ 9043 if ((ring->me == me_id) && 9044 (ring->pipe == pipe_id) && 9045 (ring->queue == queue_id)) 9046 amdgpu_fence_process(ring); 9047 } 9048 break; 9049 } 9050 } 9051 9052 return 0; 9053 } 9054 9055 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9056 struct amdgpu_irq_src *source, 9057 unsigned type, 9058 enum amdgpu_interrupt_state state) 9059 { 9060 switch (state) { 9061 case AMDGPU_IRQ_STATE_DISABLE: 9062 case AMDGPU_IRQ_STATE_ENABLE: 9063 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9064 PRIV_REG_INT_ENABLE, 9065 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9066 break; 9067 default: 9068 break; 9069 } 9070 9071 return 0; 9072 } 9073 9074 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9075 struct amdgpu_irq_src *source, 9076 unsigned type, 9077 enum amdgpu_interrupt_state state) 9078 { 9079 switch (state) { 9080 case AMDGPU_IRQ_STATE_DISABLE: 9081 case AMDGPU_IRQ_STATE_ENABLE: 9082 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9083 PRIV_INSTR_INT_ENABLE, 9084 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9085 break; 9086 default: 9087 break; 9088 } 9089 9090 return 0; 9091 } 9092 9093 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9094 struct amdgpu_iv_entry *entry) 9095 { 9096 u8 me_id, pipe_id, queue_id; 9097 struct amdgpu_ring *ring; 9098 int i; 9099 9100 me_id = (entry->ring_id & 0x0c) >> 2; 9101 pipe_id = (entry->ring_id & 0x03) >> 0; 9102 queue_id = (entry->ring_id & 0x70) >> 4; 9103 9104 switch (me_id) { 9105 case 0: 9106 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9107 ring = &adev->gfx.gfx_ring[i]; 9108 /* we only enabled 1 gfx queue per pipe for now */ 9109 if (ring->me == me_id && ring->pipe == pipe_id) 9110 drm_sched_fault(&ring->sched); 9111 } 9112 break; 9113 case 1: 9114 case 2: 9115 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9116 ring = &adev->gfx.compute_ring[i]; 9117 if (ring->me == me_id && ring->pipe == pipe_id && 9118 ring->queue == queue_id) 9119 drm_sched_fault(&ring->sched); 9120 } 9121 break; 9122 default: 9123 BUG(); 9124 } 9125 } 9126 9127 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9128 struct amdgpu_irq_src *source, 9129 struct amdgpu_iv_entry *entry) 9130 { 9131 DRM_ERROR("Illegal register access in command stream\n"); 9132 gfx_v10_0_handle_priv_fault(adev, entry); 9133 return 0; 9134 } 9135 9136 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9137 struct amdgpu_irq_src *source, 9138 struct amdgpu_iv_entry *entry) 9139 { 9140 DRM_ERROR("Illegal instruction in command stream\n"); 9141 gfx_v10_0_handle_priv_fault(adev, entry); 9142 return 0; 9143 } 9144 9145 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9146 struct amdgpu_irq_src *src, 9147 unsigned int type, 9148 enum amdgpu_interrupt_state state) 9149 { 9150 uint32_t tmp, target; 9151 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9152 9153 if (ring->me == 1) 9154 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9155 else 9156 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9157 target += ring->pipe; 9158 9159 switch (type) { 9160 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9161 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9162 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9163 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9164 GENERIC2_INT_ENABLE, 0); 9165 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9166 9167 tmp = RREG32_SOC15_IP(GC, target); 9168 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9169 GENERIC2_INT_ENABLE, 0); 9170 WREG32_SOC15_IP(GC, target, tmp); 9171 } else { 9172 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9173 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9174 GENERIC2_INT_ENABLE, 1); 9175 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9176 9177 tmp = RREG32_SOC15_IP(GC, target); 9178 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9179 GENERIC2_INT_ENABLE, 1); 9180 WREG32_SOC15_IP(GC, target, tmp); 9181 } 9182 break; 9183 default: 9184 BUG(); /* kiq only support GENERIC2_INT now */ 9185 break; 9186 } 9187 return 0; 9188 } 9189 9190 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9191 struct amdgpu_irq_src *source, 9192 struct amdgpu_iv_entry *entry) 9193 { 9194 u8 me_id, pipe_id, queue_id; 9195 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9196 9197 me_id = (entry->ring_id & 0x0c) >> 2; 9198 pipe_id = (entry->ring_id & 0x03) >> 0; 9199 queue_id = (entry->ring_id & 0x70) >> 4; 9200 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9201 me_id, pipe_id, queue_id); 9202 9203 amdgpu_fence_process(ring); 9204 return 0; 9205 } 9206 9207 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9208 { 9209 const unsigned int gcr_cntl = 9210 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9211 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9212 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9213 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9214 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9215 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9216 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9217 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9218 9219 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9220 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9221 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9222 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9223 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9224 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9225 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9226 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9227 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9228 } 9229 9230 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9231 .name = "gfx_v10_0", 9232 .early_init = gfx_v10_0_early_init, 9233 .late_init = gfx_v10_0_late_init, 9234 .sw_init = gfx_v10_0_sw_init, 9235 .sw_fini = gfx_v10_0_sw_fini, 9236 .hw_init = gfx_v10_0_hw_init, 9237 .hw_fini = gfx_v10_0_hw_fini, 9238 .suspend = gfx_v10_0_suspend, 9239 .resume = gfx_v10_0_resume, 9240 .is_idle = gfx_v10_0_is_idle, 9241 .wait_for_idle = gfx_v10_0_wait_for_idle, 9242 .soft_reset = gfx_v10_0_soft_reset, 9243 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9244 .set_powergating_state = gfx_v10_0_set_powergating_state, 9245 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9246 }; 9247 9248 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9249 .type = AMDGPU_RING_TYPE_GFX, 9250 .align_mask = 0xff, 9251 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9252 .support_64bit_ptrs = true, 9253 .secure_submission_supported = true, 9254 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9255 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9256 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9257 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9258 5 + /* COND_EXEC */ 9259 7 + /* PIPELINE_SYNC */ 9260 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9261 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9262 2 + /* VM_FLUSH */ 9263 8 + /* FENCE for VM_FLUSH */ 9264 20 + /* GDS switch */ 9265 4 + /* double SWITCH_BUFFER, 9266 * the first COND_EXEC jump to the place 9267 * just prior to this double SWITCH_BUFFER 9268 */ 9269 5 + /* COND_EXEC */ 9270 7 + /* HDP_flush */ 9271 4 + /* VGT_flush */ 9272 14 + /* CE_META */ 9273 31 + /* DE_META */ 9274 3 + /* CNTX_CTRL */ 9275 5 + /* HDP_INVL */ 9276 8 + 8 + /* FENCE x2 */ 9277 2 + /* SWITCH_BUFFER */ 9278 8, /* gfx_v10_0_emit_mem_sync */ 9279 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9280 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9281 .emit_fence = gfx_v10_0_ring_emit_fence, 9282 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9283 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9284 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9285 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9286 .test_ring = gfx_v10_0_ring_test_ring, 9287 .test_ib = gfx_v10_0_ring_test_ib, 9288 .insert_nop = amdgpu_ring_insert_nop, 9289 .pad_ib = amdgpu_ring_generic_pad_ib, 9290 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9291 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9292 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9293 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9294 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9295 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9296 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9297 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9298 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9299 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9300 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9301 }; 9302 9303 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9304 .type = AMDGPU_RING_TYPE_COMPUTE, 9305 .align_mask = 0xff, 9306 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9307 .support_64bit_ptrs = true, 9308 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9309 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9310 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9311 .emit_frame_size = 9312 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9313 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9314 5 + /* hdp invalidate */ 9315 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9316 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9317 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9318 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9319 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9320 8, /* gfx_v10_0_emit_mem_sync */ 9321 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9322 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9323 .emit_fence = gfx_v10_0_ring_emit_fence, 9324 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9325 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9326 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9327 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9328 .test_ring = gfx_v10_0_ring_test_ring, 9329 .test_ib = gfx_v10_0_ring_test_ib, 9330 .insert_nop = amdgpu_ring_insert_nop, 9331 .pad_ib = amdgpu_ring_generic_pad_ib, 9332 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9333 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9334 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9335 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9336 }; 9337 9338 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9339 .type = AMDGPU_RING_TYPE_KIQ, 9340 .align_mask = 0xff, 9341 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9342 .support_64bit_ptrs = true, 9343 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9344 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9345 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9346 .emit_frame_size = 9347 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9348 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9349 5 + /*hdp invalidate */ 9350 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9351 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9352 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9353 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9354 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9355 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9356 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9357 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9358 .test_ring = gfx_v10_0_ring_test_ring, 9359 .test_ib = gfx_v10_0_ring_test_ib, 9360 .insert_nop = amdgpu_ring_insert_nop, 9361 .pad_ib = amdgpu_ring_generic_pad_ib, 9362 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9363 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9364 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9365 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9366 }; 9367 9368 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9369 { 9370 int i; 9371 9372 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9373 9374 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9375 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9376 9377 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9378 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9379 } 9380 9381 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9382 .set = gfx_v10_0_set_eop_interrupt_state, 9383 .process = gfx_v10_0_eop_irq, 9384 }; 9385 9386 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9387 .set = gfx_v10_0_set_priv_reg_fault_state, 9388 .process = gfx_v10_0_priv_reg_irq, 9389 }; 9390 9391 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9392 .set = gfx_v10_0_set_priv_inst_fault_state, 9393 .process = gfx_v10_0_priv_inst_irq, 9394 }; 9395 9396 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9397 .set = gfx_v10_0_kiq_set_interrupt_state, 9398 .process = gfx_v10_0_kiq_irq, 9399 }; 9400 9401 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9402 { 9403 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9404 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9405 9406 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9407 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9408 9409 adev->gfx.priv_reg_irq.num_types = 1; 9410 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9411 9412 adev->gfx.priv_inst_irq.num_types = 1; 9413 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9414 } 9415 9416 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9417 { 9418 switch (adev->ip_versions[GC_HWIP][0]) { 9419 case IP_VERSION(10, 1, 10): 9420 case IP_VERSION(10, 1, 1): 9421 case IP_VERSION(10, 1, 3): 9422 case IP_VERSION(10, 1, 4): 9423 case IP_VERSION(10, 3, 2): 9424 case IP_VERSION(10, 3, 1): 9425 case IP_VERSION(10, 3, 4): 9426 case IP_VERSION(10, 3, 5): 9427 case IP_VERSION(10, 3, 6): 9428 case IP_VERSION(10, 3, 3): 9429 case IP_VERSION(10, 3, 7): 9430 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9431 break; 9432 case IP_VERSION(10, 1, 2): 9433 case IP_VERSION(10, 3, 0): 9434 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9435 break; 9436 default: 9437 break; 9438 } 9439 } 9440 9441 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9442 { 9443 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9444 adev->gfx.config.max_sh_per_se * 9445 adev->gfx.config.max_shader_engines; 9446 9447 adev->gds.gds_size = 0x10000; 9448 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9449 adev->gds.gws_size = 64; 9450 adev->gds.oa_size = 16; 9451 } 9452 9453 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9454 { 9455 /* set gfx eng mqd */ 9456 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9457 sizeof(struct v10_gfx_mqd); 9458 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9459 gfx_v10_0_gfx_mqd_init; 9460 /* set compute eng mqd */ 9461 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9462 sizeof(struct v10_compute_mqd); 9463 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9464 gfx_v10_0_compute_mqd_init; 9465 } 9466 9467 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9468 u32 bitmap) 9469 { 9470 u32 data; 9471 9472 if (!bitmap) 9473 return; 9474 9475 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9476 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9477 9478 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9479 } 9480 9481 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9482 { 9483 u32 disabled_mask = 9484 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9485 u32 efuse_setting = 0; 9486 u32 vbios_setting = 0; 9487 9488 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9489 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9490 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9491 9492 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9493 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9494 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9495 9496 disabled_mask |= efuse_setting | vbios_setting; 9497 9498 return (~disabled_mask); 9499 } 9500 9501 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9502 { 9503 u32 wgp_idx, wgp_active_bitmap; 9504 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9505 9506 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9507 cu_active_bitmap = 0; 9508 9509 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9510 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9511 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9512 if (wgp_active_bitmap & (1 << wgp_idx)) 9513 cu_active_bitmap |= cu_bitmap_per_wgp; 9514 } 9515 9516 return cu_active_bitmap; 9517 } 9518 9519 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9520 struct amdgpu_cu_info *cu_info) 9521 { 9522 int i, j, k, counter, active_cu_number = 0; 9523 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9524 unsigned disable_masks[4 * 2]; 9525 9526 if (!adev || !cu_info) 9527 return -EINVAL; 9528 9529 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9530 9531 mutex_lock(&adev->grbm_idx_mutex); 9532 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9533 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9534 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9535 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 9536 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 9537 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) || 9538 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) && 9539 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9540 continue; 9541 mask = 1; 9542 ao_bitmap = 0; 9543 counter = 0; 9544 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9545 if (i < 4 && j < 2) 9546 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9547 adev, disable_masks[i * 2 + j]); 9548 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9549 cu_info->bitmap[i][j] = bitmap; 9550 9551 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9552 if (bitmap & mask) { 9553 if (counter < adev->gfx.config.max_cu_per_sh) 9554 ao_bitmap |= mask; 9555 counter++; 9556 } 9557 mask <<= 1; 9558 } 9559 active_cu_number += counter; 9560 if (i < 2 && j < 2) 9561 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9562 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9563 } 9564 } 9565 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9566 mutex_unlock(&adev->grbm_idx_mutex); 9567 9568 cu_info->number = active_cu_number; 9569 cu_info->ao_cu_mask = ao_cu_mask; 9570 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9571 9572 return 0; 9573 } 9574 9575 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9576 { 9577 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9578 9579 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9580 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9581 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9582 9583 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9584 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9585 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9586 9587 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9588 adev->gfx.config.max_shader_engines); 9589 disabled_sa = efuse_setting | vbios_setting; 9590 disabled_sa &= max_sa_mask; 9591 9592 return disabled_sa; 9593 } 9594 9595 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9596 { 9597 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9598 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9599 9600 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9601 9602 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9603 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9604 max_shader_engines = adev->gfx.config.max_shader_engines; 9605 9606 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9607 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9608 disabled_sa_per_se &= max_sa_per_se_mask; 9609 if (disabled_sa_per_se == max_sa_per_se_mask) { 9610 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9611 break; 9612 } 9613 } 9614 } 9615 9616 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9617 { 9618 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9619 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9620 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9621 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9622 9623 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9624 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9625 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9626 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9627 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9628 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9629 9630 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9631 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9632 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9633 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9634 9635 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9636 9637 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9638 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9639 } 9640 9641 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9642 { 9643 .type = AMD_IP_BLOCK_TYPE_GFX, 9644 .major = 10, 9645 .minor = 0, 9646 .rev = 0, 9647 .funcs = &gfx_v10_0_ip_funcs, 9648 }; 9649