1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "navi10_enum.h" 39 #include "hdp/hdp_5_0_0_offset.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15_common.h" 44 #include "clearstate_gfx10.h" 45 #include "v10_structs.h" 46 #include "gfx_v10_0.h" 47 #include "nbio_v2_3.h" 48 49 /** 50 * Navi10 has two graphic rings to share each graphic pipe. 51 * 1. Primary ring 52 * 2. Async ring 53 * 54 * In bring-up phase, it just used primary ring so set gfx ring number as 1 at 55 * first. 56 */ 57 #define GFX10_NUM_GFX_RINGS 2 58 #define GFX10_MEC_HPD_SIZE 2048 59 60 #define F32_CE_PROGRAM_RAM_SIZE 65536 61 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 62 63 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 68 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 72 73 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 74 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 75 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 76 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 77 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 78 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 79 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 80 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 81 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 82 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 83 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 84 85 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 86 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 87 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 88 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 89 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 90 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 91 92 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 93 { 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 131 }; 132 133 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 134 { 135 /* Pending on emulation bring up */ 136 }; 137 138 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 139 { 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000), 175 }; 176 177 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 178 { 179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 219 }; 220 221 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 222 { 223 /* Pending on emulation bring up */ 224 }; 225 226 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 227 { 228 /* Pending on emulation bring up */ 229 }; 230 231 #define DEFAULT_SH_MEM_CONFIG \ 232 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 233 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 234 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 235 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 236 237 238 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 239 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 240 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 241 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 242 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 243 struct amdgpu_cu_info *cu_info); 244 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 245 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 246 u32 sh_num, u32 instance); 247 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 248 249 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 250 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 251 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 252 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 253 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 254 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 255 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start); 256 257 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 258 { 259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 260 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 261 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 262 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 263 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 264 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 265 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 266 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 267 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 268 } 269 270 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 271 struct amdgpu_ring *ring) 272 { 273 struct amdgpu_device *adev = kiq_ring->adev; 274 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 275 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 276 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 277 278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 279 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 280 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 281 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 282 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 283 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 284 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 285 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 286 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 287 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 288 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 289 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 290 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 291 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 292 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 293 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 294 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 295 } 296 297 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 298 struct amdgpu_ring *ring, 299 enum amdgpu_unmap_queues_action action, 300 u64 gpu_addr, u64 seq) 301 { 302 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 303 304 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 305 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 306 PACKET3_UNMAP_QUEUES_ACTION(action) | 307 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 308 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 309 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 310 amdgpu_ring_write(kiq_ring, 311 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 312 313 if (action == PREEMPT_QUEUES_NO_UNMAP) { 314 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 315 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 316 amdgpu_ring_write(kiq_ring, seq); 317 } else { 318 amdgpu_ring_write(kiq_ring, 0); 319 amdgpu_ring_write(kiq_ring, 0); 320 amdgpu_ring_write(kiq_ring, 0); 321 } 322 } 323 324 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 325 struct amdgpu_ring *ring, 326 u64 addr, 327 u64 seq) 328 { 329 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 330 331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 332 amdgpu_ring_write(kiq_ring, 333 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 334 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 335 PACKET3_QUERY_STATUS_COMMAND(2)); 336 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 337 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 338 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 339 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 340 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 341 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 342 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 343 } 344 345 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 346 .kiq_set_resources = gfx10_kiq_set_resources, 347 .kiq_map_queues = gfx10_kiq_map_queues, 348 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 349 .kiq_query_status = gfx10_kiq_query_status, 350 .set_resources_size = 8, 351 .map_queues_size = 7, 352 .unmap_queues_size = 6, 353 .query_status_size = 7, 354 }; 355 356 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 357 { 358 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 359 } 360 361 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 362 { 363 switch (adev->asic_type) { 364 case CHIP_NAVI10: 365 soc15_program_register_sequence(adev, 366 golden_settings_gc_10_1, 367 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 368 soc15_program_register_sequence(adev, 369 golden_settings_gc_10_0_nv10, 370 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 371 break; 372 case CHIP_NAVI14: 373 soc15_program_register_sequence(adev, 374 golden_settings_gc_10_1_1, 375 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 376 soc15_program_register_sequence(adev, 377 golden_settings_gc_10_1_nv14, 378 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 379 break; 380 case CHIP_NAVI12: 381 soc15_program_register_sequence(adev, 382 golden_settings_gc_10_1_2, 383 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 384 soc15_program_register_sequence(adev, 385 golden_settings_gc_10_1_2_nv12, 386 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 387 break; 388 default: 389 break; 390 } 391 } 392 393 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 394 { 395 adev->gfx.scratch.num_reg = 8; 396 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 397 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 398 } 399 400 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 401 bool wc, uint32_t reg, uint32_t val) 402 { 403 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 404 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 405 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 406 amdgpu_ring_write(ring, reg); 407 amdgpu_ring_write(ring, 0); 408 amdgpu_ring_write(ring, val); 409 } 410 411 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 412 int mem_space, int opt, uint32_t addr0, 413 uint32_t addr1, uint32_t ref, uint32_t mask, 414 uint32_t inv) 415 { 416 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 417 amdgpu_ring_write(ring, 418 /* memory (1) or register (0) */ 419 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 420 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 421 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 422 WAIT_REG_MEM_ENGINE(eng_sel))); 423 424 if (mem_space) 425 BUG_ON(addr0 & 0x3); /* Dword align */ 426 amdgpu_ring_write(ring, addr0); 427 amdgpu_ring_write(ring, addr1); 428 amdgpu_ring_write(ring, ref); 429 amdgpu_ring_write(ring, mask); 430 amdgpu_ring_write(ring, inv); /* poll interval */ 431 } 432 433 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 434 { 435 struct amdgpu_device *adev = ring->adev; 436 uint32_t scratch; 437 uint32_t tmp = 0; 438 unsigned i; 439 int r; 440 441 r = amdgpu_gfx_scratch_get(adev, &scratch); 442 if (r) { 443 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 444 return r; 445 } 446 447 WREG32(scratch, 0xCAFEDEAD); 448 449 r = amdgpu_ring_alloc(ring, 3); 450 if (r) { 451 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 452 ring->idx, r); 453 amdgpu_gfx_scratch_free(adev, scratch); 454 return r; 455 } 456 457 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 458 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 459 amdgpu_ring_write(ring, 0xDEADBEEF); 460 amdgpu_ring_commit(ring); 461 462 for (i = 0; i < adev->usec_timeout; i++) { 463 tmp = RREG32(scratch); 464 if (tmp == 0xDEADBEEF) 465 break; 466 if (amdgpu_emu_mode == 1) 467 msleep(1); 468 else 469 udelay(1); 470 } 471 if (i < adev->usec_timeout) { 472 if (amdgpu_emu_mode == 1) 473 DRM_INFO("ring test on %d succeeded in %d msecs\n", 474 ring->idx, i); 475 else 476 DRM_INFO("ring test on %d succeeded in %d usecs\n", 477 ring->idx, i); 478 } else { 479 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 480 ring->idx, scratch, tmp); 481 r = -EINVAL; 482 } 483 amdgpu_gfx_scratch_free(adev, scratch); 484 485 return r; 486 } 487 488 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 489 { 490 struct amdgpu_device *adev = ring->adev; 491 struct amdgpu_ib ib; 492 struct dma_fence *f = NULL; 493 uint32_t scratch; 494 uint32_t tmp = 0; 495 long r; 496 497 r = amdgpu_gfx_scratch_get(adev, &scratch); 498 if (r) { 499 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 500 return r; 501 } 502 503 WREG32(scratch, 0xCAFEDEAD); 504 505 memset(&ib, 0, sizeof(ib)); 506 r = amdgpu_ib_get(adev, NULL, 256, &ib); 507 if (r) { 508 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 509 goto err1; 510 } 511 512 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 513 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 514 ib.ptr[2] = 0xDEADBEEF; 515 ib.length_dw = 3; 516 517 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 518 if (r) 519 goto err2; 520 521 r = dma_fence_wait_timeout(f, false, timeout); 522 if (r == 0) { 523 DRM_ERROR("amdgpu: IB test timed out.\n"); 524 r = -ETIMEDOUT; 525 goto err2; 526 } else if (r < 0) { 527 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 528 goto err2; 529 } 530 531 tmp = RREG32(scratch); 532 if (tmp == 0xDEADBEEF) { 533 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 534 r = 0; 535 } else { 536 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 537 scratch, tmp); 538 r = -EINVAL; 539 } 540 err2: 541 amdgpu_ib_free(adev, &ib, NULL); 542 dma_fence_put(f); 543 err1: 544 amdgpu_gfx_scratch_free(adev, scratch); 545 546 return r; 547 } 548 549 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 550 { 551 release_firmware(adev->gfx.pfp_fw); 552 adev->gfx.pfp_fw = NULL; 553 release_firmware(adev->gfx.me_fw); 554 adev->gfx.me_fw = NULL; 555 release_firmware(adev->gfx.ce_fw); 556 adev->gfx.ce_fw = NULL; 557 release_firmware(adev->gfx.rlc_fw); 558 adev->gfx.rlc_fw = NULL; 559 release_firmware(adev->gfx.mec_fw); 560 adev->gfx.mec_fw = NULL; 561 release_firmware(adev->gfx.mec2_fw); 562 adev->gfx.mec2_fw = NULL; 563 564 kfree(adev->gfx.rlc.register_list_format); 565 } 566 567 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 568 { 569 adev->gfx.cp_fw_write_wait = false; 570 571 switch (adev->asic_type) { 572 case CHIP_NAVI10: 573 case CHIP_NAVI12: 574 case CHIP_NAVI14: 575 if ((adev->gfx.me_fw_version >= 0x00000046) && 576 (adev->gfx.me_feature_version >= 27) && 577 (adev->gfx.pfp_fw_version >= 0x00000068) && 578 (adev->gfx.pfp_feature_version >= 27) && 579 (adev->gfx.mec_fw_version >= 0x0000005b) && 580 (adev->gfx.mec_feature_version >= 27)) 581 adev->gfx.cp_fw_write_wait = true; 582 break; 583 default: 584 break; 585 } 586 587 if (adev->gfx.cp_fw_write_wait == false) 588 DRM_WARN_ONCE("Warning: check cp_fw_version and update it to realize \ 589 GRBM requires 1-cycle delay in cp firmware\n"); 590 } 591 592 593 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 594 { 595 const struct rlc_firmware_header_v2_1 *rlc_hdr; 596 597 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 598 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 599 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 600 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 601 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 602 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 603 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 604 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 605 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 606 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 607 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 608 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 609 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 610 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 611 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 612 } 613 614 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 615 { 616 switch (adev->asic_type) { 617 case CHIP_NAVI10: 618 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 619 break; 620 default: 621 break; 622 } 623 } 624 625 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 626 { 627 const char *chip_name; 628 char fw_name[40]; 629 char wks[10]; 630 int err; 631 struct amdgpu_firmware_info *info = NULL; 632 const struct common_firmware_header *header = NULL; 633 const struct gfx_firmware_header_v1_0 *cp_hdr; 634 const struct rlc_firmware_header_v2_0 *rlc_hdr; 635 unsigned int *tmp = NULL; 636 unsigned int i = 0; 637 uint16_t version_major; 638 uint16_t version_minor; 639 640 DRM_DEBUG("\n"); 641 642 memset(wks, 0, sizeof(wks)); 643 switch (adev->asic_type) { 644 case CHIP_NAVI10: 645 chip_name = "navi10"; 646 break; 647 case CHIP_NAVI14: 648 chip_name = "navi14"; 649 if (!(adev->pdev->device == 0x7340 && 650 adev->pdev->revision != 0x00)) 651 snprintf(wks, sizeof(wks), "_wks"); 652 break; 653 case CHIP_NAVI12: 654 chip_name = "navi12"; 655 break; 656 default: 657 BUG(); 658 } 659 660 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 661 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 662 if (err) 663 goto out; 664 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 665 if (err) 666 goto out; 667 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 668 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 669 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 670 671 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 672 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 673 if (err) 674 goto out; 675 err = amdgpu_ucode_validate(adev->gfx.me_fw); 676 if (err) 677 goto out; 678 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 679 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 680 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 681 682 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 683 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 684 if (err) 685 goto out; 686 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 687 if (err) 688 goto out; 689 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 690 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 691 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 692 693 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 694 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 695 if (err) 696 goto out; 697 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 698 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 699 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 700 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 701 if (version_major == 2 && version_minor == 1) 702 adev->gfx.rlc.is_rlc_v2_1 = true; 703 704 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 705 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 706 adev->gfx.rlc.save_and_restore_offset = 707 le32_to_cpu(rlc_hdr->save_and_restore_offset); 708 adev->gfx.rlc.clear_state_descriptor_offset = 709 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 710 adev->gfx.rlc.avail_scratch_ram_locations = 711 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 712 adev->gfx.rlc.reg_restore_list_size = 713 le32_to_cpu(rlc_hdr->reg_restore_list_size); 714 adev->gfx.rlc.reg_list_format_start = 715 le32_to_cpu(rlc_hdr->reg_list_format_start); 716 adev->gfx.rlc.reg_list_format_separate_start = 717 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 718 adev->gfx.rlc.starting_offsets_start = 719 le32_to_cpu(rlc_hdr->starting_offsets_start); 720 adev->gfx.rlc.reg_list_format_size_bytes = 721 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 722 adev->gfx.rlc.reg_list_size_bytes = 723 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 724 adev->gfx.rlc.register_list_format = 725 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 726 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 727 if (!adev->gfx.rlc.register_list_format) { 728 err = -ENOMEM; 729 goto out; 730 } 731 732 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 733 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 734 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 735 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 736 737 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 738 739 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 740 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 741 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 742 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 743 744 if (adev->gfx.rlc.is_rlc_v2_1) 745 gfx_v10_0_init_rlc_ext_microcode(adev); 746 747 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 748 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 749 if (err) 750 goto out; 751 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 752 if (err) 753 goto out; 754 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 755 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 756 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 757 758 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 759 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 760 if (!err) { 761 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 762 if (err) 763 goto out; 764 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 765 adev->gfx.mec2_fw->data; 766 adev->gfx.mec2_fw_version = 767 le32_to_cpu(cp_hdr->header.ucode_version); 768 adev->gfx.mec2_feature_version = 769 le32_to_cpu(cp_hdr->ucode_feature_version); 770 } else { 771 err = 0; 772 adev->gfx.mec2_fw = NULL; 773 } 774 775 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 776 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 777 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 778 info->fw = adev->gfx.pfp_fw; 779 header = (const struct common_firmware_header *)info->fw->data; 780 adev->firmware.fw_size += 781 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 782 783 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 784 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 785 info->fw = adev->gfx.me_fw; 786 header = (const struct common_firmware_header *)info->fw->data; 787 adev->firmware.fw_size += 788 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 789 790 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 791 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 792 info->fw = adev->gfx.ce_fw; 793 header = (const struct common_firmware_header *)info->fw->data; 794 adev->firmware.fw_size += 795 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 796 797 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 798 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 799 info->fw = adev->gfx.rlc_fw; 800 header = (const struct common_firmware_header *)info->fw->data; 801 adev->firmware.fw_size += 802 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 803 804 if (adev->gfx.rlc.is_rlc_v2_1 && 805 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 806 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 807 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 808 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 809 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 810 info->fw = adev->gfx.rlc_fw; 811 adev->firmware.fw_size += 812 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 813 814 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 815 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 816 info->fw = adev->gfx.rlc_fw; 817 adev->firmware.fw_size += 818 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 819 820 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 821 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 822 info->fw = adev->gfx.rlc_fw; 823 adev->firmware.fw_size += 824 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 825 } 826 827 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 828 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 829 info->fw = adev->gfx.mec_fw; 830 header = (const struct common_firmware_header *)info->fw->data; 831 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 832 adev->firmware.fw_size += 833 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 834 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 835 836 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 837 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 838 info->fw = adev->gfx.mec_fw; 839 adev->firmware.fw_size += 840 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 841 842 if (adev->gfx.mec2_fw) { 843 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 844 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 845 info->fw = adev->gfx.mec2_fw; 846 header = (const struct common_firmware_header *)info->fw->data; 847 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 848 adev->firmware.fw_size += 849 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 850 le32_to_cpu(cp_hdr->jt_size) * 4, 851 PAGE_SIZE); 852 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 853 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 854 info->fw = adev->gfx.mec2_fw; 855 adev->firmware.fw_size += 856 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 857 PAGE_SIZE); 858 } 859 } 860 861 gfx_v10_0_check_fw_write_wait(adev); 862 out: 863 if (err) { 864 dev_err(adev->dev, 865 "gfx10: Failed to load firmware \"%s\"\n", 866 fw_name); 867 release_firmware(adev->gfx.pfp_fw); 868 adev->gfx.pfp_fw = NULL; 869 release_firmware(adev->gfx.me_fw); 870 adev->gfx.me_fw = NULL; 871 release_firmware(adev->gfx.ce_fw); 872 adev->gfx.ce_fw = NULL; 873 release_firmware(adev->gfx.rlc_fw); 874 adev->gfx.rlc_fw = NULL; 875 release_firmware(adev->gfx.mec_fw); 876 adev->gfx.mec_fw = NULL; 877 release_firmware(adev->gfx.mec2_fw); 878 adev->gfx.mec2_fw = NULL; 879 } 880 881 gfx_v10_0_check_gfxoff_flag(adev); 882 883 return err; 884 } 885 886 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 887 { 888 u32 count = 0; 889 const struct cs_section_def *sect = NULL; 890 const struct cs_extent_def *ext = NULL; 891 892 /* begin clear state */ 893 count += 2; 894 /* context control state */ 895 count += 3; 896 897 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 898 for (ext = sect->section; ext->extent != NULL; ++ext) { 899 if (sect->id == SECT_CONTEXT) 900 count += 2 + ext->reg_count; 901 else 902 return 0; 903 } 904 } 905 906 /* set PA_SC_TILE_STEERING_OVERRIDE */ 907 count += 3; 908 /* end clear state */ 909 count += 2; 910 /* clear state */ 911 count += 2; 912 913 return count; 914 } 915 916 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 917 volatile u32 *buffer) 918 { 919 u32 count = 0, i; 920 const struct cs_section_def *sect = NULL; 921 const struct cs_extent_def *ext = NULL; 922 int ctx_reg_offset; 923 924 if (adev->gfx.rlc.cs_data == NULL) 925 return; 926 if (buffer == NULL) 927 return; 928 929 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 930 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 931 932 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 933 buffer[count++] = cpu_to_le32(0x80000000); 934 buffer[count++] = cpu_to_le32(0x80000000); 935 936 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 937 for (ext = sect->section; ext->extent != NULL; ++ext) { 938 if (sect->id == SECT_CONTEXT) { 939 buffer[count++] = 940 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 941 buffer[count++] = cpu_to_le32(ext->reg_index - 942 PACKET3_SET_CONTEXT_REG_START); 943 for (i = 0; i < ext->reg_count; i++) 944 buffer[count++] = cpu_to_le32(ext->extent[i]); 945 } else { 946 return; 947 } 948 } 949 } 950 951 ctx_reg_offset = 952 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 953 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 954 buffer[count++] = cpu_to_le32(ctx_reg_offset); 955 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 956 957 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 958 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 959 960 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 961 buffer[count++] = cpu_to_le32(0); 962 } 963 964 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 965 { 966 /* clear state block */ 967 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 968 &adev->gfx.rlc.clear_state_gpu_addr, 969 (void **)&adev->gfx.rlc.cs_ptr); 970 971 /* jump table block */ 972 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 973 &adev->gfx.rlc.cp_table_gpu_addr, 974 (void **)&adev->gfx.rlc.cp_table_ptr); 975 } 976 977 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 978 { 979 const struct cs_section_def *cs_data; 980 int r; 981 982 adev->gfx.rlc.cs_data = gfx10_cs_data; 983 984 cs_data = adev->gfx.rlc.cs_data; 985 986 if (cs_data) { 987 /* init clear state block */ 988 r = amdgpu_gfx_rlc_init_csb(adev); 989 if (r) 990 return r; 991 } 992 993 return 0; 994 } 995 996 static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev) 997 { 998 int r; 999 1000 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 1001 if (unlikely(r != 0)) 1002 return r; 1003 1004 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, 1005 AMDGPU_GEM_DOMAIN_VRAM); 1006 if (!r) 1007 adev->gfx.rlc.clear_state_gpu_addr = 1008 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); 1009 1010 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1011 1012 return r; 1013 } 1014 1015 static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev) 1016 { 1017 int r; 1018 1019 if (!adev->gfx.rlc.clear_state_obj) 1020 return; 1021 1022 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); 1023 if (likely(r == 0)) { 1024 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 1025 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1026 } 1027 } 1028 1029 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 1030 { 1031 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1032 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1033 } 1034 1035 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 1036 { 1037 int r; 1038 1039 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 1040 1041 amdgpu_gfx_graphics_queue_acquire(adev); 1042 1043 r = gfx_v10_0_init_microcode(adev); 1044 if (r) 1045 DRM_ERROR("Failed to load gfx firmware!\n"); 1046 1047 return r; 1048 } 1049 1050 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 1051 { 1052 int r; 1053 u32 *hpd; 1054 const __le32 *fw_data = NULL; 1055 unsigned fw_size; 1056 u32 *fw = NULL; 1057 size_t mec_hpd_size; 1058 1059 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 1060 1061 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1062 1063 /* take ownership of the relevant compute queues */ 1064 amdgpu_gfx_compute_queue_acquire(adev); 1065 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 1066 1067 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1068 AMDGPU_GEM_DOMAIN_GTT, 1069 &adev->gfx.mec.hpd_eop_obj, 1070 &adev->gfx.mec.hpd_eop_gpu_addr, 1071 (void **)&hpd); 1072 if (r) { 1073 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1074 gfx_v10_0_mec_fini(adev); 1075 return r; 1076 } 1077 1078 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 1079 1080 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1081 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1082 1083 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1084 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1085 1086 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1087 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1088 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1089 1090 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1091 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1092 &adev->gfx.mec.mec_fw_obj, 1093 &adev->gfx.mec.mec_fw_gpu_addr, 1094 (void **)&fw); 1095 if (r) { 1096 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 1097 gfx_v10_0_mec_fini(adev); 1098 return r; 1099 } 1100 1101 memcpy(fw, fw_data, fw_size); 1102 1103 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1104 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1105 } 1106 1107 return 0; 1108 } 1109 1110 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1111 { 1112 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1113 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1114 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1115 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1116 } 1117 1118 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1119 uint32_t thread, uint32_t regno, 1120 uint32_t num, uint32_t *out) 1121 { 1122 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1123 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1124 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1125 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1126 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1127 while (num--) 1128 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1129 } 1130 1131 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1132 { 1133 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 1134 * field when performing a select_se_sh so it should be 1135 * zero here */ 1136 WARN_ON(simd != 0); 1137 1138 /* type 2 wave data */ 1139 dst[(*no_fields)++] = 2; 1140 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1141 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1142 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1143 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1144 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1145 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1146 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1147 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 1148 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1149 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1150 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1151 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1152 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1153 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1154 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1155 } 1156 1157 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1158 uint32_t wave, uint32_t start, 1159 uint32_t size, uint32_t *dst) 1160 { 1161 WARN_ON(simd != 0); 1162 1163 wave_read_regs( 1164 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1165 dst); 1166 } 1167 1168 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1169 uint32_t wave, uint32_t thread, 1170 uint32_t start, uint32_t size, 1171 uint32_t *dst) 1172 { 1173 wave_read_regs( 1174 adev, wave, thread, 1175 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1176 } 1177 1178 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 1179 u32 me, u32 pipe, u32 q, u32 vm) 1180 { 1181 nv_grbm_select(adev, me, pipe, q, vm); 1182 } 1183 1184 1185 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 1186 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 1187 .select_se_sh = &gfx_v10_0_select_se_sh, 1188 .read_wave_data = &gfx_v10_0_read_wave_data, 1189 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 1190 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 1191 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 1192 }; 1193 1194 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 1195 { 1196 u32 gb_addr_config; 1197 1198 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 1199 1200 switch (adev->asic_type) { 1201 case CHIP_NAVI10: 1202 case CHIP_NAVI14: 1203 case CHIP_NAVI12: 1204 adev->gfx.config.max_hw_contexts = 8; 1205 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1206 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1207 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1208 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1209 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1210 break; 1211 default: 1212 BUG(); 1213 break; 1214 } 1215 1216 adev->gfx.config.gb_addr_config = gb_addr_config; 1217 1218 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1219 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1220 GB_ADDR_CONFIG, NUM_PIPES); 1221 1222 adev->gfx.config.max_tile_pipes = 1223 adev->gfx.config.gb_addr_config_fields.num_pipes; 1224 1225 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1226 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1227 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 1228 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1229 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1230 GB_ADDR_CONFIG, NUM_RB_PER_SE); 1231 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1232 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1233 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 1234 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1235 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1236 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 1237 } 1238 1239 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1240 int me, int pipe, int queue) 1241 { 1242 int r; 1243 struct amdgpu_ring *ring; 1244 unsigned int irq_type; 1245 1246 ring = &adev->gfx.gfx_ring[ring_id]; 1247 1248 ring->me = me; 1249 ring->pipe = pipe; 1250 ring->queue = queue; 1251 1252 ring->ring_obj = NULL; 1253 ring->use_doorbell = true; 1254 1255 if (!ring_id) 1256 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1257 else 1258 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1259 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1260 1261 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1262 r = amdgpu_ring_init(adev, ring, 1024, 1263 &adev->gfx.eop_irq, irq_type); 1264 if (r) 1265 return r; 1266 return 0; 1267 } 1268 1269 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1270 int mec, int pipe, int queue) 1271 { 1272 int r; 1273 unsigned irq_type; 1274 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1275 1276 ring = &adev->gfx.compute_ring[ring_id]; 1277 1278 /* mec0 is me1 */ 1279 ring->me = mec + 1; 1280 ring->pipe = pipe; 1281 ring->queue = queue; 1282 1283 ring->ring_obj = NULL; 1284 ring->use_doorbell = true; 1285 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1286 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1287 + (ring_id * GFX10_MEC_HPD_SIZE); 1288 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1289 1290 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1291 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1292 + ring->pipe; 1293 1294 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1295 r = amdgpu_ring_init(adev, ring, 1024, 1296 &adev->gfx.eop_irq, irq_type); 1297 if (r) 1298 return r; 1299 1300 return 0; 1301 } 1302 1303 static int gfx_v10_0_sw_init(void *handle) 1304 { 1305 int i, j, k, r, ring_id = 0; 1306 struct amdgpu_kiq *kiq; 1307 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1308 1309 switch (adev->asic_type) { 1310 case CHIP_NAVI10: 1311 case CHIP_NAVI14: 1312 case CHIP_NAVI12: 1313 adev->gfx.me.num_me = 1; 1314 adev->gfx.me.num_pipe_per_me = 2; 1315 adev->gfx.me.num_queue_per_pipe = 1; 1316 adev->gfx.mec.num_mec = 2; 1317 adev->gfx.mec.num_pipe_per_mec = 4; 1318 adev->gfx.mec.num_queue_per_pipe = 8; 1319 break; 1320 default: 1321 adev->gfx.me.num_me = 1; 1322 adev->gfx.me.num_pipe_per_me = 1; 1323 adev->gfx.me.num_queue_per_pipe = 1; 1324 adev->gfx.mec.num_mec = 1; 1325 adev->gfx.mec.num_pipe_per_mec = 4; 1326 adev->gfx.mec.num_queue_per_pipe = 8; 1327 break; 1328 } 1329 1330 /* KIQ event */ 1331 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1332 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 1333 &adev->gfx.kiq.irq); 1334 if (r) 1335 return r; 1336 1337 /* EOP Event */ 1338 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1339 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 1340 &adev->gfx.eop_irq); 1341 if (r) 1342 return r; 1343 1344 /* Privileged reg */ 1345 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 1346 &adev->gfx.priv_reg_irq); 1347 if (r) 1348 return r; 1349 1350 /* Privileged inst */ 1351 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 1352 &adev->gfx.priv_inst_irq); 1353 if (r) 1354 return r; 1355 1356 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1357 1358 gfx_v10_0_scratch_init(adev); 1359 1360 r = gfx_v10_0_me_init(adev); 1361 if (r) 1362 return r; 1363 1364 r = gfx_v10_0_rlc_init(adev); 1365 if (r) { 1366 DRM_ERROR("Failed to init rlc BOs!\n"); 1367 return r; 1368 } 1369 1370 r = gfx_v10_0_mec_init(adev); 1371 if (r) { 1372 DRM_ERROR("Failed to init MEC BOs!\n"); 1373 return r; 1374 } 1375 1376 /* set up the gfx ring */ 1377 for (i = 0; i < adev->gfx.me.num_me; i++) { 1378 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1379 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1380 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1381 continue; 1382 1383 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 1384 i, k, j); 1385 if (r) 1386 return r; 1387 ring_id++; 1388 } 1389 } 1390 } 1391 1392 ring_id = 0; 1393 /* set up the compute queues - allocate horizontally across pipes */ 1394 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1395 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1396 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1397 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1398 j)) 1399 continue; 1400 1401 r = gfx_v10_0_compute_ring_init(adev, ring_id, 1402 i, k, j); 1403 if (r) 1404 return r; 1405 1406 ring_id++; 1407 } 1408 } 1409 } 1410 1411 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 1412 if (r) { 1413 DRM_ERROR("Failed to init KIQ BOs!\n"); 1414 return r; 1415 } 1416 1417 kiq = &adev->gfx.kiq; 1418 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1419 if (r) 1420 return r; 1421 1422 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 1423 if (r) 1424 return r; 1425 1426 /* allocate visible FB for rlc auto-loading fw */ 1427 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1428 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 1429 if (r) 1430 return r; 1431 } 1432 1433 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 1434 1435 gfx_v10_0_gpu_early_init(adev); 1436 1437 return 0; 1438 } 1439 1440 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 1441 { 1442 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1443 &adev->gfx.pfp.pfp_fw_gpu_addr, 1444 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1445 } 1446 1447 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 1448 { 1449 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 1450 &adev->gfx.ce.ce_fw_gpu_addr, 1451 (void **)&adev->gfx.ce.ce_fw_ptr); 1452 } 1453 1454 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 1455 { 1456 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1457 &adev->gfx.me.me_fw_gpu_addr, 1458 (void **)&adev->gfx.me.me_fw_ptr); 1459 } 1460 1461 static int gfx_v10_0_sw_fini(void *handle) 1462 { 1463 int i; 1464 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1465 1466 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1467 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1468 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1469 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1470 1471 amdgpu_gfx_mqd_sw_fini(adev); 1472 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1473 amdgpu_gfx_kiq_fini(adev); 1474 1475 gfx_v10_0_pfp_fini(adev); 1476 gfx_v10_0_ce_fini(adev); 1477 gfx_v10_0_me_fini(adev); 1478 gfx_v10_0_rlc_fini(adev); 1479 gfx_v10_0_mec_fini(adev); 1480 1481 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1482 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 1483 1484 gfx_v10_0_free_microcode(adev); 1485 1486 return 0; 1487 } 1488 1489 1490 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev) 1491 { 1492 /* TODO */ 1493 } 1494 1495 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1496 u32 sh_num, u32 instance) 1497 { 1498 u32 data; 1499 1500 if (instance == 0xffffffff) 1501 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1502 INSTANCE_BROADCAST_WRITES, 1); 1503 else 1504 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1505 instance); 1506 1507 if (se_num == 0xffffffff) 1508 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1509 1); 1510 else 1511 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1512 1513 if (sh_num == 0xffffffff) 1514 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1515 1); 1516 else 1517 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1518 1519 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1520 } 1521 1522 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1523 { 1524 u32 data, mask; 1525 1526 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1527 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1528 1529 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1530 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1531 1532 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1533 adev->gfx.config.max_sh_per_se); 1534 1535 return (~data) & mask; 1536 } 1537 1538 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 1539 { 1540 int i, j; 1541 u32 data; 1542 u32 active_rbs = 0; 1543 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1544 adev->gfx.config.max_sh_per_se; 1545 1546 mutex_lock(&adev->grbm_idx_mutex); 1547 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1548 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1549 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1550 data = gfx_v10_0_get_rb_active_bitmap(adev); 1551 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1552 rb_bitmap_width_per_sh); 1553 } 1554 } 1555 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1556 mutex_unlock(&adev->grbm_idx_mutex); 1557 1558 adev->gfx.config.backend_enable_mask = active_rbs; 1559 adev->gfx.config.num_rbs = hweight32(active_rbs); 1560 } 1561 1562 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 1563 { 1564 uint32_t num_sc; 1565 uint32_t enabled_rb_per_sh; 1566 uint32_t active_rb_bitmap; 1567 uint32_t num_rb_per_sc; 1568 uint32_t num_packer_per_sc; 1569 uint32_t pa_sc_tile_steering_override; 1570 1571 /* init num_sc */ 1572 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 1573 adev->gfx.config.num_sc_per_sh; 1574 /* init num_rb_per_sc */ 1575 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 1576 enabled_rb_per_sh = hweight32(active_rb_bitmap); 1577 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 1578 /* init num_packer_per_sc */ 1579 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 1580 1581 pa_sc_tile_steering_override = 0; 1582 pa_sc_tile_steering_override |= 1583 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 1584 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 1585 pa_sc_tile_steering_override |= 1586 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 1587 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 1588 pa_sc_tile_steering_override |= 1589 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 1590 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 1591 1592 return pa_sc_tile_steering_override; 1593 } 1594 1595 #define DEFAULT_SH_MEM_BASES (0x6000) 1596 #define FIRST_COMPUTE_VMID (8) 1597 #define LAST_COMPUTE_VMID (16) 1598 1599 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 1600 { 1601 int i; 1602 uint32_t sh_mem_bases; 1603 1604 /* 1605 * Configure apertures: 1606 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1607 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1608 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1609 */ 1610 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1611 1612 mutex_lock(&adev->srbm_mutex); 1613 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1614 nv_grbm_select(adev, 0, 0, 0, i); 1615 /* CP and shaders */ 1616 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1617 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1618 } 1619 nv_grbm_select(adev, 0, 0, 0, 0); 1620 mutex_unlock(&adev->srbm_mutex); 1621 1622 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1623 acccess. These should be enabled by FW for target VMIDs. */ 1624 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1625 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 1626 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 1627 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 1628 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 1629 } 1630 } 1631 1632 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 1633 { 1634 int vmid; 1635 1636 /* 1637 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1638 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1639 * the driver can enable them for graphics. VMID0 should maintain 1640 * access so that HWS firmware can save/restore entries. 1641 */ 1642 for (vmid = 1; vmid < 16; vmid++) { 1643 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 1644 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 1645 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 1646 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 1647 } 1648 } 1649 1650 1651 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 1652 { 1653 int i, j, k; 1654 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 1655 u32 tmp, wgp_active_bitmap = 0; 1656 u32 gcrd_targets_disable_tcp = 0; 1657 u32 utcl_invreq_disable = 0; 1658 /* 1659 * GCRD_TARGETS_DISABLE field contains 1660 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 1661 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 1662 */ 1663 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 1664 2 * max_wgp_per_sh + /* TCP */ 1665 max_wgp_per_sh + /* SQC */ 1666 4); /* GL1C */ 1667 /* 1668 * UTCL1_UTCL0_INVREQ_DISABLE field contains 1669 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 1670 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 1671 */ 1672 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 1673 2 * max_wgp_per_sh + /* TCP */ 1674 2 * max_wgp_per_sh + /* SQC */ 1675 4 + /* RMI */ 1676 1); /* SQG */ 1677 1678 if (adev->asic_type == CHIP_NAVI10 || 1679 adev->asic_type == CHIP_NAVI14 || 1680 adev->asic_type == CHIP_NAVI12) { 1681 mutex_lock(&adev->grbm_idx_mutex); 1682 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1683 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1684 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1685 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 1686 /* 1687 * Set corresponding TCP bits for the inactive WGPs in 1688 * GCRD_SA_TARGETS_DISABLE 1689 */ 1690 gcrd_targets_disable_tcp = 0; 1691 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 1692 utcl_invreq_disable = 0; 1693 1694 for (k = 0; k < max_wgp_per_sh; k++) { 1695 if (!(wgp_active_bitmap & (1 << k))) { 1696 gcrd_targets_disable_tcp |= 3 << (2 * k); 1697 utcl_invreq_disable |= (3 << (2 * k)) | 1698 (3 << (2 * (max_wgp_per_sh + k))); 1699 } 1700 } 1701 1702 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 1703 /* only override TCP & SQC bits */ 1704 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 1705 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 1706 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 1707 1708 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 1709 /* only override TCP bits */ 1710 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 1711 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 1712 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 1713 } 1714 } 1715 1716 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1717 mutex_unlock(&adev->grbm_idx_mutex); 1718 } 1719 } 1720 1721 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 1722 { 1723 /* TCCs are global (not instanced). */ 1724 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 1725 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 1726 1727 adev->gfx.config.tcc_disabled_mask = 1728 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1729 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1730 } 1731 1732 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 1733 { 1734 u32 tmp; 1735 int i; 1736 1737 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1738 1739 gfx_v10_0_tiling_mode_table_init(adev); 1740 1741 gfx_v10_0_setup_rb(adev); 1742 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 1743 gfx_v10_0_get_tcc_info(adev); 1744 adev->gfx.config.pa_sc_tile_steering_override = 1745 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 1746 1747 /* XXX SH_MEM regs */ 1748 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1749 mutex_lock(&adev->srbm_mutex); 1750 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1751 nv_grbm_select(adev, 0, 0, 0, i); 1752 /* CP and shaders */ 1753 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1754 if (i != 0) { 1755 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1756 (adev->gmc.private_aperture_start >> 48)); 1757 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1758 (adev->gmc.shared_aperture_start >> 48)); 1759 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1760 } 1761 } 1762 nv_grbm_select(adev, 0, 0, 0, 0); 1763 1764 mutex_unlock(&adev->srbm_mutex); 1765 1766 gfx_v10_0_init_compute_vmid(adev); 1767 gfx_v10_0_init_gds_vmid(adev); 1768 1769 } 1770 1771 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1772 bool enable) 1773 { 1774 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1775 1776 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1777 enable ? 1 : 0); 1778 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1779 enable ? 1 : 0); 1780 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1781 enable ? 1 : 0); 1782 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1783 enable ? 1 : 0); 1784 1785 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1786 } 1787 1788 static void gfx_v10_0_init_csb(struct amdgpu_device *adev) 1789 { 1790 /* csib */ 1791 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 1792 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1793 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 1794 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1795 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1796 } 1797 1798 static void gfx_v10_0_init_pg(struct amdgpu_device *adev) 1799 { 1800 int i; 1801 1802 gfx_v10_0_init_csb(adev); 1803 1804 for (i = 0; i < adev->num_vmhubs; i++) 1805 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 1806 1807 /* TODO: init power gating */ 1808 return; 1809 } 1810 1811 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 1812 { 1813 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 1814 1815 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1816 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 1817 } 1818 1819 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 1820 { 1821 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1822 udelay(50); 1823 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1824 udelay(50); 1825 } 1826 1827 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1828 bool enable) 1829 { 1830 uint32_t rlc_pg_cntl; 1831 1832 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 1833 1834 if (!enable) { 1835 /* RLC_PG_CNTL[23] = 0 (default) 1836 * RLC will wait for handshake acks with SMU 1837 * GFXOFF will be enabled 1838 * RLC_PG_CNTL[23] = 1 1839 * RLC will not issue any message to SMU 1840 * hence no handshake between SMU & RLC 1841 * GFXOFF will be disabled 1842 */ 1843 rlc_pg_cntl |= 0x800000; 1844 } else 1845 rlc_pg_cntl &= ~0x800000; 1846 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 1847 } 1848 1849 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 1850 { 1851 /* TODO: enable rlc & smu handshake until smu 1852 * and gfxoff feature works as expected */ 1853 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1854 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 1855 1856 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1857 udelay(50); 1858 } 1859 1860 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 1861 { 1862 uint32_t tmp; 1863 1864 /* enable Save Restore Machine */ 1865 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1866 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1867 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1868 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1869 } 1870 1871 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 1872 { 1873 const struct rlc_firmware_header_v2_0 *hdr; 1874 const __le32 *fw_data; 1875 unsigned i, fw_size; 1876 1877 if (!adev->gfx.rlc_fw) 1878 return -EINVAL; 1879 1880 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1881 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1882 1883 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1884 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1885 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1886 1887 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 1888 RLCG_UCODE_LOADING_START_ADDRESS); 1889 1890 for (i = 0; i < fw_size; i++) 1891 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 1892 le32_to_cpup(fw_data++)); 1893 1894 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1895 1896 return 0; 1897 } 1898 1899 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 1900 { 1901 int r; 1902 1903 if (amdgpu_sriov_vf(adev)) 1904 return 0; 1905 1906 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1907 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1908 if (r) 1909 return r; 1910 gfx_v10_0_init_pg(adev); 1911 1912 /* enable RLC SRM */ 1913 gfx_v10_0_rlc_enable_srm(adev); 1914 1915 } else { 1916 adev->gfx.rlc.funcs->stop(adev); 1917 1918 /* disable CG */ 1919 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 1920 1921 /* disable PG */ 1922 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 1923 1924 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1925 /* legacy rlc firmware loading */ 1926 r = gfx_v10_0_rlc_load_microcode(adev); 1927 if (r) 1928 return r; 1929 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1930 /* rlc backdoor autoload firmware */ 1931 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 1932 if (r) 1933 return r; 1934 } 1935 1936 gfx_v10_0_init_pg(adev); 1937 adev->gfx.rlc.funcs->start(adev); 1938 1939 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1940 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1941 if (r) 1942 return r; 1943 } 1944 } 1945 return 0; 1946 } 1947 1948 static struct { 1949 FIRMWARE_ID id; 1950 unsigned int offset; 1951 unsigned int size; 1952 } rlc_autoload_info[FIRMWARE_ID_MAX]; 1953 1954 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 1955 { 1956 int ret; 1957 RLC_TABLE_OF_CONTENT *rlc_toc; 1958 1959 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 1960 AMDGPU_GEM_DOMAIN_GTT, 1961 &adev->gfx.rlc.rlc_toc_bo, 1962 &adev->gfx.rlc.rlc_toc_gpu_addr, 1963 (void **)&adev->gfx.rlc.rlc_toc_buf); 1964 if (ret) { 1965 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 1966 return ret; 1967 } 1968 1969 /* Copy toc from psp sos fw to rlc toc buffer */ 1970 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 1971 1972 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 1973 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 1974 (rlc_toc->id < FIRMWARE_ID_MAX)) { 1975 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 1976 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 1977 /* Offset needs 4KB alignment */ 1978 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 1979 } 1980 1981 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 1982 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 1983 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 1984 1985 rlc_toc++; 1986 }; 1987 1988 return 0; 1989 } 1990 1991 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 1992 { 1993 uint32_t total_size = 0; 1994 FIRMWARE_ID id; 1995 int ret; 1996 1997 ret = gfx_v10_0_parse_rlc_toc(adev); 1998 if (ret) { 1999 dev_err(adev->dev, "failed to parse rlc toc\n"); 2000 return 0; 2001 } 2002 2003 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 2004 total_size += rlc_autoload_info[id].size; 2005 2006 /* In case the offset in rlc toc ucode is aligned */ 2007 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 2008 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 2009 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 2010 2011 return total_size; 2012 } 2013 2014 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 2015 { 2016 int r; 2017 uint32_t total_size; 2018 2019 total_size = gfx_v10_0_calc_toc_total_size(adev); 2020 2021 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 2022 AMDGPU_GEM_DOMAIN_GTT, 2023 &adev->gfx.rlc.rlc_autoload_bo, 2024 &adev->gfx.rlc.rlc_autoload_gpu_addr, 2025 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 2026 if (r) { 2027 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 2028 return r; 2029 } 2030 2031 return 0; 2032 } 2033 2034 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 2035 { 2036 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 2037 &adev->gfx.rlc.rlc_toc_gpu_addr, 2038 (void **)&adev->gfx.rlc.rlc_toc_buf); 2039 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 2040 &adev->gfx.rlc.rlc_autoload_gpu_addr, 2041 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 2042 } 2043 2044 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 2045 FIRMWARE_ID id, 2046 const void *fw_data, 2047 uint32_t fw_size) 2048 { 2049 uint32_t toc_offset; 2050 uint32_t toc_fw_size; 2051 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 2052 2053 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 2054 return; 2055 2056 toc_offset = rlc_autoload_info[id].offset; 2057 toc_fw_size = rlc_autoload_info[id].size; 2058 2059 if (fw_size == 0) 2060 fw_size = toc_fw_size; 2061 2062 if (fw_size > toc_fw_size) 2063 fw_size = toc_fw_size; 2064 2065 memcpy(ptr + toc_offset, fw_data, fw_size); 2066 2067 if (fw_size < toc_fw_size) 2068 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 2069 } 2070 2071 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 2072 { 2073 void *data; 2074 uint32_t size; 2075 2076 data = adev->gfx.rlc.rlc_toc_buf; 2077 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 2078 2079 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2080 FIRMWARE_ID_RLC_TOC, 2081 data, size); 2082 } 2083 2084 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 2085 { 2086 const __le32 *fw_data; 2087 uint32_t fw_size; 2088 const struct gfx_firmware_header_v1_0 *cp_hdr; 2089 const struct rlc_firmware_header_v2_0 *rlc_hdr; 2090 2091 /* pfp ucode */ 2092 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2093 adev->gfx.pfp_fw->data; 2094 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2095 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2096 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2097 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2098 FIRMWARE_ID_CP_PFP, 2099 fw_data, fw_size); 2100 2101 /* ce ucode */ 2102 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2103 adev->gfx.ce_fw->data; 2104 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2105 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2106 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2107 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2108 FIRMWARE_ID_CP_CE, 2109 fw_data, fw_size); 2110 2111 /* me ucode */ 2112 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2113 adev->gfx.me_fw->data; 2114 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2115 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2116 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2117 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2118 FIRMWARE_ID_CP_ME, 2119 fw_data, fw_size); 2120 2121 /* rlc ucode */ 2122 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 2123 adev->gfx.rlc_fw->data; 2124 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2125 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 2126 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 2127 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2128 FIRMWARE_ID_RLC_G_UCODE, 2129 fw_data, fw_size); 2130 2131 /* mec1 ucode */ 2132 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2133 adev->gfx.mec_fw->data; 2134 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2135 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2136 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 2137 cp_hdr->jt_size * 4; 2138 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2139 FIRMWARE_ID_CP_MEC, 2140 fw_data, fw_size); 2141 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 2142 } 2143 2144 /* Temporarily put sdma part here */ 2145 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 2146 { 2147 const __le32 *fw_data; 2148 uint32_t fw_size; 2149 const struct sdma_firmware_header_v1_0 *sdma_hdr; 2150 int i; 2151 2152 for (i = 0; i < adev->sdma.num_instances; i++) { 2153 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 2154 adev->sdma.instance[i].fw->data; 2155 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 2156 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 2157 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 2158 2159 if (i == 0) { 2160 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2161 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 2162 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2163 FIRMWARE_ID_SDMA0_JT, 2164 (uint32_t *)fw_data + 2165 sdma_hdr->jt_offset, 2166 sdma_hdr->jt_size * 4); 2167 } else if (i == 1) { 2168 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2169 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 2170 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2171 FIRMWARE_ID_SDMA1_JT, 2172 (uint32_t *)fw_data + 2173 sdma_hdr->jt_offset, 2174 sdma_hdr->jt_size * 4); 2175 } 2176 } 2177 } 2178 2179 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 2180 { 2181 uint32_t rlc_g_offset, rlc_g_size, tmp; 2182 uint64_t gpu_addr; 2183 2184 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 2185 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 2186 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 2187 2188 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 2189 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 2190 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 2191 2192 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 2193 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 2194 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 2195 2196 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 2197 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 2198 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 2199 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 2200 return -EINVAL; 2201 } 2202 2203 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 2204 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2205 DRM_ERROR("RLC ROM should halt itself\n"); 2206 return -EINVAL; 2207 } 2208 2209 return 0; 2210 } 2211 2212 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 2213 { 2214 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2215 uint32_t tmp; 2216 int i; 2217 uint64_t addr; 2218 2219 /* Trigger an invalidation of the L1 instruction caches */ 2220 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2221 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2222 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2223 2224 /* Wait for invalidation complete */ 2225 for (i = 0; i < usec_timeout; i++) { 2226 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2227 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2228 INVALIDATE_CACHE_COMPLETE)) 2229 break; 2230 udelay(1); 2231 } 2232 2233 if (i >= usec_timeout) { 2234 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2235 return -EINVAL; 2236 } 2237 2238 /* Program me ucode address into intruction cache address register */ 2239 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2240 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 2241 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2242 lower_32_bits(addr) & 0xFFFFF000); 2243 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2244 upper_32_bits(addr)); 2245 2246 return 0; 2247 } 2248 2249 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 2250 { 2251 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2252 uint32_t tmp; 2253 int i; 2254 uint64_t addr; 2255 2256 /* Trigger an invalidation of the L1 instruction caches */ 2257 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2258 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2259 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2260 2261 /* Wait for invalidation complete */ 2262 for (i = 0; i < usec_timeout; i++) { 2263 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2264 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2265 INVALIDATE_CACHE_COMPLETE)) 2266 break; 2267 udelay(1); 2268 } 2269 2270 if (i >= usec_timeout) { 2271 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2272 return -EINVAL; 2273 } 2274 2275 /* Program ce ucode address into intruction cache address register */ 2276 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2277 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 2278 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2279 lower_32_bits(addr) & 0xFFFFF000); 2280 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2281 upper_32_bits(addr)); 2282 2283 return 0; 2284 } 2285 2286 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 2287 { 2288 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2289 uint32_t tmp; 2290 int i; 2291 uint64_t addr; 2292 2293 /* Trigger an invalidation of the L1 instruction caches */ 2294 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2295 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2296 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2297 2298 /* Wait for invalidation complete */ 2299 for (i = 0; i < usec_timeout; i++) { 2300 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2301 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2302 INVALIDATE_CACHE_COMPLETE)) 2303 break; 2304 udelay(1); 2305 } 2306 2307 if (i >= usec_timeout) { 2308 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2309 return -EINVAL; 2310 } 2311 2312 /* Program pfp ucode address into intruction cache address register */ 2313 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2314 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 2315 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2316 lower_32_bits(addr) & 0xFFFFF000); 2317 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2318 upper_32_bits(addr)); 2319 2320 return 0; 2321 } 2322 2323 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 2324 { 2325 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2326 uint32_t tmp; 2327 int i; 2328 uint64_t addr; 2329 2330 /* Trigger an invalidation of the L1 instruction caches */ 2331 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2332 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2333 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2334 2335 /* Wait for invalidation complete */ 2336 for (i = 0; i < usec_timeout; i++) { 2337 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2338 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2339 INVALIDATE_CACHE_COMPLETE)) 2340 break; 2341 udelay(1); 2342 } 2343 2344 if (i >= usec_timeout) { 2345 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2346 return -EINVAL; 2347 } 2348 2349 /* Program mec1 ucode address into intruction cache address register */ 2350 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2351 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 2352 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2353 lower_32_bits(addr) & 0xFFFFF000); 2354 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2355 upper_32_bits(addr)); 2356 2357 return 0; 2358 } 2359 2360 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2361 { 2362 uint32_t cp_status; 2363 uint32_t bootload_status; 2364 int i, r; 2365 2366 for (i = 0; i < adev->usec_timeout; i++) { 2367 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 2368 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 2369 if ((cp_status == 0) && 2370 (REG_GET_FIELD(bootload_status, 2371 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2372 break; 2373 } 2374 udelay(1); 2375 } 2376 2377 if (i >= adev->usec_timeout) { 2378 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2379 return -ETIMEDOUT; 2380 } 2381 2382 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2383 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 2384 if (r) 2385 return r; 2386 2387 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 2388 if (r) 2389 return r; 2390 2391 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 2392 if (r) 2393 return r; 2394 2395 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 2396 if (r) 2397 return r; 2398 } 2399 2400 return 0; 2401 } 2402 2403 static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2404 { 2405 int i; 2406 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2407 2408 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2409 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2410 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2411 if (!enable) { 2412 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2413 adev->gfx.gfx_ring[i].sched.ready = false; 2414 } 2415 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2416 udelay(50); 2417 } 2418 2419 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2420 { 2421 int r; 2422 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2423 const __le32 *fw_data; 2424 unsigned i, fw_size; 2425 uint32_t tmp; 2426 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2427 2428 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2429 adev->gfx.pfp_fw->data; 2430 2431 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2432 2433 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2434 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2435 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2436 2437 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2438 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2439 &adev->gfx.pfp.pfp_fw_obj, 2440 &adev->gfx.pfp.pfp_fw_gpu_addr, 2441 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2442 if (r) { 2443 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2444 gfx_v10_0_pfp_fini(adev); 2445 return r; 2446 } 2447 2448 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2449 2450 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2451 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2452 2453 /* Trigger an invalidation of the L1 instruction caches */ 2454 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2455 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2456 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2457 2458 /* Wait for invalidation complete */ 2459 for (i = 0; i < usec_timeout; i++) { 2460 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2461 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2462 INVALIDATE_CACHE_COMPLETE)) 2463 break; 2464 udelay(1); 2465 } 2466 2467 if (i >= usec_timeout) { 2468 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2469 return -EINVAL; 2470 } 2471 2472 if (amdgpu_emu_mode == 1) 2473 adev->nbio_funcs->hdp_flush(adev, NULL); 2474 2475 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 2476 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2477 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2478 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2479 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2480 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 2481 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2482 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 2483 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2484 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2485 2486 return 0; 2487 } 2488 2489 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 2490 { 2491 int r; 2492 const struct gfx_firmware_header_v1_0 *ce_hdr; 2493 const __le32 *fw_data; 2494 unsigned i, fw_size; 2495 uint32_t tmp; 2496 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2497 2498 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2499 adev->gfx.ce_fw->data; 2500 2501 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2502 2503 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2504 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2505 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 2506 2507 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 2508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2509 &adev->gfx.ce.ce_fw_obj, 2510 &adev->gfx.ce.ce_fw_gpu_addr, 2511 (void **)&adev->gfx.ce.ce_fw_ptr); 2512 if (r) { 2513 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 2514 gfx_v10_0_ce_fini(adev); 2515 return r; 2516 } 2517 2518 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 2519 2520 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 2521 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 2522 2523 /* Trigger an invalidation of the L1 instruction caches */ 2524 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2525 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2526 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2527 2528 /* Wait for invalidation complete */ 2529 for (i = 0; i < usec_timeout; i++) { 2530 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2531 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2532 INVALIDATE_CACHE_COMPLETE)) 2533 break; 2534 udelay(1); 2535 } 2536 2537 if (i >= usec_timeout) { 2538 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2539 return -EINVAL; 2540 } 2541 2542 if (amdgpu_emu_mode == 1) 2543 adev->nbio_funcs->hdp_flush(adev, NULL); 2544 2545 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 2546 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 2547 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 2548 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 2549 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2550 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2551 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 2552 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2553 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 2554 2555 return 0; 2556 } 2557 2558 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2559 { 2560 int r; 2561 const struct gfx_firmware_header_v1_0 *me_hdr; 2562 const __le32 *fw_data; 2563 unsigned i, fw_size; 2564 uint32_t tmp; 2565 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2566 2567 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2568 adev->gfx.me_fw->data; 2569 2570 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2571 2572 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2573 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2574 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2575 2576 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2577 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2578 &adev->gfx.me.me_fw_obj, 2579 &adev->gfx.me.me_fw_gpu_addr, 2580 (void **)&adev->gfx.me.me_fw_ptr); 2581 if (r) { 2582 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2583 gfx_v10_0_me_fini(adev); 2584 return r; 2585 } 2586 2587 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2588 2589 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2590 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2591 2592 /* Trigger an invalidation of the L1 instruction caches */ 2593 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2594 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2595 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2596 2597 /* Wait for invalidation complete */ 2598 for (i = 0; i < usec_timeout; i++) { 2599 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2600 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2601 INVALIDATE_CACHE_COMPLETE)) 2602 break; 2603 udelay(1); 2604 } 2605 2606 if (i >= usec_timeout) { 2607 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2608 return -EINVAL; 2609 } 2610 2611 if (amdgpu_emu_mode == 1) 2612 adev->nbio_funcs->hdp_flush(adev, NULL); 2613 2614 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 2615 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2616 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2617 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2618 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2619 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2620 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 2621 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2622 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2623 2624 return 0; 2625 } 2626 2627 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2628 { 2629 int r; 2630 2631 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2632 return -EINVAL; 2633 2634 gfx_v10_0_cp_gfx_enable(adev, false); 2635 2636 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 2637 if (r) { 2638 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2639 return r; 2640 } 2641 2642 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 2643 if (r) { 2644 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 2645 return r; 2646 } 2647 2648 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 2649 if (r) { 2650 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2651 return r; 2652 } 2653 2654 return 0; 2655 } 2656 2657 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 2658 { 2659 struct amdgpu_ring *ring; 2660 const struct cs_section_def *sect = NULL; 2661 const struct cs_extent_def *ext = NULL; 2662 int r, i; 2663 int ctx_reg_offset; 2664 2665 /* init the CP */ 2666 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 2667 adev->gfx.config.max_hw_contexts - 1); 2668 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2669 2670 gfx_v10_0_cp_gfx_enable(adev, true); 2671 2672 ring = &adev->gfx.gfx_ring[0]; 2673 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 2674 if (r) { 2675 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2676 return r; 2677 } 2678 2679 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2680 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2681 2682 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2683 amdgpu_ring_write(ring, 0x80000000); 2684 amdgpu_ring_write(ring, 0x80000000); 2685 2686 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 2687 for (ext = sect->section; ext->extent != NULL; ++ext) { 2688 if (sect->id == SECT_CONTEXT) { 2689 amdgpu_ring_write(ring, 2690 PACKET3(PACKET3_SET_CONTEXT_REG, 2691 ext->reg_count)); 2692 amdgpu_ring_write(ring, ext->reg_index - 2693 PACKET3_SET_CONTEXT_REG_START); 2694 for (i = 0; i < ext->reg_count; i++) 2695 amdgpu_ring_write(ring, ext->extent[i]); 2696 } 2697 } 2698 } 2699 2700 ctx_reg_offset = 2701 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 2702 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2703 amdgpu_ring_write(ring, ctx_reg_offset); 2704 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 2705 2706 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2707 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2708 2709 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2710 amdgpu_ring_write(ring, 0); 2711 2712 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2713 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2714 amdgpu_ring_write(ring, 0x8000); 2715 amdgpu_ring_write(ring, 0x8000); 2716 2717 amdgpu_ring_commit(ring); 2718 2719 /* submit cs packet to copy state 0 to next available state */ 2720 ring = &adev->gfx.gfx_ring[1]; 2721 r = amdgpu_ring_alloc(ring, 2); 2722 if (r) { 2723 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2724 return r; 2725 } 2726 2727 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2728 amdgpu_ring_write(ring, 0); 2729 2730 amdgpu_ring_commit(ring); 2731 2732 return 0; 2733 } 2734 2735 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2736 CP_PIPE_ID pipe) 2737 { 2738 u32 tmp; 2739 2740 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 2741 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2742 2743 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 2744 } 2745 2746 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2747 struct amdgpu_ring *ring) 2748 { 2749 u32 tmp; 2750 2751 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2752 if (ring->use_doorbell) { 2753 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2754 DOORBELL_OFFSET, ring->doorbell_index); 2755 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2756 DOORBELL_EN, 1); 2757 } else { 2758 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2759 DOORBELL_EN, 0); 2760 } 2761 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2762 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2763 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2764 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2765 2766 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2767 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2768 } 2769 2770 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 2771 { 2772 struct amdgpu_ring *ring; 2773 u32 tmp; 2774 u32 rb_bufsz; 2775 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2776 u32 i; 2777 2778 /* Set the write pointer delay */ 2779 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2780 2781 /* set the RB to use vmid 0 */ 2782 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2783 2784 /* Init gfx ring 0 for pipe 0 */ 2785 mutex_lock(&adev->srbm_mutex); 2786 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2787 mutex_unlock(&adev->srbm_mutex); 2788 /* Set ring buffer size */ 2789 ring = &adev->gfx.gfx_ring[0]; 2790 rb_bufsz = order_base_2(ring->ring_size / 8); 2791 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2792 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2793 #ifdef __BIG_ENDIAN 2794 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2795 #endif 2796 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2797 2798 /* Initialize the ring buffer's write pointers */ 2799 ring->wptr = 0; 2800 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2801 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2802 2803 /* set the wb address wether it's enabled or not */ 2804 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2805 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2806 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2807 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2808 2809 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2810 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2811 lower_32_bits(wptr_gpu_addr)); 2812 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2813 upper_32_bits(wptr_gpu_addr)); 2814 2815 mdelay(1); 2816 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2817 2818 rb_addr = ring->gpu_addr >> 8; 2819 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2820 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2821 2822 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 2823 2824 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2825 2826 /* Init gfx ring 1 for pipe 1 */ 2827 mutex_lock(&adev->srbm_mutex); 2828 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 2829 mutex_unlock(&adev->srbm_mutex); 2830 ring = &adev->gfx.gfx_ring[1]; 2831 rb_bufsz = order_base_2(ring->ring_size / 8); 2832 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 2833 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 2834 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2835 /* Initialize the ring buffer's write pointers */ 2836 ring->wptr = 0; 2837 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2838 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 2839 /* Set the wb address wether it's enabled or not */ 2840 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2841 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2842 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2843 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2844 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2845 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2846 lower_32_bits(wptr_gpu_addr)); 2847 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2848 upper_32_bits(wptr_gpu_addr)); 2849 2850 mdelay(1); 2851 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2852 2853 rb_addr = ring->gpu_addr >> 8; 2854 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 2855 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 2856 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 2857 2858 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2859 2860 /* Switch to pipe 0 */ 2861 mutex_lock(&adev->srbm_mutex); 2862 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2863 mutex_unlock(&adev->srbm_mutex); 2864 2865 /* start the ring */ 2866 gfx_v10_0_cp_gfx_start(adev); 2867 2868 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2869 ring = &adev->gfx.gfx_ring[i]; 2870 ring->sched.ready = true; 2871 } 2872 2873 return 0; 2874 } 2875 2876 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2877 { 2878 int i; 2879 2880 if (enable) { 2881 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2882 } else { 2883 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2884 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 2885 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2886 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2887 adev->gfx.compute_ring[i].sched.ready = false; 2888 adev->gfx.kiq.ring.sched.ready = false; 2889 } 2890 udelay(50); 2891 } 2892 2893 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2894 { 2895 const struct gfx_firmware_header_v1_0 *mec_hdr; 2896 const __le32 *fw_data; 2897 unsigned i; 2898 u32 tmp; 2899 u32 usec_timeout = 50000; /* Wait for 50 ms */ 2900 2901 if (!adev->gfx.mec_fw) 2902 return -EINVAL; 2903 2904 gfx_v10_0_cp_compute_enable(adev, false); 2905 2906 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2907 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2908 2909 fw_data = (const __le32 *) 2910 (adev->gfx.mec_fw->data + 2911 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2912 2913 /* Trigger an invalidation of the L1 instruction caches */ 2914 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2915 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2916 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2917 2918 /* Wait for invalidation complete */ 2919 for (i = 0; i < usec_timeout; i++) { 2920 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2921 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2922 INVALIDATE_CACHE_COMPLETE)) 2923 break; 2924 udelay(1); 2925 } 2926 2927 if (i >= usec_timeout) { 2928 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2929 return -EINVAL; 2930 } 2931 2932 if (amdgpu_emu_mode == 1) 2933 adev->nbio_funcs->hdp_flush(adev, NULL); 2934 2935 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 2936 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2937 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2938 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2939 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2940 2941 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 2942 0xFFFFF000); 2943 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2944 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2945 2946 /* MEC1 */ 2947 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 2948 2949 for (i = 0; i < mec_hdr->jt_size; i++) 2950 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2951 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2952 2953 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 2954 2955 /* 2956 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 2957 * different microcode than MEC1. 2958 */ 2959 2960 return 0; 2961 } 2962 2963 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 2964 { 2965 uint32_t tmp; 2966 struct amdgpu_device *adev = ring->adev; 2967 2968 /* tell RLC which is KIQ queue */ 2969 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2970 tmp &= 0xffffff00; 2971 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2972 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2973 tmp |= 0x80; 2974 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2975 } 2976 2977 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 2978 { 2979 struct amdgpu_device *adev = ring->adev; 2980 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 2981 uint64_t hqd_gpu_addr, wb_gpu_addr; 2982 uint32_t tmp; 2983 uint32_t rb_bufsz; 2984 2985 /* set up gfx hqd wptr */ 2986 mqd->cp_gfx_hqd_wptr = 0; 2987 mqd->cp_gfx_hqd_wptr_hi = 0; 2988 2989 /* set the pointer to the MQD */ 2990 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 2991 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2992 2993 /* set up mqd control */ 2994 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 2995 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2996 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2997 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2998 mqd->cp_gfx_mqd_control = tmp; 2999 3000 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3001 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 3002 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3003 mqd->cp_gfx_hqd_vmid = 0; 3004 3005 /* set up default queue priority level 3006 * 0x0 = low priority, 0x1 = high priority */ 3007 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 3008 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3009 mqd->cp_gfx_hqd_queue_priority = tmp; 3010 3011 /* set up time quantum */ 3012 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 3013 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3014 mqd->cp_gfx_hqd_quantum = tmp; 3015 3016 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3017 hqd_gpu_addr = ring->gpu_addr >> 8; 3018 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3019 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3020 3021 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3022 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3023 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3024 mqd->cp_gfx_hqd_rptr_addr_hi = 3025 upper_32_bits(wb_gpu_addr) & 0xffff; 3026 3027 /* set up rb_wptr_poll addr */ 3028 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3029 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3030 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3031 3032 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3033 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 3034 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 3035 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3036 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3037 #ifdef __BIG_ENDIAN 3038 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3039 #endif 3040 mqd->cp_gfx_hqd_cntl = tmp; 3041 3042 /* set up cp_doorbell_control */ 3043 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3044 if (ring->use_doorbell) { 3045 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3046 DOORBELL_OFFSET, ring->doorbell_index); 3047 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3048 DOORBELL_EN, 1); 3049 } else 3050 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3051 DOORBELL_EN, 0); 3052 mqd->cp_rb_doorbell_control = tmp; 3053 3054 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3055 ring->wptr = 0; 3056 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 3057 3058 /* active the queue */ 3059 mqd->cp_gfx_hqd_active = 1; 3060 3061 return 0; 3062 } 3063 3064 #ifdef BRING_UP_DEBUG 3065 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3066 { 3067 struct amdgpu_device *adev = ring->adev; 3068 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3069 3070 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3071 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3072 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3073 3074 /* set GFX_MQD_BASE */ 3075 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3076 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3077 3078 /* set GFX_MQD_CONTROL */ 3079 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3080 3081 /* set GFX_HQD_VMID to 0 */ 3082 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3083 3084 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 3085 mqd->cp_gfx_hqd_queue_priority); 3086 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3087 3088 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3089 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3090 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3091 3092 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3093 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3094 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3095 3096 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3097 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3098 3099 /* set RB_WPTR_POLL_ADDR */ 3100 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3101 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3102 3103 /* set RB_DOORBELL_CONTROL */ 3104 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3105 3106 /* active the queue */ 3107 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3108 3109 return 0; 3110 } 3111 #endif 3112 3113 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 3114 { 3115 struct amdgpu_device *adev = ring->adev; 3116 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3117 3118 if (!adev->in_gpu_reset && !adev->in_suspend) { 3119 memset((void *)mqd, 0, sizeof(*mqd)); 3120 mutex_lock(&adev->srbm_mutex); 3121 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3122 gfx_v10_0_gfx_mqd_init(ring); 3123 #ifdef BRING_UP_DEBUG 3124 gfx_v10_0_gfx_queue_init_register(ring); 3125 #endif 3126 nv_grbm_select(adev, 0, 0, 0, 0); 3127 mutex_unlock(&adev->srbm_mutex); 3128 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]) 3129 memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd)); 3130 } else if (adev->in_gpu_reset) { 3131 /* reset mqd with the backup copy */ 3132 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]) 3133 memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd)); 3134 /* reset the ring */ 3135 ring->wptr = 0; 3136 amdgpu_ring_clear_ring(ring); 3137 #ifdef BRING_UP_DEBUG 3138 mutex_lock(&adev->srbm_mutex); 3139 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3140 gfx_v10_0_gfx_queue_init_register(ring); 3141 nv_grbm_select(adev, 0, 0, 0, 0); 3142 mutex_unlock(&adev->srbm_mutex); 3143 #endif 3144 } else { 3145 amdgpu_ring_clear_ring(ring); 3146 } 3147 3148 return 0; 3149 } 3150 3151 #ifndef BRING_UP_DEBUG 3152 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 3153 { 3154 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3155 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3156 int r, i; 3157 3158 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3159 return -EINVAL; 3160 3161 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3162 adev->gfx.num_gfx_rings); 3163 if (r) { 3164 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3165 return r; 3166 } 3167 3168 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3169 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3170 3171 r = amdgpu_ring_test_ring(kiq_ring); 3172 if (r) { 3173 DRM_ERROR("kfq enable failed\n"); 3174 kiq_ring->sched.ready = false; 3175 } 3176 return r; 3177 } 3178 #endif 3179 3180 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3181 { 3182 int r, i; 3183 struct amdgpu_ring *ring; 3184 3185 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3186 ring = &adev->gfx.gfx_ring[i]; 3187 3188 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3189 if (unlikely(r != 0)) 3190 goto done; 3191 3192 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3193 if (!r) { 3194 r = gfx_v10_0_gfx_init_queue(ring); 3195 amdgpu_bo_kunmap(ring->mqd_obj); 3196 ring->mqd_ptr = NULL; 3197 } 3198 amdgpu_bo_unreserve(ring->mqd_obj); 3199 if (r) 3200 goto done; 3201 } 3202 #ifndef BRING_UP_DEBUG 3203 r = gfx_v10_0_kiq_enable_kgq(adev); 3204 if (r) 3205 goto done; 3206 #endif 3207 r = gfx_v10_0_cp_gfx_start(adev); 3208 if (r) 3209 goto done; 3210 3211 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3212 ring = &adev->gfx.gfx_ring[i]; 3213 ring->sched.ready = true; 3214 } 3215 done: 3216 return r; 3217 } 3218 3219 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 3220 { 3221 struct amdgpu_device *adev = ring->adev; 3222 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3223 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3224 uint32_t tmp; 3225 3226 mqd->header = 0xC0310800; 3227 mqd->compute_pipelinestat_enable = 0x00000001; 3228 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3229 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3230 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3231 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3232 mqd->compute_misc_reserved = 0x00000003; 3233 3234 eop_base_addr = ring->eop_gpu_addr >> 8; 3235 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3236 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3237 3238 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3239 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3240 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3241 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 3242 3243 mqd->cp_hqd_eop_control = tmp; 3244 3245 /* enable doorbell? */ 3246 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3247 3248 if (ring->use_doorbell) { 3249 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3250 DOORBELL_OFFSET, ring->doorbell_index); 3251 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3252 DOORBELL_EN, 1); 3253 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3254 DOORBELL_SOURCE, 0); 3255 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3256 DOORBELL_HIT, 0); 3257 } else { 3258 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3259 DOORBELL_EN, 0); 3260 } 3261 3262 mqd->cp_hqd_pq_doorbell_control = tmp; 3263 3264 /* disable the queue if it's active */ 3265 ring->wptr = 0; 3266 mqd->cp_hqd_dequeue_request = 0; 3267 mqd->cp_hqd_pq_rptr = 0; 3268 mqd->cp_hqd_pq_wptr_lo = 0; 3269 mqd->cp_hqd_pq_wptr_hi = 0; 3270 3271 /* set the pointer to the MQD */ 3272 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3273 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3274 3275 /* set MQD vmid to 0 */ 3276 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3277 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3278 mqd->cp_mqd_control = tmp; 3279 3280 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3281 hqd_gpu_addr = ring->gpu_addr >> 8; 3282 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3283 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3284 3285 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3286 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3287 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3288 (order_base_2(ring->ring_size / 4) - 1)); 3289 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3290 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3291 #ifdef __BIG_ENDIAN 3292 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3293 #endif 3294 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3295 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3296 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3297 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3298 mqd->cp_hqd_pq_control = tmp; 3299 3300 /* set the wb address whether it's enabled or not */ 3301 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3302 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3303 mqd->cp_hqd_pq_rptr_report_addr_hi = 3304 upper_32_bits(wb_gpu_addr) & 0xffff; 3305 3306 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3307 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3308 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3309 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3310 3311 tmp = 0; 3312 /* enable the doorbell if requested */ 3313 if (ring->use_doorbell) { 3314 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3315 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3316 DOORBELL_OFFSET, ring->doorbell_index); 3317 3318 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3319 DOORBELL_EN, 1); 3320 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3321 DOORBELL_SOURCE, 0); 3322 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3323 DOORBELL_HIT, 0); 3324 } 3325 3326 mqd->cp_hqd_pq_doorbell_control = tmp; 3327 3328 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3329 ring->wptr = 0; 3330 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3331 3332 /* set the vmid for the queue */ 3333 mqd->cp_hqd_vmid = 0; 3334 3335 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3336 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3337 mqd->cp_hqd_persistent_state = tmp; 3338 3339 /* set MIN_IB_AVAIL_SIZE */ 3340 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3341 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3342 mqd->cp_hqd_ib_control = tmp; 3343 3344 /* activate the queue */ 3345 mqd->cp_hqd_active = 1; 3346 3347 return 0; 3348 } 3349 3350 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 3351 { 3352 struct amdgpu_device *adev = ring->adev; 3353 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3354 int j; 3355 3356 /* disable wptr polling */ 3357 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3358 3359 /* write the EOP addr */ 3360 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3361 mqd->cp_hqd_eop_base_addr_lo); 3362 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3363 mqd->cp_hqd_eop_base_addr_hi); 3364 3365 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3366 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 3367 mqd->cp_hqd_eop_control); 3368 3369 /* enable doorbell? */ 3370 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3371 mqd->cp_hqd_pq_doorbell_control); 3372 3373 /* disable the queue if it's active */ 3374 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3375 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3376 for (j = 0; j < adev->usec_timeout; j++) { 3377 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3378 break; 3379 udelay(1); 3380 } 3381 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3382 mqd->cp_hqd_dequeue_request); 3383 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 3384 mqd->cp_hqd_pq_rptr); 3385 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3386 mqd->cp_hqd_pq_wptr_lo); 3387 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3388 mqd->cp_hqd_pq_wptr_hi); 3389 } 3390 3391 /* set the pointer to the MQD */ 3392 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 3393 mqd->cp_mqd_base_addr_lo); 3394 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3395 mqd->cp_mqd_base_addr_hi); 3396 3397 /* set MQD vmid to 0 */ 3398 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 3399 mqd->cp_mqd_control); 3400 3401 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3402 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 3403 mqd->cp_hqd_pq_base_lo); 3404 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 3405 mqd->cp_hqd_pq_base_hi); 3406 3407 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3408 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 3409 mqd->cp_hqd_pq_control); 3410 3411 /* set the wb address whether it's enabled or not */ 3412 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3413 mqd->cp_hqd_pq_rptr_report_addr_lo); 3414 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3415 mqd->cp_hqd_pq_rptr_report_addr_hi); 3416 3417 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3418 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3419 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3420 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3421 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3422 3423 /* enable the doorbell if requested */ 3424 if (ring->use_doorbell) { 3425 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3426 (adev->doorbell_index.kiq * 2) << 2); 3427 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3428 (adev->doorbell_index.userqueue_end * 2) << 2); 3429 } 3430 3431 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3432 mqd->cp_hqd_pq_doorbell_control); 3433 3434 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3435 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3436 mqd->cp_hqd_pq_wptr_lo); 3437 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3438 mqd->cp_hqd_pq_wptr_hi); 3439 3440 /* set the vmid for the queue */ 3441 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3442 3443 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3444 mqd->cp_hqd_persistent_state); 3445 3446 /* activate the queue */ 3447 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 3448 mqd->cp_hqd_active); 3449 3450 if (ring->use_doorbell) 3451 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3452 3453 return 0; 3454 } 3455 3456 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 3457 { 3458 struct amdgpu_device *adev = ring->adev; 3459 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3460 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3461 3462 gfx_v10_0_kiq_setting(ring); 3463 3464 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3465 /* reset MQD to a clean status */ 3466 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3467 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3468 3469 /* reset ring buffer */ 3470 ring->wptr = 0; 3471 amdgpu_ring_clear_ring(ring); 3472 3473 mutex_lock(&adev->srbm_mutex); 3474 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3475 gfx_v10_0_kiq_init_register(ring); 3476 nv_grbm_select(adev, 0, 0, 0, 0); 3477 mutex_unlock(&adev->srbm_mutex); 3478 } else { 3479 memset((void *)mqd, 0, sizeof(*mqd)); 3480 mutex_lock(&adev->srbm_mutex); 3481 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3482 gfx_v10_0_compute_mqd_init(ring); 3483 gfx_v10_0_kiq_init_register(ring); 3484 nv_grbm_select(adev, 0, 0, 0, 0); 3485 mutex_unlock(&adev->srbm_mutex); 3486 3487 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3488 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3489 } 3490 3491 return 0; 3492 } 3493 3494 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 3495 { 3496 struct amdgpu_device *adev = ring->adev; 3497 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3498 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3499 3500 if (!adev->in_gpu_reset && !adev->in_suspend) { 3501 memset((void *)mqd, 0, sizeof(*mqd)); 3502 mutex_lock(&adev->srbm_mutex); 3503 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3504 gfx_v10_0_compute_mqd_init(ring); 3505 nv_grbm_select(adev, 0, 0, 0, 0); 3506 mutex_unlock(&adev->srbm_mutex); 3507 3508 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3509 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3510 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3511 /* reset MQD to a clean status */ 3512 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3513 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3514 3515 /* reset ring buffer */ 3516 ring->wptr = 0; 3517 amdgpu_ring_clear_ring(ring); 3518 } else { 3519 amdgpu_ring_clear_ring(ring); 3520 } 3521 3522 return 0; 3523 } 3524 3525 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 3526 { 3527 struct amdgpu_ring *ring; 3528 int r; 3529 3530 ring = &adev->gfx.kiq.ring; 3531 3532 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3533 if (unlikely(r != 0)) 3534 return r; 3535 3536 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3537 if (unlikely(r != 0)) 3538 return r; 3539 3540 gfx_v10_0_kiq_init_queue(ring); 3541 amdgpu_bo_kunmap(ring->mqd_obj); 3542 ring->mqd_ptr = NULL; 3543 amdgpu_bo_unreserve(ring->mqd_obj); 3544 ring->sched.ready = true; 3545 return 0; 3546 } 3547 3548 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 3549 { 3550 struct amdgpu_ring *ring = NULL; 3551 int r = 0, i; 3552 3553 gfx_v10_0_cp_compute_enable(adev, true); 3554 3555 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3556 ring = &adev->gfx.compute_ring[i]; 3557 3558 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3559 if (unlikely(r != 0)) 3560 goto done; 3561 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3562 if (!r) { 3563 r = gfx_v10_0_kcq_init_queue(ring); 3564 amdgpu_bo_kunmap(ring->mqd_obj); 3565 ring->mqd_ptr = NULL; 3566 } 3567 amdgpu_bo_unreserve(ring->mqd_obj); 3568 if (r) 3569 goto done; 3570 } 3571 3572 r = amdgpu_gfx_enable_kcq(adev); 3573 done: 3574 return r; 3575 } 3576 3577 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 3578 { 3579 int r, i; 3580 struct amdgpu_ring *ring; 3581 3582 if (!(adev->flags & AMD_IS_APU)) 3583 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3584 3585 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3586 /* legacy firmware loading */ 3587 r = gfx_v10_0_cp_gfx_load_microcode(adev); 3588 if (r) 3589 return r; 3590 3591 r = gfx_v10_0_cp_compute_load_microcode(adev); 3592 if (r) 3593 return r; 3594 } 3595 3596 r = gfx_v10_0_kiq_resume(adev); 3597 if (r) 3598 return r; 3599 3600 r = gfx_v10_0_kcq_resume(adev); 3601 if (r) 3602 return r; 3603 3604 if (!amdgpu_async_gfx_ring) { 3605 r = gfx_v10_0_cp_gfx_resume(adev); 3606 if (r) 3607 return r; 3608 } else { 3609 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 3610 if (r) 3611 return r; 3612 } 3613 3614 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3615 ring = &adev->gfx.gfx_ring[i]; 3616 DRM_INFO("gfx %d ring me %d pipe %d q %d\n", 3617 i, ring->me, ring->pipe, ring->queue); 3618 r = amdgpu_ring_test_ring(ring); 3619 if (r) { 3620 ring->sched.ready = false; 3621 return r; 3622 } 3623 } 3624 3625 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3626 ring = &adev->gfx.compute_ring[i]; 3627 ring->sched.ready = true; 3628 DRM_INFO("compute ring %d mec %d pipe %d q %d\n", 3629 i, ring->me, ring->pipe, ring->queue); 3630 r = amdgpu_ring_test_ring(ring); 3631 if (r) 3632 ring->sched.ready = false; 3633 } 3634 3635 return 0; 3636 } 3637 3638 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 3639 { 3640 gfx_v10_0_cp_gfx_enable(adev, enable); 3641 gfx_v10_0_cp_compute_enable(adev, enable); 3642 } 3643 3644 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 3645 { 3646 uint32_t data, pattern = 0xDEADBEEF; 3647 3648 /* check if mmVGT_ESGS_RING_SIZE_UMD 3649 * has been remapped to mmVGT_ESGS_RING_SIZE */ 3650 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 3651 3652 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 3653 3654 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 3655 3656 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 3657 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 3658 return true; 3659 } else { 3660 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 3661 return false; 3662 } 3663 } 3664 3665 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 3666 { 3667 uint32_t data; 3668 3669 /* initialize cam_index to 0 3670 * index will auto-inc after each data writting */ 3671 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 3672 3673 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 3674 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 3675 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3676 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 3677 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3678 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3679 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3680 3681 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 3682 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 3683 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3684 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 3685 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3686 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3687 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3688 3689 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 3690 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 3691 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3692 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 3693 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3694 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3695 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3696 3697 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 3698 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 3699 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3700 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 3701 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3702 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3703 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3704 3705 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 3706 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 3707 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3708 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 3709 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3710 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3711 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3712 3713 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 3714 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 3715 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3716 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 3717 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3718 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3719 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3720 3721 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 3722 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 3723 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3724 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 3725 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3726 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3727 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3728 } 3729 3730 static int gfx_v10_0_hw_init(void *handle) 3731 { 3732 int r; 3733 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3734 3735 r = gfx_v10_0_csb_vram_pin(adev); 3736 if (r) 3737 return r; 3738 3739 if (!amdgpu_emu_mode) 3740 gfx_v10_0_init_golden_registers(adev); 3741 3742 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3743 /** 3744 * For gfx 10, rlc firmware loading relies on smu firmware is 3745 * loaded firstly, so in direct type, it has to load smc ucode 3746 * here before rlc. 3747 */ 3748 r = smu_load_microcode(&adev->smu); 3749 if (r) 3750 return r; 3751 3752 r = smu_check_fw_status(&adev->smu); 3753 if (r) { 3754 pr_err("SMC firmware status is not correct\n"); 3755 return r; 3756 } 3757 } 3758 3759 /* if GRBM CAM not remapped, set up the remapping */ 3760 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 3761 gfx_v10_0_setup_grbm_cam_remapping(adev); 3762 3763 gfx_v10_0_constants_init(adev); 3764 3765 r = gfx_v10_0_rlc_resume(adev); 3766 if (r) 3767 return r; 3768 3769 /* 3770 * init golden registers and rlc resume may override some registers, 3771 * reconfig them here 3772 */ 3773 gfx_v10_0_tcp_harvest(adev); 3774 3775 r = gfx_v10_0_cp_resume(adev); 3776 if (r) 3777 return r; 3778 3779 return r; 3780 } 3781 3782 #ifndef BRING_UP_DEBUG 3783 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 3784 { 3785 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3786 struct amdgpu_ring *kiq_ring = &kiq->ring; 3787 int i; 3788 3789 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3790 return -EINVAL; 3791 3792 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 3793 adev->gfx.num_gfx_rings)) 3794 return -ENOMEM; 3795 3796 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3797 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 3798 PREEMPT_QUEUES, 0, 0); 3799 3800 return amdgpu_ring_test_ring(kiq_ring); 3801 } 3802 #endif 3803 3804 static int gfx_v10_0_hw_fini(void *handle) 3805 { 3806 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3807 int r; 3808 3809 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3810 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3811 #ifndef BRING_UP_DEBUG 3812 if (amdgpu_async_gfx_ring) { 3813 r = gfx_v10_0_kiq_disable_kgq(adev); 3814 if (r) 3815 DRM_ERROR("KGQ disable failed\n"); 3816 } 3817 #endif 3818 if (amdgpu_gfx_disable_kcq(adev)) 3819 DRM_ERROR("KCQ disable failed\n"); 3820 if (amdgpu_sriov_vf(adev)) { 3821 pr_debug("For SRIOV client, shouldn't do anything.\n"); 3822 return 0; 3823 } 3824 gfx_v10_0_cp_enable(adev, false); 3825 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3826 gfx_v10_0_csb_vram_unpin(adev); 3827 3828 return 0; 3829 } 3830 3831 static int gfx_v10_0_suspend(void *handle) 3832 { 3833 return gfx_v10_0_hw_fini(handle); 3834 } 3835 3836 static int gfx_v10_0_resume(void *handle) 3837 { 3838 return gfx_v10_0_hw_init(handle); 3839 } 3840 3841 static bool gfx_v10_0_is_idle(void *handle) 3842 { 3843 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3844 3845 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3846 GRBM_STATUS, GUI_ACTIVE)) 3847 return false; 3848 else 3849 return true; 3850 } 3851 3852 static int gfx_v10_0_wait_for_idle(void *handle) 3853 { 3854 unsigned i; 3855 u32 tmp; 3856 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3857 3858 for (i = 0; i < adev->usec_timeout; i++) { 3859 /* read MC_STATUS */ 3860 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 3861 GRBM_STATUS__GUI_ACTIVE_MASK; 3862 3863 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3864 return 0; 3865 udelay(1); 3866 } 3867 return -ETIMEDOUT; 3868 } 3869 3870 static int gfx_v10_0_soft_reset(void *handle) 3871 { 3872 u32 grbm_soft_reset = 0; 3873 u32 tmp; 3874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3875 3876 /* GRBM_STATUS */ 3877 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3878 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3879 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3880 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 3881 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 3882 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK 3883 | GRBM_STATUS__BCI_BUSY_MASK)) { 3884 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3885 GRBM_SOFT_RESET, SOFT_RESET_CP, 3886 1); 3887 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3888 GRBM_SOFT_RESET, SOFT_RESET_GFX, 3889 1); 3890 } 3891 3892 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3893 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3894 GRBM_SOFT_RESET, SOFT_RESET_CP, 3895 1); 3896 } 3897 3898 /* GRBM_STATUS2 */ 3899 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3900 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3901 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3902 GRBM_SOFT_RESET, SOFT_RESET_RLC, 3903 1); 3904 3905 if (grbm_soft_reset) { 3906 /* stop the rlc */ 3907 gfx_v10_0_rlc_stop(adev); 3908 3909 /* Disable GFX parsing/prefetching */ 3910 gfx_v10_0_cp_gfx_enable(adev, false); 3911 3912 /* Disable MEC parsing/prefetching */ 3913 gfx_v10_0_cp_compute_enable(adev, false); 3914 3915 if (grbm_soft_reset) { 3916 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3917 tmp |= grbm_soft_reset; 3918 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3919 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3920 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3921 3922 udelay(50); 3923 3924 tmp &= ~grbm_soft_reset; 3925 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3926 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3927 } 3928 3929 /* Wait a little for things to settle down */ 3930 udelay(50); 3931 } 3932 return 0; 3933 } 3934 3935 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3936 { 3937 uint64_t clock; 3938 3939 mutex_lock(&adev->gfx.gpu_clock_mutex); 3940 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3941 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3942 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3943 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3944 return clock; 3945 } 3946 3947 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3948 uint32_t vmid, 3949 uint32_t gds_base, uint32_t gds_size, 3950 uint32_t gws_base, uint32_t gws_size, 3951 uint32_t oa_base, uint32_t oa_size) 3952 { 3953 struct amdgpu_device *adev = ring->adev; 3954 3955 /* GDS Base */ 3956 gfx_v10_0_write_data_to_reg(ring, 0, false, 3957 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 3958 gds_base); 3959 3960 /* GDS Size */ 3961 gfx_v10_0_write_data_to_reg(ring, 0, false, 3962 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 3963 gds_size); 3964 3965 /* GWS */ 3966 gfx_v10_0_write_data_to_reg(ring, 0, false, 3967 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 3968 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3969 3970 /* OA */ 3971 gfx_v10_0_write_data_to_reg(ring, 0, false, 3972 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 3973 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3974 } 3975 3976 static int gfx_v10_0_early_init(void *handle) 3977 { 3978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3979 3980 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS; 3981 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 3982 3983 gfx_v10_0_set_kiq_pm4_funcs(adev); 3984 gfx_v10_0_set_ring_funcs(adev); 3985 gfx_v10_0_set_irq_funcs(adev); 3986 gfx_v10_0_set_gds_init(adev); 3987 gfx_v10_0_set_rlc_funcs(adev); 3988 3989 return 0; 3990 } 3991 3992 static int gfx_v10_0_late_init(void *handle) 3993 { 3994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3995 int r; 3996 3997 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3998 if (r) 3999 return r; 4000 4001 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4002 if (r) 4003 return r; 4004 4005 return 0; 4006 } 4007 4008 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 4009 { 4010 uint32_t rlc_cntl; 4011 4012 /* if RLC is not enabled, do nothing */ 4013 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4014 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4015 } 4016 4017 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 4018 { 4019 uint32_t data; 4020 unsigned i; 4021 4022 data = RLC_SAFE_MODE__CMD_MASK; 4023 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4024 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4025 4026 /* wait for RLC_SAFE_MODE */ 4027 for (i = 0; i < adev->usec_timeout; i++) { 4028 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4029 break; 4030 udelay(1); 4031 } 4032 } 4033 4034 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 4035 { 4036 uint32_t data; 4037 4038 data = RLC_SAFE_MODE__CMD_MASK; 4039 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4040 } 4041 4042 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4043 bool enable) 4044 { 4045 uint32_t data, def; 4046 4047 /* It is disabled by HW by default */ 4048 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4049 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4050 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4051 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4052 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4053 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4054 4055 /* only for Vega10 & Raven1 */ 4056 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4057 4058 if (def != data) 4059 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4060 4061 /* MGLS is a global flag to control all MGLS in GFX */ 4062 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4063 /* 2 - RLC memory Light sleep */ 4064 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4065 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4066 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4067 if (def != data) 4068 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4069 } 4070 /* 3 - CP memory Light sleep */ 4071 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4072 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4073 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4074 if (def != data) 4075 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4076 } 4077 } 4078 } else { 4079 /* 1 - MGCG_OVERRIDE */ 4080 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4081 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4082 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4083 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4084 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4085 if (def != data) 4086 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4087 4088 /* 2 - disable MGLS in RLC */ 4089 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4090 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4091 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4092 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4093 } 4094 4095 /* 3 - disable MGLS in CP */ 4096 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4097 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4098 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4099 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4100 } 4101 } 4102 } 4103 4104 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 4105 bool enable) 4106 { 4107 uint32_t data, def; 4108 4109 /* Enable 3D CGCG/CGLS */ 4110 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 4111 /* write cmd to clear cgcg/cgls ov */ 4112 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4113 /* unset CGCG override */ 4114 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4115 /* update CGCG and CGLS override bits */ 4116 if (def != data) 4117 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4118 /* enable 3Dcgcg FSM(0x0000363f) */ 4119 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4120 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4121 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4122 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4123 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4124 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4125 if (def != data) 4126 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4127 4128 /* set IDLE_POLL_COUNT(0x00900100) */ 4129 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4130 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4131 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4132 if (def != data) 4133 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4134 } else { 4135 /* Disable CGCG/CGLS */ 4136 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4137 /* disable cgcg, cgls should be disabled */ 4138 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4139 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4140 /* disable cgcg and cgls in FSM */ 4141 if (def != data) 4142 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4143 } 4144 } 4145 4146 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4147 bool enable) 4148 { 4149 uint32_t def, data; 4150 4151 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4152 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4153 /* unset CGCG override */ 4154 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4155 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4156 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4157 else 4158 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4159 /* update CGCG and CGLS override bits */ 4160 if (def != data) 4161 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4162 4163 /* enable cgcg FSM(0x0000363F) */ 4164 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4165 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4166 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4167 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4168 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4169 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4170 if (def != data) 4171 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4172 4173 /* set IDLE_POLL_COUNT(0x00900100) */ 4174 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4175 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4176 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4177 if (def != data) 4178 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4179 } else { 4180 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4181 /* reset CGCG/CGLS bits */ 4182 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4183 /* disable cgcg and cgls in FSM */ 4184 if (def != data) 4185 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4186 } 4187 } 4188 4189 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4190 bool enable) 4191 { 4192 amdgpu_gfx_rlc_enter_safe_mode(adev); 4193 4194 if (enable) { 4195 /* CGCG/CGLS should be enabled after MGCG/MGLS 4196 * === MGCG + MGLS === 4197 */ 4198 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4199 /* === CGCG /CGLS for GFX 3D Only === */ 4200 gfx_v10_0_update_3d_clock_gating(adev, enable); 4201 /* === CGCG + CGLS === */ 4202 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4203 } else { 4204 /* CGCG/CGLS should be disabled before MGCG/MGLS 4205 * === CGCG + CGLS === 4206 */ 4207 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4208 /* === CGCG /CGLS for GFX 3D Only === */ 4209 gfx_v10_0_update_3d_clock_gating(adev, enable); 4210 /* === MGCG + MGLS === */ 4211 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4212 } 4213 4214 if (adev->cg_flags & 4215 (AMD_CG_SUPPORT_GFX_MGCG | 4216 AMD_CG_SUPPORT_GFX_CGLS | 4217 AMD_CG_SUPPORT_GFX_CGCG | 4218 AMD_CG_SUPPORT_GFX_CGLS | 4219 AMD_CG_SUPPORT_GFX_3D_CGCG | 4220 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4221 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 4222 4223 amdgpu_gfx_rlc_exit_safe_mode(adev); 4224 4225 return 0; 4226 } 4227 4228 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 4229 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 4230 .set_safe_mode = gfx_v10_0_set_safe_mode, 4231 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 4232 .init = gfx_v10_0_rlc_init, 4233 .get_csb_size = gfx_v10_0_get_csb_size, 4234 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 4235 .resume = gfx_v10_0_rlc_resume, 4236 .stop = gfx_v10_0_rlc_stop, 4237 .reset = gfx_v10_0_rlc_reset, 4238 .start = gfx_v10_0_rlc_start 4239 }; 4240 4241 static int gfx_v10_0_set_powergating_state(void *handle, 4242 enum amd_powergating_state state) 4243 { 4244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4245 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 4246 switch (adev->asic_type) { 4247 case CHIP_NAVI10: 4248 case CHIP_NAVI14: 4249 if (!enable) { 4250 amdgpu_gfx_off_ctrl(adev, false); 4251 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 4252 } else 4253 amdgpu_gfx_off_ctrl(adev, true); 4254 break; 4255 default: 4256 break; 4257 } 4258 return 0; 4259 } 4260 4261 static int gfx_v10_0_set_clockgating_state(void *handle, 4262 enum amd_clockgating_state state) 4263 { 4264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4265 4266 switch (adev->asic_type) { 4267 case CHIP_NAVI10: 4268 case CHIP_NAVI14: 4269 case CHIP_NAVI12: 4270 gfx_v10_0_update_gfx_clock_gating(adev, 4271 state == AMD_CG_STATE_GATE ? true : false); 4272 break; 4273 default: 4274 break; 4275 } 4276 return 0; 4277 } 4278 4279 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 4280 { 4281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4282 int data; 4283 4284 /* AMD_CG_SUPPORT_GFX_MGCG */ 4285 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4286 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4287 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4288 4289 /* AMD_CG_SUPPORT_GFX_CGCG */ 4290 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4291 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4292 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4293 4294 /* AMD_CG_SUPPORT_GFX_CGLS */ 4295 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4296 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4297 4298 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 4299 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4300 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 4301 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 4302 4303 /* AMD_CG_SUPPORT_GFX_CP_LS */ 4304 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4305 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 4306 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 4307 4308 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4309 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4310 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4311 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4312 4313 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4314 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4315 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4316 } 4317 4318 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4319 { 4320 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 4321 } 4322 4323 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4324 { 4325 struct amdgpu_device *adev = ring->adev; 4326 u64 wptr; 4327 4328 /* XXX check if swapping is necessary on BE */ 4329 if (ring->use_doorbell) { 4330 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 4331 } else { 4332 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 4333 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 4334 } 4335 4336 return wptr; 4337 } 4338 4339 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4340 { 4341 struct amdgpu_device *adev = ring->adev; 4342 4343 if (ring->use_doorbell) { 4344 /* XXX check if swapping is necessary on BE */ 4345 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4346 WDOORBELL64(ring->doorbell_index, ring->wptr); 4347 } else { 4348 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4349 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 4350 } 4351 } 4352 4353 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4354 { 4355 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 4356 } 4357 4358 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4359 { 4360 u64 wptr; 4361 4362 /* XXX check if swapping is necessary on BE */ 4363 if (ring->use_doorbell) 4364 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 4365 else 4366 BUG(); 4367 return wptr; 4368 } 4369 4370 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4371 { 4372 struct amdgpu_device *adev = ring->adev; 4373 4374 /* XXX check if swapping is necessary on BE */ 4375 if (ring->use_doorbell) { 4376 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4377 WDOORBELL64(ring->doorbell_index, ring->wptr); 4378 } else { 4379 BUG(); /* only DOORBELL method supported on gfx10 now */ 4380 } 4381 } 4382 4383 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4384 { 4385 struct amdgpu_device *adev = ring->adev; 4386 u32 ref_and_mask, reg_mem_engine; 4387 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 4388 4389 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4390 switch (ring->me) { 4391 case 1: 4392 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4393 break; 4394 case 2: 4395 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4396 break; 4397 default: 4398 return; 4399 } 4400 reg_mem_engine = 0; 4401 } else { 4402 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4403 reg_mem_engine = 1; /* pfp */ 4404 } 4405 4406 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4407 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 4408 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 4409 ref_and_mask, ref_and_mask, 0x20); 4410 } 4411 4412 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4413 struct amdgpu_job *job, 4414 struct amdgpu_ib *ib, 4415 uint32_t flags) 4416 { 4417 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4418 u32 header, control = 0; 4419 4420 if (ib->flags & AMDGPU_IB_FLAG_CE) 4421 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 4422 else 4423 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4424 4425 control |= ib->length_dw | (vmid << 24); 4426 4427 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 4428 control |= INDIRECT_BUFFER_PRE_ENB(1); 4429 4430 if (flags & AMDGPU_IB_PREEMPTED) 4431 control |= INDIRECT_BUFFER_PRE_RESUME(1); 4432 4433 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 4434 gfx_v10_0_ring_emit_de_meta(ring, 4435 flags & AMDGPU_IB_PREEMPTED ? true : false); 4436 } 4437 4438 amdgpu_ring_write(ring, header); 4439 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4440 amdgpu_ring_write(ring, 4441 #ifdef __BIG_ENDIAN 4442 (2 << 0) | 4443 #endif 4444 lower_32_bits(ib->gpu_addr)); 4445 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4446 amdgpu_ring_write(ring, control); 4447 } 4448 4449 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4450 struct amdgpu_job *job, 4451 struct amdgpu_ib *ib, 4452 uint32_t flags) 4453 { 4454 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4455 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4456 4457 /* Currently, there is a high possibility to get wave ID mismatch 4458 * between ME and GDS, leading to a hw deadlock, because ME generates 4459 * different wave IDs than the GDS expects. This situation happens 4460 * randomly when at least 5 compute pipes use GDS ordered append. 4461 * The wave IDs generated by ME are also wrong after suspend/resume. 4462 * Those are probably bugs somewhere else in the kernel driver. 4463 * 4464 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 4465 * GDS to 0 for this ring (me/pipe). 4466 */ 4467 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 4468 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4469 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 4470 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 4471 } 4472 4473 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4474 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4475 amdgpu_ring_write(ring, 4476 #ifdef __BIG_ENDIAN 4477 (2 << 0) | 4478 #endif 4479 lower_32_bits(ib->gpu_addr)); 4480 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4481 amdgpu_ring_write(ring, control); 4482 } 4483 4484 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4485 u64 seq, unsigned flags) 4486 { 4487 struct amdgpu_device *adev = ring->adev; 4488 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4489 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4490 4491 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 4492 if (adev->pdev->device == 0x50) 4493 int_sel = false; 4494 4495 /* RELEASE_MEM - flush caches, send int */ 4496 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4497 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4498 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4499 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 4500 PACKET3_RELEASE_MEM_GCR_GLM_WB | 4501 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4502 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4503 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4504 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4505 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4506 4507 /* 4508 * the address should be Qword aligned if 64bit write, Dword 4509 * aligned if only send 32bit data low (discard data high) 4510 */ 4511 if (write64bit) 4512 BUG_ON(addr & 0x7); 4513 else 4514 BUG_ON(addr & 0x3); 4515 amdgpu_ring_write(ring, lower_32_bits(addr)); 4516 amdgpu_ring_write(ring, upper_32_bits(addr)); 4517 amdgpu_ring_write(ring, lower_32_bits(seq)); 4518 amdgpu_ring_write(ring, upper_32_bits(seq)); 4519 amdgpu_ring_write(ring, 0); 4520 } 4521 4522 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4523 { 4524 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4525 uint32_t seq = ring->fence_drv.sync_seq; 4526 uint64_t addr = ring->fence_drv.gpu_addr; 4527 4528 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4529 upper_32_bits(addr), seq, 0xffffffff, 4); 4530 } 4531 4532 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4533 unsigned vmid, uint64_t pd_addr) 4534 { 4535 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4536 4537 /* compute doesn't have PFP */ 4538 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4539 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4540 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4541 amdgpu_ring_write(ring, 0x0); 4542 } 4543 } 4544 4545 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4546 u64 seq, unsigned int flags) 4547 { 4548 struct amdgpu_device *adev = ring->adev; 4549 4550 /* we only allocate 32bit for each seq wb address */ 4551 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4552 4553 /* write fence seq to the "addr" */ 4554 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4555 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4556 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4557 amdgpu_ring_write(ring, lower_32_bits(addr)); 4558 amdgpu_ring_write(ring, upper_32_bits(addr)); 4559 amdgpu_ring_write(ring, lower_32_bits(seq)); 4560 4561 if (flags & AMDGPU_FENCE_FLAG_INT) { 4562 /* set register to trigger INT */ 4563 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4564 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4565 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4566 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 4567 amdgpu_ring_write(ring, 0); 4568 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4569 } 4570 } 4571 4572 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 4573 { 4574 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4575 amdgpu_ring_write(ring, 0); 4576 } 4577 4578 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 4579 { 4580 uint32_t dw2 = 0; 4581 4582 if (amdgpu_mcbp) 4583 gfx_v10_0_ring_emit_ce_meta(ring, 4584 flags & AMDGPU_IB_PREEMPTED ? true : false); 4585 4586 gfx_v10_0_ring_emit_tmz(ring, true); 4587 4588 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4589 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4590 /* set load_global_config & load_global_uconfig */ 4591 dw2 |= 0x8001; 4592 /* set load_cs_sh_regs */ 4593 dw2 |= 0x01000000; 4594 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4595 dw2 |= 0x10002; 4596 4597 /* set load_ce_ram if preamble presented */ 4598 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 4599 dw2 |= 0x10000000; 4600 } else { 4601 /* still load_ce_ram if this is the first time preamble presented 4602 * although there is no context switch happens. 4603 */ 4604 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 4605 dw2 |= 0x10000000; 4606 } 4607 4608 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4609 amdgpu_ring_write(ring, dw2); 4610 amdgpu_ring_write(ring, 0); 4611 } 4612 4613 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 4614 { 4615 unsigned ret; 4616 4617 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4618 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 4619 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 4620 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 4621 ret = ring->wptr & ring->buf_mask; 4622 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 4623 4624 return ret; 4625 } 4626 4627 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 4628 { 4629 unsigned cur; 4630 BUG_ON(offset > ring->buf_mask); 4631 BUG_ON(ring->ring[offset] != 0x55aa55aa); 4632 4633 cur = (ring->wptr - 1) & ring->buf_mask; 4634 if (likely(cur > offset)) 4635 ring->ring[offset] = cur - offset; 4636 else 4637 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 4638 } 4639 4640 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 4641 { 4642 int i, r = 0; 4643 struct amdgpu_device *adev = ring->adev; 4644 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4645 struct amdgpu_ring *kiq_ring = &kiq->ring; 4646 4647 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4648 return -EINVAL; 4649 4650 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) 4651 return -ENOMEM; 4652 4653 /* assert preemption condition */ 4654 amdgpu_ring_set_preempt_cond_exec(ring, false); 4655 4656 /* assert IB preemption, emit the trailing fence */ 4657 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4658 ring->trail_fence_gpu_addr, 4659 ++ring->trail_seq); 4660 amdgpu_ring_commit(kiq_ring); 4661 4662 /* poll the trailing fence */ 4663 for (i = 0; i < adev->usec_timeout; i++) { 4664 if (ring->trail_seq == 4665 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4666 break; 4667 udelay(1); 4668 } 4669 4670 if (i >= adev->usec_timeout) { 4671 r = -EINVAL; 4672 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4673 } 4674 4675 /* deassert preemption condition */ 4676 amdgpu_ring_set_preempt_cond_exec(ring, true); 4677 return r; 4678 } 4679 4680 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 4681 { 4682 struct amdgpu_device *adev = ring->adev; 4683 struct v10_ce_ib_state ce_payload = {0}; 4684 uint64_t csa_addr; 4685 int cnt; 4686 4687 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 4688 csa_addr = amdgpu_csa_vaddr(ring->adev); 4689 4690 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4691 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 4692 WRITE_DATA_DST_SEL(8) | 4693 WR_CONFIRM) | 4694 WRITE_DATA_CACHE_POLICY(0)); 4695 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4696 offsetof(struct v10_gfx_meta_data, ce_payload))); 4697 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4698 offsetof(struct v10_gfx_meta_data, ce_payload))); 4699 4700 if (resume) 4701 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4702 offsetof(struct v10_gfx_meta_data, 4703 ce_payload), 4704 sizeof(ce_payload) >> 2); 4705 else 4706 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 4707 sizeof(ce_payload) >> 2); 4708 } 4709 4710 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 4711 { 4712 struct amdgpu_device *adev = ring->adev; 4713 struct v10_de_ib_state de_payload = {0}; 4714 uint64_t csa_addr, gds_addr; 4715 int cnt; 4716 4717 csa_addr = amdgpu_csa_vaddr(ring->adev); 4718 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 4719 PAGE_SIZE); 4720 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 4721 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 4722 4723 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 4724 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4725 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 4726 WRITE_DATA_DST_SEL(8) | 4727 WR_CONFIRM) | 4728 WRITE_DATA_CACHE_POLICY(0)); 4729 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4730 offsetof(struct v10_gfx_meta_data, de_payload))); 4731 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4732 offsetof(struct v10_gfx_meta_data, de_payload))); 4733 4734 if (resume) 4735 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4736 offsetof(struct v10_gfx_meta_data, 4737 de_payload), 4738 sizeof(de_payload) >> 2); 4739 else 4740 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 4741 sizeof(de_payload) >> 2); 4742 } 4743 4744 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 4745 { 4746 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4747 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 4748 } 4749 4750 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 4751 { 4752 struct amdgpu_device *adev = ring->adev; 4753 4754 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4755 amdgpu_ring_write(ring, 0 | /* src: register*/ 4756 (5 << 8) | /* dst: memory */ 4757 (1 << 20)); /* write confirm */ 4758 amdgpu_ring_write(ring, reg); 4759 amdgpu_ring_write(ring, 0); 4760 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4761 adev->virt.reg_val_offs * 4)); 4762 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4763 adev->virt.reg_val_offs * 4)); 4764 } 4765 4766 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 4767 uint32_t val) 4768 { 4769 uint32_t cmd = 0; 4770 4771 switch (ring->funcs->type) { 4772 case AMDGPU_RING_TYPE_GFX: 4773 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4774 break; 4775 case AMDGPU_RING_TYPE_KIQ: 4776 cmd = (1 << 16); /* no inc addr */ 4777 break; 4778 default: 4779 cmd = WR_CONFIRM; 4780 break; 4781 } 4782 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4783 amdgpu_ring_write(ring, cmd); 4784 amdgpu_ring_write(ring, reg); 4785 amdgpu_ring_write(ring, 0); 4786 amdgpu_ring_write(ring, val); 4787 } 4788 4789 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4790 uint32_t val, uint32_t mask) 4791 { 4792 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4793 } 4794 4795 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4796 uint32_t reg0, uint32_t reg1, 4797 uint32_t ref, uint32_t mask) 4798 { 4799 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4800 struct amdgpu_device *adev = ring->adev; 4801 bool fw_version_ok = false; 4802 4803 fw_version_ok = adev->gfx.cp_fw_write_wait; 4804 4805 if (fw_version_ok) 4806 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4807 ref, mask, 0x20); 4808 else 4809 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 4810 ref, mask); 4811 } 4812 4813 static void 4814 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4815 uint32_t me, uint32_t pipe, 4816 enum amdgpu_interrupt_state state) 4817 { 4818 uint32_t cp_int_cntl, cp_int_cntl_reg; 4819 4820 if (!me) { 4821 switch (pipe) { 4822 case 0: 4823 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 4824 break; 4825 case 1: 4826 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 4827 break; 4828 default: 4829 DRM_DEBUG("invalid pipe %d\n", pipe); 4830 return; 4831 } 4832 } else { 4833 DRM_DEBUG("invalid me %d\n", me); 4834 return; 4835 } 4836 4837 switch (state) { 4838 case AMDGPU_IRQ_STATE_DISABLE: 4839 cp_int_cntl = RREG32(cp_int_cntl_reg); 4840 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4841 TIME_STAMP_INT_ENABLE, 0); 4842 WREG32(cp_int_cntl_reg, cp_int_cntl); 4843 break; 4844 case AMDGPU_IRQ_STATE_ENABLE: 4845 cp_int_cntl = RREG32(cp_int_cntl_reg); 4846 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4847 TIME_STAMP_INT_ENABLE, 1); 4848 WREG32(cp_int_cntl_reg, cp_int_cntl); 4849 break; 4850 default: 4851 break; 4852 } 4853 } 4854 4855 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4856 int me, int pipe, 4857 enum amdgpu_interrupt_state state) 4858 { 4859 u32 mec_int_cntl, mec_int_cntl_reg; 4860 4861 /* 4862 * amdgpu controls only the first MEC. That's why this function only 4863 * handles the setting of interrupts for this specific MEC. All other 4864 * pipes' interrupts are set by amdkfd. 4865 */ 4866 4867 if (me == 1) { 4868 switch (pipe) { 4869 case 0: 4870 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4871 break; 4872 case 1: 4873 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 4874 break; 4875 case 2: 4876 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 4877 break; 4878 case 3: 4879 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 4880 break; 4881 default: 4882 DRM_DEBUG("invalid pipe %d\n", pipe); 4883 return; 4884 } 4885 } else { 4886 DRM_DEBUG("invalid me %d\n", me); 4887 return; 4888 } 4889 4890 switch (state) { 4891 case AMDGPU_IRQ_STATE_DISABLE: 4892 mec_int_cntl = RREG32(mec_int_cntl_reg); 4893 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4894 TIME_STAMP_INT_ENABLE, 0); 4895 WREG32(mec_int_cntl_reg, mec_int_cntl); 4896 break; 4897 case AMDGPU_IRQ_STATE_ENABLE: 4898 mec_int_cntl = RREG32(mec_int_cntl_reg); 4899 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4900 TIME_STAMP_INT_ENABLE, 1); 4901 WREG32(mec_int_cntl_reg, mec_int_cntl); 4902 break; 4903 default: 4904 break; 4905 } 4906 } 4907 4908 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4909 struct amdgpu_irq_src *src, 4910 unsigned type, 4911 enum amdgpu_interrupt_state state) 4912 { 4913 switch (type) { 4914 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4915 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4916 break; 4917 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4918 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4919 break; 4920 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4921 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4922 break; 4923 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4924 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4925 break; 4926 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4927 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4928 break; 4929 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4930 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4931 break; 4932 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4933 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4934 break; 4935 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4936 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4937 break; 4938 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4939 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4940 break; 4941 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4942 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4943 break; 4944 default: 4945 break; 4946 } 4947 return 0; 4948 } 4949 4950 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 4951 struct amdgpu_irq_src *source, 4952 struct amdgpu_iv_entry *entry) 4953 { 4954 int i; 4955 u8 me_id, pipe_id, queue_id; 4956 struct amdgpu_ring *ring; 4957 4958 DRM_DEBUG("IH: CP EOP\n"); 4959 me_id = (entry->ring_id & 0x0c) >> 2; 4960 pipe_id = (entry->ring_id & 0x03) >> 0; 4961 queue_id = (entry->ring_id & 0x70) >> 4; 4962 4963 switch (me_id) { 4964 case 0: 4965 if (pipe_id == 0) 4966 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4967 else 4968 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4969 break; 4970 case 1: 4971 case 2: 4972 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4973 ring = &adev->gfx.compute_ring[i]; 4974 /* Per-queue interrupt is supported for MEC starting from VI. 4975 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4976 */ 4977 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4978 amdgpu_fence_process(ring); 4979 } 4980 break; 4981 } 4982 return 0; 4983 } 4984 4985 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4986 struct amdgpu_irq_src *source, 4987 unsigned type, 4988 enum amdgpu_interrupt_state state) 4989 { 4990 switch (state) { 4991 case AMDGPU_IRQ_STATE_DISABLE: 4992 case AMDGPU_IRQ_STATE_ENABLE: 4993 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4994 PRIV_REG_INT_ENABLE, 4995 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4996 break; 4997 default: 4998 break; 4999 } 5000 5001 return 0; 5002 } 5003 5004 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5005 struct amdgpu_irq_src *source, 5006 unsigned type, 5007 enum amdgpu_interrupt_state state) 5008 { 5009 switch (state) { 5010 case AMDGPU_IRQ_STATE_DISABLE: 5011 case AMDGPU_IRQ_STATE_ENABLE: 5012 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5013 PRIV_INSTR_INT_ENABLE, 5014 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5015 default: 5016 break; 5017 } 5018 5019 return 0; 5020 } 5021 5022 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 5023 struct amdgpu_iv_entry *entry) 5024 { 5025 u8 me_id, pipe_id, queue_id; 5026 struct amdgpu_ring *ring; 5027 int i; 5028 5029 me_id = (entry->ring_id & 0x0c) >> 2; 5030 pipe_id = (entry->ring_id & 0x03) >> 0; 5031 queue_id = (entry->ring_id & 0x70) >> 4; 5032 5033 switch (me_id) { 5034 case 0: 5035 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5036 ring = &adev->gfx.gfx_ring[i]; 5037 /* we only enabled 1 gfx queue per pipe for now */ 5038 if (ring->me == me_id && ring->pipe == pipe_id) 5039 drm_sched_fault(&ring->sched); 5040 } 5041 break; 5042 case 1: 5043 case 2: 5044 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5045 ring = &adev->gfx.compute_ring[i]; 5046 if (ring->me == me_id && ring->pipe == pipe_id && 5047 ring->queue == queue_id) 5048 drm_sched_fault(&ring->sched); 5049 } 5050 break; 5051 default: 5052 BUG(); 5053 } 5054 } 5055 5056 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 5057 struct amdgpu_irq_src *source, 5058 struct amdgpu_iv_entry *entry) 5059 { 5060 DRM_ERROR("Illegal register access in command stream\n"); 5061 gfx_v10_0_handle_priv_fault(adev, entry); 5062 return 0; 5063 } 5064 5065 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 5066 struct amdgpu_irq_src *source, 5067 struct amdgpu_iv_entry *entry) 5068 { 5069 DRM_ERROR("Illegal instruction in command stream\n"); 5070 gfx_v10_0_handle_priv_fault(adev, entry); 5071 return 0; 5072 } 5073 5074 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 5075 struct amdgpu_irq_src *src, 5076 unsigned int type, 5077 enum amdgpu_interrupt_state state) 5078 { 5079 uint32_t tmp, target; 5080 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5081 5082 if (ring->me == 1) 5083 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5084 else 5085 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 5086 target += ring->pipe; 5087 5088 switch (type) { 5089 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 5090 if (state == AMDGPU_IRQ_STATE_DISABLE) { 5091 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5092 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5093 GENERIC2_INT_ENABLE, 0); 5094 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5095 5096 tmp = RREG32(target); 5097 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 5098 GENERIC2_INT_ENABLE, 0); 5099 WREG32(target, tmp); 5100 } else { 5101 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5102 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5103 GENERIC2_INT_ENABLE, 1); 5104 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5105 5106 tmp = RREG32(target); 5107 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 5108 GENERIC2_INT_ENABLE, 1); 5109 WREG32(target, tmp); 5110 } 5111 break; 5112 default: 5113 BUG(); /* kiq only support GENERIC2_INT now */ 5114 break; 5115 } 5116 return 0; 5117 } 5118 5119 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 5120 struct amdgpu_irq_src *source, 5121 struct amdgpu_iv_entry *entry) 5122 { 5123 u8 me_id, pipe_id, queue_id; 5124 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5125 5126 me_id = (entry->ring_id & 0x0c) >> 2; 5127 pipe_id = (entry->ring_id & 0x03) >> 0; 5128 queue_id = (entry->ring_id & 0x70) >> 4; 5129 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 5130 me_id, pipe_id, queue_id); 5131 5132 amdgpu_fence_process(ring); 5133 return 0; 5134 } 5135 5136 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 5137 .name = "gfx_v10_0", 5138 .early_init = gfx_v10_0_early_init, 5139 .late_init = gfx_v10_0_late_init, 5140 .sw_init = gfx_v10_0_sw_init, 5141 .sw_fini = gfx_v10_0_sw_fini, 5142 .hw_init = gfx_v10_0_hw_init, 5143 .hw_fini = gfx_v10_0_hw_fini, 5144 .suspend = gfx_v10_0_suspend, 5145 .resume = gfx_v10_0_resume, 5146 .is_idle = gfx_v10_0_is_idle, 5147 .wait_for_idle = gfx_v10_0_wait_for_idle, 5148 .soft_reset = gfx_v10_0_soft_reset, 5149 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 5150 .set_powergating_state = gfx_v10_0_set_powergating_state, 5151 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 5152 }; 5153 5154 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 5155 .type = AMDGPU_RING_TYPE_GFX, 5156 .align_mask = 0xff, 5157 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5158 .support_64bit_ptrs = true, 5159 .vmhub = AMDGPU_GFXHUB_0, 5160 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 5161 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 5162 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 5163 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5164 5 + /* COND_EXEC */ 5165 7 + /* PIPELINE_SYNC */ 5166 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5167 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5168 2 + /* VM_FLUSH */ 5169 8 + /* FENCE for VM_FLUSH */ 5170 20 + /* GDS switch */ 5171 4 + /* double SWITCH_BUFFER, 5172 * the first COND_EXEC jump to the place 5173 * just prior to this double SWITCH_BUFFER 5174 */ 5175 5 + /* COND_EXEC */ 5176 7 + /* HDP_flush */ 5177 4 + /* VGT_flush */ 5178 14 + /* CE_META */ 5179 31 + /* DE_META */ 5180 3 + /* CNTX_CTRL */ 5181 5 + /* HDP_INVL */ 5182 8 + 8 + /* FENCE x2 */ 5183 2, /* SWITCH_BUFFER */ 5184 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 5185 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 5186 .emit_fence = gfx_v10_0_ring_emit_fence, 5187 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5188 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5189 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5190 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5191 .test_ring = gfx_v10_0_ring_test_ring, 5192 .test_ib = gfx_v10_0_ring_test_ib, 5193 .insert_nop = amdgpu_ring_insert_nop, 5194 .pad_ib = amdgpu_ring_generic_pad_ib, 5195 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 5196 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 5197 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 5198 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 5199 .preempt_ib = gfx_v10_0_ring_preempt_ib, 5200 .emit_tmz = gfx_v10_0_ring_emit_tmz, 5201 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5202 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5203 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5204 }; 5205 5206 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 5207 .type = AMDGPU_RING_TYPE_COMPUTE, 5208 .align_mask = 0xff, 5209 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5210 .support_64bit_ptrs = true, 5211 .vmhub = AMDGPU_GFXHUB_0, 5212 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5213 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5214 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5215 .emit_frame_size = 5216 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5217 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5218 5 + /* hdp invalidate */ 5219 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5220 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5221 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5222 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5223 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 5224 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5225 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5226 .emit_fence = gfx_v10_0_ring_emit_fence, 5227 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5228 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5229 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5230 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5231 .test_ring = gfx_v10_0_ring_test_ring, 5232 .test_ib = gfx_v10_0_ring_test_ib, 5233 .insert_nop = amdgpu_ring_insert_nop, 5234 .pad_ib = amdgpu_ring_generic_pad_ib, 5235 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5236 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5237 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5238 }; 5239 5240 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 5241 .type = AMDGPU_RING_TYPE_KIQ, 5242 .align_mask = 0xff, 5243 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5244 .support_64bit_ptrs = true, 5245 .vmhub = AMDGPU_GFXHUB_0, 5246 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5247 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5248 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5249 .emit_frame_size = 5250 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5251 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5252 5 + /*hdp invalidate */ 5253 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5254 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5255 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5256 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5257 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5258 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5259 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5260 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 5261 .test_ring = gfx_v10_0_ring_test_ring, 5262 .test_ib = gfx_v10_0_ring_test_ib, 5263 .insert_nop = amdgpu_ring_insert_nop, 5264 .pad_ib = amdgpu_ring_generic_pad_ib, 5265 .emit_rreg = gfx_v10_0_ring_emit_rreg, 5266 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5267 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5268 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5269 }; 5270 5271 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 5272 { 5273 int i; 5274 5275 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 5276 5277 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5278 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 5279 5280 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5281 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 5282 } 5283 5284 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 5285 .set = gfx_v10_0_set_eop_interrupt_state, 5286 .process = gfx_v10_0_eop_irq, 5287 }; 5288 5289 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 5290 .set = gfx_v10_0_set_priv_reg_fault_state, 5291 .process = gfx_v10_0_priv_reg_irq, 5292 }; 5293 5294 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 5295 .set = gfx_v10_0_set_priv_inst_fault_state, 5296 .process = gfx_v10_0_priv_inst_irq, 5297 }; 5298 5299 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 5300 .set = gfx_v10_0_kiq_set_interrupt_state, 5301 .process = gfx_v10_0_kiq_irq, 5302 }; 5303 5304 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 5305 { 5306 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5307 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 5308 5309 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 5310 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 5311 5312 adev->gfx.priv_reg_irq.num_types = 1; 5313 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 5314 5315 adev->gfx.priv_inst_irq.num_types = 1; 5316 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 5317 } 5318 5319 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 5320 { 5321 switch (adev->asic_type) { 5322 case CHIP_NAVI10: 5323 case CHIP_NAVI14: 5324 case CHIP_NAVI12: 5325 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 5326 break; 5327 default: 5328 break; 5329 } 5330 } 5331 5332 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 5333 { 5334 /* init asic gds info */ 5335 switch (adev->asic_type) { 5336 case CHIP_NAVI10: 5337 default: 5338 adev->gds.gds_size = 0x10000; 5339 adev->gds.gds_compute_max_wave_id = 0x4ff; 5340 break; 5341 } 5342 5343 adev->gds.gws_size = 64; 5344 adev->gds.oa_size = 16; 5345 } 5346 5347 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5348 u32 bitmap) 5349 { 5350 u32 data; 5351 5352 if (!bitmap) 5353 return; 5354 5355 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5356 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5357 5358 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 5359 } 5360 5361 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5362 { 5363 u32 data, wgp_bitmask; 5364 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 5365 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 5366 5367 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5368 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5369 5370 wgp_bitmask = 5371 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5372 5373 return (~data) & wgp_bitmask; 5374 } 5375 5376 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5377 { 5378 u32 wgp_idx, wgp_active_bitmap; 5379 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5380 5381 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5382 cu_active_bitmap = 0; 5383 5384 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5385 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5386 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5387 if (wgp_active_bitmap & (1 << wgp_idx)) 5388 cu_active_bitmap |= cu_bitmap_per_wgp; 5389 } 5390 5391 return cu_active_bitmap; 5392 } 5393 5394 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 5395 struct amdgpu_cu_info *cu_info) 5396 { 5397 int i, j, k, counter, active_cu_number = 0; 5398 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5399 unsigned disable_masks[4 * 2]; 5400 5401 if (!adev || !cu_info) 5402 return -EINVAL; 5403 5404 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5405 5406 mutex_lock(&adev->grbm_idx_mutex); 5407 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5408 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5409 mask = 1; 5410 ao_bitmap = 0; 5411 counter = 0; 5412 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5413 if (i < 4 && j < 2) 5414 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 5415 adev, disable_masks[i * 2 + j]); 5416 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 5417 cu_info->bitmap[i][j] = bitmap; 5418 5419 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5420 if (bitmap & mask) { 5421 if (counter < adev->gfx.config.max_cu_per_sh) 5422 ao_bitmap |= mask; 5423 counter++; 5424 } 5425 mask <<= 1; 5426 } 5427 active_cu_number += counter; 5428 if (i < 2 && j < 2) 5429 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5430 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5431 } 5432 } 5433 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5434 mutex_unlock(&adev->grbm_idx_mutex); 5435 5436 cu_info->number = active_cu_number; 5437 cu_info->ao_cu_mask = ao_cu_mask; 5438 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5439 5440 return 0; 5441 } 5442 5443 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 5444 { 5445 .type = AMD_IP_BLOCK_TYPE_GFX, 5446 .major = 10, 5447 .minor = 0, 5448 .rev = 0, 5449 .funcs = &gfx_v10_0_ip_funcs, 5450 }; 5451