1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "smuio/smuio_11_0_0_offset.h" 39 #include "smuio/smuio_11_0_0_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "clearstate_gfx10.h" 47 #include "v10_structs.h" 48 #include "gfx_v10_0.h" 49 #include "nbio_v2_3.h" 50 51 /** 52 * Navi10 has two graphic rings to share each graphic pipe. 53 * 1. Primary ring 54 * 2. Async ring 55 */ 56 #define GFX10_NUM_GFX_RINGS_NV1X 1 57 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 58 #define GFX10_MEC_HPD_SIZE 2048 59 60 #define F32_CE_PROGRAM_RAM_SIZE 65536 61 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 62 63 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 65 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 66 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 67 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 68 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 69 70 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 71 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 72 73 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 74 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 75 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 76 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 77 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 79 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 81 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 83 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 93 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 95 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 97 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 98 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 100 101 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 102 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 103 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 104 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 105 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 106 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 107 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 108 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 109 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 110 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 111 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 112 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 113 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 114 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 115 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 116 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 117 118 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 119 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 120 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 121 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 122 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 123 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 124 #define mmCP_HYP_CE_UCODE_DATA 0x5819 125 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 126 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 127 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 128 #define mmCP_HYP_ME_UCODE_DATA 0x5817 129 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 130 131 #define mmCPG_PSP_DEBUG 0x5c10 132 #define mmCPG_PSP_DEBUG_BASE_IDX 1 133 #define mmCPC_PSP_DEBUG 0x5c11 134 #define mmCPC_PSP_DEBUG_BASE_IDX 1 135 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 136 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 137 138 //CC_GC_SA_UNIT_DISABLE 139 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 140 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 141 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 142 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 143 //GC_USER_SA_UNIT_DISABLE 144 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 145 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 146 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 147 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 148 //PA_SC_ENHANCE_3 149 #define mmPA_SC_ENHANCE_3 0x1085 150 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 151 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 152 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 153 154 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 155 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 156 157 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 158 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 159 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 160 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 161 162 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 163 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 164 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 165 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 166 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 167 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 168 169 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 170 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 171 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 172 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 173 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 174 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 175 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 176 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 177 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 178 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 179 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 180 181 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 182 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 183 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 184 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 185 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 186 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 187 188 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 189 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 190 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 191 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 192 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 193 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 194 195 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 196 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 197 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 198 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 199 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 200 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 201 202 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 205 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 212 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 215 216 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 217 { 218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 258 }; 259 260 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 261 { 262 /* Pending on emulation bring up */ 263 }; 264 265 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 266 { 267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1319 }; 1320 1321 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1322 { 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1361 }; 1362 1363 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1364 { 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 1405 }; 1406 1407 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 1408 { 1409 static void *scratch_reg0; 1410 static void *scratch_reg1; 1411 static void *spare_int; 1412 uint32_t i = 0; 1413 uint32_t retries = 50000; 1414 1415 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 1416 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 1417 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 1418 1419 if (amdgpu_sriov_runtime(adev)) { 1420 pr_err("shouldn't call rlcg write register during runtime\n"); 1421 return; 1422 } 1423 1424 writel(v, scratch_reg0); 1425 writel(offset | 0x80000000, scratch_reg1); 1426 writel(1, spare_int); 1427 for (i = 0; i < retries; i++) { 1428 u32 tmp; 1429 1430 tmp = readl(scratch_reg1); 1431 if (!(tmp & 0x80000000)) 1432 break; 1433 1434 udelay(10); 1435 } 1436 1437 if (i >= retries) 1438 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 1439 } 1440 1441 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1442 { 1443 /* Pending on emulation bring up */ 1444 }; 1445 1446 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1447 { 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2068 }; 2069 2070 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2071 { 2072 /* Pending on emulation bring up */ 2073 }; 2074 2075 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2076 { 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3129 }; 3130 3131 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3132 { 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3175 }; 3176 3177 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3178 { 3179 /* Pending on emulation bring up */ 3180 }; 3181 3182 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3183 { 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3225 3226 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3228 }; 3229 3230 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3231 { 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3255 3256 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3258 }; 3259 3260 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3261 { 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3297 }; 3298 3299 #define DEFAULT_SH_MEM_CONFIG \ 3300 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3301 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3302 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3303 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3304 3305 3306 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3307 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3308 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3309 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3310 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3311 struct amdgpu_cu_info *cu_info); 3312 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3313 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3314 u32 sh_num, u32 instance); 3315 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3316 3317 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3318 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3319 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3320 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3321 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3322 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3323 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3324 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3325 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3326 3327 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3328 { 3329 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3330 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3331 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3332 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3333 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3334 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3335 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3336 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3337 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3338 } 3339 3340 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3341 struct amdgpu_ring *ring) 3342 { 3343 struct amdgpu_device *adev = kiq_ring->adev; 3344 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3345 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3346 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3347 3348 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3349 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3350 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3351 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3352 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3353 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3354 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3355 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3356 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3357 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3358 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3359 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3360 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3361 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3362 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3363 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3364 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3365 } 3366 3367 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3368 struct amdgpu_ring *ring, 3369 enum amdgpu_unmap_queues_action action, 3370 u64 gpu_addr, u64 seq) 3371 { 3372 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3373 3374 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3375 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3376 PACKET3_UNMAP_QUEUES_ACTION(action) | 3377 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3378 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3379 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3380 amdgpu_ring_write(kiq_ring, 3381 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3382 3383 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3384 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3385 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3386 amdgpu_ring_write(kiq_ring, seq); 3387 } else { 3388 amdgpu_ring_write(kiq_ring, 0); 3389 amdgpu_ring_write(kiq_ring, 0); 3390 amdgpu_ring_write(kiq_ring, 0); 3391 } 3392 } 3393 3394 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3395 struct amdgpu_ring *ring, 3396 u64 addr, 3397 u64 seq) 3398 { 3399 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3400 3401 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3402 amdgpu_ring_write(kiq_ring, 3403 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3404 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3405 PACKET3_QUERY_STATUS_COMMAND(2)); 3406 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3407 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3408 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3409 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3410 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3411 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3412 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3413 } 3414 3415 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3416 uint16_t pasid, uint32_t flush_type, 3417 bool all_hub) 3418 { 3419 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3420 amdgpu_ring_write(kiq_ring, 3421 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3422 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3423 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3424 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3425 } 3426 3427 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3428 .kiq_set_resources = gfx10_kiq_set_resources, 3429 .kiq_map_queues = gfx10_kiq_map_queues, 3430 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3431 .kiq_query_status = gfx10_kiq_query_status, 3432 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3433 .set_resources_size = 8, 3434 .map_queues_size = 7, 3435 .unmap_queues_size = 6, 3436 .query_status_size = 7, 3437 .invalidate_tlbs_size = 2, 3438 }; 3439 3440 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3441 { 3442 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3443 } 3444 3445 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3446 { 3447 switch (adev->asic_type) { 3448 case CHIP_NAVI10: 3449 soc15_program_register_sequence(adev, 3450 golden_settings_gc_rlc_spm_10_0_nv10, 3451 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3452 break; 3453 case CHIP_NAVI14: 3454 soc15_program_register_sequence(adev, 3455 golden_settings_gc_rlc_spm_10_1_nv14, 3456 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3457 break; 3458 case CHIP_NAVI12: 3459 soc15_program_register_sequence(adev, 3460 golden_settings_gc_rlc_spm_10_1_2_nv12, 3461 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3462 break; 3463 default: 3464 break; 3465 } 3466 } 3467 3468 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3469 { 3470 switch (adev->asic_type) { 3471 case CHIP_NAVI10: 3472 soc15_program_register_sequence(adev, 3473 golden_settings_gc_10_1, 3474 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3475 soc15_program_register_sequence(adev, 3476 golden_settings_gc_10_0_nv10, 3477 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3478 break; 3479 case CHIP_NAVI14: 3480 soc15_program_register_sequence(adev, 3481 golden_settings_gc_10_1_1, 3482 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3483 soc15_program_register_sequence(adev, 3484 golden_settings_gc_10_1_nv14, 3485 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3486 break; 3487 case CHIP_NAVI12: 3488 soc15_program_register_sequence(adev, 3489 golden_settings_gc_10_1_2, 3490 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3491 soc15_program_register_sequence(adev, 3492 golden_settings_gc_10_1_2_nv12, 3493 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3494 break; 3495 case CHIP_SIENNA_CICHLID: 3496 soc15_program_register_sequence(adev, 3497 golden_settings_gc_10_3, 3498 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3499 soc15_program_register_sequence(adev, 3500 golden_settings_gc_10_3_sienna_cichlid, 3501 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3502 break; 3503 case CHIP_NAVY_FLOUNDER: 3504 soc15_program_register_sequence(adev, 3505 golden_settings_gc_10_3_2, 3506 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3507 break; 3508 case CHIP_VANGOGH: 3509 soc15_program_register_sequence(adev, 3510 golden_settings_gc_10_3_vangogh, 3511 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3512 break; 3513 case CHIP_DIMGREY_CAVEFISH: 3514 soc15_program_register_sequence(adev, 3515 golden_settings_gc_10_3_4, 3516 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3517 break; 3518 default: 3519 break; 3520 } 3521 gfx_v10_0_init_spm_golden_registers(adev); 3522 } 3523 3524 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3525 { 3526 adev->gfx.scratch.num_reg = 8; 3527 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3528 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3529 } 3530 3531 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3532 bool wc, uint32_t reg, uint32_t val) 3533 { 3534 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3535 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3536 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3537 amdgpu_ring_write(ring, reg); 3538 amdgpu_ring_write(ring, 0); 3539 amdgpu_ring_write(ring, val); 3540 } 3541 3542 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3543 int mem_space, int opt, uint32_t addr0, 3544 uint32_t addr1, uint32_t ref, uint32_t mask, 3545 uint32_t inv) 3546 { 3547 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3548 amdgpu_ring_write(ring, 3549 /* memory (1) or register (0) */ 3550 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3551 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3552 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3553 WAIT_REG_MEM_ENGINE(eng_sel))); 3554 3555 if (mem_space) 3556 BUG_ON(addr0 & 0x3); /* Dword align */ 3557 amdgpu_ring_write(ring, addr0); 3558 amdgpu_ring_write(ring, addr1); 3559 amdgpu_ring_write(ring, ref); 3560 amdgpu_ring_write(ring, mask); 3561 amdgpu_ring_write(ring, inv); /* poll interval */ 3562 } 3563 3564 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3565 { 3566 struct amdgpu_device *adev = ring->adev; 3567 uint32_t scratch; 3568 uint32_t tmp = 0; 3569 unsigned i; 3570 int r; 3571 3572 r = amdgpu_gfx_scratch_get(adev, &scratch); 3573 if (r) { 3574 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3575 return r; 3576 } 3577 3578 WREG32(scratch, 0xCAFEDEAD); 3579 3580 r = amdgpu_ring_alloc(ring, 3); 3581 if (r) { 3582 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3583 ring->idx, r); 3584 amdgpu_gfx_scratch_free(adev, scratch); 3585 return r; 3586 } 3587 3588 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3589 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3590 amdgpu_ring_write(ring, 0xDEADBEEF); 3591 amdgpu_ring_commit(ring); 3592 3593 for (i = 0; i < adev->usec_timeout; i++) { 3594 tmp = RREG32(scratch); 3595 if (tmp == 0xDEADBEEF) 3596 break; 3597 if (amdgpu_emu_mode == 1) 3598 msleep(1); 3599 else 3600 udelay(1); 3601 } 3602 3603 if (i >= adev->usec_timeout) 3604 r = -ETIMEDOUT; 3605 3606 amdgpu_gfx_scratch_free(adev, scratch); 3607 3608 return r; 3609 } 3610 3611 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3612 { 3613 struct amdgpu_device *adev = ring->adev; 3614 struct amdgpu_ib ib; 3615 struct dma_fence *f = NULL; 3616 unsigned index; 3617 uint64_t gpu_addr; 3618 uint32_t tmp; 3619 long r; 3620 3621 r = amdgpu_device_wb_get(adev, &index); 3622 if (r) 3623 return r; 3624 3625 gpu_addr = adev->wb.gpu_addr + (index * 4); 3626 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3627 memset(&ib, 0, sizeof(ib)); 3628 r = amdgpu_ib_get(adev, NULL, 16, 3629 AMDGPU_IB_POOL_DIRECT, &ib); 3630 if (r) 3631 goto err1; 3632 3633 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3634 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3635 ib.ptr[2] = lower_32_bits(gpu_addr); 3636 ib.ptr[3] = upper_32_bits(gpu_addr); 3637 ib.ptr[4] = 0xDEADBEEF; 3638 ib.length_dw = 5; 3639 3640 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3641 if (r) 3642 goto err2; 3643 3644 r = dma_fence_wait_timeout(f, false, timeout); 3645 if (r == 0) { 3646 r = -ETIMEDOUT; 3647 goto err2; 3648 } else if (r < 0) { 3649 goto err2; 3650 } 3651 3652 tmp = adev->wb.wb[index]; 3653 if (tmp == 0xDEADBEEF) 3654 r = 0; 3655 else 3656 r = -EINVAL; 3657 err2: 3658 amdgpu_ib_free(adev, &ib, NULL); 3659 dma_fence_put(f); 3660 err1: 3661 amdgpu_device_wb_free(adev, index); 3662 return r; 3663 } 3664 3665 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3666 { 3667 release_firmware(adev->gfx.pfp_fw); 3668 adev->gfx.pfp_fw = NULL; 3669 release_firmware(adev->gfx.me_fw); 3670 adev->gfx.me_fw = NULL; 3671 release_firmware(adev->gfx.ce_fw); 3672 adev->gfx.ce_fw = NULL; 3673 release_firmware(adev->gfx.rlc_fw); 3674 adev->gfx.rlc_fw = NULL; 3675 release_firmware(adev->gfx.mec_fw); 3676 adev->gfx.mec_fw = NULL; 3677 release_firmware(adev->gfx.mec2_fw); 3678 adev->gfx.mec2_fw = NULL; 3679 3680 kfree(adev->gfx.rlc.register_list_format); 3681 } 3682 3683 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3684 { 3685 adev->gfx.cp_fw_write_wait = false; 3686 3687 switch (adev->asic_type) { 3688 case CHIP_NAVI10: 3689 case CHIP_NAVI12: 3690 case CHIP_NAVI14: 3691 if ((adev->gfx.me_fw_version >= 0x00000046) && 3692 (adev->gfx.me_feature_version >= 27) && 3693 (adev->gfx.pfp_fw_version >= 0x00000068) && 3694 (adev->gfx.pfp_feature_version >= 27) && 3695 (adev->gfx.mec_fw_version >= 0x0000005b) && 3696 (adev->gfx.mec_feature_version >= 27)) 3697 adev->gfx.cp_fw_write_wait = true; 3698 break; 3699 case CHIP_SIENNA_CICHLID: 3700 case CHIP_NAVY_FLOUNDER: 3701 case CHIP_VANGOGH: 3702 case CHIP_DIMGREY_CAVEFISH: 3703 adev->gfx.cp_fw_write_wait = true; 3704 break; 3705 default: 3706 break; 3707 } 3708 3709 if (!adev->gfx.cp_fw_write_wait) 3710 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3711 } 3712 3713 3714 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3715 { 3716 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3717 3718 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 3719 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 3720 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 3721 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 3722 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 3723 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 3724 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 3725 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 3726 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 3727 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 3728 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 3729 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 3730 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 3731 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 3732 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 3733 } 3734 3735 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 3736 { 3737 const struct rlc_firmware_header_v2_2 *rlc_hdr; 3738 3739 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 3740 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 3741 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 3742 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 3743 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 3744 } 3745 3746 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3747 { 3748 bool ret = false; 3749 3750 switch (adev->pdev->revision) { 3751 case 0xc2: 3752 case 0xc3: 3753 ret = true; 3754 break; 3755 default: 3756 ret = false; 3757 break; 3758 } 3759 3760 return ret ; 3761 } 3762 3763 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3764 { 3765 switch (adev->asic_type) { 3766 case CHIP_NAVI10: 3767 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3768 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3769 break; 3770 case CHIP_VANGOGH: 3771 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3772 break; 3773 default: 3774 break; 3775 } 3776 } 3777 3778 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3779 { 3780 const char *chip_name; 3781 char fw_name[40]; 3782 char wks[10]; 3783 int err; 3784 struct amdgpu_firmware_info *info = NULL; 3785 const struct common_firmware_header *header = NULL; 3786 const struct gfx_firmware_header_v1_0 *cp_hdr; 3787 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3788 unsigned int *tmp = NULL; 3789 unsigned int i = 0; 3790 uint16_t version_major; 3791 uint16_t version_minor; 3792 3793 DRM_DEBUG("\n"); 3794 3795 memset(wks, 0, sizeof(wks)); 3796 switch (adev->asic_type) { 3797 case CHIP_NAVI10: 3798 chip_name = "navi10"; 3799 break; 3800 case CHIP_NAVI14: 3801 chip_name = "navi14"; 3802 if (!(adev->pdev->device == 0x7340 && 3803 adev->pdev->revision != 0x00)) 3804 snprintf(wks, sizeof(wks), "_wks"); 3805 break; 3806 case CHIP_NAVI12: 3807 chip_name = "navi12"; 3808 break; 3809 case CHIP_SIENNA_CICHLID: 3810 chip_name = "sienna_cichlid"; 3811 break; 3812 case CHIP_NAVY_FLOUNDER: 3813 chip_name = "navy_flounder"; 3814 break; 3815 case CHIP_VANGOGH: 3816 chip_name = "vangogh"; 3817 break; 3818 case CHIP_DIMGREY_CAVEFISH: 3819 chip_name = "dimgrey_cavefish"; 3820 break; 3821 default: 3822 BUG(); 3823 } 3824 3825 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 3826 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 3827 if (err) 3828 goto out; 3829 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 3830 if (err) 3831 goto out; 3832 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3833 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3834 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3835 3836 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 3837 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 3838 if (err) 3839 goto out; 3840 err = amdgpu_ucode_validate(adev->gfx.me_fw); 3841 if (err) 3842 goto out; 3843 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3844 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3845 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3846 3847 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 3848 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 3849 if (err) 3850 goto out; 3851 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 3852 if (err) 3853 goto out; 3854 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3855 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3856 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3857 3858 if (!amdgpu_sriov_vf(adev)) { 3859 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 3860 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 3861 if (err) 3862 goto out; 3863 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 3864 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3865 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 3866 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 3867 3868 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 3869 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 3870 adev->gfx.rlc.save_and_restore_offset = 3871 le32_to_cpu(rlc_hdr->save_and_restore_offset); 3872 adev->gfx.rlc.clear_state_descriptor_offset = 3873 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 3874 adev->gfx.rlc.avail_scratch_ram_locations = 3875 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 3876 adev->gfx.rlc.reg_restore_list_size = 3877 le32_to_cpu(rlc_hdr->reg_restore_list_size); 3878 adev->gfx.rlc.reg_list_format_start = 3879 le32_to_cpu(rlc_hdr->reg_list_format_start); 3880 adev->gfx.rlc.reg_list_format_separate_start = 3881 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 3882 adev->gfx.rlc.starting_offsets_start = 3883 le32_to_cpu(rlc_hdr->starting_offsets_start); 3884 adev->gfx.rlc.reg_list_format_size_bytes = 3885 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 3886 adev->gfx.rlc.reg_list_size_bytes = 3887 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 3888 adev->gfx.rlc.register_list_format = 3889 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 3890 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 3891 if (!adev->gfx.rlc.register_list_format) { 3892 err = -ENOMEM; 3893 goto out; 3894 } 3895 3896 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3897 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 3898 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 3899 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 3900 3901 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 3902 3903 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3904 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 3905 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 3906 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 3907 3908 if (version_major == 2) { 3909 if (version_minor >= 1) 3910 gfx_v10_0_init_rlc_ext_microcode(adev); 3911 if (version_minor == 2) 3912 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 3913 } 3914 } 3915 3916 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 3917 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 3918 if (err) 3919 goto out; 3920 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 3921 if (err) 3922 goto out; 3923 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3924 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3925 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3926 3927 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 3928 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 3929 if (!err) { 3930 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 3931 if (err) 3932 goto out; 3933 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 3934 adev->gfx.mec2_fw->data; 3935 adev->gfx.mec2_fw_version = 3936 le32_to_cpu(cp_hdr->header.ucode_version); 3937 adev->gfx.mec2_feature_version = 3938 le32_to_cpu(cp_hdr->ucode_feature_version); 3939 } else { 3940 err = 0; 3941 adev->gfx.mec2_fw = NULL; 3942 } 3943 3944 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 3945 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 3946 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 3947 info->fw = adev->gfx.pfp_fw; 3948 header = (const struct common_firmware_header *)info->fw->data; 3949 adev->firmware.fw_size += 3950 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3951 3952 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 3953 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 3954 info->fw = adev->gfx.me_fw; 3955 header = (const struct common_firmware_header *)info->fw->data; 3956 adev->firmware.fw_size += 3957 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3958 3959 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 3960 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 3961 info->fw = adev->gfx.ce_fw; 3962 header = (const struct common_firmware_header *)info->fw->data; 3963 adev->firmware.fw_size += 3964 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3965 3966 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 3967 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 3968 info->fw = adev->gfx.rlc_fw; 3969 if (info->fw) { 3970 header = (const struct common_firmware_header *)info->fw->data; 3971 adev->firmware.fw_size += 3972 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3973 } 3974 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 3975 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 3976 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 3977 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 3978 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 3979 info->fw = adev->gfx.rlc_fw; 3980 adev->firmware.fw_size += 3981 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 3982 3983 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 3984 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 3985 info->fw = adev->gfx.rlc_fw; 3986 adev->firmware.fw_size += 3987 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 3988 3989 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 3990 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 3991 info->fw = adev->gfx.rlc_fw; 3992 adev->firmware.fw_size += 3993 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 3994 3995 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 3996 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 3997 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 3998 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 3999 info->fw = adev->gfx.rlc_fw; 4000 adev->firmware.fw_size += 4001 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4002 4003 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4004 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4005 info->fw = adev->gfx.rlc_fw; 4006 adev->firmware.fw_size += 4007 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4008 } 4009 } 4010 4011 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4012 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4013 info->fw = adev->gfx.mec_fw; 4014 header = (const struct common_firmware_header *)info->fw->data; 4015 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4016 adev->firmware.fw_size += 4017 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4018 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4019 4020 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4021 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4022 info->fw = adev->gfx.mec_fw; 4023 adev->firmware.fw_size += 4024 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4025 4026 if (adev->gfx.mec2_fw) { 4027 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4028 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4029 info->fw = adev->gfx.mec2_fw; 4030 header = (const struct common_firmware_header *)info->fw->data; 4031 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4032 adev->firmware.fw_size += 4033 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4034 le32_to_cpu(cp_hdr->jt_size) * 4, 4035 PAGE_SIZE); 4036 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4037 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4038 info->fw = adev->gfx.mec2_fw; 4039 adev->firmware.fw_size += 4040 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4041 PAGE_SIZE); 4042 } 4043 } 4044 4045 gfx_v10_0_check_fw_write_wait(adev); 4046 out: 4047 if (err) { 4048 dev_err(adev->dev, 4049 "gfx10: Failed to load firmware \"%s\"\n", 4050 fw_name); 4051 release_firmware(adev->gfx.pfp_fw); 4052 adev->gfx.pfp_fw = NULL; 4053 release_firmware(adev->gfx.me_fw); 4054 adev->gfx.me_fw = NULL; 4055 release_firmware(adev->gfx.ce_fw); 4056 adev->gfx.ce_fw = NULL; 4057 release_firmware(adev->gfx.rlc_fw); 4058 adev->gfx.rlc_fw = NULL; 4059 release_firmware(adev->gfx.mec_fw); 4060 adev->gfx.mec_fw = NULL; 4061 release_firmware(adev->gfx.mec2_fw); 4062 adev->gfx.mec2_fw = NULL; 4063 } 4064 4065 gfx_v10_0_check_gfxoff_flag(adev); 4066 4067 return err; 4068 } 4069 4070 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4071 { 4072 u32 count = 0; 4073 const struct cs_section_def *sect = NULL; 4074 const struct cs_extent_def *ext = NULL; 4075 4076 /* begin clear state */ 4077 count += 2; 4078 /* context control state */ 4079 count += 3; 4080 4081 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4082 for (ext = sect->section; ext->extent != NULL; ++ext) { 4083 if (sect->id == SECT_CONTEXT) 4084 count += 2 + ext->reg_count; 4085 else 4086 return 0; 4087 } 4088 } 4089 4090 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4091 count += 3; 4092 /* end clear state */ 4093 count += 2; 4094 /* clear state */ 4095 count += 2; 4096 4097 return count; 4098 } 4099 4100 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4101 volatile u32 *buffer) 4102 { 4103 u32 count = 0, i; 4104 const struct cs_section_def *sect = NULL; 4105 const struct cs_extent_def *ext = NULL; 4106 int ctx_reg_offset; 4107 4108 if (adev->gfx.rlc.cs_data == NULL) 4109 return; 4110 if (buffer == NULL) 4111 return; 4112 4113 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4114 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4115 4116 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4117 buffer[count++] = cpu_to_le32(0x80000000); 4118 buffer[count++] = cpu_to_le32(0x80000000); 4119 4120 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4121 for (ext = sect->section; ext->extent != NULL; ++ext) { 4122 if (sect->id == SECT_CONTEXT) { 4123 buffer[count++] = 4124 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4125 buffer[count++] = cpu_to_le32(ext->reg_index - 4126 PACKET3_SET_CONTEXT_REG_START); 4127 for (i = 0; i < ext->reg_count; i++) 4128 buffer[count++] = cpu_to_le32(ext->extent[i]); 4129 } else { 4130 return; 4131 } 4132 } 4133 } 4134 4135 ctx_reg_offset = 4136 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4137 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4138 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4139 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4140 4141 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4142 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4143 4144 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4145 buffer[count++] = cpu_to_le32(0); 4146 } 4147 4148 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4149 { 4150 /* clear state block */ 4151 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4152 &adev->gfx.rlc.clear_state_gpu_addr, 4153 (void **)&adev->gfx.rlc.cs_ptr); 4154 4155 /* jump table block */ 4156 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4157 &adev->gfx.rlc.cp_table_gpu_addr, 4158 (void **)&adev->gfx.rlc.cp_table_ptr); 4159 } 4160 4161 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4162 { 4163 const struct cs_section_def *cs_data; 4164 int r; 4165 4166 adev->gfx.rlc.cs_data = gfx10_cs_data; 4167 4168 cs_data = adev->gfx.rlc.cs_data; 4169 4170 if (cs_data) { 4171 /* init clear state block */ 4172 r = amdgpu_gfx_rlc_init_csb(adev); 4173 if (r) 4174 return r; 4175 } 4176 4177 /* init spm vmid with 0xf */ 4178 if (adev->gfx.rlc.funcs->update_spm_vmid) 4179 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4180 4181 return 0; 4182 } 4183 4184 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4185 { 4186 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4187 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4188 } 4189 4190 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4191 { 4192 int r; 4193 4194 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4195 4196 amdgpu_gfx_graphics_queue_acquire(adev); 4197 4198 r = gfx_v10_0_init_microcode(adev); 4199 if (r) 4200 DRM_ERROR("Failed to load gfx firmware!\n"); 4201 4202 return r; 4203 } 4204 4205 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4206 { 4207 int r; 4208 u32 *hpd; 4209 const __le32 *fw_data = NULL; 4210 unsigned fw_size; 4211 u32 *fw = NULL; 4212 size_t mec_hpd_size; 4213 4214 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4215 4216 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4217 4218 /* take ownership of the relevant compute queues */ 4219 amdgpu_gfx_compute_queue_acquire(adev); 4220 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4221 4222 if (mec_hpd_size) { 4223 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4224 AMDGPU_GEM_DOMAIN_GTT, 4225 &adev->gfx.mec.hpd_eop_obj, 4226 &adev->gfx.mec.hpd_eop_gpu_addr, 4227 (void **)&hpd); 4228 if (r) { 4229 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4230 gfx_v10_0_mec_fini(adev); 4231 return r; 4232 } 4233 4234 memset(hpd, 0, mec_hpd_size); 4235 4236 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4237 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4238 } 4239 4240 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4241 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4242 4243 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4244 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4245 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4246 4247 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4248 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4249 &adev->gfx.mec.mec_fw_obj, 4250 &adev->gfx.mec.mec_fw_gpu_addr, 4251 (void **)&fw); 4252 if (r) { 4253 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4254 gfx_v10_0_mec_fini(adev); 4255 return r; 4256 } 4257 4258 memcpy(fw, fw_data, fw_size); 4259 4260 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4261 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4262 } 4263 4264 return 0; 4265 } 4266 4267 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4268 { 4269 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4270 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4271 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4272 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4273 } 4274 4275 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4276 uint32_t thread, uint32_t regno, 4277 uint32_t num, uint32_t *out) 4278 { 4279 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4280 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4281 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4282 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4283 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4284 while (num--) 4285 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4286 } 4287 4288 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4289 { 4290 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4291 * field when performing a select_se_sh so it should be 4292 * zero here */ 4293 WARN_ON(simd != 0); 4294 4295 /* type 2 wave data */ 4296 dst[(*no_fields)++] = 2; 4297 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4298 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4299 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4300 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4301 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4302 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4303 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4304 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4305 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4306 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4307 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4308 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4309 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4310 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4311 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4312 } 4313 4314 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4315 uint32_t wave, uint32_t start, 4316 uint32_t size, uint32_t *dst) 4317 { 4318 WARN_ON(simd != 0); 4319 4320 wave_read_regs( 4321 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4322 dst); 4323 } 4324 4325 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4326 uint32_t wave, uint32_t thread, 4327 uint32_t start, uint32_t size, 4328 uint32_t *dst) 4329 { 4330 wave_read_regs( 4331 adev, wave, thread, 4332 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4333 } 4334 4335 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4336 u32 me, u32 pipe, u32 q, u32 vm) 4337 { 4338 nv_grbm_select(adev, me, pipe, q, vm); 4339 } 4340 4341 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4342 bool enable) 4343 { 4344 uint32_t data, def; 4345 4346 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4347 4348 if (enable) 4349 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4350 else 4351 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4352 4353 if (data != def) 4354 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4355 } 4356 4357 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4358 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4359 .select_se_sh = &gfx_v10_0_select_se_sh, 4360 .read_wave_data = &gfx_v10_0_read_wave_data, 4361 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4362 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4363 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4364 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4365 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4366 }; 4367 4368 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4369 { 4370 u32 gb_addr_config; 4371 4372 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4373 4374 switch (adev->asic_type) { 4375 case CHIP_NAVI10: 4376 case CHIP_NAVI14: 4377 case CHIP_NAVI12: 4378 adev->gfx.config.max_hw_contexts = 8; 4379 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4380 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4381 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4382 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4383 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4384 break; 4385 case CHIP_SIENNA_CICHLID: 4386 case CHIP_NAVY_FLOUNDER: 4387 case CHIP_VANGOGH: 4388 case CHIP_DIMGREY_CAVEFISH: 4389 adev->gfx.config.max_hw_contexts = 8; 4390 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4391 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4392 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4393 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4394 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4395 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4396 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4397 break; 4398 default: 4399 BUG(); 4400 break; 4401 } 4402 4403 adev->gfx.config.gb_addr_config = gb_addr_config; 4404 4405 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4406 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4407 GB_ADDR_CONFIG, NUM_PIPES); 4408 4409 adev->gfx.config.max_tile_pipes = 4410 adev->gfx.config.gb_addr_config_fields.num_pipes; 4411 4412 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4413 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4414 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4415 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4416 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4417 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4418 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4419 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4420 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4421 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4422 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4423 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4424 } 4425 4426 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4427 int me, int pipe, int queue) 4428 { 4429 int r; 4430 struct amdgpu_ring *ring; 4431 unsigned int irq_type; 4432 4433 ring = &adev->gfx.gfx_ring[ring_id]; 4434 4435 ring->me = me; 4436 ring->pipe = pipe; 4437 ring->queue = queue; 4438 4439 ring->ring_obj = NULL; 4440 ring->use_doorbell = true; 4441 4442 if (!ring_id) 4443 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4444 else 4445 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4446 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4447 4448 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4449 r = amdgpu_ring_init(adev, ring, 1024, 4450 &adev->gfx.eop_irq, irq_type, 4451 AMDGPU_RING_PRIO_DEFAULT); 4452 if (r) 4453 return r; 4454 return 0; 4455 } 4456 4457 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4458 int mec, int pipe, int queue) 4459 { 4460 int r; 4461 unsigned irq_type; 4462 struct amdgpu_ring *ring; 4463 unsigned int hw_prio; 4464 4465 ring = &adev->gfx.compute_ring[ring_id]; 4466 4467 /* mec0 is me1 */ 4468 ring->me = mec + 1; 4469 ring->pipe = pipe; 4470 ring->queue = queue; 4471 4472 ring->ring_obj = NULL; 4473 ring->use_doorbell = true; 4474 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4475 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4476 + (ring_id * GFX10_MEC_HPD_SIZE); 4477 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4478 4479 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4480 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4481 + ring->pipe; 4482 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 4483 ring->queue) ? 4484 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4485 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4486 r = amdgpu_ring_init(adev, ring, 1024, 4487 &adev->gfx.eop_irq, irq_type, hw_prio); 4488 if (r) 4489 return r; 4490 4491 return 0; 4492 } 4493 4494 static int gfx_v10_0_sw_init(void *handle) 4495 { 4496 int i, j, k, r, ring_id = 0; 4497 struct amdgpu_kiq *kiq; 4498 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4499 4500 switch (adev->asic_type) { 4501 case CHIP_NAVI10: 4502 case CHIP_NAVI14: 4503 case CHIP_NAVI12: 4504 adev->gfx.me.num_me = 1; 4505 adev->gfx.me.num_pipe_per_me = 1; 4506 adev->gfx.me.num_queue_per_pipe = 1; 4507 adev->gfx.mec.num_mec = 2; 4508 adev->gfx.mec.num_pipe_per_mec = 4; 4509 adev->gfx.mec.num_queue_per_pipe = 8; 4510 break; 4511 case CHIP_SIENNA_CICHLID: 4512 case CHIP_NAVY_FLOUNDER: 4513 case CHIP_VANGOGH: 4514 case CHIP_DIMGREY_CAVEFISH: 4515 adev->gfx.me.num_me = 1; 4516 adev->gfx.me.num_pipe_per_me = 1; 4517 adev->gfx.me.num_queue_per_pipe = 1; 4518 adev->gfx.mec.num_mec = 2; 4519 adev->gfx.mec.num_pipe_per_mec = 4; 4520 adev->gfx.mec.num_queue_per_pipe = 4; 4521 break; 4522 default: 4523 adev->gfx.me.num_me = 1; 4524 adev->gfx.me.num_pipe_per_me = 1; 4525 adev->gfx.me.num_queue_per_pipe = 1; 4526 adev->gfx.mec.num_mec = 1; 4527 adev->gfx.mec.num_pipe_per_mec = 4; 4528 adev->gfx.mec.num_queue_per_pipe = 8; 4529 break; 4530 } 4531 4532 /* KIQ event */ 4533 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4534 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4535 &adev->gfx.kiq.irq); 4536 if (r) 4537 return r; 4538 4539 /* EOP Event */ 4540 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4541 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4542 &adev->gfx.eop_irq); 4543 if (r) 4544 return r; 4545 4546 /* Privileged reg */ 4547 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4548 &adev->gfx.priv_reg_irq); 4549 if (r) 4550 return r; 4551 4552 /* Privileged inst */ 4553 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4554 &adev->gfx.priv_inst_irq); 4555 if (r) 4556 return r; 4557 4558 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4559 4560 gfx_v10_0_scratch_init(adev); 4561 4562 r = gfx_v10_0_me_init(adev); 4563 if (r) 4564 return r; 4565 4566 r = gfx_v10_0_rlc_init(adev); 4567 if (r) { 4568 DRM_ERROR("Failed to init rlc BOs!\n"); 4569 return r; 4570 } 4571 4572 r = gfx_v10_0_mec_init(adev); 4573 if (r) { 4574 DRM_ERROR("Failed to init MEC BOs!\n"); 4575 return r; 4576 } 4577 4578 /* set up the gfx ring */ 4579 for (i = 0; i < adev->gfx.me.num_me; i++) { 4580 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4581 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4582 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4583 continue; 4584 4585 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4586 i, k, j); 4587 if (r) 4588 return r; 4589 ring_id++; 4590 } 4591 } 4592 } 4593 4594 ring_id = 0; 4595 /* set up the compute queues - allocate horizontally across pipes */ 4596 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4597 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4598 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4599 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4600 j)) 4601 continue; 4602 4603 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4604 i, k, j); 4605 if (r) 4606 return r; 4607 4608 ring_id++; 4609 } 4610 } 4611 } 4612 4613 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4614 if (r) { 4615 DRM_ERROR("Failed to init KIQ BOs!\n"); 4616 return r; 4617 } 4618 4619 kiq = &adev->gfx.kiq; 4620 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4621 if (r) 4622 return r; 4623 4624 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4625 if (r) 4626 return r; 4627 4628 /* allocate visible FB for rlc auto-loading fw */ 4629 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4630 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4631 if (r) 4632 return r; 4633 } 4634 4635 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4636 4637 gfx_v10_0_gpu_early_init(adev); 4638 4639 return 0; 4640 } 4641 4642 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4643 { 4644 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4645 &adev->gfx.pfp.pfp_fw_gpu_addr, 4646 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4647 } 4648 4649 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4650 { 4651 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4652 &adev->gfx.ce.ce_fw_gpu_addr, 4653 (void **)&adev->gfx.ce.ce_fw_ptr); 4654 } 4655 4656 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4657 { 4658 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4659 &adev->gfx.me.me_fw_gpu_addr, 4660 (void **)&adev->gfx.me.me_fw_ptr); 4661 } 4662 4663 static int gfx_v10_0_sw_fini(void *handle) 4664 { 4665 int i; 4666 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4667 4668 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4669 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4670 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4671 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4672 4673 amdgpu_gfx_mqd_sw_fini(adev); 4674 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4675 amdgpu_gfx_kiq_fini(adev); 4676 4677 gfx_v10_0_pfp_fini(adev); 4678 gfx_v10_0_ce_fini(adev); 4679 gfx_v10_0_me_fini(adev); 4680 gfx_v10_0_rlc_fini(adev); 4681 gfx_v10_0_mec_fini(adev); 4682 4683 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4684 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4685 4686 gfx_v10_0_free_microcode(adev); 4687 4688 return 0; 4689 } 4690 4691 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4692 u32 sh_num, u32 instance) 4693 { 4694 u32 data; 4695 4696 if (instance == 0xffffffff) 4697 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4698 INSTANCE_BROADCAST_WRITES, 1); 4699 else 4700 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4701 instance); 4702 4703 if (se_num == 0xffffffff) 4704 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4705 1); 4706 else 4707 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4708 4709 if (sh_num == 0xffffffff) 4710 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4711 1); 4712 else 4713 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4714 4715 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4716 } 4717 4718 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4719 { 4720 u32 data, mask; 4721 4722 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4723 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4724 4725 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4726 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4727 4728 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4729 adev->gfx.config.max_sh_per_se); 4730 4731 return (~data) & mask; 4732 } 4733 4734 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4735 { 4736 int i, j; 4737 u32 data; 4738 u32 active_rbs = 0; 4739 u32 bitmap; 4740 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4741 adev->gfx.config.max_sh_per_se; 4742 4743 mutex_lock(&adev->grbm_idx_mutex); 4744 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4745 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4746 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4747 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 4748 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4749 continue; 4750 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4751 data = gfx_v10_0_get_rb_active_bitmap(adev); 4752 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4753 rb_bitmap_width_per_sh); 4754 } 4755 } 4756 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4757 mutex_unlock(&adev->grbm_idx_mutex); 4758 4759 adev->gfx.config.backend_enable_mask = active_rbs; 4760 adev->gfx.config.num_rbs = hweight32(active_rbs); 4761 } 4762 4763 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4764 { 4765 uint32_t num_sc; 4766 uint32_t enabled_rb_per_sh; 4767 uint32_t active_rb_bitmap; 4768 uint32_t num_rb_per_sc; 4769 uint32_t num_packer_per_sc; 4770 uint32_t pa_sc_tile_steering_override; 4771 4772 /* for ASICs that integrates GFX v10.3 4773 * pa_sc_tile_steering_override should be set to 0 */ 4774 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 4775 return 0; 4776 4777 /* init num_sc */ 4778 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4779 adev->gfx.config.num_sc_per_sh; 4780 /* init num_rb_per_sc */ 4781 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4782 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4783 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4784 /* init num_packer_per_sc */ 4785 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4786 4787 pa_sc_tile_steering_override = 0; 4788 pa_sc_tile_steering_override |= 4789 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4790 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4791 pa_sc_tile_steering_override |= 4792 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4793 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4794 pa_sc_tile_steering_override |= 4795 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4796 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4797 4798 return pa_sc_tile_steering_override; 4799 } 4800 4801 #define DEFAULT_SH_MEM_BASES (0x6000) 4802 4803 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4804 { 4805 int i; 4806 uint32_t sh_mem_bases; 4807 4808 /* 4809 * Configure apertures: 4810 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4811 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4812 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4813 */ 4814 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4815 4816 mutex_lock(&adev->srbm_mutex); 4817 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4818 nv_grbm_select(adev, 0, 0, 0, i); 4819 /* CP and shaders */ 4820 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4821 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4822 } 4823 nv_grbm_select(adev, 0, 0, 0, 0); 4824 mutex_unlock(&adev->srbm_mutex); 4825 4826 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4827 acccess. These should be enabled by FW for target VMIDs. */ 4828 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4829 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4830 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4831 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4832 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4833 } 4834 } 4835 4836 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4837 { 4838 int vmid; 4839 4840 /* 4841 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4842 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4843 * the driver can enable them for graphics. VMID0 should maintain 4844 * access so that HWS firmware can save/restore entries. 4845 */ 4846 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4847 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4848 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4849 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4850 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4851 } 4852 } 4853 4854 4855 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4856 { 4857 int i, j, k; 4858 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4859 u32 tmp, wgp_active_bitmap = 0; 4860 u32 gcrd_targets_disable_tcp = 0; 4861 u32 utcl_invreq_disable = 0; 4862 /* 4863 * GCRD_TARGETS_DISABLE field contains 4864 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4865 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4866 */ 4867 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4868 2 * max_wgp_per_sh + /* TCP */ 4869 max_wgp_per_sh + /* SQC */ 4870 4); /* GL1C */ 4871 /* 4872 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4873 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4874 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4875 */ 4876 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4877 2 * max_wgp_per_sh + /* TCP */ 4878 2 * max_wgp_per_sh + /* SQC */ 4879 4 + /* RMI */ 4880 1); /* SQG */ 4881 4882 if (adev->asic_type == CHIP_NAVI10 || 4883 adev->asic_type == CHIP_NAVI14 || 4884 adev->asic_type == CHIP_NAVI12) { 4885 mutex_lock(&adev->grbm_idx_mutex); 4886 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4887 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4888 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4889 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4890 /* 4891 * Set corresponding TCP bits for the inactive WGPs in 4892 * GCRD_SA_TARGETS_DISABLE 4893 */ 4894 gcrd_targets_disable_tcp = 0; 4895 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4896 utcl_invreq_disable = 0; 4897 4898 for (k = 0; k < max_wgp_per_sh; k++) { 4899 if (!(wgp_active_bitmap & (1 << k))) { 4900 gcrd_targets_disable_tcp |= 3 << (2 * k); 4901 utcl_invreq_disable |= (3 << (2 * k)) | 4902 (3 << (2 * (max_wgp_per_sh + k))); 4903 } 4904 } 4905 4906 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4907 /* only override TCP & SQC bits */ 4908 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 4909 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4910 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4911 4912 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4913 /* only override TCP bits */ 4914 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 4915 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4916 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4917 } 4918 } 4919 4920 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4921 mutex_unlock(&adev->grbm_idx_mutex); 4922 } 4923 } 4924 4925 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4926 { 4927 /* TCCs are global (not instanced). */ 4928 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4929 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4930 4931 adev->gfx.config.tcc_disabled_mask = 4932 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4933 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4934 } 4935 4936 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4937 { 4938 u32 tmp; 4939 int i; 4940 4941 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4942 4943 gfx_v10_0_setup_rb(adev); 4944 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4945 gfx_v10_0_get_tcc_info(adev); 4946 adev->gfx.config.pa_sc_tile_steering_override = 4947 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4948 4949 /* XXX SH_MEM regs */ 4950 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4951 mutex_lock(&adev->srbm_mutex); 4952 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 4953 nv_grbm_select(adev, 0, 0, 0, i); 4954 /* CP and shaders */ 4955 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4956 if (i != 0) { 4957 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4958 (adev->gmc.private_aperture_start >> 48)); 4959 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4960 (adev->gmc.shared_aperture_start >> 48)); 4961 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4962 } 4963 } 4964 nv_grbm_select(adev, 0, 0, 0, 0); 4965 4966 mutex_unlock(&adev->srbm_mutex); 4967 4968 gfx_v10_0_init_compute_vmid(adev); 4969 gfx_v10_0_init_gds_vmid(adev); 4970 4971 } 4972 4973 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 4974 bool enable) 4975 { 4976 u32 tmp; 4977 4978 if (amdgpu_sriov_vf(adev)) 4979 return; 4980 4981 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 4982 4983 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 4984 enable ? 1 : 0); 4985 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 4986 enable ? 1 : 0); 4987 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 4988 enable ? 1 : 0); 4989 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 4990 enable ? 1 : 0); 4991 4992 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 4993 } 4994 4995 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 4996 { 4997 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 4998 4999 /* csib */ 5000 if (adev->asic_type == CHIP_NAVI12) { 5001 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5002 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5003 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5004 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5005 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5006 } else { 5007 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5008 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5009 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5010 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5011 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5012 } 5013 return 0; 5014 } 5015 5016 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5017 { 5018 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5019 5020 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5021 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5022 } 5023 5024 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5025 { 5026 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5027 udelay(50); 5028 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5029 udelay(50); 5030 } 5031 5032 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5033 bool enable) 5034 { 5035 uint32_t rlc_pg_cntl; 5036 5037 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5038 5039 if (!enable) { 5040 /* RLC_PG_CNTL[23] = 0 (default) 5041 * RLC will wait for handshake acks with SMU 5042 * GFXOFF will be enabled 5043 * RLC_PG_CNTL[23] = 1 5044 * RLC will not issue any message to SMU 5045 * hence no handshake between SMU & RLC 5046 * GFXOFF will be disabled 5047 */ 5048 rlc_pg_cntl |= 0x800000; 5049 } else 5050 rlc_pg_cntl &= ~0x800000; 5051 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5052 } 5053 5054 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5055 { 5056 /* TODO: enable rlc & smu handshake until smu 5057 * and gfxoff feature works as expected */ 5058 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5059 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5060 5061 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5062 udelay(50); 5063 } 5064 5065 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5066 { 5067 uint32_t tmp; 5068 5069 /* enable Save Restore Machine */ 5070 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 5071 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5072 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5073 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 5074 } 5075 5076 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5077 { 5078 const struct rlc_firmware_header_v2_0 *hdr; 5079 const __le32 *fw_data; 5080 unsigned i, fw_size; 5081 5082 if (!adev->gfx.rlc_fw) 5083 return -EINVAL; 5084 5085 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5086 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5087 5088 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5089 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5090 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5091 5092 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5093 RLCG_UCODE_LOADING_START_ADDRESS); 5094 5095 for (i = 0; i < fw_size; i++) 5096 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5097 le32_to_cpup(fw_data++)); 5098 5099 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5100 5101 return 0; 5102 } 5103 5104 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5105 { 5106 int r; 5107 5108 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 5109 5110 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5111 if (r) 5112 return r; 5113 5114 gfx_v10_0_init_csb(adev); 5115 5116 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5117 gfx_v10_0_rlc_enable_srm(adev); 5118 } else { 5119 if (amdgpu_sriov_vf(adev)) { 5120 gfx_v10_0_init_csb(adev); 5121 return 0; 5122 } 5123 5124 adev->gfx.rlc.funcs->stop(adev); 5125 5126 /* disable CG */ 5127 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5128 5129 /* disable PG */ 5130 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5131 5132 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5133 /* legacy rlc firmware loading */ 5134 r = gfx_v10_0_rlc_load_microcode(adev); 5135 if (r) 5136 return r; 5137 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5138 /* rlc backdoor autoload firmware */ 5139 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5140 if (r) 5141 return r; 5142 } 5143 5144 gfx_v10_0_init_csb(adev); 5145 5146 adev->gfx.rlc.funcs->start(adev); 5147 5148 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5149 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5150 if (r) 5151 return r; 5152 } 5153 } 5154 return 0; 5155 } 5156 5157 static struct { 5158 FIRMWARE_ID id; 5159 unsigned int offset; 5160 unsigned int size; 5161 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5162 5163 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5164 { 5165 int ret; 5166 RLC_TABLE_OF_CONTENT *rlc_toc; 5167 5168 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 5169 AMDGPU_GEM_DOMAIN_GTT, 5170 &adev->gfx.rlc.rlc_toc_bo, 5171 &adev->gfx.rlc.rlc_toc_gpu_addr, 5172 (void **)&adev->gfx.rlc.rlc_toc_buf); 5173 if (ret) { 5174 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5175 return ret; 5176 } 5177 5178 /* Copy toc from psp sos fw to rlc toc buffer */ 5179 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 5180 5181 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5182 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5183 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5184 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5185 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5186 /* Offset needs 4KB alignment */ 5187 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5188 } 5189 5190 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5191 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5192 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5193 5194 rlc_toc++; 5195 } 5196 5197 return 0; 5198 } 5199 5200 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5201 { 5202 uint32_t total_size = 0; 5203 FIRMWARE_ID id; 5204 int ret; 5205 5206 ret = gfx_v10_0_parse_rlc_toc(adev); 5207 if (ret) { 5208 dev_err(adev->dev, "failed to parse rlc toc\n"); 5209 return 0; 5210 } 5211 5212 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5213 total_size += rlc_autoload_info[id].size; 5214 5215 /* In case the offset in rlc toc ucode is aligned */ 5216 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5217 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5218 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5219 5220 return total_size; 5221 } 5222 5223 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5224 { 5225 int r; 5226 uint32_t total_size; 5227 5228 total_size = gfx_v10_0_calc_toc_total_size(adev); 5229 5230 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5231 AMDGPU_GEM_DOMAIN_GTT, 5232 &adev->gfx.rlc.rlc_autoload_bo, 5233 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5234 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5235 if (r) { 5236 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5237 return r; 5238 } 5239 5240 return 0; 5241 } 5242 5243 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5244 { 5245 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5246 &adev->gfx.rlc.rlc_toc_gpu_addr, 5247 (void **)&adev->gfx.rlc.rlc_toc_buf); 5248 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5249 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5250 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5251 } 5252 5253 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5254 FIRMWARE_ID id, 5255 const void *fw_data, 5256 uint32_t fw_size) 5257 { 5258 uint32_t toc_offset; 5259 uint32_t toc_fw_size; 5260 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5261 5262 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5263 return; 5264 5265 toc_offset = rlc_autoload_info[id].offset; 5266 toc_fw_size = rlc_autoload_info[id].size; 5267 5268 if (fw_size == 0) 5269 fw_size = toc_fw_size; 5270 5271 if (fw_size > toc_fw_size) 5272 fw_size = toc_fw_size; 5273 5274 memcpy(ptr + toc_offset, fw_data, fw_size); 5275 5276 if (fw_size < toc_fw_size) 5277 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5278 } 5279 5280 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5281 { 5282 void *data; 5283 uint32_t size; 5284 5285 data = adev->gfx.rlc.rlc_toc_buf; 5286 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5287 5288 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5289 FIRMWARE_ID_RLC_TOC, 5290 data, size); 5291 } 5292 5293 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5294 { 5295 const __le32 *fw_data; 5296 uint32_t fw_size; 5297 const struct gfx_firmware_header_v1_0 *cp_hdr; 5298 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5299 5300 /* pfp ucode */ 5301 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5302 adev->gfx.pfp_fw->data; 5303 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5304 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5305 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5306 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5307 FIRMWARE_ID_CP_PFP, 5308 fw_data, fw_size); 5309 5310 /* ce ucode */ 5311 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5312 adev->gfx.ce_fw->data; 5313 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5314 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5315 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5316 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5317 FIRMWARE_ID_CP_CE, 5318 fw_data, fw_size); 5319 5320 /* me ucode */ 5321 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5322 adev->gfx.me_fw->data; 5323 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5324 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5325 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5326 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5327 FIRMWARE_ID_CP_ME, 5328 fw_data, fw_size); 5329 5330 /* rlc ucode */ 5331 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5332 adev->gfx.rlc_fw->data; 5333 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5334 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5335 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5336 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5337 FIRMWARE_ID_RLC_G_UCODE, 5338 fw_data, fw_size); 5339 5340 /* mec1 ucode */ 5341 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5342 adev->gfx.mec_fw->data; 5343 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5344 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5345 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5346 cp_hdr->jt_size * 4; 5347 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5348 FIRMWARE_ID_CP_MEC, 5349 fw_data, fw_size); 5350 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5351 } 5352 5353 /* Temporarily put sdma part here */ 5354 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5355 { 5356 const __le32 *fw_data; 5357 uint32_t fw_size; 5358 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5359 int i; 5360 5361 for (i = 0; i < adev->sdma.num_instances; i++) { 5362 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5363 adev->sdma.instance[i].fw->data; 5364 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5365 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5366 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5367 5368 if (i == 0) { 5369 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5370 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5371 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5372 FIRMWARE_ID_SDMA0_JT, 5373 (uint32_t *)fw_data + 5374 sdma_hdr->jt_offset, 5375 sdma_hdr->jt_size * 4); 5376 } else if (i == 1) { 5377 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5378 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5379 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5380 FIRMWARE_ID_SDMA1_JT, 5381 (uint32_t *)fw_data + 5382 sdma_hdr->jt_offset, 5383 sdma_hdr->jt_size * 4); 5384 } 5385 } 5386 } 5387 5388 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5389 { 5390 uint32_t rlc_g_offset, rlc_g_size, tmp; 5391 uint64_t gpu_addr; 5392 5393 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5394 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5395 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5396 5397 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5398 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5399 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5400 5401 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5402 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5403 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5404 5405 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5406 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5407 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5408 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5409 return -EINVAL; 5410 } 5411 5412 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5413 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5414 DRM_ERROR("RLC ROM should halt itself\n"); 5415 return -EINVAL; 5416 } 5417 5418 return 0; 5419 } 5420 5421 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5422 { 5423 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5424 uint32_t tmp; 5425 int i; 5426 uint64_t addr; 5427 5428 /* Trigger an invalidation of the L1 instruction caches */ 5429 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5430 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5431 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5432 5433 /* Wait for invalidation complete */ 5434 for (i = 0; i < usec_timeout; i++) { 5435 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5436 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5437 INVALIDATE_CACHE_COMPLETE)) 5438 break; 5439 udelay(1); 5440 } 5441 5442 if (i >= usec_timeout) { 5443 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5444 return -EINVAL; 5445 } 5446 5447 /* Program me ucode address into intruction cache address register */ 5448 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5449 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5450 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5451 lower_32_bits(addr) & 0xFFFFF000); 5452 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5453 upper_32_bits(addr)); 5454 5455 return 0; 5456 } 5457 5458 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5459 { 5460 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5461 uint32_t tmp; 5462 int i; 5463 uint64_t addr; 5464 5465 /* Trigger an invalidation of the L1 instruction caches */ 5466 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5467 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5468 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5469 5470 /* Wait for invalidation complete */ 5471 for (i = 0; i < usec_timeout; i++) { 5472 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5473 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5474 INVALIDATE_CACHE_COMPLETE)) 5475 break; 5476 udelay(1); 5477 } 5478 5479 if (i >= usec_timeout) { 5480 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5481 return -EINVAL; 5482 } 5483 5484 /* Program ce ucode address into intruction cache address register */ 5485 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5486 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5487 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5488 lower_32_bits(addr) & 0xFFFFF000); 5489 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5490 upper_32_bits(addr)); 5491 5492 return 0; 5493 } 5494 5495 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5496 { 5497 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5498 uint32_t tmp; 5499 int i; 5500 uint64_t addr; 5501 5502 /* Trigger an invalidation of the L1 instruction caches */ 5503 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5504 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5505 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5506 5507 /* Wait for invalidation complete */ 5508 for (i = 0; i < usec_timeout; i++) { 5509 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5510 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5511 INVALIDATE_CACHE_COMPLETE)) 5512 break; 5513 udelay(1); 5514 } 5515 5516 if (i >= usec_timeout) { 5517 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5518 return -EINVAL; 5519 } 5520 5521 /* Program pfp ucode address into intruction cache address register */ 5522 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5523 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5524 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5525 lower_32_bits(addr) & 0xFFFFF000); 5526 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5527 upper_32_bits(addr)); 5528 5529 return 0; 5530 } 5531 5532 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5533 { 5534 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5535 uint32_t tmp; 5536 int i; 5537 uint64_t addr; 5538 5539 /* Trigger an invalidation of the L1 instruction caches */ 5540 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5541 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5542 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5543 5544 /* Wait for invalidation complete */ 5545 for (i = 0; i < usec_timeout; i++) { 5546 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5547 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5548 INVALIDATE_CACHE_COMPLETE)) 5549 break; 5550 udelay(1); 5551 } 5552 5553 if (i >= usec_timeout) { 5554 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5555 return -EINVAL; 5556 } 5557 5558 /* Program mec1 ucode address into intruction cache address register */ 5559 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5560 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5561 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5562 lower_32_bits(addr) & 0xFFFFF000); 5563 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5564 upper_32_bits(addr)); 5565 5566 return 0; 5567 } 5568 5569 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5570 { 5571 uint32_t cp_status; 5572 uint32_t bootload_status; 5573 int i, r; 5574 5575 for (i = 0; i < adev->usec_timeout; i++) { 5576 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5577 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5578 if ((cp_status == 0) && 5579 (REG_GET_FIELD(bootload_status, 5580 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5581 break; 5582 } 5583 udelay(1); 5584 } 5585 5586 if (i >= adev->usec_timeout) { 5587 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5588 return -ETIMEDOUT; 5589 } 5590 5591 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5592 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5593 if (r) 5594 return r; 5595 5596 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5597 if (r) 5598 return r; 5599 5600 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5601 if (r) 5602 return r; 5603 5604 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5605 if (r) 5606 return r; 5607 } 5608 5609 return 0; 5610 } 5611 5612 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5613 { 5614 int i; 5615 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5616 5617 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5618 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5619 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5620 5621 if (adev->asic_type == CHIP_NAVI12) { 5622 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5623 } else { 5624 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5625 } 5626 5627 for (i = 0; i < adev->usec_timeout; i++) { 5628 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5629 break; 5630 udelay(1); 5631 } 5632 5633 if (i >= adev->usec_timeout) 5634 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5635 5636 return 0; 5637 } 5638 5639 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5640 { 5641 int r; 5642 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5643 const __le32 *fw_data; 5644 unsigned i, fw_size; 5645 uint32_t tmp; 5646 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5647 5648 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5649 adev->gfx.pfp_fw->data; 5650 5651 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5652 5653 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5654 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5655 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5656 5657 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5658 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5659 &adev->gfx.pfp.pfp_fw_obj, 5660 &adev->gfx.pfp.pfp_fw_gpu_addr, 5661 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5662 if (r) { 5663 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5664 gfx_v10_0_pfp_fini(adev); 5665 return r; 5666 } 5667 5668 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5669 5670 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5671 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5672 5673 /* Trigger an invalidation of the L1 instruction caches */ 5674 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5675 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5676 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5677 5678 /* Wait for invalidation complete */ 5679 for (i = 0; i < usec_timeout; i++) { 5680 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5681 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5682 INVALIDATE_CACHE_COMPLETE)) 5683 break; 5684 udelay(1); 5685 } 5686 5687 if (i >= usec_timeout) { 5688 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5689 return -EINVAL; 5690 } 5691 5692 if (amdgpu_emu_mode == 1) 5693 adev->hdp.funcs->flush_hdp(adev, NULL); 5694 5695 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5696 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5697 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5698 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5699 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5700 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5701 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5702 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5703 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5704 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5705 5706 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5707 5708 for (i = 0; i < pfp_hdr->jt_size; i++) 5709 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5710 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5711 5712 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5713 5714 return 0; 5715 } 5716 5717 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5718 { 5719 int r; 5720 const struct gfx_firmware_header_v1_0 *ce_hdr; 5721 const __le32 *fw_data; 5722 unsigned i, fw_size; 5723 uint32_t tmp; 5724 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5725 5726 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5727 adev->gfx.ce_fw->data; 5728 5729 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5730 5731 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5732 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5733 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5734 5735 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5736 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5737 &adev->gfx.ce.ce_fw_obj, 5738 &adev->gfx.ce.ce_fw_gpu_addr, 5739 (void **)&adev->gfx.ce.ce_fw_ptr); 5740 if (r) { 5741 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5742 gfx_v10_0_ce_fini(adev); 5743 return r; 5744 } 5745 5746 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5747 5748 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5749 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5750 5751 /* Trigger an invalidation of the L1 instruction caches */ 5752 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5753 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5754 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5755 5756 /* Wait for invalidation complete */ 5757 for (i = 0; i < usec_timeout; i++) { 5758 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5759 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5760 INVALIDATE_CACHE_COMPLETE)) 5761 break; 5762 udelay(1); 5763 } 5764 5765 if (i >= usec_timeout) { 5766 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5767 return -EINVAL; 5768 } 5769 5770 if (amdgpu_emu_mode == 1) 5771 adev->hdp.funcs->flush_hdp(adev, NULL); 5772 5773 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5774 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5775 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5776 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5777 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5778 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5779 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5780 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5781 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5782 5783 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5784 5785 for (i = 0; i < ce_hdr->jt_size; i++) 5786 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5787 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5788 5789 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5790 5791 return 0; 5792 } 5793 5794 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5795 { 5796 int r; 5797 const struct gfx_firmware_header_v1_0 *me_hdr; 5798 const __le32 *fw_data; 5799 unsigned i, fw_size; 5800 uint32_t tmp; 5801 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5802 5803 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5804 adev->gfx.me_fw->data; 5805 5806 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5807 5808 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5809 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5810 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5811 5812 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5813 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5814 &adev->gfx.me.me_fw_obj, 5815 &adev->gfx.me.me_fw_gpu_addr, 5816 (void **)&adev->gfx.me.me_fw_ptr); 5817 if (r) { 5818 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5819 gfx_v10_0_me_fini(adev); 5820 return r; 5821 } 5822 5823 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5824 5825 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5826 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5827 5828 /* Trigger an invalidation of the L1 instruction caches */ 5829 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5830 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5831 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5832 5833 /* Wait for invalidation complete */ 5834 for (i = 0; i < usec_timeout; i++) { 5835 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5836 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5837 INVALIDATE_CACHE_COMPLETE)) 5838 break; 5839 udelay(1); 5840 } 5841 5842 if (i >= usec_timeout) { 5843 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5844 return -EINVAL; 5845 } 5846 5847 if (amdgpu_emu_mode == 1) 5848 adev->hdp.funcs->flush_hdp(adev, NULL); 5849 5850 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5851 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5852 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5853 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5854 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5855 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5856 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5857 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5858 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5859 5860 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5861 5862 for (i = 0; i < me_hdr->jt_size; i++) 5863 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5864 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5865 5866 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5867 5868 return 0; 5869 } 5870 5871 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5872 { 5873 int r; 5874 5875 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5876 return -EINVAL; 5877 5878 gfx_v10_0_cp_gfx_enable(adev, false); 5879 5880 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5881 if (r) { 5882 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5883 return r; 5884 } 5885 5886 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5887 if (r) { 5888 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5889 return r; 5890 } 5891 5892 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5893 if (r) { 5894 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5895 return r; 5896 } 5897 5898 return 0; 5899 } 5900 5901 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5902 { 5903 struct amdgpu_ring *ring; 5904 const struct cs_section_def *sect = NULL; 5905 const struct cs_extent_def *ext = NULL; 5906 int r, i; 5907 int ctx_reg_offset; 5908 5909 /* init the CP */ 5910 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5911 adev->gfx.config.max_hw_contexts - 1); 5912 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5913 5914 gfx_v10_0_cp_gfx_enable(adev, true); 5915 5916 ring = &adev->gfx.gfx_ring[0]; 5917 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5918 if (r) { 5919 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5920 return r; 5921 } 5922 5923 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5924 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5925 5926 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5927 amdgpu_ring_write(ring, 0x80000000); 5928 amdgpu_ring_write(ring, 0x80000000); 5929 5930 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5931 for (ext = sect->section; ext->extent != NULL; ++ext) { 5932 if (sect->id == SECT_CONTEXT) { 5933 amdgpu_ring_write(ring, 5934 PACKET3(PACKET3_SET_CONTEXT_REG, 5935 ext->reg_count)); 5936 amdgpu_ring_write(ring, ext->reg_index - 5937 PACKET3_SET_CONTEXT_REG_START); 5938 for (i = 0; i < ext->reg_count; i++) 5939 amdgpu_ring_write(ring, ext->extent[i]); 5940 } 5941 } 5942 } 5943 5944 ctx_reg_offset = 5945 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5946 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5947 amdgpu_ring_write(ring, ctx_reg_offset); 5948 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5949 5950 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5951 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5952 5953 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5954 amdgpu_ring_write(ring, 0); 5955 5956 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 5957 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 5958 amdgpu_ring_write(ring, 0x8000); 5959 amdgpu_ring_write(ring, 0x8000); 5960 5961 amdgpu_ring_commit(ring); 5962 5963 /* submit cs packet to copy state 0 to next available state */ 5964 if (adev->gfx.num_gfx_rings > 1) { 5965 /* maximum supported gfx ring is 2 */ 5966 ring = &adev->gfx.gfx_ring[1]; 5967 r = amdgpu_ring_alloc(ring, 2); 5968 if (r) { 5969 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5970 return r; 5971 } 5972 5973 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5974 amdgpu_ring_write(ring, 0); 5975 5976 amdgpu_ring_commit(ring); 5977 } 5978 return 0; 5979 } 5980 5981 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 5982 CP_PIPE_ID pipe) 5983 { 5984 u32 tmp; 5985 5986 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 5987 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 5988 5989 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 5990 } 5991 5992 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 5993 struct amdgpu_ring *ring) 5994 { 5995 u32 tmp; 5996 5997 if (!amdgpu_async_gfx_ring) { 5998 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 5999 if (ring->use_doorbell) { 6000 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6001 DOORBELL_OFFSET, ring->doorbell_index); 6002 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6003 DOORBELL_EN, 1); 6004 } else { 6005 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6006 DOORBELL_EN, 0); 6007 } 6008 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6009 } 6010 switch (adev->asic_type) { 6011 case CHIP_SIENNA_CICHLID: 6012 case CHIP_NAVY_FLOUNDER: 6013 case CHIP_VANGOGH: 6014 case CHIP_DIMGREY_CAVEFISH: 6015 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6016 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6017 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6018 6019 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6020 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6021 break; 6022 default: 6023 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6024 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6025 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6026 6027 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6028 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6029 break; 6030 } 6031 } 6032 6033 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6034 { 6035 struct amdgpu_ring *ring; 6036 u32 tmp; 6037 u32 rb_bufsz; 6038 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6039 u32 i; 6040 6041 /* Set the write pointer delay */ 6042 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6043 6044 /* set the RB to use vmid 0 */ 6045 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6046 6047 /* Init gfx ring 0 for pipe 0 */ 6048 mutex_lock(&adev->srbm_mutex); 6049 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6050 6051 /* Set ring buffer size */ 6052 ring = &adev->gfx.gfx_ring[0]; 6053 rb_bufsz = order_base_2(ring->ring_size / 8); 6054 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6055 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6056 #ifdef __BIG_ENDIAN 6057 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6058 #endif 6059 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6060 6061 /* Initialize the ring buffer's write pointers */ 6062 ring->wptr = 0; 6063 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6064 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6065 6066 /* set the wb address wether it's enabled or not */ 6067 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6068 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6069 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6070 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6071 6072 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6073 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6074 lower_32_bits(wptr_gpu_addr)); 6075 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6076 upper_32_bits(wptr_gpu_addr)); 6077 6078 mdelay(1); 6079 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6080 6081 rb_addr = ring->gpu_addr >> 8; 6082 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6083 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6084 6085 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6086 6087 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6088 mutex_unlock(&adev->srbm_mutex); 6089 6090 /* Init gfx ring 1 for pipe 1 */ 6091 if (adev->gfx.num_gfx_rings > 1) { 6092 mutex_lock(&adev->srbm_mutex); 6093 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6094 /* maximum supported gfx ring is 2 */ 6095 ring = &adev->gfx.gfx_ring[1]; 6096 rb_bufsz = order_base_2(ring->ring_size / 8); 6097 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6098 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6099 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6100 /* Initialize the ring buffer's write pointers */ 6101 ring->wptr = 0; 6102 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6103 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6104 /* Set the wb address wether it's enabled or not */ 6105 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6106 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6107 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6108 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6109 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6110 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6111 lower_32_bits(wptr_gpu_addr)); 6112 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6113 upper_32_bits(wptr_gpu_addr)); 6114 6115 mdelay(1); 6116 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6117 6118 rb_addr = ring->gpu_addr >> 8; 6119 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6120 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6121 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6122 6123 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6124 mutex_unlock(&adev->srbm_mutex); 6125 } 6126 /* Switch to pipe 0 */ 6127 mutex_lock(&adev->srbm_mutex); 6128 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6129 mutex_unlock(&adev->srbm_mutex); 6130 6131 /* start the ring */ 6132 gfx_v10_0_cp_gfx_start(adev); 6133 6134 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6135 ring = &adev->gfx.gfx_ring[i]; 6136 ring->sched.ready = true; 6137 } 6138 6139 return 0; 6140 } 6141 6142 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6143 { 6144 if (enable) { 6145 switch (adev->asic_type) { 6146 case CHIP_SIENNA_CICHLID: 6147 case CHIP_NAVY_FLOUNDER: 6148 case CHIP_VANGOGH: 6149 case CHIP_DIMGREY_CAVEFISH: 6150 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6151 break; 6152 default: 6153 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6154 break; 6155 } 6156 } else { 6157 switch (adev->asic_type) { 6158 case CHIP_SIENNA_CICHLID: 6159 case CHIP_NAVY_FLOUNDER: 6160 case CHIP_VANGOGH: 6161 case CHIP_DIMGREY_CAVEFISH: 6162 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6163 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6164 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6165 break; 6166 default: 6167 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6168 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6169 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6170 break; 6171 } 6172 adev->gfx.kiq.ring.sched.ready = false; 6173 } 6174 udelay(50); 6175 } 6176 6177 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6178 { 6179 const struct gfx_firmware_header_v1_0 *mec_hdr; 6180 const __le32 *fw_data; 6181 unsigned i; 6182 u32 tmp; 6183 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6184 6185 if (!adev->gfx.mec_fw) 6186 return -EINVAL; 6187 6188 gfx_v10_0_cp_compute_enable(adev, false); 6189 6190 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6191 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6192 6193 fw_data = (const __le32 *) 6194 (adev->gfx.mec_fw->data + 6195 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6196 6197 /* Trigger an invalidation of the L1 instruction caches */ 6198 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6199 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6200 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6201 6202 /* Wait for invalidation complete */ 6203 for (i = 0; i < usec_timeout; i++) { 6204 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6205 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6206 INVALIDATE_CACHE_COMPLETE)) 6207 break; 6208 udelay(1); 6209 } 6210 6211 if (i >= usec_timeout) { 6212 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6213 return -EINVAL; 6214 } 6215 6216 if (amdgpu_emu_mode == 1) 6217 adev->hdp.funcs->flush_hdp(adev, NULL); 6218 6219 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6220 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6221 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6222 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6223 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6224 6225 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6226 0xFFFFF000); 6227 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6228 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6229 6230 /* MEC1 */ 6231 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6232 6233 for (i = 0; i < mec_hdr->jt_size; i++) 6234 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6235 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6236 6237 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6238 6239 /* 6240 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6241 * different microcode than MEC1. 6242 */ 6243 6244 return 0; 6245 } 6246 6247 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6248 { 6249 uint32_t tmp; 6250 struct amdgpu_device *adev = ring->adev; 6251 6252 /* tell RLC which is KIQ queue */ 6253 switch (adev->asic_type) { 6254 case CHIP_SIENNA_CICHLID: 6255 case CHIP_NAVY_FLOUNDER: 6256 case CHIP_VANGOGH: 6257 case CHIP_DIMGREY_CAVEFISH: 6258 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6259 tmp &= 0xffffff00; 6260 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6261 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6262 tmp |= 0x80; 6263 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6264 break; 6265 default: 6266 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6267 tmp &= 0xffffff00; 6268 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6269 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6270 tmp |= 0x80; 6271 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6272 break; 6273 } 6274 } 6275 6276 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6277 { 6278 struct amdgpu_device *adev = ring->adev; 6279 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6280 uint64_t hqd_gpu_addr, wb_gpu_addr; 6281 uint32_t tmp; 6282 uint32_t rb_bufsz; 6283 6284 /* set up gfx hqd wptr */ 6285 mqd->cp_gfx_hqd_wptr = 0; 6286 mqd->cp_gfx_hqd_wptr_hi = 0; 6287 6288 /* set the pointer to the MQD */ 6289 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6290 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6291 6292 /* set up mqd control */ 6293 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6294 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6295 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6296 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6297 mqd->cp_gfx_mqd_control = tmp; 6298 6299 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6300 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6301 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6302 mqd->cp_gfx_hqd_vmid = 0; 6303 6304 /* set up default queue priority level 6305 * 0x0 = low priority, 0x1 = high priority */ 6306 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6307 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6308 mqd->cp_gfx_hqd_queue_priority = tmp; 6309 6310 /* set up time quantum */ 6311 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6312 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6313 mqd->cp_gfx_hqd_quantum = tmp; 6314 6315 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6316 hqd_gpu_addr = ring->gpu_addr >> 8; 6317 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6318 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6319 6320 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6321 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6322 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6323 mqd->cp_gfx_hqd_rptr_addr_hi = 6324 upper_32_bits(wb_gpu_addr) & 0xffff; 6325 6326 /* set up rb_wptr_poll addr */ 6327 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6328 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6329 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6330 6331 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6332 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6333 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6334 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6335 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6336 #ifdef __BIG_ENDIAN 6337 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6338 #endif 6339 mqd->cp_gfx_hqd_cntl = tmp; 6340 6341 /* set up cp_doorbell_control */ 6342 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6343 if (ring->use_doorbell) { 6344 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6345 DOORBELL_OFFSET, ring->doorbell_index); 6346 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6347 DOORBELL_EN, 1); 6348 } else 6349 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6350 DOORBELL_EN, 0); 6351 mqd->cp_rb_doorbell_control = tmp; 6352 6353 /*if there are 2 gfx rings, set the lower doorbell range of the first ring, 6354 *otherwise the range of the second ring will override the first ring */ 6355 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6356 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6357 6358 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6359 ring->wptr = 0; 6360 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6361 6362 /* active the queue */ 6363 mqd->cp_gfx_hqd_active = 1; 6364 6365 return 0; 6366 } 6367 6368 #ifdef BRING_UP_DEBUG 6369 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6370 { 6371 struct amdgpu_device *adev = ring->adev; 6372 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6373 6374 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6375 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6376 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6377 6378 /* set GFX_MQD_BASE */ 6379 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6380 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6381 6382 /* set GFX_MQD_CONTROL */ 6383 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6384 6385 /* set GFX_HQD_VMID to 0 */ 6386 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6387 6388 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6389 mqd->cp_gfx_hqd_queue_priority); 6390 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6391 6392 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6393 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6394 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6395 6396 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6397 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6398 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6399 6400 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6401 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6402 6403 /* set RB_WPTR_POLL_ADDR */ 6404 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6405 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6406 6407 /* set RB_DOORBELL_CONTROL */ 6408 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6409 6410 /* active the queue */ 6411 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6412 6413 return 0; 6414 } 6415 #endif 6416 6417 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6418 { 6419 struct amdgpu_device *adev = ring->adev; 6420 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6421 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6422 6423 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6424 memset((void *)mqd, 0, sizeof(*mqd)); 6425 mutex_lock(&adev->srbm_mutex); 6426 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6427 gfx_v10_0_gfx_mqd_init(ring); 6428 #ifdef BRING_UP_DEBUG 6429 gfx_v10_0_gfx_queue_init_register(ring); 6430 #endif 6431 nv_grbm_select(adev, 0, 0, 0, 0); 6432 mutex_unlock(&adev->srbm_mutex); 6433 if (adev->gfx.me.mqd_backup[mqd_idx]) 6434 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6435 } else if (amdgpu_in_reset(adev)) { 6436 /* reset mqd with the backup copy */ 6437 if (adev->gfx.me.mqd_backup[mqd_idx]) 6438 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6439 /* reset the ring */ 6440 ring->wptr = 0; 6441 adev->wb.wb[ring->wptr_offs] = 0; 6442 amdgpu_ring_clear_ring(ring); 6443 #ifdef BRING_UP_DEBUG 6444 mutex_lock(&adev->srbm_mutex); 6445 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6446 gfx_v10_0_gfx_queue_init_register(ring); 6447 nv_grbm_select(adev, 0, 0, 0, 0); 6448 mutex_unlock(&adev->srbm_mutex); 6449 #endif 6450 } else { 6451 amdgpu_ring_clear_ring(ring); 6452 } 6453 6454 return 0; 6455 } 6456 6457 #ifndef BRING_UP_DEBUG 6458 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6459 { 6460 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6461 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6462 int r, i; 6463 6464 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6465 return -EINVAL; 6466 6467 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6468 adev->gfx.num_gfx_rings); 6469 if (r) { 6470 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6471 return r; 6472 } 6473 6474 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6475 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6476 6477 return amdgpu_ring_test_helper(kiq_ring); 6478 } 6479 #endif 6480 6481 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6482 { 6483 int r, i; 6484 struct amdgpu_ring *ring; 6485 6486 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6487 ring = &adev->gfx.gfx_ring[i]; 6488 6489 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6490 if (unlikely(r != 0)) 6491 goto done; 6492 6493 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6494 if (!r) { 6495 r = gfx_v10_0_gfx_init_queue(ring); 6496 amdgpu_bo_kunmap(ring->mqd_obj); 6497 ring->mqd_ptr = NULL; 6498 } 6499 amdgpu_bo_unreserve(ring->mqd_obj); 6500 if (r) 6501 goto done; 6502 } 6503 #ifndef BRING_UP_DEBUG 6504 r = gfx_v10_0_kiq_enable_kgq(adev); 6505 if (r) 6506 goto done; 6507 #endif 6508 r = gfx_v10_0_cp_gfx_start(adev); 6509 if (r) 6510 goto done; 6511 6512 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6513 ring = &adev->gfx.gfx_ring[i]; 6514 ring->sched.ready = true; 6515 } 6516 done: 6517 return r; 6518 } 6519 6520 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6521 { 6522 struct amdgpu_device *adev = ring->adev; 6523 6524 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6525 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 6526 ring->queue)) { 6527 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6528 mqd->cp_hqd_queue_priority = 6529 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6530 } 6531 } 6532 } 6533 6534 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6535 { 6536 struct amdgpu_device *adev = ring->adev; 6537 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6538 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6539 uint32_t tmp; 6540 6541 mqd->header = 0xC0310800; 6542 mqd->compute_pipelinestat_enable = 0x00000001; 6543 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6544 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6545 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6546 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6547 mqd->compute_misc_reserved = 0x00000003; 6548 6549 eop_base_addr = ring->eop_gpu_addr >> 8; 6550 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6551 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6552 6553 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6554 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6555 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6556 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6557 6558 mqd->cp_hqd_eop_control = tmp; 6559 6560 /* enable doorbell? */ 6561 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6562 6563 if (ring->use_doorbell) { 6564 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6565 DOORBELL_OFFSET, ring->doorbell_index); 6566 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6567 DOORBELL_EN, 1); 6568 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6569 DOORBELL_SOURCE, 0); 6570 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6571 DOORBELL_HIT, 0); 6572 } else { 6573 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6574 DOORBELL_EN, 0); 6575 } 6576 6577 mqd->cp_hqd_pq_doorbell_control = tmp; 6578 6579 /* disable the queue if it's active */ 6580 ring->wptr = 0; 6581 mqd->cp_hqd_dequeue_request = 0; 6582 mqd->cp_hqd_pq_rptr = 0; 6583 mqd->cp_hqd_pq_wptr_lo = 0; 6584 mqd->cp_hqd_pq_wptr_hi = 0; 6585 6586 /* set the pointer to the MQD */ 6587 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6588 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6589 6590 /* set MQD vmid to 0 */ 6591 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6592 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6593 mqd->cp_mqd_control = tmp; 6594 6595 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6596 hqd_gpu_addr = ring->gpu_addr >> 8; 6597 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6598 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6599 6600 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6601 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6602 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6603 (order_base_2(ring->ring_size / 4) - 1)); 6604 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6605 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6606 #ifdef __BIG_ENDIAN 6607 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6608 #endif 6609 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6610 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6611 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6612 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6613 mqd->cp_hqd_pq_control = tmp; 6614 6615 /* set the wb address whether it's enabled or not */ 6616 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6617 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6618 mqd->cp_hqd_pq_rptr_report_addr_hi = 6619 upper_32_bits(wb_gpu_addr) & 0xffff; 6620 6621 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6622 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6623 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6624 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6625 6626 tmp = 0; 6627 /* enable the doorbell if requested */ 6628 if (ring->use_doorbell) { 6629 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6630 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6631 DOORBELL_OFFSET, ring->doorbell_index); 6632 6633 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6634 DOORBELL_EN, 1); 6635 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6636 DOORBELL_SOURCE, 0); 6637 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6638 DOORBELL_HIT, 0); 6639 } 6640 6641 mqd->cp_hqd_pq_doorbell_control = tmp; 6642 6643 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6644 ring->wptr = 0; 6645 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6646 6647 /* set the vmid for the queue */ 6648 mqd->cp_hqd_vmid = 0; 6649 6650 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6651 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6652 mqd->cp_hqd_persistent_state = tmp; 6653 6654 /* set MIN_IB_AVAIL_SIZE */ 6655 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6656 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6657 mqd->cp_hqd_ib_control = tmp; 6658 6659 /* set static priority for a compute queue/ring */ 6660 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6661 6662 /* map_queues packet doesn't need activate the queue, 6663 * so only kiq need set this field. 6664 */ 6665 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6666 mqd->cp_hqd_active = 1; 6667 6668 return 0; 6669 } 6670 6671 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6672 { 6673 struct amdgpu_device *adev = ring->adev; 6674 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6675 int j; 6676 6677 /* inactivate the queue */ 6678 if (amdgpu_sriov_vf(adev)) 6679 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6680 6681 /* disable wptr polling */ 6682 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6683 6684 /* write the EOP addr */ 6685 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6686 mqd->cp_hqd_eop_base_addr_lo); 6687 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6688 mqd->cp_hqd_eop_base_addr_hi); 6689 6690 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6691 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6692 mqd->cp_hqd_eop_control); 6693 6694 /* enable doorbell? */ 6695 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6696 mqd->cp_hqd_pq_doorbell_control); 6697 6698 /* disable the queue if it's active */ 6699 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6700 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6701 for (j = 0; j < adev->usec_timeout; j++) { 6702 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6703 break; 6704 udelay(1); 6705 } 6706 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6707 mqd->cp_hqd_dequeue_request); 6708 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6709 mqd->cp_hqd_pq_rptr); 6710 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6711 mqd->cp_hqd_pq_wptr_lo); 6712 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6713 mqd->cp_hqd_pq_wptr_hi); 6714 } 6715 6716 /* set the pointer to the MQD */ 6717 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6718 mqd->cp_mqd_base_addr_lo); 6719 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6720 mqd->cp_mqd_base_addr_hi); 6721 6722 /* set MQD vmid to 0 */ 6723 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6724 mqd->cp_mqd_control); 6725 6726 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6727 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6728 mqd->cp_hqd_pq_base_lo); 6729 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6730 mqd->cp_hqd_pq_base_hi); 6731 6732 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6733 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6734 mqd->cp_hqd_pq_control); 6735 6736 /* set the wb address whether it's enabled or not */ 6737 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6738 mqd->cp_hqd_pq_rptr_report_addr_lo); 6739 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6740 mqd->cp_hqd_pq_rptr_report_addr_hi); 6741 6742 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6743 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6744 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6745 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6746 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6747 6748 /* enable the doorbell if requested */ 6749 if (ring->use_doorbell) { 6750 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6751 (adev->doorbell_index.kiq * 2) << 2); 6752 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6753 (adev->doorbell_index.userqueue_end * 2) << 2); 6754 } 6755 6756 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6757 mqd->cp_hqd_pq_doorbell_control); 6758 6759 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6760 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6761 mqd->cp_hqd_pq_wptr_lo); 6762 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6763 mqd->cp_hqd_pq_wptr_hi); 6764 6765 /* set the vmid for the queue */ 6766 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6767 6768 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6769 mqd->cp_hqd_persistent_state); 6770 6771 /* activate the queue */ 6772 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6773 mqd->cp_hqd_active); 6774 6775 if (ring->use_doorbell) 6776 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6777 6778 return 0; 6779 } 6780 6781 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6782 { 6783 struct amdgpu_device *adev = ring->adev; 6784 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6785 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6786 6787 gfx_v10_0_kiq_setting(ring); 6788 6789 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6790 /* reset MQD to a clean status */ 6791 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6792 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6793 6794 /* reset ring buffer */ 6795 ring->wptr = 0; 6796 amdgpu_ring_clear_ring(ring); 6797 6798 mutex_lock(&adev->srbm_mutex); 6799 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6800 gfx_v10_0_kiq_init_register(ring); 6801 nv_grbm_select(adev, 0, 0, 0, 0); 6802 mutex_unlock(&adev->srbm_mutex); 6803 } else { 6804 memset((void *)mqd, 0, sizeof(*mqd)); 6805 mutex_lock(&adev->srbm_mutex); 6806 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6807 gfx_v10_0_compute_mqd_init(ring); 6808 gfx_v10_0_kiq_init_register(ring); 6809 nv_grbm_select(adev, 0, 0, 0, 0); 6810 mutex_unlock(&adev->srbm_mutex); 6811 6812 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6813 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6814 } 6815 6816 return 0; 6817 } 6818 6819 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6820 { 6821 struct amdgpu_device *adev = ring->adev; 6822 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6823 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6824 6825 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6826 memset((void *)mqd, 0, sizeof(*mqd)); 6827 mutex_lock(&adev->srbm_mutex); 6828 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6829 gfx_v10_0_compute_mqd_init(ring); 6830 nv_grbm_select(adev, 0, 0, 0, 0); 6831 mutex_unlock(&adev->srbm_mutex); 6832 6833 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6834 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6835 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6836 /* reset MQD to a clean status */ 6837 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6838 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6839 6840 /* reset ring buffer */ 6841 ring->wptr = 0; 6842 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 6843 amdgpu_ring_clear_ring(ring); 6844 } else { 6845 amdgpu_ring_clear_ring(ring); 6846 } 6847 6848 return 0; 6849 } 6850 6851 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6852 { 6853 struct amdgpu_ring *ring; 6854 int r; 6855 6856 ring = &adev->gfx.kiq.ring; 6857 6858 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6859 if (unlikely(r != 0)) 6860 return r; 6861 6862 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6863 if (unlikely(r != 0)) 6864 return r; 6865 6866 gfx_v10_0_kiq_init_queue(ring); 6867 amdgpu_bo_kunmap(ring->mqd_obj); 6868 ring->mqd_ptr = NULL; 6869 amdgpu_bo_unreserve(ring->mqd_obj); 6870 ring->sched.ready = true; 6871 return 0; 6872 } 6873 6874 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6875 { 6876 struct amdgpu_ring *ring = NULL; 6877 int r = 0, i; 6878 6879 gfx_v10_0_cp_compute_enable(adev, true); 6880 6881 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6882 ring = &adev->gfx.compute_ring[i]; 6883 6884 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6885 if (unlikely(r != 0)) 6886 goto done; 6887 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6888 if (!r) { 6889 r = gfx_v10_0_kcq_init_queue(ring); 6890 amdgpu_bo_kunmap(ring->mqd_obj); 6891 ring->mqd_ptr = NULL; 6892 } 6893 amdgpu_bo_unreserve(ring->mqd_obj); 6894 if (r) 6895 goto done; 6896 } 6897 6898 r = amdgpu_gfx_enable_kcq(adev); 6899 done: 6900 return r; 6901 } 6902 6903 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6904 { 6905 int r, i; 6906 struct amdgpu_ring *ring; 6907 6908 if (!(adev->flags & AMD_IS_APU)) 6909 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6910 6911 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6912 /* legacy firmware loading */ 6913 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6914 if (r) 6915 return r; 6916 6917 r = gfx_v10_0_cp_compute_load_microcode(adev); 6918 if (r) 6919 return r; 6920 } 6921 6922 r = gfx_v10_0_kiq_resume(adev); 6923 if (r) 6924 return r; 6925 6926 r = gfx_v10_0_kcq_resume(adev); 6927 if (r) 6928 return r; 6929 6930 if (!amdgpu_async_gfx_ring) { 6931 r = gfx_v10_0_cp_gfx_resume(adev); 6932 if (r) 6933 return r; 6934 } else { 6935 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6936 if (r) 6937 return r; 6938 } 6939 6940 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6941 ring = &adev->gfx.gfx_ring[i]; 6942 r = amdgpu_ring_test_helper(ring); 6943 if (r) 6944 return r; 6945 } 6946 6947 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6948 ring = &adev->gfx.compute_ring[i]; 6949 r = amdgpu_ring_test_helper(ring); 6950 if (r) 6951 return r; 6952 } 6953 6954 return 0; 6955 } 6956 6957 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6958 { 6959 gfx_v10_0_cp_gfx_enable(adev, enable); 6960 gfx_v10_0_cp_compute_enable(adev, enable); 6961 } 6962 6963 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6964 { 6965 uint32_t data, pattern = 0xDEADBEEF; 6966 6967 /* check if mmVGT_ESGS_RING_SIZE_UMD 6968 * has been remapped to mmVGT_ESGS_RING_SIZE */ 6969 switch (adev->asic_type) { 6970 case CHIP_SIENNA_CICHLID: 6971 case CHIP_NAVY_FLOUNDER: 6972 case CHIP_DIMGREY_CAVEFISH: 6973 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6974 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6975 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6976 6977 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6978 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 6979 return true; 6980 } else { 6981 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6982 return false; 6983 } 6984 break; 6985 case CHIP_VANGOGH: 6986 return true; 6987 default: 6988 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6989 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 6990 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6991 6992 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 6993 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6994 return true; 6995 } else { 6996 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 6997 return false; 6998 } 6999 break; 7000 } 7001 } 7002 7003 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7004 { 7005 uint32_t data; 7006 7007 /* initialize cam_index to 0 7008 * index will auto-inc after each data writting */ 7009 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7010 7011 switch (adev->asic_type) { 7012 case CHIP_SIENNA_CICHLID: 7013 case CHIP_NAVY_FLOUNDER: 7014 case CHIP_VANGOGH: 7015 case CHIP_DIMGREY_CAVEFISH: 7016 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7017 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7018 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7019 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7020 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7021 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7022 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7023 7024 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7025 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7026 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7027 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7028 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7029 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7030 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7031 7032 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7033 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7034 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7035 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7036 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7037 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7038 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7039 7040 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7041 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7042 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7043 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7044 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7045 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7046 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7047 7048 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7049 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7050 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7051 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7052 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7053 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7054 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7055 7056 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7057 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7058 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7059 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7060 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7061 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7062 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7063 7064 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7065 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7066 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7067 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7068 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7069 break; 7070 default: 7071 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7072 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7073 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7074 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7075 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7076 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7077 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7078 7079 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7080 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7081 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7082 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7083 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7084 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7085 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7086 7087 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7088 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7089 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7090 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7091 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7092 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7093 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7094 7095 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7096 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7097 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7098 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7099 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7100 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7101 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7102 7103 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7104 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7105 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7106 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7107 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7108 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7109 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7110 7111 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7112 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7113 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7114 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7115 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7116 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7117 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7118 7119 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7120 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7121 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7122 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7123 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7124 break; 7125 } 7126 7127 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7128 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7129 } 7130 7131 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7132 { 7133 uint32_t data; 7134 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7135 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7136 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7137 7138 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7139 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7140 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7141 } 7142 7143 static int gfx_v10_0_hw_init(void *handle) 7144 { 7145 int r; 7146 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7147 7148 if (!amdgpu_emu_mode) 7149 gfx_v10_0_init_golden_registers(adev); 7150 7151 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7152 /** 7153 * For gfx 10, rlc firmware loading relies on smu firmware is 7154 * loaded firstly, so in direct type, it has to load smc ucode 7155 * here before rlc. 7156 */ 7157 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) { 7158 r = smu_load_microcode(&adev->smu); 7159 if (r) 7160 return r; 7161 7162 r = smu_check_fw_status(&adev->smu); 7163 if (r) { 7164 pr_err("SMC firmware status is not correct\n"); 7165 return r; 7166 } 7167 } 7168 gfx_v10_0_disable_gpa_mode(adev); 7169 } 7170 7171 /* if GRBM CAM not remapped, set up the remapping */ 7172 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7173 gfx_v10_0_setup_grbm_cam_remapping(adev); 7174 7175 gfx_v10_0_constants_init(adev); 7176 7177 r = gfx_v10_0_rlc_resume(adev); 7178 if (r) 7179 return r; 7180 7181 /* 7182 * init golden registers and rlc resume may override some registers, 7183 * reconfig them here 7184 */ 7185 gfx_v10_0_tcp_harvest(adev); 7186 7187 r = gfx_v10_0_cp_resume(adev); 7188 if (r) 7189 return r; 7190 7191 if (adev->asic_type == CHIP_SIENNA_CICHLID) 7192 gfx_v10_3_program_pbb_mode(adev); 7193 7194 return r; 7195 } 7196 7197 #ifndef BRING_UP_DEBUG 7198 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7199 { 7200 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7201 struct amdgpu_ring *kiq_ring = &kiq->ring; 7202 int i; 7203 7204 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7205 return -EINVAL; 7206 7207 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7208 adev->gfx.num_gfx_rings)) 7209 return -ENOMEM; 7210 7211 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7212 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7213 PREEMPT_QUEUES, 0, 0); 7214 7215 return amdgpu_ring_test_helper(kiq_ring); 7216 } 7217 #endif 7218 7219 static int gfx_v10_0_hw_fini(void *handle) 7220 { 7221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7222 int r; 7223 uint32_t tmp; 7224 7225 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7226 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7227 7228 if (!adev->in_pci_err_recovery) { 7229 #ifndef BRING_UP_DEBUG 7230 if (amdgpu_async_gfx_ring) { 7231 r = gfx_v10_0_kiq_disable_kgq(adev); 7232 if (r) 7233 DRM_ERROR("KGQ disable failed\n"); 7234 } 7235 #endif 7236 if (amdgpu_gfx_disable_kcq(adev)) 7237 DRM_ERROR("KCQ disable failed\n"); 7238 } 7239 7240 if (amdgpu_sriov_vf(adev)) { 7241 gfx_v10_0_cp_gfx_enable(adev, false); 7242 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7243 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7244 tmp &= 0xffffff00; 7245 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7246 7247 return 0; 7248 } 7249 gfx_v10_0_cp_enable(adev, false); 7250 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7251 7252 return 0; 7253 } 7254 7255 static int gfx_v10_0_suspend(void *handle) 7256 { 7257 return gfx_v10_0_hw_fini(handle); 7258 } 7259 7260 static int gfx_v10_0_resume(void *handle) 7261 { 7262 return gfx_v10_0_hw_init(handle); 7263 } 7264 7265 static bool gfx_v10_0_is_idle(void *handle) 7266 { 7267 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7268 7269 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7270 GRBM_STATUS, GUI_ACTIVE)) 7271 return false; 7272 else 7273 return true; 7274 } 7275 7276 static int gfx_v10_0_wait_for_idle(void *handle) 7277 { 7278 unsigned i; 7279 u32 tmp; 7280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7281 7282 for (i = 0; i < adev->usec_timeout; i++) { 7283 /* read MC_STATUS */ 7284 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7285 GRBM_STATUS__GUI_ACTIVE_MASK; 7286 7287 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7288 return 0; 7289 udelay(1); 7290 } 7291 return -ETIMEDOUT; 7292 } 7293 7294 static int gfx_v10_0_soft_reset(void *handle) 7295 { 7296 u32 grbm_soft_reset = 0; 7297 u32 tmp; 7298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7299 7300 /* GRBM_STATUS */ 7301 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7302 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7303 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7304 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7305 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7306 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7307 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7308 GRBM_SOFT_RESET, SOFT_RESET_CP, 7309 1); 7310 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7311 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7312 1); 7313 } 7314 7315 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7316 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7317 GRBM_SOFT_RESET, SOFT_RESET_CP, 7318 1); 7319 } 7320 7321 /* GRBM_STATUS2 */ 7322 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7323 switch (adev->asic_type) { 7324 case CHIP_SIENNA_CICHLID: 7325 case CHIP_NAVY_FLOUNDER: 7326 case CHIP_VANGOGH: 7327 case CHIP_DIMGREY_CAVEFISH: 7328 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7329 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7330 GRBM_SOFT_RESET, 7331 SOFT_RESET_RLC, 7332 1); 7333 break; 7334 default: 7335 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7336 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7337 GRBM_SOFT_RESET, 7338 SOFT_RESET_RLC, 7339 1); 7340 break; 7341 } 7342 7343 if (grbm_soft_reset) { 7344 /* stop the rlc */ 7345 gfx_v10_0_rlc_stop(adev); 7346 7347 /* Disable GFX parsing/prefetching */ 7348 gfx_v10_0_cp_gfx_enable(adev, false); 7349 7350 /* Disable MEC parsing/prefetching */ 7351 gfx_v10_0_cp_compute_enable(adev, false); 7352 7353 if (grbm_soft_reset) { 7354 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7355 tmp |= grbm_soft_reset; 7356 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7357 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7358 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7359 7360 udelay(50); 7361 7362 tmp &= ~grbm_soft_reset; 7363 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7364 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7365 } 7366 7367 /* Wait a little for things to settle down */ 7368 udelay(50); 7369 } 7370 return 0; 7371 } 7372 7373 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7374 { 7375 uint64_t clock; 7376 7377 amdgpu_gfx_off_ctrl(adev, false); 7378 mutex_lock(&adev->gfx.gpu_clock_mutex); 7379 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 7380 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 7381 mutex_unlock(&adev->gfx.gpu_clock_mutex); 7382 amdgpu_gfx_off_ctrl(adev, true); 7383 return clock; 7384 } 7385 7386 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7387 uint32_t vmid, 7388 uint32_t gds_base, uint32_t gds_size, 7389 uint32_t gws_base, uint32_t gws_size, 7390 uint32_t oa_base, uint32_t oa_size) 7391 { 7392 struct amdgpu_device *adev = ring->adev; 7393 7394 /* GDS Base */ 7395 gfx_v10_0_write_data_to_reg(ring, 0, false, 7396 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7397 gds_base); 7398 7399 /* GDS Size */ 7400 gfx_v10_0_write_data_to_reg(ring, 0, false, 7401 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7402 gds_size); 7403 7404 /* GWS */ 7405 gfx_v10_0_write_data_to_reg(ring, 0, false, 7406 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7407 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7408 7409 /* OA */ 7410 gfx_v10_0_write_data_to_reg(ring, 0, false, 7411 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7412 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7413 } 7414 7415 static int gfx_v10_0_early_init(void *handle) 7416 { 7417 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7418 7419 switch (adev->asic_type) { 7420 case CHIP_NAVI10: 7421 case CHIP_NAVI14: 7422 case CHIP_NAVI12: 7423 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7424 break; 7425 case CHIP_SIENNA_CICHLID: 7426 case CHIP_NAVY_FLOUNDER: 7427 case CHIP_VANGOGH: 7428 case CHIP_DIMGREY_CAVEFISH: 7429 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7430 break; 7431 default: 7432 break; 7433 } 7434 7435 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7436 AMDGPU_MAX_COMPUTE_RINGS); 7437 7438 gfx_v10_0_set_kiq_pm4_funcs(adev); 7439 gfx_v10_0_set_ring_funcs(adev); 7440 gfx_v10_0_set_irq_funcs(adev); 7441 gfx_v10_0_set_gds_init(adev); 7442 gfx_v10_0_set_rlc_funcs(adev); 7443 7444 return 0; 7445 } 7446 7447 static int gfx_v10_0_late_init(void *handle) 7448 { 7449 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7450 int r; 7451 7452 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7453 if (r) 7454 return r; 7455 7456 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7457 if (r) 7458 return r; 7459 7460 return 0; 7461 } 7462 7463 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7464 { 7465 uint32_t rlc_cntl; 7466 7467 /* if RLC is not enabled, do nothing */ 7468 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7469 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7470 } 7471 7472 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7473 { 7474 uint32_t data; 7475 unsigned i; 7476 7477 data = RLC_SAFE_MODE__CMD_MASK; 7478 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7479 7480 switch (adev->asic_type) { 7481 case CHIP_SIENNA_CICHLID: 7482 case CHIP_NAVY_FLOUNDER: 7483 case CHIP_VANGOGH: 7484 case CHIP_DIMGREY_CAVEFISH: 7485 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7486 7487 /* wait for RLC_SAFE_MODE */ 7488 for (i = 0; i < adev->usec_timeout; i++) { 7489 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7490 RLC_SAFE_MODE, CMD)) 7491 break; 7492 udelay(1); 7493 } 7494 break; 7495 default: 7496 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7497 7498 /* wait for RLC_SAFE_MODE */ 7499 for (i = 0; i < adev->usec_timeout; i++) { 7500 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7501 RLC_SAFE_MODE, CMD)) 7502 break; 7503 udelay(1); 7504 } 7505 break; 7506 } 7507 } 7508 7509 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7510 { 7511 uint32_t data; 7512 7513 data = RLC_SAFE_MODE__CMD_MASK; 7514 switch (adev->asic_type) { 7515 case CHIP_SIENNA_CICHLID: 7516 case CHIP_NAVY_FLOUNDER: 7517 case CHIP_VANGOGH: 7518 case CHIP_DIMGREY_CAVEFISH: 7519 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7520 break; 7521 default: 7522 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7523 break; 7524 } 7525 } 7526 7527 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7528 bool enable) 7529 { 7530 uint32_t data, def; 7531 7532 /* It is disabled by HW by default */ 7533 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7534 /* 0 - Disable some blocks' MGCG */ 7535 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7536 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7537 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7538 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7539 7540 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7541 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7542 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7543 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7544 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7545 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7546 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7547 7548 if (def != data) 7549 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7550 7551 /* MGLS is a global flag to control all MGLS in GFX */ 7552 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7553 /* 2 - RLC memory Light sleep */ 7554 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7555 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7556 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7557 if (def != data) 7558 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7559 } 7560 /* 3 - CP memory Light sleep */ 7561 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7562 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7563 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7564 if (def != data) 7565 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7566 } 7567 } 7568 } else { 7569 /* 1 - MGCG_OVERRIDE */ 7570 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7571 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7572 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7573 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7574 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 7575 if (def != data) 7576 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7577 7578 /* 2 - disable MGLS in CP */ 7579 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7580 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7581 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7582 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7583 } 7584 7585 /* 3 - disable MGLS in RLC */ 7586 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7587 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7588 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7589 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7590 } 7591 7592 } 7593 } 7594 7595 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7596 bool enable) 7597 { 7598 uint32_t data, def; 7599 7600 /* Enable 3D CGCG/CGLS */ 7601 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 7602 /* write cmd to clear cgcg/cgls ov */ 7603 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7604 /* unset CGCG override */ 7605 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7606 /* update CGCG and CGLS override bits */ 7607 if (def != data) 7608 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7609 /* enable 3Dcgcg FSM(0x0000363f) */ 7610 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7611 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7612 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7613 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7614 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7615 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7616 if (def != data) 7617 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7618 7619 /* set IDLE_POLL_COUNT(0x00900100) */ 7620 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7621 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7622 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7623 if (def != data) 7624 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7625 } else { 7626 /* Disable CGCG/CGLS */ 7627 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7628 /* disable cgcg, cgls should be disabled */ 7629 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 7630 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 7631 /* disable cgcg and cgls in FSM */ 7632 if (def != data) 7633 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7634 } 7635 } 7636 7637 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7638 bool enable) 7639 { 7640 uint32_t def, data; 7641 7642 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 7643 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7644 /* unset CGCG override */ 7645 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7646 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7647 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7648 else 7649 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7650 /* update CGCG and CGLS override bits */ 7651 if (def != data) 7652 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7653 7654 /* enable cgcg FSM(0x0000363F) */ 7655 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7656 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7657 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7658 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7659 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7660 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7661 if (def != data) 7662 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7663 7664 /* set IDLE_POLL_COUNT(0x00900100) */ 7665 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7666 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7667 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7668 if (def != data) 7669 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7670 } else { 7671 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7672 /* reset CGCG/CGLS bits */ 7673 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 7674 /* disable cgcg and cgls in FSM */ 7675 if (def != data) 7676 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7677 } 7678 } 7679 7680 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7681 bool enable) 7682 { 7683 uint32_t def, data; 7684 7685 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) { 7686 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7687 /* unset FGCG override */ 7688 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7689 /* update FGCG override bits */ 7690 if (def != data) 7691 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7692 7693 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7694 /* unset RLC SRAM CLK GATER override */ 7695 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7696 /* update RLC SRAM CLK GATER override bits */ 7697 if (def != data) 7698 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7699 } else { 7700 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7701 /* reset FGCG bits */ 7702 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7703 /* disable FGCG*/ 7704 if (def != data) 7705 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7706 7707 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7708 /* reset RLC SRAM CLK GATER bits */ 7709 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7710 /* disable RLC SRAM CLK*/ 7711 if (def != data) 7712 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7713 } 7714 } 7715 7716 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7717 bool enable) 7718 { 7719 amdgpu_gfx_rlc_enter_safe_mode(adev); 7720 7721 if (enable) { 7722 /* enable FGCG firstly*/ 7723 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7724 /* CGCG/CGLS should be enabled after MGCG/MGLS 7725 * === MGCG + MGLS === 7726 */ 7727 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7728 /* === CGCG /CGLS for GFX 3D Only === */ 7729 gfx_v10_0_update_3d_clock_gating(adev, enable); 7730 /* === CGCG + CGLS === */ 7731 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7732 } else { 7733 /* CGCG/CGLS should be disabled before MGCG/MGLS 7734 * === CGCG + CGLS === 7735 */ 7736 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7737 /* === CGCG /CGLS for GFX 3D Only === */ 7738 gfx_v10_0_update_3d_clock_gating(adev, enable); 7739 /* === MGCG + MGLS === */ 7740 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7741 /* disable fgcg at last*/ 7742 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7743 } 7744 7745 if (adev->cg_flags & 7746 (AMD_CG_SUPPORT_GFX_MGCG | 7747 AMD_CG_SUPPORT_GFX_CGLS | 7748 AMD_CG_SUPPORT_GFX_CGCG | 7749 AMD_CG_SUPPORT_GFX_3D_CGCG | 7750 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7751 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7752 7753 amdgpu_gfx_rlc_exit_safe_mode(adev); 7754 7755 return 0; 7756 } 7757 7758 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 7759 { 7760 u32 reg, data; 7761 7762 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7763 if (amdgpu_sriov_is_pp_one_vf(adev)) 7764 data = RREG32_NO_KIQ(reg); 7765 else 7766 data = RREG32(reg); 7767 7768 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7769 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7770 7771 if (amdgpu_sriov_is_pp_one_vf(adev)) 7772 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7773 else 7774 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7775 } 7776 7777 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7778 uint32_t offset, 7779 struct soc15_reg_rlcg *entries, int arr_size) 7780 { 7781 int i; 7782 uint32_t reg; 7783 7784 if (!entries) 7785 return false; 7786 7787 for (i = 0; i < arr_size; i++) { 7788 const struct soc15_reg_rlcg *entry; 7789 7790 entry = &entries[i]; 7791 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7792 if (offset == reg) 7793 return true; 7794 } 7795 7796 return false; 7797 } 7798 7799 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7800 { 7801 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7802 } 7803 7804 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7805 { 7806 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7807 7808 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7809 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7810 else 7811 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7812 7813 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7814 } 7815 7816 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7817 { 7818 amdgpu_gfx_rlc_enter_safe_mode(adev); 7819 7820 gfx_v10_cntl_power_gating(adev, enable); 7821 7822 amdgpu_gfx_rlc_exit_safe_mode(adev); 7823 } 7824 7825 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 7826 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7827 .set_safe_mode = gfx_v10_0_set_safe_mode, 7828 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7829 .init = gfx_v10_0_rlc_init, 7830 .get_csb_size = gfx_v10_0_get_csb_size, 7831 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7832 .resume = gfx_v10_0_rlc_resume, 7833 .stop = gfx_v10_0_rlc_stop, 7834 .reset = gfx_v10_0_rlc_reset, 7835 .start = gfx_v10_0_rlc_start, 7836 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7837 }; 7838 7839 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 7840 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7841 .set_safe_mode = gfx_v10_0_set_safe_mode, 7842 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7843 .init = gfx_v10_0_rlc_init, 7844 .get_csb_size = gfx_v10_0_get_csb_size, 7845 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7846 .resume = gfx_v10_0_rlc_resume, 7847 .stop = gfx_v10_0_rlc_stop, 7848 .reset = gfx_v10_0_rlc_reset, 7849 .start = gfx_v10_0_rlc_start, 7850 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7851 .rlcg_wreg = gfx_v10_rlcg_wreg, 7852 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 7853 }; 7854 7855 static int gfx_v10_0_set_powergating_state(void *handle, 7856 enum amd_powergating_state state) 7857 { 7858 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7859 bool enable = (state == AMD_PG_STATE_GATE); 7860 7861 if (amdgpu_sriov_vf(adev)) 7862 return 0; 7863 7864 switch (adev->asic_type) { 7865 case CHIP_NAVI10: 7866 case CHIP_NAVI14: 7867 case CHIP_NAVI12: 7868 case CHIP_SIENNA_CICHLID: 7869 case CHIP_NAVY_FLOUNDER: 7870 case CHIP_DIMGREY_CAVEFISH: 7871 amdgpu_gfx_off_ctrl(adev, enable); 7872 break; 7873 case CHIP_VANGOGH: 7874 gfx_v10_cntl_pg(adev, enable); 7875 break; 7876 default: 7877 break; 7878 } 7879 return 0; 7880 } 7881 7882 static int gfx_v10_0_set_clockgating_state(void *handle, 7883 enum amd_clockgating_state state) 7884 { 7885 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7886 7887 if (amdgpu_sriov_vf(adev)) 7888 return 0; 7889 7890 switch (adev->asic_type) { 7891 case CHIP_NAVI10: 7892 case CHIP_NAVI14: 7893 case CHIP_NAVI12: 7894 case CHIP_SIENNA_CICHLID: 7895 case CHIP_NAVY_FLOUNDER: 7896 case CHIP_VANGOGH: 7897 case CHIP_DIMGREY_CAVEFISH: 7898 gfx_v10_0_update_gfx_clock_gating(adev, 7899 state == AMD_CG_STATE_GATE); 7900 break; 7901 default: 7902 break; 7903 } 7904 return 0; 7905 } 7906 7907 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 7908 { 7909 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7910 int data; 7911 7912 /* AMD_CG_SUPPORT_GFX_FGCG */ 7913 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7914 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 7915 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 7916 7917 /* AMD_CG_SUPPORT_GFX_MGCG */ 7918 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7919 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 7920 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 7921 7922 /* AMD_CG_SUPPORT_GFX_CGCG */ 7923 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 7924 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 7925 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 7926 7927 /* AMD_CG_SUPPORT_GFX_CGLS */ 7928 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 7929 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 7930 7931 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 7932 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 7933 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 7934 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 7935 7936 /* AMD_CG_SUPPORT_GFX_CP_LS */ 7937 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 7938 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 7939 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 7940 7941 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 7942 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 7943 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 7944 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 7945 7946 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 7947 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 7948 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 7949 } 7950 7951 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 7952 { 7953 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 7954 } 7955 7956 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 7957 { 7958 struct amdgpu_device *adev = ring->adev; 7959 u64 wptr; 7960 7961 /* XXX check if swapping is necessary on BE */ 7962 if (ring->use_doorbell) { 7963 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 7964 } else { 7965 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 7966 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 7967 } 7968 7969 return wptr; 7970 } 7971 7972 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 7973 { 7974 struct amdgpu_device *adev = ring->adev; 7975 7976 if (ring->use_doorbell) { 7977 /* XXX check if swapping is necessary on BE */ 7978 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 7979 WDOORBELL64(ring->doorbell_index, ring->wptr); 7980 } else { 7981 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 7982 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 7983 } 7984 } 7985 7986 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 7987 { 7988 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 7989 } 7990 7991 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 7992 { 7993 u64 wptr; 7994 7995 /* XXX check if swapping is necessary on BE */ 7996 if (ring->use_doorbell) 7997 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 7998 else 7999 BUG(); 8000 return wptr; 8001 } 8002 8003 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8004 { 8005 struct amdgpu_device *adev = ring->adev; 8006 8007 /* XXX check if swapping is necessary on BE */ 8008 if (ring->use_doorbell) { 8009 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8010 WDOORBELL64(ring->doorbell_index, ring->wptr); 8011 } else { 8012 BUG(); /* only DOORBELL method supported on gfx10 now */ 8013 } 8014 } 8015 8016 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8017 { 8018 struct amdgpu_device *adev = ring->adev; 8019 u32 ref_and_mask, reg_mem_engine; 8020 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8021 8022 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8023 switch (ring->me) { 8024 case 1: 8025 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8026 break; 8027 case 2: 8028 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8029 break; 8030 default: 8031 return; 8032 } 8033 reg_mem_engine = 0; 8034 } else { 8035 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8036 reg_mem_engine = 1; /* pfp */ 8037 } 8038 8039 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8040 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8041 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8042 ref_and_mask, ref_and_mask, 0x20); 8043 } 8044 8045 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8046 struct amdgpu_job *job, 8047 struct amdgpu_ib *ib, 8048 uint32_t flags) 8049 { 8050 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8051 u32 header, control = 0; 8052 8053 if (ib->flags & AMDGPU_IB_FLAG_CE) 8054 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8055 else 8056 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8057 8058 control |= ib->length_dw | (vmid << 24); 8059 8060 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8061 control |= INDIRECT_BUFFER_PRE_ENB(1); 8062 8063 if (flags & AMDGPU_IB_PREEMPTED) 8064 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8065 8066 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8067 gfx_v10_0_ring_emit_de_meta(ring, 8068 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8069 } 8070 8071 amdgpu_ring_write(ring, header); 8072 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8073 amdgpu_ring_write(ring, 8074 #ifdef __BIG_ENDIAN 8075 (2 << 0) | 8076 #endif 8077 lower_32_bits(ib->gpu_addr)); 8078 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8079 amdgpu_ring_write(ring, control); 8080 } 8081 8082 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8083 struct amdgpu_job *job, 8084 struct amdgpu_ib *ib, 8085 uint32_t flags) 8086 { 8087 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8088 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8089 8090 /* Currently, there is a high possibility to get wave ID mismatch 8091 * between ME and GDS, leading to a hw deadlock, because ME generates 8092 * different wave IDs than the GDS expects. This situation happens 8093 * randomly when at least 5 compute pipes use GDS ordered append. 8094 * The wave IDs generated by ME are also wrong after suspend/resume. 8095 * Those are probably bugs somewhere else in the kernel driver. 8096 * 8097 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8098 * GDS to 0 for this ring (me/pipe). 8099 */ 8100 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8101 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8102 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8103 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8104 } 8105 8106 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8107 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8108 amdgpu_ring_write(ring, 8109 #ifdef __BIG_ENDIAN 8110 (2 << 0) | 8111 #endif 8112 lower_32_bits(ib->gpu_addr)); 8113 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8114 amdgpu_ring_write(ring, control); 8115 } 8116 8117 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8118 u64 seq, unsigned flags) 8119 { 8120 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8121 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8122 8123 /* RELEASE_MEM - flush caches, send int */ 8124 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8125 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8126 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8127 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8128 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8129 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8130 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8131 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8132 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8133 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8134 8135 /* 8136 * the address should be Qword aligned if 64bit write, Dword 8137 * aligned if only send 32bit data low (discard data high) 8138 */ 8139 if (write64bit) 8140 BUG_ON(addr & 0x7); 8141 else 8142 BUG_ON(addr & 0x3); 8143 amdgpu_ring_write(ring, lower_32_bits(addr)); 8144 amdgpu_ring_write(ring, upper_32_bits(addr)); 8145 amdgpu_ring_write(ring, lower_32_bits(seq)); 8146 amdgpu_ring_write(ring, upper_32_bits(seq)); 8147 amdgpu_ring_write(ring, 0); 8148 } 8149 8150 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8151 { 8152 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8153 uint32_t seq = ring->fence_drv.sync_seq; 8154 uint64_t addr = ring->fence_drv.gpu_addr; 8155 8156 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8157 upper_32_bits(addr), seq, 0xffffffff, 4); 8158 } 8159 8160 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8161 unsigned vmid, uint64_t pd_addr) 8162 { 8163 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8164 8165 /* compute doesn't have PFP */ 8166 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8167 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8168 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8169 amdgpu_ring_write(ring, 0x0); 8170 } 8171 } 8172 8173 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8174 u64 seq, unsigned int flags) 8175 { 8176 struct amdgpu_device *adev = ring->adev; 8177 8178 /* we only allocate 32bit for each seq wb address */ 8179 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8180 8181 /* write fence seq to the "addr" */ 8182 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8183 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8184 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8185 amdgpu_ring_write(ring, lower_32_bits(addr)); 8186 amdgpu_ring_write(ring, upper_32_bits(addr)); 8187 amdgpu_ring_write(ring, lower_32_bits(seq)); 8188 8189 if (flags & AMDGPU_FENCE_FLAG_INT) { 8190 /* set register to trigger INT */ 8191 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8192 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8193 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8194 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8195 amdgpu_ring_write(ring, 0); 8196 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8197 } 8198 } 8199 8200 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8201 { 8202 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8203 amdgpu_ring_write(ring, 0); 8204 } 8205 8206 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8207 uint32_t flags) 8208 { 8209 uint32_t dw2 = 0; 8210 8211 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8212 gfx_v10_0_ring_emit_ce_meta(ring, 8213 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8214 8215 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8216 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8217 /* set load_global_config & load_global_uconfig */ 8218 dw2 |= 0x8001; 8219 /* set load_cs_sh_regs */ 8220 dw2 |= 0x01000000; 8221 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8222 dw2 |= 0x10002; 8223 8224 /* set load_ce_ram if preamble presented */ 8225 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8226 dw2 |= 0x10000000; 8227 } else { 8228 /* still load_ce_ram if this is the first time preamble presented 8229 * although there is no context switch happens. 8230 */ 8231 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8232 dw2 |= 0x10000000; 8233 } 8234 8235 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8236 amdgpu_ring_write(ring, dw2); 8237 amdgpu_ring_write(ring, 0); 8238 } 8239 8240 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8241 { 8242 unsigned ret; 8243 8244 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8245 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8246 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8247 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8248 ret = ring->wptr & ring->buf_mask; 8249 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8250 8251 return ret; 8252 } 8253 8254 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8255 { 8256 unsigned cur; 8257 BUG_ON(offset > ring->buf_mask); 8258 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8259 8260 cur = (ring->wptr - 1) & ring->buf_mask; 8261 if (likely(cur > offset)) 8262 ring->ring[offset] = cur - offset; 8263 else 8264 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8265 } 8266 8267 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8268 { 8269 int i, r = 0; 8270 struct amdgpu_device *adev = ring->adev; 8271 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8272 struct amdgpu_ring *kiq_ring = &kiq->ring; 8273 unsigned long flags; 8274 8275 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8276 return -EINVAL; 8277 8278 spin_lock_irqsave(&kiq->ring_lock, flags); 8279 8280 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8281 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8282 return -ENOMEM; 8283 } 8284 8285 /* assert preemption condition */ 8286 amdgpu_ring_set_preempt_cond_exec(ring, false); 8287 8288 /* assert IB preemption, emit the trailing fence */ 8289 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8290 ring->trail_fence_gpu_addr, 8291 ++ring->trail_seq); 8292 amdgpu_ring_commit(kiq_ring); 8293 8294 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8295 8296 /* poll the trailing fence */ 8297 for (i = 0; i < adev->usec_timeout; i++) { 8298 if (ring->trail_seq == 8299 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8300 break; 8301 udelay(1); 8302 } 8303 8304 if (i >= adev->usec_timeout) { 8305 r = -EINVAL; 8306 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8307 } 8308 8309 /* deassert preemption condition */ 8310 amdgpu_ring_set_preempt_cond_exec(ring, true); 8311 return r; 8312 } 8313 8314 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8315 { 8316 struct amdgpu_device *adev = ring->adev; 8317 struct v10_ce_ib_state ce_payload = {0}; 8318 uint64_t csa_addr; 8319 int cnt; 8320 8321 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8322 csa_addr = amdgpu_csa_vaddr(ring->adev); 8323 8324 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8325 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8326 WRITE_DATA_DST_SEL(8) | 8327 WR_CONFIRM) | 8328 WRITE_DATA_CACHE_POLICY(0)); 8329 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8330 offsetof(struct v10_gfx_meta_data, ce_payload))); 8331 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8332 offsetof(struct v10_gfx_meta_data, ce_payload))); 8333 8334 if (resume) 8335 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8336 offsetof(struct v10_gfx_meta_data, 8337 ce_payload), 8338 sizeof(ce_payload) >> 2); 8339 else 8340 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8341 sizeof(ce_payload) >> 2); 8342 } 8343 8344 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8345 { 8346 struct amdgpu_device *adev = ring->adev; 8347 struct v10_de_ib_state de_payload = {0}; 8348 uint64_t csa_addr, gds_addr; 8349 int cnt; 8350 8351 csa_addr = amdgpu_csa_vaddr(ring->adev); 8352 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8353 PAGE_SIZE); 8354 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8355 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8356 8357 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8358 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8359 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8360 WRITE_DATA_DST_SEL(8) | 8361 WR_CONFIRM) | 8362 WRITE_DATA_CACHE_POLICY(0)); 8363 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8364 offsetof(struct v10_gfx_meta_data, de_payload))); 8365 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8366 offsetof(struct v10_gfx_meta_data, de_payload))); 8367 8368 if (resume) 8369 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8370 offsetof(struct v10_gfx_meta_data, 8371 de_payload), 8372 sizeof(de_payload) >> 2); 8373 else 8374 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8375 sizeof(de_payload) >> 2); 8376 } 8377 8378 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8379 bool secure) 8380 { 8381 uint32_t v = secure ? FRAME_TMZ : 0; 8382 8383 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8384 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8385 } 8386 8387 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8388 uint32_t reg_val_offs) 8389 { 8390 struct amdgpu_device *adev = ring->adev; 8391 8392 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8393 amdgpu_ring_write(ring, 0 | /* src: register*/ 8394 (5 << 8) | /* dst: memory */ 8395 (1 << 20)); /* write confirm */ 8396 amdgpu_ring_write(ring, reg); 8397 amdgpu_ring_write(ring, 0); 8398 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8399 reg_val_offs * 4)); 8400 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8401 reg_val_offs * 4)); 8402 } 8403 8404 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8405 uint32_t val) 8406 { 8407 uint32_t cmd = 0; 8408 8409 switch (ring->funcs->type) { 8410 case AMDGPU_RING_TYPE_GFX: 8411 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8412 break; 8413 case AMDGPU_RING_TYPE_KIQ: 8414 cmd = (1 << 16); /* no inc addr */ 8415 break; 8416 default: 8417 cmd = WR_CONFIRM; 8418 break; 8419 } 8420 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8421 amdgpu_ring_write(ring, cmd); 8422 amdgpu_ring_write(ring, reg); 8423 amdgpu_ring_write(ring, 0); 8424 amdgpu_ring_write(ring, val); 8425 } 8426 8427 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8428 uint32_t val, uint32_t mask) 8429 { 8430 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8431 } 8432 8433 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8434 uint32_t reg0, uint32_t reg1, 8435 uint32_t ref, uint32_t mask) 8436 { 8437 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8438 struct amdgpu_device *adev = ring->adev; 8439 bool fw_version_ok = false; 8440 8441 fw_version_ok = adev->gfx.cp_fw_write_wait; 8442 8443 if (fw_version_ok) 8444 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8445 ref, mask, 0x20); 8446 else 8447 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8448 ref, mask); 8449 } 8450 8451 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8452 unsigned vmid) 8453 { 8454 struct amdgpu_device *adev = ring->adev; 8455 uint32_t value = 0; 8456 8457 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8458 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8459 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8460 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8461 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8462 } 8463 8464 static void 8465 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8466 uint32_t me, uint32_t pipe, 8467 enum amdgpu_interrupt_state state) 8468 { 8469 uint32_t cp_int_cntl, cp_int_cntl_reg; 8470 8471 if (!me) { 8472 switch (pipe) { 8473 case 0: 8474 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8475 break; 8476 case 1: 8477 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8478 break; 8479 default: 8480 DRM_DEBUG("invalid pipe %d\n", pipe); 8481 return; 8482 } 8483 } else { 8484 DRM_DEBUG("invalid me %d\n", me); 8485 return; 8486 } 8487 8488 switch (state) { 8489 case AMDGPU_IRQ_STATE_DISABLE: 8490 cp_int_cntl = RREG32(cp_int_cntl_reg); 8491 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8492 TIME_STAMP_INT_ENABLE, 0); 8493 WREG32(cp_int_cntl_reg, cp_int_cntl); 8494 break; 8495 case AMDGPU_IRQ_STATE_ENABLE: 8496 cp_int_cntl = RREG32(cp_int_cntl_reg); 8497 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8498 TIME_STAMP_INT_ENABLE, 1); 8499 WREG32(cp_int_cntl_reg, cp_int_cntl); 8500 break; 8501 default: 8502 break; 8503 } 8504 } 8505 8506 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8507 int me, int pipe, 8508 enum amdgpu_interrupt_state state) 8509 { 8510 u32 mec_int_cntl, mec_int_cntl_reg; 8511 8512 /* 8513 * amdgpu controls only the first MEC. That's why this function only 8514 * handles the setting of interrupts for this specific MEC. All other 8515 * pipes' interrupts are set by amdkfd. 8516 */ 8517 8518 if (me == 1) { 8519 switch (pipe) { 8520 case 0: 8521 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8522 break; 8523 case 1: 8524 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8525 break; 8526 case 2: 8527 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8528 break; 8529 case 3: 8530 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8531 break; 8532 default: 8533 DRM_DEBUG("invalid pipe %d\n", pipe); 8534 return; 8535 } 8536 } else { 8537 DRM_DEBUG("invalid me %d\n", me); 8538 return; 8539 } 8540 8541 switch (state) { 8542 case AMDGPU_IRQ_STATE_DISABLE: 8543 mec_int_cntl = RREG32(mec_int_cntl_reg); 8544 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8545 TIME_STAMP_INT_ENABLE, 0); 8546 WREG32(mec_int_cntl_reg, mec_int_cntl); 8547 break; 8548 case AMDGPU_IRQ_STATE_ENABLE: 8549 mec_int_cntl = RREG32(mec_int_cntl_reg); 8550 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8551 TIME_STAMP_INT_ENABLE, 1); 8552 WREG32(mec_int_cntl_reg, mec_int_cntl); 8553 break; 8554 default: 8555 break; 8556 } 8557 } 8558 8559 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8560 struct amdgpu_irq_src *src, 8561 unsigned type, 8562 enum amdgpu_interrupt_state state) 8563 { 8564 switch (type) { 8565 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8566 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8567 break; 8568 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8569 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8570 break; 8571 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8572 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8573 break; 8574 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8575 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8576 break; 8577 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8578 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8579 break; 8580 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8581 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8582 break; 8583 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8584 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8585 break; 8586 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8587 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8588 break; 8589 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8590 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8591 break; 8592 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8593 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8594 break; 8595 default: 8596 break; 8597 } 8598 return 0; 8599 } 8600 8601 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8602 struct amdgpu_irq_src *source, 8603 struct amdgpu_iv_entry *entry) 8604 { 8605 int i; 8606 u8 me_id, pipe_id, queue_id; 8607 struct amdgpu_ring *ring; 8608 8609 DRM_DEBUG("IH: CP EOP\n"); 8610 me_id = (entry->ring_id & 0x0c) >> 2; 8611 pipe_id = (entry->ring_id & 0x03) >> 0; 8612 queue_id = (entry->ring_id & 0x70) >> 4; 8613 8614 switch (me_id) { 8615 case 0: 8616 if (pipe_id == 0) 8617 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8618 else 8619 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8620 break; 8621 case 1: 8622 case 2: 8623 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8624 ring = &adev->gfx.compute_ring[i]; 8625 /* Per-queue interrupt is supported for MEC starting from VI. 8626 * The interrupt can only be enabled/disabled per pipe instead of per queue. 8627 */ 8628 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 8629 amdgpu_fence_process(ring); 8630 } 8631 break; 8632 } 8633 return 0; 8634 } 8635 8636 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8637 struct amdgpu_irq_src *source, 8638 unsigned type, 8639 enum amdgpu_interrupt_state state) 8640 { 8641 switch (state) { 8642 case AMDGPU_IRQ_STATE_DISABLE: 8643 case AMDGPU_IRQ_STATE_ENABLE: 8644 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8645 PRIV_REG_INT_ENABLE, 8646 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8647 break; 8648 default: 8649 break; 8650 } 8651 8652 return 0; 8653 } 8654 8655 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8656 struct amdgpu_irq_src *source, 8657 unsigned type, 8658 enum amdgpu_interrupt_state state) 8659 { 8660 switch (state) { 8661 case AMDGPU_IRQ_STATE_DISABLE: 8662 case AMDGPU_IRQ_STATE_ENABLE: 8663 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8664 PRIV_INSTR_INT_ENABLE, 8665 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8666 break; 8667 default: 8668 break; 8669 } 8670 8671 return 0; 8672 } 8673 8674 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8675 struct amdgpu_iv_entry *entry) 8676 { 8677 u8 me_id, pipe_id, queue_id; 8678 struct amdgpu_ring *ring; 8679 int i; 8680 8681 me_id = (entry->ring_id & 0x0c) >> 2; 8682 pipe_id = (entry->ring_id & 0x03) >> 0; 8683 queue_id = (entry->ring_id & 0x70) >> 4; 8684 8685 switch (me_id) { 8686 case 0: 8687 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 8688 ring = &adev->gfx.gfx_ring[i]; 8689 /* we only enabled 1 gfx queue per pipe for now */ 8690 if (ring->me == me_id && ring->pipe == pipe_id) 8691 drm_sched_fault(&ring->sched); 8692 } 8693 break; 8694 case 1: 8695 case 2: 8696 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8697 ring = &adev->gfx.compute_ring[i]; 8698 if (ring->me == me_id && ring->pipe == pipe_id && 8699 ring->queue == queue_id) 8700 drm_sched_fault(&ring->sched); 8701 } 8702 break; 8703 default: 8704 BUG(); 8705 } 8706 } 8707 8708 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 8709 struct amdgpu_irq_src *source, 8710 struct amdgpu_iv_entry *entry) 8711 { 8712 DRM_ERROR("Illegal register access in command stream\n"); 8713 gfx_v10_0_handle_priv_fault(adev, entry); 8714 return 0; 8715 } 8716 8717 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 8718 struct amdgpu_irq_src *source, 8719 struct amdgpu_iv_entry *entry) 8720 { 8721 DRM_ERROR("Illegal instruction in command stream\n"); 8722 gfx_v10_0_handle_priv_fault(adev, entry); 8723 return 0; 8724 } 8725 8726 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 8727 struct amdgpu_irq_src *src, 8728 unsigned int type, 8729 enum amdgpu_interrupt_state state) 8730 { 8731 uint32_t tmp, target; 8732 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8733 8734 if (ring->me == 1) 8735 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8736 else 8737 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 8738 target += ring->pipe; 8739 8740 switch (type) { 8741 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 8742 if (state == AMDGPU_IRQ_STATE_DISABLE) { 8743 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8744 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8745 GENERIC2_INT_ENABLE, 0); 8746 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8747 8748 tmp = RREG32(target); 8749 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8750 GENERIC2_INT_ENABLE, 0); 8751 WREG32(target, tmp); 8752 } else { 8753 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8754 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8755 GENERIC2_INT_ENABLE, 1); 8756 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8757 8758 tmp = RREG32(target); 8759 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8760 GENERIC2_INT_ENABLE, 1); 8761 WREG32(target, tmp); 8762 } 8763 break; 8764 default: 8765 BUG(); /* kiq only support GENERIC2_INT now */ 8766 break; 8767 } 8768 return 0; 8769 } 8770 8771 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 8772 struct amdgpu_irq_src *source, 8773 struct amdgpu_iv_entry *entry) 8774 { 8775 u8 me_id, pipe_id, queue_id; 8776 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8777 8778 me_id = (entry->ring_id & 0x0c) >> 2; 8779 pipe_id = (entry->ring_id & 0x03) >> 0; 8780 queue_id = (entry->ring_id & 0x70) >> 4; 8781 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 8782 me_id, pipe_id, queue_id); 8783 8784 amdgpu_fence_process(ring); 8785 return 0; 8786 } 8787 8788 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 8789 { 8790 const unsigned int gcr_cntl = 8791 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 8792 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 8793 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 8794 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 8795 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 8796 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 8797 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 8798 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 8799 8800 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 8801 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 8802 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 8803 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 8804 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 8805 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 8806 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 8807 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 8808 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 8809 } 8810 8811 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 8812 .name = "gfx_v10_0", 8813 .early_init = gfx_v10_0_early_init, 8814 .late_init = gfx_v10_0_late_init, 8815 .sw_init = gfx_v10_0_sw_init, 8816 .sw_fini = gfx_v10_0_sw_fini, 8817 .hw_init = gfx_v10_0_hw_init, 8818 .hw_fini = gfx_v10_0_hw_fini, 8819 .suspend = gfx_v10_0_suspend, 8820 .resume = gfx_v10_0_resume, 8821 .is_idle = gfx_v10_0_is_idle, 8822 .wait_for_idle = gfx_v10_0_wait_for_idle, 8823 .soft_reset = gfx_v10_0_soft_reset, 8824 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 8825 .set_powergating_state = gfx_v10_0_set_powergating_state, 8826 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 8827 }; 8828 8829 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 8830 .type = AMDGPU_RING_TYPE_GFX, 8831 .align_mask = 0xff, 8832 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8833 .support_64bit_ptrs = true, 8834 .vmhub = AMDGPU_GFXHUB_0, 8835 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 8836 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 8837 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 8838 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 8839 5 + /* COND_EXEC */ 8840 7 + /* PIPELINE_SYNC */ 8841 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8842 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8843 2 + /* VM_FLUSH */ 8844 8 + /* FENCE for VM_FLUSH */ 8845 20 + /* GDS switch */ 8846 4 + /* double SWITCH_BUFFER, 8847 * the first COND_EXEC jump to the place 8848 * just prior to this double SWITCH_BUFFER 8849 */ 8850 5 + /* COND_EXEC */ 8851 7 + /* HDP_flush */ 8852 4 + /* VGT_flush */ 8853 14 + /* CE_META */ 8854 31 + /* DE_META */ 8855 3 + /* CNTX_CTRL */ 8856 5 + /* HDP_INVL */ 8857 8 + 8 + /* FENCE x2 */ 8858 2 + /* SWITCH_BUFFER */ 8859 8, /* gfx_v10_0_emit_mem_sync */ 8860 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 8861 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 8862 .emit_fence = gfx_v10_0_ring_emit_fence, 8863 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8864 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8865 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8866 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8867 .test_ring = gfx_v10_0_ring_test_ring, 8868 .test_ib = gfx_v10_0_ring_test_ib, 8869 .insert_nop = amdgpu_ring_insert_nop, 8870 .pad_ib = amdgpu_ring_generic_pad_ib, 8871 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 8872 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 8873 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 8874 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 8875 .preempt_ib = gfx_v10_0_ring_preempt_ib, 8876 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 8877 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8878 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8879 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8880 .soft_recovery = gfx_v10_0_ring_soft_recovery, 8881 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8882 }; 8883 8884 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 8885 .type = AMDGPU_RING_TYPE_COMPUTE, 8886 .align_mask = 0xff, 8887 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8888 .support_64bit_ptrs = true, 8889 .vmhub = AMDGPU_GFXHUB_0, 8890 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8891 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8892 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8893 .emit_frame_size = 8894 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8895 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8896 5 + /* hdp invalidate */ 8897 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8898 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8899 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8900 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8901 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 8902 8, /* gfx_v10_0_emit_mem_sync */ 8903 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8904 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8905 .emit_fence = gfx_v10_0_ring_emit_fence, 8906 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8907 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8908 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8909 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8910 .test_ring = gfx_v10_0_ring_test_ring, 8911 .test_ib = gfx_v10_0_ring_test_ib, 8912 .insert_nop = amdgpu_ring_insert_nop, 8913 .pad_ib = amdgpu_ring_generic_pad_ib, 8914 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8915 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8916 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8917 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8918 }; 8919 8920 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 8921 .type = AMDGPU_RING_TYPE_KIQ, 8922 .align_mask = 0xff, 8923 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8924 .support_64bit_ptrs = true, 8925 .vmhub = AMDGPU_GFXHUB_0, 8926 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8927 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8928 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8929 .emit_frame_size = 8930 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8931 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8932 5 + /*hdp invalidate */ 8933 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8934 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8935 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8936 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8937 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 8938 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8939 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8940 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 8941 .test_ring = gfx_v10_0_ring_test_ring, 8942 .test_ib = gfx_v10_0_ring_test_ib, 8943 .insert_nop = amdgpu_ring_insert_nop, 8944 .pad_ib = amdgpu_ring_generic_pad_ib, 8945 .emit_rreg = gfx_v10_0_ring_emit_rreg, 8946 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8947 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8948 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8949 }; 8950 8951 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 8952 { 8953 int i; 8954 8955 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 8956 8957 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 8958 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 8959 8960 for (i = 0; i < adev->gfx.num_compute_rings; i++) 8961 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 8962 } 8963 8964 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 8965 .set = gfx_v10_0_set_eop_interrupt_state, 8966 .process = gfx_v10_0_eop_irq, 8967 }; 8968 8969 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 8970 .set = gfx_v10_0_set_priv_reg_fault_state, 8971 .process = gfx_v10_0_priv_reg_irq, 8972 }; 8973 8974 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 8975 .set = gfx_v10_0_set_priv_inst_fault_state, 8976 .process = gfx_v10_0_priv_inst_irq, 8977 }; 8978 8979 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 8980 .set = gfx_v10_0_kiq_set_interrupt_state, 8981 .process = gfx_v10_0_kiq_irq, 8982 }; 8983 8984 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 8985 { 8986 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 8987 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 8988 8989 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 8990 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 8991 8992 adev->gfx.priv_reg_irq.num_types = 1; 8993 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 8994 8995 adev->gfx.priv_inst_irq.num_types = 1; 8996 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 8997 } 8998 8999 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9000 { 9001 switch (adev->asic_type) { 9002 case CHIP_NAVI10: 9003 case CHIP_NAVI14: 9004 case CHIP_SIENNA_CICHLID: 9005 case CHIP_NAVY_FLOUNDER: 9006 case CHIP_VANGOGH: 9007 case CHIP_DIMGREY_CAVEFISH: 9008 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9009 break; 9010 case CHIP_NAVI12: 9011 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9012 break; 9013 default: 9014 break; 9015 } 9016 } 9017 9018 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9019 { 9020 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9021 adev->gfx.config.max_sh_per_se * 9022 adev->gfx.config.max_shader_engines; 9023 9024 adev->gds.gds_size = 0x10000; 9025 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9026 adev->gds.gws_size = 64; 9027 adev->gds.oa_size = 16; 9028 } 9029 9030 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9031 u32 bitmap) 9032 { 9033 u32 data; 9034 9035 if (!bitmap) 9036 return; 9037 9038 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9039 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9040 9041 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9042 } 9043 9044 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9045 { 9046 u32 data, wgp_bitmask; 9047 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9048 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9049 9050 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9051 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9052 9053 wgp_bitmask = 9054 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9055 9056 return (~data) & wgp_bitmask; 9057 } 9058 9059 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9060 { 9061 u32 wgp_idx, wgp_active_bitmap; 9062 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9063 9064 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9065 cu_active_bitmap = 0; 9066 9067 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9068 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9069 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9070 if (wgp_active_bitmap & (1 << wgp_idx)) 9071 cu_active_bitmap |= cu_bitmap_per_wgp; 9072 } 9073 9074 return cu_active_bitmap; 9075 } 9076 9077 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9078 struct amdgpu_cu_info *cu_info) 9079 { 9080 int i, j, k, counter, active_cu_number = 0; 9081 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9082 unsigned disable_masks[4 * 2]; 9083 9084 if (!adev || !cu_info) 9085 return -EINVAL; 9086 9087 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9088 9089 mutex_lock(&adev->grbm_idx_mutex); 9090 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9091 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9092 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9093 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 9094 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9095 continue; 9096 mask = 1; 9097 ao_bitmap = 0; 9098 counter = 0; 9099 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9100 if (i < 4 && j < 2) 9101 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9102 adev, disable_masks[i * 2 + j]); 9103 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9104 cu_info->bitmap[i][j] = bitmap; 9105 9106 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9107 if (bitmap & mask) { 9108 if (counter < adev->gfx.config.max_cu_per_sh) 9109 ao_bitmap |= mask; 9110 counter++; 9111 } 9112 mask <<= 1; 9113 } 9114 active_cu_number += counter; 9115 if (i < 2 && j < 2) 9116 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9117 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9118 } 9119 } 9120 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9121 mutex_unlock(&adev->grbm_idx_mutex); 9122 9123 cu_info->number = active_cu_number; 9124 cu_info->ao_cu_mask = ao_cu_mask; 9125 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9126 9127 return 0; 9128 } 9129 9130 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9131 { 9132 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9133 9134 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9135 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9136 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9137 9138 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9139 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9140 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9141 9142 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9143 adev->gfx.config.max_shader_engines); 9144 disabled_sa = efuse_setting | vbios_setting; 9145 disabled_sa &= max_sa_mask; 9146 9147 return disabled_sa; 9148 } 9149 9150 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9151 { 9152 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9153 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9154 9155 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9156 9157 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9158 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9159 max_shader_engines = adev->gfx.config.max_shader_engines; 9160 9161 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9162 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9163 disabled_sa_per_se &= max_sa_per_se_mask; 9164 if (disabled_sa_per_se == max_sa_per_se_mask) { 9165 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9166 break; 9167 } 9168 } 9169 } 9170 9171 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9172 { 9173 .type = AMD_IP_BLOCK_TYPE_GFX, 9174 .major = 10, 9175 .minor = 0, 9176 .rev = 0, 9177 .funcs = &gfx_v10_0_ip_funcs, 9178 }; 9179