xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (revision 817396dc9f6ab2481b94071de2e586aae876e89c)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_smu.h"
33 #include "nv.h"
34 #include "nvd.h"
35 
36 #include "gc/gc_10_1_0_offset.h"
37 #include "gc/gc_10_1_0_sh_mask.h"
38 #include "navi10_enum.h"
39 #include "hdp/hdp_5_0_0_offset.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41 
42 #include "soc15.h"
43 #include "soc15_common.h"
44 #include "clearstate_gfx10.h"
45 #include "v10_structs.h"
46 #include "gfx_v10_0.h"
47 #include "nbio_v2_3.h"
48 
49 /**
50  * Navi10 has two graphic rings to share each graphic pipe.
51  * 1. Primary ring
52  * 2. Async ring
53  */
54 #define GFX10_NUM_GFX_RINGS	2
55 #define GFX10_MEC_HPD_SIZE	2048
56 
57 #define F32_CE_PROGRAM_RAM_SIZE		65536
58 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
59 
60 #define mmCGTT_GS_NGG_CLK_CTRL	0x5087
61 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
62 
63 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
64 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
65 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
66 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
67 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
68 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
69 
70 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
71 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
72 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
73 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
74 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
75 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
76 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
77 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
78 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
79 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
80 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
81 
82 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
83 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
84 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
85 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
86 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
87 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
88 
89 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
90 {
91 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
92 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
93 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
94 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
95 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
96 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
97 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
98 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
99 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070104),
124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
131 };
132 
133 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
134 {
135 	/* Pending on emulation bring up */
136 };
137 
138 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
139 {
140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070105),
172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
178 };
179 
180 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
181 {
182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
222 };
223 
224 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
225 {
226 	/* Pending on emulation bring up */
227 };
228 
229 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
230 {
231 	/* Pending on emulation bring up */
232 };
233 
234 #define DEFAULT_SH_MEM_CONFIG \
235 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
236 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
237 	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
238 	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
239 
240 
241 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
242 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
243 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
244 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
245 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
246                                  struct amdgpu_cu_info *cu_info);
247 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
248 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
249 				   u32 sh_num, u32 instance);
250 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
251 
252 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
253 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
254 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
255 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
256 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
257 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
258 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
259 
260 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
261 {
262 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
263 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
264 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
265 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
266 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
267 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
268 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
269 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
270 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
271 }
272 
273 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
274 				 struct amdgpu_ring *ring)
275 {
276 	struct amdgpu_device *adev = kiq_ring->adev;
277 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
278 	uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
279 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
280 
281 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
282 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
283 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
284 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
285 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
286 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
287 			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
288 			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
289 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
290 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
291 			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
292 			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
293 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
294 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
295 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
296 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
297 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
298 }
299 
300 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
301 				   struct amdgpu_ring *ring,
302 				   enum amdgpu_unmap_queues_action action,
303 				   u64 gpu_addr, u64 seq)
304 {
305 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
306 
307 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
308 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
309 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
310 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
311 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
312 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
313 	amdgpu_ring_write(kiq_ring,
314 		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
315 
316 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
317 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
318 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
319 		amdgpu_ring_write(kiq_ring, seq);
320 	} else {
321 		amdgpu_ring_write(kiq_ring, 0);
322 		amdgpu_ring_write(kiq_ring, 0);
323 		amdgpu_ring_write(kiq_ring, 0);
324 	}
325 }
326 
327 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
328 				   struct amdgpu_ring *ring,
329 				   u64 addr,
330 				   u64 seq)
331 {
332 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
333 
334 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
335 	amdgpu_ring_write(kiq_ring,
336 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
337 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
338 			  PACKET3_QUERY_STATUS_COMMAND(2));
339 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
340 			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
341 			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
342 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
343 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
344 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
345 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
346 }
347 
348 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
349 	.kiq_set_resources = gfx10_kiq_set_resources,
350 	.kiq_map_queues = gfx10_kiq_map_queues,
351 	.kiq_unmap_queues = gfx10_kiq_unmap_queues,
352 	.kiq_query_status = gfx10_kiq_query_status,
353 	.set_resources_size = 8,
354 	.map_queues_size = 7,
355 	.unmap_queues_size = 6,
356 	.query_status_size = 7,
357 };
358 
359 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
360 {
361 	adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
362 }
363 
364 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
365 {
366 	switch (adev->asic_type) {
367 	case CHIP_NAVI10:
368 		soc15_program_register_sequence(adev,
369 						golden_settings_gc_10_1,
370 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
371 		soc15_program_register_sequence(adev,
372 						golden_settings_gc_10_0_nv10,
373 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
374 		break;
375 	case CHIP_NAVI14:
376 		soc15_program_register_sequence(adev,
377 						golden_settings_gc_10_1_1,
378 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
379 		soc15_program_register_sequence(adev,
380 						golden_settings_gc_10_1_nv14,
381 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
382 		break;
383 	case CHIP_NAVI12:
384 		soc15_program_register_sequence(adev,
385 						golden_settings_gc_10_1_2,
386 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
387 		soc15_program_register_sequence(adev,
388 						golden_settings_gc_10_1_2_nv12,
389 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
390 		break;
391 	default:
392 		break;
393 	}
394 }
395 
396 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
397 {
398 	adev->gfx.scratch.num_reg = 8;
399 	adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
400 	adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
401 }
402 
403 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
404 				       bool wc, uint32_t reg, uint32_t val)
405 {
406 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
407 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
408 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
409 	amdgpu_ring_write(ring, reg);
410 	amdgpu_ring_write(ring, 0);
411 	amdgpu_ring_write(ring, val);
412 }
413 
414 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
415 				  int mem_space, int opt, uint32_t addr0,
416 				  uint32_t addr1, uint32_t ref, uint32_t mask,
417 				  uint32_t inv)
418 {
419 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
420 	amdgpu_ring_write(ring,
421 			  /* memory (1) or register (0) */
422 			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
423 			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
424 			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
425 			   WAIT_REG_MEM_ENGINE(eng_sel)));
426 
427 	if (mem_space)
428 		BUG_ON(addr0 & 0x3); /* Dword align */
429 	amdgpu_ring_write(ring, addr0);
430 	amdgpu_ring_write(ring, addr1);
431 	amdgpu_ring_write(ring, ref);
432 	amdgpu_ring_write(ring, mask);
433 	amdgpu_ring_write(ring, inv); /* poll interval */
434 }
435 
436 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
437 {
438 	struct amdgpu_device *adev = ring->adev;
439 	uint32_t scratch;
440 	uint32_t tmp = 0;
441 	unsigned i;
442 	int r;
443 
444 	r = amdgpu_gfx_scratch_get(adev, &scratch);
445 	if (r) {
446 		DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
447 		return r;
448 	}
449 
450 	WREG32(scratch, 0xCAFEDEAD);
451 
452 	r = amdgpu_ring_alloc(ring, 3);
453 	if (r) {
454 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
455 			  ring->idx, r);
456 		amdgpu_gfx_scratch_free(adev, scratch);
457 		return r;
458 	}
459 
460 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
461 	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
462 	amdgpu_ring_write(ring, 0xDEADBEEF);
463 	amdgpu_ring_commit(ring);
464 
465 	for (i = 0; i < adev->usec_timeout; i++) {
466 		tmp = RREG32(scratch);
467 		if (tmp == 0xDEADBEEF)
468 			break;
469 		if (amdgpu_emu_mode == 1)
470 			msleep(1);
471 		else
472 			udelay(1);
473 	}
474 
475 	if (i >= adev->usec_timeout)
476 		r = -ETIMEDOUT;
477 
478 	amdgpu_gfx_scratch_free(adev, scratch);
479 
480 	return r;
481 }
482 
483 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
484 {
485 	struct amdgpu_device *adev = ring->adev;
486 	struct amdgpu_ib ib;
487 	struct dma_fence *f = NULL;
488 	uint32_t scratch;
489 	uint32_t tmp = 0;
490 	long r;
491 
492 	r = amdgpu_gfx_scratch_get(adev, &scratch);
493 	if (r) {
494 		DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
495 		return r;
496 	}
497 
498 	WREG32(scratch, 0xCAFEDEAD);
499 
500 	memset(&ib, 0, sizeof(ib));
501 	r = amdgpu_ib_get(adev, NULL, 256, &ib);
502 	if (r) {
503 		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
504 		goto err1;
505 	}
506 
507 	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
508 	ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
509 	ib.ptr[2] = 0xDEADBEEF;
510 	ib.length_dw = 3;
511 
512 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
513 	if (r)
514 		goto err2;
515 
516 	r = dma_fence_wait_timeout(f, false, timeout);
517 	if (r == 0) {
518 		DRM_ERROR("amdgpu: IB test timed out.\n");
519 		r = -ETIMEDOUT;
520 		goto err2;
521 	} else if (r < 0) {
522 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
523 		goto err2;
524 	}
525 
526 	tmp = RREG32(scratch);
527 	if (tmp == 0xDEADBEEF)
528 		r = 0;
529 	else
530 		r = -EINVAL;
531 err2:
532 	amdgpu_ib_free(adev, &ib, NULL);
533 	dma_fence_put(f);
534 err1:
535 	amdgpu_gfx_scratch_free(adev, scratch);
536 
537 	return r;
538 }
539 
540 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
541 {
542 	release_firmware(adev->gfx.pfp_fw);
543 	adev->gfx.pfp_fw = NULL;
544 	release_firmware(adev->gfx.me_fw);
545 	adev->gfx.me_fw = NULL;
546 	release_firmware(adev->gfx.ce_fw);
547 	adev->gfx.ce_fw = NULL;
548 	release_firmware(adev->gfx.rlc_fw);
549 	adev->gfx.rlc_fw = NULL;
550 	release_firmware(adev->gfx.mec_fw);
551 	adev->gfx.mec_fw = NULL;
552 	release_firmware(adev->gfx.mec2_fw);
553 	adev->gfx.mec2_fw = NULL;
554 
555 	kfree(adev->gfx.rlc.register_list_format);
556 }
557 
558 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
559 {
560 	adev->gfx.cp_fw_write_wait = false;
561 
562 	switch (adev->asic_type) {
563 	case CHIP_NAVI10:
564 	case CHIP_NAVI12:
565 	case CHIP_NAVI14:
566 		if ((adev->gfx.me_fw_version >= 0x00000046) &&
567 		    (adev->gfx.me_feature_version >= 27) &&
568 		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
569 		    (adev->gfx.pfp_feature_version >= 27) &&
570 		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
571 		    (adev->gfx.mec_feature_version >= 27))
572 			adev->gfx.cp_fw_write_wait = true;
573 		break;
574 	default:
575 		break;
576 	}
577 
578 	if (adev->gfx.cp_fw_write_wait == false)
579 		DRM_WARN_ONCE("CP firmware version too old, please update!");
580 }
581 
582 
583 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
584 {
585 	const struct rlc_firmware_header_v2_1 *rlc_hdr;
586 
587 	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
588 	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
589 	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
590 	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
591 	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
592 	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
593 	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
594 	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
595 	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
596 	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
597 	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
598 	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
599 	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
600 	adev->gfx.rlc.reg_list_format_direct_reg_list_length =
601 			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
602 }
603 
604 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
605 {
606 	bool ret = false;
607 
608 	switch (adev->pdev->revision) {
609 	case 0xc2:
610 	case 0xc3:
611 		ret = true;
612 		break;
613 	default:
614 		ret = false;
615 		break;
616 	}
617 
618 	return ret ;
619 }
620 
621 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
622 {
623 	switch (adev->asic_type) {
624 	case CHIP_NAVI10:
625 		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
626 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
627 		break;
628 	default:
629 		break;
630 	}
631 }
632 
633 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
634 {
635 	const char *chip_name;
636 	char fw_name[40];
637 	char wks[10];
638 	int err;
639 	struct amdgpu_firmware_info *info = NULL;
640 	const struct common_firmware_header *header = NULL;
641 	const struct gfx_firmware_header_v1_0 *cp_hdr;
642 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
643 	unsigned int *tmp = NULL;
644 	unsigned int i = 0;
645 	uint16_t version_major;
646 	uint16_t version_minor;
647 
648 	DRM_DEBUG("\n");
649 
650 	memset(wks, 0, sizeof(wks));
651 	switch (adev->asic_type) {
652 	case CHIP_NAVI10:
653 		chip_name = "navi10";
654 		break;
655 	case CHIP_NAVI14:
656 		chip_name = "navi14";
657 		if (!(adev->pdev->device == 0x7340 &&
658 		      adev->pdev->revision != 0x00))
659 			snprintf(wks, sizeof(wks), "_wks");
660 		break;
661 	case CHIP_NAVI12:
662 		chip_name = "navi12";
663 		break;
664 	default:
665 		BUG();
666 	}
667 
668 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
669 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
670 	if (err)
671 		goto out;
672 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
673 	if (err)
674 		goto out;
675 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
676 	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
677 	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
678 
679 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
680 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
681 	if (err)
682 		goto out;
683 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
684 	if (err)
685 		goto out;
686 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
687 	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
688 	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
689 
690 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
691 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
692 	if (err)
693 		goto out;
694 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
695 	if (err)
696 		goto out;
697 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
698 	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
699 	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
700 
701 	if (!amdgpu_sriov_vf(adev)) {
702 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
703 		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
704 		if (err)
705 			goto out;
706 		err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
707 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
708 		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
709 		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
710 		if (version_major == 2 && version_minor == 1)
711 			adev->gfx.rlc.is_rlc_v2_1 = true;
712 
713 		adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
714 		adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
715 		adev->gfx.rlc.save_and_restore_offset =
716 			le32_to_cpu(rlc_hdr->save_and_restore_offset);
717 		adev->gfx.rlc.clear_state_descriptor_offset =
718 			le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
719 		adev->gfx.rlc.avail_scratch_ram_locations =
720 			le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
721 		adev->gfx.rlc.reg_restore_list_size =
722 			le32_to_cpu(rlc_hdr->reg_restore_list_size);
723 		adev->gfx.rlc.reg_list_format_start =
724 			le32_to_cpu(rlc_hdr->reg_list_format_start);
725 		adev->gfx.rlc.reg_list_format_separate_start =
726 			le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
727 		adev->gfx.rlc.starting_offsets_start =
728 			le32_to_cpu(rlc_hdr->starting_offsets_start);
729 		adev->gfx.rlc.reg_list_format_size_bytes =
730 			le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
731 		adev->gfx.rlc.reg_list_size_bytes =
732 			le32_to_cpu(rlc_hdr->reg_list_size_bytes);
733 		adev->gfx.rlc.register_list_format =
734 			kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
735 					adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
736 		if (!adev->gfx.rlc.register_list_format) {
737 			err = -ENOMEM;
738 			goto out;
739 		}
740 
741 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
742 							   le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
743 		for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
744 			adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
745 
746 		adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
747 
748 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
749 							   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
750 		for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
751 			adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
752 
753 		if (adev->gfx.rlc.is_rlc_v2_1)
754 			gfx_v10_0_init_rlc_ext_microcode(adev);
755 	}
756 
757 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
758 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
759 	if (err)
760 		goto out;
761 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
762 	if (err)
763 		goto out;
764 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
765 	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
766 	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
767 
768 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
769 	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
770 	if (!err) {
771 		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
772 		if (err)
773 			goto out;
774 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
775 		adev->gfx.mec2_fw->data;
776 		adev->gfx.mec2_fw_version =
777 		le32_to_cpu(cp_hdr->header.ucode_version);
778 		adev->gfx.mec2_feature_version =
779 		le32_to_cpu(cp_hdr->ucode_feature_version);
780 	} else {
781 		err = 0;
782 		adev->gfx.mec2_fw = NULL;
783 	}
784 
785 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
786 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
787 		info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
788 		info->fw = adev->gfx.pfp_fw;
789 		header = (const struct common_firmware_header *)info->fw->data;
790 		adev->firmware.fw_size +=
791 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
792 
793 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
794 		info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
795 		info->fw = adev->gfx.me_fw;
796 		header = (const struct common_firmware_header *)info->fw->data;
797 		adev->firmware.fw_size +=
798 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
799 
800 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
801 		info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
802 		info->fw = adev->gfx.ce_fw;
803 		header = (const struct common_firmware_header *)info->fw->data;
804 		adev->firmware.fw_size +=
805 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
806 
807 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
808 		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
809 		info->fw = adev->gfx.rlc_fw;
810 		header = (const struct common_firmware_header *)info->fw->data;
811 		adev->firmware.fw_size +=
812 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
813 
814 		if (adev->gfx.rlc.is_rlc_v2_1 &&
815 		    adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
816 		    adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
817 		    adev->gfx.rlc.save_restore_list_srm_size_bytes) {
818 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
819 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
820 			info->fw = adev->gfx.rlc_fw;
821 			adev->firmware.fw_size +=
822 				ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
823 
824 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
825 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
826 			info->fw = adev->gfx.rlc_fw;
827 			adev->firmware.fw_size +=
828 				ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
829 
830 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
831 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
832 			info->fw = adev->gfx.rlc_fw;
833 			adev->firmware.fw_size +=
834 				ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
835 		}
836 
837 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
838 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
839 		info->fw = adev->gfx.mec_fw;
840 		header = (const struct common_firmware_header *)info->fw->data;
841 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
842 		adev->firmware.fw_size +=
843 			ALIGN(le32_to_cpu(header->ucode_size_bytes) -
844 			      le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
845 
846 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
847 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
848 		info->fw = adev->gfx.mec_fw;
849 		adev->firmware.fw_size +=
850 			ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
851 
852 		if (adev->gfx.mec2_fw) {
853 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
854 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
855 			info->fw = adev->gfx.mec2_fw;
856 			header = (const struct common_firmware_header *)info->fw->data;
857 			cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
858 			adev->firmware.fw_size +=
859 				ALIGN(le32_to_cpu(header->ucode_size_bytes) -
860 				      le32_to_cpu(cp_hdr->jt_size) * 4,
861 				      PAGE_SIZE);
862 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
863 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
864 			info->fw = adev->gfx.mec2_fw;
865 			adev->firmware.fw_size +=
866 				ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
867 				      PAGE_SIZE);
868 		}
869 	}
870 
871 	gfx_v10_0_check_fw_write_wait(adev);
872 out:
873 	if (err) {
874 		dev_err(adev->dev,
875 			"gfx10: Failed to load firmware \"%s\"\n",
876 			fw_name);
877 		release_firmware(adev->gfx.pfp_fw);
878 		adev->gfx.pfp_fw = NULL;
879 		release_firmware(adev->gfx.me_fw);
880 		adev->gfx.me_fw = NULL;
881 		release_firmware(adev->gfx.ce_fw);
882 		adev->gfx.ce_fw = NULL;
883 		release_firmware(adev->gfx.rlc_fw);
884 		adev->gfx.rlc_fw = NULL;
885 		release_firmware(adev->gfx.mec_fw);
886 		adev->gfx.mec_fw = NULL;
887 		release_firmware(adev->gfx.mec2_fw);
888 		adev->gfx.mec2_fw = NULL;
889 	}
890 
891 	gfx_v10_0_check_gfxoff_flag(adev);
892 
893 	return err;
894 }
895 
896 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
897 {
898 	u32 count = 0;
899 	const struct cs_section_def *sect = NULL;
900 	const struct cs_extent_def *ext = NULL;
901 
902 	/* begin clear state */
903 	count += 2;
904 	/* context control state */
905 	count += 3;
906 
907 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
908 		for (ext = sect->section; ext->extent != NULL; ++ext) {
909 			if (sect->id == SECT_CONTEXT)
910 				count += 2 + ext->reg_count;
911 			else
912 				return 0;
913 		}
914 	}
915 
916 	/* set PA_SC_TILE_STEERING_OVERRIDE */
917 	count += 3;
918 	/* end clear state */
919 	count += 2;
920 	/* clear state */
921 	count += 2;
922 
923 	return count;
924 }
925 
926 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
927 				    volatile u32 *buffer)
928 {
929 	u32 count = 0, i;
930 	const struct cs_section_def *sect = NULL;
931 	const struct cs_extent_def *ext = NULL;
932 	int ctx_reg_offset;
933 
934 	if (adev->gfx.rlc.cs_data == NULL)
935 		return;
936 	if (buffer == NULL)
937 		return;
938 
939 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
940 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
941 
942 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
943 	buffer[count++] = cpu_to_le32(0x80000000);
944 	buffer[count++] = cpu_to_le32(0x80000000);
945 
946 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
947 		for (ext = sect->section; ext->extent != NULL; ++ext) {
948 			if (sect->id == SECT_CONTEXT) {
949 				buffer[count++] =
950 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
951 				buffer[count++] = cpu_to_le32(ext->reg_index -
952 						PACKET3_SET_CONTEXT_REG_START);
953 				for (i = 0; i < ext->reg_count; i++)
954 					buffer[count++] = cpu_to_le32(ext->extent[i]);
955 			} else {
956 				return;
957 			}
958 		}
959 	}
960 
961 	ctx_reg_offset =
962 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
963 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
964 	buffer[count++] = cpu_to_le32(ctx_reg_offset);
965 	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
966 
967 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
968 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
969 
970 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
971 	buffer[count++] = cpu_to_le32(0);
972 }
973 
974 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
975 {
976 	/* clear state block */
977 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
978 			&adev->gfx.rlc.clear_state_gpu_addr,
979 			(void **)&adev->gfx.rlc.cs_ptr);
980 
981 	/* jump table block */
982 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
983 			&adev->gfx.rlc.cp_table_gpu_addr,
984 			(void **)&adev->gfx.rlc.cp_table_ptr);
985 }
986 
987 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
988 {
989 	const struct cs_section_def *cs_data;
990 	int r;
991 
992 	adev->gfx.rlc.cs_data = gfx10_cs_data;
993 
994 	cs_data = adev->gfx.rlc.cs_data;
995 
996 	if (cs_data) {
997 		/* init clear state block */
998 		r = amdgpu_gfx_rlc_init_csb(adev);
999 		if (r)
1000 			return r;
1001 	}
1002 
1003 	return 0;
1004 }
1005 
1006 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
1007 {
1008 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1009 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1010 }
1011 
1012 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
1013 {
1014 	int r;
1015 
1016 	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
1017 
1018 	amdgpu_gfx_graphics_queue_acquire(adev);
1019 
1020 	r = gfx_v10_0_init_microcode(adev);
1021 	if (r)
1022 		DRM_ERROR("Failed to load gfx firmware!\n");
1023 
1024 	return r;
1025 }
1026 
1027 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
1028 {
1029 	int r;
1030 	u32 *hpd;
1031 	const __le32 *fw_data = NULL;
1032 	unsigned fw_size;
1033 	u32 *fw = NULL;
1034 	size_t mec_hpd_size;
1035 
1036 	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
1037 
1038 	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1039 
1040 	/* take ownership of the relevant compute queues */
1041 	amdgpu_gfx_compute_queue_acquire(adev);
1042 	mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
1043 
1044 	r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1045 				      AMDGPU_GEM_DOMAIN_GTT,
1046 				      &adev->gfx.mec.hpd_eop_obj,
1047 				      &adev->gfx.mec.hpd_eop_gpu_addr,
1048 				      (void **)&hpd);
1049 	if (r) {
1050 		dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1051 		gfx_v10_0_mec_fini(adev);
1052 		return r;
1053 	}
1054 
1055 	memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1056 
1057 	amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1058 	amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1059 
1060 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1061 		mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1062 
1063 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1064 			 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1065 		fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1066 
1067 		r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1068 					      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1069 					      &adev->gfx.mec.mec_fw_obj,
1070 					      &adev->gfx.mec.mec_fw_gpu_addr,
1071 					      (void **)&fw);
1072 		if (r) {
1073 			dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
1074 			gfx_v10_0_mec_fini(adev);
1075 			return r;
1076 		}
1077 
1078 		memcpy(fw, fw_data, fw_size);
1079 
1080 		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1081 		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1082 	}
1083 
1084 	return 0;
1085 }
1086 
1087 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
1088 {
1089 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1090 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1091 		(address << SQ_IND_INDEX__INDEX__SHIFT));
1092 	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1093 }
1094 
1095 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
1096 			   uint32_t thread, uint32_t regno,
1097 			   uint32_t num, uint32_t *out)
1098 {
1099 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1100 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1101 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
1102 		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
1103 		(SQ_IND_INDEX__AUTO_INCR_MASK));
1104 	while (num--)
1105 		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1106 }
1107 
1108 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1109 {
1110 	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE
1111 	 * field when performing a select_se_sh so it should be
1112 	 * zero here */
1113 	WARN_ON(simd != 0);
1114 
1115 	/* type 2 wave data */
1116 	dst[(*no_fields)++] = 2;
1117 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
1118 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
1119 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
1120 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
1121 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
1122 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
1123 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
1124 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
1125 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
1126 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
1127 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
1128 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
1129 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
1130 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
1131 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
1132 }
1133 
1134 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1135 				     uint32_t wave, uint32_t start,
1136 				     uint32_t size, uint32_t *dst)
1137 {
1138 	WARN_ON(simd != 0);
1139 
1140 	wave_read_regs(
1141 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
1142 		dst);
1143 }
1144 
1145 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1146 				      uint32_t wave, uint32_t thread,
1147 				      uint32_t start, uint32_t size,
1148 				      uint32_t *dst)
1149 {
1150 	wave_read_regs(
1151 		adev, wave, thread,
1152 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1153 }
1154 
1155 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
1156 									  u32 me, u32 pipe, u32 q, u32 vm)
1157  {
1158        nv_grbm_select(adev, me, pipe, q, vm);
1159  }
1160 
1161 
1162 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
1163 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
1164 	.select_se_sh = &gfx_v10_0_select_se_sh,
1165 	.read_wave_data = &gfx_v10_0_read_wave_data,
1166 	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
1167 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
1168 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
1169 };
1170 
1171 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
1172 {
1173 	u32 gb_addr_config;
1174 
1175 	adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
1176 
1177 	switch (adev->asic_type) {
1178 	case CHIP_NAVI10:
1179 	case CHIP_NAVI14:
1180 	case CHIP_NAVI12:
1181 		adev->gfx.config.max_hw_contexts = 8;
1182 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1183 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1184 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1185 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1186 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1187 		break;
1188 	default:
1189 		BUG();
1190 		break;
1191 	}
1192 
1193 	adev->gfx.config.gb_addr_config = gb_addr_config;
1194 
1195 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1196 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1197 				      GB_ADDR_CONFIG, NUM_PIPES);
1198 
1199 	adev->gfx.config.max_tile_pipes =
1200 		adev->gfx.config.gb_addr_config_fields.num_pipes;
1201 
1202 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1203 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1204 				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
1205 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1206 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1207 				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
1208 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1209 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1210 				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
1211 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1212 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1213 				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
1214 }
1215 
1216 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
1217 				   int me, int pipe, int queue)
1218 {
1219 	int r;
1220 	struct amdgpu_ring *ring;
1221 	unsigned int irq_type;
1222 
1223 	ring = &adev->gfx.gfx_ring[ring_id];
1224 
1225 	ring->me = me;
1226 	ring->pipe = pipe;
1227 	ring->queue = queue;
1228 
1229 	ring->ring_obj = NULL;
1230 	ring->use_doorbell = true;
1231 
1232 	if (!ring_id)
1233 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1234 	else
1235 		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
1236 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1237 
1238 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
1239 	r = amdgpu_ring_init(adev, ring, 1024,
1240 			     &adev->gfx.eop_irq, irq_type);
1241 	if (r)
1242 		return r;
1243 	return 0;
1244 }
1245 
1246 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1247 				       int mec, int pipe, int queue)
1248 {
1249 	int r;
1250 	unsigned irq_type;
1251 	struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1252 
1253 	ring = &adev->gfx.compute_ring[ring_id];
1254 
1255 	/* mec0 is me1 */
1256 	ring->me = mec + 1;
1257 	ring->pipe = pipe;
1258 	ring->queue = queue;
1259 
1260 	ring->ring_obj = NULL;
1261 	ring->use_doorbell = true;
1262 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1263 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1264 				+ (ring_id * GFX10_MEC_HPD_SIZE);
1265 	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1266 
1267 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1268 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1269 		+ ring->pipe;
1270 
1271 	/* type-2 packets are deprecated on MEC, use type-3 instead */
1272 	r = amdgpu_ring_init(adev, ring, 1024,
1273 			     &adev->gfx.eop_irq, irq_type);
1274 	if (r)
1275 		return r;
1276 
1277 	return 0;
1278 }
1279 
1280 static int gfx_v10_0_sw_init(void *handle)
1281 {
1282 	int i, j, k, r, ring_id = 0;
1283 	struct amdgpu_kiq *kiq;
1284 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285 
1286 	switch (adev->asic_type) {
1287 	case CHIP_NAVI10:
1288 	case CHIP_NAVI14:
1289 	case CHIP_NAVI12:
1290 		adev->gfx.me.num_me = 1;
1291 		adev->gfx.me.num_pipe_per_me = 2;
1292 		adev->gfx.me.num_queue_per_pipe = 1;
1293 		adev->gfx.mec.num_mec = 2;
1294 		adev->gfx.mec.num_pipe_per_mec = 4;
1295 		adev->gfx.mec.num_queue_per_pipe = 8;
1296 		break;
1297 	default:
1298 		adev->gfx.me.num_me = 1;
1299 		adev->gfx.me.num_pipe_per_me = 1;
1300 		adev->gfx.me.num_queue_per_pipe = 1;
1301 		adev->gfx.mec.num_mec = 1;
1302 		adev->gfx.mec.num_pipe_per_mec = 4;
1303 		adev->gfx.mec.num_queue_per_pipe = 8;
1304 		break;
1305 	}
1306 
1307 	/* KIQ event */
1308 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1309 			      GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
1310 			      &adev->gfx.kiq.irq);
1311 	if (r)
1312 		return r;
1313 
1314 	/* EOP Event */
1315 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1316 			      GFX_10_1__SRCID__CP_EOP_INTERRUPT,
1317 			      &adev->gfx.eop_irq);
1318 	if (r)
1319 		return r;
1320 
1321 	/* Privileged reg */
1322 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
1323 			      &adev->gfx.priv_reg_irq);
1324 	if (r)
1325 		return r;
1326 
1327 	/* Privileged inst */
1328 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
1329 			      &adev->gfx.priv_inst_irq);
1330 	if (r)
1331 		return r;
1332 
1333 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1334 
1335 	gfx_v10_0_scratch_init(adev);
1336 
1337 	r = gfx_v10_0_me_init(adev);
1338 	if (r)
1339 		return r;
1340 
1341 	r = gfx_v10_0_rlc_init(adev);
1342 	if (r) {
1343 		DRM_ERROR("Failed to init rlc BOs!\n");
1344 		return r;
1345 	}
1346 
1347 	r = gfx_v10_0_mec_init(adev);
1348 	if (r) {
1349 		DRM_ERROR("Failed to init MEC BOs!\n");
1350 		return r;
1351 	}
1352 
1353 	/* set up the gfx ring */
1354 	for (i = 0; i < adev->gfx.me.num_me; i++) {
1355 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1356 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1357 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1358 					continue;
1359 
1360 				r = gfx_v10_0_gfx_ring_init(adev, ring_id,
1361 							    i, k, j);
1362 				if (r)
1363 					return r;
1364 				ring_id++;
1365 			}
1366 		}
1367 	}
1368 
1369 	ring_id = 0;
1370 	/* set up the compute queues - allocate horizontally across pipes */
1371 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1372 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1373 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1374 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1375 								     j))
1376 					continue;
1377 
1378 				r = gfx_v10_0_compute_ring_init(adev, ring_id,
1379 								i, k, j);
1380 				if (r)
1381 					return r;
1382 
1383 				ring_id++;
1384 			}
1385 		}
1386 	}
1387 
1388 	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
1389 	if (r) {
1390 		DRM_ERROR("Failed to init KIQ BOs!\n");
1391 		return r;
1392 	}
1393 
1394 	kiq = &adev->gfx.kiq;
1395 	r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1396 	if (r)
1397 		return r;
1398 
1399 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
1400 	if (r)
1401 		return r;
1402 
1403 	/* allocate visible FB for rlc auto-loading fw */
1404 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1405 		r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
1406 		if (r)
1407 			return r;
1408 	}
1409 
1410 	adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
1411 
1412 	gfx_v10_0_gpu_early_init(adev);
1413 
1414 	return 0;
1415 }
1416 
1417 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
1418 {
1419 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1420 			      &adev->gfx.pfp.pfp_fw_gpu_addr,
1421 			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
1422 }
1423 
1424 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
1425 {
1426 	amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
1427 			      &adev->gfx.ce.ce_fw_gpu_addr,
1428 			      (void **)&adev->gfx.ce.ce_fw_ptr);
1429 }
1430 
1431 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
1432 {
1433 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1434 			      &adev->gfx.me.me_fw_gpu_addr,
1435 			      (void **)&adev->gfx.me.me_fw_ptr);
1436 }
1437 
1438 static int gfx_v10_0_sw_fini(void *handle)
1439 {
1440 	int i;
1441 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1442 
1443 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1444 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1445 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
1446 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1447 
1448 	amdgpu_gfx_mqd_sw_fini(adev);
1449 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
1450 	amdgpu_gfx_kiq_fini(adev);
1451 
1452 	gfx_v10_0_pfp_fini(adev);
1453 	gfx_v10_0_ce_fini(adev);
1454 	gfx_v10_0_me_fini(adev);
1455 	gfx_v10_0_rlc_fini(adev);
1456 	gfx_v10_0_mec_fini(adev);
1457 
1458 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1459 		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
1460 
1461 	gfx_v10_0_free_microcode(adev);
1462 
1463 	return 0;
1464 }
1465 
1466 
1467 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
1468 {
1469 	/* TODO */
1470 }
1471 
1472 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1473 				   u32 sh_num, u32 instance)
1474 {
1475 	u32 data;
1476 
1477 	if (instance == 0xffffffff)
1478 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1479 				     INSTANCE_BROADCAST_WRITES, 1);
1480 	else
1481 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1482 				     instance);
1483 
1484 	if (se_num == 0xffffffff)
1485 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1486 				     1);
1487 	else
1488 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1489 
1490 	if (sh_num == 0xffffffff)
1491 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1492 				     1);
1493 	else
1494 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1495 
1496 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1497 }
1498 
1499 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1500 {
1501 	u32 data, mask;
1502 
1503 	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1504 	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1505 
1506 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1507 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1508 
1509 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1510 					 adev->gfx.config.max_sh_per_se);
1511 
1512 	return (~data) & mask;
1513 }
1514 
1515 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
1516 {
1517 	int i, j;
1518 	u32 data;
1519 	u32 active_rbs = 0;
1520 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1521 					adev->gfx.config.max_sh_per_se;
1522 
1523 	mutex_lock(&adev->grbm_idx_mutex);
1524 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1525 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1526 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1527 			data = gfx_v10_0_get_rb_active_bitmap(adev);
1528 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1529 					       rb_bitmap_width_per_sh);
1530 		}
1531 	}
1532 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1533 	mutex_unlock(&adev->grbm_idx_mutex);
1534 
1535 	adev->gfx.config.backend_enable_mask = active_rbs;
1536 	adev->gfx.config.num_rbs = hweight32(active_rbs);
1537 }
1538 
1539 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
1540 {
1541 	uint32_t num_sc;
1542 	uint32_t enabled_rb_per_sh;
1543 	uint32_t active_rb_bitmap;
1544 	uint32_t num_rb_per_sc;
1545 	uint32_t num_packer_per_sc;
1546 	uint32_t pa_sc_tile_steering_override;
1547 
1548 	/* init num_sc */
1549 	num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
1550 			adev->gfx.config.num_sc_per_sh;
1551 	/* init num_rb_per_sc */
1552 	active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
1553 	enabled_rb_per_sh = hweight32(active_rb_bitmap);
1554 	num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
1555 	/* init num_packer_per_sc */
1556 	num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
1557 
1558 	pa_sc_tile_steering_override = 0;
1559 	pa_sc_tile_steering_override |=
1560 		(order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
1561 		PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
1562 	pa_sc_tile_steering_override |=
1563 		(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
1564 		PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
1565 	pa_sc_tile_steering_override |=
1566 		(order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
1567 		PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
1568 
1569 	return pa_sc_tile_steering_override;
1570 }
1571 
1572 #define DEFAULT_SH_MEM_BASES	(0x6000)
1573 #define FIRST_COMPUTE_VMID	(8)
1574 #define LAST_COMPUTE_VMID	(16)
1575 
1576 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
1577 {
1578 	int i;
1579 	uint32_t sh_mem_bases;
1580 
1581 	/*
1582 	 * Configure apertures:
1583 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1584 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1585 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1586 	 */
1587 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1588 
1589 	mutex_lock(&adev->srbm_mutex);
1590 	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1591 		nv_grbm_select(adev, 0, 0, 0, i);
1592 		/* CP and shaders */
1593 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1594 		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1595 	}
1596 	nv_grbm_select(adev, 0, 0, 0, 0);
1597 	mutex_unlock(&adev->srbm_mutex);
1598 
1599 	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
1600 	   acccess. These should be enabled by FW for target VMIDs. */
1601 	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1602 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1603 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
1604 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
1605 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
1606 	}
1607 }
1608 
1609 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
1610 {
1611 	int vmid;
1612 
1613 	/*
1614 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1615 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
1616 	 * the driver can enable them for graphics. VMID0 should maintain
1617 	 * access so that HWS firmware can save/restore entries.
1618 	 */
1619 	for (vmid = 1; vmid < 16; vmid++) {
1620 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
1621 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
1622 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
1623 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
1624 	}
1625 }
1626 
1627 
1628 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
1629 {
1630 	int i, j, k;
1631 	int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
1632 	u32 tmp, wgp_active_bitmap = 0;
1633 	u32 gcrd_targets_disable_tcp = 0;
1634 	u32 utcl_invreq_disable = 0;
1635 	/*
1636 	 * GCRD_TARGETS_DISABLE field contains
1637 	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
1638 	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
1639 	 */
1640 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
1641 		2 * max_wgp_per_sh + /* TCP */
1642 		max_wgp_per_sh + /* SQC */
1643 		4); /* GL1C */
1644 	/*
1645 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
1646 	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
1647 	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
1648 	 */
1649 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
1650 		2 * max_wgp_per_sh + /* TCP */
1651 		2 * max_wgp_per_sh + /* SQC */
1652 		4 + /* RMI */
1653 		1); /* SQG */
1654 
1655 	if (adev->asic_type == CHIP_NAVI10 ||
1656 	    adev->asic_type == CHIP_NAVI14 ||
1657 	    adev->asic_type == CHIP_NAVI12) {
1658 		mutex_lock(&adev->grbm_idx_mutex);
1659 		for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1660 			for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1661 				gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1662 				wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
1663 				/*
1664 				 * Set corresponding TCP bits for the inactive WGPs in
1665 				 * GCRD_SA_TARGETS_DISABLE
1666 				 */
1667 				gcrd_targets_disable_tcp = 0;
1668 				/* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
1669 				utcl_invreq_disable = 0;
1670 
1671 				for (k = 0; k < max_wgp_per_sh; k++) {
1672 					if (!(wgp_active_bitmap & (1 << k))) {
1673 						gcrd_targets_disable_tcp |= 3 << (2 * k);
1674 						utcl_invreq_disable |= (3 << (2 * k)) |
1675 							(3 << (2 * (max_wgp_per_sh + k)));
1676 					}
1677 				}
1678 
1679 				tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1680 				/* only override TCP & SQC bits */
1681 				tmp &= 0xffffffff << (4 * max_wgp_per_sh);
1682 				tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
1683 				WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1684 
1685 				tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1686 				/* only override TCP bits */
1687 				tmp &= 0xffffffff << (2 * max_wgp_per_sh);
1688 				tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
1689 				WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1690 			}
1691 		}
1692 
1693 		gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1694 		mutex_unlock(&adev->grbm_idx_mutex);
1695 	}
1696 }
1697 
1698 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
1699 {
1700 	/* TCCs are global (not instanced). */
1701 	uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
1702 			       RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
1703 
1704 	adev->gfx.config.tcc_disabled_mask =
1705 		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1706 		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1707 }
1708 
1709 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
1710 {
1711 	u32 tmp;
1712 	int i;
1713 
1714 	WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1715 
1716 	gfx_v10_0_tiling_mode_table_init(adev);
1717 
1718 	gfx_v10_0_setup_rb(adev);
1719 	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
1720 	gfx_v10_0_get_tcc_info(adev);
1721 	adev->gfx.config.pa_sc_tile_steering_override =
1722 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
1723 
1724 	/* XXX SH_MEM regs */
1725 	/* where to put LDS, scratch, GPUVM in FSA64 space */
1726 	mutex_lock(&adev->srbm_mutex);
1727 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1728 		nv_grbm_select(adev, 0, 0, 0, i);
1729 		/* CP and shaders */
1730 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1731 		if (i != 0) {
1732 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1733 				(adev->gmc.private_aperture_start >> 48));
1734 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1735 				(adev->gmc.shared_aperture_start >> 48));
1736 			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1737 		}
1738 	}
1739 	nv_grbm_select(adev, 0, 0, 0, 0);
1740 
1741 	mutex_unlock(&adev->srbm_mutex);
1742 
1743 	gfx_v10_0_init_compute_vmid(adev);
1744 	gfx_v10_0_init_gds_vmid(adev);
1745 
1746 }
1747 
1748 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1749 					       bool enable)
1750 {
1751 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1752 
1753 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1754 			    enable ? 1 : 0);
1755 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1756 			    enable ? 1 : 0);
1757 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1758 			    enable ? 1 : 0);
1759 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1760 			    enable ? 1 : 0);
1761 
1762 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1763 }
1764 
1765 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
1766 {
1767 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1768 
1769 	/* csib */
1770 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
1771 		     adev->gfx.rlc.clear_state_gpu_addr >> 32);
1772 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
1773 		     adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1774 	WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1775 
1776 	return 0;
1777 }
1778 
1779 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
1780 {
1781 	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1782 
1783 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1784 	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1785 }
1786 
1787 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
1788 {
1789 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1790 	udelay(50);
1791 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1792 	udelay(50);
1793 }
1794 
1795 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1796 					     bool enable)
1797 {
1798 	uint32_t rlc_pg_cntl;
1799 
1800 	rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
1801 
1802 	if (!enable) {
1803 		/* RLC_PG_CNTL[23] = 0 (default)
1804 		 * RLC will wait for handshake acks with SMU
1805 		 * GFXOFF will be enabled
1806 		 * RLC_PG_CNTL[23] = 1
1807 		 * RLC will not issue any message to SMU
1808 		 * hence no handshake between SMU & RLC
1809 		 * GFXOFF will be disabled
1810 		 */
1811 		rlc_pg_cntl |= 0x800000;
1812 	} else
1813 		rlc_pg_cntl &= ~0x800000;
1814 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
1815 }
1816 
1817 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
1818 {
1819 	/* TODO: enable rlc & smu handshake until smu
1820 	 * and gfxoff feature works as expected */
1821 	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1822 		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
1823 
1824 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1825 	udelay(50);
1826 }
1827 
1828 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
1829 {
1830 	uint32_t tmp;
1831 
1832 	/* enable Save Restore Machine */
1833 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1834 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1835 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1836 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1837 }
1838 
1839 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
1840 {
1841 	const struct rlc_firmware_header_v2_0 *hdr;
1842 	const __le32 *fw_data;
1843 	unsigned i, fw_size;
1844 
1845 	if (!adev->gfx.rlc_fw)
1846 		return -EINVAL;
1847 
1848 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1849 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
1850 
1851 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1852 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1853 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1854 
1855 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1856 		     RLCG_UCODE_LOADING_START_ADDRESS);
1857 
1858 	for (i = 0; i < fw_size; i++)
1859 		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
1860 			     le32_to_cpup(fw_data++));
1861 
1862 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1863 
1864 	return 0;
1865 }
1866 
1867 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
1868 {
1869 	int r;
1870 
1871 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1872 
1873 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1874 		if (r)
1875 			return r;
1876 
1877 		gfx_v10_0_init_csb(adev);
1878 
1879 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
1880 			gfx_v10_0_rlc_enable_srm(adev);
1881 	} else {
1882 		adev->gfx.rlc.funcs->stop(adev);
1883 
1884 		/* disable CG */
1885 		WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1886 
1887 		/* disable PG */
1888 		WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
1889 
1890 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1891 			/* legacy rlc firmware loading */
1892 			r = gfx_v10_0_rlc_load_microcode(adev);
1893 			if (r)
1894 				return r;
1895 		} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1896 			/* rlc backdoor autoload firmware */
1897 			r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
1898 			if (r)
1899 				return r;
1900 		}
1901 
1902 		gfx_v10_0_init_csb(adev);
1903 
1904 		adev->gfx.rlc.funcs->start(adev);
1905 
1906 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1907 			r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1908 			if (r)
1909 				return r;
1910 		}
1911 	}
1912 	return 0;
1913 }
1914 
1915 static struct {
1916 	FIRMWARE_ID	id;
1917 	unsigned int	offset;
1918 	unsigned int	size;
1919 } rlc_autoload_info[FIRMWARE_ID_MAX];
1920 
1921 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
1922 {
1923 	int ret;
1924 	RLC_TABLE_OF_CONTENT *rlc_toc;
1925 
1926 	ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
1927 					AMDGPU_GEM_DOMAIN_GTT,
1928 					&adev->gfx.rlc.rlc_toc_bo,
1929 					&adev->gfx.rlc.rlc_toc_gpu_addr,
1930 					(void **)&adev->gfx.rlc.rlc_toc_buf);
1931 	if (ret) {
1932 		dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
1933 		return ret;
1934 	}
1935 
1936 	/* Copy toc from psp sos fw to rlc toc buffer */
1937 	memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
1938 
1939 	rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
1940 	while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
1941 		(rlc_toc->id < FIRMWARE_ID_MAX)) {
1942 		if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
1943 		    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
1944 			/* Offset needs 4KB alignment */
1945 			rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
1946 		}
1947 
1948 		rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
1949 		rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
1950 		rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
1951 
1952 		rlc_toc++;
1953 	}
1954 
1955 	return 0;
1956 }
1957 
1958 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
1959 {
1960 	uint32_t total_size = 0;
1961 	FIRMWARE_ID id;
1962 	int ret;
1963 
1964 	ret = gfx_v10_0_parse_rlc_toc(adev);
1965 	if (ret) {
1966 		dev_err(adev->dev, "failed to parse rlc toc\n");
1967 		return 0;
1968 	}
1969 
1970 	for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
1971 		total_size += rlc_autoload_info[id].size;
1972 
1973 	/* In case the offset in rlc toc ucode is aligned */
1974 	if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
1975 		total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
1976 				rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
1977 
1978 	return total_size;
1979 }
1980 
1981 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
1982 {
1983 	int r;
1984 	uint32_t total_size;
1985 
1986 	total_size = gfx_v10_0_calc_toc_total_size(adev);
1987 
1988 	r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
1989 				      AMDGPU_GEM_DOMAIN_GTT,
1990 				      &adev->gfx.rlc.rlc_autoload_bo,
1991 				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
1992 				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1993 	if (r) {
1994 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1995 		return r;
1996 	}
1997 
1998 	return 0;
1999 }
2000 
2001 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
2002 {
2003 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
2004 			      &adev->gfx.rlc.rlc_toc_gpu_addr,
2005 			      (void **)&adev->gfx.rlc.rlc_toc_buf);
2006 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
2007 			      &adev->gfx.rlc.rlc_autoload_gpu_addr,
2008 			      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
2009 }
2010 
2011 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
2012 						       FIRMWARE_ID id,
2013 						       const void *fw_data,
2014 						       uint32_t fw_size)
2015 {
2016 	uint32_t toc_offset;
2017 	uint32_t toc_fw_size;
2018 	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
2019 
2020 	if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
2021 		return;
2022 
2023 	toc_offset = rlc_autoload_info[id].offset;
2024 	toc_fw_size = rlc_autoload_info[id].size;
2025 
2026 	if (fw_size == 0)
2027 		fw_size = toc_fw_size;
2028 
2029 	if (fw_size > toc_fw_size)
2030 		fw_size = toc_fw_size;
2031 
2032 	memcpy(ptr + toc_offset, fw_data, fw_size);
2033 
2034 	if (fw_size < toc_fw_size)
2035 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
2036 }
2037 
2038 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
2039 {
2040 	void *data;
2041 	uint32_t size;
2042 
2043 	data = adev->gfx.rlc.rlc_toc_buf;
2044 	size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
2045 
2046 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2047 						   FIRMWARE_ID_RLC_TOC,
2048 						   data, size);
2049 }
2050 
2051 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
2052 {
2053 	const __le32 *fw_data;
2054 	uint32_t fw_size;
2055 	const struct gfx_firmware_header_v1_0 *cp_hdr;
2056 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
2057 
2058 	/* pfp ucode */
2059 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2060 		adev->gfx.pfp_fw->data;
2061 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2062 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2063 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2064 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2065 						   FIRMWARE_ID_CP_PFP,
2066 						   fw_data, fw_size);
2067 
2068 	/* ce ucode */
2069 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2070 		adev->gfx.ce_fw->data;
2071 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2072 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2073 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2074 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2075 						   FIRMWARE_ID_CP_CE,
2076 						   fw_data, fw_size);
2077 
2078 	/* me ucode */
2079 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2080 		adev->gfx.me_fw->data;
2081 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2082 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2083 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2084 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2085 						   FIRMWARE_ID_CP_ME,
2086 						   fw_data, fw_size);
2087 
2088 	/* rlc ucode */
2089 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
2090 		adev->gfx.rlc_fw->data;
2091 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2092 		le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
2093 	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
2094 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2095 						   FIRMWARE_ID_RLC_G_UCODE,
2096 						   fw_data, fw_size);
2097 
2098 	/* mec1 ucode */
2099 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2100 		adev->gfx.mec_fw->data;
2101 	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2102 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2103 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
2104 		cp_hdr->jt_size * 4;
2105 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2106 						   FIRMWARE_ID_CP_MEC,
2107 						   fw_data, fw_size);
2108 	/* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
2109 }
2110 
2111 /* Temporarily put sdma part here */
2112 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
2113 {
2114 	const __le32 *fw_data;
2115 	uint32_t fw_size;
2116 	const struct sdma_firmware_header_v1_0 *sdma_hdr;
2117 	int i;
2118 
2119 	for (i = 0; i < adev->sdma.num_instances; i++) {
2120 		sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
2121 			adev->sdma.instance[i].fw->data;
2122 		fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
2123 			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
2124 		fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
2125 
2126 		if (i == 0) {
2127 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2128 				FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
2129 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2130 				FIRMWARE_ID_SDMA0_JT,
2131 				(uint32_t *)fw_data +
2132 				sdma_hdr->jt_offset,
2133 				sdma_hdr->jt_size * 4);
2134 		} else if (i == 1) {
2135 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2136 				FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
2137 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2138 				FIRMWARE_ID_SDMA1_JT,
2139 				(uint32_t *)fw_data +
2140 				sdma_hdr->jt_offset,
2141 				sdma_hdr->jt_size * 4);
2142 		}
2143 	}
2144 }
2145 
2146 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
2147 {
2148 	uint32_t rlc_g_offset, rlc_g_size, tmp;
2149 	uint64_t gpu_addr;
2150 
2151 	gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
2152 	gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
2153 	gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
2154 
2155 	rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
2156 	rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
2157 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
2158 
2159 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2160 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2161 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
2162 
2163 	tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
2164 	if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
2165 		   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
2166 		DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
2167 		return -EINVAL;
2168 	}
2169 
2170 	tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2171 	if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2172 		DRM_ERROR("RLC ROM should halt itself\n");
2173 		return -EINVAL;
2174 	}
2175 
2176 	return 0;
2177 }
2178 
2179 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
2180 {
2181 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2182 	uint32_t tmp;
2183 	int i;
2184 	uint64_t addr;
2185 
2186 	/* Trigger an invalidation of the L1 instruction caches */
2187 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2188 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2189 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2190 
2191 	/* Wait for invalidation complete */
2192 	for (i = 0; i < usec_timeout; i++) {
2193 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2194 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2195 			INVALIDATE_CACHE_COMPLETE))
2196 			break;
2197 		udelay(1);
2198 	}
2199 
2200 	if (i >= usec_timeout) {
2201 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2202 		return -EINVAL;
2203 	}
2204 
2205 	/* Program me ucode address into intruction cache address register */
2206 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2207 		rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
2208 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2209 			lower_32_bits(addr) & 0xFFFFF000);
2210 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2211 			upper_32_bits(addr));
2212 
2213 	return 0;
2214 }
2215 
2216 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
2217 {
2218 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2219 	uint32_t tmp;
2220 	int i;
2221 	uint64_t addr;
2222 
2223 	/* Trigger an invalidation of the L1 instruction caches */
2224 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2225 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2226 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2227 
2228 	/* Wait for invalidation complete */
2229 	for (i = 0; i < usec_timeout; i++) {
2230 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2231 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2232 			INVALIDATE_CACHE_COMPLETE))
2233 			break;
2234 		udelay(1);
2235 	}
2236 
2237 	if (i >= usec_timeout) {
2238 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2239 		return -EINVAL;
2240 	}
2241 
2242 	/* Program ce ucode address into intruction cache address register */
2243 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2244 		rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
2245 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2246 			lower_32_bits(addr) & 0xFFFFF000);
2247 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2248 			upper_32_bits(addr));
2249 
2250 	return 0;
2251 }
2252 
2253 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
2254 {
2255 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2256 	uint32_t tmp;
2257 	int i;
2258 	uint64_t addr;
2259 
2260 	/* Trigger an invalidation of the L1 instruction caches */
2261 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2262 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2263 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2264 
2265 	/* Wait for invalidation complete */
2266 	for (i = 0; i < usec_timeout; i++) {
2267 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2268 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2269 			INVALIDATE_CACHE_COMPLETE))
2270 			break;
2271 		udelay(1);
2272 	}
2273 
2274 	if (i >= usec_timeout) {
2275 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2276 		return -EINVAL;
2277 	}
2278 
2279 	/* Program pfp ucode address into intruction cache address register */
2280 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2281 		rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
2282 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2283 			lower_32_bits(addr) & 0xFFFFF000);
2284 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2285 			upper_32_bits(addr));
2286 
2287 	return 0;
2288 }
2289 
2290 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
2291 {
2292 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2293 	uint32_t tmp;
2294 	int i;
2295 	uint64_t addr;
2296 
2297 	/* Trigger an invalidation of the L1 instruction caches */
2298 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2299 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2300 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2301 
2302 	/* Wait for invalidation complete */
2303 	for (i = 0; i < usec_timeout; i++) {
2304 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2305 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2306 			INVALIDATE_CACHE_COMPLETE))
2307 			break;
2308 		udelay(1);
2309 	}
2310 
2311 	if (i >= usec_timeout) {
2312 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2313 		return -EINVAL;
2314 	}
2315 
2316 	/* Program mec1 ucode address into intruction cache address register */
2317 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2318 		rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
2319 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2320 			lower_32_bits(addr) & 0xFFFFF000);
2321 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2322 			upper_32_bits(addr));
2323 
2324 	return 0;
2325 }
2326 
2327 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2328 {
2329 	uint32_t cp_status;
2330 	uint32_t bootload_status;
2331 	int i, r;
2332 
2333 	for (i = 0; i < adev->usec_timeout; i++) {
2334 		cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
2335 		bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
2336 		if ((cp_status == 0) &&
2337 		    (REG_GET_FIELD(bootload_status,
2338 			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2339 			break;
2340 		}
2341 		udelay(1);
2342 	}
2343 
2344 	if (i >= adev->usec_timeout) {
2345 		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2346 		return -ETIMEDOUT;
2347 	}
2348 
2349 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2350 		r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
2351 		if (r)
2352 			return r;
2353 
2354 		r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
2355 		if (r)
2356 			return r;
2357 
2358 		r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
2359 		if (r)
2360 			return r;
2361 
2362 		r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
2363 		if (r)
2364 			return r;
2365 	}
2366 
2367 	return 0;
2368 }
2369 
2370 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2371 {
2372 	int i;
2373 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2374 
2375 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2376 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2377 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2378 	if (!enable) {
2379 		for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2380 			adev->gfx.gfx_ring[i].sched.ready = false;
2381 	}
2382 	WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2383 
2384 	for (i = 0; i < adev->usec_timeout; i++) {
2385 		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
2386 			break;
2387 		udelay(1);
2388 	}
2389 
2390 	if (i >= adev->usec_timeout)
2391 		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2392 
2393 	return 0;
2394 }
2395 
2396 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2397 {
2398 	int r;
2399 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
2400 	const __le32 *fw_data;
2401 	unsigned i, fw_size;
2402 	uint32_t tmp;
2403 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2404 
2405 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2406 		adev->gfx.pfp_fw->data;
2407 
2408 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2409 
2410 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2411 		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2412 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2413 
2414 	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2415 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2416 				      &adev->gfx.pfp.pfp_fw_obj,
2417 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
2418 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
2419 	if (r) {
2420 		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2421 		gfx_v10_0_pfp_fini(adev);
2422 		return r;
2423 	}
2424 
2425 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2426 
2427 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2428 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2429 
2430 	/* Trigger an invalidation of the L1 instruction caches */
2431 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2432 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2433 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2434 
2435 	/* Wait for invalidation complete */
2436 	for (i = 0; i < usec_timeout; i++) {
2437 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2438 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2439 			INVALIDATE_CACHE_COMPLETE))
2440 			break;
2441 		udelay(1);
2442 	}
2443 
2444 	if (i >= usec_timeout) {
2445 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2446 		return -EINVAL;
2447 	}
2448 
2449 	if (amdgpu_emu_mode == 1)
2450 		adev->nbio.funcs->hdp_flush(adev, NULL);
2451 
2452 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
2453 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2454 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2455 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2456 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2457 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
2458 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2459 		adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
2460 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2461 		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2462 
2463 	return 0;
2464 }
2465 
2466 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
2467 {
2468 	int r;
2469 	const struct gfx_firmware_header_v1_0 *ce_hdr;
2470 	const __le32 *fw_data;
2471 	unsigned i, fw_size;
2472 	uint32_t tmp;
2473 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2474 
2475 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2476 		adev->gfx.ce_fw->data;
2477 
2478 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2479 
2480 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2481 		le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2482 	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
2483 
2484 	r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
2485 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2486 				      &adev->gfx.ce.ce_fw_obj,
2487 				      &adev->gfx.ce.ce_fw_gpu_addr,
2488 				      (void **)&adev->gfx.ce.ce_fw_ptr);
2489 	if (r) {
2490 		dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
2491 		gfx_v10_0_ce_fini(adev);
2492 		return r;
2493 	}
2494 
2495 	memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
2496 
2497 	amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
2498 	amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
2499 
2500 	/* Trigger an invalidation of the L1 instruction caches */
2501 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2502 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2503 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2504 
2505 	/* Wait for invalidation complete */
2506 	for (i = 0; i < usec_timeout; i++) {
2507 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2508 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2509 			INVALIDATE_CACHE_COMPLETE))
2510 			break;
2511 		udelay(1);
2512 	}
2513 
2514 	if (i >= usec_timeout) {
2515 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2516 		return -EINVAL;
2517 	}
2518 
2519 	if (amdgpu_emu_mode == 1)
2520 		adev->nbio.funcs->hdp_flush(adev, NULL);
2521 
2522 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
2523 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
2524 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
2525 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
2526 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2527 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2528 		adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
2529 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2530 		upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
2531 
2532 	return 0;
2533 }
2534 
2535 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2536 {
2537 	int r;
2538 	const struct gfx_firmware_header_v1_0 *me_hdr;
2539 	const __le32 *fw_data;
2540 	unsigned i, fw_size;
2541 	uint32_t tmp;
2542 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2543 
2544 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
2545 		adev->gfx.me_fw->data;
2546 
2547 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2548 
2549 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2550 		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2551 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2552 
2553 	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2554 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2555 				      &adev->gfx.me.me_fw_obj,
2556 				      &adev->gfx.me.me_fw_gpu_addr,
2557 				      (void **)&adev->gfx.me.me_fw_ptr);
2558 	if (r) {
2559 		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2560 		gfx_v10_0_me_fini(adev);
2561 		return r;
2562 	}
2563 
2564 	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2565 
2566 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2567 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2568 
2569 	/* Trigger an invalidation of the L1 instruction caches */
2570 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2571 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2572 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2573 
2574 	/* Wait for invalidation complete */
2575 	for (i = 0; i < usec_timeout; i++) {
2576 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2577 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2578 			INVALIDATE_CACHE_COMPLETE))
2579 			break;
2580 		udelay(1);
2581 	}
2582 
2583 	if (i >= usec_timeout) {
2584 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2585 		return -EINVAL;
2586 	}
2587 
2588 	if (amdgpu_emu_mode == 1)
2589 		adev->nbio.funcs->hdp_flush(adev, NULL);
2590 
2591 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
2592 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2593 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2594 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2595 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2596 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2597 		adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
2598 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2599 		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2600 
2601 	return 0;
2602 }
2603 
2604 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2605 {
2606 	int r;
2607 
2608 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2609 		return -EINVAL;
2610 
2611 	gfx_v10_0_cp_gfx_enable(adev, false);
2612 
2613 	r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
2614 	if (r) {
2615 		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2616 		return r;
2617 	}
2618 
2619 	r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
2620 	if (r) {
2621 		dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
2622 		return r;
2623 	}
2624 
2625 	r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
2626 	if (r) {
2627 		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2628 		return r;
2629 	}
2630 
2631 	return 0;
2632 }
2633 
2634 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
2635 {
2636 	struct amdgpu_ring *ring;
2637 	const struct cs_section_def *sect = NULL;
2638 	const struct cs_extent_def *ext = NULL;
2639 	int r, i;
2640 	int ctx_reg_offset;
2641 
2642 	/* init the CP */
2643 	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
2644 		     adev->gfx.config.max_hw_contexts - 1);
2645 	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2646 
2647 	gfx_v10_0_cp_gfx_enable(adev, true);
2648 
2649 	ring = &adev->gfx.gfx_ring[0];
2650 	r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
2651 	if (r) {
2652 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2653 		return r;
2654 	}
2655 
2656 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2657 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2658 
2659 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2660 	amdgpu_ring_write(ring, 0x80000000);
2661 	amdgpu_ring_write(ring, 0x80000000);
2662 
2663 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
2664 		for (ext = sect->section; ext->extent != NULL; ++ext) {
2665 			if (sect->id == SECT_CONTEXT) {
2666 				amdgpu_ring_write(ring,
2667 						  PACKET3(PACKET3_SET_CONTEXT_REG,
2668 							  ext->reg_count));
2669 				amdgpu_ring_write(ring, ext->reg_index -
2670 						  PACKET3_SET_CONTEXT_REG_START);
2671 				for (i = 0; i < ext->reg_count; i++)
2672 					amdgpu_ring_write(ring, ext->extent[i]);
2673 			}
2674 		}
2675 	}
2676 
2677 	ctx_reg_offset =
2678 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
2679 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2680 	amdgpu_ring_write(ring, ctx_reg_offset);
2681 	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
2682 
2683 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2684 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2685 
2686 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2687 	amdgpu_ring_write(ring, 0);
2688 
2689 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2690 	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2691 	amdgpu_ring_write(ring, 0x8000);
2692 	amdgpu_ring_write(ring, 0x8000);
2693 
2694 	amdgpu_ring_commit(ring);
2695 
2696 	/* submit cs packet to copy state 0 to next available state */
2697 	ring = &adev->gfx.gfx_ring[1];
2698 	r = amdgpu_ring_alloc(ring, 2);
2699 	if (r) {
2700 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2701 		return r;
2702 	}
2703 
2704 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2705 	amdgpu_ring_write(ring, 0);
2706 
2707 	amdgpu_ring_commit(ring);
2708 
2709 	return 0;
2710 }
2711 
2712 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2713 					 CP_PIPE_ID pipe)
2714 {
2715 	u32 tmp;
2716 
2717 	tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2718 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2719 
2720 	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
2721 }
2722 
2723 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2724 					  struct amdgpu_ring *ring)
2725 {
2726 	u32 tmp;
2727 
2728 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2729 	if (ring->use_doorbell) {
2730 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2731 				    DOORBELL_OFFSET, ring->doorbell_index);
2732 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2733 				    DOORBELL_EN, 1);
2734 	} else {
2735 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2736 				    DOORBELL_EN, 0);
2737 	}
2738 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2739 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2740 			    DOORBELL_RANGE_LOWER, ring->doorbell_index);
2741 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2742 
2743 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2744 		     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2745 }
2746 
2747 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
2748 {
2749 	struct amdgpu_ring *ring;
2750 	u32 tmp;
2751 	u32 rb_bufsz;
2752 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
2753 	u32 i;
2754 
2755 	/* Set the write pointer delay */
2756 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2757 
2758 	/* set the RB to use vmid 0 */
2759 	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2760 
2761 	/* Init gfx ring 0 for pipe 0 */
2762 	mutex_lock(&adev->srbm_mutex);
2763 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2764 
2765 	/* Set ring buffer size */
2766 	ring = &adev->gfx.gfx_ring[0];
2767 	rb_bufsz = order_base_2(ring->ring_size / 8);
2768 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2769 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2770 #ifdef __BIG_ENDIAN
2771 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2772 #endif
2773 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2774 
2775 	/* Initialize the ring buffer's write pointers */
2776 	ring->wptr = 0;
2777 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2778 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2779 
2780 	/* set the wb address wether it's enabled or not */
2781 	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2782 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2783 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2784 		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2785 
2786 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2787 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2788 		     lower_32_bits(wptr_gpu_addr));
2789 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2790 		     upper_32_bits(wptr_gpu_addr));
2791 
2792 	mdelay(1);
2793 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2794 
2795 	rb_addr = ring->gpu_addr >> 8;
2796 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2797 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2798 
2799 	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2800 
2801 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2802 	mutex_unlock(&adev->srbm_mutex);
2803 
2804 	/* Init gfx ring 1 for pipe 1 */
2805 	mutex_lock(&adev->srbm_mutex);
2806 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2807 	ring = &adev->gfx.gfx_ring[1];
2808 	rb_bufsz = order_base_2(ring->ring_size / 8);
2809 	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2810 	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2811 	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2812 	/* Initialize the ring buffer's write pointers */
2813 	ring->wptr = 0;
2814 	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2815 	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2816 	/* Set the wb address wether it's enabled or not */
2817 	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2818 	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2819 	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2820 		CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2821 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2822 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2823 		lower_32_bits(wptr_gpu_addr));
2824 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2825 		upper_32_bits(wptr_gpu_addr));
2826 
2827 	mdelay(1);
2828 	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2829 
2830 	rb_addr = ring->gpu_addr >> 8;
2831 	WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2832 	WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2833 	WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2834 
2835 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2836 	mutex_unlock(&adev->srbm_mutex);
2837 
2838 	/* Switch to pipe 0 */
2839 	mutex_lock(&adev->srbm_mutex);
2840 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2841 	mutex_unlock(&adev->srbm_mutex);
2842 
2843 	/* start the ring */
2844 	gfx_v10_0_cp_gfx_start(adev);
2845 
2846 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2847 		ring = &adev->gfx.gfx_ring[i];
2848 		ring->sched.ready = true;
2849 	}
2850 
2851 	return 0;
2852 }
2853 
2854 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2855 {
2856 	int i;
2857 
2858 	if (enable) {
2859 		WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2860 	} else {
2861 		WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2862 			     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2863 			      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2864 		for (i = 0; i < adev->gfx.num_compute_rings; i++)
2865 			adev->gfx.compute_ring[i].sched.ready = false;
2866 		adev->gfx.kiq.ring.sched.ready = false;
2867 	}
2868 	udelay(50);
2869 }
2870 
2871 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2872 {
2873 	const struct gfx_firmware_header_v1_0 *mec_hdr;
2874 	const __le32 *fw_data;
2875 	unsigned i;
2876 	u32 tmp;
2877 	u32 usec_timeout = 50000; /* Wait for 50 ms */
2878 
2879 	if (!adev->gfx.mec_fw)
2880 		return -EINVAL;
2881 
2882 	gfx_v10_0_cp_compute_enable(adev, false);
2883 
2884 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2885 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2886 
2887 	fw_data = (const __le32 *)
2888 		(adev->gfx.mec_fw->data +
2889 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2890 
2891 	/* Trigger an invalidation of the L1 instruction caches */
2892 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2893 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2894 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2895 
2896 	/* Wait for invalidation complete */
2897 	for (i = 0; i < usec_timeout; i++) {
2898 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2899 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2900 				       INVALIDATE_CACHE_COMPLETE))
2901 			break;
2902 		udelay(1);
2903 	}
2904 
2905 	if (i >= usec_timeout) {
2906 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2907 		return -EINVAL;
2908 	}
2909 
2910 	if (amdgpu_emu_mode == 1)
2911 		adev->nbio.funcs->hdp_flush(adev, NULL);
2912 
2913 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
2914 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2915 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2916 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2917 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2918 
2919 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
2920 		     0xFFFFF000);
2921 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2922 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2923 
2924 	/* MEC1 */
2925 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
2926 
2927 	for (i = 0; i < mec_hdr->jt_size; i++)
2928 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2929 			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2930 
2931 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2932 
2933 	/*
2934 	 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
2935 	 * different microcode than MEC1.
2936 	 */
2937 
2938 	return 0;
2939 }
2940 
2941 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
2942 {
2943 	uint32_t tmp;
2944 	struct amdgpu_device *adev = ring->adev;
2945 
2946 	/* tell RLC which is KIQ queue */
2947 	tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2948 	tmp &= 0xffffff00;
2949 	tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2950 	WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2951 	tmp |= 0x80;
2952 	WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2953 }
2954 
2955 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
2956 {
2957 	struct amdgpu_device *adev = ring->adev;
2958 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
2959 	uint64_t hqd_gpu_addr, wb_gpu_addr;
2960 	uint32_t tmp;
2961 	uint32_t rb_bufsz;
2962 
2963 	/* set up gfx hqd wptr */
2964 	mqd->cp_gfx_hqd_wptr = 0;
2965 	mqd->cp_gfx_hqd_wptr_hi = 0;
2966 
2967 	/* set the pointer to the MQD */
2968 	mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
2969 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2970 
2971 	/* set up mqd control */
2972 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
2973 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2974 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2975 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2976 	mqd->cp_gfx_mqd_control = tmp;
2977 
2978 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2979 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
2980 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
2981 	mqd->cp_gfx_hqd_vmid = 0;
2982 
2983 	/* set up default queue priority level
2984 	 * 0x0 = low priority, 0x1 = high priority */
2985 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
2986 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
2987 	mqd->cp_gfx_hqd_queue_priority = tmp;
2988 
2989 	/* set up time quantum */
2990 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
2991 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
2992 	mqd->cp_gfx_hqd_quantum = tmp;
2993 
2994 	/* set up gfx hqd base. this is similar as CP_RB_BASE */
2995 	hqd_gpu_addr = ring->gpu_addr >> 8;
2996 	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
2997 	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
2998 
2999 	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3000 	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3001 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3002 	mqd->cp_gfx_hqd_rptr_addr_hi =
3003 		upper_32_bits(wb_gpu_addr) & 0xffff;
3004 
3005 	/* set up rb_wptr_poll addr */
3006 	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3007 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3008 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3009 
3010 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3011 	rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
3012 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
3013 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3014 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3015 #ifdef __BIG_ENDIAN
3016 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3017 #endif
3018 	mqd->cp_gfx_hqd_cntl = tmp;
3019 
3020 	/* set up cp_doorbell_control */
3021 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3022 	if (ring->use_doorbell) {
3023 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3024 				    DOORBELL_OFFSET, ring->doorbell_index);
3025 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3026 				    DOORBELL_EN, 1);
3027 	} else
3028 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3029 				    DOORBELL_EN, 0);
3030 	mqd->cp_rb_doorbell_control = tmp;
3031 
3032 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3033 	ring->wptr = 0;
3034 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
3035 
3036 	/* active the queue */
3037 	mqd->cp_gfx_hqd_active = 1;
3038 
3039 	return 0;
3040 }
3041 
3042 #ifdef BRING_UP_DEBUG
3043 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3044 {
3045 	struct amdgpu_device *adev = ring->adev;
3046 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3047 
3048 	/* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3049 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3050 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3051 
3052 	/* set GFX_MQD_BASE */
3053 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3054 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3055 
3056 	/* set GFX_MQD_CONTROL */
3057 	WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3058 
3059 	/* set GFX_HQD_VMID to 0 */
3060 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3061 
3062 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
3063 			mqd->cp_gfx_hqd_queue_priority);
3064 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3065 
3066 	/* set GFX_HQD_BASE, similar as CP_RB_BASE */
3067 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3068 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3069 
3070 	/* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
3071 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3072 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3073 
3074 	/* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
3075 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3076 
3077 	/* set RB_WPTR_POLL_ADDR */
3078 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3079 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3080 
3081 	/* set RB_DOORBELL_CONTROL */
3082 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3083 
3084 	/* active the queue */
3085 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3086 
3087 	return 0;
3088 }
3089 #endif
3090 
3091 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
3092 {
3093 	struct amdgpu_device *adev = ring->adev;
3094 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3095 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3096 
3097 	if (!adev->in_gpu_reset && !adev->in_suspend) {
3098 		memset((void *)mqd, 0, sizeof(*mqd));
3099 		mutex_lock(&adev->srbm_mutex);
3100 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3101 		gfx_v10_0_gfx_mqd_init(ring);
3102 #ifdef BRING_UP_DEBUG
3103 		gfx_v10_0_gfx_queue_init_register(ring);
3104 #endif
3105 		nv_grbm_select(adev, 0, 0, 0, 0);
3106 		mutex_unlock(&adev->srbm_mutex);
3107 		if (adev->gfx.me.mqd_backup[mqd_idx])
3108 			memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3109 	} else if (adev->in_gpu_reset) {
3110 		/* reset mqd with the backup copy */
3111 		if (adev->gfx.me.mqd_backup[mqd_idx])
3112 			memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3113 		/* reset the ring */
3114 		ring->wptr = 0;
3115 		adev->wb.wb[ring->wptr_offs] = 0;
3116 		amdgpu_ring_clear_ring(ring);
3117 #ifdef BRING_UP_DEBUG
3118 		mutex_lock(&adev->srbm_mutex);
3119 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3120 		gfx_v10_0_gfx_queue_init_register(ring);
3121 		nv_grbm_select(adev, 0, 0, 0, 0);
3122 		mutex_unlock(&adev->srbm_mutex);
3123 #endif
3124 	} else {
3125 		amdgpu_ring_clear_ring(ring);
3126 	}
3127 
3128 	return 0;
3129 }
3130 
3131 #ifndef BRING_UP_DEBUG
3132 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
3133 {
3134 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3135 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3136 	int r, i;
3137 
3138 	if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3139 		return -EINVAL;
3140 
3141 	r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3142 					adev->gfx.num_gfx_rings);
3143 	if (r) {
3144 		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3145 		return r;
3146 	}
3147 
3148 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3149 		kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3150 
3151 	r = amdgpu_ring_test_ring(kiq_ring);
3152 	if (r) {
3153 		DRM_ERROR("kfq enable failed\n");
3154 		kiq_ring->sched.ready = false;
3155 	}
3156 	return r;
3157 }
3158 #endif
3159 
3160 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3161 {
3162 	int r, i;
3163 	struct amdgpu_ring *ring;
3164 
3165 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3166 		ring = &adev->gfx.gfx_ring[i];
3167 
3168 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
3169 		if (unlikely(r != 0))
3170 			goto done;
3171 
3172 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3173 		if (!r) {
3174 			r = gfx_v10_0_gfx_init_queue(ring);
3175 			amdgpu_bo_kunmap(ring->mqd_obj);
3176 			ring->mqd_ptr = NULL;
3177 		}
3178 		amdgpu_bo_unreserve(ring->mqd_obj);
3179 		if (r)
3180 			goto done;
3181 	}
3182 #ifndef BRING_UP_DEBUG
3183 	r = gfx_v10_0_kiq_enable_kgq(adev);
3184 	if (r)
3185 		goto done;
3186 #endif
3187 	r = gfx_v10_0_cp_gfx_start(adev);
3188 	if (r)
3189 		goto done;
3190 
3191 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3192 		ring = &adev->gfx.gfx_ring[i];
3193 		ring->sched.ready = true;
3194 	}
3195 done:
3196 	return r;
3197 }
3198 
3199 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
3200 {
3201 	struct amdgpu_device *adev = ring->adev;
3202 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
3203 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3204 	uint32_t tmp;
3205 
3206 	mqd->header = 0xC0310800;
3207 	mqd->compute_pipelinestat_enable = 0x00000001;
3208 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3209 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3210 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3211 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3212 	mqd->compute_misc_reserved = 0x00000003;
3213 
3214 	eop_base_addr = ring->eop_gpu_addr >> 8;
3215 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3216 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3217 
3218 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3219 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3220 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3221 			(order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
3222 
3223 	mqd->cp_hqd_eop_control = tmp;
3224 
3225 	/* enable doorbell? */
3226 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3227 
3228 	if (ring->use_doorbell) {
3229 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3230 				    DOORBELL_OFFSET, ring->doorbell_index);
3231 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3232 				    DOORBELL_EN, 1);
3233 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3234 				    DOORBELL_SOURCE, 0);
3235 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3236 				    DOORBELL_HIT, 0);
3237 	} else {
3238 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3239 				    DOORBELL_EN, 0);
3240 	}
3241 
3242 	mqd->cp_hqd_pq_doorbell_control = tmp;
3243 
3244 	/* disable the queue if it's active */
3245 	ring->wptr = 0;
3246 	mqd->cp_hqd_dequeue_request = 0;
3247 	mqd->cp_hqd_pq_rptr = 0;
3248 	mqd->cp_hqd_pq_wptr_lo = 0;
3249 	mqd->cp_hqd_pq_wptr_hi = 0;
3250 
3251 	/* set the pointer to the MQD */
3252 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3253 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3254 
3255 	/* set MQD vmid to 0 */
3256 	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3257 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3258 	mqd->cp_mqd_control = tmp;
3259 
3260 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3261 	hqd_gpu_addr = ring->gpu_addr >> 8;
3262 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3263 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3264 
3265 	/* set up the HQD, this is similar to CP_RB0_CNTL */
3266 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3267 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3268 			    (order_base_2(ring->ring_size / 4) - 1));
3269 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3270 			    ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3271 #ifdef __BIG_ENDIAN
3272 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3273 #endif
3274 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3275 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3276 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3277 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3278 	mqd->cp_hqd_pq_control = tmp;
3279 
3280 	/* set the wb address whether it's enabled or not */
3281 	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3282 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3283 	mqd->cp_hqd_pq_rptr_report_addr_hi =
3284 		upper_32_bits(wb_gpu_addr) & 0xffff;
3285 
3286 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3287 	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3288 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3289 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3290 
3291 	tmp = 0;
3292 	/* enable the doorbell if requested */
3293 	if (ring->use_doorbell) {
3294 		tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3295 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3296 				DOORBELL_OFFSET, ring->doorbell_index);
3297 
3298 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3299 				    DOORBELL_EN, 1);
3300 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3301 				    DOORBELL_SOURCE, 0);
3302 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3303 				    DOORBELL_HIT, 0);
3304 	}
3305 
3306 	mqd->cp_hqd_pq_doorbell_control = tmp;
3307 
3308 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3309 	ring->wptr = 0;
3310 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3311 
3312 	/* set the vmid for the queue */
3313 	mqd->cp_hqd_vmid = 0;
3314 
3315 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3316 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3317 	mqd->cp_hqd_persistent_state = tmp;
3318 
3319 	/* set MIN_IB_AVAIL_SIZE */
3320 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3321 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3322 	mqd->cp_hqd_ib_control = tmp;
3323 
3324 	/* activate the queue */
3325 	mqd->cp_hqd_active = 1;
3326 
3327 	return 0;
3328 }
3329 
3330 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
3331 {
3332 	struct amdgpu_device *adev = ring->adev;
3333 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
3334 	int j;
3335 
3336 	/* disable wptr polling */
3337 	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3338 
3339 	/* write the EOP addr */
3340 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3341 	       mqd->cp_hqd_eop_base_addr_lo);
3342 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3343 	       mqd->cp_hqd_eop_base_addr_hi);
3344 
3345 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3346 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3347 	       mqd->cp_hqd_eop_control);
3348 
3349 	/* enable doorbell? */
3350 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3351 	       mqd->cp_hqd_pq_doorbell_control);
3352 
3353 	/* disable the queue if it's active */
3354 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3355 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3356 		for (j = 0; j < adev->usec_timeout; j++) {
3357 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3358 				break;
3359 			udelay(1);
3360 		}
3361 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3362 		       mqd->cp_hqd_dequeue_request);
3363 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3364 		       mqd->cp_hqd_pq_rptr);
3365 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3366 		       mqd->cp_hqd_pq_wptr_lo);
3367 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3368 		       mqd->cp_hqd_pq_wptr_hi);
3369 	}
3370 
3371 	/* set the pointer to the MQD */
3372 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3373 	       mqd->cp_mqd_base_addr_lo);
3374 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3375 	       mqd->cp_mqd_base_addr_hi);
3376 
3377 	/* set MQD vmid to 0 */
3378 	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3379 	       mqd->cp_mqd_control);
3380 
3381 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3382 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3383 	       mqd->cp_hqd_pq_base_lo);
3384 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3385 	       mqd->cp_hqd_pq_base_hi);
3386 
3387 	/* set up the HQD, this is similar to CP_RB0_CNTL */
3388 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3389 	       mqd->cp_hqd_pq_control);
3390 
3391 	/* set the wb address whether it's enabled or not */
3392 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3393 		mqd->cp_hqd_pq_rptr_report_addr_lo);
3394 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3395 		mqd->cp_hqd_pq_rptr_report_addr_hi);
3396 
3397 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3398 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3399 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
3400 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3401 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
3402 
3403 	/* enable the doorbell if requested */
3404 	if (ring->use_doorbell) {
3405 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3406 			(adev->doorbell_index.kiq * 2) << 2);
3407 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3408 			(adev->doorbell_index.userqueue_end * 2) << 2);
3409 	}
3410 
3411 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3412 	       mqd->cp_hqd_pq_doorbell_control);
3413 
3414 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3415 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3416 	       mqd->cp_hqd_pq_wptr_lo);
3417 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3418 	       mqd->cp_hqd_pq_wptr_hi);
3419 
3420 	/* set the vmid for the queue */
3421 	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3422 
3423 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3424 	       mqd->cp_hqd_persistent_state);
3425 
3426 	/* activate the queue */
3427 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3428 	       mqd->cp_hqd_active);
3429 
3430 	if (ring->use_doorbell)
3431 		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3432 
3433 	return 0;
3434 }
3435 
3436 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
3437 {
3438 	struct amdgpu_device *adev = ring->adev;
3439 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
3440 	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3441 
3442 	gfx_v10_0_kiq_setting(ring);
3443 
3444 	if (adev->in_gpu_reset) { /* for GPU_RESET case */
3445 		/* reset MQD to a clean status */
3446 		if (adev->gfx.mec.mqd_backup[mqd_idx])
3447 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3448 
3449 		/* reset ring buffer */
3450 		ring->wptr = 0;
3451 		amdgpu_ring_clear_ring(ring);
3452 
3453 		mutex_lock(&adev->srbm_mutex);
3454 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3455 		gfx_v10_0_kiq_init_register(ring);
3456 		nv_grbm_select(adev, 0, 0, 0, 0);
3457 		mutex_unlock(&adev->srbm_mutex);
3458 	} else {
3459 		memset((void *)mqd, 0, sizeof(*mqd));
3460 		mutex_lock(&adev->srbm_mutex);
3461 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3462 		gfx_v10_0_compute_mqd_init(ring);
3463 		gfx_v10_0_kiq_init_register(ring);
3464 		nv_grbm_select(adev, 0, 0, 0, 0);
3465 		mutex_unlock(&adev->srbm_mutex);
3466 
3467 		if (adev->gfx.mec.mqd_backup[mqd_idx])
3468 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3469 	}
3470 
3471 	return 0;
3472 }
3473 
3474 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
3475 {
3476 	struct amdgpu_device *adev = ring->adev;
3477 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
3478 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
3479 
3480 	if (!adev->in_gpu_reset && !adev->in_suspend) {
3481 		memset((void *)mqd, 0, sizeof(*mqd));
3482 		mutex_lock(&adev->srbm_mutex);
3483 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3484 		gfx_v10_0_compute_mqd_init(ring);
3485 		nv_grbm_select(adev, 0, 0, 0, 0);
3486 		mutex_unlock(&adev->srbm_mutex);
3487 
3488 		if (adev->gfx.mec.mqd_backup[mqd_idx])
3489 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3490 	} else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3491 		/* reset MQD to a clean status */
3492 		if (adev->gfx.mec.mqd_backup[mqd_idx])
3493 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3494 
3495 		/* reset ring buffer */
3496 		ring->wptr = 0;
3497 		amdgpu_ring_clear_ring(ring);
3498 	} else {
3499 		amdgpu_ring_clear_ring(ring);
3500 	}
3501 
3502 	return 0;
3503 }
3504 
3505 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
3506 {
3507 	struct amdgpu_ring *ring;
3508 	int r;
3509 
3510 	ring = &adev->gfx.kiq.ring;
3511 
3512 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
3513 	if (unlikely(r != 0))
3514 		return r;
3515 
3516 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3517 	if (unlikely(r != 0))
3518 		return r;
3519 
3520 	gfx_v10_0_kiq_init_queue(ring);
3521 	amdgpu_bo_kunmap(ring->mqd_obj);
3522 	ring->mqd_ptr = NULL;
3523 	amdgpu_bo_unreserve(ring->mqd_obj);
3524 	ring->sched.ready = true;
3525 	return 0;
3526 }
3527 
3528 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
3529 {
3530 	struct amdgpu_ring *ring = NULL;
3531 	int r = 0, i;
3532 
3533 	gfx_v10_0_cp_compute_enable(adev, true);
3534 
3535 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3536 		ring = &adev->gfx.compute_ring[i];
3537 
3538 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
3539 		if (unlikely(r != 0))
3540 			goto done;
3541 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3542 		if (!r) {
3543 			r = gfx_v10_0_kcq_init_queue(ring);
3544 			amdgpu_bo_kunmap(ring->mqd_obj);
3545 			ring->mqd_ptr = NULL;
3546 		}
3547 		amdgpu_bo_unreserve(ring->mqd_obj);
3548 		if (r)
3549 			goto done;
3550 	}
3551 
3552 	r = amdgpu_gfx_enable_kcq(adev);
3553 done:
3554 	return r;
3555 }
3556 
3557 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
3558 {
3559 	int r, i;
3560 	struct amdgpu_ring *ring;
3561 
3562 	if (!(adev->flags & AMD_IS_APU))
3563 		gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3564 
3565 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3566 		/* legacy firmware loading */
3567 		r = gfx_v10_0_cp_gfx_load_microcode(adev);
3568 		if (r)
3569 			return r;
3570 
3571 		r = gfx_v10_0_cp_compute_load_microcode(adev);
3572 		if (r)
3573 			return r;
3574 	}
3575 
3576 	r = gfx_v10_0_kiq_resume(adev);
3577 	if (r)
3578 		return r;
3579 
3580 	r = gfx_v10_0_kcq_resume(adev);
3581 	if (r)
3582 		return r;
3583 
3584 	if (!amdgpu_async_gfx_ring) {
3585 		r = gfx_v10_0_cp_gfx_resume(adev);
3586 		if (r)
3587 			return r;
3588 	} else {
3589 		r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
3590 		if (r)
3591 			return r;
3592 	}
3593 
3594 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3595 		ring = &adev->gfx.gfx_ring[i];
3596 		r = amdgpu_ring_test_helper(ring);
3597 		if (r)
3598 			return r;
3599 	}
3600 
3601 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3602 		ring = &adev->gfx.compute_ring[i];
3603 		r = amdgpu_ring_test_helper(ring);
3604 		if (r)
3605 			return r;
3606 	}
3607 
3608 	return 0;
3609 }
3610 
3611 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
3612 {
3613 	gfx_v10_0_cp_gfx_enable(adev, enable);
3614 	gfx_v10_0_cp_compute_enable(adev, enable);
3615 }
3616 
3617 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
3618 {
3619 	uint32_t data, pattern = 0xDEADBEEF;
3620 
3621 	/* check if mmVGT_ESGS_RING_SIZE_UMD
3622 	 * has been remapped to mmVGT_ESGS_RING_SIZE */
3623 	data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
3624 
3625 	WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
3626 
3627 	WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
3628 
3629 	if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
3630 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
3631 		return true;
3632 	} else {
3633 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
3634 		return false;
3635 	}
3636 }
3637 
3638 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
3639 {
3640 	uint32_t data;
3641 
3642 	/* initialize cam_index to 0
3643 	 * index will auto-inc after each data writting */
3644 	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
3645 
3646 	/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
3647 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
3648 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3649 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
3650 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3651 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3652 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3653 
3654 	/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
3655 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
3656 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3657 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
3658 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3659 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3660 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3661 
3662 	/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
3663 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
3664 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3665 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
3666 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3667 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3668 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3669 
3670 	/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
3671 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
3672 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3673 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
3674 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3675 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3676 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3677 
3678 	/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
3679 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
3680 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3681 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
3682 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3683 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3684 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3685 
3686 	/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
3687 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
3688 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3689 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
3690 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3691 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3692 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3693 
3694 	/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
3695 	data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
3696 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3697 	       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
3698 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3699 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3700 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3701 }
3702 
3703 static int gfx_v10_0_hw_init(void *handle)
3704 {
3705 	int r;
3706 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3707 
3708 	if (!amdgpu_emu_mode)
3709 		gfx_v10_0_init_golden_registers(adev);
3710 
3711 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3712 		/**
3713 		 * For gfx 10, rlc firmware loading relies on smu firmware is
3714 		 * loaded firstly, so in direct type, it has to load smc ucode
3715 		 * here before rlc.
3716 		 */
3717 		r = smu_load_microcode(&adev->smu);
3718 		if (r)
3719 			return r;
3720 
3721 		r = smu_check_fw_status(&adev->smu);
3722 		if (r) {
3723 			pr_err("SMC firmware status is not correct\n");
3724 			return r;
3725 		}
3726 	}
3727 
3728 	/* if GRBM CAM not remapped, set up the remapping */
3729 	if (!gfx_v10_0_check_grbm_cam_remapping(adev))
3730 		gfx_v10_0_setup_grbm_cam_remapping(adev);
3731 
3732 	gfx_v10_0_constants_init(adev);
3733 
3734 	r = gfx_v10_0_rlc_resume(adev);
3735 	if (r)
3736 		return r;
3737 
3738 	/*
3739 	 * init golden registers and rlc resume may override some registers,
3740 	 * reconfig them here
3741 	 */
3742 	gfx_v10_0_tcp_harvest(adev);
3743 
3744 	r = gfx_v10_0_cp_resume(adev);
3745 	if (r)
3746 		return r;
3747 
3748 	return r;
3749 }
3750 
3751 #ifndef BRING_UP_DEBUG
3752 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
3753 {
3754 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3755 	struct amdgpu_ring *kiq_ring = &kiq->ring;
3756 	int i;
3757 
3758 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
3759 		return -EINVAL;
3760 
3761 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
3762 					adev->gfx.num_gfx_rings))
3763 		return -ENOMEM;
3764 
3765 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3766 		kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
3767 					   PREEMPT_QUEUES, 0, 0);
3768 
3769 	return amdgpu_ring_test_ring(kiq_ring);
3770 }
3771 #endif
3772 
3773 static int gfx_v10_0_hw_fini(void *handle)
3774 {
3775 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3776 	int r;
3777 
3778 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3779 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3780 #ifndef BRING_UP_DEBUG
3781 	if (amdgpu_async_gfx_ring) {
3782 		r = gfx_v10_0_kiq_disable_kgq(adev);
3783 		if (r)
3784 			DRM_ERROR("KGQ disable failed\n");
3785 	}
3786 #endif
3787 	if (amdgpu_gfx_disable_kcq(adev))
3788 		DRM_ERROR("KCQ disable failed\n");
3789 	if (amdgpu_sriov_vf(adev)) {
3790 		gfx_v10_0_cp_gfx_enable(adev, false);
3791 		return 0;
3792 	}
3793 	gfx_v10_0_cp_enable(adev, false);
3794 	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3795 
3796 	return 0;
3797 }
3798 
3799 static int gfx_v10_0_suspend(void *handle)
3800 {
3801 	return gfx_v10_0_hw_fini(handle);
3802 }
3803 
3804 static int gfx_v10_0_resume(void *handle)
3805 {
3806 	return gfx_v10_0_hw_init(handle);
3807 }
3808 
3809 static bool gfx_v10_0_is_idle(void *handle)
3810 {
3811 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3812 
3813 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3814 				GRBM_STATUS, GUI_ACTIVE))
3815 		return false;
3816 	else
3817 		return true;
3818 }
3819 
3820 static int gfx_v10_0_wait_for_idle(void *handle)
3821 {
3822 	unsigned i;
3823 	u32 tmp;
3824 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3825 
3826 	for (i = 0; i < adev->usec_timeout; i++) {
3827 		/* read MC_STATUS */
3828 		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3829 			GRBM_STATUS__GUI_ACTIVE_MASK;
3830 
3831 		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3832 			return 0;
3833 		udelay(1);
3834 	}
3835 	return -ETIMEDOUT;
3836 }
3837 
3838 static int gfx_v10_0_soft_reset(void *handle)
3839 {
3840 	u32 grbm_soft_reset = 0;
3841 	u32 tmp;
3842 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3843 
3844 	/* GRBM_STATUS */
3845 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3846 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3847 		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3848 		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
3849 		   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
3850 		   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
3851 		   | GRBM_STATUS__BCI_BUSY_MASK)) {
3852 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3853 						GRBM_SOFT_RESET, SOFT_RESET_CP,
3854 						1);
3855 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3856 						GRBM_SOFT_RESET, SOFT_RESET_GFX,
3857 						1);
3858 	}
3859 
3860 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3861 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3862 						GRBM_SOFT_RESET, SOFT_RESET_CP,
3863 						1);
3864 	}
3865 
3866 	/* GRBM_STATUS2 */
3867 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3868 	if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3869 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3870 						GRBM_SOFT_RESET, SOFT_RESET_RLC,
3871 						1);
3872 
3873 	if (grbm_soft_reset) {
3874 		/* stop the rlc */
3875 		gfx_v10_0_rlc_stop(adev);
3876 
3877 		/* Disable GFX parsing/prefetching */
3878 		gfx_v10_0_cp_gfx_enable(adev, false);
3879 
3880 		/* Disable MEC parsing/prefetching */
3881 		gfx_v10_0_cp_compute_enable(adev, false);
3882 
3883 		if (grbm_soft_reset) {
3884 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3885 			tmp |= grbm_soft_reset;
3886 			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3887 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3888 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3889 
3890 			udelay(50);
3891 
3892 			tmp &= ~grbm_soft_reset;
3893 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3894 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3895 		}
3896 
3897 		/* Wait a little for things to settle down */
3898 		udelay(50);
3899 	}
3900 	return 0;
3901 }
3902 
3903 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3904 {
3905 	uint64_t clock;
3906 
3907 	mutex_lock(&adev->gfx.gpu_clock_mutex);
3908 	WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3909 	clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3910 		((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3911 	mutex_unlock(&adev->gfx.gpu_clock_mutex);
3912 	return clock;
3913 }
3914 
3915 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3916 					   uint32_t vmid,
3917 					   uint32_t gds_base, uint32_t gds_size,
3918 					   uint32_t gws_base, uint32_t gws_size,
3919 					   uint32_t oa_base, uint32_t oa_size)
3920 {
3921 	struct amdgpu_device *adev = ring->adev;
3922 
3923 	/* GDS Base */
3924 	gfx_v10_0_write_data_to_reg(ring, 0, false,
3925 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3926 				    gds_base);
3927 
3928 	/* GDS Size */
3929 	gfx_v10_0_write_data_to_reg(ring, 0, false,
3930 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3931 				    gds_size);
3932 
3933 	/* GWS */
3934 	gfx_v10_0_write_data_to_reg(ring, 0, false,
3935 				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3936 				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3937 
3938 	/* OA */
3939 	gfx_v10_0_write_data_to_reg(ring, 0, false,
3940 				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3941 				    (1 << (oa_size + oa_base)) - (1 << oa_base));
3942 }
3943 
3944 static int gfx_v10_0_early_init(void *handle)
3945 {
3946 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3947 
3948 	adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;
3949 	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3950 
3951 	gfx_v10_0_set_kiq_pm4_funcs(adev);
3952 	gfx_v10_0_set_ring_funcs(adev);
3953 	gfx_v10_0_set_irq_funcs(adev);
3954 	gfx_v10_0_set_gds_init(adev);
3955 	gfx_v10_0_set_rlc_funcs(adev);
3956 
3957 	return 0;
3958 }
3959 
3960 static int gfx_v10_0_late_init(void *handle)
3961 {
3962 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3963 	int r;
3964 
3965 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3966 	if (r)
3967 		return r;
3968 
3969 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3970 	if (r)
3971 		return r;
3972 
3973 	return 0;
3974 }
3975 
3976 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
3977 {
3978 	uint32_t rlc_cntl;
3979 
3980 	/* if RLC is not enabled, do nothing */
3981 	rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3982 	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
3983 }
3984 
3985 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
3986 {
3987 	uint32_t data;
3988 	unsigned i;
3989 
3990 	data = RLC_SAFE_MODE__CMD_MASK;
3991 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3992 	WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3993 
3994 	/* wait for RLC_SAFE_MODE */
3995 	for (i = 0; i < adev->usec_timeout; i++) {
3996 		if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3997 			break;
3998 		udelay(1);
3999 	}
4000 }
4001 
4002 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
4003 {
4004 	uint32_t data;
4005 
4006 	data = RLC_SAFE_MODE__CMD_MASK;
4007 	WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4008 }
4009 
4010 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4011 						      bool enable)
4012 {
4013 	uint32_t data, def;
4014 
4015 	/* It is disabled by HW by default */
4016 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4017 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
4018 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4019 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4020 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4021 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4022 
4023 		/* only for Vega10 & Raven1 */
4024 		data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4025 
4026 		if (def != data)
4027 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4028 
4029 		/* MGLS is a global flag to control all MGLS in GFX */
4030 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4031 			/* 2 - RLC memory Light sleep */
4032 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4033 				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4034 				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4035 				if (def != data)
4036 					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4037 			}
4038 			/* 3 - CP memory Light sleep */
4039 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4040 				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4041 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4042 				if (def != data)
4043 					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4044 			}
4045 		}
4046 	} else {
4047 		/* 1 - MGCG_OVERRIDE */
4048 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4049 		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4050 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4051 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4052 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4053 		if (def != data)
4054 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4055 
4056 		/* 2 - disable MGLS in RLC */
4057 		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4058 		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4059 			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4060 			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4061 		}
4062 
4063 		/* 3 - disable MGLS in CP */
4064 		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4065 		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4066 			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4067 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4068 		}
4069 	}
4070 }
4071 
4072 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
4073 					   bool enable)
4074 {
4075 	uint32_t data, def;
4076 
4077 	/* Enable 3D CGCG/CGLS */
4078 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
4079 		/* write cmd to clear cgcg/cgls ov */
4080 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4081 		/* unset CGCG override */
4082 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4083 		/* update CGCG and CGLS override bits */
4084 		if (def != data)
4085 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4086 		/* enable 3Dcgcg FSM(0x0000363f) */
4087 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4088 		data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4089 			RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4090 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4091 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4092 				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4093 		if (def != data)
4094 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4095 
4096 		/* set IDLE_POLL_COUNT(0x00900100) */
4097 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4098 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4099 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4100 		if (def != data)
4101 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4102 	} else {
4103 		/* Disable CGCG/CGLS */
4104 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4105 		/* disable cgcg, cgls should be disabled */
4106 		data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4107 			  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4108 		/* disable cgcg and cgls in FSM */
4109 		if (def != data)
4110 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4111 	}
4112 }
4113 
4114 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4115 						      bool enable)
4116 {
4117 	uint32_t def, data;
4118 
4119 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4120 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4121 		/* unset CGCG override */
4122 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4123 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4124 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4125 		else
4126 			data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4127 		/* update CGCG and CGLS override bits */
4128 		if (def != data)
4129 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4130 
4131 		/* enable cgcg FSM(0x0000363F) */
4132 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4133 		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4134 			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4135 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4136 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4137 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4138 		if (def != data)
4139 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4140 
4141 		/* set IDLE_POLL_COUNT(0x00900100) */
4142 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4143 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4144 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4145 		if (def != data)
4146 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4147 	} else {
4148 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4149 		/* reset CGCG/CGLS bits */
4150 		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4151 		/* disable cgcg and cgls in FSM */
4152 		if (def != data)
4153 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4154 	}
4155 }
4156 
4157 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4158 					    bool enable)
4159 {
4160 	amdgpu_gfx_rlc_enter_safe_mode(adev);
4161 
4162 	if (enable) {
4163 		/* CGCG/CGLS should be enabled after MGCG/MGLS
4164 		 * ===  MGCG + MGLS ===
4165 		 */
4166 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4167 		/* ===  CGCG /CGLS for GFX 3D Only === */
4168 		gfx_v10_0_update_3d_clock_gating(adev, enable);
4169 		/* ===  CGCG + CGLS === */
4170 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4171 	} else {
4172 		/* CGCG/CGLS should be disabled before MGCG/MGLS
4173 		 * ===  CGCG + CGLS ===
4174 		 */
4175 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4176 		/* ===  CGCG /CGLS for GFX 3D Only === */
4177 		gfx_v10_0_update_3d_clock_gating(adev, enable);
4178 		/* ===  MGCG + MGLS === */
4179 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4180 	}
4181 
4182 	if (adev->cg_flags &
4183 	    (AMD_CG_SUPPORT_GFX_MGCG |
4184 	     AMD_CG_SUPPORT_GFX_CGLS |
4185 	     AMD_CG_SUPPORT_GFX_CGCG |
4186 	     AMD_CG_SUPPORT_GFX_CGLS |
4187 	     AMD_CG_SUPPORT_GFX_3D_CGCG |
4188 	     AMD_CG_SUPPORT_GFX_3D_CGLS))
4189 		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
4190 
4191 	amdgpu_gfx_rlc_exit_safe_mode(adev);
4192 
4193 	return 0;
4194 }
4195 
4196 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
4197 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
4198 	.set_safe_mode = gfx_v10_0_set_safe_mode,
4199 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
4200 	.init = gfx_v10_0_rlc_init,
4201 	.get_csb_size = gfx_v10_0_get_csb_size,
4202 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
4203 	.resume = gfx_v10_0_rlc_resume,
4204 	.stop = gfx_v10_0_rlc_stop,
4205 	.reset = gfx_v10_0_rlc_reset,
4206 	.start = gfx_v10_0_rlc_start
4207 };
4208 
4209 static int gfx_v10_0_set_powergating_state(void *handle,
4210 					  enum amd_powergating_state state)
4211 {
4212 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4213 	bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
4214 	switch (adev->asic_type) {
4215 	case CHIP_NAVI10:
4216 	case CHIP_NAVI14:
4217 		if (!enable) {
4218 			amdgpu_gfx_off_ctrl(adev, false);
4219 			cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
4220 		} else
4221 			amdgpu_gfx_off_ctrl(adev, true);
4222 		break;
4223 	default:
4224 		break;
4225 	}
4226 	return 0;
4227 }
4228 
4229 static int gfx_v10_0_set_clockgating_state(void *handle,
4230 					  enum amd_clockgating_state state)
4231 {
4232 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4233 
4234 	switch (adev->asic_type) {
4235 	case CHIP_NAVI10:
4236 	case CHIP_NAVI14:
4237 	case CHIP_NAVI12:
4238 		gfx_v10_0_update_gfx_clock_gating(adev,
4239 						 state == AMD_CG_STATE_GATE ? true : false);
4240 		break;
4241 	default:
4242 		break;
4243 	}
4244 	return 0;
4245 }
4246 
4247 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
4248 {
4249 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4250 	int data;
4251 
4252 	/* AMD_CG_SUPPORT_GFX_MGCG */
4253 	data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4254 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4255 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
4256 
4257 	/* AMD_CG_SUPPORT_GFX_CGCG */
4258 	data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4259 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4260 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
4261 
4262 	/* AMD_CG_SUPPORT_GFX_CGLS */
4263 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4264 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
4265 
4266 	/* AMD_CG_SUPPORT_GFX_RLC_LS */
4267 	data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4268 	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
4269 		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
4270 
4271 	/* AMD_CG_SUPPORT_GFX_CP_LS */
4272 	data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4273 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
4274 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
4275 
4276 	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
4277 	data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4278 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4279 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4280 
4281 	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
4282 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4283 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4284 }
4285 
4286 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4287 {
4288 	return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
4289 }
4290 
4291 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4292 {
4293 	struct amdgpu_device *adev = ring->adev;
4294 	u64 wptr;
4295 
4296 	/* XXX check if swapping is necessary on BE */
4297 	if (ring->use_doorbell) {
4298 		wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4299 	} else {
4300 		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4301 		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4302 	}
4303 
4304 	return wptr;
4305 }
4306 
4307 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4308 {
4309 	struct amdgpu_device *adev = ring->adev;
4310 
4311 	if (ring->use_doorbell) {
4312 		/* XXX check if swapping is necessary on BE */
4313 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4314 		WDOORBELL64(ring->doorbell_index, ring->wptr);
4315 	} else {
4316 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4317 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4318 	}
4319 }
4320 
4321 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4322 {
4323 	return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
4324 }
4325 
4326 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4327 {
4328 	u64 wptr;
4329 
4330 	/* XXX check if swapping is necessary on BE */
4331 	if (ring->use_doorbell)
4332 		wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4333 	else
4334 		BUG();
4335 	return wptr;
4336 }
4337 
4338 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4339 {
4340 	struct amdgpu_device *adev = ring->adev;
4341 
4342 	/* XXX check if swapping is necessary on BE */
4343 	if (ring->use_doorbell) {
4344 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4345 		WDOORBELL64(ring->doorbell_index, ring->wptr);
4346 	} else {
4347 		BUG(); /* only DOORBELL method supported on gfx10 now */
4348 	}
4349 }
4350 
4351 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4352 {
4353 	struct amdgpu_device *adev = ring->adev;
4354 	u32 ref_and_mask, reg_mem_engine;
4355 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4356 
4357 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4358 		switch (ring->me) {
4359 		case 1:
4360 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4361 			break;
4362 		case 2:
4363 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4364 			break;
4365 		default:
4366 			return;
4367 		}
4368 		reg_mem_engine = 0;
4369 	} else {
4370 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4371 		reg_mem_engine = 1; /* pfp */
4372 	}
4373 
4374 	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4375 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4376 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4377 			       ref_and_mask, ref_and_mask, 0x20);
4378 }
4379 
4380 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4381 				       struct amdgpu_job *job,
4382 				       struct amdgpu_ib *ib,
4383 				       uint32_t flags)
4384 {
4385 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4386 	u32 header, control = 0;
4387 
4388 	if (ib->flags & AMDGPU_IB_FLAG_CE)
4389 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
4390 	else
4391 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4392 
4393 	control |= ib->length_dw | (vmid << 24);
4394 
4395 	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4396 		control |= INDIRECT_BUFFER_PRE_ENB(1);
4397 
4398 		if (flags & AMDGPU_IB_PREEMPTED)
4399 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
4400 
4401 		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
4402 			gfx_v10_0_ring_emit_de_meta(ring,
4403 				    flags & AMDGPU_IB_PREEMPTED ? true : false);
4404 	}
4405 
4406 	amdgpu_ring_write(ring, header);
4407 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4408 	amdgpu_ring_write(ring,
4409 #ifdef __BIG_ENDIAN
4410 		(2 << 0) |
4411 #endif
4412 		lower_32_bits(ib->gpu_addr));
4413 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4414 	amdgpu_ring_write(ring, control);
4415 }
4416 
4417 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4418 					   struct amdgpu_job *job,
4419 					   struct amdgpu_ib *ib,
4420 					   uint32_t flags)
4421 {
4422 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4423 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4424 
4425 	/* Currently, there is a high possibility to get wave ID mismatch
4426 	 * between ME and GDS, leading to a hw deadlock, because ME generates
4427 	 * different wave IDs than the GDS expects. This situation happens
4428 	 * randomly when at least 5 compute pipes use GDS ordered append.
4429 	 * The wave IDs generated by ME are also wrong after suspend/resume.
4430 	 * Those are probably bugs somewhere else in the kernel driver.
4431 	 *
4432 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4433 	 * GDS to 0 for this ring (me/pipe).
4434 	 */
4435 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4436 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4437 		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4438 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4439 	}
4440 
4441 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4442 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4443 	amdgpu_ring_write(ring,
4444 #ifdef __BIG_ENDIAN
4445 				(2 << 0) |
4446 #endif
4447 				lower_32_bits(ib->gpu_addr));
4448 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4449 	amdgpu_ring_write(ring, control);
4450 }
4451 
4452 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4453 				     u64 seq, unsigned flags)
4454 {
4455 	struct amdgpu_device *adev = ring->adev;
4456 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4457 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4458 
4459 	/* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
4460 	if (adev->pdev->device == 0x50)
4461 		int_sel = false;
4462 
4463 	/* RELEASE_MEM - flush caches, send int */
4464 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4465 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4466 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
4467 				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
4468 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
4469 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4470 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4471 				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4472 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4473 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4474 
4475 	/*
4476 	 * the address should be Qword aligned if 64bit write, Dword
4477 	 * aligned if only send 32bit data low (discard data high)
4478 	 */
4479 	if (write64bit)
4480 		BUG_ON(addr & 0x7);
4481 	else
4482 		BUG_ON(addr & 0x3);
4483 	amdgpu_ring_write(ring, lower_32_bits(addr));
4484 	amdgpu_ring_write(ring, upper_32_bits(addr));
4485 	amdgpu_ring_write(ring, lower_32_bits(seq));
4486 	amdgpu_ring_write(ring, upper_32_bits(seq));
4487 	amdgpu_ring_write(ring, 0);
4488 }
4489 
4490 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4491 {
4492 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4493 	uint32_t seq = ring->fence_drv.sync_seq;
4494 	uint64_t addr = ring->fence_drv.gpu_addr;
4495 
4496 	gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4497 			       upper_32_bits(addr), seq, 0xffffffff, 4);
4498 }
4499 
4500 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4501 					 unsigned vmid, uint64_t pd_addr)
4502 {
4503 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4504 
4505 	/* compute doesn't have PFP */
4506 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4507 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
4508 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4509 		amdgpu_ring_write(ring, 0x0);
4510 	}
4511 }
4512 
4513 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4514 					  u64 seq, unsigned int flags)
4515 {
4516 	struct amdgpu_device *adev = ring->adev;
4517 
4518 	/* we only allocate 32bit for each seq wb address */
4519 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4520 
4521 	/* write fence seq to the "addr" */
4522 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4523 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4524 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4525 	amdgpu_ring_write(ring, lower_32_bits(addr));
4526 	amdgpu_ring_write(ring, upper_32_bits(addr));
4527 	amdgpu_ring_write(ring, lower_32_bits(seq));
4528 
4529 	if (flags & AMDGPU_FENCE_FLAG_INT) {
4530 		/* set register to trigger INT */
4531 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4532 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4533 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4534 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4535 		amdgpu_ring_write(ring, 0);
4536 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4537 	}
4538 }
4539 
4540 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
4541 {
4542 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4543 	amdgpu_ring_write(ring, 0);
4544 }
4545 
4546 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4547 {
4548 	uint32_t dw2 = 0;
4549 
4550 	if (amdgpu_mcbp)
4551 		gfx_v10_0_ring_emit_ce_meta(ring,
4552 				    flags & AMDGPU_IB_PREEMPTED ? true : false);
4553 
4554 	gfx_v10_0_ring_emit_tmz(ring, true);
4555 
4556 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4557 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4558 		/* set load_global_config & load_global_uconfig */
4559 		dw2 |= 0x8001;
4560 		/* set load_cs_sh_regs */
4561 		dw2 |= 0x01000000;
4562 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
4563 		dw2 |= 0x10002;
4564 
4565 		/* set load_ce_ram if preamble presented */
4566 		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4567 			dw2 |= 0x10000000;
4568 	} else {
4569 		/* still load_ce_ram if this is the first time preamble presented
4570 		 * although there is no context switch happens.
4571 		 */
4572 		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4573 			dw2 |= 0x10000000;
4574 	}
4575 
4576 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4577 	amdgpu_ring_write(ring, dw2);
4578 	amdgpu_ring_write(ring, 0);
4579 }
4580 
4581 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4582 {
4583 	unsigned ret;
4584 
4585 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4586 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4587 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4588 	amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4589 	ret = ring->wptr & ring->buf_mask;
4590 	amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4591 
4592 	return ret;
4593 }
4594 
4595 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4596 {
4597 	unsigned cur;
4598 	BUG_ON(offset > ring->buf_mask);
4599 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
4600 
4601 	cur = (ring->wptr - 1) & ring->buf_mask;
4602 	if (likely(cur > offset))
4603 		ring->ring[offset] = cur - offset;
4604 	else
4605 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
4606 }
4607 
4608 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
4609 {
4610 	int i, r = 0;
4611 	struct amdgpu_device *adev = ring->adev;
4612 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4613 	struct amdgpu_ring *kiq_ring = &kiq->ring;
4614 
4615 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4616 		return -EINVAL;
4617 
4618 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
4619 		return -ENOMEM;
4620 
4621 	/* assert preemption condition */
4622 	amdgpu_ring_set_preempt_cond_exec(ring, false);
4623 
4624 	/* assert IB preemption, emit the trailing fence */
4625 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4626 				   ring->trail_fence_gpu_addr,
4627 				   ++ring->trail_seq);
4628 	amdgpu_ring_commit(kiq_ring);
4629 
4630 	/* poll the trailing fence */
4631 	for (i = 0; i < adev->usec_timeout; i++) {
4632 		if (ring->trail_seq ==
4633 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4634 			break;
4635 		udelay(1);
4636 	}
4637 
4638 	if (i >= adev->usec_timeout) {
4639 		r = -EINVAL;
4640 		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4641 	}
4642 
4643 	/* deassert preemption condition */
4644 	amdgpu_ring_set_preempt_cond_exec(ring, true);
4645 	return r;
4646 }
4647 
4648 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
4649 {
4650 	struct amdgpu_device *adev = ring->adev;
4651 	struct v10_ce_ib_state ce_payload = {0};
4652 	uint64_t csa_addr;
4653 	int cnt;
4654 
4655 	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4656 	csa_addr = amdgpu_csa_vaddr(ring->adev);
4657 
4658 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4659 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4660 				 WRITE_DATA_DST_SEL(8) |
4661 				 WR_CONFIRM) |
4662 				 WRITE_DATA_CACHE_POLICY(0));
4663 	amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4664 			      offsetof(struct v10_gfx_meta_data, ce_payload)));
4665 	amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4666 			      offsetof(struct v10_gfx_meta_data, ce_payload)));
4667 
4668 	if (resume)
4669 		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4670 					   offsetof(struct v10_gfx_meta_data,
4671 						    ce_payload),
4672 					   sizeof(ce_payload) >> 2);
4673 	else
4674 		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
4675 					   sizeof(ce_payload) >> 2);
4676 }
4677 
4678 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
4679 {
4680 	struct amdgpu_device *adev = ring->adev;
4681 	struct v10_de_ib_state de_payload = {0};
4682 	uint64_t csa_addr, gds_addr;
4683 	int cnt;
4684 
4685 	csa_addr = amdgpu_csa_vaddr(ring->adev);
4686 	gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
4687 			 PAGE_SIZE);
4688 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4689 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4690 
4691 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4692 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4693 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4694 				 WRITE_DATA_DST_SEL(8) |
4695 				 WR_CONFIRM) |
4696 				 WRITE_DATA_CACHE_POLICY(0));
4697 	amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4698 			      offsetof(struct v10_gfx_meta_data, de_payload)));
4699 	amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4700 			      offsetof(struct v10_gfx_meta_data, de_payload)));
4701 
4702 	if (resume)
4703 		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4704 					   offsetof(struct v10_gfx_meta_data,
4705 						    de_payload),
4706 					   sizeof(de_payload) >> 2);
4707 	else
4708 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
4709 					   sizeof(de_payload) >> 2);
4710 }
4711 
4712 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4713 {
4714 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4715 	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4716 }
4717 
4718 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4719 {
4720 	struct amdgpu_device *adev = ring->adev;
4721 
4722 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4723 	amdgpu_ring_write(ring, 0 |	/* src: register*/
4724 				(5 << 8) |	/* dst: memory */
4725 				(1 << 20));	/* write confirm */
4726 	amdgpu_ring_write(ring, reg);
4727 	amdgpu_ring_write(ring, 0);
4728 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4729 				adev->virt.reg_val_offs * 4));
4730 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4731 				adev->virt.reg_val_offs * 4));
4732 }
4733 
4734 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4735 				   uint32_t val)
4736 {
4737 	uint32_t cmd = 0;
4738 
4739 	switch (ring->funcs->type) {
4740 	case AMDGPU_RING_TYPE_GFX:
4741 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4742 		break;
4743 	case AMDGPU_RING_TYPE_KIQ:
4744 		cmd = (1 << 16); /* no inc addr */
4745 		break;
4746 	default:
4747 		cmd = WR_CONFIRM;
4748 		break;
4749 	}
4750 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4751 	amdgpu_ring_write(ring, cmd);
4752 	amdgpu_ring_write(ring, reg);
4753 	amdgpu_ring_write(ring, 0);
4754 	amdgpu_ring_write(ring, val);
4755 }
4756 
4757 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4758 					uint32_t val, uint32_t mask)
4759 {
4760 	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4761 }
4762 
4763 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4764 						   uint32_t reg0, uint32_t reg1,
4765 						   uint32_t ref, uint32_t mask)
4766 {
4767 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4768 	struct amdgpu_device *adev = ring->adev;
4769 	bool fw_version_ok = false;
4770 
4771 	fw_version_ok = adev->gfx.cp_fw_write_wait;
4772 
4773 	if (fw_version_ok)
4774 		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4775 				       ref, mask, 0x20);
4776 	else
4777 		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4778 							   ref, mask);
4779 }
4780 
4781 static void
4782 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4783 				      uint32_t me, uint32_t pipe,
4784 				      enum amdgpu_interrupt_state state)
4785 {
4786 	uint32_t cp_int_cntl, cp_int_cntl_reg;
4787 
4788 	if (!me) {
4789 		switch (pipe) {
4790 		case 0:
4791 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
4792 			break;
4793 		case 1:
4794 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
4795 			break;
4796 		default:
4797 			DRM_DEBUG("invalid pipe %d\n", pipe);
4798 			return;
4799 		}
4800 	} else {
4801 		DRM_DEBUG("invalid me %d\n", me);
4802 		return;
4803 	}
4804 
4805 	switch (state) {
4806 	case AMDGPU_IRQ_STATE_DISABLE:
4807 		cp_int_cntl = RREG32(cp_int_cntl_reg);
4808 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4809 					    TIME_STAMP_INT_ENABLE, 0);
4810 		WREG32(cp_int_cntl_reg, cp_int_cntl);
4811 		break;
4812 	case AMDGPU_IRQ_STATE_ENABLE:
4813 		cp_int_cntl = RREG32(cp_int_cntl_reg);
4814 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4815 					    TIME_STAMP_INT_ENABLE, 1);
4816 		WREG32(cp_int_cntl_reg, cp_int_cntl);
4817 		break;
4818 	default:
4819 		break;
4820 	}
4821 }
4822 
4823 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4824 						     int me, int pipe,
4825 						     enum amdgpu_interrupt_state state)
4826 {
4827 	u32 mec_int_cntl, mec_int_cntl_reg;
4828 
4829 	/*
4830 	 * amdgpu controls only the first MEC. That's why this function only
4831 	 * handles the setting of interrupts for this specific MEC. All other
4832 	 * pipes' interrupts are set by amdkfd.
4833 	 */
4834 
4835 	if (me == 1) {
4836 		switch (pipe) {
4837 		case 0:
4838 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4839 			break;
4840 		case 1:
4841 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4842 			break;
4843 		case 2:
4844 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4845 			break;
4846 		case 3:
4847 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4848 			break;
4849 		default:
4850 			DRM_DEBUG("invalid pipe %d\n", pipe);
4851 			return;
4852 		}
4853 	} else {
4854 		DRM_DEBUG("invalid me %d\n", me);
4855 		return;
4856 	}
4857 
4858 	switch (state) {
4859 	case AMDGPU_IRQ_STATE_DISABLE:
4860 		mec_int_cntl = RREG32(mec_int_cntl_reg);
4861 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4862 					     TIME_STAMP_INT_ENABLE, 0);
4863 		WREG32(mec_int_cntl_reg, mec_int_cntl);
4864 		break;
4865 	case AMDGPU_IRQ_STATE_ENABLE:
4866 		mec_int_cntl = RREG32(mec_int_cntl_reg);
4867 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4868 					     TIME_STAMP_INT_ENABLE, 1);
4869 		WREG32(mec_int_cntl_reg, mec_int_cntl);
4870 		break;
4871 	default:
4872 		break;
4873 	}
4874 }
4875 
4876 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4877 					    struct amdgpu_irq_src *src,
4878 					    unsigned type,
4879 					    enum amdgpu_interrupt_state state)
4880 {
4881 	switch (type) {
4882 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4883 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4884 		break;
4885 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4886 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4887 		break;
4888 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4889 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4890 		break;
4891 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4892 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4893 		break;
4894 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4895 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4896 		break;
4897 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4898 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4899 		break;
4900 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4901 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4902 		break;
4903 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4904 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4905 		break;
4906 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4907 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4908 		break;
4909 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4910 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4911 		break;
4912 	default:
4913 		break;
4914 	}
4915 	return 0;
4916 }
4917 
4918 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
4919 			     struct amdgpu_irq_src *source,
4920 			     struct amdgpu_iv_entry *entry)
4921 {
4922 	int i;
4923 	u8 me_id, pipe_id, queue_id;
4924 	struct amdgpu_ring *ring;
4925 
4926 	DRM_DEBUG("IH: CP EOP\n");
4927 	me_id = (entry->ring_id & 0x0c) >> 2;
4928 	pipe_id = (entry->ring_id & 0x03) >> 0;
4929 	queue_id = (entry->ring_id & 0x70) >> 4;
4930 
4931 	switch (me_id) {
4932 	case 0:
4933 		if (pipe_id == 0)
4934 			amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4935 		else
4936 			amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4937 		break;
4938 	case 1:
4939 	case 2:
4940 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4941 			ring = &adev->gfx.compute_ring[i];
4942 			/* Per-queue interrupt is supported for MEC starting from VI.
4943 			  * The interrupt can only be enabled/disabled per pipe instead of per queue.
4944 			  */
4945 			if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4946 				amdgpu_fence_process(ring);
4947 		}
4948 		break;
4949 	}
4950 	return 0;
4951 }
4952 
4953 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4954 					      struct amdgpu_irq_src *source,
4955 					      unsigned type,
4956 					      enum amdgpu_interrupt_state state)
4957 {
4958 	switch (state) {
4959 	case AMDGPU_IRQ_STATE_DISABLE:
4960 	case AMDGPU_IRQ_STATE_ENABLE:
4961 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4962 			       PRIV_REG_INT_ENABLE,
4963 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4964 		break;
4965 	default:
4966 		break;
4967 	}
4968 
4969 	return 0;
4970 }
4971 
4972 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4973 					       struct amdgpu_irq_src *source,
4974 					       unsigned type,
4975 					       enum amdgpu_interrupt_state state)
4976 {
4977 	switch (state) {
4978 	case AMDGPU_IRQ_STATE_DISABLE:
4979 	case AMDGPU_IRQ_STATE_ENABLE:
4980 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4981 			       PRIV_INSTR_INT_ENABLE,
4982 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4983 	default:
4984 		break;
4985 	}
4986 
4987 	return 0;
4988 }
4989 
4990 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
4991 					struct amdgpu_iv_entry *entry)
4992 {
4993 	u8 me_id, pipe_id, queue_id;
4994 	struct amdgpu_ring *ring;
4995 	int i;
4996 
4997 	me_id = (entry->ring_id & 0x0c) >> 2;
4998 	pipe_id = (entry->ring_id & 0x03) >> 0;
4999 	queue_id = (entry->ring_id & 0x70) >> 4;
5000 
5001 	switch (me_id) {
5002 	case 0:
5003 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5004 			ring = &adev->gfx.gfx_ring[i];
5005 			/* we only enabled 1 gfx queue per pipe for now */
5006 			if (ring->me == me_id && ring->pipe == pipe_id)
5007 				drm_sched_fault(&ring->sched);
5008 		}
5009 		break;
5010 	case 1:
5011 	case 2:
5012 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5013 			ring = &adev->gfx.compute_ring[i];
5014 			if (ring->me == me_id && ring->pipe == pipe_id &&
5015 			    ring->queue == queue_id)
5016 				drm_sched_fault(&ring->sched);
5017 		}
5018 		break;
5019 	default:
5020 		BUG();
5021 	}
5022 }
5023 
5024 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
5025 				  struct amdgpu_irq_src *source,
5026 				  struct amdgpu_iv_entry *entry)
5027 {
5028 	DRM_ERROR("Illegal register access in command stream\n");
5029 	gfx_v10_0_handle_priv_fault(adev, entry);
5030 	return 0;
5031 }
5032 
5033 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
5034 				   struct amdgpu_irq_src *source,
5035 				   struct amdgpu_iv_entry *entry)
5036 {
5037 	DRM_ERROR("Illegal instruction in command stream\n");
5038 	gfx_v10_0_handle_priv_fault(adev, entry);
5039 	return 0;
5040 }
5041 
5042 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5043 					     struct amdgpu_irq_src *src,
5044 					     unsigned int type,
5045 					     enum amdgpu_interrupt_state state)
5046 {
5047 	uint32_t tmp, target;
5048 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5049 
5050 	if (ring->me == 1)
5051 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5052 	else
5053 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
5054 	target += ring->pipe;
5055 
5056 	switch (type) {
5057 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5058 		if (state == AMDGPU_IRQ_STATE_DISABLE) {
5059 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5060 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5061 					    GENERIC2_INT_ENABLE, 0);
5062 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5063 
5064 			tmp = RREG32(target);
5065 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5066 					    GENERIC2_INT_ENABLE, 0);
5067 			WREG32(target, tmp);
5068 		} else {
5069 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5070 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5071 					    GENERIC2_INT_ENABLE, 1);
5072 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5073 
5074 			tmp = RREG32(target);
5075 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5076 					    GENERIC2_INT_ENABLE, 1);
5077 			WREG32(target, tmp);
5078 		}
5079 		break;
5080 	default:
5081 		BUG(); /* kiq only support GENERIC2_INT now */
5082 		break;
5083 	}
5084 	return 0;
5085 }
5086 
5087 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
5088 			     struct amdgpu_irq_src *source,
5089 			     struct amdgpu_iv_entry *entry)
5090 {
5091 	u8 me_id, pipe_id, queue_id;
5092 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5093 
5094 	me_id = (entry->ring_id & 0x0c) >> 2;
5095 	pipe_id = (entry->ring_id & 0x03) >> 0;
5096 	queue_id = (entry->ring_id & 0x70) >> 4;
5097 	DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
5098 		   me_id, pipe_id, queue_id);
5099 
5100 	amdgpu_fence_process(ring);
5101 	return 0;
5102 }
5103 
5104 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
5105 	.name = "gfx_v10_0",
5106 	.early_init = gfx_v10_0_early_init,
5107 	.late_init = gfx_v10_0_late_init,
5108 	.sw_init = gfx_v10_0_sw_init,
5109 	.sw_fini = gfx_v10_0_sw_fini,
5110 	.hw_init = gfx_v10_0_hw_init,
5111 	.hw_fini = gfx_v10_0_hw_fini,
5112 	.suspend = gfx_v10_0_suspend,
5113 	.resume = gfx_v10_0_resume,
5114 	.is_idle = gfx_v10_0_is_idle,
5115 	.wait_for_idle = gfx_v10_0_wait_for_idle,
5116 	.soft_reset = gfx_v10_0_soft_reset,
5117 	.set_clockgating_state = gfx_v10_0_set_clockgating_state,
5118 	.set_powergating_state = gfx_v10_0_set_powergating_state,
5119 	.get_clockgating_state = gfx_v10_0_get_clockgating_state,
5120 };
5121 
5122 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
5123 	.type = AMDGPU_RING_TYPE_GFX,
5124 	.align_mask = 0xff,
5125 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
5126 	.support_64bit_ptrs = true,
5127 	.vmhub = AMDGPU_GFXHUB_0,
5128 	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
5129 	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
5130 	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
5131 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
5132 		5 + /* COND_EXEC */
5133 		7 + /* PIPELINE_SYNC */
5134 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5135 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5136 		2 + /* VM_FLUSH */
5137 		8 + /* FENCE for VM_FLUSH */
5138 		20 + /* GDS switch */
5139 		4 + /* double SWITCH_BUFFER,
5140 		     * the first COND_EXEC jump to the place
5141 		     * just prior to this double SWITCH_BUFFER
5142 		     */
5143 		5 + /* COND_EXEC */
5144 		7 + /* HDP_flush */
5145 		4 + /* VGT_flush */
5146 		14 + /*	CE_META */
5147 		31 + /*	DE_META */
5148 		3 + /* CNTX_CTRL */
5149 		5 + /* HDP_INVL */
5150 		8 + 8 + /* FENCE x2 */
5151 		2, /* SWITCH_BUFFER */
5152 	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
5153 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
5154 	.emit_fence = gfx_v10_0_ring_emit_fence,
5155 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5156 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5157 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5158 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5159 	.test_ring = gfx_v10_0_ring_test_ring,
5160 	.test_ib = gfx_v10_0_ring_test_ib,
5161 	.insert_nop = amdgpu_ring_insert_nop,
5162 	.pad_ib = amdgpu_ring_generic_pad_ib,
5163 	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
5164 	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
5165 	.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
5166 	.patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
5167 	.preempt_ib = gfx_v10_0_ring_preempt_ib,
5168 	.emit_tmz = gfx_v10_0_ring_emit_tmz,
5169 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
5170 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5171 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5172 };
5173 
5174 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
5175 	.type = AMDGPU_RING_TYPE_COMPUTE,
5176 	.align_mask = 0xff,
5177 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
5178 	.support_64bit_ptrs = true,
5179 	.vmhub = AMDGPU_GFXHUB_0,
5180 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
5181 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
5182 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
5183 	.emit_frame_size =
5184 		20 + /* gfx_v10_0_ring_emit_gds_switch */
5185 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
5186 		5 + /* hdp invalidate */
5187 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5188 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5189 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5190 		2 + /* gfx_v10_0_ring_emit_vm_flush */
5191 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
5192 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
5193 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
5194 	.emit_fence = gfx_v10_0_ring_emit_fence,
5195 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5196 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5197 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5198 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5199 	.test_ring = gfx_v10_0_ring_test_ring,
5200 	.test_ib = gfx_v10_0_ring_test_ib,
5201 	.insert_nop = amdgpu_ring_insert_nop,
5202 	.pad_ib = amdgpu_ring_generic_pad_ib,
5203 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
5204 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5205 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5206 };
5207 
5208 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
5209 	.type = AMDGPU_RING_TYPE_KIQ,
5210 	.align_mask = 0xff,
5211 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
5212 	.support_64bit_ptrs = true,
5213 	.vmhub = AMDGPU_GFXHUB_0,
5214 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
5215 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
5216 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
5217 	.emit_frame_size =
5218 		20 + /* gfx_v10_0_ring_emit_gds_switch */
5219 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
5220 		5 + /*hdp invalidate */
5221 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5222 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5223 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5224 		2 + /* gfx_v10_0_ring_emit_vm_flush */
5225 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5226 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
5227 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
5228 	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
5229 	.test_ring = gfx_v10_0_ring_test_ring,
5230 	.test_ib = gfx_v10_0_ring_test_ib,
5231 	.insert_nop = amdgpu_ring_insert_nop,
5232 	.pad_ib = amdgpu_ring_generic_pad_ib,
5233 	.emit_rreg = gfx_v10_0_ring_emit_rreg,
5234 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
5235 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5236 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5237 };
5238 
5239 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
5240 {
5241 	int i;
5242 
5243 	adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
5244 
5245 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5246 		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
5247 
5248 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
5249 		adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
5250 }
5251 
5252 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
5253 	.set = gfx_v10_0_set_eop_interrupt_state,
5254 	.process = gfx_v10_0_eop_irq,
5255 };
5256 
5257 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
5258 	.set = gfx_v10_0_set_priv_reg_fault_state,
5259 	.process = gfx_v10_0_priv_reg_irq,
5260 };
5261 
5262 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
5263 	.set = gfx_v10_0_set_priv_inst_fault_state,
5264 	.process = gfx_v10_0_priv_inst_irq,
5265 };
5266 
5267 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
5268 	.set = gfx_v10_0_kiq_set_interrupt_state,
5269 	.process = gfx_v10_0_kiq_irq,
5270 };
5271 
5272 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
5273 {
5274 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5275 	adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
5276 
5277 	adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
5278 	adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
5279 
5280 	adev->gfx.priv_reg_irq.num_types = 1;
5281 	adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
5282 
5283 	adev->gfx.priv_inst_irq.num_types = 1;
5284 	adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
5285 }
5286 
5287 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
5288 {
5289 	switch (adev->asic_type) {
5290 	case CHIP_NAVI10:
5291 	case CHIP_NAVI14:
5292 	case CHIP_NAVI12:
5293 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
5294 		break;
5295 	default:
5296 		break;
5297 	}
5298 }
5299 
5300 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
5301 {
5302 	unsigned total_cu = adev->gfx.config.max_cu_per_sh *
5303 			    adev->gfx.config.max_sh_per_se *
5304 			    adev->gfx.config.max_shader_engines;
5305 
5306 	adev->gds.gds_size = 0x10000;
5307 	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
5308 	adev->gds.gws_size = 64;
5309 	adev->gds.oa_size = 16;
5310 }
5311 
5312 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5313 							  u32 bitmap)
5314 {
5315 	u32 data;
5316 
5317 	if (!bitmap)
5318 		return;
5319 
5320 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5321 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5322 
5323 	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
5324 }
5325 
5326 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5327 {
5328 	u32 data, wgp_bitmask;
5329 	data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
5330 	data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
5331 
5332 	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5333 	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5334 
5335 	wgp_bitmask =
5336 		amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5337 
5338 	return (~data) & wgp_bitmask;
5339 }
5340 
5341 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5342 {
5343 	u32 wgp_idx, wgp_active_bitmap;
5344 	u32 cu_bitmap_per_wgp, cu_active_bitmap;
5345 
5346 	wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5347 	cu_active_bitmap = 0;
5348 
5349 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5350 		/* if there is one WGP enabled, it means 2 CUs will be enabled */
5351 		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5352 		if (wgp_active_bitmap & (1 << wgp_idx))
5353 			cu_active_bitmap |= cu_bitmap_per_wgp;
5354 	}
5355 
5356 	return cu_active_bitmap;
5357 }
5358 
5359 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
5360 				 struct amdgpu_cu_info *cu_info)
5361 {
5362 	int i, j, k, counter, active_cu_number = 0;
5363 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5364 	unsigned disable_masks[4 * 2];
5365 
5366 	if (!adev || !cu_info)
5367 		return -EINVAL;
5368 
5369 	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5370 
5371 	mutex_lock(&adev->grbm_idx_mutex);
5372 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5373 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5374 			mask = 1;
5375 			ao_bitmap = 0;
5376 			counter = 0;
5377 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5378 			if (i < 4 && j < 2)
5379 				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
5380 					adev, disable_masks[i * 2 + j]);
5381 			bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
5382 			cu_info->bitmap[i][j] = bitmap;
5383 
5384 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5385 				if (bitmap & mask) {
5386 					if (counter < adev->gfx.config.max_cu_per_sh)
5387 						ao_bitmap |= mask;
5388 					counter++;
5389 				}
5390 				mask <<= 1;
5391 			}
5392 			active_cu_number += counter;
5393 			if (i < 2 && j < 2)
5394 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5395 			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5396 		}
5397 	}
5398 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5399 	mutex_unlock(&adev->grbm_idx_mutex);
5400 
5401 	cu_info->number = active_cu_number;
5402 	cu_info->ao_cu_mask = ao_cu_mask;
5403 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5404 
5405 	return 0;
5406 }
5407 
5408 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
5409 {
5410 	.type = AMD_IP_BLOCK_TYPE_GFX,
5411 	.major = 10,
5412 	.minor = 0,
5413 	.rev = 0,
5414 	.funcs = &gfx_v10_0_ip_funcs,
5415 };
5416