1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_smu.h"
33 #include "nv.h"
34 #include "nvd.h"
35 
36 #include "gc/gc_10_1_0_offset.h"
37 #include "gc/gc_10_1_0_sh_mask.h"
38 #include "navi10_enum.h"
39 #include "hdp/hdp_5_0_0_offset.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41 
42 #include "soc15.h"
43 #include "soc15_common.h"
44 #include "clearstate_gfx10.h"
45 #include "v10_structs.h"
46 #include "gfx_v10_0.h"
47 #include "nbio_v2_3.h"
48 
49 /**
50  * Navi10 has two graphic rings to share each graphic pipe.
51  * 1. Primary ring
52  * 2. Async ring
53  *
54  * In bring-up phase, it just used primary ring so set gfx ring number as 1 at
55  * first.
56  */
57 #define GFX10_NUM_GFX_RINGS	2
58 #define GFX10_MEC_HPD_SIZE	2048
59 
60 #define F32_CE_PROGRAM_RAM_SIZE		65536
61 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
62 
63 #define mmCGTT_GS_NGG_CLK_CTRL	0x5087
64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
65 
66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
68 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
72 
73 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
74 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
75 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
76 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
77 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
78 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
79 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
80 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
81 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
82 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
83 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
84 
85 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
86 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
87 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
88 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
89 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
90 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
91 
92 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
93 {
94 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
95 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
96 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
97 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
98 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
99 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070104),
127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
134 };
135 
136 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
137 {
138 	/* Pending on emulation bring up */
139 };
140 
141 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
142 {
143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070105),
175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
181 };
182 
183 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
184 {
185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
225 };
226 
227 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
228 {
229 	/* Pending on emulation bring up */
230 };
231 
232 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
233 {
234 	/* Pending on emulation bring up */
235 };
236 
237 #define DEFAULT_SH_MEM_CONFIG \
238 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
239 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
240 	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
241 	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
242 
243 
244 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
245 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
246 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
247 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
248 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
249                                  struct amdgpu_cu_info *cu_info);
250 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
251 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
252 				   u32 sh_num, u32 instance);
253 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
254 
255 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
256 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
257 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
258 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
259 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
260 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
261 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
262 
263 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
264 {
265 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
266 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
267 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
268 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
269 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
270 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
271 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
272 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
273 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
274 }
275 
276 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
277 				 struct amdgpu_ring *ring)
278 {
279 	struct amdgpu_device *adev = kiq_ring->adev;
280 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
281 	uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
282 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
283 
284 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
285 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
286 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
287 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
288 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
289 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
290 			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
291 			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
292 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
293 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
294 			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
295 			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
296 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
297 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
298 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
299 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
300 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
301 }
302 
303 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
304 				   struct amdgpu_ring *ring,
305 				   enum amdgpu_unmap_queues_action action,
306 				   u64 gpu_addr, u64 seq)
307 {
308 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
309 
310 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
311 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
312 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
313 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
314 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
315 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
316 	amdgpu_ring_write(kiq_ring,
317 		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
318 
319 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
320 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
321 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
322 		amdgpu_ring_write(kiq_ring, seq);
323 	} else {
324 		amdgpu_ring_write(kiq_ring, 0);
325 		amdgpu_ring_write(kiq_ring, 0);
326 		amdgpu_ring_write(kiq_ring, 0);
327 	}
328 }
329 
330 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
331 				   struct amdgpu_ring *ring,
332 				   u64 addr,
333 				   u64 seq)
334 {
335 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
336 
337 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
338 	amdgpu_ring_write(kiq_ring,
339 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
340 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
341 			  PACKET3_QUERY_STATUS_COMMAND(2));
342 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
343 			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
344 			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
345 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
346 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
347 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
348 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
349 }
350 
351 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
352 	.kiq_set_resources = gfx10_kiq_set_resources,
353 	.kiq_map_queues = gfx10_kiq_map_queues,
354 	.kiq_unmap_queues = gfx10_kiq_unmap_queues,
355 	.kiq_query_status = gfx10_kiq_query_status,
356 	.set_resources_size = 8,
357 	.map_queues_size = 7,
358 	.unmap_queues_size = 6,
359 	.query_status_size = 7,
360 };
361 
362 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
363 {
364 	adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
365 }
366 
367 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
368 {
369 	switch (adev->asic_type) {
370 	case CHIP_NAVI10:
371 		soc15_program_register_sequence(adev,
372 						golden_settings_gc_10_1,
373 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
374 		soc15_program_register_sequence(adev,
375 						golden_settings_gc_10_0_nv10,
376 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
377 		break;
378 	case CHIP_NAVI14:
379 		soc15_program_register_sequence(adev,
380 						golden_settings_gc_10_1_1,
381 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
382 		soc15_program_register_sequence(adev,
383 						golden_settings_gc_10_1_nv14,
384 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
385 		break;
386 	case CHIP_NAVI12:
387 		soc15_program_register_sequence(adev,
388 						golden_settings_gc_10_1_2,
389 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
390 		soc15_program_register_sequence(adev,
391 						golden_settings_gc_10_1_2_nv12,
392 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
393 		break;
394 	default:
395 		break;
396 	}
397 }
398 
399 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
400 {
401 	adev->gfx.scratch.num_reg = 8;
402 	adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
403 	adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
404 }
405 
406 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
407 				       bool wc, uint32_t reg, uint32_t val)
408 {
409 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
410 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
411 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
412 	amdgpu_ring_write(ring, reg);
413 	amdgpu_ring_write(ring, 0);
414 	amdgpu_ring_write(ring, val);
415 }
416 
417 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
418 				  int mem_space, int opt, uint32_t addr0,
419 				  uint32_t addr1, uint32_t ref, uint32_t mask,
420 				  uint32_t inv)
421 {
422 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
423 	amdgpu_ring_write(ring,
424 			  /* memory (1) or register (0) */
425 			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
426 			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
427 			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
428 			   WAIT_REG_MEM_ENGINE(eng_sel)));
429 
430 	if (mem_space)
431 		BUG_ON(addr0 & 0x3); /* Dword align */
432 	amdgpu_ring_write(ring, addr0);
433 	amdgpu_ring_write(ring, addr1);
434 	amdgpu_ring_write(ring, ref);
435 	amdgpu_ring_write(ring, mask);
436 	amdgpu_ring_write(ring, inv); /* poll interval */
437 }
438 
439 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
440 {
441 	struct amdgpu_device *adev = ring->adev;
442 	uint32_t scratch;
443 	uint32_t tmp = 0;
444 	unsigned i;
445 	int r;
446 
447 	r = amdgpu_gfx_scratch_get(adev, &scratch);
448 	if (r) {
449 		DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
450 		return r;
451 	}
452 
453 	WREG32(scratch, 0xCAFEDEAD);
454 
455 	r = amdgpu_ring_alloc(ring, 3);
456 	if (r) {
457 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
458 			  ring->idx, r);
459 		amdgpu_gfx_scratch_free(adev, scratch);
460 		return r;
461 	}
462 
463 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
464 	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
465 	amdgpu_ring_write(ring, 0xDEADBEEF);
466 	amdgpu_ring_commit(ring);
467 
468 	for (i = 0; i < adev->usec_timeout; i++) {
469 		tmp = RREG32(scratch);
470 		if (tmp == 0xDEADBEEF)
471 			break;
472 		if (amdgpu_emu_mode == 1)
473 			msleep(1);
474 		else
475 			udelay(1);
476 	}
477 	if (i < adev->usec_timeout) {
478 		if (amdgpu_emu_mode == 1)
479 			DRM_INFO("ring test on %d succeeded in %d msecs\n",
480 				 ring->idx, i);
481 		else
482 			DRM_INFO("ring test on %d succeeded in %d usecs\n",
483 				 ring->idx, i);
484 	} else {
485 		DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
486 			  ring->idx, scratch, tmp);
487 		r = -EINVAL;
488 	}
489 	amdgpu_gfx_scratch_free(adev, scratch);
490 
491 	return r;
492 }
493 
494 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
495 {
496 	struct amdgpu_device *adev = ring->adev;
497 	struct amdgpu_ib ib;
498 	struct dma_fence *f = NULL;
499 	uint32_t scratch;
500 	uint32_t tmp = 0;
501 	long r;
502 
503 	r = amdgpu_gfx_scratch_get(adev, &scratch);
504 	if (r) {
505 		DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
506 		return r;
507 	}
508 
509 	WREG32(scratch, 0xCAFEDEAD);
510 
511 	memset(&ib, 0, sizeof(ib));
512 	r = amdgpu_ib_get(adev, NULL, 256, &ib);
513 	if (r) {
514 		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
515 		goto err1;
516 	}
517 
518 	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
519 	ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
520 	ib.ptr[2] = 0xDEADBEEF;
521 	ib.length_dw = 3;
522 
523 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
524 	if (r)
525 		goto err2;
526 
527 	r = dma_fence_wait_timeout(f, false, timeout);
528 	if (r == 0) {
529 		DRM_ERROR("amdgpu: IB test timed out.\n");
530 		r = -ETIMEDOUT;
531 		goto err2;
532 	} else if (r < 0) {
533 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
534 		goto err2;
535 	}
536 
537 	tmp = RREG32(scratch);
538 	if (tmp == 0xDEADBEEF) {
539 		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
540 		r = 0;
541 	} else {
542 		DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
543 			  scratch, tmp);
544 		r = -EINVAL;
545 	}
546 err2:
547 	amdgpu_ib_free(adev, &ib, NULL);
548 	dma_fence_put(f);
549 err1:
550 	amdgpu_gfx_scratch_free(adev, scratch);
551 
552 	return r;
553 }
554 
555 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
556 {
557 	release_firmware(adev->gfx.pfp_fw);
558 	adev->gfx.pfp_fw = NULL;
559 	release_firmware(adev->gfx.me_fw);
560 	adev->gfx.me_fw = NULL;
561 	release_firmware(adev->gfx.ce_fw);
562 	adev->gfx.ce_fw = NULL;
563 	release_firmware(adev->gfx.rlc_fw);
564 	adev->gfx.rlc_fw = NULL;
565 	release_firmware(adev->gfx.mec_fw);
566 	adev->gfx.mec_fw = NULL;
567 	release_firmware(adev->gfx.mec2_fw);
568 	adev->gfx.mec2_fw = NULL;
569 
570 	kfree(adev->gfx.rlc.register_list_format);
571 }
572 
573 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
574 {
575 	adev->gfx.cp_fw_write_wait = false;
576 
577 	switch (adev->asic_type) {
578 	case CHIP_NAVI10:
579 	case CHIP_NAVI12:
580 	case CHIP_NAVI14:
581 		if ((adev->gfx.me_fw_version >= 0x00000046) &&
582 		    (adev->gfx.me_feature_version >= 27) &&
583 		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
584 		    (adev->gfx.pfp_feature_version >= 27) &&
585 		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
586 		    (adev->gfx.mec_feature_version >= 27))
587 			adev->gfx.cp_fw_write_wait = true;
588 		break;
589 	default:
590 		break;
591 	}
592 
593 	if (adev->gfx.cp_fw_write_wait == false)
594 		DRM_WARN_ONCE("Warning: check cp_fw_version and update it to realize \
595 			      GRBM requires 1-cycle delay in cp firmware\n");
596 }
597 
598 
599 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
600 {
601 	const struct rlc_firmware_header_v2_1 *rlc_hdr;
602 
603 	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
604 	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
605 	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
606 	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
607 	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
608 	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
609 	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
610 	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
611 	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
612 	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
613 	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
614 	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
615 	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
616 	adev->gfx.rlc.reg_list_format_direct_reg_list_length =
617 			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
618 }
619 
620 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
621 {
622 	switch (adev->asic_type) {
623 	case CHIP_NAVI10:
624 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
625 		break;
626 	default:
627 		break;
628 	}
629 }
630 
631 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
632 {
633 	const char *chip_name;
634 	char fw_name[40];
635 	char wks[10];
636 	int err;
637 	struct amdgpu_firmware_info *info = NULL;
638 	const struct common_firmware_header *header = NULL;
639 	const struct gfx_firmware_header_v1_0 *cp_hdr;
640 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
641 	unsigned int *tmp = NULL;
642 	unsigned int i = 0;
643 	uint16_t version_major;
644 	uint16_t version_minor;
645 
646 	DRM_DEBUG("\n");
647 
648 	memset(wks, 0, sizeof(wks));
649 	switch (adev->asic_type) {
650 	case CHIP_NAVI10:
651 		chip_name = "navi10";
652 		break;
653 	case CHIP_NAVI14:
654 		chip_name = "navi14";
655 		if (!(adev->pdev->device == 0x7340 &&
656 		      adev->pdev->revision != 0x00))
657 			snprintf(wks, sizeof(wks), "_wks");
658 		break;
659 	case CHIP_NAVI12:
660 		chip_name = "navi12";
661 		break;
662 	default:
663 		BUG();
664 	}
665 
666 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
667 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
668 	if (err)
669 		goto out;
670 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
671 	if (err)
672 		goto out;
673 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
674 	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
675 	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
676 
677 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
678 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
679 	if (err)
680 		goto out;
681 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
682 	if (err)
683 		goto out;
684 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
685 	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
686 	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
687 
688 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
689 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
690 	if (err)
691 		goto out;
692 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
693 	if (err)
694 		goto out;
695 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
696 	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
697 	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
698 
699 	if (!amdgpu_sriov_vf(adev)) {
700 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
701 		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
702 		if (err)
703 			goto out;
704 		err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
705 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
706 		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
707 		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
708 		if (version_major == 2 && version_minor == 1)
709 			adev->gfx.rlc.is_rlc_v2_1 = true;
710 
711 		adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
712 		adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
713 		adev->gfx.rlc.save_and_restore_offset =
714 			le32_to_cpu(rlc_hdr->save_and_restore_offset);
715 		adev->gfx.rlc.clear_state_descriptor_offset =
716 			le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
717 		adev->gfx.rlc.avail_scratch_ram_locations =
718 			le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
719 		adev->gfx.rlc.reg_restore_list_size =
720 			le32_to_cpu(rlc_hdr->reg_restore_list_size);
721 		adev->gfx.rlc.reg_list_format_start =
722 			le32_to_cpu(rlc_hdr->reg_list_format_start);
723 		adev->gfx.rlc.reg_list_format_separate_start =
724 			le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
725 		adev->gfx.rlc.starting_offsets_start =
726 			le32_to_cpu(rlc_hdr->starting_offsets_start);
727 		adev->gfx.rlc.reg_list_format_size_bytes =
728 			le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
729 		adev->gfx.rlc.reg_list_size_bytes =
730 			le32_to_cpu(rlc_hdr->reg_list_size_bytes);
731 		adev->gfx.rlc.register_list_format =
732 			kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
733 					adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
734 		if (!adev->gfx.rlc.register_list_format) {
735 			err = -ENOMEM;
736 			goto out;
737 		}
738 
739 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
740 							   le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
741 		for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
742 			adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
743 
744 		adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
745 
746 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
747 							   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
748 		for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
749 			adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
750 
751 		if (adev->gfx.rlc.is_rlc_v2_1)
752 			gfx_v10_0_init_rlc_ext_microcode(adev);
753 	}
754 
755 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
756 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
757 	if (err)
758 		goto out;
759 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
760 	if (err)
761 		goto out;
762 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
763 	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
764 	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
765 
766 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
767 	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
768 	if (!err) {
769 		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
770 		if (err)
771 			goto out;
772 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
773 		adev->gfx.mec2_fw->data;
774 		adev->gfx.mec2_fw_version =
775 		le32_to_cpu(cp_hdr->header.ucode_version);
776 		adev->gfx.mec2_feature_version =
777 		le32_to_cpu(cp_hdr->ucode_feature_version);
778 	} else {
779 		err = 0;
780 		adev->gfx.mec2_fw = NULL;
781 	}
782 
783 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
784 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
785 		info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
786 		info->fw = adev->gfx.pfp_fw;
787 		header = (const struct common_firmware_header *)info->fw->data;
788 		adev->firmware.fw_size +=
789 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
790 
791 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
792 		info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
793 		info->fw = adev->gfx.me_fw;
794 		header = (const struct common_firmware_header *)info->fw->data;
795 		adev->firmware.fw_size +=
796 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
797 
798 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
799 		info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
800 		info->fw = adev->gfx.ce_fw;
801 		header = (const struct common_firmware_header *)info->fw->data;
802 		adev->firmware.fw_size +=
803 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
804 
805 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
806 		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
807 		info->fw = adev->gfx.rlc_fw;
808 		header = (const struct common_firmware_header *)info->fw->data;
809 		adev->firmware.fw_size +=
810 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
811 
812 		if (adev->gfx.rlc.is_rlc_v2_1 &&
813 		    adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
814 		    adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
815 		    adev->gfx.rlc.save_restore_list_srm_size_bytes) {
816 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
817 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
818 			info->fw = adev->gfx.rlc_fw;
819 			adev->firmware.fw_size +=
820 				ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
821 
822 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
823 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
824 			info->fw = adev->gfx.rlc_fw;
825 			adev->firmware.fw_size +=
826 				ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
827 
828 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
829 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
830 			info->fw = adev->gfx.rlc_fw;
831 			adev->firmware.fw_size +=
832 				ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
833 		}
834 
835 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
836 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
837 		info->fw = adev->gfx.mec_fw;
838 		header = (const struct common_firmware_header *)info->fw->data;
839 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
840 		adev->firmware.fw_size +=
841 			ALIGN(le32_to_cpu(header->ucode_size_bytes) -
842 			      le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
843 
844 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
845 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
846 		info->fw = adev->gfx.mec_fw;
847 		adev->firmware.fw_size +=
848 			ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
849 
850 		if (adev->gfx.mec2_fw) {
851 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
852 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
853 			info->fw = adev->gfx.mec2_fw;
854 			header = (const struct common_firmware_header *)info->fw->data;
855 			cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
856 			adev->firmware.fw_size +=
857 				ALIGN(le32_to_cpu(header->ucode_size_bytes) -
858 				      le32_to_cpu(cp_hdr->jt_size) * 4,
859 				      PAGE_SIZE);
860 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
861 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
862 			info->fw = adev->gfx.mec2_fw;
863 			adev->firmware.fw_size +=
864 				ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
865 				      PAGE_SIZE);
866 		}
867 	}
868 
869 	gfx_v10_0_check_fw_write_wait(adev);
870 out:
871 	if (err) {
872 		dev_err(adev->dev,
873 			"gfx10: Failed to load firmware \"%s\"\n",
874 			fw_name);
875 		release_firmware(adev->gfx.pfp_fw);
876 		adev->gfx.pfp_fw = NULL;
877 		release_firmware(adev->gfx.me_fw);
878 		adev->gfx.me_fw = NULL;
879 		release_firmware(adev->gfx.ce_fw);
880 		adev->gfx.ce_fw = NULL;
881 		release_firmware(adev->gfx.rlc_fw);
882 		adev->gfx.rlc_fw = NULL;
883 		release_firmware(adev->gfx.mec_fw);
884 		adev->gfx.mec_fw = NULL;
885 		release_firmware(adev->gfx.mec2_fw);
886 		adev->gfx.mec2_fw = NULL;
887 	}
888 
889 	gfx_v10_0_check_gfxoff_flag(adev);
890 
891 	return err;
892 }
893 
894 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
895 {
896 	u32 count = 0;
897 	const struct cs_section_def *sect = NULL;
898 	const struct cs_extent_def *ext = NULL;
899 
900 	/* begin clear state */
901 	count += 2;
902 	/* context control state */
903 	count += 3;
904 
905 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
906 		for (ext = sect->section; ext->extent != NULL; ++ext) {
907 			if (sect->id == SECT_CONTEXT)
908 				count += 2 + ext->reg_count;
909 			else
910 				return 0;
911 		}
912 	}
913 
914 	/* set PA_SC_TILE_STEERING_OVERRIDE */
915 	count += 3;
916 	/* end clear state */
917 	count += 2;
918 	/* clear state */
919 	count += 2;
920 
921 	return count;
922 }
923 
924 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
925 				    volatile u32 *buffer)
926 {
927 	u32 count = 0, i;
928 	const struct cs_section_def *sect = NULL;
929 	const struct cs_extent_def *ext = NULL;
930 	int ctx_reg_offset;
931 
932 	if (adev->gfx.rlc.cs_data == NULL)
933 		return;
934 	if (buffer == NULL)
935 		return;
936 
937 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
938 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
939 
940 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
941 	buffer[count++] = cpu_to_le32(0x80000000);
942 	buffer[count++] = cpu_to_le32(0x80000000);
943 
944 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
945 		for (ext = sect->section; ext->extent != NULL; ++ext) {
946 			if (sect->id == SECT_CONTEXT) {
947 				buffer[count++] =
948 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
949 				buffer[count++] = cpu_to_le32(ext->reg_index -
950 						PACKET3_SET_CONTEXT_REG_START);
951 				for (i = 0; i < ext->reg_count; i++)
952 					buffer[count++] = cpu_to_le32(ext->extent[i]);
953 			} else {
954 				return;
955 			}
956 		}
957 	}
958 
959 	ctx_reg_offset =
960 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
961 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
962 	buffer[count++] = cpu_to_le32(ctx_reg_offset);
963 	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
964 
965 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
966 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
967 
968 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
969 	buffer[count++] = cpu_to_le32(0);
970 }
971 
972 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
973 {
974 	/* clear state block */
975 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
976 			&adev->gfx.rlc.clear_state_gpu_addr,
977 			(void **)&adev->gfx.rlc.cs_ptr);
978 
979 	/* jump table block */
980 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
981 			&adev->gfx.rlc.cp_table_gpu_addr,
982 			(void **)&adev->gfx.rlc.cp_table_ptr);
983 }
984 
985 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
986 {
987 	const struct cs_section_def *cs_data;
988 	int r;
989 
990 	adev->gfx.rlc.cs_data = gfx10_cs_data;
991 
992 	cs_data = adev->gfx.rlc.cs_data;
993 
994 	if (cs_data) {
995 		/* init clear state block */
996 		r = amdgpu_gfx_rlc_init_csb(adev);
997 		if (r)
998 			return r;
999 	}
1000 
1001 	return 0;
1002 }
1003 
1004 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
1005 {
1006 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1007 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1008 }
1009 
1010 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
1011 {
1012 	int r;
1013 
1014 	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
1015 
1016 	amdgpu_gfx_graphics_queue_acquire(adev);
1017 
1018 	r = gfx_v10_0_init_microcode(adev);
1019 	if (r)
1020 		DRM_ERROR("Failed to load gfx firmware!\n");
1021 
1022 	return r;
1023 }
1024 
1025 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
1026 {
1027 	int r;
1028 	u32 *hpd;
1029 	const __le32 *fw_data = NULL;
1030 	unsigned fw_size;
1031 	u32 *fw = NULL;
1032 	size_t mec_hpd_size;
1033 
1034 	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
1035 
1036 	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1037 
1038 	/* take ownership of the relevant compute queues */
1039 	amdgpu_gfx_compute_queue_acquire(adev);
1040 	mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
1041 
1042 	r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1043 				      AMDGPU_GEM_DOMAIN_GTT,
1044 				      &adev->gfx.mec.hpd_eop_obj,
1045 				      &adev->gfx.mec.hpd_eop_gpu_addr,
1046 				      (void **)&hpd);
1047 	if (r) {
1048 		dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1049 		gfx_v10_0_mec_fini(adev);
1050 		return r;
1051 	}
1052 
1053 	memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1054 
1055 	amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1056 	amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1057 
1058 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1059 		mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1060 
1061 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1062 			 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1063 		fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1064 
1065 		r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1066 					      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1067 					      &adev->gfx.mec.mec_fw_obj,
1068 					      &adev->gfx.mec.mec_fw_gpu_addr,
1069 					      (void **)&fw);
1070 		if (r) {
1071 			dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
1072 			gfx_v10_0_mec_fini(adev);
1073 			return r;
1074 		}
1075 
1076 		memcpy(fw, fw_data, fw_size);
1077 
1078 		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1079 		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1080 	}
1081 
1082 	return 0;
1083 }
1084 
1085 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
1086 {
1087 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1088 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1089 		(address << SQ_IND_INDEX__INDEX__SHIFT));
1090 	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1091 }
1092 
1093 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
1094 			   uint32_t thread, uint32_t regno,
1095 			   uint32_t num, uint32_t *out)
1096 {
1097 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1098 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1099 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
1100 		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
1101 		(SQ_IND_INDEX__AUTO_INCR_MASK));
1102 	while (num--)
1103 		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1104 }
1105 
1106 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1107 {
1108 	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE
1109 	 * field when performing a select_se_sh so it should be
1110 	 * zero here */
1111 	WARN_ON(simd != 0);
1112 
1113 	/* type 2 wave data */
1114 	dst[(*no_fields)++] = 2;
1115 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
1116 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
1117 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
1118 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
1119 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
1120 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
1121 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
1122 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
1123 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
1124 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
1125 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
1126 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
1127 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
1128 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
1129 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
1130 }
1131 
1132 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1133 				     uint32_t wave, uint32_t start,
1134 				     uint32_t size, uint32_t *dst)
1135 {
1136 	WARN_ON(simd != 0);
1137 
1138 	wave_read_regs(
1139 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
1140 		dst);
1141 }
1142 
1143 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1144 				      uint32_t wave, uint32_t thread,
1145 				      uint32_t start, uint32_t size,
1146 				      uint32_t *dst)
1147 {
1148 	wave_read_regs(
1149 		adev, wave, thread,
1150 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1151 }
1152 
1153 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
1154 									  u32 me, u32 pipe, u32 q, u32 vm)
1155  {
1156        nv_grbm_select(adev, me, pipe, q, vm);
1157  }
1158 
1159 
1160 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
1161 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
1162 	.select_se_sh = &gfx_v10_0_select_se_sh,
1163 	.read_wave_data = &gfx_v10_0_read_wave_data,
1164 	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
1165 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
1166 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
1167 };
1168 
1169 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
1170 {
1171 	u32 gb_addr_config;
1172 
1173 	adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
1174 
1175 	switch (adev->asic_type) {
1176 	case CHIP_NAVI10:
1177 	case CHIP_NAVI14:
1178 	case CHIP_NAVI12:
1179 		adev->gfx.config.max_hw_contexts = 8;
1180 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1181 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1182 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1183 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1184 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1185 		break;
1186 	default:
1187 		BUG();
1188 		break;
1189 	}
1190 
1191 	adev->gfx.config.gb_addr_config = gb_addr_config;
1192 
1193 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1194 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1195 				      GB_ADDR_CONFIG, NUM_PIPES);
1196 
1197 	adev->gfx.config.max_tile_pipes =
1198 		adev->gfx.config.gb_addr_config_fields.num_pipes;
1199 
1200 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1201 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1202 				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
1203 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1204 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1205 				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
1206 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1207 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1208 				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
1209 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1210 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1211 				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
1212 }
1213 
1214 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
1215 				   int me, int pipe, int queue)
1216 {
1217 	int r;
1218 	struct amdgpu_ring *ring;
1219 	unsigned int irq_type;
1220 
1221 	ring = &adev->gfx.gfx_ring[ring_id];
1222 
1223 	ring->me = me;
1224 	ring->pipe = pipe;
1225 	ring->queue = queue;
1226 
1227 	ring->ring_obj = NULL;
1228 	ring->use_doorbell = true;
1229 
1230 	if (!ring_id)
1231 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1232 	else
1233 		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
1234 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1235 
1236 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
1237 	r = amdgpu_ring_init(adev, ring, 1024,
1238 			     &adev->gfx.eop_irq, irq_type);
1239 	if (r)
1240 		return r;
1241 	return 0;
1242 }
1243 
1244 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1245 				       int mec, int pipe, int queue)
1246 {
1247 	int r;
1248 	unsigned irq_type;
1249 	struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1250 
1251 	ring = &adev->gfx.compute_ring[ring_id];
1252 
1253 	/* mec0 is me1 */
1254 	ring->me = mec + 1;
1255 	ring->pipe = pipe;
1256 	ring->queue = queue;
1257 
1258 	ring->ring_obj = NULL;
1259 	ring->use_doorbell = true;
1260 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1261 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1262 				+ (ring_id * GFX10_MEC_HPD_SIZE);
1263 	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1264 
1265 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1266 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1267 		+ ring->pipe;
1268 
1269 	/* type-2 packets are deprecated on MEC, use type-3 instead */
1270 	r = amdgpu_ring_init(adev, ring, 1024,
1271 			     &adev->gfx.eop_irq, irq_type);
1272 	if (r)
1273 		return r;
1274 
1275 	return 0;
1276 }
1277 
1278 static int gfx_v10_0_sw_init(void *handle)
1279 {
1280 	int i, j, k, r, ring_id = 0;
1281 	struct amdgpu_kiq *kiq;
1282 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1283 
1284 	switch (adev->asic_type) {
1285 	case CHIP_NAVI10:
1286 	case CHIP_NAVI14:
1287 	case CHIP_NAVI12:
1288 		adev->gfx.me.num_me = 1;
1289 		adev->gfx.me.num_pipe_per_me = 2;
1290 		adev->gfx.me.num_queue_per_pipe = 1;
1291 		adev->gfx.mec.num_mec = 2;
1292 		adev->gfx.mec.num_pipe_per_mec = 4;
1293 		adev->gfx.mec.num_queue_per_pipe = 8;
1294 		break;
1295 	default:
1296 		adev->gfx.me.num_me = 1;
1297 		adev->gfx.me.num_pipe_per_me = 1;
1298 		adev->gfx.me.num_queue_per_pipe = 1;
1299 		adev->gfx.mec.num_mec = 1;
1300 		adev->gfx.mec.num_pipe_per_mec = 4;
1301 		adev->gfx.mec.num_queue_per_pipe = 8;
1302 		break;
1303 	}
1304 
1305 	/* KIQ event */
1306 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1307 			      GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
1308 			      &adev->gfx.kiq.irq);
1309 	if (r)
1310 		return r;
1311 
1312 	/* EOP Event */
1313 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1314 			      GFX_10_1__SRCID__CP_EOP_INTERRUPT,
1315 			      &adev->gfx.eop_irq);
1316 	if (r)
1317 		return r;
1318 
1319 	/* Privileged reg */
1320 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
1321 			      &adev->gfx.priv_reg_irq);
1322 	if (r)
1323 		return r;
1324 
1325 	/* Privileged inst */
1326 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
1327 			      &adev->gfx.priv_inst_irq);
1328 	if (r)
1329 		return r;
1330 
1331 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1332 
1333 	gfx_v10_0_scratch_init(adev);
1334 
1335 	r = gfx_v10_0_me_init(adev);
1336 	if (r)
1337 		return r;
1338 
1339 	r = gfx_v10_0_rlc_init(adev);
1340 	if (r) {
1341 		DRM_ERROR("Failed to init rlc BOs!\n");
1342 		return r;
1343 	}
1344 
1345 	r = gfx_v10_0_mec_init(adev);
1346 	if (r) {
1347 		DRM_ERROR("Failed to init MEC BOs!\n");
1348 		return r;
1349 	}
1350 
1351 	/* set up the gfx ring */
1352 	for (i = 0; i < adev->gfx.me.num_me; i++) {
1353 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1354 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1355 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1356 					continue;
1357 
1358 				r = gfx_v10_0_gfx_ring_init(adev, ring_id,
1359 							    i, k, j);
1360 				if (r)
1361 					return r;
1362 				ring_id++;
1363 			}
1364 		}
1365 	}
1366 
1367 	ring_id = 0;
1368 	/* set up the compute queues - allocate horizontally across pipes */
1369 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1370 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1371 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1372 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1373 								     j))
1374 					continue;
1375 
1376 				r = gfx_v10_0_compute_ring_init(adev, ring_id,
1377 								i, k, j);
1378 				if (r)
1379 					return r;
1380 
1381 				ring_id++;
1382 			}
1383 		}
1384 	}
1385 
1386 	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
1387 	if (r) {
1388 		DRM_ERROR("Failed to init KIQ BOs!\n");
1389 		return r;
1390 	}
1391 
1392 	kiq = &adev->gfx.kiq;
1393 	r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1394 	if (r)
1395 		return r;
1396 
1397 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
1398 	if (r)
1399 		return r;
1400 
1401 	/* allocate visible FB for rlc auto-loading fw */
1402 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1403 		r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
1404 		if (r)
1405 			return r;
1406 	}
1407 
1408 	adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
1409 
1410 	gfx_v10_0_gpu_early_init(adev);
1411 
1412 	return 0;
1413 }
1414 
1415 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
1416 {
1417 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1418 			      &adev->gfx.pfp.pfp_fw_gpu_addr,
1419 			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
1420 }
1421 
1422 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
1423 {
1424 	amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
1425 			      &adev->gfx.ce.ce_fw_gpu_addr,
1426 			      (void **)&adev->gfx.ce.ce_fw_ptr);
1427 }
1428 
1429 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
1430 {
1431 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1432 			      &adev->gfx.me.me_fw_gpu_addr,
1433 			      (void **)&adev->gfx.me.me_fw_ptr);
1434 }
1435 
1436 static int gfx_v10_0_sw_fini(void *handle)
1437 {
1438 	int i;
1439 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1440 
1441 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1442 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1443 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
1444 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1445 
1446 	amdgpu_gfx_mqd_sw_fini(adev);
1447 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
1448 	amdgpu_gfx_kiq_fini(adev);
1449 
1450 	gfx_v10_0_pfp_fini(adev);
1451 	gfx_v10_0_ce_fini(adev);
1452 	gfx_v10_0_me_fini(adev);
1453 	gfx_v10_0_rlc_fini(adev);
1454 	gfx_v10_0_mec_fini(adev);
1455 
1456 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1457 		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
1458 
1459 	gfx_v10_0_free_microcode(adev);
1460 
1461 	return 0;
1462 }
1463 
1464 
1465 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
1466 {
1467 	/* TODO */
1468 }
1469 
1470 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1471 				   u32 sh_num, u32 instance)
1472 {
1473 	u32 data;
1474 
1475 	if (instance == 0xffffffff)
1476 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1477 				     INSTANCE_BROADCAST_WRITES, 1);
1478 	else
1479 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1480 				     instance);
1481 
1482 	if (se_num == 0xffffffff)
1483 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1484 				     1);
1485 	else
1486 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1487 
1488 	if (sh_num == 0xffffffff)
1489 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1490 				     1);
1491 	else
1492 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1493 
1494 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1495 }
1496 
1497 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1498 {
1499 	u32 data, mask;
1500 
1501 	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1502 	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1503 
1504 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1505 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1506 
1507 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1508 					 adev->gfx.config.max_sh_per_se);
1509 
1510 	return (~data) & mask;
1511 }
1512 
1513 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
1514 {
1515 	int i, j;
1516 	u32 data;
1517 	u32 active_rbs = 0;
1518 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1519 					adev->gfx.config.max_sh_per_se;
1520 
1521 	mutex_lock(&adev->grbm_idx_mutex);
1522 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1523 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1524 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1525 			data = gfx_v10_0_get_rb_active_bitmap(adev);
1526 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1527 					       rb_bitmap_width_per_sh);
1528 		}
1529 	}
1530 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1531 	mutex_unlock(&adev->grbm_idx_mutex);
1532 
1533 	adev->gfx.config.backend_enable_mask = active_rbs;
1534 	adev->gfx.config.num_rbs = hweight32(active_rbs);
1535 }
1536 
1537 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
1538 {
1539 	uint32_t num_sc;
1540 	uint32_t enabled_rb_per_sh;
1541 	uint32_t active_rb_bitmap;
1542 	uint32_t num_rb_per_sc;
1543 	uint32_t num_packer_per_sc;
1544 	uint32_t pa_sc_tile_steering_override;
1545 
1546 	/* init num_sc */
1547 	num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
1548 			adev->gfx.config.num_sc_per_sh;
1549 	/* init num_rb_per_sc */
1550 	active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
1551 	enabled_rb_per_sh = hweight32(active_rb_bitmap);
1552 	num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
1553 	/* init num_packer_per_sc */
1554 	num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
1555 
1556 	pa_sc_tile_steering_override = 0;
1557 	pa_sc_tile_steering_override |=
1558 		(order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
1559 		PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
1560 	pa_sc_tile_steering_override |=
1561 		(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
1562 		PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
1563 	pa_sc_tile_steering_override |=
1564 		(order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
1565 		PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
1566 
1567 	return pa_sc_tile_steering_override;
1568 }
1569 
1570 #define DEFAULT_SH_MEM_BASES	(0x6000)
1571 #define FIRST_COMPUTE_VMID	(8)
1572 #define LAST_COMPUTE_VMID	(16)
1573 
1574 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
1575 {
1576 	int i;
1577 	uint32_t sh_mem_bases;
1578 
1579 	/*
1580 	 * Configure apertures:
1581 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1582 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1583 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1584 	 */
1585 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1586 
1587 	mutex_lock(&adev->srbm_mutex);
1588 	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1589 		nv_grbm_select(adev, 0, 0, 0, i);
1590 		/* CP and shaders */
1591 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1592 		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1593 	}
1594 	nv_grbm_select(adev, 0, 0, 0, 0);
1595 	mutex_unlock(&adev->srbm_mutex);
1596 
1597 	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
1598 	   acccess. These should be enabled by FW for target VMIDs. */
1599 	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1600 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1601 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
1602 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
1603 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
1604 	}
1605 }
1606 
1607 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
1608 {
1609 	int vmid;
1610 
1611 	/*
1612 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1613 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
1614 	 * the driver can enable them for graphics. VMID0 should maintain
1615 	 * access so that HWS firmware can save/restore entries.
1616 	 */
1617 	for (vmid = 1; vmid < 16; vmid++) {
1618 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
1619 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
1620 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
1621 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
1622 	}
1623 }
1624 
1625 
1626 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
1627 {
1628 	int i, j, k;
1629 	int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
1630 	u32 tmp, wgp_active_bitmap = 0;
1631 	u32 gcrd_targets_disable_tcp = 0;
1632 	u32 utcl_invreq_disable = 0;
1633 	/*
1634 	 * GCRD_TARGETS_DISABLE field contains
1635 	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
1636 	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
1637 	 */
1638 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
1639 		2 * max_wgp_per_sh + /* TCP */
1640 		max_wgp_per_sh + /* SQC */
1641 		4); /* GL1C */
1642 	/*
1643 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
1644 	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
1645 	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
1646 	 */
1647 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
1648 		2 * max_wgp_per_sh + /* TCP */
1649 		2 * max_wgp_per_sh + /* SQC */
1650 		4 + /* RMI */
1651 		1); /* SQG */
1652 
1653 	if (adev->asic_type == CHIP_NAVI10 ||
1654 	    adev->asic_type == CHIP_NAVI14 ||
1655 	    adev->asic_type == CHIP_NAVI12) {
1656 		mutex_lock(&adev->grbm_idx_mutex);
1657 		for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1658 			for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1659 				gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1660 				wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
1661 				/*
1662 				 * Set corresponding TCP bits for the inactive WGPs in
1663 				 * GCRD_SA_TARGETS_DISABLE
1664 				 */
1665 				gcrd_targets_disable_tcp = 0;
1666 				/* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
1667 				utcl_invreq_disable = 0;
1668 
1669 				for (k = 0; k < max_wgp_per_sh; k++) {
1670 					if (!(wgp_active_bitmap & (1 << k))) {
1671 						gcrd_targets_disable_tcp |= 3 << (2 * k);
1672 						utcl_invreq_disable |= (3 << (2 * k)) |
1673 							(3 << (2 * (max_wgp_per_sh + k)));
1674 					}
1675 				}
1676 
1677 				tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1678 				/* only override TCP & SQC bits */
1679 				tmp &= 0xffffffff << (4 * max_wgp_per_sh);
1680 				tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
1681 				WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1682 
1683 				tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1684 				/* only override TCP bits */
1685 				tmp &= 0xffffffff << (2 * max_wgp_per_sh);
1686 				tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
1687 				WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1688 			}
1689 		}
1690 
1691 		gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1692 		mutex_unlock(&adev->grbm_idx_mutex);
1693 	}
1694 }
1695 
1696 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
1697 {
1698 	/* TCCs are global (not instanced). */
1699 	uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
1700 			       RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
1701 
1702 	adev->gfx.config.tcc_disabled_mask =
1703 		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1704 		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1705 }
1706 
1707 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
1708 {
1709 	u32 tmp;
1710 	int i;
1711 
1712 	WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1713 
1714 	gfx_v10_0_tiling_mode_table_init(adev);
1715 
1716 	gfx_v10_0_setup_rb(adev);
1717 	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
1718 	gfx_v10_0_get_tcc_info(adev);
1719 	adev->gfx.config.pa_sc_tile_steering_override =
1720 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
1721 
1722 	/* XXX SH_MEM regs */
1723 	/* where to put LDS, scratch, GPUVM in FSA64 space */
1724 	mutex_lock(&adev->srbm_mutex);
1725 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1726 		nv_grbm_select(adev, 0, 0, 0, i);
1727 		/* CP and shaders */
1728 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1729 		if (i != 0) {
1730 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1731 				(adev->gmc.private_aperture_start >> 48));
1732 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1733 				(adev->gmc.shared_aperture_start >> 48));
1734 			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1735 		}
1736 	}
1737 	nv_grbm_select(adev, 0, 0, 0, 0);
1738 
1739 	mutex_unlock(&adev->srbm_mutex);
1740 
1741 	gfx_v10_0_init_compute_vmid(adev);
1742 	gfx_v10_0_init_gds_vmid(adev);
1743 
1744 }
1745 
1746 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1747 					       bool enable)
1748 {
1749 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1750 
1751 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1752 			    enable ? 1 : 0);
1753 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1754 			    enable ? 1 : 0);
1755 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1756 			    enable ? 1 : 0);
1757 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1758 			    enable ? 1 : 0);
1759 
1760 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1761 }
1762 
1763 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
1764 {
1765 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1766 
1767 	/* csib */
1768 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
1769 		     adev->gfx.rlc.clear_state_gpu_addr >> 32);
1770 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
1771 		     adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1772 	WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1773 
1774 	return 0;
1775 }
1776 
1777 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
1778 {
1779 	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1780 
1781 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1782 	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1783 }
1784 
1785 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
1786 {
1787 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1788 	udelay(50);
1789 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1790 	udelay(50);
1791 }
1792 
1793 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1794 					     bool enable)
1795 {
1796 	uint32_t rlc_pg_cntl;
1797 
1798 	rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
1799 
1800 	if (!enable) {
1801 		/* RLC_PG_CNTL[23] = 0 (default)
1802 		 * RLC will wait for handshake acks with SMU
1803 		 * GFXOFF will be enabled
1804 		 * RLC_PG_CNTL[23] = 1
1805 		 * RLC will not issue any message to SMU
1806 		 * hence no handshake between SMU & RLC
1807 		 * GFXOFF will be disabled
1808 		 */
1809 		rlc_pg_cntl |= 0x800000;
1810 	} else
1811 		rlc_pg_cntl &= ~0x800000;
1812 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
1813 }
1814 
1815 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
1816 {
1817 	/* TODO: enable rlc & smu handshake until smu
1818 	 * and gfxoff feature works as expected */
1819 	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1820 		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
1821 
1822 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1823 	udelay(50);
1824 }
1825 
1826 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
1827 {
1828 	uint32_t tmp;
1829 
1830 	/* enable Save Restore Machine */
1831 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1832 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1833 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1834 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1835 }
1836 
1837 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
1838 {
1839 	const struct rlc_firmware_header_v2_0 *hdr;
1840 	const __le32 *fw_data;
1841 	unsigned i, fw_size;
1842 
1843 	if (!adev->gfx.rlc_fw)
1844 		return -EINVAL;
1845 
1846 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1847 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
1848 
1849 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1850 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1851 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1852 
1853 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1854 		     RLCG_UCODE_LOADING_START_ADDRESS);
1855 
1856 	for (i = 0; i < fw_size; i++)
1857 		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
1858 			     le32_to_cpup(fw_data++));
1859 
1860 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1861 
1862 	return 0;
1863 }
1864 
1865 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
1866 {
1867 	int r;
1868 
1869 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1870 
1871 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1872 		if (r)
1873 			return r;
1874 
1875 		gfx_v10_0_init_csb(adev);
1876 
1877 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
1878 			gfx_v10_0_rlc_enable_srm(adev);
1879 	} else {
1880 		adev->gfx.rlc.funcs->stop(adev);
1881 
1882 		/* disable CG */
1883 		WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1884 
1885 		/* disable PG */
1886 		WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
1887 
1888 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1889 			/* legacy rlc firmware loading */
1890 			r = gfx_v10_0_rlc_load_microcode(adev);
1891 			if (r)
1892 				return r;
1893 		} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1894 			/* rlc backdoor autoload firmware */
1895 			r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
1896 			if (r)
1897 				return r;
1898 		}
1899 
1900 		gfx_v10_0_init_csb(adev);
1901 
1902 		adev->gfx.rlc.funcs->start(adev);
1903 
1904 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1905 			r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1906 			if (r)
1907 				return r;
1908 		}
1909 	}
1910 	return 0;
1911 }
1912 
1913 static struct {
1914 	FIRMWARE_ID	id;
1915 	unsigned int	offset;
1916 	unsigned int	size;
1917 } rlc_autoload_info[FIRMWARE_ID_MAX];
1918 
1919 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
1920 {
1921 	int ret;
1922 	RLC_TABLE_OF_CONTENT *rlc_toc;
1923 
1924 	ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
1925 					AMDGPU_GEM_DOMAIN_GTT,
1926 					&adev->gfx.rlc.rlc_toc_bo,
1927 					&adev->gfx.rlc.rlc_toc_gpu_addr,
1928 					(void **)&adev->gfx.rlc.rlc_toc_buf);
1929 	if (ret) {
1930 		dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
1931 		return ret;
1932 	}
1933 
1934 	/* Copy toc from psp sos fw to rlc toc buffer */
1935 	memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
1936 
1937 	rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
1938 	while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
1939 		(rlc_toc->id < FIRMWARE_ID_MAX)) {
1940 		if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
1941 		    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
1942 			/* Offset needs 4KB alignment */
1943 			rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
1944 		}
1945 
1946 		rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
1947 		rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
1948 		rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
1949 
1950 		rlc_toc++;
1951 	};
1952 
1953 	return 0;
1954 }
1955 
1956 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
1957 {
1958 	uint32_t total_size = 0;
1959 	FIRMWARE_ID id;
1960 	int ret;
1961 
1962 	ret = gfx_v10_0_parse_rlc_toc(adev);
1963 	if (ret) {
1964 		dev_err(adev->dev, "failed to parse rlc toc\n");
1965 		return 0;
1966 	}
1967 
1968 	for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
1969 		total_size += rlc_autoload_info[id].size;
1970 
1971 	/* In case the offset in rlc toc ucode is aligned */
1972 	if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
1973 		total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
1974 				rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
1975 
1976 	return total_size;
1977 }
1978 
1979 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
1980 {
1981 	int r;
1982 	uint32_t total_size;
1983 
1984 	total_size = gfx_v10_0_calc_toc_total_size(adev);
1985 
1986 	r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
1987 				      AMDGPU_GEM_DOMAIN_GTT,
1988 				      &adev->gfx.rlc.rlc_autoload_bo,
1989 				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
1990 				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1991 	if (r) {
1992 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1993 		return r;
1994 	}
1995 
1996 	return 0;
1997 }
1998 
1999 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
2000 {
2001 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
2002 			      &adev->gfx.rlc.rlc_toc_gpu_addr,
2003 			      (void **)&adev->gfx.rlc.rlc_toc_buf);
2004 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
2005 			      &adev->gfx.rlc.rlc_autoload_gpu_addr,
2006 			      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
2007 }
2008 
2009 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
2010 						       FIRMWARE_ID id,
2011 						       const void *fw_data,
2012 						       uint32_t fw_size)
2013 {
2014 	uint32_t toc_offset;
2015 	uint32_t toc_fw_size;
2016 	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
2017 
2018 	if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
2019 		return;
2020 
2021 	toc_offset = rlc_autoload_info[id].offset;
2022 	toc_fw_size = rlc_autoload_info[id].size;
2023 
2024 	if (fw_size == 0)
2025 		fw_size = toc_fw_size;
2026 
2027 	if (fw_size > toc_fw_size)
2028 		fw_size = toc_fw_size;
2029 
2030 	memcpy(ptr + toc_offset, fw_data, fw_size);
2031 
2032 	if (fw_size < toc_fw_size)
2033 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
2034 }
2035 
2036 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
2037 {
2038 	void *data;
2039 	uint32_t size;
2040 
2041 	data = adev->gfx.rlc.rlc_toc_buf;
2042 	size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
2043 
2044 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2045 						   FIRMWARE_ID_RLC_TOC,
2046 						   data, size);
2047 }
2048 
2049 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
2050 {
2051 	const __le32 *fw_data;
2052 	uint32_t fw_size;
2053 	const struct gfx_firmware_header_v1_0 *cp_hdr;
2054 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
2055 
2056 	/* pfp ucode */
2057 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2058 		adev->gfx.pfp_fw->data;
2059 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2060 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2061 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2062 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2063 						   FIRMWARE_ID_CP_PFP,
2064 						   fw_data, fw_size);
2065 
2066 	/* ce ucode */
2067 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2068 		adev->gfx.ce_fw->data;
2069 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2070 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2071 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2072 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2073 						   FIRMWARE_ID_CP_CE,
2074 						   fw_data, fw_size);
2075 
2076 	/* me ucode */
2077 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2078 		adev->gfx.me_fw->data;
2079 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2080 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2081 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2082 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2083 						   FIRMWARE_ID_CP_ME,
2084 						   fw_data, fw_size);
2085 
2086 	/* rlc ucode */
2087 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
2088 		adev->gfx.rlc_fw->data;
2089 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2090 		le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
2091 	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
2092 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2093 						   FIRMWARE_ID_RLC_G_UCODE,
2094 						   fw_data, fw_size);
2095 
2096 	/* mec1 ucode */
2097 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2098 		adev->gfx.mec_fw->data;
2099 	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2100 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2101 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
2102 		cp_hdr->jt_size * 4;
2103 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2104 						   FIRMWARE_ID_CP_MEC,
2105 						   fw_data, fw_size);
2106 	/* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
2107 }
2108 
2109 /* Temporarily put sdma part here */
2110 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
2111 {
2112 	const __le32 *fw_data;
2113 	uint32_t fw_size;
2114 	const struct sdma_firmware_header_v1_0 *sdma_hdr;
2115 	int i;
2116 
2117 	for (i = 0; i < adev->sdma.num_instances; i++) {
2118 		sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
2119 			adev->sdma.instance[i].fw->data;
2120 		fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
2121 			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
2122 		fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
2123 
2124 		if (i == 0) {
2125 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2126 				FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
2127 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2128 				FIRMWARE_ID_SDMA0_JT,
2129 				(uint32_t *)fw_data +
2130 				sdma_hdr->jt_offset,
2131 				sdma_hdr->jt_size * 4);
2132 		} else if (i == 1) {
2133 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2134 				FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
2135 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2136 				FIRMWARE_ID_SDMA1_JT,
2137 				(uint32_t *)fw_data +
2138 				sdma_hdr->jt_offset,
2139 				sdma_hdr->jt_size * 4);
2140 		}
2141 	}
2142 }
2143 
2144 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
2145 {
2146 	uint32_t rlc_g_offset, rlc_g_size, tmp;
2147 	uint64_t gpu_addr;
2148 
2149 	gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
2150 	gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
2151 	gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
2152 
2153 	rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
2154 	rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
2155 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
2156 
2157 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2158 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2159 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
2160 
2161 	tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
2162 	if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
2163 		   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
2164 		DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
2165 		return -EINVAL;
2166 	}
2167 
2168 	tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2169 	if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2170 		DRM_ERROR("RLC ROM should halt itself\n");
2171 		return -EINVAL;
2172 	}
2173 
2174 	return 0;
2175 }
2176 
2177 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
2178 {
2179 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2180 	uint32_t tmp;
2181 	int i;
2182 	uint64_t addr;
2183 
2184 	/* Trigger an invalidation of the L1 instruction caches */
2185 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2186 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2187 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2188 
2189 	/* Wait for invalidation complete */
2190 	for (i = 0; i < usec_timeout; i++) {
2191 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2192 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2193 			INVALIDATE_CACHE_COMPLETE))
2194 			break;
2195 		udelay(1);
2196 	}
2197 
2198 	if (i >= usec_timeout) {
2199 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2200 		return -EINVAL;
2201 	}
2202 
2203 	/* Program me ucode address into intruction cache address register */
2204 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2205 		rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
2206 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2207 			lower_32_bits(addr) & 0xFFFFF000);
2208 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2209 			upper_32_bits(addr));
2210 
2211 	return 0;
2212 }
2213 
2214 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
2215 {
2216 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2217 	uint32_t tmp;
2218 	int i;
2219 	uint64_t addr;
2220 
2221 	/* Trigger an invalidation of the L1 instruction caches */
2222 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2223 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2224 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2225 
2226 	/* Wait for invalidation complete */
2227 	for (i = 0; i < usec_timeout; i++) {
2228 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2229 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2230 			INVALIDATE_CACHE_COMPLETE))
2231 			break;
2232 		udelay(1);
2233 	}
2234 
2235 	if (i >= usec_timeout) {
2236 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2237 		return -EINVAL;
2238 	}
2239 
2240 	/* Program ce ucode address into intruction cache address register */
2241 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2242 		rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
2243 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2244 			lower_32_bits(addr) & 0xFFFFF000);
2245 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2246 			upper_32_bits(addr));
2247 
2248 	return 0;
2249 }
2250 
2251 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
2252 {
2253 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2254 	uint32_t tmp;
2255 	int i;
2256 	uint64_t addr;
2257 
2258 	/* Trigger an invalidation of the L1 instruction caches */
2259 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2260 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2261 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2262 
2263 	/* Wait for invalidation complete */
2264 	for (i = 0; i < usec_timeout; i++) {
2265 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2266 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2267 			INVALIDATE_CACHE_COMPLETE))
2268 			break;
2269 		udelay(1);
2270 	}
2271 
2272 	if (i >= usec_timeout) {
2273 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2274 		return -EINVAL;
2275 	}
2276 
2277 	/* Program pfp ucode address into intruction cache address register */
2278 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2279 		rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
2280 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2281 			lower_32_bits(addr) & 0xFFFFF000);
2282 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2283 			upper_32_bits(addr));
2284 
2285 	return 0;
2286 }
2287 
2288 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
2289 {
2290 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2291 	uint32_t tmp;
2292 	int i;
2293 	uint64_t addr;
2294 
2295 	/* Trigger an invalidation of the L1 instruction caches */
2296 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2297 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2298 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2299 
2300 	/* Wait for invalidation complete */
2301 	for (i = 0; i < usec_timeout; i++) {
2302 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2303 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2304 			INVALIDATE_CACHE_COMPLETE))
2305 			break;
2306 		udelay(1);
2307 	}
2308 
2309 	if (i >= usec_timeout) {
2310 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2311 		return -EINVAL;
2312 	}
2313 
2314 	/* Program mec1 ucode address into intruction cache address register */
2315 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2316 		rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
2317 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2318 			lower_32_bits(addr) & 0xFFFFF000);
2319 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2320 			upper_32_bits(addr));
2321 
2322 	return 0;
2323 }
2324 
2325 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2326 {
2327 	uint32_t cp_status;
2328 	uint32_t bootload_status;
2329 	int i, r;
2330 
2331 	for (i = 0; i < adev->usec_timeout; i++) {
2332 		cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
2333 		bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
2334 		if ((cp_status == 0) &&
2335 		    (REG_GET_FIELD(bootload_status,
2336 			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2337 			break;
2338 		}
2339 		udelay(1);
2340 	}
2341 
2342 	if (i >= adev->usec_timeout) {
2343 		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2344 		return -ETIMEDOUT;
2345 	}
2346 
2347 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2348 		r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
2349 		if (r)
2350 			return r;
2351 
2352 		r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
2353 		if (r)
2354 			return r;
2355 
2356 		r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
2357 		if (r)
2358 			return r;
2359 
2360 		r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
2361 		if (r)
2362 			return r;
2363 	}
2364 
2365 	return 0;
2366 }
2367 
2368 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2369 {
2370 	int i;
2371 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2372 
2373 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2374 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2375 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2376 	if (!enable) {
2377 		for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2378 			adev->gfx.gfx_ring[i].sched.ready = false;
2379 	}
2380 	WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2381 
2382 	for (i = 0; i < adev->usec_timeout; i++) {
2383 		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
2384 			break;
2385 		udelay(1);
2386 	}
2387 
2388 	if (i >= adev->usec_timeout)
2389 		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2390 
2391 	return 0;
2392 }
2393 
2394 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2395 {
2396 	int r;
2397 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
2398 	const __le32 *fw_data;
2399 	unsigned i, fw_size;
2400 	uint32_t tmp;
2401 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2402 
2403 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2404 		adev->gfx.pfp_fw->data;
2405 
2406 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2407 
2408 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2409 		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2410 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2411 
2412 	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2413 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2414 				      &adev->gfx.pfp.pfp_fw_obj,
2415 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
2416 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
2417 	if (r) {
2418 		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2419 		gfx_v10_0_pfp_fini(adev);
2420 		return r;
2421 	}
2422 
2423 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2424 
2425 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2426 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2427 
2428 	/* Trigger an invalidation of the L1 instruction caches */
2429 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2430 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2431 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2432 
2433 	/* Wait for invalidation complete */
2434 	for (i = 0; i < usec_timeout; i++) {
2435 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2436 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2437 			INVALIDATE_CACHE_COMPLETE))
2438 			break;
2439 		udelay(1);
2440 	}
2441 
2442 	if (i >= usec_timeout) {
2443 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2444 		return -EINVAL;
2445 	}
2446 
2447 	if (amdgpu_emu_mode == 1)
2448 		adev->nbio.funcs->hdp_flush(adev, NULL);
2449 
2450 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
2451 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2452 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2453 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2454 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2455 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
2456 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2457 		adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
2458 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2459 		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2460 
2461 	return 0;
2462 }
2463 
2464 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
2465 {
2466 	int r;
2467 	const struct gfx_firmware_header_v1_0 *ce_hdr;
2468 	const __le32 *fw_data;
2469 	unsigned i, fw_size;
2470 	uint32_t tmp;
2471 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2472 
2473 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2474 		adev->gfx.ce_fw->data;
2475 
2476 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2477 
2478 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2479 		le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2480 	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
2481 
2482 	r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
2483 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2484 				      &adev->gfx.ce.ce_fw_obj,
2485 				      &adev->gfx.ce.ce_fw_gpu_addr,
2486 				      (void **)&adev->gfx.ce.ce_fw_ptr);
2487 	if (r) {
2488 		dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
2489 		gfx_v10_0_ce_fini(adev);
2490 		return r;
2491 	}
2492 
2493 	memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
2494 
2495 	amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
2496 	amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
2497 
2498 	/* Trigger an invalidation of the L1 instruction caches */
2499 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2500 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2501 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2502 
2503 	/* Wait for invalidation complete */
2504 	for (i = 0; i < usec_timeout; i++) {
2505 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2506 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2507 			INVALIDATE_CACHE_COMPLETE))
2508 			break;
2509 		udelay(1);
2510 	}
2511 
2512 	if (i >= usec_timeout) {
2513 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2514 		return -EINVAL;
2515 	}
2516 
2517 	if (amdgpu_emu_mode == 1)
2518 		adev->nbio.funcs->hdp_flush(adev, NULL);
2519 
2520 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
2521 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
2522 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
2523 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
2524 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2525 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2526 		adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
2527 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2528 		upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
2529 
2530 	return 0;
2531 }
2532 
2533 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2534 {
2535 	int r;
2536 	const struct gfx_firmware_header_v1_0 *me_hdr;
2537 	const __le32 *fw_data;
2538 	unsigned i, fw_size;
2539 	uint32_t tmp;
2540 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2541 
2542 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
2543 		adev->gfx.me_fw->data;
2544 
2545 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2546 
2547 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2548 		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2549 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2550 
2551 	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2552 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2553 				      &adev->gfx.me.me_fw_obj,
2554 				      &adev->gfx.me.me_fw_gpu_addr,
2555 				      (void **)&adev->gfx.me.me_fw_ptr);
2556 	if (r) {
2557 		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2558 		gfx_v10_0_me_fini(adev);
2559 		return r;
2560 	}
2561 
2562 	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2563 
2564 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2565 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2566 
2567 	/* Trigger an invalidation of the L1 instruction caches */
2568 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2569 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2570 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2571 
2572 	/* Wait for invalidation complete */
2573 	for (i = 0; i < usec_timeout; i++) {
2574 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2575 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2576 			INVALIDATE_CACHE_COMPLETE))
2577 			break;
2578 		udelay(1);
2579 	}
2580 
2581 	if (i >= usec_timeout) {
2582 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2583 		return -EINVAL;
2584 	}
2585 
2586 	if (amdgpu_emu_mode == 1)
2587 		adev->nbio.funcs->hdp_flush(adev, NULL);
2588 
2589 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
2590 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2591 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2592 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2593 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2594 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2595 		adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
2596 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2597 		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2598 
2599 	return 0;
2600 }
2601 
2602 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2603 {
2604 	int r;
2605 
2606 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2607 		return -EINVAL;
2608 
2609 	gfx_v10_0_cp_gfx_enable(adev, false);
2610 
2611 	r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
2612 	if (r) {
2613 		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2614 		return r;
2615 	}
2616 
2617 	r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
2618 	if (r) {
2619 		dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
2620 		return r;
2621 	}
2622 
2623 	r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
2624 	if (r) {
2625 		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2626 		return r;
2627 	}
2628 
2629 	return 0;
2630 }
2631 
2632 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
2633 {
2634 	struct amdgpu_ring *ring;
2635 	const struct cs_section_def *sect = NULL;
2636 	const struct cs_extent_def *ext = NULL;
2637 	int r, i;
2638 	int ctx_reg_offset;
2639 
2640 	/* init the CP */
2641 	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
2642 		     adev->gfx.config.max_hw_contexts - 1);
2643 	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2644 
2645 	gfx_v10_0_cp_gfx_enable(adev, true);
2646 
2647 	ring = &adev->gfx.gfx_ring[0];
2648 	r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
2649 	if (r) {
2650 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2651 		return r;
2652 	}
2653 
2654 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2655 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2656 
2657 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2658 	amdgpu_ring_write(ring, 0x80000000);
2659 	amdgpu_ring_write(ring, 0x80000000);
2660 
2661 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
2662 		for (ext = sect->section; ext->extent != NULL; ++ext) {
2663 			if (sect->id == SECT_CONTEXT) {
2664 				amdgpu_ring_write(ring,
2665 						  PACKET3(PACKET3_SET_CONTEXT_REG,
2666 							  ext->reg_count));
2667 				amdgpu_ring_write(ring, ext->reg_index -
2668 						  PACKET3_SET_CONTEXT_REG_START);
2669 				for (i = 0; i < ext->reg_count; i++)
2670 					amdgpu_ring_write(ring, ext->extent[i]);
2671 			}
2672 		}
2673 	}
2674 
2675 	ctx_reg_offset =
2676 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
2677 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2678 	amdgpu_ring_write(ring, ctx_reg_offset);
2679 	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
2680 
2681 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2682 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2683 
2684 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2685 	amdgpu_ring_write(ring, 0);
2686 
2687 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2688 	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2689 	amdgpu_ring_write(ring, 0x8000);
2690 	amdgpu_ring_write(ring, 0x8000);
2691 
2692 	amdgpu_ring_commit(ring);
2693 
2694 	/* submit cs packet to copy state 0 to next available state */
2695 	ring = &adev->gfx.gfx_ring[1];
2696 	r = amdgpu_ring_alloc(ring, 2);
2697 	if (r) {
2698 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2699 		return r;
2700 	}
2701 
2702 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2703 	amdgpu_ring_write(ring, 0);
2704 
2705 	amdgpu_ring_commit(ring);
2706 
2707 	return 0;
2708 }
2709 
2710 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2711 					 CP_PIPE_ID pipe)
2712 {
2713 	u32 tmp;
2714 
2715 	tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2716 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2717 
2718 	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
2719 }
2720 
2721 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2722 					  struct amdgpu_ring *ring)
2723 {
2724 	u32 tmp;
2725 
2726 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2727 	if (ring->use_doorbell) {
2728 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2729 				    DOORBELL_OFFSET, ring->doorbell_index);
2730 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2731 				    DOORBELL_EN, 1);
2732 	} else {
2733 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2734 				    DOORBELL_EN, 0);
2735 	}
2736 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2737 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2738 			    DOORBELL_RANGE_LOWER, ring->doorbell_index);
2739 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2740 
2741 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2742 		     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2743 }
2744 
2745 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
2746 {
2747 	struct amdgpu_ring *ring;
2748 	u32 tmp;
2749 	u32 rb_bufsz;
2750 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
2751 	u32 i;
2752 
2753 	/* Set the write pointer delay */
2754 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2755 
2756 	/* set the RB to use vmid 0 */
2757 	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2758 
2759 	/* Init gfx ring 0 for pipe 0 */
2760 	mutex_lock(&adev->srbm_mutex);
2761 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2762 
2763 	/* Set ring buffer size */
2764 	ring = &adev->gfx.gfx_ring[0];
2765 	rb_bufsz = order_base_2(ring->ring_size / 8);
2766 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2767 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2768 #ifdef __BIG_ENDIAN
2769 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2770 #endif
2771 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2772 
2773 	/* Initialize the ring buffer's write pointers */
2774 	ring->wptr = 0;
2775 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2776 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2777 
2778 	/* set the wb address wether it's enabled or not */
2779 	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2780 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2781 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2782 		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2783 
2784 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2785 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2786 		     lower_32_bits(wptr_gpu_addr));
2787 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2788 		     upper_32_bits(wptr_gpu_addr));
2789 
2790 	mdelay(1);
2791 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2792 
2793 	rb_addr = ring->gpu_addr >> 8;
2794 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2795 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2796 
2797 	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2798 
2799 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2800 	mutex_unlock(&adev->srbm_mutex);
2801 
2802 	/* Init gfx ring 1 for pipe 1 */
2803 	mutex_lock(&adev->srbm_mutex);
2804 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2805 	ring = &adev->gfx.gfx_ring[1];
2806 	rb_bufsz = order_base_2(ring->ring_size / 8);
2807 	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2808 	tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2809 	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2810 	/* Initialize the ring buffer's write pointers */
2811 	ring->wptr = 0;
2812 	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2813 	WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2814 	/* Set the wb address wether it's enabled or not */
2815 	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2816 	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2817 	WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2818 		CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2819 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2820 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2821 		lower_32_bits(wptr_gpu_addr));
2822 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2823 		upper_32_bits(wptr_gpu_addr));
2824 
2825 	mdelay(1);
2826 	WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2827 
2828 	rb_addr = ring->gpu_addr >> 8;
2829 	WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2830 	WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2831 	WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2832 
2833 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2834 	mutex_unlock(&adev->srbm_mutex);
2835 
2836 	/* Switch to pipe 0 */
2837 	mutex_lock(&adev->srbm_mutex);
2838 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2839 	mutex_unlock(&adev->srbm_mutex);
2840 
2841 	/* start the ring */
2842 	gfx_v10_0_cp_gfx_start(adev);
2843 
2844 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2845 		ring = &adev->gfx.gfx_ring[i];
2846 		ring->sched.ready = true;
2847 	}
2848 
2849 	return 0;
2850 }
2851 
2852 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2853 {
2854 	int i;
2855 
2856 	if (enable) {
2857 		WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2858 	} else {
2859 		WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2860 			     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2861 			      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2862 		for (i = 0; i < adev->gfx.num_compute_rings; i++)
2863 			adev->gfx.compute_ring[i].sched.ready = false;
2864 		adev->gfx.kiq.ring.sched.ready = false;
2865 	}
2866 	udelay(50);
2867 }
2868 
2869 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2870 {
2871 	const struct gfx_firmware_header_v1_0 *mec_hdr;
2872 	const __le32 *fw_data;
2873 	unsigned i;
2874 	u32 tmp;
2875 	u32 usec_timeout = 50000; /* Wait for 50 ms */
2876 
2877 	if (!adev->gfx.mec_fw)
2878 		return -EINVAL;
2879 
2880 	gfx_v10_0_cp_compute_enable(adev, false);
2881 
2882 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2883 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2884 
2885 	fw_data = (const __le32 *)
2886 		(adev->gfx.mec_fw->data +
2887 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2888 
2889 	/* Trigger an invalidation of the L1 instruction caches */
2890 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2891 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2892 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2893 
2894 	/* Wait for invalidation complete */
2895 	for (i = 0; i < usec_timeout; i++) {
2896 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2897 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2898 				       INVALIDATE_CACHE_COMPLETE))
2899 			break;
2900 		udelay(1);
2901 	}
2902 
2903 	if (i >= usec_timeout) {
2904 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2905 		return -EINVAL;
2906 	}
2907 
2908 	if (amdgpu_emu_mode == 1)
2909 		adev->nbio.funcs->hdp_flush(adev, NULL);
2910 
2911 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
2912 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2913 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2914 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2915 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2916 
2917 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
2918 		     0xFFFFF000);
2919 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2920 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2921 
2922 	/* MEC1 */
2923 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
2924 
2925 	for (i = 0; i < mec_hdr->jt_size; i++)
2926 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2927 			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2928 
2929 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2930 
2931 	/*
2932 	 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
2933 	 * different microcode than MEC1.
2934 	 */
2935 
2936 	return 0;
2937 }
2938 
2939 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
2940 {
2941 	uint32_t tmp;
2942 	struct amdgpu_device *adev = ring->adev;
2943 
2944 	/* tell RLC which is KIQ queue */
2945 	tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2946 	tmp &= 0xffffff00;
2947 	tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2948 	WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2949 	tmp |= 0x80;
2950 	WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2951 }
2952 
2953 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
2954 {
2955 	struct amdgpu_device *adev = ring->adev;
2956 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
2957 	uint64_t hqd_gpu_addr, wb_gpu_addr;
2958 	uint32_t tmp;
2959 	uint32_t rb_bufsz;
2960 
2961 	/* set up gfx hqd wptr */
2962 	mqd->cp_gfx_hqd_wptr = 0;
2963 	mqd->cp_gfx_hqd_wptr_hi = 0;
2964 
2965 	/* set the pointer to the MQD */
2966 	mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
2967 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2968 
2969 	/* set up mqd control */
2970 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
2971 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2972 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2973 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2974 	mqd->cp_gfx_mqd_control = tmp;
2975 
2976 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2977 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
2978 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
2979 	mqd->cp_gfx_hqd_vmid = 0;
2980 
2981 	/* set up default queue priority level
2982 	 * 0x0 = low priority, 0x1 = high priority */
2983 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
2984 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
2985 	mqd->cp_gfx_hqd_queue_priority = tmp;
2986 
2987 	/* set up time quantum */
2988 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
2989 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
2990 	mqd->cp_gfx_hqd_quantum = tmp;
2991 
2992 	/* set up gfx hqd base. this is similar as CP_RB_BASE */
2993 	hqd_gpu_addr = ring->gpu_addr >> 8;
2994 	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
2995 	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
2996 
2997 	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
2998 	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2999 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3000 	mqd->cp_gfx_hqd_rptr_addr_hi =
3001 		upper_32_bits(wb_gpu_addr) & 0xffff;
3002 
3003 	/* set up rb_wptr_poll addr */
3004 	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3005 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3006 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3007 
3008 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3009 	rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
3010 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
3011 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3012 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3013 #ifdef __BIG_ENDIAN
3014 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3015 #endif
3016 	mqd->cp_gfx_hqd_cntl = tmp;
3017 
3018 	/* set up cp_doorbell_control */
3019 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3020 	if (ring->use_doorbell) {
3021 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3022 				    DOORBELL_OFFSET, ring->doorbell_index);
3023 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3024 				    DOORBELL_EN, 1);
3025 	} else
3026 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3027 				    DOORBELL_EN, 0);
3028 	mqd->cp_rb_doorbell_control = tmp;
3029 
3030 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3031 	ring->wptr = 0;
3032 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
3033 
3034 	/* active the queue */
3035 	mqd->cp_gfx_hqd_active = 1;
3036 
3037 	return 0;
3038 }
3039 
3040 #ifdef BRING_UP_DEBUG
3041 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3042 {
3043 	struct amdgpu_device *adev = ring->adev;
3044 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3045 
3046 	/* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3047 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3048 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3049 
3050 	/* set GFX_MQD_BASE */
3051 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3052 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3053 
3054 	/* set GFX_MQD_CONTROL */
3055 	WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3056 
3057 	/* set GFX_HQD_VMID to 0 */
3058 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3059 
3060 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
3061 			mqd->cp_gfx_hqd_queue_priority);
3062 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3063 
3064 	/* set GFX_HQD_BASE, similar as CP_RB_BASE */
3065 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3066 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3067 
3068 	/* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
3069 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3070 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3071 
3072 	/* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
3073 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3074 
3075 	/* set RB_WPTR_POLL_ADDR */
3076 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3077 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3078 
3079 	/* set RB_DOORBELL_CONTROL */
3080 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3081 
3082 	/* active the queue */
3083 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3084 
3085 	return 0;
3086 }
3087 #endif
3088 
3089 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
3090 {
3091 	struct amdgpu_device *adev = ring->adev;
3092 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3093 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3094 
3095 	if (!adev->in_gpu_reset && !adev->in_suspend) {
3096 		memset((void *)mqd, 0, sizeof(*mqd));
3097 		mutex_lock(&adev->srbm_mutex);
3098 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3099 		gfx_v10_0_gfx_mqd_init(ring);
3100 #ifdef BRING_UP_DEBUG
3101 		gfx_v10_0_gfx_queue_init_register(ring);
3102 #endif
3103 		nv_grbm_select(adev, 0, 0, 0, 0);
3104 		mutex_unlock(&adev->srbm_mutex);
3105 		if (adev->gfx.me.mqd_backup[mqd_idx])
3106 			memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3107 	} else if (adev->in_gpu_reset) {
3108 		/* reset mqd with the backup copy */
3109 		if (adev->gfx.me.mqd_backup[mqd_idx])
3110 			memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3111 		/* reset the ring */
3112 		ring->wptr = 0;
3113 		adev->wb.wb[ring->wptr_offs] = 0;
3114 		amdgpu_ring_clear_ring(ring);
3115 #ifdef BRING_UP_DEBUG
3116 		mutex_lock(&adev->srbm_mutex);
3117 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3118 		gfx_v10_0_gfx_queue_init_register(ring);
3119 		nv_grbm_select(adev, 0, 0, 0, 0);
3120 		mutex_unlock(&adev->srbm_mutex);
3121 #endif
3122 	} else {
3123 		amdgpu_ring_clear_ring(ring);
3124 	}
3125 
3126 	return 0;
3127 }
3128 
3129 #ifndef BRING_UP_DEBUG
3130 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
3131 {
3132 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3133 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3134 	int r, i;
3135 
3136 	if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3137 		return -EINVAL;
3138 
3139 	r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3140 					adev->gfx.num_gfx_rings);
3141 	if (r) {
3142 		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3143 		return r;
3144 	}
3145 
3146 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3147 		kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3148 
3149 	r = amdgpu_ring_test_ring(kiq_ring);
3150 	if (r) {
3151 		DRM_ERROR("kfq enable failed\n");
3152 		kiq_ring->sched.ready = false;
3153 	}
3154 	return r;
3155 }
3156 #endif
3157 
3158 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3159 {
3160 	int r, i;
3161 	struct amdgpu_ring *ring;
3162 
3163 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3164 		ring = &adev->gfx.gfx_ring[i];
3165 
3166 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
3167 		if (unlikely(r != 0))
3168 			goto done;
3169 
3170 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3171 		if (!r) {
3172 			r = gfx_v10_0_gfx_init_queue(ring);
3173 			amdgpu_bo_kunmap(ring->mqd_obj);
3174 			ring->mqd_ptr = NULL;
3175 		}
3176 		amdgpu_bo_unreserve(ring->mqd_obj);
3177 		if (r)
3178 			goto done;
3179 	}
3180 #ifndef BRING_UP_DEBUG
3181 	r = gfx_v10_0_kiq_enable_kgq(adev);
3182 	if (r)
3183 		goto done;
3184 #endif
3185 	r = gfx_v10_0_cp_gfx_start(adev);
3186 	if (r)
3187 		goto done;
3188 
3189 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3190 		ring = &adev->gfx.gfx_ring[i];
3191 		ring->sched.ready = true;
3192 	}
3193 done:
3194 	return r;
3195 }
3196 
3197 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
3198 {
3199 	struct amdgpu_device *adev = ring->adev;
3200 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
3201 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3202 	uint32_t tmp;
3203 
3204 	mqd->header = 0xC0310800;
3205 	mqd->compute_pipelinestat_enable = 0x00000001;
3206 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3207 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3208 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3209 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3210 	mqd->compute_misc_reserved = 0x00000003;
3211 
3212 	eop_base_addr = ring->eop_gpu_addr >> 8;
3213 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3214 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3215 
3216 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3217 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3218 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3219 			(order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
3220 
3221 	mqd->cp_hqd_eop_control = tmp;
3222 
3223 	/* enable doorbell? */
3224 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3225 
3226 	if (ring->use_doorbell) {
3227 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3228 				    DOORBELL_OFFSET, ring->doorbell_index);
3229 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3230 				    DOORBELL_EN, 1);
3231 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3232 				    DOORBELL_SOURCE, 0);
3233 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3234 				    DOORBELL_HIT, 0);
3235 	} else {
3236 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3237 				    DOORBELL_EN, 0);
3238 	}
3239 
3240 	mqd->cp_hqd_pq_doorbell_control = tmp;
3241 
3242 	/* disable the queue if it's active */
3243 	ring->wptr = 0;
3244 	mqd->cp_hqd_dequeue_request = 0;
3245 	mqd->cp_hqd_pq_rptr = 0;
3246 	mqd->cp_hqd_pq_wptr_lo = 0;
3247 	mqd->cp_hqd_pq_wptr_hi = 0;
3248 
3249 	/* set the pointer to the MQD */
3250 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3251 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3252 
3253 	/* set MQD vmid to 0 */
3254 	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3255 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3256 	mqd->cp_mqd_control = tmp;
3257 
3258 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3259 	hqd_gpu_addr = ring->gpu_addr >> 8;
3260 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3261 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3262 
3263 	/* set up the HQD, this is similar to CP_RB0_CNTL */
3264 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3265 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3266 			    (order_base_2(ring->ring_size / 4) - 1));
3267 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3268 			    ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3269 #ifdef __BIG_ENDIAN
3270 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3271 #endif
3272 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3273 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3274 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3275 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3276 	mqd->cp_hqd_pq_control = tmp;
3277 
3278 	/* set the wb address whether it's enabled or not */
3279 	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3280 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3281 	mqd->cp_hqd_pq_rptr_report_addr_hi =
3282 		upper_32_bits(wb_gpu_addr) & 0xffff;
3283 
3284 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3285 	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3286 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3287 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3288 
3289 	tmp = 0;
3290 	/* enable the doorbell if requested */
3291 	if (ring->use_doorbell) {
3292 		tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3293 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3294 				DOORBELL_OFFSET, ring->doorbell_index);
3295 
3296 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3297 				    DOORBELL_EN, 1);
3298 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3299 				    DOORBELL_SOURCE, 0);
3300 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3301 				    DOORBELL_HIT, 0);
3302 	}
3303 
3304 	mqd->cp_hqd_pq_doorbell_control = tmp;
3305 
3306 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3307 	ring->wptr = 0;
3308 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3309 
3310 	/* set the vmid for the queue */
3311 	mqd->cp_hqd_vmid = 0;
3312 
3313 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3314 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3315 	mqd->cp_hqd_persistent_state = tmp;
3316 
3317 	/* set MIN_IB_AVAIL_SIZE */
3318 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3319 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3320 	mqd->cp_hqd_ib_control = tmp;
3321 
3322 	/* activate the queue */
3323 	mqd->cp_hqd_active = 1;
3324 
3325 	return 0;
3326 }
3327 
3328 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
3329 {
3330 	struct amdgpu_device *adev = ring->adev;
3331 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
3332 	int j;
3333 
3334 	/* disable wptr polling */
3335 	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3336 
3337 	/* write the EOP addr */
3338 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3339 	       mqd->cp_hqd_eop_base_addr_lo);
3340 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3341 	       mqd->cp_hqd_eop_base_addr_hi);
3342 
3343 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3344 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3345 	       mqd->cp_hqd_eop_control);
3346 
3347 	/* enable doorbell? */
3348 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3349 	       mqd->cp_hqd_pq_doorbell_control);
3350 
3351 	/* disable the queue if it's active */
3352 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3353 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3354 		for (j = 0; j < adev->usec_timeout; j++) {
3355 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3356 				break;
3357 			udelay(1);
3358 		}
3359 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3360 		       mqd->cp_hqd_dequeue_request);
3361 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3362 		       mqd->cp_hqd_pq_rptr);
3363 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3364 		       mqd->cp_hqd_pq_wptr_lo);
3365 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3366 		       mqd->cp_hqd_pq_wptr_hi);
3367 	}
3368 
3369 	/* set the pointer to the MQD */
3370 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3371 	       mqd->cp_mqd_base_addr_lo);
3372 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3373 	       mqd->cp_mqd_base_addr_hi);
3374 
3375 	/* set MQD vmid to 0 */
3376 	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3377 	       mqd->cp_mqd_control);
3378 
3379 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3380 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3381 	       mqd->cp_hqd_pq_base_lo);
3382 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3383 	       mqd->cp_hqd_pq_base_hi);
3384 
3385 	/* set up the HQD, this is similar to CP_RB0_CNTL */
3386 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3387 	       mqd->cp_hqd_pq_control);
3388 
3389 	/* set the wb address whether it's enabled or not */
3390 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3391 		mqd->cp_hqd_pq_rptr_report_addr_lo);
3392 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3393 		mqd->cp_hqd_pq_rptr_report_addr_hi);
3394 
3395 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3396 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3397 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
3398 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3399 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
3400 
3401 	/* enable the doorbell if requested */
3402 	if (ring->use_doorbell) {
3403 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3404 			(adev->doorbell_index.kiq * 2) << 2);
3405 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3406 			(adev->doorbell_index.userqueue_end * 2) << 2);
3407 	}
3408 
3409 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3410 	       mqd->cp_hqd_pq_doorbell_control);
3411 
3412 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3413 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3414 	       mqd->cp_hqd_pq_wptr_lo);
3415 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3416 	       mqd->cp_hqd_pq_wptr_hi);
3417 
3418 	/* set the vmid for the queue */
3419 	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3420 
3421 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3422 	       mqd->cp_hqd_persistent_state);
3423 
3424 	/* activate the queue */
3425 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3426 	       mqd->cp_hqd_active);
3427 
3428 	if (ring->use_doorbell)
3429 		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3430 
3431 	return 0;
3432 }
3433 
3434 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
3435 {
3436 	struct amdgpu_device *adev = ring->adev;
3437 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
3438 	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3439 
3440 	gfx_v10_0_kiq_setting(ring);
3441 
3442 	if (adev->in_gpu_reset) { /* for GPU_RESET case */
3443 		/* reset MQD to a clean status */
3444 		if (adev->gfx.mec.mqd_backup[mqd_idx])
3445 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3446 
3447 		/* reset ring buffer */
3448 		ring->wptr = 0;
3449 		amdgpu_ring_clear_ring(ring);
3450 
3451 		mutex_lock(&adev->srbm_mutex);
3452 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3453 		gfx_v10_0_kiq_init_register(ring);
3454 		nv_grbm_select(adev, 0, 0, 0, 0);
3455 		mutex_unlock(&adev->srbm_mutex);
3456 	} else {
3457 		memset((void *)mqd, 0, sizeof(*mqd));
3458 		mutex_lock(&adev->srbm_mutex);
3459 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3460 		gfx_v10_0_compute_mqd_init(ring);
3461 		gfx_v10_0_kiq_init_register(ring);
3462 		nv_grbm_select(adev, 0, 0, 0, 0);
3463 		mutex_unlock(&adev->srbm_mutex);
3464 
3465 		if (adev->gfx.mec.mqd_backup[mqd_idx])
3466 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3467 	}
3468 
3469 	return 0;
3470 }
3471 
3472 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
3473 {
3474 	struct amdgpu_device *adev = ring->adev;
3475 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
3476 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
3477 
3478 	if (!adev->in_gpu_reset && !adev->in_suspend) {
3479 		memset((void *)mqd, 0, sizeof(*mqd));
3480 		mutex_lock(&adev->srbm_mutex);
3481 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3482 		gfx_v10_0_compute_mqd_init(ring);
3483 		nv_grbm_select(adev, 0, 0, 0, 0);
3484 		mutex_unlock(&adev->srbm_mutex);
3485 
3486 		if (adev->gfx.mec.mqd_backup[mqd_idx])
3487 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3488 	} else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3489 		/* reset MQD to a clean status */
3490 		if (adev->gfx.mec.mqd_backup[mqd_idx])
3491 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3492 
3493 		/* reset ring buffer */
3494 		ring->wptr = 0;
3495 		amdgpu_ring_clear_ring(ring);
3496 	} else {
3497 		amdgpu_ring_clear_ring(ring);
3498 	}
3499 
3500 	return 0;
3501 }
3502 
3503 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
3504 {
3505 	struct amdgpu_ring *ring;
3506 	int r;
3507 
3508 	ring = &adev->gfx.kiq.ring;
3509 
3510 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
3511 	if (unlikely(r != 0))
3512 		return r;
3513 
3514 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3515 	if (unlikely(r != 0))
3516 		return r;
3517 
3518 	gfx_v10_0_kiq_init_queue(ring);
3519 	amdgpu_bo_kunmap(ring->mqd_obj);
3520 	ring->mqd_ptr = NULL;
3521 	amdgpu_bo_unreserve(ring->mqd_obj);
3522 	ring->sched.ready = true;
3523 	return 0;
3524 }
3525 
3526 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
3527 {
3528 	struct amdgpu_ring *ring = NULL;
3529 	int r = 0, i;
3530 
3531 	gfx_v10_0_cp_compute_enable(adev, true);
3532 
3533 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3534 		ring = &adev->gfx.compute_ring[i];
3535 
3536 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
3537 		if (unlikely(r != 0))
3538 			goto done;
3539 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3540 		if (!r) {
3541 			r = gfx_v10_0_kcq_init_queue(ring);
3542 			amdgpu_bo_kunmap(ring->mqd_obj);
3543 			ring->mqd_ptr = NULL;
3544 		}
3545 		amdgpu_bo_unreserve(ring->mqd_obj);
3546 		if (r)
3547 			goto done;
3548 	}
3549 
3550 	r = amdgpu_gfx_enable_kcq(adev);
3551 done:
3552 	return r;
3553 }
3554 
3555 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
3556 {
3557 	int r, i;
3558 	struct amdgpu_ring *ring;
3559 
3560 	if (!(adev->flags & AMD_IS_APU))
3561 		gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3562 
3563 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3564 		/* legacy firmware loading */
3565 		r = gfx_v10_0_cp_gfx_load_microcode(adev);
3566 		if (r)
3567 			return r;
3568 
3569 		r = gfx_v10_0_cp_compute_load_microcode(adev);
3570 		if (r)
3571 			return r;
3572 	}
3573 
3574 	r = gfx_v10_0_kiq_resume(adev);
3575 	if (r)
3576 		return r;
3577 
3578 	r = gfx_v10_0_kcq_resume(adev);
3579 	if (r)
3580 		return r;
3581 
3582 	if (!amdgpu_async_gfx_ring) {
3583 		r = gfx_v10_0_cp_gfx_resume(adev);
3584 		if (r)
3585 			return r;
3586 	} else {
3587 		r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
3588 		if (r)
3589 			return r;
3590 	}
3591 
3592 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3593 		ring = &adev->gfx.gfx_ring[i];
3594 		DRM_INFO("gfx %d ring me %d pipe %d q %d\n",
3595 			 i, ring->me, ring->pipe, ring->queue);
3596 		r = amdgpu_ring_test_ring(ring);
3597 		if (r) {
3598 			ring->sched.ready = false;
3599 			return r;
3600 		}
3601 	}
3602 
3603 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3604 		ring = &adev->gfx.compute_ring[i];
3605 		ring->sched.ready = true;
3606 		DRM_INFO("compute ring %d mec %d pipe %d q %d\n",
3607 			 i, ring->me, ring->pipe, ring->queue);
3608 		r = amdgpu_ring_test_ring(ring);
3609 		if (r)
3610 			ring->sched.ready = false;
3611 	}
3612 
3613 	return 0;
3614 }
3615 
3616 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
3617 {
3618 	gfx_v10_0_cp_gfx_enable(adev, enable);
3619 	gfx_v10_0_cp_compute_enable(adev, enable);
3620 }
3621 
3622 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
3623 {
3624 	uint32_t data, pattern = 0xDEADBEEF;
3625 
3626 	/* check if mmVGT_ESGS_RING_SIZE_UMD
3627 	 * has been remapped to mmVGT_ESGS_RING_SIZE */
3628 	data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
3629 
3630 	WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
3631 
3632 	WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
3633 
3634 	if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
3635 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
3636 		return true;
3637 	} else {
3638 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
3639 		return false;
3640 	}
3641 }
3642 
3643 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
3644 {
3645 	uint32_t data;
3646 
3647 	/* initialize cam_index to 0
3648 	 * index will auto-inc after each data writting */
3649 	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
3650 
3651 	/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
3652 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
3653 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3654 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
3655 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3656 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3657 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3658 
3659 	/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
3660 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
3661 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3662 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
3663 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3664 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3665 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3666 
3667 	/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
3668 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
3669 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3670 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
3671 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3672 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3673 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3674 
3675 	/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
3676 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
3677 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3678 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
3679 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3680 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3681 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3682 
3683 	/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
3684 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
3685 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3686 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
3687 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3688 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3689 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3690 
3691 	/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
3692 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
3693 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3694 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
3695 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3696 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3697 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3698 
3699 	/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
3700 	data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
3701 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3702 	       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
3703 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3704 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3705 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3706 }
3707 
3708 static int gfx_v10_0_hw_init(void *handle)
3709 {
3710 	int r;
3711 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3712 
3713 	if (!amdgpu_emu_mode)
3714 		gfx_v10_0_init_golden_registers(adev);
3715 
3716 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3717 		/**
3718 		 * For gfx 10, rlc firmware loading relies on smu firmware is
3719 		 * loaded firstly, so in direct type, it has to load smc ucode
3720 		 * here before rlc.
3721 		 */
3722 		r = smu_load_microcode(&adev->smu);
3723 		if (r)
3724 			return r;
3725 
3726 		r = smu_check_fw_status(&adev->smu);
3727 		if (r) {
3728 			pr_err("SMC firmware status is not correct\n");
3729 			return r;
3730 		}
3731 	}
3732 
3733 	/* if GRBM CAM not remapped, set up the remapping */
3734 	if (!gfx_v10_0_check_grbm_cam_remapping(adev))
3735 		gfx_v10_0_setup_grbm_cam_remapping(adev);
3736 
3737 	gfx_v10_0_constants_init(adev);
3738 
3739 	r = gfx_v10_0_rlc_resume(adev);
3740 	if (r)
3741 		return r;
3742 
3743 	/*
3744 	 * init golden registers and rlc resume may override some registers,
3745 	 * reconfig them here
3746 	 */
3747 	gfx_v10_0_tcp_harvest(adev);
3748 
3749 	r = gfx_v10_0_cp_resume(adev);
3750 	if (r)
3751 		return r;
3752 
3753 	return r;
3754 }
3755 
3756 #ifndef BRING_UP_DEBUG
3757 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
3758 {
3759 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3760 	struct amdgpu_ring *kiq_ring = &kiq->ring;
3761 	int i;
3762 
3763 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
3764 		return -EINVAL;
3765 
3766 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
3767 					adev->gfx.num_gfx_rings))
3768 		return -ENOMEM;
3769 
3770 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3771 		kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
3772 					   PREEMPT_QUEUES, 0, 0);
3773 
3774 	return amdgpu_ring_test_ring(kiq_ring);
3775 }
3776 #endif
3777 
3778 static int gfx_v10_0_hw_fini(void *handle)
3779 {
3780 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3781 	int r;
3782 
3783 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3784 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3785 #ifndef BRING_UP_DEBUG
3786 	if (amdgpu_async_gfx_ring) {
3787 		r = gfx_v10_0_kiq_disable_kgq(adev);
3788 		if (r)
3789 			DRM_ERROR("KGQ disable failed\n");
3790 	}
3791 #endif
3792 	if (amdgpu_gfx_disable_kcq(adev))
3793 		DRM_ERROR("KCQ disable failed\n");
3794 	if (amdgpu_sriov_vf(adev)) {
3795 		gfx_v10_0_cp_gfx_enable(adev, false);
3796 		return 0;
3797 	}
3798 	gfx_v10_0_cp_enable(adev, false);
3799 	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3800 
3801 	return 0;
3802 }
3803 
3804 static int gfx_v10_0_suspend(void *handle)
3805 {
3806 	return gfx_v10_0_hw_fini(handle);
3807 }
3808 
3809 static int gfx_v10_0_resume(void *handle)
3810 {
3811 	return gfx_v10_0_hw_init(handle);
3812 }
3813 
3814 static bool gfx_v10_0_is_idle(void *handle)
3815 {
3816 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3817 
3818 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3819 				GRBM_STATUS, GUI_ACTIVE))
3820 		return false;
3821 	else
3822 		return true;
3823 }
3824 
3825 static int gfx_v10_0_wait_for_idle(void *handle)
3826 {
3827 	unsigned i;
3828 	u32 tmp;
3829 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3830 
3831 	for (i = 0; i < adev->usec_timeout; i++) {
3832 		/* read MC_STATUS */
3833 		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3834 			GRBM_STATUS__GUI_ACTIVE_MASK;
3835 
3836 		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3837 			return 0;
3838 		udelay(1);
3839 	}
3840 	return -ETIMEDOUT;
3841 }
3842 
3843 static int gfx_v10_0_soft_reset(void *handle)
3844 {
3845 	u32 grbm_soft_reset = 0;
3846 	u32 tmp;
3847 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3848 
3849 	/* GRBM_STATUS */
3850 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3851 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3852 		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3853 		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
3854 		   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
3855 		   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
3856 		   | GRBM_STATUS__BCI_BUSY_MASK)) {
3857 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3858 						GRBM_SOFT_RESET, SOFT_RESET_CP,
3859 						1);
3860 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3861 						GRBM_SOFT_RESET, SOFT_RESET_GFX,
3862 						1);
3863 	}
3864 
3865 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3866 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3867 						GRBM_SOFT_RESET, SOFT_RESET_CP,
3868 						1);
3869 	}
3870 
3871 	/* GRBM_STATUS2 */
3872 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3873 	if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3874 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3875 						GRBM_SOFT_RESET, SOFT_RESET_RLC,
3876 						1);
3877 
3878 	if (grbm_soft_reset) {
3879 		/* stop the rlc */
3880 		gfx_v10_0_rlc_stop(adev);
3881 
3882 		/* Disable GFX parsing/prefetching */
3883 		gfx_v10_0_cp_gfx_enable(adev, false);
3884 
3885 		/* Disable MEC parsing/prefetching */
3886 		gfx_v10_0_cp_compute_enable(adev, false);
3887 
3888 		if (grbm_soft_reset) {
3889 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3890 			tmp |= grbm_soft_reset;
3891 			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3892 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3893 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3894 
3895 			udelay(50);
3896 
3897 			tmp &= ~grbm_soft_reset;
3898 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3899 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3900 		}
3901 
3902 		/* Wait a little for things to settle down */
3903 		udelay(50);
3904 	}
3905 	return 0;
3906 }
3907 
3908 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3909 {
3910 	uint64_t clock;
3911 
3912 	mutex_lock(&adev->gfx.gpu_clock_mutex);
3913 	WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3914 	clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3915 		((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3916 	mutex_unlock(&adev->gfx.gpu_clock_mutex);
3917 	return clock;
3918 }
3919 
3920 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3921 					   uint32_t vmid,
3922 					   uint32_t gds_base, uint32_t gds_size,
3923 					   uint32_t gws_base, uint32_t gws_size,
3924 					   uint32_t oa_base, uint32_t oa_size)
3925 {
3926 	struct amdgpu_device *adev = ring->adev;
3927 
3928 	/* GDS Base */
3929 	gfx_v10_0_write_data_to_reg(ring, 0, false,
3930 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3931 				    gds_base);
3932 
3933 	/* GDS Size */
3934 	gfx_v10_0_write_data_to_reg(ring, 0, false,
3935 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3936 				    gds_size);
3937 
3938 	/* GWS */
3939 	gfx_v10_0_write_data_to_reg(ring, 0, false,
3940 				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3941 				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3942 
3943 	/* OA */
3944 	gfx_v10_0_write_data_to_reg(ring, 0, false,
3945 				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3946 				    (1 << (oa_size + oa_base)) - (1 << oa_base));
3947 }
3948 
3949 static int gfx_v10_0_early_init(void *handle)
3950 {
3951 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3952 
3953 	adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;
3954 	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3955 
3956 	gfx_v10_0_set_kiq_pm4_funcs(adev);
3957 	gfx_v10_0_set_ring_funcs(adev);
3958 	gfx_v10_0_set_irq_funcs(adev);
3959 	gfx_v10_0_set_gds_init(adev);
3960 	gfx_v10_0_set_rlc_funcs(adev);
3961 
3962 	return 0;
3963 }
3964 
3965 static int gfx_v10_0_late_init(void *handle)
3966 {
3967 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3968 	int r;
3969 
3970 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3971 	if (r)
3972 		return r;
3973 
3974 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3975 	if (r)
3976 		return r;
3977 
3978 	return 0;
3979 }
3980 
3981 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
3982 {
3983 	uint32_t rlc_cntl;
3984 
3985 	/* if RLC is not enabled, do nothing */
3986 	rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3987 	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
3988 }
3989 
3990 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
3991 {
3992 	uint32_t data;
3993 	unsigned i;
3994 
3995 	data = RLC_SAFE_MODE__CMD_MASK;
3996 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3997 	WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3998 
3999 	/* wait for RLC_SAFE_MODE */
4000 	for (i = 0; i < adev->usec_timeout; i++) {
4001 		if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
4002 			break;
4003 		udelay(1);
4004 	}
4005 }
4006 
4007 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
4008 {
4009 	uint32_t data;
4010 
4011 	data = RLC_SAFE_MODE__CMD_MASK;
4012 	WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4013 }
4014 
4015 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4016 						      bool enable)
4017 {
4018 	uint32_t data, def;
4019 
4020 	/* It is disabled by HW by default */
4021 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4022 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
4023 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4024 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4025 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4026 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4027 
4028 		/* only for Vega10 & Raven1 */
4029 		data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4030 
4031 		if (def != data)
4032 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4033 
4034 		/* MGLS is a global flag to control all MGLS in GFX */
4035 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4036 			/* 2 - RLC memory Light sleep */
4037 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4038 				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4039 				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4040 				if (def != data)
4041 					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4042 			}
4043 			/* 3 - CP memory Light sleep */
4044 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4045 				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4046 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4047 				if (def != data)
4048 					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4049 			}
4050 		}
4051 	} else {
4052 		/* 1 - MGCG_OVERRIDE */
4053 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4054 		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4055 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4056 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4057 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4058 		if (def != data)
4059 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4060 
4061 		/* 2 - disable MGLS in RLC */
4062 		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4063 		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4064 			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4065 			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4066 		}
4067 
4068 		/* 3 - disable MGLS in CP */
4069 		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4070 		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4071 			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4072 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4073 		}
4074 	}
4075 }
4076 
4077 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
4078 					   bool enable)
4079 {
4080 	uint32_t data, def;
4081 
4082 	/* Enable 3D CGCG/CGLS */
4083 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
4084 		/* write cmd to clear cgcg/cgls ov */
4085 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4086 		/* unset CGCG override */
4087 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4088 		/* update CGCG and CGLS override bits */
4089 		if (def != data)
4090 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4091 		/* enable 3Dcgcg FSM(0x0000363f) */
4092 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4093 		data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4094 			RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4095 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4096 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4097 				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4098 		if (def != data)
4099 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4100 
4101 		/* set IDLE_POLL_COUNT(0x00900100) */
4102 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4103 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4104 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4105 		if (def != data)
4106 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4107 	} else {
4108 		/* Disable CGCG/CGLS */
4109 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4110 		/* disable cgcg, cgls should be disabled */
4111 		data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4112 			  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4113 		/* disable cgcg and cgls in FSM */
4114 		if (def != data)
4115 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4116 	}
4117 }
4118 
4119 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4120 						      bool enable)
4121 {
4122 	uint32_t def, data;
4123 
4124 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4125 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4126 		/* unset CGCG override */
4127 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4128 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4129 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4130 		else
4131 			data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4132 		/* update CGCG and CGLS override bits */
4133 		if (def != data)
4134 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4135 
4136 		/* enable cgcg FSM(0x0000363F) */
4137 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4138 		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4139 			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4140 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4141 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4142 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4143 		if (def != data)
4144 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4145 
4146 		/* set IDLE_POLL_COUNT(0x00900100) */
4147 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4148 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4149 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4150 		if (def != data)
4151 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4152 	} else {
4153 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4154 		/* reset CGCG/CGLS bits */
4155 		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4156 		/* disable cgcg and cgls in FSM */
4157 		if (def != data)
4158 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4159 	}
4160 }
4161 
4162 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4163 					    bool enable)
4164 {
4165 	amdgpu_gfx_rlc_enter_safe_mode(adev);
4166 
4167 	if (enable) {
4168 		/* CGCG/CGLS should be enabled after MGCG/MGLS
4169 		 * ===  MGCG + MGLS ===
4170 		 */
4171 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4172 		/* ===  CGCG /CGLS for GFX 3D Only === */
4173 		gfx_v10_0_update_3d_clock_gating(adev, enable);
4174 		/* ===  CGCG + CGLS === */
4175 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4176 	} else {
4177 		/* CGCG/CGLS should be disabled before MGCG/MGLS
4178 		 * ===  CGCG + CGLS ===
4179 		 */
4180 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4181 		/* ===  CGCG /CGLS for GFX 3D Only === */
4182 		gfx_v10_0_update_3d_clock_gating(adev, enable);
4183 		/* ===  MGCG + MGLS === */
4184 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4185 	}
4186 
4187 	if (adev->cg_flags &
4188 	    (AMD_CG_SUPPORT_GFX_MGCG |
4189 	     AMD_CG_SUPPORT_GFX_CGLS |
4190 	     AMD_CG_SUPPORT_GFX_CGCG |
4191 	     AMD_CG_SUPPORT_GFX_CGLS |
4192 	     AMD_CG_SUPPORT_GFX_3D_CGCG |
4193 	     AMD_CG_SUPPORT_GFX_3D_CGLS))
4194 		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
4195 
4196 	amdgpu_gfx_rlc_exit_safe_mode(adev);
4197 
4198 	return 0;
4199 }
4200 
4201 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
4202 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
4203 	.set_safe_mode = gfx_v10_0_set_safe_mode,
4204 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
4205 	.init = gfx_v10_0_rlc_init,
4206 	.get_csb_size = gfx_v10_0_get_csb_size,
4207 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
4208 	.resume = gfx_v10_0_rlc_resume,
4209 	.stop = gfx_v10_0_rlc_stop,
4210 	.reset = gfx_v10_0_rlc_reset,
4211 	.start = gfx_v10_0_rlc_start
4212 };
4213 
4214 static int gfx_v10_0_set_powergating_state(void *handle,
4215 					  enum amd_powergating_state state)
4216 {
4217 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4218 	bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
4219 	switch (adev->asic_type) {
4220 	case CHIP_NAVI10:
4221 	case CHIP_NAVI14:
4222 		if (!enable) {
4223 			amdgpu_gfx_off_ctrl(adev, false);
4224 			cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
4225 		} else
4226 			amdgpu_gfx_off_ctrl(adev, true);
4227 		break;
4228 	default:
4229 		break;
4230 	}
4231 	return 0;
4232 }
4233 
4234 static int gfx_v10_0_set_clockgating_state(void *handle,
4235 					  enum amd_clockgating_state state)
4236 {
4237 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4238 
4239 	switch (adev->asic_type) {
4240 	case CHIP_NAVI10:
4241 	case CHIP_NAVI14:
4242 	case CHIP_NAVI12:
4243 		gfx_v10_0_update_gfx_clock_gating(adev,
4244 						 state == AMD_CG_STATE_GATE ? true : false);
4245 		break;
4246 	default:
4247 		break;
4248 	}
4249 	return 0;
4250 }
4251 
4252 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
4253 {
4254 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4255 	int data;
4256 
4257 	/* AMD_CG_SUPPORT_GFX_MGCG */
4258 	data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4259 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4260 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
4261 
4262 	/* AMD_CG_SUPPORT_GFX_CGCG */
4263 	data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4264 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4265 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
4266 
4267 	/* AMD_CG_SUPPORT_GFX_CGLS */
4268 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4269 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
4270 
4271 	/* AMD_CG_SUPPORT_GFX_RLC_LS */
4272 	data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4273 	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
4274 		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
4275 
4276 	/* AMD_CG_SUPPORT_GFX_CP_LS */
4277 	data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4278 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
4279 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
4280 
4281 	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
4282 	data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4283 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4284 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4285 
4286 	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
4287 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4288 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4289 }
4290 
4291 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4292 {
4293 	return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
4294 }
4295 
4296 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4297 {
4298 	struct amdgpu_device *adev = ring->adev;
4299 	u64 wptr;
4300 
4301 	/* XXX check if swapping is necessary on BE */
4302 	if (ring->use_doorbell) {
4303 		wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4304 	} else {
4305 		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4306 		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4307 	}
4308 
4309 	return wptr;
4310 }
4311 
4312 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4313 {
4314 	struct amdgpu_device *adev = ring->adev;
4315 
4316 	if (ring->use_doorbell) {
4317 		/* XXX check if swapping is necessary on BE */
4318 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4319 		WDOORBELL64(ring->doorbell_index, ring->wptr);
4320 	} else {
4321 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4322 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4323 	}
4324 }
4325 
4326 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4327 {
4328 	return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
4329 }
4330 
4331 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4332 {
4333 	u64 wptr;
4334 
4335 	/* XXX check if swapping is necessary on BE */
4336 	if (ring->use_doorbell)
4337 		wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4338 	else
4339 		BUG();
4340 	return wptr;
4341 }
4342 
4343 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4344 {
4345 	struct amdgpu_device *adev = ring->adev;
4346 
4347 	/* XXX check if swapping is necessary on BE */
4348 	if (ring->use_doorbell) {
4349 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4350 		WDOORBELL64(ring->doorbell_index, ring->wptr);
4351 	} else {
4352 		BUG(); /* only DOORBELL method supported on gfx10 now */
4353 	}
4354 }
4355 
4356 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4357 {
4358 	struct amdgpu_device *adev = ring->adev;
4359 	u32 ref_and_mask, reg_mem_engine;
4360 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4361 
4362 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4363 		switch (ring->me) {
4364 		case 1:
4365 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4366 			break;
4367 		case 2:
4368 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4369 			break;
4370 		default:
4371 			return;
4372 		}
4373 		reg_mem_engine = 0;
4374 	} else {
4375 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4376 		reg_mem_engine = 1; /* pfp */
4377 	}
4378 
4379 	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4380 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4381 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4382 			       ref_and_mask, ref_and_mask, 0x20);
4383 }
4384 
4385 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4386 				       struct amdgpu_job *job,
4387 				       struct amdgpu_ib *ib,
4388 				       uint32_t flags)
4389 {
4390 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4391 	u32 header, control = 0;
4392 
4393 	if (ib->flags & AMDGPU_IB_FLAG_CE)
4394 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
4395 	else
4396 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4397 
4398 	control |= ib->length_dw | (vmid << 24);
4399 
4400 	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4401 		control |= INDIRECT_BUFFER_PRE_ENB(1);
4402 
4403 		if (flags & AMDGPU_IB_PREEMPTED)
4404 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
4405 
4406 		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
4407 			gfx_v10_0_ring_emit_de_meta(ring,
4408 				    flags & AMDGPU_IB_PREEMPTED ? true : false);
4409 	}
4410 
4411 	amdgpu_ring_write(ring, header);
4412 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4413 	amdgpu_ring_write(ring,
4414 #ifdef __BIG_ENDIAN
4415 		(2 << 0) |
4416 #endif
4417 		lower_32_bits(ib->gpu_addr));
4418 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4419 	amdgpu_ring_write(ring, control);
4420 }
4421 
4422 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4423 					   struct amdgpu_job *job,
4424 					   struct amdgpu_ib *ib,
4425 					   uint32_t flags)
4426 {
4427 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4428 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4429 
4430 	/* Currently, there is a high possibility to get wave ID mismatch
4431 	 * between ME and GDS, leading to a hw deadlock, because ME generates
4432 	 * different wave IDs than the GDS expects. This situation happens
4433 	 * randomly when at least 5 compute pipes use GDS ordered append.
4434 	 * The wave IDs generated by ME are also wrong after suspend/resume.
4435 	 * Those are probably bugs somewhere else in the kernel driver.
4436 	 *
4437 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4438 	 * GDS to 0 for this ring (me/pipe).
4439 	 */
4440 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4441 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4442 		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4443 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4444 	}
4445 
4446 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4447 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4448 	amdgpu_ring_write(ring,
4449 #ifdef __BIG_ENDIAN
4450 				(2 << 0) |
4451 #endif
4452 				lower_32_bits(ib->gpu_addr));
4453 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4454 	amdgpu_ring_write(ring, control);
4455 }
4456 
4457 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4458 				     u64 seq, unsigned flags)
4459 {
4460 	struct amdgpu_device *adev = ring->adev;
4461 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4462 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4463 
4464 	/* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
4465 	if (adev->pdev->device == 0x50)
4466 		int_sel = false;
4467 
4468 	/* RELEASE_MEM - flush caches, send int */
4469 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4470 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4471 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
4472 				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
4473 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
4474 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4475 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4476 				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4477 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4478 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4479 
4480 	/*
4481 	 * the address should be Qword aligned if 64bit write, Dword
4482 	 * aligned if only send 32bit data low (discard data high)
4483 	 */
4484 	if (write64bit)
4485 		BUG_ON(addr & 0x7);
4486 	else
4487 		BUG_ON(addr & 0x3);
4488 	amdgpu_ring_write(ring, lower_32_bits(addr));
4489 	amdgpu_ring_write(ring, upper_32_bits(addr));
4490 	amdgpu_ring_write(ring, lower_32_bits(seq));
4491 	amdgpu_ring_write(ring, upper_32_bits(seq));
4492 	amdgpu_ring_write(ring, 0);
4493 }
4494 
4495 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4496 {
4497 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4498 	uint32_t seq = ring->fence_drv.sync_seq;
4499 	uint64_t addr = ring->fence_drv.gpu_addr;
4500 
4501 	gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4502 			       upper_32_bits(addr), seq, 0xffffffff, 4);
4503 }
4504 
4505 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4506 					 unsigned vmid, uint64_t pd_addr)
4507 {
4508 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4509 
4510 	/* compute doesn't have PFP */
4511 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4512 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
4513 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4514 		amdgpu_ring_write(ring, 0x0);
4515 	}
4516 }
4517 
4518 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4519 					  u64 seq, unsigned int flags)
4520 {
4521 	struct amdgpu_device *adev = ring->adev;
4522 
4523 	/* we only allocate 32bit for each seq wb address */
4524 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4525 
4526 	/* write fence seq to the "addr" */
4527 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4528 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4529 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4530 	amdgpu_ring_write(ring, lower_32_bits(addr));
4531 	amdgpu_ring_write(ring, upper_32_bits(addr));
4532 	amdgpu_ring_write(ring, lower_32_bits(seq));
4533 
4534 	if (flags & AMDGPU_FENCE_FLAG_INT) {
4535 		/* set register to trigger INT */
4536 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4537 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4538 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4539 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4540 		amdgpu_ring_write(ring, 0);
4541 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4542 	}
4543 }
4544 
4545 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
4546 {
4547 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4548 	amdgpu_ring_write(ring, 0);
4549 }
4550 
4551 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4552 {
4553 	uint32_t dw2 = 0;
4554 
4555 	if (amdgpu_mcbp)
4556 		gfx_v10_0_ring_emit_ce_meta(ring,
4557 				    flags & AMDGPU_IB_PREEMPTED ? true : false);
4558 
4559 	gfx_v10_0_ring_emit_tmz(ring, true);
4560 
4561 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4562 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4563 		/* set load_global_config & load_global_uconfig */
4564 		dw2 |= 0x8001;
4565 		/* set load_cs_sh_regs */
4566 		dw2 |= 0x01000000;
4567 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
4568 		dw2 |= 0x10002;
4569 
4570 		/* set load_ce_ram if preamble presented */
4571 		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4572 			dw2 |= 0x10000000;
4573 	} else {
4574 		/* still load_ce_ram if this is the first time preamble presented
4575 		 * although there is no context switch happens.
4576 		 */
4577 		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4578 			dw2 |= 0x10000000;
4579 	}
4580 
4581 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4582 	amdgpu_ring_write(ring, dw2);
4583 	amdgpu_ring_write(ring, 0);
4584 }
4585 
4586 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4587 {
4588 	unsigned ret;
4589 
4590 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4591 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4592 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4593 	amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4594 	ret = ring->wptr & ring->buf_mask;
4595 	amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4596 
4597 	return ret;
4598 }
4599 
4600 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4601 {
4602 	unsigned cur;
4603 	BUG_ON(offset > ring->buf_mask);
4604 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
4605 
4606 	cur = (ring->wptr - 1) & ring->buf_mask;
4607 	if (likely(cur > offset))
4608 		ring->ring[offset] = cur - offset;
4609 	else
4610 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
4611 }
4612 
4613 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
4614 {
4615 	int i, r = 0;
4616 	struct amdgpu_device *adev = ring->adev;
4617 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4618 	struct amdgpu_ring *kiq_ring = &kiq->ring;
4619 
4620 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4621 		return -EINVAL;
4622 
4623 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
4624 		return -ENOMEM;
4625 
4626 	/* assert preemption condition */
4627 	amdgpu_ring_set_preempt_cond_exec(ring, false);
4628 
4629 	/* assert IB preemption, emit the trailing fence */
4630 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4631 				   ring->trail_fence_gpu_addr,
4632 				   ++ring->trail_seq);
4633 	amdgpu_ring_commit(kiq_ring);
4634 
4635 	/* poll the trailing fence */
4636 	for (i = 0; i < adev->usec_timeout; i++) {
4637 		if (ring->trail_seq ==
4638 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4639 			break;
4640 		udelay(1);
4641 	}
4642 
4643 	if (i >= adev->usec_timeout) {
4644 		r = -EINVAL;
4645 		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4646 	}
4647 
4648 	/* deassert preemption condition */
4649 	amdgpu_ring_set_preempt_cond_exec(ring, true);
4650 	return r;
4651 }
4652 
4653 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
4654 {
4655 	struct amdgpu_device *adev = ring->adev;
4656 	struct v10_ce_ib_state ce_payload = {0};
4657 	uint64_t csa_addr;
4658 	int cnt;
4659 
4660 	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4661 	csa_addr = amdgpu_csa_vaddr(ring->adev);
4662 
4663 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4664 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4665 				 WRITE_DATA_DST_SEL(8) |
4666 				 WR_CONFIRM) |
4667 				 WRITE_DATA_CACHE_POLICY(0));
4668 	amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4669 			      offsetof(struct v10_gfx_meta_data, ce_payload)));
4670 	amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4671 			      offsetof(struct v10_gfx_meta_data, ce_payload)));
4672 
4673 	if (resume)
4674 		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4675 					   offsetof(struct v10_gfx_meta_data,
4676 						    ce_payload),
4677 					   sizeof(ce_payload) >> 2);
4678 	else
4679 		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
4680 					   sizeof(ce_payload) >> 2);
4681 }
4682 
4683 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
4684 {
4685 	struct amdgpu_device *adev = ring->adev;
4686 	struct v10_de_ib_state de_payload = {0};
4687 	uint64_t csa_addr, gds_addr;
4688 	int cnt;
4689 
4690 	csa_addr = amdgpu_csa_vaddr(ring->adev);
4691 	gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
4692 			 PAGE_SIZE);
4693 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4694 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4695 
4696 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4697 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4698 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4699 				 WRITE_DATA_DST_SEL(8) |
4700 				 WR_CONFIRM) |
4701 				 WRITE_DATA_CACHE_POLICY(0));
4702 	amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4703 			      offsetof(struct v10_gfx_meta_data, de_payload)));
4704 	amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4705 			      offsetof(struct v10_gfx_meta_data, de_payload)));
4706 
4707 	if (resume)
4708 		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4709 					   offsetof(struct v10_gfx_meta_data,
4710 						    de_payload),
4711 					   sizeof(de_payload) >> 2);
4712 	else
4713 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
4714 					   sizeof(de_payload) >> 2);
4715 }
4716 
4717 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4718 {
4719 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4720 	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4721 }
4722 
4723 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4724 {
4725 	struct amdgpu_device *adev = ring->adev;
4726 
4727 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4728 	amdgpu_ring_write(ring, 0 |	/* src: register*/
4729 				(5 << 8) |	/* dst: memory */
4730 				(1 << 20));	/* write confirm */
4731 	amdgpu_ring_write(ring, reg);
4732 	amdgpu_ring_write(ring, 0);
4733 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4734 				adev->virt.reg_val_offs * 4));
4735 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4736 				adev->virt.reg_val_offs * 4));
4737 }
4738 
4739 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4740 				   uint32_t val)
4741 {
4742 	uint32_t cmd = 0;
4743 
4744 	switch (ring->funcs->type) {
4745 	case AMDGPU_RING_TYPE_GFX:
4746 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4747 		break;
4748 	case AMDGPU_RING_TYPE_KIQ:
4749 		cmd = (1 << 16); /* no inc addr */
4750 		break;
4751 	default:
4752 		cmd = WR_CONFIRM;
4753 		break;
4754 	}
4755 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4756 	amdgpu_ring_write(ring, cmd);
4757 	amdgpu_ring_write(ring, reg);
4758 	amdgpu_ring_write(ring, 0);
4759 	amdgpu_ring_write(ring, val);
4760 }
4761 
4762 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4763 					uint32_t val, uint32_t mask)
4764 {
4765 	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4766 }
4767 
4768 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4769 						   uint32_t reg0, uint32_t reg1,
4770 						   uint32_t ref, uint32_t mask)
4771 {
4772 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4773 	struct amdgpu_device *adev = ring->adev;
4774 	bool fw_version_ok = false;
4775 
4776 	fw_version_ok = adev->gfx.cp_fw_write_wait;
4777 
4778 	if (fw_version_ok)
4779 		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4780 				       ref, mask, 0x20);
4781 	else
4782 		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4783 							   ref, mask);
4784 }
4785 
4786 static void
4787 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4788 				      uint32_t me, uint32_t pipe,
4789 				      enum amdgpu_interrupt_state state)
4790 {
4791 	uint32_t cp_int_cntl, cp_int_cntl_reg;
4792 
4793 	if (!me) {
4794 		switch (pipe) {
4795 		case 0:
4796 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
4797 			break;
4798 		case 1:
4799 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
4800 			break;
4801 		default:
4802 			DRM_DEBUG("invalid pipe %d\n", pipe);
4803 			return;
4804 		}
4805 	} else {
4806 		DRM_DEBUG("invalid me %d\n", me);
4807 		return;
4808 	}
4809 
4810 	switch (state) {
4811 	case AMDGPU_IRQ_STATE_DISABLE:
4812 		cp_int_cntl = RREG32(cp_int_cntl_reg);
4813 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4814 					    TIME_STAMP_INT_ENABLE, 0);
4815 		WREG32(cp_int_cntl_reg, cp_int_cntl);
4816 		break;
4817 	case AMDGPU_IRQ_STATE_ENABLE:
4818 		cp_int_cntl = RREG32(cp_int_cntl_reg);
4819 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4820 					    TIME_STAMP_INT_ENABLE, 1);
4821 		WREG32(cp_int_cntl_reg, cp_int_cntl);
4822 		break;
4823 	default:
4824 		break;
4825 	}
4826 }
4827 
4828 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4829 						     int me, int pipe,
4830 						     enum amdgpu_interrupt_state state)
4831 {
4832 	u32 mec_int_cntl, mec_int_cntl_reg;
4833 
4834 	/*
4835 	 * amdgpu controls only the first MEC. That's why this function only
4836 	 * handles the setting of interrupts for this specific MEC. All other
4837 	 * pipes' interrupts are set by amdkfd.
4838 	 */
4839 
4840 	if (me == 1) {
4841 		switch (pipe) {
4842 		case 0:
4843 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4844 			break;
4845 		case 1:
4846 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4847 			break;
4848 		case 2:
4849 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4850 			break;
4851 		case 3:
4852 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4853 			break;
4854 		default:
4855 			DRM_DEBUG("invalid pipe %d\n", pipe);
4856 			return;
4857 		}
4858 	} else {
4859 		DRM_DEBUG("invalid me %d\n", me);
4860 		return;
4861 	}
4862 
4863 	switch (state) {
4864 	case AMDGPU_IRQ_STATE_DISABLE:
4865 		mec_int_cntl = RREG32(mec_int_cntl_reg);
4866 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4867 					     TIME_STAMP_INT_ENABLE, 0);
4868 		WREG32(mec_int_cntl_reg, mec_int_cntl);
4869 		break;
4870 	case AMDGPU_IRQ_STATE_ENABLE:
4871 		mec_int_cntl = RREG32(mec_int_cntl_reg);
4872 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4873 					     TIME_STAMP_INT_ENABLE, 1);
4874 		WREG32(mec_int_cntl_reg, mec_int_cntl);
4875 		break;
4876 	default:
4877 		break;
4878 	}
4879 }
4880 
4881 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4882 					    struct amdgpu_irq_src *src,
4883 					    unsigned type,
4884 					    enum amdgpu_interrupt_state state)
4885 {
4886 	switch (type) {
4887 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4888 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4889 		break;
4890 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4891 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4892 		break;
4893 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4894 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4895 		break;
4896 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4897 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4898 		break;
4899 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4900 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4901 		break;
4902 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4903 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4904 		break;
4905 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4906 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4907 		break;
4908 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4909 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4910 		break;
4911 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4912 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4913 		break;
4914 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4915 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4916 		break;
4917 	default:
4918 		break;
4919 	}
4920 	return 0;
4921 }
4922 
4923 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
4924 			     struct amdgpu_irq_src *source,
4925 			     struct amdgpu_iv_entry *entry)
4926 {
4927 	int i;
4928 	u8 me_id, pipe_id, queue_id;
4929 	struct amdgpu_ring *ring;
4930 
4931 	DRM_DEBUG("IH: CP EOP\n");
4932 	me_id = (entry->ring_id & 0x0c) >> 2;
4933 	pipe_id = (entry->ring_id & 0x03) >> 0;
4934 	queue_id = (entry->ring_id & 0x70) >> 4;
4935 
4936 	switch (me_id) {
4937 	case 0:
4938 		if (pipe_id == 0)
4939 			amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4940 		else
4941 			amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4942 		break;
4943 	case 1:
4944 	case 2:
4945 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4946 			ring = &adev->gfx.compute_ring[i];
4947 			/* Per-queue interrupt is supported for MEC starting from VI.
4948 			  * The interrupt can only be enabled/disabled per pipe instead of per queue.
4949 			  */
4950 			if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4951 				amdgpu_fence_process(ring);
4952 		}
4953 		break;
4954 	}
4955 	return 0;
4956 }
4957 
4958 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4959 					      struct amdgpu_irq_src *source,
4960 					      unsigned type,
4961 					      enum amdgpu_interrupt_state state)
4962 {
4963 	switch (state) {
4964 	case AMDGPU_IRQ_STATE_DISABLE:
4965 	case AMDGPU_IRQ_STATE_ENABLE:
4966 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4967 			       PRIV_REG_INT_ENABLE,
4968 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4969 		break;
4970 	default:
4971 		break;
4972 	}
4973 
4974 	return 0;
4975 }
4976 
4977 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4978 					       struct amdgpu_irq_src *source,
4979 					       unsigned type,
4980 					       enum amdgpu_interrupt_state state)
4981 {
4982 	switch (state) {
4983 	case AMDGPU_IRQ_STATE_DISABLE:
4984 	case AMDGPU_IRQ_STATE_ENABLE:
4985 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4986 			       PRIV_INSTR_INT_ENABLE,
4987 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4988 	default:
4989 		break;
4990 	}
4991 
4992 	return 0;
4993 }
4994 
4995 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
4996 					struct amdgpu_iv_entry *entry)
4997 {
4998 	u8 me_id, pipe_id, queue_id;
4999 	struct amdgpu_ring *ring;
5000 	int i;
5001 
5002 	me_id = (entry->ring_id & 0x0c) >> 2;
5003 	pipe_id = (entry->ring_id & 0x03) >> 0;
5004 	queue_id = (entry->ring_id & 0x70) >> 4;
5005 
5006 	switch (me_id) {
5007 	case 0:
5008 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5009 			ring = &adev->gfx.gfx_ring[i];
5010 			/* we only enabled 1 gfx queue per pipe for now */
5011 			if (ring->me == me_id && ring->pipe == pipe_id)
5012 				drm_sched_fault(&ring->sched);
5013 		}
5014 		break;
5015 	case 1:
5016 	case 2:
5017 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5018 			ring = &adev->gfx.compute_ring[i];
5019 			if (ring->me == me_id && ring->pipe == pipe_id &&
5020 			    ring->queue == queue_id)
5021 				drm_sched_fault(&ring->sched);
5022 		}
5023 		break;
5024 	default:
5025 		BUG();
5026 	}
5027 }
5028 
5029 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
5030 				  struct amdgpu_irq_src *source,
5031 				  struct amdgpu_iv_entry *entry)
5032 {
5033 	DRM_ERROR("Illegal register access in command stream\n");
5034 	gfx_v10_0_handle_priv_fault(adev, entry);
5035 	return 0;
5036 }
5037 
5038 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
5039 				   struct amdgpu_irq_src *source,
5040 				   struct amdgpu_iv_entry *entry)
5041 {
5042 	DRM_ERROR("Illegal instruction in command stream\n");
5043 	gfx_v10_0_handle_priv_fault(adev, entry);
5044 	return 0;
5045 }
5046 
5047 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5048 					     struct amdgpu_irq_src *src,
5049 					     unsigned int type,
5050 					     enum amdgpu_interrupt_state state)
5051 {
5052 	uint32_t tmp, target;
5053 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5054 
5055 	if (ring->me == 1)
5056 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5057 	else
5058 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
5059 	target += ring->pipe;
5060 
5061 	switch (type) {
5062 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5063 		if (state == AMDGPU_IRQ_STATE_DISABLE) {
5064 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5065 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5066 					    GENERIC2_INT_ENABLE, 0);
5067 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5068 
5069 			tmp = RREG32(target);
5070 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5071 					    GENERIC2_INT_ENABLE, 0);
5072 			WREG32(target, tmp);
5073 		} else {
5074 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5075 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5076 					    GENERIC2_INT_ENABLE, 1);
5077 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5078 
5079 			tmp = RREG32(target);
5080 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5081 					    GENERIC2_INT_ENABLE, 1);
5082 			WREG32(target, tmp);
5083 		}
5084 		break;
5085 	default:
5086 		BUG(); /* kiq only support GENERIC2_INT now */
5087 		break;
5088 	}
5089 	return 0;
5090 }
5091 
5092 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
5093 			     struct amdgpu_irq_src *source,
5094 			     struct amdgpu_iv_entry *entry)
5095 {
5096 	u8 me_id, pipe_id, queue_id;
5097 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5098 
5099 	me_id = (entry->ring_id & 0x0c) >> 2;
5100 	pipe_id = (entry->ring_id & 0x03) >> 0;
5101 	queue_id = (entry->ring_id & 0x70) >> 4;
5102 	DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
5103 		   me_id, pipe_id, queue_id);
5104 
5105 	amdgpu_fence_process(ring);
5106 	return 0;
5107 }
5108 
5109 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
5110 	.name = "gfx_v10_0",
5111 	.early_init = gfx_v10_0_early_init,
5112 	.late_init = gfx_v10_0_late_init,
5113 	.sw_init = gfx_v10_0_sw_init,
5114 	.sw_fini = gfx_v10_0_sw_fini,
5115 	.hw_init = gfx_v10_0_hw_init,
5116 	.hw_fini = gfx_v10_0_hw_fini,
5117 	.suspend = gfx_v10_0_suspend,
5118 	.resume = gfx_v10_0_resume,
5119 	.is_idle = gfx_v10_0_is_idle,
5120 	.wait_for_idle = gfx_v10_0_wait_for_idle,
5121 	.soft_reset = gfx_v10_0_soft_reset,
5122 	.set_clockgating_state = gfx_v10_0_set_clockgating_state,
5123 	.set_powergating_state = gfx_v10_0_set_powergating_state,
5124 	.get_clockgating_state = gfx_v10_0_get_clockgating_state,
5125 };
5126 
5127 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
5128 	.type = AMDGPU_RING_TYPE_GFX,
5129 	.align_mask = 0xff,
5130 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
5131 	.support_64bit_ptrs = true,
5132 	.vmhub = AMDGPU_GFXHUB_0,
5133 	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
5134 	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
5135 	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
5136 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
5137 		5 + /* COND_EXEC */
5138 		7 + /* PIPELINE_SYNC */
5139 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5140 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5141 		2 + /* VM_FLUSH */
5142 		8 + /* FENCE for VM_FLUSH */
5143 		20 + /* GDS switch */
5144 		4 + /* double SWITCH_BUFFER,
5145 		     * the first COND_EXEC jump to the place
5146 		     * just prior to this double SWITCH_BUFFER
5147 		     */
5148 		5 + /* COND_EXEC */
5149 		7 + /* HDP_flush */
5150 		4 + /* VGT_flush */
5151 		14 + /*	CE_META */
5152 		31 + /*	DE_META */
5153 		3 + /* CNTX_CTRL */
5154 		5 + /* HDP_INVL */
5155 		8 + 8 + /* FENCE x2 */
5156 		2, /* SWITCH_BUFFER */
5157 	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
5158 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
5159 	.emit_fence = gfx_v10_0_ring_emit_fence,
5160 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5161 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5162 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5163 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5164 	.test_ring = gfx_v10_0_ring_test_ring,
5165 	.test_ib = gfx_v10_0_ring_test_ib,
5166 	.insert_nop = amdgpu_ring_insert_nop,
5167 	.pad_ib = amdgpu_ring_generic_pad_ib,
5168 	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
5169 	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
5170 	.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
5171 	.patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
5172 	.preempt_ib = gfx_v10_0_ring_preempt_ib,
5173 	.emit_tmz = gfx_v10_0_ring_emit_tmz,
5174 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
5175 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5176 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5177 };
5178 
5179 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
5180 	.type = AMDGPU_RING_TYPE_COMPUTE,
5181 	.align_mask = 0xff,
5182 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
5183 	.support_64bit_ptrs = true,
5184 	.vmhub = AMDGPU_GFXHUB_0,
5185 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
5186 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
5187 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
5188 	.emit_frame_size =
5189 		20 + /* gfx_v10_0_ring_emit_gds_switch */
5190 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
5191 		5 + /* hdp invalidate */
5192 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5193 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5194 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5195 		2 + /* gfx_v10_0_ring_emit_vm_flush */
5196 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
5197 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
5198 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
5199 	.emit_fence = gfx_v10_0_ring_emit_fence,
5200 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5201 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5202 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5203 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5204 	.test_ring = gfx_v10_0_ring_test_ring,
5205 	.test_ib = gfx_v10_0_ring_test_ib,
5206 	.insert_nop = amdgpu_ring_insert_nop,
5207 	.pad_ib = amdgpu_ring_generic_pad_ib,
5208 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
5209 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5210 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5211 };
5212 
5213 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
5214 	.type = AMDGPU_RING_TYPE_KIQ,
5215 	.align_mask = 0xff,
5216 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
5217 	.support_64bit_ptrs = true,
5218 	.vmhub = AMDGPU_GFXHUB_0,
5219 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
5220 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
5221 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
5222 	.emit_frame_size =
5223 		20 + /* gfx_v10_0_ring_emit_gds_switch */
5224 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
5225 		5 + /*hdp invalidate */
5226 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
5227 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5228 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5229 		2 + /* gfx_v10_0_ring_emit_vm_flush */
5230 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5231 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
5232 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
5233 	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
5234 	.test_ring = gfx_v10_0_ring_test_ring,
5235 	.test_ib = gfx_v10_0_ring_test_ib,
5236 	.insert_nop = amdgpu_ring_insert_nop,
5237 	.pad_ib = amdgpu_ring_generic_pad_ib,
5238 	.emit_rreg = gfx_v10_0_ring_emit_rreg,
5239 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
5240 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5241 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5242 };
5243 
5244 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
5245 {
5246 	int i;
5247 
5248 	adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
5249 
5250 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5251 		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
5252 
5253 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
5254 		adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
5255 }
5256 
5257 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
5258 	.set = gfx_v10_0_set_eop_interrupt_state,
5259 	.process = gfx_v10_0_eop_irq,
5260 };
5261 
5262 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
5263 	.set = gfx_v10_0_set_priv_reg_fault_state,
5264 	.process = gfx_v10_0_priv_reg_irq,
5265 };
5266 
5267 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
5268 	.set = gfx_v10_0_set_priv_inst_fault_state,
5269 	.process = gfx_v10_0_priv_inst_irq,
5270 };
5271 
5272 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
5273 	.set = gfx_v10_0_kiq_set_interrupt_state,
5274 	.process = gfx_v10_0_kiq_irq,
5275 };
5276 
5277 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
5278 {
5279 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5280 	adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
5281 
5282 	adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
5283 	adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
5284 
5285 	adev->gfx.priv_reg_irq.num_types = 1;
5286 	adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
5287 
5288 	adev->gfx.priv_inst_irq.num_types = 1;
5289 	adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
5290 }
5291 
5292 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
5293 {
5294 	switch (adev->asic_type) {
5295 	case CHIP_NAVI10:
5296 	case CHIP_NAVI14:
5297 	case CHIP_NAVI12:
5298 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
5299 		break;
5300 	default:
5301 		break;
5302 	}
5303 }
5304 
5305 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
5306 {
5307 	unsigned total_cu = adev->gfx.config.max_cu_per_sh *
5308 			    adev->gfx.config.max_sh_per_se *
5309 			    adev->gfx.config.max_shader_engines;
5310 
5311 	adev->gds.gds_size = 0x10000;
5312 	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
5313 	adev->gds.gws_size = 64;
5314 	adev->gds.oa_size = 16;
5315 }
5316 
5317 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5318 							  u32 bitmap)
5319 {
5320 	u32 data;
5321 
5322 	if (!bitmap)
5323 		return;
5324 
5325 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5326 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5327 
5328 	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
5329 }
5330 
5331 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5332 {
5333 	u32 data, wgp_bitmask;
5334 	data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
5335 	data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
5336 
5337 	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5338 	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5339 
5340 	wgp_bitmask =
5341 		amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5342 
5343 	return (~data) & wgp_bitmask;
5344 }
5345 
5346 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5347 {
5348 	u32 wgp_idx, wgp_active_bitmap;
5349 	u32 cu_bitmap_per_wgp, cu_active_bitmap;
5350 
5351 	wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5352 	cu_active_bitmap = 0;
5353 
5354 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5355 		/* if there is one WGP enabled, it means 2 CUs will be enabled */
5356 		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5357 		if (wgp_active_bitmap & (1 << wgp_idx))
5358 			cu_active_bitmap |= cu_bitmap_per_wgp;
5359 	}
5360 
5361 	return cu_active_bitmap;
5362 }
5363 
5364 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
5365 				 struct amdgpu_cu_info *cu_info)
5366 {
5367 	int i, j, k, counter, active_cu_number = 0;
5368 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5369 	unsigned disable_masks[4 * 2];
5370 
5371 	if (!adev || !cu_info)
5372 		return -EINVAL;
5373 
5374 	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5375 
5376 	mutex_lock(&adev->grbm_idx_mutex);
5377 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5378 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5379 			mask = 1;
5380 			ao_bitmap = 0;
5381 			counter = 0;
5382 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5383 			if (i < 4 && j < 2)
5384 				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
5385 					adev, disable_masks[i * 2 + j]);
5386 			bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
5387 			cu_info->bitmap[i][j] = bitmap;
5388 
5389 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5390 				if (bitmap & mask) {
5391 					if (counter < adev->gfx.config.max_cu_per_sh)
5392 						ao_bitmap |= mask;
5393 					counter++;
5394 				}
5395 				mask <<= 1;
5396 			}
5397 			active_cu_number += counter;
5398 			if (i < 2 && j < 2)
5399 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5400 			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5401 		}
5402 	}
5403 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5404 	mutex_unlock(&adev->grbm_idx_mutex);
5405 
5406 	cu_info->number = active_cu_number;
5407 	cu_info->ao_cu_mask = ao_cu_mask;
5408 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5409 
5410 	return 0;
5411 }
5412 
5413 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
5414 {
5415 	.type = AMD_IP_BLOCK_TYPE_GFX,
5416 	.major = 10,
5417 	.minor = 0,
5418 	.rev = 0,
5419 	.funcs = &gfx_v10_0_ip_funcs,
5420 };
5421