1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define RLCG_VFGATE_DISABLED 0x4000000 60 #define RLCG_WRONG_OPERATION_TYPE 0x2000000 61 #define RLCG_NOT_IN_RANGE 0x1000000 62 63 #define F32_CE_PROGRAM_RAM_SIZE 65536 64 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 65 66 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 67 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 68 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 69 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 70 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 71 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 72 73 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 74 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 75 76 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 77 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 78 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 79 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 80 81 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 82 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 83 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 84 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 85 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 86 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 87 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 88 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 90 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 92 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 94 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 96 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 97 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 98 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 99 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 100 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 101 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 102 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 103 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 104 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 105 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 106 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 107 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 108 109 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 111 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 113 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 114 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 115 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 116 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 117 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 118 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 119 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 120 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 121 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 122 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 124 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 125 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 126 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 127 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 128 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 129 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 130 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 131 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 132 133 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 134 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 135 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 136 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 137 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 138 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 139 #define mmCP_HYP_CE_UCODE_DATA 0x5819 140 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 141 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 142 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 143 #define mmCP_HYP_ME_UCODE_DATA 0x5817 144 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 145 146 #define mmCPG_PSP_DEBUG 0x5c10 147 #define mmCPG_PSP_DEBUG_BASE_IDX 1 148 #define mmCPC_PSP_DEBUG 0x5c11 149 #define mmCPC_PSP_DEBUG_BASE_IDX 1 150 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 151 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 152 153 //CC_GC_SA_UNIT_DISABLE 154 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 155 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 156 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 157 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 158 //GC_USER_SA_UNIT_DISABLE 159 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 160 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 161 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 162 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 163 //PA_SC_ENHANCE_3 164 #define mmPA_SC_ENHANCE_3 0x1085 165 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 166 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 167 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 168 169 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 170 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 171 172 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 173 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 174 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 175 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 176 177 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 178 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 179 180 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 181 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 182 183 #define GFX_RLCG_GC_WRITE_OLD (0x8 << 28) 184 #define GFX_RLCG_GC_WRITE (0x0 << 28) 185 #define GFX_RLCG_GC_READ (0x1 << 28) 186 #define GFX_RLCG_MMHUB_WRITE (0x2 << 28) 187 188 #define RLCG_ERROR_REPORT_ENABLED(adev) \ 189 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 190 191 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 192 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 193 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 194 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 195 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 196 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 197 198 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 203 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 204 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 205 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 206 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 207 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 208 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 209 210 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 211 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 212 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 213 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 214 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 215 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 216 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 222 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 223 224 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 225 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 226 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 228 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 229 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 230 231 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 232 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 233 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 234 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 235 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 236 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 237 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 243 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 244 245 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 246 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 247 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 249 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 250 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 251 252 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 253 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 254 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 256 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 257 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 258 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish_ce.bin"); 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish_pfp.bin"); 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish_me.bin"); 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish_mec.bin"); 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish_mec2.bin"); 264 MODULE_FIRMWARE("amdgpu/cyan_skillfish_rlc.bin"); 265 266 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 267 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 268 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 269 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 270 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 271 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 272 273 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 274 { 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 315 }; 316 317 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 318 { 319 /* Pending on emulation bring up */ 320 }; 321 322 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 323 { 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1376 }; 1377 1378 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1379 { 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1418 }; 1419 1420 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1421 { 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1464 }; 1465 1466 static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip, 1467 int write, u32 *rlcg_flag) 1468 { 1469 switch (hwip) { 1470 case GC_HWIP: 1471 if (amdgpu_sriov_reg_indirect_gc(adev)) { 1472 *rlcg_flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ; 1473 1474 return true; 1475 /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */ 1476 } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ)) { 1477 *rlcg_flag = GFX_RLCG_GC_WRITE_OLD; 1478 1479 return true; 1480 } 1481 1482 break; 1483 case MMHUB_HWIP: 1484 if (amdgpu_sriov_reg_indirect_mmhub(adev) && 1485 (acc_flags & AMDGPU_REGS_RLC) && write) { 1486 *rlcg_flag = GFX_RLCG_MMHUB_WRITE; 1487 return true; 1488 } 1489 1490 break; 1491 default: 1492 DRM_DEBUG("Not program register by RLCG\n"); 1493 } 1494 1495 return false; 1496 } 1497 1498 static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag) 1499 { 1500 static void *scratch_reg0; 1501 static void *scratch_reg1; 1502 static void *scratch_reg2; 1503 static void *scratch_reg3; 1504 static void *spare_int; 1505 static uint32_t grbm_cntl; 1506 static uint32_t grbm_idx; 1507 uint32_t i = 0; 1508 uint32_t retries = 50000; 1509 u32 ret = 0; 1510 u32 tmp; 1511 1512 scratch_reg0 = adev->rmmio + 1513 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4; 1514 scratch_reg1 = adev->rmmio + 1515 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4; 1516 scratch_reg2 = adev->rmmio + 1517 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4; 1518 scratch_reg3 = adev->rmmio + 1519 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4; 1520 1521 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 1522 spare_int = adev->rmmio + 1523 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX] 1524 + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4; 1525 } else { 1526 spare_int = adev->rmmio + 1527 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4; 1528 } 1529 1530 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 1531 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; 1532 1533 if (offset == grbm_cntl || offset == grbm_idx) { 1534 if (offset == grbm_cntl) 1535 writel(v, scratch_reg2); 1536 else if (offset == grbm_idx) 1537 writel(v, scratch_reg3); 1538 1539 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 1540 } else { 1541 writel(v, scratch_reg0); 1542 writel(offset | flag, scratch_reg1); 1543 writel(1, spare_int); 1544 1545 for (i = 0; i < retries; i++) { 1546 tmp = readl(scratch_reg1); 1547 if (!(tmp & flag)) 1548 break; 1549 1550 udelay(10); 1551 } 1552 1553 if (i >= retries) { 1554 if (RLCG_ERROR_REPORT_ENABLED(adev)) { 1555 if (tmp & RLCG_VFGATE_DISABLED) 1556 pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset); 1557 else if (tmp & RLCG_WRONG_OPERATION_TYPE) 1558 pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset); 1559 else if (tmp & RLCG_NOT_IN_RANGE) 1560 pr_err("The register is not in range, program reg:0x%05x failed!\n", offset); 1561 else 1562 pr_err("Unknown error type, program reg:0x%05x failed!\n", offset); 1563 } else 1564 pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset); 1565 } 1566 } 1567 1568 ret = readl(scratch_reg0); 1569 1570 return ret; 1571 } 1572 1573 static void gfx_v10_sriov_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip) 1574 { 1575 u32 rlcg_flag; 1576 1577 if (!amdgpu_sriov_runtime(adev) && 1578 gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) { 1579 gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag); 1580 return; 1581 } 1582 1583 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1584 WREG32_NO_KIQ(offset, value); 1585 else 1586 WREG32(offset, value); 1587 } 1588 1589 static u32 gfx_v10_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip) 1590 { 1591 u32 rlcg_flag; 1592 1593 if (!amdgpu_sriov_runtime(adev) && 1594 gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag)) 1595 return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag); 1596 1597 if (acc_flags & AMDGPU_REGS_NO_KIQ) 1598 return RREG32_NO_KIQ(offset); 1599 else 1600 return RREG32(offset); 1601 } 1602 1603 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1604 { 1605 /* Pending on emulation bring up */ 1606 }; 1607 1608 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1609 { 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2230 }; 2231 2232 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2233 { 2234 /* Pending on emulation bring up */ 2235 }; 2236 2237 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2238 { 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3291 }; 3292 3293 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3294 { 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3338 }; 3339 3340 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3341 { 3342 /* Pending on emulation bring up */ 3343 }; 3344 3345 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3346 { 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3388 3389 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3391 }; 3392 3393 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3394 { 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3419 3420 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3422 }; 3423 3424 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = 3425 { 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3446 }; 3447 3448 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3449 { 3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3486 }; 3487 3488 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000), 3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3521 }; 3522 3523 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3558 }; 3559 3560 #define DEFAULT_SH_MEM_CONFIG \ 3561 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3562 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3563 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3564 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3565 3566 /* TODO: pending on golden setting value of gb address config */ 3567 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3568 3569 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3570 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3571 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3572 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3573 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3574 struct amdgpu_cu_info *cu_info); 3575 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3576 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3577 u32 sh_num, u32 instance); 3578 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3579 3580 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3581 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3582 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3583 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3584 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3585 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3586 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3587 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3588 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3589 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3590 3591 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3592 { 3593 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3594 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3595 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3596 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3597 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3598 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3599 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3600 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3601 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3602 } 3603 3604 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3605 struct amdgpu_ring *ring) 3606 { 3607 struct amdgpu_device *adev = kiq_ring->adev; 3608 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3609 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3610 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3611 3612 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3613 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3614 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3615 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3616 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3617 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3618 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3619 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3620 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3621 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3622 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3623 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3624 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3625 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3626 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3627 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3628 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3629 } 3630 3631 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3632 struct amdgpu_ring *ring, 3633 enum amdgpu_unmap_queues_action action, 3634 u64 gpu_addr, u64 seq) 3635 { 3636 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3637 3638 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3639 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3640 PACKET3_UNMAP_QUEUES_ACTION(action) | 3641 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3642 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3643 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3644 amdgpu_ring_write(kiq_ring, 3645 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3646 3647 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3648 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3649 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3650 amdgpu_ring_write(kiq_ring, seq); 3651 } else { 3652 amdgpu_ring_write(kiq_ring, 0); 3653 amdgpu_ring_write(kiq_ring, 0); 3654 amdgpu_ring_write(kiq_ring, 0); 3655 } 3656 } 3657 3658 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3659 struct amdgpu_ring *ring, 3660 u64 addr, 3661 u64 seq) 3662 { 3663 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3664 3665 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3666 amdgpu_ring_write(kiq_ring, 3667 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3668 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3669 PACKET3_QUERY_STATUS_COMMAND(2)); 3670 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3671 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3672 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3673 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3674 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3675 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3676 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3677 } 3678 3679 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3680 uint16_t pasid, uint32_t flush_type, 3681 bool all_hub) 3682 { 3683 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3684 amdgpu_ring_write(kiq_ring, 3685 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3686 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3687 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3688 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3689 } 3690 3691 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3692 .kiq_set_resources = gfx10_kiq_set_resources, 3693 .kiq_map_queues = gfx10_kiq_map_queues, 3694 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3695 .kiq_query_status = gfx10_kiq_query_status, 3696 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3697 .set_resources_size = 8, 3698 .map_queues_size = 7, 3699 .unmap_queues_size = 6, 3700 .query_status_size = 7, 3701 .invalidate_tlbs_size = 2, 3702 }; 3703 3704 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3705 { 3706 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3707 } 3708 3709 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3710 { 3711 switch (adev->ip_versions[GC_HWIP][0]) { 3712 case IP_VERSION(10, 1, 10): 3713 soc15_program_register_sequence(adev, 3714 golden_settings_gc_rlc_spm_10_0_nv10, 3715 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3716 break; 3717 case IP_VERSION(10, 1, 1): 3718 soc15_program_register_sequence(adev, 3719 golden_settings_gc_rlc_spm_10_1_nv14, 3720 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3721 break; 3722 case IP_VERSION(10, 1, 2): 3723 soc15_program_register_sequence(adev, 3724 golden_settings_gc_rlc_spm_10_1_2_nv12, 3725 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3726 break; 3727 default: 3728 break; 3729 } 3730 } 3731 3732 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3733 { 3734 switch (adev->ip_versions[GC_HWIP][0]) { 3735 case IP_VERSION(10, 1, 10): 3736 soc15_program_register_sequence(adev, 3737 golden_settings_gc_10_1, 3738 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3739 soc15_program_register_sequence(adev, 3740 golden_settings_gc_10_0_nv10, 3741 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3742 break; 3743 case IP_VERSION(10, 1, 1): 3744 soc15_program_register_sequence(adev, 3745 golden_settings_gc_10_1_1, 3746 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3747 soc15_program_register_sequence(adev, 3748 golden_settings_gc_10_1_nv14, 3749 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3750 break; 3751 case IP_VERSION(10, 1, 2): 3752 soc15_program_register_sequence(adev, 3753 golden_settings_gc_10_1_2, 3754 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3755 soc15_program_register_sequence(adev, 3756 golden_settings_gc_10_1_2_nv12, 3757 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3758 break; 3759 case IP_VERSION(10, 3, 0): 3760 soc15_program_register_sequence(adev, 3761 golden_settings_gc_10_3, 3762 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3763 soc15_program_register_sequence(adev, 3764 golden_settings_gc_10_3_sienna_cichlid, 3765 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3766 break; 3767 case IP_VERSION(10, 3, 2): 3768 soc15_program_register_sequence(adev, 3769 golden_settings_gc_10_3_2, 3770 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3771 break; 3772 case IP_VERSION(10, 3, 1): 3773 soc15_program_register_sequence(adev, 3774 golden_settings_gc_10_3_vangogh, 3775 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3776 break; 3777 case IP_VERSION(10, 3, 3): 3778 soc15_program_register_sequence(adev, 3779 golden_settings_gc_10_3_3, 3780 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3781 break; 3782 case IP_VERSION(10, 3, 4): 3783 soc15_program_register_sequence(adev, 3784 golden_settings_gc_10_3_4, 3785 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3786 break; 3787 case IP_VERSION(10, 3, 5): 3788 soc15_program_register_sequence(adev, 3789 golden_settings_gc_10_3_5, 3790 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3791 break; 3792 case IP_VERSION(10, 1, 3): 3793 soc15_program_register_sequence(adev, 3794 golden_settings_gc_10_0_cyan_skillfish, 3795 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3796 break; 3797 default: 3798 break; 3799 } 3800 gfx_v10_0_init_spm_golden_registers(adev); 3801 } 3802 3803 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3804 { 3805 adev->gfx.scratch.num_reg = 8; 3806 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3807 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3808 } 3809 3810 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3811 bool wc, uint32_t reg, uint32_t val) 3812 { 3813 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3814 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3815 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3816 amdgpu_ring_write(ring, reg); 3817 amdgpu_ring_write(ring, 0); 3818 amdgpu_ring_write(ring, val); 3819 } 3820 3821 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3822 int mem_space, int opt, uint32_t addr0, 3823 uint32_t addr1, uint32_t ref, uint32_t mask, 3824 uint32_t inv) 3825 { 3826 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3827 amdgpu_ring_write(ring, 3828 /* memory (1) or register (0) */ 3829 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3830 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3831 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3832 WAIT_REG_MEM_ENGINE(eng_sel))); 3833 3834 if (mem_space) 3835 BUG_ON(addr0 & 0x3); /* Dword align */ 3836 amdgpu_ring_write(ring, addr0); 3837 amdgpu_ring_write(ring, addr1); 3838 amdgpu_ring_write(ring, ref); 3839 amdgpu_ring_write(ring, mask); 3840 amdgpu_ring_write(ring, inv); /* poll interval */ 3841 } 3842 3843 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3844 { 3845 struct amdgpu_device *adev = ring->adev; 3846 uint32_t scratch; 3847 uint32_t tmp = 0; 3848 unsigned i; 3849 int r; 3850 3851 r = amdgpu_gfx_scratch_get(adev, &scratch); 3852 if (r) { 3853 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3854 return r; 3855 } 3856 3857 WREG32(scratch, 0xCAFEDEAD); 3858 3859 r = amdgpu_ring_alloc(ring, 3); 3860 if (r) { 3861 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3862 ring->idx, r); 3863 amdgpu_gfx_scratch_free(adev, scratch); 3864 return r; 3865 } 3866 3867 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3868 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3869 amdgpu_ring_write(ring, 0xDEADBEEF); 3870 amdgpu_ring_commit(ring); 3871 3872 for (i = 0; i < adev->usec_timeout; i++) { 3873 tmp = RREG32(scratch); 3874 if (tmp == 0xDEADBEEF) 3875 break; 3876 if (amdgpu_emu_mode == 1) 3877 msleep(1); 3878 else 3879 udelay(1); 3880 } 3881 3882 if (i >= adev->usec_timeout) 3883 r = -ETIMEDOUT; 3884 3885 amdgpu_gfx_scratch_free(adev, scratch); 3886 3887 return r; 3888 } 3889 3890 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3891 { 3892 struct amdgpu_device *adev = ring->adev; 3893 struct amdgpu_ib ib; 3894 struct dma_fence *f = NULL; 3895 unsigned index; 3896 uint64_t gpu_addr; 3897 uint32_t tmp; 3898 long r; 3899 3900 r = amdgpu_device_wb_get(adev, &index); 3901 if (r) 3902 return r; 3903 3904 gpu_addr = adev->wb.gpu_addr + (index * 4); 3905 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3906 memset(&ib, 0, sizeof(ib)); 3907 r = amdgpu_ib_get(adev, NULL, 16, 3908 AMDGPU_IB_POOL_DIRECT, &ib); 3909 if (r) 3910 goto err1; 3911 3912 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3913 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3914 ib.ptr[2] = lower_32_bits(gpu_addr); 3915 ib.ptr[3] = upper_32_bits(gpu_addr); 3916 ib.ptr[4] = 0xDEADBEEF; 3917 ib.length_dw = 5; 3918 3919 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3920 if (r) 3921 goto err2; 3922 3923 r = dma_fence_wait_timeout(f, false, timeout); 3924 if (r == 0) { 3925 r = -ETIMEDOUT; 3926 goto err2; 3927 } else if (r < 0) { 3928 goto err2; 3929 } 3930 3931 tmp = adev->wb.wb[index]; 3932 if (tmp == 0xDEADBEEF) 3933 r = 0; 3934 else 3935 r = -EINVAL; 3936 err2: 3937 amdgpu_ib_free(adev, &ib, NULL); 3938 dma_fence_put(f); 3939 err1: 3940 amdgpu_device_wb_free(adev, index); 3941 return r; 3942 } 3943 3944 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3945 { 3946 release_firmware(adev->gfx.pfp_fw); 3947 adev->gfx.pfp_fw = NULL; 3948 release_firmware(adev->gfx.me_fw); 3949 adev->gfx.me_fw = NULL; 3950 release_firmware(adev->gfx.ce_fw); 3951 adev->gfx.ce_fw = NULL; 3952 release_firmware(adev->gfx.rlc_fw); 3953 adev->gfx.rlc_fw = NULL; 3954 release_firmware(adev->gfx.mec_fw); 3955 adev->gfx.mec_fw = NULL; 3956 release_firmware(adev->gfx.mec2_fw); 3957 adev->gfx.mec2_fw = NULL; 3958 3959 kfree(adev->gfx.rlc.register_list_format); 3960 } 3961 3962 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3963 { 3964 adev->gfx.cp_fw_write_wait = false; 3965 3966 switch (adev->ip_versions[GC_HWIP][0]) { 3967 case IP_VERSION(10, 1, 10): 3968 case IP_VERSION(10, 1, 2): 3969 case IP_VERSION(10, 1, 1): 3970 case IP_VERSION(10, 1, 3): 3971 if ((adev->gfx.me_fw_version >= 0x00000046) && 3972 (adev->gfx.me_feature_version >= 27) && 3973 (adev->gfx.pfp_fw_version >= 0x00000068) && 3974 (adev->gfx.pfp_feature_version >= 27) && 3975 (adev->gfx.mec_fw_version >= 0x0000005b) && 3976 (adev->gfx.mec_feature_version >= 27)) 3977 adev->gfx.cp_fw_write_wait = true; 3978 break; 3979 case IP_VERSION(10, 3, 0): 3980 case IP_VERSION(10, 3, 2): 3981 case IP_VERSION(10, 3, 1): 3982 case IP_VERSION(10, 3, 4): 3983 case IP_VERSION(10, 3, 5): 3984 case IP_VERSION(10, 3, 3): 3985 adev->gfx.cp_fw_write_wait = true; 3986 break; 3987 default: 3988 break; 3989 } 3990 3991 if (!adev->gfx.cp_fw_write_wait) 3992 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3993 } 3994 3995 3996 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3997 { 3998 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3999 4000 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 4001 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 4002 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 4003 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 4004 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 4005 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 4006 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 4007 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 4008 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 4009 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 4010 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 4011 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 4012 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 4013 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 4014 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 4015 } 4016 4017 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 4018 { 4019 const struct rlc_firmware_header_v2_2 *rlc_hdr; 4020 4021 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 4022 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 4023 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 4024 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 4025 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 4026 } 4027 4028 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 4029 { 4030 bool ret = false; 4031 4032 switch (adev->pdev->revision) { 4033 case 0xc2: 4034 case 0xc3: 4035 ret = true; 4036 break; 4037 default: 4038 ret = false; 4039 break; 4040 } 4041 4042 return ret ; 4043 } 4044 4045 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 4046 { 4047 switch (adev->ip_versions[GC_HWIP][0]) { 4048 case IP_VERSION(10, 1, 10): 4049 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 4050 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 4051 break; 4052 default: 4053 break; 4054 } 4055 } 4056 4057 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 4058 { 4059 const char *chip_name; 4060 char fw_name[40]; 4061 char *wks = ""; 4062 int err; 4063 struct amdgpu_firmware_info *info = NULL; 4064 const struct common_firmware_header *header = NULL; 4065 const struct gfx_firmware_header_v1_0 *cp_hdr; 4066 const struct rlc_firmware_header_v2_0 *rlc_hdr; 4067 unsigned int *tmp = NULL; 4068 unsigned int i = 0; 4069 uint16_t version_major; 4070 uint16_t version_minor; 4071 4072 DRM_DEBUG("\n"); 4073 4074 switch (adev->ip_versions[GC_HWIP][0]) { 4075 case IP_VERSION(10, 1, 10): 4076 chip_name = "navi10"; 4077 break; 4078 case IP_VERSION(10, 1, 1): 4079 chip_name = "navi14"; 4080 if (!(adev->pdev->device == 0x7340 && 4081 adev->pdev->revision != 0x00)) 4082 wks = "_wks"; 4083 break; 4084 case IP_VERSION(10, 1, 2): 4085 chip_name = "navi12"; 4086 break; 4087 case IP_VERSION(10, 3, 0): 4088 chip_name = "sienna_cichlid"; 4089 break; 4090 case IP_VERSION(10, 3, 2): 4091 chip_name = "navy_flounder"; 4092 break; 4093 case IP_VERSION(10, 3, 1): 4094 chip_name = "vangogh"; 4095 break; 4096 case IP_VERSION(10, 3, 4): 4097 chip_name = "dimgrey_cavefish"; 4098 break; 4099 case IP_VERSION(10, 3, 5): 4100 chip_name = "beige_goby"; 4101 break; 4102 case IP_VERSION(10, 3, 3): 4103 chip_name = "yellow_carp"; 4104 break; 4105 case IP_VERSION(10, 1, 3): 4106 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 4107 chip_name = "cyan_skillfish2"; 4108 else 4109 chip_name = "cyan_skillfish"; 4110 break; 4111 default: 4112 BUG(); 4113 } 4114 4115 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 4116 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 4117 if (err) 4118 goto out; 4119 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 4120 if (err) 4121 goto out; 4122 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 4123 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4124 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4125 4126 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 4127 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 4128 if (err) 4129 goto out; 4130 err = amdgpu_ucode_validate(adev->gfx.me_fw); 4131 if (err) 4132 goto out; 4133 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 4134 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4135 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4136 4137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 4138 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 4139 if (err) 4140 goto out; 4141 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 4142 if (err) 4143 goto out; 4144 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 4145 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4146 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4147 4148 if (!amdgpu_sriov_vf(adev)) { 4149 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 4150 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4151 if (err) 4152 goto out; 4153 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 4154 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4155 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4156 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4157 4158 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 4159 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 4160 adev->gfx.rlc.save_and_restore_offset = 4161 le32_to_cpu(rlc_hdr->save_and_restore_offset); 4162 adev->gfx.rlc.clear_state_descriptor_offset = 4163 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 4164 adev->gfx.rlc.avail_scratch_ram_locations = 4165 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 4166 adev->gfx.rlc.reg_restore_list_size = 4167 le32_to_cpu(rlc_hdr->reg_restore_list_size); 4168 adev->gfx.rlc.reg_list_format_start = 4169 le32_to_cpu(rlc_hdr->reg_list_format_start); 4170 adev->gfx.rlc.reg_list_format_separate_start = 4171 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 4172 adev->gfx.rlc.starting_offsets_start = 4173 le32_to_cpu(rlc_hdr->starting_offsets_start); 4174 adev->gfx.rlc.reg_list_format_size_bytes = 4175 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 4176 adev->gfx.rlc.reg_list_size_bytes = 4177 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 4178 adev->gfx.rlc.register_list_format = 4179 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 4180 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 4181 if (!adev->gfx.rlc.register_list_format) { 4182 err = -ENOMEM; 4183 goto out; 4184 } 4185 4186 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 4187 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 4188 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 4189 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 4190 4191 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 4192 4193 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 4194 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 4195 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 4196 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 4197 4198 if (version_major == 2) { 4199 if (version_minor >= 1) 4200 gfx_v10_0_init_rlc_ext_microcode(adev); 4201 if (version_minor == 2) 4202 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 4203 } 4204 } 4205 4206 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 4207 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 4208 if (err) 4209 goto out; 4210 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 4211 if (err) 4212 goto out; 4213 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4214 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 4215 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 4216 4217 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 4218 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 4219 if (!err) { 4220 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 4221 if (err) 4222 goto out; 4223 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 4224 adev->gfx.mec2_fw->data; 4225 adev->gfx.mec2_fw_version = 4226 le32_to_cpu(cp_hdr->header.ucode_version); 4227 adev->gfx.mec2_feature_version = 4228 le32_to_cpu(cp_hdr->ucode_feature_version); 4229 } else { 4230 err = 0; 4231 adev->gfx.mec2_fw = NULL; 4232 } 4233 4234 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 4235 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 4236 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 4237 info->fw = adev->gfx.pfp_fw; 4238 header = (const struct common_firmware_header *)info->fw->data; 4239 adev->firmware.fw_size += 4240 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4241 4242 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 4243 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 4244 info->fw = adev->gfx.me_fw; 4245 header = (const struct common_firmware_header *)info->fw->data; 4246 adev->firmware.fw_size += 4247 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4248 4249 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 4250 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 4251 info->fw = adev->gfx.ce_fw; 4252 header = (const struct common_firmware_header *)info->fw->data; 4253 adev->firmware.fw_size += 4254 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4255 4256 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 4257 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 4258 info->fw = adev->gfx.rlc_fw; 4259 if (info->fw) { 4260 header = (const struct common_firmware_header *)info->fw->data; 4261 adev->firmware.fw_size += 4262 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 4263 } 4264 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 4265 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 4266 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 4267 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 4268 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 4269 info->fw = adev->gfx.rlc_fw; 4270 adev->firmware.fw_size += 4271 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 4272 4273 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 4274 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 4275 info->fw = adev->gfx.rlc_fw; 4276 adev->firmware.fw_size += 4277 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 4278 4279 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 4280 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 4281 info->fw = adev->gfx.rlc_fw; 4282 adev->firmware.fw_size += 4283 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 4284 4285 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 4286 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 4287 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 4288 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 4289 info->fw = adev->gfx.rlc_fw; 4290 adev->firmware.fw_size += 4291 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4292 4293 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4294 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4295 info->fw = adev->gfx.rlc_fw; 4296 adev->firmware.fw_size += 4297 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4298 } 4299 } 4300 4301 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4302 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4303 info->fw = adev->gfx.mec_fw; 4304 header = (const struct common_firmware_header *)info->fw->data; 4305 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4306 adev->firmware.fw_size += 4307 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4308 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4309 4310 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4311 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4312 info->fw = adev->gfx.mec_fw; 4313 adev->firmware.fw_size += 4314 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4315 4316 if (adev->gfx.mec2_fw) { 4317 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4318 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4319 info->fw = adev->gfx.mec2_fw; 4320 header = (const struct common_firmware_header *)info->fw->data; 4321 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4322 adev->firmware.fw_size += 4323 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4324 le32_to_cpu(cp_hdr->jt_size) * 4, 4325 PAGE_SIZE); 4326 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4327 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4328 info->fw = adev->gfx.mec2_fw; 4329 adev->firmware.fw_size += 4330 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4331 PAGE_SIZE); 4332 } 4333 } 4334 4335 gfx_v10_0_check_fw_write_wait(adev); 4336 out: 4337 if (err) { 4338 dev_err(adev->dev, 4339 "gfx10: Failed to load firmware \"%s\"\n", 4340 fw_name); 4341 release_firmware(adev->gfx.pfp_fw); 4342 adev->gfx.pfp_fw = NULL; 4343 release_firmware(adev->gfx.me_fw); 4344 adev->gfx.me_fw = NULL; 4345 release_firmware(adev->gfx.ce_fw); 4346 adev->gfx.ce_fw = NULL; 4347 release_firmware(adev->gfx.rlc_fw); 4348 adev->gfx.rlc_fw = NULL; 4349 release_firmware(adev->gfx.mec_fw); 4350 adev->gfx.mec_fw = NULL; 4351 release_firmware(adev->gfx.mec2_fw); 4352 adev->gfx.mec2_fw = NULL; 4353 } 4354 4355 gfx_v10_0_check_gfxoff_flag(adev); 4356 4357 return err; 4358 } 4359 4360 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4361 { 4362 u32 count = 0; 4363 const struct cs_section_def *sect = NULL; 4364 const struct cs_extent_def *ext = NULL; 4365 4366 /* begin clear state */ 4367 count += 2; 4368 /* context control state */ 4369 count += 3; 4370 4371 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4372 for (ext = sect->section; ext->extent != NULL; ++ext) { 4373 if (sect->id == SECT_CONTEXT) 4374 count += 2 + ext->reg_count; 4375 else 4376 return 0; 4377 } 4378 } 4379 4380 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4381 count += 3; 4382 /* end clear state */ 4383 count += 2; 4384 /* clear state */ 4385 count += 2; 4386 4387 return count; 4388 } 4389 4390 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4391 volatile u32 *buffer) 4392 { 4393 u32 count = 0, i; 4394 const struct cs_section_def *sect = NULL; 4395 const struct cs_extent_def *ext = NULL; 4396 int ctx_reg_offset; 4397 4398 if (adev->gfx.rlc.cs_data == NULL) 4399 return; 4400 if (buffer == NULL) 4401 return; 4402 4403 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4404 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4405 4406 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4407 buffer[count++] = cpu_to_le32(0x80000000); 4408 buffer[count++] = cpu_to_le32(0x80000000); 4409 4410 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4411 for (ext = sect->section; ext->extent != NULL; ++ext) { 4412 if (sect->id == SECT_CONTEXT) { 4413 buffer[count++] = 4414 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4415 buffer[count++] = cpu_to_le32(ext->reg_index - 4416 PACKET3_SET_CONTEXT_REG_START); 4417 for (i = 0; i < ext->reg_count; i++) 4418 buffer[count++] = cpu_to_le32(ext->extent[i]); 4419 } else { 4420 return; 4421 } 4422 } 4423 } 4424 4425 ctx_reg_offset = 4426 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4427 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4428 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4429 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4430 4431 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4432 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4433 4434 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4435 buffer[count++] = cpu_to_le32(0); 4436 } 4437 4438 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4439 { 4440 /* clear state block */ 4441 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4442 &adev->gfx.rlc.clear_state_gpu_addr, 4443 (void **)&adev->gfx.rlc.cs_ptr); 4444 4445 /* jump table block */ 4446 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4447 &adev->gfx.rlc.cp_table_gpu_addr, 4448 (void **)&adev->gfx.rlc.cp_table_ptr); 4449 } 4450 4451 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4452 { 4453 const struct cs_section_def *cs_data; 4454 int r; 4455 4456 adev->gfx.rlc.cs_data = gfx10_cs_data; 4457 4458 cs_data = adev->gfx.rlc.cs_data; 4459 4460 if (cs_data) { 4461 /* init clear state block */ 4462 r = amdgpu_gfx_rlc_init_csb(adev); 4463 if (r) 4464 return r; 4465 } 4466 4467 /* init spm vmid with 0xf */ 4468 if (adev->gfx.rlc.funcs->update_spm_vmid) 4469 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4470 4471 return 0; 4472 } 4473 4474 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4475 { 4476 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4477 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4478 } 4479 4480 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4481 { 4482 int r; 4483 4484 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4485 4486 amdgpu_gfx_graphics_queue_acquire(adev); 4487 4488 r = gfx_v10_0_init_microcode(adev); 4489 if (r) 4490 DRM_ERROR("Failed to load gfx firmware!\n"); 4491 4492 return r; 4493 } 4494 4495 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4496 { 4497 int r; 4498 u32 *hpd; 4499 const __le32 *fw_data = NULL; 4500 unsigned fw_size; 4501 u32 *fw = NULL; 4502 size_t mec_hpd_size; 4503 4504 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4505 4506 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4507 4508 /* take ownership of the relevant compute queues */ 4509 amdgpu_gfx_compute_queue_acquire(adev); 4510 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4511 4512 if (mec_hpd_size) { 4513 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4514 AMDGPU_GEM_DOMAIN_GTT, 4515 &adev->gfx.mec.hpd_eop_obj, 4516 &adev->gfx.mec.hpd_eop_gpu_addr, 4517 (void **)&hpd); 4518 if (r) { 4519 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4520 gfx_v10_0_mec_fini(adev); 4521 return r; 4522 } 4523 4524 memset(hpd, 0, mec_hpd_size); 4525 4526 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4527 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4528 } 4529 4530 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4531 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4532 4533 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4534 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4535 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4536 4537 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4538 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4539 &adev->gfx.mec.mec_fw_obj, 4540 &adev->gfx.mec.mec_fw_gpu_addr, 4541 (void **)&fw); 4542 if (r) { 4543 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4544 gfx_v10_0_mec_fini(adev); 4545 return r; 4546 } 4547 4548 memcpy(fw, fw_data, fw_size); 4549 4550 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4551 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4552 } 4553 4554 return 0; 4555 } 4556 4557 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4558 { 4559 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4560 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4561 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4562 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4563 } 4564 4565 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4566 uint32_t thread, uint32_t regno, 4567 uint32_t num, uint32_t *out) 4568 { 4569 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4570 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4571 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4572 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4573 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4574 while (num--) 4575 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4576 } 4577 4578 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4579 { 4580 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4581 * field when performing a select_se_sh so it should be 4582 * zero here */ 4583 WARN_ON(simd != 0); 4584 4585 /* type 2 wave data */ 4586 dst[(*no_fields)++] = 2; 4587 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4588 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4589 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4590 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4591 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4592 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4593 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4594 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4595 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4596 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4597 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4598 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4599 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4600 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4601 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4602 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4603 } 4604 4605 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4606 uint32_t wave, uint32_t start, 4607 uint32_t size, uint32_t *dst) 4608 { 4609 WARN_ON(simd != 0); 4610 4611 wave_read_regs( 4612 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4613 dst); 4614 } 4615 4616 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4617 uint32_t wave, uint32_t thread, 4618 uint32_t start, uint32_t size, 4619 uint32_t *dst) 4620 { 4621 wave_read_regs( 4622 adev, wave, thread, 4623 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4624 } 4625 4626 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4627 u32 me, u32 pipe, u32 q, u32 vm) 4628 { 4629 nv_grbm_select(adev, me, pipe, q, vm); 4630 } 4631 4632 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4633 bool enable) 4634 { 4635 uint32_t data, def; 4636 4637 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4638 4639 if (enable) 4640 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4641 else 4642 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4643 4644 if (data != def) 4645 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4646 } 4647 4648 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4649 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4650 .select_se_sh = &gfx_v10_0_select_se_sh, 4651 .read_wave_data = &gfx_v10_0_read_wave_data, 4652 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4653 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4654 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4655 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4656 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4657 }; 4658 4659 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4660 { 4661 u32 gb_addr_config; 4662 4663 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4664 4665 switch (adev->ip_versions[GC_HWIP][0]) { 4666 case IP_VERSION(10, 1, 10): 4667 case IP_VERSION(10, 1, 1): 4668 case IP_VERSION(10, 1, 2): 4669 adev->gfx.config.max_hw_contexts = 8; 4670 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4671 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4672 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4673 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4674 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4675 break; 4676 case IP_VERSION(10, 3, 0): 4677 case IP_VERSION(10, 3, 2): 4678 case IP_VERSION(10, 3, 1): 4679 case IP_VERSION(10, 3, 4): 4680 case IP_VERSION(10, 3, 5): 4681 case IP_VERSION(10, 3, 3): 4682 adev->gfx.config.max_hw_contexts = 8; 4683 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4684 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4685 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4686 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4687 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4688 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4689 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4690 break; 4691 case IP_VERSION(10, 1, 3): 4692 adev->gfx.config.max_hw_contexts = 8; 4693 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4694 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4695 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4696 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4697 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4698 break; 4699 default: 4700 BUG(); 4701 break; 4702 } 4703 4704 adev->gfx.config.gb_addr_config = gb_addr_config; 4705 4706 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4707 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4708 GB_ADDR_CONFIG, NUM_PIPES); 4709 4710 adev->gfx.config.max_tile_pipes = 4711 adev->gfx.config.gb_addr_config_fields.num_pipes; 4712 4713 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4714 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4715 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4716 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4717 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4718 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4719 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4720 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4721 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4722 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4723 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4724 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4725 } 4726 4727 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4728 int me, int pipe, int queue) 4729 { 4730 int r; 4731 struct amdgpu_ring *ring; 4732 unsigned int irq_type; 4733 4734 ring = &adev->gfx.gfx_ring[ring_id]; 4735 4736 ring->me = me; 4737 ring->pipe = pipe; 4738 ring->queue = queue; 4739 4740 ring->ring_obj = NULL; 4741 ring->use_doorbell = true; 4742 4743 if (!ring_id) 4744 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4745 else 4746 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4747 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4748 4749 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4750 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4751 AMDGPU_RING_PRIO_DEFAULT, NULL); 4752 if (r) 4753 return r; 4754 return 0; 4755 } 4756 4757 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4758 int mec, int pipe, int queue) 4759 { 4760 int r; 4761 unsigned irq_type; 4762 struct amdgpu_ring *ring; 4763 unsigned int hw_prio; 4764 4765 ring = &adev->gfx.compute_ring[ring_id]; 4766 4767 /* mec0 is me1 */ 4768 ring->me = mec + 1; 4769 ring->pipe = pipe; 4770 ring->queue = queue; 4771 4772 ring->ring_obj = NULL; 4773 ring->use_doorbell = true; 4774 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4775 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4776 + (ring_id * GFX10_MEC_HPD_SIZE); 4777 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4778 4779 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4780 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4781 + ring->pipe; 4782 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4783 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4784 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4785 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4786 hw_prio, NULL); 4787 if (r) 4788 return r; 4789 4790 return 0; 4791 } 4792 4793 static int gfx_v10_0_sw_init(void *handle) 4794 { 4795 int i, j, k, r, ring_id = 0; 4796 struct amdgpu_kiq *kiq; 4797 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4798 4799 switch (adev->ip_versions[GC_HWIP][0]) { 4800 case IP_VERSION(10, 1, 10): 4801 case IP_VERSION(10, 1, 1): 4802 case IP_VERSION(10, 1, 2): 4803 case IP_VERSION(10, 1, 3): 4804 adev->gfx.me.num_me = 1; 4805 adev->gfx.me.num_pipe_per_me = 1; 4806 adev->gfx.me.num_queue_per_pipe = 1; 4807 adev->gfx.mec.num_mec = 2; 4808 adev->gfx.mec.num_pipe_per_mec = 4; 4809 adev->gfx.mec.num_queue_per_pipe = 8; 4810 break; 4811 case IP_VERSION(10, 3, 0): 4812 case IP_VERSION(10, 3, 2): 4813 case IP_VERSION(10, 3, 1): 4814 case IP_VERSION(10, 3, 4): 4815 case IP_VERSION(10, 3, 5): 4816 case IP_VERSION(10, 3, 3): 4817 adev->gfx.me.num_me = 1; 4818 adev->gfx.me.num_pipe_per_me = 1; 4819 adev->gfx.me.num_queue_per_pipe = 1; 4820 adev->gfx.mec.num_mec = 2; 4821 adev->gfx.mec.num_pipe_per_mec = 4; 4822 adev->gfx.mec.num_queue_per_pipe = 4; 4823 break; 4824 default: 4825 adev->gfx.me.num_me = 1; 4826 adev->gfx.me.num_pipe_per_me = 1; 4827 adev->gfx.me.num_queue_per_pipe = 1; 4828 adev->gfx.mec.num_mec = 1; 4829 adev->gfx.mec.num_pipe_per_mec = 4; 4830 adev->gfx.mec.num_queue_per_pipe = 8; 4831 break; 4832 } 4833 4834 /* KIQ event */ 4835 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4836 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4837 &adev->gfx.kiq.irq); 4838 if (r) 4839 return r; 4840 4841 /* EOP Event */ 4842 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4843 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4844 &adev->gfx.eop_irq); 4845 if (r) 4846 return r; 4847 4848 /* Privileged reg */ 4849 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4850 &adev->gfx.priv_reg_irq); 4851 if (r) 4852 return r; 4853 4854 /* Privileged inst */ 4855 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4856 &adev->gfx.priv_inst_irq); 4857 if (r) 4858 return r; 4859 4860 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4861 4862 gfx_v10_0_scratch_init(adev); 4863 4864 r = gfx_v10_0_me_init(adev); 4865 if (r) 4866 return r; 4867 4868 r = gfx_v10_0_rlc_init(adev); 4869 if (r) { 4870 DRM_ERROR("Failed to init rlc BOs!\n"); 4871 return r; 4872 } 4873 4874 r = gfx_v10_0_mec_init(adev); 4875 if (r) { 4876 DRM_ERROR("Failed to init MEC BOs!\n"); 4877 return r; 4878 } 4879 4880 /* set up the gfx ring */ 4881 for (i = 0; i < adev->gfx.me.num_me; i++) { 4882 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4883 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4884 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4885 continue; 4886 4887 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4888 i, k, j); 4889 if (r) 4890 return r; 4891 ring_id++; 4892 } 4893 } 4894 } 4895 4896 ring_id = 0; 4897 /* set up the compute queues - allocate horizontally across pipes */ 4898 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4899 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4900 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4901 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4902 j)) 4903 continue; 4904 4905 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4906 i, k, j); 4907 if (r) 4908 return r; 4909 4910 ring_id++; 4911 } 4912 } 4913 } 4914 4915 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4916 if (r) { 4917 DRM_ERROR("Failed to init KIQ BOs!\n"); 4918 return r; 4919 } 4920 4921 kiq = &adev->gfx.kiq; 4922 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4923 if (r) 4924 return r; 4925 4926 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4927 if (r) 4928 return r; 4929 4930 /* allocate visible FB for rlc auto-loading fw */ 4931 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4932 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4933 if (r) 4934 return r; 4935 } 4936 4937 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4938 4939 gfx_v10_0_gpu_early_init(adev); 4940 4941 return 0; 4942 } 4943 4944 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4945 { 4946 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4947 &adev->gfx.pfp.pfp_fw_gpu_addr, 4948 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4949 } 4950 4951 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4952 { 4953 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4954 &adev->gfx.ce.ce_fw_gpu_addr, 4955 (void **)&adev->gfx.ce.ce_fw_ptr); 4956 } 4957 4958 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4959 { 4960 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4961 &adev->gfx.me.me_fw_gpu_addr, 4962 (void **)&adev->gfx.me.me_fw_ptr); 4963 } 4964 4965 static int gfx_v10_0_sw_fini(void *handle) 4966 { 4967 int i; 4968 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4969 4970 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4971 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4972 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4973 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4974 4975 amdgpu_gfx_mqd_sw_fini(adev); 4976 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4977 amdgpu_gfx_kiq_fini(adev); 4978 4979 gfx_v10_0_pfp_fini(adev); 4980 gfx_v10_0_ce_fini(adev); 4981 gfx_v10_0_me_fini(adev); 4982 gfx_v10_0_rlc_fini(adev); 4983 gfx_v10_0_mec_fini(adev); 4984 4985 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4986 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4987 4988 gfx_v10_0_free_microcode(adev); 4989 4990 return 0; 4991 } 4992 4993 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4994 u32 sh_num, u32 instance) 4995 { 4996 u32 data; 4997 4998 if (instance == 0xffffffff) 4999 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 5000 INSTANCE_BROADCAST_WRITES, 1); 5001 else 5002 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 5003 instance); 5004 5005 if (se_num == 0xffffffff) 5006 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 5007 1); 5008 else 5009 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 5010 5011 if (sh_num == 0xffffffff) 5012 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 5013 1); 5014 else 5015 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 5016 5017 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 5018 } 5019 5020 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 5021 { 5022 u32 data, mask; 5023 5024 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 5025 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 5026 5027 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 5028 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 5029 5030 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 5031 adev->gfx.config.max_sh_per_se); 5032 5033 return (~data) & mask; 5034 } 5035 5036 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 5037 { 5038 int i, j; 5039 u32 data; 5040 u32 active_rbs = 0; 5041 u32 bitmap; 5042 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 5043 adev->gfx.config.max_sh_per_se; 5044 5045 mutex_lock(&adev->grbm_idx_mutex); 5046 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5047 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5048 bitmap = i * adev->gfx.config.max_sh_per_se + j; 5049 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 5050 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) && 5051 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 5052 continue; 5053 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5054 data = gfx_v10_0_get_rb_active_bitmap(adev); 5055 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 5056 rb_bitmap_width_per_sh); 5057 } 5058 } 5059 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5060 mutex_unlock(&adev->grbm_idx_mutex); 5061 5062 adev->gfx.config.backend_enable_mask = active_rbs; 5063 adev->gfx.config.num_rbs = hweight32(active_rbs); 5064 } 5065 5066 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 5067 { 5068 uint32_t num_sc; 5069 uint32_t enabled_rb_per_sh; 5070 uint32_t active_rb_bitmap; 5071 uint32_t num_rb_per_sc; 5072 uint32_t num_packer_per_sc; 5073 uint32_t pa_sc_tile_steering_override; 5074 5075 /* for ASICs that integrates GFX v10.3 5076 * pa_sc_tile_steering_override should be set to 0 */ 5077 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 5078 return 0; 5079 5080 /* init num_sc */ 5081 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 5082 adev->gfx.config.num_sc_per_sh; 5083 /* init num_rb_per_sc */ 5084 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 5085 enabled_rb_per_sh = hweight32(active_rb_bitmap); 5086 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 5087 /* init num_packer_per_sc */ 5088 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 5089 5090 pa_sc_tile_steering_override = 0; 5091 pa_sc_tile_steering_override |= 5092 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 5093 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 5094 pa_sc_tile_steering_override |= 5095 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 5096 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 5097 pa_sc_tile_steering_override |= 5098 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 5099 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 5100 5101 return pa_sc_tile_steering_override; 5102 } 5103 5104 #define DEFAULT_SH_MEM_BASES (0x6000) 5105 5106 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 5107 { 5108 int i; 5109 uint32_t sh_mem_bases; 5110 5111 /* 5112 * Configure apertures: 5113 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 5114 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 5115 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 5116 */ 5117 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 5118 5119 mutex_lock(&adev->srbm_mutex); 5120 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5121 nv_grbm_select(adev, 0, 0, 0, i); 5122 /* CP and shaders */ 5123 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5124 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 5125 } 5126 nv_grbm_select(adev, 0, 0, 0, 0); 5127 mutex_unlock(&adev->srbm_mutex); 5128 5129 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 5130 acccess. These should be enabled by FW for target VMIDs. */ 5131 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 5132 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 5133 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 5134 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 5135 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 5136 } 5137 } 5138 5139 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 5140 { 5141 int vmid; 5142 5143 /* 5144 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 5145 * access. Compute VMIDs should be enabled by FW for target VMIDs, 5146 * the driver can enable them for graphics. VMID0 should maintain 5147 * access so that HWS firmware can save/restore entries. 5148 */ 5149 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 5150 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 5151 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 5152 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 5153 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 5154 } 5155 } 5156 5157 5158 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 5159 { 5160 int i, j, k; 5161 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 5162 u32 tmp, wgp_active_bitmap = 0; 5163 u32 gcrd_targets_disable_tcp = 0; 5164 u32 utcl_invreq_disable = 0; 5165 /* 5166 * GCRD_TARGETS_DISABLE field contains 5167 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 5168 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 5169 */ 5170 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 5171 2 * max_wgp_per_sh + /* TCP */ 5172 max_wgp_per_sh + /* SQC */ 5173 4); /* GL1C */ 5174 /* 5175 * UTCL1_UTCL0_INVREQ_DISABLE field contains 5176 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 5177 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 5178 */ 5179 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 5180 2 * max_wgp_per_sh + /* TCP */ 5181 2 * max_wgp_per_sh + /* SQC */ 5182 4 + /* RMI */ 5183 1); /* SQG */ 5184 5185 mutex_lock(&adev->grbm_idx_mutex); 5186 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5187 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5188 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5189 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5190 /* 5191 * Set corresponding TCP bits for the inactive WGPs in 5192 * GCRD_SA_TARGETS_DISABLE 5193 */ 5194 gcrd_targets_disable_tcp = 0; 5195 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 5196 utcl_invreq_disable = 0; 5197 5198 for (k = 0; k < max_wgp_per_sh; k++) { 5199 if (!(wgp_active_bitmap & (1 << k))) { 5200 gcrd_targets_disable_tcp |= 3 << (2 * k); 5201 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5202 utcl_invreq_disable |= (3 << (2 * k)) | 5203 (3 << (2 * (max_wgp_per_sh + k))); 5204 } 5205 } 5206 5207 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5208 /* only override TCP & SQC bits */ 5209 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5210 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5211 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5212 5213 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5214 /* only override TCP & SQC bits */ 5215 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5216 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5217 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5218 } 5219 } 5220 5221 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5222 mutex_unlock(&adev->grbm_idx_mutex); 5223 } 5224 5225 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5226 { 5227 /* TCCs are global (not instanced). */ 5228 uint32_t tcc_disable; 5229 5230 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 5231 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5232 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5233 } else { 5234 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5235 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5236 } 5237 5238 adev->gfx.config.tcc_disabled_mask = 5239 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5240 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5241 } 5242 5243 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5244 { 5245 u32 tmp; 5246 int i; 5247 5248 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5249 5250 gfx_v10_0_setup_rb(adev); 5251 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5252 gfx_v10_0_get_tcc_info(adev); 5253 adev->gfx.config.pa_sc_tile_steering_override = 5254 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5255 5256 /* XXX SH_MEM regs */ 5257 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5258 mutex_lock(&adev->srbm_mutex); 5259 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 5260 nv_grbm_select(adev, 0, 0, 0, i); 5261 /* CP and shaders */ 5262 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5263 if (i != 0) { 5264 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5265 (adev->gmc.private_aperture_start >> 48)); 5266 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5267 (adev->gmc.shared_aperture_start >> 48)); 5268 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5269 } 5270 } 5271 nv_grbm_select(adev, 0, 0, 0, 0); 5272 5273 mutex_unlock(&adev->srbm_mutex); 5274 5275 gfx_v10_0_init_compute_vmid(adev); 5276 gfx_v10_0_init_gds_vmid(adev); 5277 5278 } 5279 5280 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5281 bool enable) 5282 { 5283 u32 tmp; 5284 5285 if (amdgpu_sriov_vf(adev)) 5286 return; 5287 5288 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5289 5290 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5291 enable ? 1 : 0); 5292 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5293 enable ? 1 : 0); 5294 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5295 enable ? 1 : 0); 5296 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5297 enable ? 1 : 0); 5298 5299 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5300 } 5301 5302 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5303 { 5304 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5305 5306 /* csib */ 5307 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5308 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5309 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5310 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5311 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5312 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5313 } else { 5314 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5315 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5316 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5317 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5318 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5319 } 5320 return 0; 5321 } 5322 5323 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5324 { 5325 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5326 5327 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5328 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5329 } 5330 5331 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5332 { 5333 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5334 udelay(50); 5335 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5336 udelay(50); 5337 } 5338 5339 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5340 bool enable) 5341 { 5342 uint32_t rlc_pg_cntl; 5343 5344 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5345 5346 if (!enable) { 5347 /* RLC_PG_CNTL[23] = 0 (default) 5348 * RLC will wait for handshake acks with SMU 5349 * GFXOFF will be enabled 5350 * RLC_PG_CNTL[23] = 1 5351 * RLC will not issue any message to SMU 5352 * hence no handshake between SMU & RLC 5353 * GFXOFF will be disabled 5354 */ 5355 rlc_pg_cntl |= 0x800000; 5356 } else 5357 rlc_pg_cntl &= ~0x800000; 5358 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5359 } 5360 5361 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5362 { 5363 /* TODO: enable rlc & smu handshake until smu 5364 * and gfxoff feature works as expected */ 5365 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5366 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5367 5368 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5369 udelay(50); 5370 } 5371 5372 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5373 { 5374 uint32_t tmp; 5375 5376 /* enable Save Restore Machine */ 5377 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5378 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5379 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5380 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5381 } 5382 5383 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5384 { 5385 const struct rlc_firmware_header_v2_0 *hdr; 5386 const __le32 *fw_data; 5387 unsigned i, fw_size; 5388 5389 if (!adev->gfx.rlc_fw) 5390 return -EINVAL; 5391 5392 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5393 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5394 5395 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5396 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5397 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5398 5399 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5400 RLCG_UCODE_LOADING_START_ADDRESS); 5401 5402 for (i = 0; i < fw_size; i++) 5403 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5404 le32_to_cpup(fw_data++)); 5405 5406 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5407 5408 return 0; 5409 } 5410 5411 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5412 { 5413 int r; 5414 5415 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5416 adev->psp.autoload_supported) { 5417 5418 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5419 if (r) 5420 return r; 5421 5422 gfx_v10_0_init_csb(adev); 5423 5424 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5425 gfx_v10_0_rlc_enable_srm(adev); 5426 } else { 5427 if (amdgpu_sriov_vf(adev)) { 5428 gfx_v10_0_init_csb(adev); 5429 return 0; 5430 } 5431 5432 adev->gfx.rlc.funcs->stop(adev); 5433 5434 /* disable CG */ 5435 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5436 5437 /* disable PG */ 5438 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5439 5440 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5441 /* legacy rlc firmware loading */ 5442 r = gfx_v10_0_rlc_load_microcode(adev); 5443 if (r) 5444 return r; 5445 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5446 /* rlc backdoor autoload firmware */ 5447 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5448 if (r) 5449 return r; 5450 } 5451 5452 gfx_v10_0_init_csb(adev); 5453 5454 adev->gfx.rlc.funcs->start(adev); 5455 5456 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5457 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5458 if (r) 5459 return r; 5460 } 5461 } 5462 return 0; 5463 } 5464 5465 static struct { 5466 FIRMWARE_ID id; 5467 unsigned int offset; 5468 unsigned int size; 5469 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5470 5471 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5472 { 5473 int ret; 5474 RLC_TABLE_OF_CONTENT *rlc_toc; 5475 5476 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5477 AMDGPU_GEM_DOMAIN_GTT, 5478 &adev->gfx.rlc.rlc_toc_bo, 5479 &adev->gfx.rlc.rlc_toc_gpu_addr, 5480 (void **)&adev->gfx.rlc.rlc_toc_buf); 5481 if (ret) { 5482 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5483 return ret; 5484 } 5485 5486 /* Copy toc from psp sos fw to rlc toc buffer */ 5487 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5488 5489 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5490 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5491 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5492 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5493 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5494 /* Offset needs 4KB alignment */ 5495 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5496 } 5497 5498 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5499 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5500 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5501 5502 rlc_toc++; 5503 } 5504 5505 return 0; 5506 } 5507 5508 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5509 { 5510 uint32_t total_size = 0; 5511 FIRMWARE_ID id; 5512 int ret; 5513 5514 ret = gfx_v10_0_parse_rlc_toc(adev); 5515 if (ret) { 5516 dev_err(adev->dev, "failed to parse rlc toc\n"); 5517 return 0; 5518 } 5519 5520 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5521 total_size += rlc_autoload_info[id].size; 5522 5523 /* In case the offset in rlc toc ucode is aligned */ 5524 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5525 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5526 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5527 5528 return total_size; 5529 } 5530 5531 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5532 { 5533 int r; 5534 uint32_t total_size; 5535 5536 total_size = gfx_v10_0_calc_toc_total_size(adev); 5537 5538 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5539 AMDGPU_GEM_DOMAIN_GTT, 5540 &adev->gfx.rlc.rlc_autoload_bo, 5541 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5542 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5543 if (r) { 5544 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5545 return r; 5546 } 5547 5548 return 0; 5549 } 5550 5551 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5552 { 5553 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5554 &adev->gfx.rlc.rlc_toc_gpu_addr, 5555 (void **)&adev->gfx.rlc.rlc_toc_buf); 5556 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5557 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5558 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5559 } 5560 5561 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5562 FIRMWARE_ID id, 5563 const void *fw_data, 5564 uint32_t fw_size) 5565 { 5566 uint32_t toc_offset; 5567 uint32_t toc_fw_size; 5568 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5569 5570 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5571 return; 5572 5573 toc_offset = rlc_autoload_info[id].offset; 5574 toc_fw_size = rlc_autoload_info[id].size; 5575 5576 if (fw_size == 0) 5577 fw_size = toc_fw_size; 5578 5579 if (fw_size > toc_fw_size) 5580 fw_size = toc_fw_size; 5581 5582 memcpy(ptr + toc_offset, fw_data, fw_size); 5583 5584 if (fw_size < toc_fw_size) 5585 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5586 } 5587 5588 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5589 { 5590 void *data; 5591 uint32_t size; 5592 5593 data = adev->gfx.rlc.rlc_toc_buf; 5594 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5595 5596 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5597 FIRMWARE_ID_RLC_TOC, 5598 data, size); 5599 } 5600 5601 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5602 { 5603 const __le32 *fw_data; 5604 uint32_t fw_size; 5605 const struct gfx_firmware_header_v1_0 *cp_hdr; 5606 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5607 5608 /* pfp ucode */ 5609 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5610 adev->gfx.pfp_fw->data; 5611 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5612 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5613 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5614 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5615 FIRMWARE_ID_CP_PFP, 5616 fw_data, fw_size); 5617 5618 /* ce ucode */ 5619 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5620 adev->gfx.ce_fw->data; 5621 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5622 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5623 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5624 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5625 FIRMWARE_ID_CP_CE, 5626 fw_data, fw_size); 5627 5628 /* me ucode */ 5629 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5630 adev->gfx.me_fw->data; 5631 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5632 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5633 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5634 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5635 FIRMWARE_ID_CP_ME, 5636 fw_data, fw_size); 5637 5638 /* rlc ucode */ 5639 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5640 adev->gfx.rlc_fw->data; 5641 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5642 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5643 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5644 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5645 FIRMWARE_ID_RLC_G_UCODE, 5646 fw_data, fw_size); 5647 5648 /* mec1 ucode */ 5649 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5650 adev->gfx.mec_fw->data; 5651 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5652 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5653 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5654 cp_hdr->jt_size * 4; 5655 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5656 FIRMWARE_ID_CP_MEC, 5657 fw_data, fw_size); 5658 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5659 } 5660 5661 /* Temporarily put sdma part here */ 5662 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5663 { 5664 const __le32 *fw_data; 5665 uint32_t fw_size; 5666 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5667 int i; 5668 5669 for (i = 0; i < adev->sdma.num_instances; i++) { 5670 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5671 adev->sdma.instance[i].fw->data; 5672 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5673 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5674 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5675 5676 if (i == 0) { 5677 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5678 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5679 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5680 FIRMWARE_ID_SDMA0_JT, 5681 (uint32_t *)fw_data + 5682 sdma_hdr->jt_offset, 5683 sdma_hdr->jt_size * 4); 5684 } else if (i == 1) { 5685 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5686 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5687 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5688 FIRMWARE_ID_SDMA1_JT, 5689 (uint32_t *)fw_data + 5690 sdma_hdr->jt_offset, 5691 sdma_hdr->jt_size * 4); 5692 } 5693 } 5694 } 5695 5696 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5697 { 5698 uint32_t rlc_g_offset, rlc_g_size, tmp; 5699 uint64_t gpu_addr; 5700 5701 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5702 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5703 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5704 5705 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5706 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5707 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5708 5709 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5710 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5711 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5712 5713 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5714 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5715 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5716 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5717 return -EINVAL; 5718 } 5719 5720 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5721 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5722 DRM_ERROR("RLC ROM should halt itself\n"); 5723 return -EINVAL; 5724 } 5725 5726 return 0; 5727 } 5728 5729 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5730 { 5731 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5732 uint32_t tmp; 5733 int i; 5734 uint64_t addr; 5735 5736 /* Trigger an invalidation of the L1 instruction caches */ 5737 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5738 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5739 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5740 5741 /* Wait for invalidation complete */ 5742 for (i = 0; i < usec_timeout; i++) { 5743 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5744 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5745 INVALIDATE_CACHE_COMPLETE)) 5746 break; 5747 udelay(1); 5748 } 5749 5750 if (i >= usec_timeout) { 5751 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5752 return -EINVAL; 5753 } 5754 5755 /* Program me ucode address into intruction cache address register */ 5756 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5757 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5758 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5759 lower_32_bits(addr) & 0xFFFFF000); 5760 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5761 upper_32_bits(addr)); 5762 5763 return 0; 5764 } 5765 5766 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5767 { 5768 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5769 uint32_t tmp; 5770 int i; 5771 uint64_t addr; 5772 5773 /* Trigger an invalidation of the L1 instruction caches */ 5774 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5775 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5776 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5777 5778 /* Wait for invalidation complete */ 5779 for (i = 0; i < usec_timeout; i++) { 5780 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5781 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5782 INVALIDATE_CACHE_COMPLETE)) 5783 break; 5784 udelay(1); 5785 } 5786 5787 if (i >= usec_timeout) { 5788 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5789 return -EINVAL; 5790 } 5791 5792 /* Program ce ucode address into intruction cache address register */ 5793 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5794 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5795 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5796 lower_32_bits(addr) & 0xFFFFF000); 5797 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5798 upper_32_bits(addr)); 5799 5800 return 0; 5801 } 5802 5803 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5804 { 5805 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5806 uint32_t tmp; 5807 int i; 5808 uint64_t addr; 5809 5810 /* Trigger an invalidation of the L1 instruction caches */ 5811 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5812 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5813 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5814 5815 /* Wait for invalidation complete */ 5816 for (i = 0; i < usec_timeout; i++) { 5817 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5818 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5819 INVALIDATE_CACHE_COMPLETE)) 5820 break; 5821 udelay(1); 5822 } 5823 5824 if (i >= usec_timeout) { 5825 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5826 return -EINVAL; 5827 } 5828 5829 /* Program pfp ucode address into intruction cache address register */ 5830 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5831 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5832 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5833 lower_32_bits(addr) & 0xFFFFF000); 5834 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5835 upper_32_bits(addr)); 5836 5837 return 0; 5838 } 5839 5840 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5841 { 5842 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5843 uint32_t tmp; 5844 int i; 5845 uint64_t addr; 5846 5847 /* Trigger an invalidation of the L1 instruction caches */ 5848 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5849 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5850 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5851 5852 /* Wait for invalidation complete */ 5853 for (i = 0; i < usec_timeout; i++) { 5854 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5855 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5856 INVALIDATE_CACHE_COMPLETE)) 5857 break; 5858 udelay(1); 5859 } 5860 5861 if (i >= usec_timeout) { 5862 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5863 return -EINVAL; 5864 } 5865 5866 /* Program mec1 ucode address into intruction cache address register */ 5867 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5868 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5869 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5870 lower_32_bits(addr) & 0xFFFFF000); 5871 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5872 upper_32_bits(addr)); 5873 5874 return 0; 5875 } 5876 5877 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5878 { 5879 uint32_t cp_status; 5880 uint32_t bootload_status; 5881 int i, r; 5882 5883 for (i = 0; i < adev->usec_timeout; i++) { 5884 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5885 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5886 if ((cp_status == 0) && 5887 (REG_GET_FIELD(bootload_status, 5888 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5889 break; 5890 } 5891 udelay(1); 5892 } 5893 5894 if (i >= adev->usec_timeout) { 5895 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5896 return -ETIMEDOUT; 5897 } 5898 5899 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5900 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5901 if (r) 5902 return r; 5903 5904 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5905 if (r) 5906 return r; 5907 5908 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5909 if (r) 5910 return r; 5911 5912 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5913 if (r) 5914 return r; 5915 } 5916 5917 return 0; 5918 } 5919 5920 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5921 { 5922 int i; 5923 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5924 5925 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5926 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5927 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5928 5929 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5930 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5931 } else { 5932 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5933 } 5934 5935 for (i = 0; i < adev->usec_timeout; i++) { 5936 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5937 break; 5938 udelay(1); 5939 } 5940 5941 if (i >= adev->usec_timeout) 5942 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5943 5944 return 0; 5945 } 5946 5947 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5948 { 5949 int r; 5950 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5951 const __le32 *fw_data; 5952 unsigned i, fw_size; 5953 uint32_t tmp; 5954 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5955 5956 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5957 adev->gfx.pfp_fw->data; 5958 5959 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5960 5961 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5962 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5963 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5964 5965 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5966 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5967 &adev->gfx.pfp.pfp_fw_obj, 5968 &adev->gfx.pfp.pfp_fw_gpu_addr, 5969 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5970 if (r) { 5971 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5972 gfx_v10_0_pfp_fini(adev); 5973 return r; 5974 } 5975 5976 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5977 5978 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5979 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5980 5981 /* Trigger an invalidation of the L1 instruction caches */ 5982 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5983 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5984 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5985 5986 /* Wait for invalidation complete */ 5987 for (i = 0; i < usec_timeout; i++) { 5988 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5989 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5990 INVALIDATE_CACHE_COMPLETE)) 5991 break; 5992 udelay(1); 5993 } 5994 5995 if (i >= usec_timeout) { 5996 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5997 return -EINVAL; 5998 } 5999 6000 if (amdgpu_emu_mode == 1) 6001 adev->hdp.funcs->flush_hdp(adev, NULL); 6002 6003 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 6004 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 6005 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 6006 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 6007 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6008 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 6009 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 6010 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 6011 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 6012 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 6013 6014 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 6015 6016 for (i = 0; i < pfp_hdr->jt_size; i++) 6017 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 6018 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 6019 6020 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 6021 6022 return 0; 6023 } 6024 6025 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 6026 { 6027 int r; 6028 const struct gfx_firmware_header_v1_0 *ce_hdr; 6029 const __le32 *fw_data; 6030 unsigned i, fw_size; 6031 uint32_t tmp; 6032 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6033 6034 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 6035 adev->gfx.ce_fw->data; 6036 6037 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 6038 6039 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 6040 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 6041 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 6042 6043 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 6044 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6045 &adev->gfx.ce.ce_fw_obj, 6046 &adev->gfx.ce.ce_fw_gpu_addr, 6047 (void **)&adev->gfx.ce.ce_fw_ptr); 6048 if (r) { 6049 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 6050 gfx_v10_0_ce_fini(adev); 6051 return r; 6052 } 6053 6054 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 6055 6056 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 6057 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 6058 6059 /* Trigger an invalidation of the L1 instruction caches */ 6060 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6061 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6062 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 6063 6064 /* Wait for invalidation complete */ 6065 for (i = 0; i < usec_timeout; i++) { 6066 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 6067 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 6068 INVALIDATE_CACHE_COMPLETE)) 6069 break; 6070 udelay(1); 6071 } 6072 6073 if (i >= usec_timeout) { 6074 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6075 return -EINVAL; 6076 } 6077 6078 if (amdgpu_emu_mode == 1) 6079 adev->hdp.funcs->flush_hdp(adev, NULL); 6080 6081 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 6082 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 6083 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 6084 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 6085 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6086 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 6087 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 6088 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 6089 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 6090 6091 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 6092 6093 for (i = 0; i < ce_hdr->jt_size; i++) 6094 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 6095 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 6096 6097 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 6098 6099 return 0; 6100 } 6101 6102 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 6103 { 6104 int r; 6105 const struct gfx_firmware_header_v1_0 *me_hdr; 6106 const __le32 *fw_data; 6107 unsigned i, fw_size; 6108 uint32_t tmp; 6109 uint32_t usec_timeout = 50000; /* wait for 50ms */ 6110 6111 me_hdr = (const struct gfx_firmware_header_v1_0 *) 6112 adev->gfx.me_fw->data; 6113 6114 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 6115 6116 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 6117 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 6118 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 6119 6120 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 6121 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 6122 &adev->gfx.me.me_fw_obj, 6123 &adev->gfx.me.me_fw_gpu_addr, 6124 (void **)&adev->gfx.me.me_fw_ptr); 6125 if (r) { 6126 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 6127 gfx_v10_0_me_fini(adev); 6128 return r; 6129 } 6130 6131 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 6132 6133 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 6134 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 6135 6136 /* Trigger an invalidation of the L1 instruction caches */ 6137 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6138 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6139 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 6140 6141 /* Wait for invalidation complete */ 6142 for (i = 0; i < usec_timeout; i++) { 6143 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 6144 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 6145 INVALIDATE_CACHE_COMPLETE)) 6146 break; 6147 udelay(1); 6148 } 6149 6150 if (i >= usec_timeout) { 6151 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6152 return -EINVAL; 6153 } 6154 6155 if (amdgpu_emu_mode == 1) 6156 adev->hdp.funcs->flush_hdp(adev, NULL); 6157 6158 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 6159 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 6160 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 6161 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 6162 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6163 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 6164 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 6165 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 6166 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 6167 6168 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 6169 6170 for (i = 0; i < me_hdr->jt_size; i++) 6171 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 6172 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 6173 6174 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 6175 6176 return 0; 6177 } 6178 6179 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 6180 { 6181 int r; 6182 6183 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 6184 return -EINVAL; 6185 6186 gfx_v10_0_cp_gfx_enable(adev, false); 6187 6188 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 6189 if (r) { 6190 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 6191 return r; 6192 } 6193 6194 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 6195 if (r) { 6196 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 6197 return r; 6198 } 6199 6200 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6201 if (r) { 6202 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6203 return r; 6204 } 6205 6206 return 0; 6207 } 6208 6209 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6210 { 6211 struct amdgpu_ring *ring; 6212 const struct cs_section_def *sect = NULL; 6213 const struct cs_extent_def *ext = NULL; 6214 int r, i; 6215 int ctx_reg_offset; 6216 6217 /* init the CP */ 6218 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6219 adev->gfx.config.max_hw_contexts - 1); 6220 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6221 6222 gfx_v10_0_cp_gfx_enable(adev, true); 6223 6224 ring = &adev->gfx.gfx_ring[0]; 6225 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6226 if (r) { 6227 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6228 return r; 6229 } 6230 6231 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6232 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6233 6234 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6235 amdgpu_ring_write(ring, 0x80000000); 6236 amdgpu_ring_write(ring, 0x80000000); 6237 6238 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6239 for (ext = sect->section; ext->extent != NULL; ++ext) { 6240 if (sect->id == SECT_CONTEXT) { 6241 amdgpu_ring_write(ring, 6242 PACKET3(PACKET3_SET_CONTEXT_REG, 6243 ext->reg_count)); 6244 amdgpu_ring_write(ring, ext->reg_index - 6245 PACKET3_SET_CONTEXT_REG_START); 6246 for (i = 0; i < ext->reg_count; i++) 6247 amdgpu_ring_write(ring, ext->extent[i]); 6248 } 6249 } 6250 } 6251 6252 ctx_reg_offset = 6253 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6254 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6255 amdgpu_ring_write(ring, ctx_reg_offset); 6256 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6257 6258 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6259 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6260 6261 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6262 amdgpu_ring_write(ring, 0); 6263 6264 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6265 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6266 amdgpu_ring_write(ring, 0x8000); 6267 amdgpu_ring_write(ring, 0x8000); 6268 6269 amdgpu_ring_commit(ring); 6270 6271 /* submit cs packet to copy state 0 to next available state */ 6272 if (adev->gfx.num_gfx_rings > 1) { 6273 /* maximum supported gfx ring is 2 */ 6274 ring = &adev->gfx.gfx_ring[1]; 6275 r = amdgpu_ring_alloc(ring, 2); 6276 if (r) { 6277 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6278 return r; 6279 } 6280 6281 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6282 amdgpu_ring_write(ring, 0); 6283 6284 amdgpu_ring_commit(ring); 6285 } 6286 return 0; 6287 } 6288 6289 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6290 CP_PIPE_ID pipe) 6291 { 6292 u32 tmp; 6293 6294 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6295 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6296 6297 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6298 } 6299 6300 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6301 struct amdgpu_ring *ring) 6302 { 6303 u32 tmp; 6304 6305 if (!amdgpu_async_gfx_ring) { 6306 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6307 if (ring->use_doorbell) { 6308 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6309 DOORBELL_OFFSET, ring->doorbell_index); 6310 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6311 DOORBELL_EN, 1); 6312 } else { 6313 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6314 DOORBELL_EN, 0); 6315 } 6316 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6317 } 6318 switch (adev->ip_versions[GC_HWIP][0]) { 6319 case IP_VERSION(10, 3, 0): 6320 case IP_VERSION(10, 3, 2): 6321 case IP_VERSION(10, 3, 1): 6322 case IP_VERSION(10, 3, 4): 6323 case IP_VERSION(10, 3, 5): 6324 case IP_VERSION(10, 3, 3): 6325 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6326 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6327 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6328 6329 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6330 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6331 break; 6332 default: 6333 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6334 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6335 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6336 6337 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6338 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6339 break; 6340 } 6341 } 6342 6343 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6344 { 6345 struct amdgpu_ring *ring; 6346 u32 tmp; 6347 u32 rb_bufsz; 6348 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6349 u32 i; 6350 6351 /* Set the write pointer delay */ 6352 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6353 6354 /* set the RB to use vmid 0 */ 6355 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6356 6357 /* Init gfx ring 0 for pipe 0 */ 6358 mutex_lock(&adev->srbm_mutex); 6359 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6360 6361 /* Set ring buffer size */ 6362 ring = &adev->gfx.gfx_ring[0]; 6363 rb_bufsz = order_base_2(ring->ring_size / 8); 6364 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6365 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6366 #ifdef __BIG_ENDIAN 6367 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6368 #endif 6369 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6370 6371 /* Initialize the ring buffer's write pointers */ 6372 ring->wptr = 0; 6373 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6374 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6375 6376 /* set the wb address wether it's enabled or not */ 6377 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6378 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6379 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6380 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6381 6382 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6383 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6384 lower_32_bits(wptr_gpu_addr)); 6385 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6386 upper_32_bits(wptr_gpu_addr)); 6387 6388 mdelay(1); 6389 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6390 6391 rb_addr = ring->gpu_addr >> 8; 6392 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6393 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6394 6395 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6396 6397 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6398 mutex_unlock(&adev->srbm_mutex); 6399 6400 /* Init gfx ring 1 for pipe 1 */ 6401 if (adev->gfx.num_gfx_rings > 1) { 6402 mutex_lock(&adev->srbm_mutex); 6403 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6404 /* maximum supported gfx ring is 2 */ 6405 ring = &adev->gfx.gfx_ring[1]; 6406 rb_bufsz = order_base_2(ring->ring_size / 8); 6407 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6408 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6409 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6410 /* Initialize the ring buffer's write pointers */ 6411 ring->wptr = 0; 6412 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6413 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6414 /* Set the wb address wether it's enabled or not */ 6415 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6416 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6417 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6418 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6419 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6420 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6421 lower_32_bits(wptr_gpu_addr)); 6422 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6423 upper_32_bits(wptr_gpu_addr)); 6424 6425 mdelay(1); 6426 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6427 6428 rb_addr = ring->gpu_addr >> 8; 6429 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6430 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6431 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6432 6433 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6434 mutex_unlock(&adev->srbm_mutex); 6435 } 6436 /* Switch to pipe 0 */ 6437 mutex_lock(&adev->srbm_mutex); 6438 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6439 mutex_unlock(&adev->srbm_mutex); 6440 6441 /* start the ring */ 6442 gfx_v10_0_cp_gfx_start(adev); 6443 6444 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6445 ring = &adev->gfx.gfx_ring[i]; 6446 ring->sched.ready = true; 6447 } 6448 6449 return 0; 6450 } 6451 6452 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6453 { 6454 if (enable) { 6455 switch (adev->ip_versions[GC_HWIP][0]) { 6456 case IP_VERSION(10, 3, 0): 6457 case IP_VERSION(10, 3, 2): 6458 case IP_VERSION(10, 3, 1): 6459 case IP_VERSION(10, 3, 4): 6460 case IP_VERSION(10, 3, 5): 6461 case IP_VERSION(10, 3, 3): 6462 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6463 break; 6464 default: 6465 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6466 break; 6467 } 6468 } else { 6469 switch (adev->ip_versions[GC_HWIP][0]) { 6470 case IP_VERSION(10, 3, 0): 6471 case IP_VERSION(10, 3, 2): 6472 case IP_VERSION(10, 3, 1): 6473 case IP_VERSION(10, 3, 4): 6474 case IP_VERSION(10, 3, 5): 6475 case IP_VERSION(10, 3, 3): 6476 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6477 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6478 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6479 break; 6480 default: 6481 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6482 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6483 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6484 break; 6485 } 6486 adev->gfx.kiq.ring.sched.ready = false; 6487 } 6488 udelay(50); 6489 } 6490 6491 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6492 { 6493 const struct gfx_firmware_header_v1_0 *mec_hdr; 6494 const __le32 *fw_data; 6495 unsigned i; 6496 u32 tmp; 6497 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6498 6499 if (!adev->gfx.mec_fw) 6500 return -EINVAL; 6501 6502 gfx_v10_0_cp_compute_enable(adev, false); 6503 6504 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6505 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6506 6507 fw_data = (const __le32 *) 6508 (adev->gfx.mec_fw->data + 6509 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6510 6511 /* Trigger an invalidation of the L1 instruction caches */ 6512 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6513 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6514 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6515 6516 /* Wait for invalidation complete */ 6517 for (i = 0; i < usec_timeout; i++) { 6518 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6519 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6520 INVALIDATE_CACHE_COMPLETE)) 6521 break; 6522 udelay(1); 6523 } 6524 6525 if (i >= usec_timeout) { 6526 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6527 return -EINVAL; 6528 } 6529 6530 if (amdgpu_emu_mode == 1) 6531 adev->hdp.funcs->flush_hdp(adev, NULL); 6532 6533 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6534 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6535 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6536 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6537 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6538 6539 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6540 0xFFFFF000); 6541 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6542 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6543 6544 /* MEC1 */ 6545 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6546 6547 for (i = 0; i < mec_hdr->jt_size; i++) 6548 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6549 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6550 6551 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6552 6553 /* 6554 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6555 * different microcode than MEC1. 6556 */ 6557 6558 return 0; 6559 } 6560 6561 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6562 { 6563 uint32_t tmp; 6564 struct amdgpu_device *adev = ring->adev; 6565 6566 /* tell RLC which is KIQ queue */ 6567 switch (adev->ip_versions[GC_HWIP][0]) { 6568 case IP_VERSION(10, 3, 0): 6569 case IP_VERSION(10, 3, 2): 6570 case IP_VERSION(10, 3, 1): 6571 case IP_VERSION(10, 3, 4): 6572 case IP_VERSION(10, 3, 5): 6573 case IP_VERSION(10, 3, 3): 6574 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6575 tmp &= 0xffffff00; 6576 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6577 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6578 tmp |= 0x80; 6579 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6580 break; 6581 default: 6582 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6583 tmp &= 0xffffff00; 6584 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6585 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6586 tmp |= 0x80; 6587 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6588 break; 6589 } 6590 } 6591 6592 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6593 { 6594 struct amdgpu_device *adev = ring->adev; 6595 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6596 uint64_t hqd_gpu_addr, wb_gpu_addr; 6597 uint32_t tmp; 6598 uint32_t rb_bufsz; 6599 6600 /* set up gfx hqd wptr */ 6601 mqd->cp_gfx_hqd_wptr = 0; 6602 mqd->cp_gfx_hqd_wptr_hi = 0; 6603 6604 /* set the pointer to the MQD */ 6605 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6606 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6607 6608 /* set up mqd control */ 6609 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6610 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6611 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6612 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6613 mqd->cp_gfx_mqd_control = tmp; 6614 6615 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6616 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6617 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6618 mqd->cp_gfx_hqd_vmid = 0; 6619 6620 /* set up default queue priority level 6621 * 0x0 = low priority, 0x1 = high priority */ 6622 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6623 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6624 mqd->cp_gfx_hqd_queue_priority = tmp; 6625 6626 /* set up time quantum */ 6627 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6628 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6629 mqd->cp_gfx_hqd_quantum = tmp; 6630 6631 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6632 hqd_gpu_addr = ring->gpu_addr >> 8; 6633 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6634 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6635 6636 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6637 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6638 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6639 mqd->cp_gfx_hqd_rptr_addr_hi = 6640 upper_32_bits(wb_gpu_addr) & 0xffff; 6641 6642 /* set up rb_wptr_poll addr */ 6643 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6644 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6645 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6646 6647 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6648 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6649 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6650 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6651 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6652 #ifdef __BIG_ENDIAN 6653 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6654 #endif 6655 mqd->cp_gfx_hqd_cntl = tmp; 6656 6657 /* set up cp_doorbell_control */ 6658 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6659 if (ring->use_doorbell) { 6660 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6661 DOORBELL_OFFSET, ring->doorbell_index); 6662 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6663 DOORBELL_EN, 1); 6664 } else 6665 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6666 DOORBELL_EN, 0); 6667 mqd->cp_rb_doorbell_control = tmp; 6668 6669 /*if there are 2 gfx rings, set the lower doorbell range of the first ring, 6670 *otherwise the range of the second ring will override the first ring */ 6671 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6672 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6673 6674 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6675 ring->wptr = 0; 6676 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6677 6678 /* active the queue */ 6679 mqd->cp_gfx_hqd_active = 1; 6680 6681 return 0; 6682 } 6683 6684 #ifdef BRING_UP_DEBUG 6685 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6686 { 6687 struct amdgpu_device *adev = ring->adev; 6688 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6689 6690 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6691 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6692 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6693 6694 /* set GFX_MQD_BASE */ 6695 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6696 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6697 6698 /* set GFX_MQD_CONTROL */ 6699 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6700 6701 /* set GFX_HQD_VMID to 0 */ 6702 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6703 6704 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6705 mqd->cp_gfx_hqd_queue_priority); 6706 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6707 6708 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6709 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6710 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6711 6712 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6713 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6714 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6715 6716 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6717 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6718 6719 /* set RB_WPTR_POLL_ADDR */ 6720 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6721 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6722 6723 /* set RB_DOORBELL_CONTROL */ 6724 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6725 6726 /* active the queue */ 6727 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6728 6729 return 0; 6730 } 6731 #endif 6732 6733 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6734 { 6735 struct amdgpu_device *adev = ring->adev; 6736 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6737 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6738 6739 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6740 memset((void *)mqd, 0, sizeof(*mqd)); 6741 mutex_lock(&adev->srbm_mutex); 6742 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6743 gfx_v10_0_gfx_mqd_init(ring); 6744 #ifdef BRING_UP_DEBUG 6745 gfx_v10_0_gfx_queue_init_register(ring); 6746 #endif 6747 nv_grbm_select(adev, 0, 0, 0, 0); 6748 mutex_unlock(&adev->srbm_mutex); 6749 if (adev->gfx.me.mqd_backup[mqd_idx]) 6750 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6751 } else if (amdgpu_in_reset(adev)) { 6752 /* reset mqd with the backup copy */ 6753 if (adev->gfx.me.mqd_backup[mqd_idx]) 6754 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6755 /* reset the ring */ 6756 ring->wptr = 0; 6757 adev->wb.wb[ring->wptr_offs] = 0; 6758 amdgpu_ring_clear_ring(ring); 6759 #ifdef BRING_UP_DEBUG 6760 mutex_lock(&adev->srbm_mutex); 6761 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6762 gfx_v10_0_gfx_queue_init_register(ring); 6763 nv_grbm_select(adev, 0, 0, 0, 0); 6764 mutex_unlock(&adev->srbm_mutex); 6765 #endif 6766 } else { 6767 amdgpu_ring_clear_ring(ring); 6768 } 6769 6770 return 0; 6771 } 6772 6773 #ifndef BRING_UP_DEBUG 6774 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6775 { 6776 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6777 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6778 int r, i; 6779 6780 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6781 return -EINVAL; 6782 6783 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6784 adev->gfx.num_gfx_rings); 6785 if (r) { 6786 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6787 return r; 6788 } 6789 6790 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6791 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6792 6793 return amdgpu_ring_test_helper(kiq_ring); 6794 } 6795 #endif 6796 6797 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6798 { 6799 int r, i; 6800 struct amdgpu_ring *ring; 6801 6802 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6803 ring = &adev->gfx.gfx_ring[i]; 6804 6805 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6806 if (unlikely(r != 0)) 6807 goto done; 6808 6809 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6810 if (!r) { 6811 r = gfx_v10_0_gfx_init_queue(ring); 6812 amdgpu_bo_kunmap(ring->mqd_obj); 6813 ring->mqd_ptr = NULL; 6814 } 6815 amdgpu_bo_unreserve(ring->mqd_obj); 6816 if (r) 6817 goto done; 6818 } 6819 #ifndef BRING_UP_DEBUG 6820 r = gfx_v10_0_kiq_enable_kgq(adev); 6821 if (r) 6822 goto done; 6823 #endif 6824 r = gfx_v10_0_cp_gfx_start(adev); 6825 if (r) 6826 goto done; 6827 6828 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6829 ring = &adev->gfx.gfx_ring[i]; 6830 ring->sched.ready = true; 6831 } 6832 done: 6833 return r; 6834 } 6835 6836 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6837 { 6838 struct amdgpu_device *adev = ring->adev; 6839 6840 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6841 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 6842 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6843 mqd->cp_hqd_queue_priority = 6844 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6845 } 6846 } 6847 } 6848 6849 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6850 { 6851 struct amdgpu_device *adev = ring->adev; 6852 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6853 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6854 uint32_t tmp; 6855 6856 mqd->header = 0xC0310800; 6857 mqd->compute_pipelinestat_enable = 0x00000001; 6858 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6859 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6860 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6861 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6862 mqd->compute_misc_reserved = 0x00000003; 6863 6864 eop_base_addr = ring->eop_gpu_addr >> 8; 6865 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6866 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6867 6868 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6869 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6870 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6871 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6872 6873 mqd->cp_hqd_eop_control = tmp; 6874 6875 /* enable doorbell? */ 6876 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6877 6878 if (ring->use_doorbell) { 6879 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6880 DOORBELL_OFFSET, ring->doorbell_index); 6881 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6882 DOORBELL_EN, 1); 6883 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6884 DOORBELL_SOURCE, 0); 6885 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6886 DOORBELL_HIT, 0); 6887 } else { 6888 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6889 DOORBELL_EN, 0); 6890 } 6891 6892 mqd->cp_hqd_pq_doorbell_control = tmp; 6893 6894 /* disable the queue if it's active */ 6895 ring->wptr = 0; 6896 mqd->cp_hqd_dequeue_request = 0; 6897 mqd->cp_hqd_pq_rptr = 0; 6898 mqd->cp_hqd_pq_wptr_lo = 0; 6899 mqd->cp_hqd_pq_wptr_hi = 0; 6900 6901 /* set the pointer to the MQD */ 6902 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6903 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6904 6905 /* set MQD vmid to 0 */ 6906 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6907 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6908 mqd->cp_mqd_control = tmp; 6909 6910 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6911 hqd_gpu_addr = ring->gpu_addr >> 8; 6912 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6913 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6914 6915 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6916 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6917 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6918 (order_base_2(ring->ring_size / 4) - 1)); 6919 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6920 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6921 #ifdef __BIG_ENDIAN 6922 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6923 #endif 6924 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6925 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6926 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6927 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6928 mqd->cp_hqd_pq_control = tmp; 6929 6930 /* set the wb address whether it's enabled or not */ 6931 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6932 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6933 mqd->cp_hqd_pq_rptr_report_addr_hi = 6934 upper_32_bits(wb_gpu_addr) & 0xffff; 6935 6936 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6937 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6938 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6939 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6940 6941 tmp = 0; 6942 /* enable the doorbell if requested */ 6943 if (ring->use_doorbell) { 6944 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6945 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6946 DOORBELL_OFFSET, ring->doorbell_index); 6947 6948 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6949 DOORBELL_EN, 1); 6950 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6951 DOORBELL_SOURCE, 0); 6952 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6953 DOORBELL_HIT, 0); 6954 } 6955 6956 mqd->cp_hqd_pq_doorbell_control = tmp; 6957 6958 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6959 ring->wptr = 0; 6960 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6961 6962 /* set the vmid for the queue */ 6963 mqd->cp_hqd_vmid = 0; 6964 6965 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6966 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6967 mqd->cp_hqd_persistent_state = tmp; 6968 6969 /* set MIN_IB_AVAIL_SIZE */ 6970 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6971 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6972 mqd->cp_hqd_ib_control = tmp; 6973 6974 /* set static priority for a compute queue/ring */ 6975 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6976 6977 /* map_queues packet doesn't need activate the queue, 6978 * so only kiq need set this field. 6979 */ 6980 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6981 mqd->cp_hqd_active = 1; 6982 6983 return 0; 6984 } 6985 6986 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6987 { 6988 struct amdgpu_device *adev = ring->adev; 6989 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6990 int j; 6991 6992 /* inactivate the queue */ 6993 if (amdgpu_sriov_vf(adev)) 6994 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6995 6996 /* disable wptr polling */ 6997 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6998 6999 /* write the EOP addr */ 7000 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 7001 mqd->cp_hqd_eop_base_addr_lo); 7002 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 7003 mqd->cp_hqd_eop_base_addr_hi); 7004 7005 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 7006 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 7007 mqd->cp_hqd_eop_control); 7008 7009 /* enable doorbell? */ 7010 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 7011 mqd->cp_hqd_pq_doorbell_control); 7012 7013 /* disable the queue if it's active */ 7014 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 7015 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 7016 for (j = 0; j < adev->usec_timeout; j++) { 7017 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 7018 break; 7019 udelay(1); 7020 } 7021 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 7022 mqd->cp_hqd_dequeue_request); 7023 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 7024 mqd->cp_hqd_pq_rptr); 7025 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7026 mqd->cp_hqd_pq_wptr_lo); 7027 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7028 mqd->cp_hqd_pq_wptr_hi); 7029 } 7030 7031 /* set the pointer to the MQD */ 7032 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 7033 mqd->cp_mqd_base_addr_lo); 7034 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 7035 mqd->cp_mqd_base_addr_hi); 7036 7037 /* set MQD vmid to 0 */ 7038 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 7039 mqd->cp_mqd_control); 7040 7041 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 7042 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 7043 mqd->cp_hqd_pq_base_lo); 7044 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 7045 mqd->cp_hqd_pq_base_hi); 7046 7047 /* set up the HQD, this is similar to CP_RB0_CNTL */ 7048 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 7049 mqd->cp_hqd_pq_control); 7050 7051 /* set the wb address whether it's enabled or not */ 7052 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 7053 mqd->cp_hqd_pq_rptr_report_addr_lo); 7054 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 7055 mqd->cp_hqd_pq_rptr_report_addr_hi); 7056 7057 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 7058 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 7059 mqd->cp_hqd_pq_wptr_poll_addr_lo); 7060 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 7061 mqd->cp_hqd_pq_wptr_poll_addr_hi); 7062 7063 /* enable the doorbell if requested */ 7064 if (ring->use_doorbell) { 7065 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 7066 (adev->doorbell_index.kiq * 2) << 2); 7067 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 7068 (adev->doorbell_index.userqueue_end * 2) << 2); 7069 } 7070 7071 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 7072 mqd->cp_hqd_pq_doorbell_control); 7073 7074 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 7075 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 7076 mqd->cp_hqd_pq_wptr_lo); 7077 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 7078 mqd->cp_hqd_pq_wptr_hi); 7079 7080 /* set the vmid for the queue */ 7081 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 7082 7083 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 7084 mqd->cp_hqd_persistent_state); 7085 7086 /* activate the queue */ 7087 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 7088 mqd->cp_hqd_active); 7089 7090 if (ring->use_doorbell) 7091 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 7092 7093 return 0; 7094 } 7095 7096 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 7097 { 7098 struct amdgpu_device *adev = ring->adev; 7099 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7100 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 7101 7102 gfx_v10_0_kiq_setting(ring); 7103 7104 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7105 /* reset MQD to a clean status */ 7106 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7107 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7108 7109 /* reset ring buffer */ 7110 ring->wptr = 0; 7111 amdgpu_ring_clear_ring(ring); 7112 7113 mutex_lock(&adev->srbm_mutex); 7114 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7115 gfx_v10_0_kiq_init_register(ring); 7116 nv_grbm_select(adev, 0, 0, 0, 0); 7117 mutex_unlock(&adev->srbm_mutex); 7118 } else { 7119 memset((void *)mqd, 0, sizeof(*mqd)); 7120 mutex_lock(&adev->srbm_mutex); 7121 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7122 gfx_v10_0_compute_mqd_init(ring); 7123 gfx_v10_0_kiq_init_register(ring); 7124 nv_grbm_select(adev, 0, 0, 0, 0); 7125 mutex_unlock(&adev->srbm_mutex); 7126 7127 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7128 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7129 } 7130 7131 return 0; 7132 } 7133 7134 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 7135 { 7136 struct amdgpu_device *adev = ring->adev; 7137 struct v10_compute_mqd *mqd = ring->mqd_ptr; 7138 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 7139 7140 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 7141 memset((void *)mqd, 0, sizeof(*mqd)); 7142 mutex_lock(&adev->srbm_mutex); 7143 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 7144 gfx_v10_0_compute_mqd_init(ring); 7145 nv_grbm_select(adev, 0, 0, 0, 0); 7146 mutex_unlock(&adev->srbm_mutex); 7147 7148 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7149 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 7150 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 7151 /* reset MQD to a clean status */ 7152 if (adev->gfx.mec.mqd_backup[mqd_idx]) 7153 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 7154 7155 /* reset ring buffer */ 7156 ring->wptr = 0; 7157 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 7158 amdgpu_ring_clear_ring(ring); 7159 } else { 7160 amdgpu_ring_clear_ring(ring); 7161 } 7162 7163 return 0; 7164 } 7165 7166 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 7167 { 7168 struct amdgpu_ring *ring; 7169 int r; 7170 7171 ring = &adev->gfx.kiq.ring; 7172 7173 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7174 if (unlikely(r != 0)) 7175 return r; 7176 7177 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7178 if (unlikely(r != 0)) 7179 return r; 7180 7181 gfx_v10_0_kiq_init_queue(ring); 7182 amdgpu_bo_kunmap(ring->mqd_obj); 7183 ring->mqd_ptr = NULL; 7184 amdgpu_bo_unreserve(ring->mqd_obj); 7185 ring->sched.ready = true; 7186 return 0; 7187 } 7188 7189 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 7190 { 7191 struct amdgpu_ring *ring = NULL; 7192 int r = 0, i; 7193 7194 gfx_v10_0_cp_compute_enable(adev, true); 7195 7196 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7197 ring = &adev->gfx.compute_ring[i]; 7198 7199 r = amdgpu_bo_reserve(ring->mqd_obj, false); 7200 if (unlikely(r != 0)) 7201 goto done; 7202 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 7203 if (!r) { 7204 r = gfx_v10_0_kcq_init_queue(ring); 7205 amdgpu_bo_kunmap(ring->mqd_obj); 7206 ring->mqd_ptr = NULL; 7207 } 7208 amdgpu_bo_unreserve(ring->mqd_obj); 7209 if (r) 7210 goto done; 7211 } 7212 7213 r = amdgpu_gfx_enable_kcq(adev); 7214 done: 7215 return r; 7216 } 7217 7218 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7219 { 7220 int r, i; 7221 struct amdgpu_ring *ring; 7222 7223 if (!(adev->flags & AMD_IS_APU)) 7224 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7225 7226 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7227 /* legacy firmware loading */ 7228 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7229 if (r) 7230 return r; 7231 7232 r = gfx_v10_0_cp_compute_load_microcode(adev); 7233 if (r) 7234 return r; 7235 } 7236 7237 r = gfx_v10_0_kiq_resume(adev); 7238 if (r) 7239 return r; 7240 7241 r = gfx_v10_0_kcq_resume(adev); 7242 if (r) 7243 return r; 7244 7245 if (!amdgpu_async_gfx_ring) { 7246 r = gfx_v10_0_cp_gfx_resume(adev); 7247 if (r) 7248 return r; 7249 } else { 7250 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7251 if (r) 7252 return r; 7253 } 7254 7255 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7256 ring = &adev->gfx.gfx_ring[i]; 7257 r = amdgpu_ring_test_helper(ring); 7258 if (r) 7259 return r; 7260 } 7261 7262 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7263 ring = &adev->gfx.compute_ring[i]; 7264 r = amdgpu_ring_test_helper(ring); 7265 if (r) 7266 return r; 7267 } 7268 7269 return 0; 7270 } 7271 7272 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7273 { 7274 gfx_v10_0_cp_gfx_enable(adev, enable); 7275 gfx_v10_0_cp_compute_enable(adev, enable); 7276 } 7277 7278 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7279 { 7280 uint32_t data, pattern = 0xDEADBEEF; 7281 7282 /* check if mmVGT_ESGS_RING_SIZE_UMD 7283 * has been remapped to mmVGT_ESGS_RING_SIZE */ 7284 switch (adev->ip_versions[GC_HWIP][0]) { 7285 case IP_VERSION(10, 3, 0): 7286 case IP_VERSION(10, 3, 2): 7287 case IP_VERSION(10, 3, 4): 7288 case IP_VERSION(10, 3, 5): 7289 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7290 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7291 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7292 7293 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7294 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 7295 return true; 7296 } else { 7297 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7298 return false; 7299 } 7300 break; 7301 case IP_VERSION(10, 3, 1): 7302 case IP_VERSION(10, 3, 3): 7303 return true; 7304 default: 7305 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7306 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7307 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7308 7309 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7310 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7311 return true; 7312 } else { 7313 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7314 return false; 7315 } 7316 break; 7317 } 7318 } 7319 7320 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7321 { 7322 uint32_t data; 7323 7324 if (amdgpu_sriov_vf(adev)) 7325 return; 7326 7327 /* initialize cam_index to 0 7328 * index will auto-inc after each data writting */ 7329 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7330 7331 switch (adev->ip_versions[GC_HWIP][0]) { 7332 case IP_VERSION(10, 3, 0): 7333 case IP_VERSION(10, 3, 2): 7334 case IP_VERSION(10, 3, 1): 7335 case IP_VERSION(10, 3, 4): 7336 case IP_VERSION(10, 3, 5): 7337 case IP_VERSION(10, 3, 3): 7338 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7339 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7340 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7341 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7342 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7343 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7344 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7345 7346 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7347 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7348 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7349 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7350 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7351 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7352 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7353 7354 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7355 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7356 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7357 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7358 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7359 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7360 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7361 7362 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7363 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7364 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7365 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7366 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7367 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7368 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7369 7370 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7371 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7372 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7373 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7374 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7375 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7376 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7377 7378 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7379 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7380 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7381 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7382 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7383 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7384 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7385 7386 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7387 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7388 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7389 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7390 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7391 break; 7392 default: 7393 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7394 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7395 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7396 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7397 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7398 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7399 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7400 7401 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7402 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7403 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7404 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7405 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7406 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7407 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7408 7409 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7410 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7411 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7412 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7413 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7414 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7415 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7416 7417 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7418 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7419 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7420 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7421 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7422 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7423 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7424 7425 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7426 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7427 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7428 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7429 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7430 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7431 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7432 7433 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7434 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7435 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7436 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7437 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7438 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7439 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7440 7441 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7442 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7443 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7444 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7445 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7446 break; 7447 } 7448 7449 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7450 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7451 } 7452 7453 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7454 { 7455 uint32_t data; 7456 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7457 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7458 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7459 7460 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7461 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7462 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7463 } 7464 7465 static int gfx_v10_0_hw_init(void *handle) 7466 { 7467 int r; 7468 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7469 7470 if (!amdgpu_emu_mode) 7471 gfx_v10_0_init_golden_registers(adev); 7472 7473 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7474 /** 7475 * For gfx 10, rlc firmware loading relies on smu firmware is 7476 * loaded firstly, so in direct type, it has to load smc ucode 7477 * here before rlc. 7478 */ 7479 if (!(adev->flags & AMD_IS_APU)) { 7480 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7481 if (r) 7482 return r; 7483 } 7484 gfx_v10_0_disable_gpa_mode(adev); 7485 } 7486 7487 /* if GRBM CAM not remapped, set up the remapping */ 7488 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7489 gfx_v10_0_setup_grbm_cam_remapping(adev); 7490 7491 gfx_v10_0_constants_init(adev); 7492 7493 r = gfx_v10_0_rlc_resume(adev); 7494 if (r) 7495 return r; 7496 7497 /* 7498 * init golden registers and rlc resume may override some registers, 7499 * reconfig them here 7500 */ 7501 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) || 7502 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) || 7503 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 7504 gfx_v10_0_tcp_harvest(adev); 7505 7506 r = gfx_v10_0_cp_resume(adev); 7507 if (r) 7508 return r; 7509 7510 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 7511 gfx_v10_3_program_pbb_mode(adev); 7512 7513 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 7514 gfx_v10_3_set_power_brake_sequence(adev); 7515 7516 return r; 7517 } 7518 7519 #ifndef BRING_UP_DEBUG 7520 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7521 { 7522 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7523 struct amdgpu_ring *kiq_ring = &kiq->ring; 7524 int i; 7525 7526 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7527 return -EINVAL; 7528 7529 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7530 adev->gfx.num_gfx_rings)) 7531 return -ENOMEM; 7532 7533 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7534 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7535 PREEMPT_QUEUES, 0, 0); 7536 7537 return amdgpu_ring_test_helper(kiq_ring); 7538 } 7539 #endif 7540 7541 static int gfx_v10_0_hw_fini(void *handle) 7542 { 7543 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7544 int r; 7545 uint32_t tmp; 7546 7547 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7548 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7549 7550 if (!adev->no_hw_access) { 7551 #ifndef BRING_UP_DEBUG 7552 if (amdgpu_async_gfx_ring) { 7553 r = gfx_v10_0_kiq_disable_kgq(adev); 7554 if (r) 7555 DRM_ERROR("KGQ disable failed\n"); 7556 } 7557 #endif 7558 if (amdgpu_gfx_disable_kcq(adev)) 7559 DRM_ERROR("KCQ disable failed\n"); 7560 } 7561 7562 if (amdgpu_sriov_vf(adev)) { 7563 gfx_v10_0_cp_gfx_enable(adev, false); 7564 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7565 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 7566 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 7567 tmp &= 0xffffff00; 7568 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 7569 } else { 7570 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7571 tmp &= 0xffffff00; 7572 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7573 } 7574 7575 return 0; 7576 } 7577 gfx_v10_0_cp_enable(adev, false); 7578 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7579 7580 return 0; 7581 } 7582 7583 static int gfx_v10_0_suspend(void *handle) 7584 { 7585 return gfx_v10_0_hw_fini(handle); 7586 } 7587 7588 static int gfx_v10_0_resume(void *handle) 7589 { 7590 return gfx_v10_0_hw_init(handle); 7591 } 7592 7593 static bool gfx_v10_0_is_idle(void *handle) 7594 { 7595 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7596 7597 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7598 GRBM_STATUS, GUI_ACTIVE)) 7599 return false; 7600 else 7601 return true; 7602 } 7603 7604 static int gfx_v10_0_wait_for_idle(void *handle) 7605 { 7606 unsigned i; 7607 u32 tmp; 7608 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7609 7610 for (i = 0; i < adev->usec_timeout; i++) { 7611 /* read MC_STATUS */ 7612 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7613 GRBM_STATUS__GUI_ACTIVE_MASK; 7614 7615 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7616 return 0; 7617 udelay(1); 7618 } 7619 return -ETIMEDOUT; 7620 } 7621 7622 static int gfx_v10_0_soft_reset(void *handle) 7623 { 7624 u32 grbm_soft_reset = 0; 7625 u32 tmp; 7626 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7627 7628 /* GRBM_STATUS */ 7629 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7630 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7631 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7632 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7633 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7634 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7635 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7636 GRBM_SOFT_RESET, SOFT_RESET_CP, 7637 1); 7638 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7639 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7640 1); 7641 } 7642 7643 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7644 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7645 GRBM_SOFT_RESET, SOFT_RESET_CP, 7646 1); 7647 } 7648 7649 /* GRBM_STATUS2 */ 7650 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7651 switch (adev->ip_versions[GC_HWIP][0]) { 7652 case IP_VERSION(10, 3, 0): 7653 case IP_VERSION(10, 3, 2): 7654 case IP_VERSION(10, 3, 1): 7655 case IP_VERSION(10, 3, 4): 7656 case IP_VERSION(10, 3, 5): 7657 case IP_VERSION(10, 3, 3): 7658 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7659 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7660 GRBM_SOFT_RESET, 7661 SOFT_RESET_RLC, 7662 1); 7663 break; 7664 default: 7665 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7666 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7667 GRBM_SOFT_RESET, 7668 SOFT_RESET_RLC, 7669 1); 7670 break; 7671 } 7672 7673 if (grbm_soft_reset) { 7674 /* stop the rlc */ 7675 gfx_v10_0_rlc_stop(adev); 7676 7677 /* Disable GFX parsing/prefetching */ 7678 gfx_v10_0_cp_gfx_enable(adev, false); 7679 7680 /* Disable MEC parsing/prefetching */ 7681 gfx_v10_0_cp_compute_enable(adev, false); 7682 7683 if (grbm_soft_reset) { 7684 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7685 tmp |= grbm_soft_reset; 7686 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7687 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7688 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7689 7690 udelay(50); 7691 7692 tmp &= ~grbm_soft_reset; 7693 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7694 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7695 } 7696 7697 /* Wait a little for things to settle down */ 7698 udelay(50); 7699 } 7700 return 0; 7701 } 7702 7703 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7704 { 7705 uint64_t clock, clock_lo, clock_hi, hi_check; 7706 7707 switch (adev->ip_versions[GC_HWIP][0]) { 7708 case IP_VERSION(10, 3, 1): 7709 case IP_VERSION(10, 3, 3): 7710 preempt_disable(); 7711 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7712 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7713 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7714 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7715 * roughly every 42 seconds. 7716 */ 7717 if (hi_check != clock_hi) { 7718 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7719 clock_hi = hi_check; 7720 } 7721 preempt_enable(); 7722 clock = clock_lo | (clock_hi << 32ULL); 7723 break; 7724 default: 7725 preempt_disable(); 7726 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7727 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7728 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7729 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7730 * roughly every 42 seconds. 7731 */ 7732 if (hi_check != clock_hi) { 7733 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7734 clock_hi = hi_check; 7735 } 7736 preempt_enable(); 7737 clock = clock_lo | (clock_hi << 32ULL); 7738 break; 7739 } 7740 return clock; 7741 } 7742 7743 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7744 uint32_t vmid, 7745 uint32_t gds_base, uint32_t gds_size, 7746 uint32_t gws_base, uint32_t gws_size, 7747 uint32_t oa_base, uint32_t oa_size) 7748 { 7749 struct amdgpu_device *adev = ring->adev; 7750 7751 /* GDS Base */ 7752 gfx_v10_0_write_data_to_reg(ring, 0, false, 7753 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7754 gds_base); 7755 7756 /* GDS Size */ 7757 gfx_v10_0_write_data_to_reg(ring, 0, false, 7758 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7759 gds_size); 7760 7761 /* GWS */ 7762 gfx_v10_0_write_data_to_reg(ring, 0, false, 7763 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7764 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7765 7766 /* OA */ 7767 gfx_v10_0_write_data_to_reg(ring, 0, false, 7768 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7769 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7770 } 7771 7772 static int gfx_v10_0_early_init(void *handle) 7773 { 7774 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7775 7776 switch (adev->ip_versions[GC_HWIP][0]) { 7777 case IP_VERSION(10, 1, 10): 7778 case IP_VERSION(10, 1, 1): 7779 case IP_VERSION(10, 1, 2): 7780 case IP_VERSION(10, 1, 3): 7781 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7782 break; 7783 case IP_VERSION(10, 3, 0): 7784 case IP_VERSION(10, 3, 2): 7785 case IP_VERSION(10, 3, 1): 7786 case IP_VERSION(10, 3, 4): 7787 case IP_VERSION(10, 3, 5): 7788 case IP_VERSION(10, 3, 3): 7789 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7790 break; 7791 default: 7792 break; 7793 } 7794 7795 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7796 AMDGPU_MAX_COMPUTE_RINGS); 7797 7798 gfx_v10_0_set_kiq_pm4_funcs(adev); 7799 gfx_v10_0_set_ring_funcs(adev); 7800 gfx_v10_0_set_irq_funcs(adev); 7801 gfx_v10_0_set_gds_init(adev); 7802 gfx_v10_0_set_rlc_funcs(adev); 7803 7804 return 0; 7805 } 7806 7807 static int gfx_v10_0_late_init(void *handle) 7808 { 7809 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7810 int r; 7811 7812 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7813 if (r) 7814 return r; 7815 7816 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7817 if (r) 7818 return r; 7819 7820 return 0; 7821 } 7822 7823 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7824 { 7825 uint32_t rlc_cntl; 7826 7827 /* if RLC is not enabled, do nothing */ 7828 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7829 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7830 } 7831 7832 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7833 { 7834 uint32_t data; 7835 unsigned i; 7836 7837 data = RLC_SAFE_MODE__CMD_MASK; 7838 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7839 7840 switch (adev->ip_versions[GC_HWIP][0]) { 7841 case IP_VERSION(10, 3, 0): 7842 case IP_VERSION(10, 3, 2): 7843 case IP_VERSION(10, 3, 1): 7844 case IP_VERSION(10, 3, 4): 7845 case IP_VERSION(10, 3, 5): 7846 case IP_VERSION(10, 3, 3): 7847 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7848 7849 /* wait for RLC_SAFE_MODE */ 7850 for (i = 0; i < adev->usec_timeout; i++) { 7851 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7852 RLC_SAFE_MODE, CMD)) 7853 break; 7854 udelay(1); 7855 } 7856 break; 7857 default: 7858 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7859 7860 /* wait for RLC_SAFE_MODE */ 7861 for (i = 0; i < adev->usec_timeout; i++) { 7862 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7863 RLC_SAFE_MODE, CMD)) 7864 break; 7865 udelay(1); 7866 } 7867 break; 7868 } 7869 } 7870 7871 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7872 { 7873 uint32_t data; 7874 7875 data = RLC_SAFE_MODE__CMD_MASK; 7876 switch (adev->ip_versions[GC_HWIP][0]) { 7877 case IP_VERSION(10, 3, 0): 7878 case IP_VERSION(10, 3, 2): 7879 case IP_VERSION(10, 3, 1): 7880 case IP_VERSION(10, 3, 4): 7881 case IP_VERSION(10, 3, 5): 7882 case IP_VERSION(10, 3, 3): 7883 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7884 break; 7885 default: 7886 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7887 break; 7888 } 7889 } 7890 7891 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7892 bool enable) 7893 { 7894 uint32_t data, def; 7895 7896 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7897 return; 7898 7899 /* It is disabled by HW by default */ 7900 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7901 /* 0 - Disable some blocks' MGCG */ 7902 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7903 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7904 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7905 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7906 7907 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7908 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7909 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7910 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7911 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7912 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7913 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7914 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7915 7916 if (def != data) 7917 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7918 7919 /* MGLS is a global flag to control all MGLS in GFX */ 7920 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7921 /* 2 - RLC memory Light sleep */ 7922 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7923 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7924 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7925 if (def != data) 7926 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7927 } 7928 /* 3 - CP memory Light sleep */ 7929 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7930 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7931 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7932 if (def != data) 7933 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7934 } 7935 } 7936 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7937 /* 1 - MGCG_OVERRIDE */ 7938 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7939 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7940 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7941 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7942 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7943 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7944 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7945 if (def != data) 7946 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7947 7948 /* 2 - disable MGLS in CP */ 7949 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7950 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7951 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7952 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7953 } 7954 7955 /* 3 - disable MGLS in RLC */ 7956 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7957 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7958 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7959 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7960 } 7961 7962 } 7963 } 7964 7965 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7966 bool enable) 7967 { 7968 uint32_t data, def; 7969 7970 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7971 return; 7972 7973 /* Enable 3D CGCG/CGLS */ 7974 if (enable) { 7975 /* write cmd to clear cgcg/cgls ov */ 7976 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7977 7978 /* unset CGCG override */ 7979 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7980 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7981 7982 /* update CGCG and CGLS override bits */ 7983 if (def != data) 7984 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7985 7986 /* enable 3Dcgcg FSM(0x0000363f) */ 7987 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7988 data = 0; 7989 7990 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7991 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7992 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7993 7994 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7995 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7996 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7997 7998 if (def != data) 7999 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8000 8001 /* set IDLE_POLL_COUNT(0x00900100) */ 8002 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8003 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8004 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8005 if (def != data) 8006 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8007 } else { 8008 /* Disable CGCG/CGLS */ 8009 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 8010 8011 /* disable cgcg, cgls should be disabled */ 8012 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 8013 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 8014 8015 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 8016 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 8017 8018 /* disable cgcg and cgls in FSM */ 8019 if (def != data) 8020 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 8021 } 8022 } 8023 8024 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 8025 bool enable) 8026 { 8027 uint32_t def, data; 8028 8029 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 8030 return; 8031 8032 if (enable) { 8033 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8034 8035 /* unset CGCG override */ 8036 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8037 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 8038 8039 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8040 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 8041 8042 /* update CGCG and CGLS override bits */ 8043 if (def != data) 8044 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8045 8046 /* enable cgcg FSM(0x0000363F) */ 8047 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8048 data = 0; 8049 8050 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8051 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 8052 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8053 8054 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8055 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 8056 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8057 8058 if (def != data) 8059 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8060 8061 /* set IDLE_POLL_COUNT(0x00900100) */ 8062 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 8063 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 8064 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 8065 if (def != data) 8066 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 8067 } else { 8068 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 8069 8070 /* reset CGCG/CGLS bits */ 8071 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 8072 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 8073 8074 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 8075 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 8076 8077 /* disable cgcg and cgls in FSM */ 8078 if (def != data) 8079 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 8080 } 8081 } 8082 8083 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 8084 bool enable) 8085 { 8086 uint32_t def, data; 8087 8088 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 8089 return; 8090 8091 if (enable) { 8092 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8093 /* unset FGCG override */ 8094 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8095 /* update FGCG override bits */ 8096 if (def != data) 8097 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8098 8099 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8100 /* unset RLC SRAM CLK GATER override */ 8101 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8102 /* update RLC SRAM CLK GATER override bits */ 8103 if (def != data) 8104 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8105 } else { 8106 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 8107 /* reset FGCG bits */ 8108 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 8109 /* disable FGCG*/ 8110 if (def != data) 8111 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 8112 8113 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 8114 /* reset RLC SRAM CLK GATER bits */ 8115 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 8116 /* disable RLC SRAM CLK*/ 8117 if (def != data) 8118 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 8119 } 8120 } 8121 8122 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 8123 { 8124 uint32_t reg_data = 0; 8125 uint32_t reg_idx = 0; 8126 uint32_t i; 8127 8128 const uint32_t tcp_ctrl_regs[] = { 8129 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8130 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8131 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8132 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8133 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8134 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8135 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8136 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8137 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8138 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8139 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 8140 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 8141 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8142 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8143 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8144 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8145 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8146 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8147 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8148 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8149 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8150 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8151 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 8152 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 8153 }; 8154 8155 const uint32_t tcp_ctrl_regs_nv12[] = { 8156 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 8157 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 8158 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 8159 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 8160 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 8161 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 8162 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 8163 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 8164 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 8165 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 8166 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8167 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8168 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8169 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8170 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8171 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8172 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8173 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8174 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8175 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8176 }; 8177 8178 const uint32_t sm_ctlr_regs[] = { 8179 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8180 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8181 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8182 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8183 }; 8184 8185 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 8186 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8187 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8188 tcp_ctrl_regs_nv12[i]; 8189 reg_data = RREG32(reg_idx); 8190 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8191 WREG32(reg_idx, reg_data); 8192 } 8193 } else { 8194 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8195 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8196 tcp_ctrl_regs[i]; 8197 reg_data = RREG32(reg_idx); 8198 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8199 WREG32(reg_idx, reg_data); 8200 } 8201 } 8202 8203 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8204 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8205 sm_ctlr_regs[i]; 8206 reg_data = RREG32(reg_idx); 8207 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8208 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8209 WREG32(reg_idx, reg_data); 8210 } 8211 } 8212 8213 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8214 bool enable) 8215 { 8216 amdgpu_gfx_rlc_enter_safe_mode(adev); 8217 8218 if (enable) { 8219 /* enable FGCG firstly*/ 8220 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8221 /* CGCG/CGLS should be enabled after MGCG/MGLS 8222 * === MGCG + MGLS === 8223 */ 8224 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8225 /* === CGCG /CGLS for GFX 3D Only === */ 8226 gfx_v10_0_update_3d_clock_gating(adev, enable); 8227 /* === CGCG + CGLS === */ 8228 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8229 8230 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) || 8231 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) || 8232 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))) 8233 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8234 } else { 8235 /* CGCG/CGLS should be disabled before MGCG/MGLS 8236 * === CGCG + CGLS === 8237 */ 8238 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8239 /* === CGCG /CGLS for GFX 3D Only === */ 8240 gfx_v10_0_update_3d_clock_gating(adev, enable); 8241 /* === MGCG + MGLS === */ 8242 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8243 /* disable fgcg at last*/ 8244 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8245 } 8246 8247 if (adev->cg_flags & 8248 (AMD_CG_SUPPORT_GFX_MGCG | 8249 AMD_CG_SUPPORT_GFX_CGLS | 8250 AMD_CG_SUPPORT_GFX_CGCG | 8251 AMD_CG_SUPPORT_GFX_3D_CGCG | 8252 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8253 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8254 8255 amdgpu_gfx_rlc_exit_safe_mode(adev); 8256 8257 return 0; 8258 } 8259 8260 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 8261 { 8262 u32 reg, data; 8263 8264 amdgpu_gfx_off_ctrl(adev, false); 8265 8266 /* not for *_SOC15 */ 8267 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8268 if (amdgpu_sriov_is_pp_one_vf(adev)) 8269 data = RREG32_NO_KIQ(reg); 8270 else 8271 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 8272 8273 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 8274 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8275 8276 if (amdgpu_sriov_is_pp_one_vf(adev)) 8277 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8278 else 8279 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8280 8281 amdgpu_gfx_off_ctrl(adev, true); 8282 } 8283 8284 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8285 uint32_t offset, 8286 struct soc15_reg_rlcg *entries, int arr_size) 8287 { 8288 int i; 8289 uint32_t reg; 8290 8291 if (!entries) 8292 return false; 8293 8294 for (i = 0; i < arr_size; i++) { 8295 const struct soc15_reg_rlcg *entry; 8296 8297 entry = &entries[i]; 8298 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8299 if (offset == reg) 8300 return true; 8301 } 8302 8303 return false; 8304 } 8305 8306 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8307 { 8308 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8309 } 8310 8311 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8312 { 8313 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8314 8315 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8316 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8317 else 8318 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8319 8320 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8321 8322 /* 8323 * CGPG enablement required and the register to program the hysteresis value 8324 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8325 * in refclk count. Note that RLC FW is modified to take 16 bits from 8326 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8327 * 8328 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8329 * of CGPG enablement starting point. 8330 * Power/performance team will optimize it and might give a new value later. 8331 */ 8332 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8333 switch (adev->ip_versions[GC_HWIP][0]) { 8334 case IP_VERSION(10, 3, 1): 8335 case IP_VERSION(10, 3, 3): 8336 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8337 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8338 break; 8339 default: 8340 break; 8341 } 8342 } 8343 } 8344 8345 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8346 { 8347 amdgpu_gfx_rlc_enter_safe_mode(adev); 8348 8349 gfx_v10_cntl_power_gating(adev, enable); 8350 8351 amdgpu_gfx_rlc_exit_safe_mode(adev); 8352 } 8353 8354 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8355 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8356 .set_safe_mode = gfx_v10_0_set_safe_mode, 8357 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8358 .init = gfx_v10_0_rlc_init, 8359 .get_csb_size = gfx_v10_0_get_csb_size, 8360 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8361 .resume = gfx_v10_0_rlc_resume, 8362 .stop = gfx_v10_0_rlc_stop, 8363 .reset = gfx_v10_0_rlc_reset, 8364 .start = gfx_v10_0_rlc_start, 8365 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8366 }; 8367 8368 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8369 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8370 .set_safe_mode = gfx_v10_0_set_safe_mode, 8371 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8372 .init = gfx_v10_0_rlc_init, 8373 .get_csb_size = gfx_v10_0_get_csb_size, 8374 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8375 .resume = gfx_v10_0_rlc_resume, 8376 .stop = gfx_v10_0_rlc_stop, 8377 .reset = gfx_v10_0_rlc_reset, 8378 .start = gfx_v10_0_rlc_start, 8379 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8380 .sriov_wreg = gfx_v10_sriov_wreg, 8381 .sriov_rreg = gfx_v10_sriov_rreg, 8382 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8383 }; 8384 8385 static int gfx_v10_0_set_powergating_state(void *handle, 8386 enum amd_powergating_state state) 8387 { 8388 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8389 bool enable = (state == AMD_PG_STATE_GATE); 8390 8391 if (amdgpu_sriov_vf(adev)) 8392 return 0; 8393 8394 switch (adev->ip_versions[GC_HWIP][0]) { 8395 case IP_VERSION(10, 1, 10): 8396 case IP_VERSION(10, 1, 1): 8397 case IP_VERSION(10, 1, 2): 8398 case IP_VERSION(10, 3, 0): 8399 case IP_VERSION(10, 3, 2): 8400 case IP_VERSION(10, 3, 4): 8401 case IP_VERSION(10, 3, 5): 8402 amdgpu_gfx_off_ctrl(adev, enable); 8403 break; 8404 case IP_VERSION(10, 3, 1): 8405 case IP_VERSION(10, 3, 3): 8406 gfx_v10_cntl_pg(adev, enable); 8407 amdgpu_gfx_off_ctrl(adev, enable); 8408 break; 8409 default: 8410 break; 8411 } 8412 return 0; 8413 } 8414 8415 static int gfx_v10_0_set_clockgating_state(void *handle, 8416 enum amd_clockgating_state state) 8417 { 8418 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8419 8420 if (amdgpu_sriov_vf(adev)) 8421 return 0; 8422 8423 switch (adev->ip_versions[GC_HWIP][0]) { 8424 case IP_VERSION(10, 1, 10): 8425 case IP_VERSION(10, 1, 1): 8426 case IP_VERSION(10, 1, 2): 8427 case IP_VERSION(10, 3, 0): 8428 case IP_VERSION(10, 3, 2): 8429 case IP_VERSION(10, 3, 1): 8430 case IP_VERSION(10, 3, 4): 8431 case IP_VERSION(10, 3, 5): 8432 case IP_VERSION(10, 3, 3): 8433 gfx_v10_0_update_gfx_clock_gating(adev, 8434 state == AMD_CG_STATE_GATE); 8435 break; 8436 default: 8437 break; 8438 } 8439 return 0; 8440 } 8441 8442 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 8443 { 8444 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8445 int data; 8446 8447 /* AMD_CG_SUPPORT_GFX_FGCG */ 8448 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8449 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8450 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8451 8452 /* AMD_CG_SUPPORT_GFX_MGCG */ 8453 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8454 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8455 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8456 8457 /* AMD_CG_SUPPORT_GFX_CGCG */ 8458 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8459 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8460 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8461 8462 /* AMD_CG_SUPPORT_GFX_CGLS */ 8463 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8464 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8465 8466 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8467 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8468 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8469 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8470 8471 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8472 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8473 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8474 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8475 8476 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8477 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8478 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8479 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8480 8481 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8482 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8483 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8484 } 8485 8486 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8487 { 8488 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 8489 } 8490 8491 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8492 { 8493 struct amdgpu_device *adev = ring->adev; 8494 u64 wptr; 8495 8496 /* XXX check if swapping is necessary on BE */ 8497 if (ring->use_doorbell) { 8498 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 8499 } else { 8500 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8501 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8502 } 8503 8504 return wptr; 8505 } 8506 8507 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8508 { 8509 struct amdgpu_device *adev = ring->adev; 8510 8511 if (ring->use_doorbell) { 8512 /* XXX check if swapping is necessary on BE */ 8513 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8514 WDOORBELL64(ring->doorbell_index, ring->wptr); 8515 } else { 8516 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 8517 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 8518 } 8519 } 8520 8521 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8522 { 8523 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 8524 } 8525 8526 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8527 { 8528 u64 wptr; 8529 8530 /* XXX check if swapping is necessary on BE */ 8531 if (ring->use_doorbell) 8532 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 8533 else 8534 BUG(); 8535 return wptr; 8536 } 8537 8538 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8539 { 8540 struct amdgpu_device *adev = ring->adev; 8541 8542 /* XXX check if swapping is necessary on BE */ 8543 if (ring->use_doorbell) { 8544 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8545 WDOORBELL64(ring->doorbell_index, ring->wptr); 8546 } else { 8547 BUG(); /* only DOORBELL method supported on gfx10 now */ 8548 } 8549 } 8550 8551 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8552 { 8553 struct amdgpu_device *adev = ring->adev; 8554 u32 ref_and_mask, reg_mem_engine; 8555 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8556 8557 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8558 switch (ring->me) { 8559 case 1: 8560 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8561 break; 8562 case 2: 8563 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8564 break; 8565 default: 8566 return; 8567 } 8568 reg_mem_engine = 0; 8569 } else { 8570 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8571 reg_mem_engine = 1; /* pfp */ 8572 } 8573 8574 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8575 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8576 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8577 ref_and_mask, ref_and_mask, 0x20); 8578 } 8579 8580 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8581 struct amdgpu_job *job, 8582 struct amdgpu_ib *ib, 8583 uint32_t flags) 8584 { 8585 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8586 u32 header, control = 0; 8587 8588 if (ib->flags & AMDGPU_IB_FLAG_CE) 8589 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8590 else 8591 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8592 8593 control |= ib->length_dw | (vmid << 24); 8594 8595 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8596 control |= INDIRECT_BUFFER_PRE_ENB(1); 8597 8598 if (flags & AMDGPU_IB_PREEMPTED) 8599 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8600 8601 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8602 gfx_v10_0_ring_emit_de_meta(ring, 8603 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8604 } 8605 8606 amdgpu_ring_write(ring, header); 8607 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8608 amdgpu_ring_write(ring, 8609 #ifdef __BIG_ENDIAN 8610 (2 << 0) | 8611 #endif 8612 lower_32_bits(ib->gpu_addr)); 8613 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8614 amdgpu_ring_write(ring, control); 8615 } 8616 8617 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8618 struct amdgpu_job *job, 8619 struct amdgpu_ib *ib, 8620 uint32_t flags) 8621 { 8622 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8623 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8624 8625 /* Currently, there is a high possibility to get wave ID mismatch 8626 * between ME and GDS, leading to a hw deadlock, because ME generates 8627 * different wave IDs than the GDS expects. This situation happens 8628 * randomly when at least 5 compute pipes use GDS ordered append. 8629 * The wave IDs generated by ME are also wrong after suspend/resume. 8630 * Those are probably bugs somewhere else in the kernel driver. 8631 * 8632 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8633 * GDS to 0 for this ring (me/pipe). 8634 */ 8635 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8636 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8637 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8638 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8639 } 8640 8641 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8642 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8643 amdgpu_ring_write(ring, 8644 #ifdef __BIG_ENDIAN 8645 (2 << 0) | 8646 #endif 8647 lower_32_bits(ib->gpu_addr)); 8648 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8649 amdgpu_ring_write(ring, control); 8650 } 8651 8652 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8653 u64 seq, unsigned flags) 8654 { 8655 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8656 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8657 8658 /* RELEASE_MEM - flush caches, send int */ 8659 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8660 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8661 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8662 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8663 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8664 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8665 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8666 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8667 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8668 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8669 8670 /* 8671 * the address should be Qword aligned if 64bit write, Dword 8672 * aligned if only send 32bit data low (discard data high) 8673 */ 8674 if (write64bit) 8675 BUG_ON(addr & 0x7); 8676 else 8677 BUG_ON(addr & 0x3); 8678 amdgpu_ring_write(ring, lower_32_bits(addr)); 8679 amdgpu_ring_write(ring, upper_32_bits(addr)); 8680 amdgpu_ring_write(ring, lower_32_bits(seq)); 8681 amdgpu_ring_write(ring, upper_32_bits(seq)); 8682 amdgpu_ring_write(ring, 0); 8683 } 8684 8685 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8686 { 8687 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8688 uint32_t seq = ring->fence_drv.sync_seq; 8689 uint64_t addr = ring->fence_drv.gpu_addr; 8690 8691 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8692 upper_32_bits(addr), seq, 0xffffffff, 4); 8693 } 8694 8695 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8696 unsigned vmid, uint64_t pd_addr) 8697 { 8698 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8699 8700 /* compute doesn't have PFP */ 8701 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8702 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8703 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8704 amdgpu_ring_write(ring, 0x0); 8705 } 8706 } 8707 8708 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8709 u64 seq, unsigned int flags) 8710 { 8711 struct amdgpu_device *adev = ring->adev; 8712 8713 /* we only allocate 32bit for each seq wb address */ 8714 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8715 8716 /* write fence seq to the "addr" */ 8717 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8718 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8719 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8720 amdgpu_ring_write(ring, lower_32_bits(addr)); 8721 amdgpu_ring_write(ring, upper_32_bits(addr)); 8722 amdgpu_ring_write(ring, lower_32_bits(seq)); 8723 8724 if (flags & AMDGPU_FENCE_FLAG_INT) { 8725 /* set register to trigger INT */ 8726 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8727 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8728 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8729 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8730 amdgpu_ring_write(ring, 0); 8731 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8732 } 8733 } 8734 8735 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8736 { 8737 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8738 amdgpu_ring_write(ring, 0); 8739 } 8740 8741 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8742 uint32_t flags) 8743 { 8744 uint32_t dw2 = 0; 8745 8746 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8747 gfx_v10_0_ring_emit_ce_meta(ring, 8748 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8749 8750 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8751 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8752 /* set load_global_config & load_global_uconfig */ 8753 dw2 |= 0x8001; 8754 /* set load_cs_sh_regs */ 8755 dw2 |= 0x01000000; 8756 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8757 dw2 |= 0x10002; 8758 8759 /* set load_ce_ram if preamble presented */ 8760 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8761 dw2 |= 0x10000000; 8762 } else { 8763 /* still load_ce_ram if this is the first time preamble presented 8764 * although there is no context switch happens. 8765 */ 8766 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8767 dw2 |= 0x10000000; 8768 } 8769 8770 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8771 amdgpu_ring_write(ring, dw2); 8772 amdgpu_ring_write(ring, 0); 8773 } 8774 8775 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8776 { 8777 unsigned ret; 8778 8779 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8780 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8781 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8782 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8783 ret = ring->wptr & ring->buf_mask; 8784 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8785 8786 return ret; 8787 } 8788 8789 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8790 { 8791 unsigned cur; 8792 BUG_ON(offset > ring->buf_mask); 8793 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8794 8795 cur = (ring->wptr - 1) & ring->buf_mask; 8796 if (likely(cur > offset)) 8797 ring->ring[offset] = cur - offset; 8798 else 8799 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8800 } 8801 8802 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8803 { 8804 int i, r = 0; 8805 struct amdgpu_device *adev = ring->adev; 8806 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8807 struct amdgpu_ring *kiq_ring = &kiq->ring; 8808 unsigned long flags; 8809 8810 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8811 return -EINVAL; 8812 8813 spin_lock_irqsave(&kiq->ring_lock, flags); 8814 8815 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8816 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8817 return -ENOMEM; 8818 } 8819 8820 /* assert preemption condition */ 8821 amdgpu_ring_set_preempt_cond_exec(ring, false); 8822 8823 /* assert IB preemption, emit the trailing fence */ 8824 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8825 ring->trail_fence_gpu_addr, 8826 ++ring->trail_seq); 8827 amdgpu_ring_commit(kiq_ring); 8828 8829 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8830 8831 /* poll the trailing fence */ 8832 for (i = 0; i < adev->usec_timeout; i++) { 8833 if (ring->trail_seq == 8834 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8835 break; 8836 udelay(1); 8837 } 8838 8839 if (i >= adev->usec_timeout) { 8840 r = -EINVAL; 8841 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8842 } 8843 8844 /* deassert preemption condition */ 8845 amdgpu_ring_set_preempt_cond_exec(ring, true); 8846 return r; 8847 } 8848 8849 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8850 { 8851 struct amdgpu_device *adev = ring->adev; 8852 struct v10_ce_ib_state ce_payload = {0}; 8853 uint64_t csa_addr; 8854 int cnt; 8855 8856 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8857 csa_addr = amdgpu_csa_vaddr(ring->adev); 8858 8859 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8860 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8861 WRITE_DATA_DST_SEL(8) | 8862 WR_CONFIRM) | 8863 WRITE_DATA_CACHE_POLICY(0)); 8864 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8865 offsetof(struct v10_gfx_meta_data, ce_payload))); 8866 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8867 offsetof(struct v10_gfx_meta_data, ce_payload))); 8868 8869 if (resume) 8870 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8871 offsetof(struct v10_gfx_meta_data, 8872 ce_payload), 8873 sizeof(ce_payload) >> 2); 8874 else 8875 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8876 sizeof(ce_payload) >> 2); 8877 } 8878 8879 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8880 { 8881 struct amdgpu_device *adev = ring->adev; 8882 struct v10_de_ib_state de_payload = {0}; 8883 uint64_t csa_addr, gds_addr; 8884 int cnt; 8885 8886 csa_addr = amdgpu_csa_vaddr(ring->adev); 8887 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8888 PAGE_SIZE); 8889 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8890 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8891 8892 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8893 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8894 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8895 WRITE_DATA_DST_SEL(8) | 8896 WR_CONFIRM) | 8897 WRITE_DATA_CACHE_POLICY(0)); 8898 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8899 offsetof(struct v10_gfx_meta_data, de_payload))); 8900 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8901 offsetof(struct v10_gfx_meta_data, de_payload))); 8902 8903 if (resume) 8904 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8905 offsetof(struct v10_gfx_meta_data, 8906 de_payload), 8907 sizeof(de_payload) >> 2); 8908 else 8909 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8910 sizeof(de_payload) >> 2); 8911 } 8912 8913 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8914 bool secure) 8915 { 8916 uint32_t v = secure ? FRAME_TMZ : 0; 8917 8918 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8919 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8920 } 8921 8922 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8923 uint32_t reg_val_offs) 8924 { 8925 struct amdgpu_device *adev = ring->adev; 8926 8927 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8928 amdgpu_ring_write(ring, 0 | /* src: register*/ 8929 (5 << 8) | /* dst: memory */ 8930 (1 << 20)); /* write confirm */ 8931 amdgpu_ring_write(ring, reg); 8932 amdgpu_ring_write(ring, 0); 8933 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8934 reg_val_offs * 4)); 8935 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8936 reg_val_offs * 4)); 8937 } 8938 8939 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8940 uint32_t val) 8941 { 8942 uint32_t cmd = 0; 8943 8944 switch (ring->funcs->type) { 8945 case AMDGPU_RING_TYPE_GFX: 8946 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8947 break; 8948 case AMDGPU_RING_TYPE_KIQ: 8949 cmd = (1 << 16); /* no inc addr */ 8950 break; 8951 default: 8952 cmd = WR_CONFIRM; 8953 break; 8954 } 8955 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8956 amdgpu_ring_write(ring, cmd); 8957 amdgpu_ring_write(ring, reg); 8958 amdgpu_ring_write(ring, 0); 8959 amdgpu_ring_write(ring, val); 8960 } 8961 8962 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8963 uint32_t val, uint32_t mask) 8964 { 8965 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8966 } 8967 8968 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8969 uint32_t reg0, uint32_t reg1, 8970 uint32_t ref, uint32_t mask) 8971 { 8972 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8973 struct amdgpu_device *adev = ring->adev; 8974 bool fw_version_ok = false; 8975 8976 fw_version_ok = adev->gfx.cp_fw_write_wait; 8977 8978 if (fw_version_ok) 8979 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8980 ref, mask, 0x20); 8981 else 8982 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8983 ref, mask); 8984 } 8985 8986 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8987 unsigned vmid) 8988 { 8989 struct amdgpu_device *adev = ring->adev; 8990 uint32_t value = 0; 8991 8992 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8993 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8994 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8995 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8996 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8997 } 8998 8999 static void 9000 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 9001 uint32_t me, uint32_t pipe, 9002 enum amdgpu_interrupt_state state) 9003 { 9004 uint32_t cp_int_cntl, cp_int_cntl_reg; 9005 9006 if (!me) { 9007 switch (pipe) { 9008 case 0: 9009 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 9010 break; 9011 case 1: 9012 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 9013 break; 9014 default: 9015 DRM_DEBUG("invalid pipe %d\n", pipe); 9016 return; 9017 } 9018 } else { 9019 DRM_DEBUG("invalid me %d\n", me); 9020 return; 9021 } 9022 9023 switch (state) { 9024 case AMDGPU_IRQ_STATE_DISABLE: 9025 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9026 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9027 TIME_STAMP_INT_ENABLE, 0); 9028 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9029 break; 9030 case AMDGPU_IRQ_STATE_ENABLE: 9031 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 9032 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 9033 TIME_STAMP_INT_ENABLE, 1); 9034 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 9035 break; 9036 default: 9037 break; 9038 } 9039 } 9040 9041 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 9042 int me, int pipe, 9043 enum amdgpu_interrupt_state state) 9044 { 9045 u32 mec_int_cntl, mec_int_cntl_reg; 9046 9047 /* 9048 * amdgpu controls only the first MEC. That's why this function only 9049 * handles the setting of interrupts for this specific MEC. All other 9050 * pipes' interrupts are set by amdkfd. 9051 */ 9052 9053 if (me == 1) { 9054 switch (pipe) { 9055 case 0: 9056 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9057 break; 9058 case 1: 9059 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 9060 break; 9061 case 2: 9062 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 9063 break; 9064 case 3: 9065 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 9066 break; 9067 default: 9068 DRM_DEBUG("invalid pipe %d\n", pipe); 9069 return; 9070 } 9071 } else { 9072 DRM_DEBUG("invalid me %d\n", me); 9073 return; 9074 } 9075 9076 switch (state) { 9077 case AMDGPU_IRQ_STATE_DISABLE: 9078 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9079 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9080 TIME_STAMP_INT_ENABLE, 0); 9081 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9082 break; 9083 case AMDGPU_IRQ_STATE_ENABLE: 9084 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9085 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9086 TIME_STAMP_INT_ENABLE, 1); 9087 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9088 break; 9089 default: 9090 break; 9091 } 9092 } 9093 9094 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9095 struct amdgpu_irq_src *src, 9096 unsigned type, 9097 enum amdgpu_interrupt_state state) 9098 { 9099 switch (type) { 9100 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9101 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9102 break; 9103 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9104 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9105 break; 9106 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9107 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9108 break; 9109 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9110 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9111 break; 9112 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9113 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9114 break; 9115 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9116 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9117 break; 9118 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9119 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9120 break; 9121 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9122 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9123 break; 9124 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9125 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9126 break; 9127 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9128 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9129 break; 9130 default: 9131 break; 9132 } 9133 return 0; 9134 } 9135 9136 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9137 struct amdgpu_irq_src *source, 9138 struct amdgpu_iv_entry *entry) 9139 { 9140 int i; 9141 u8 me_id, pipe_id, queue_id; 9142 struct amdgpu_ring *ring; 9143 9144 DRM_DEBUG("IH: CP EOP\n"); 9145 me_id = (entry->ring_id & 0x0c) >> 2; 9146 pipe_id = (entry->ring_id & 0x03) >> 0; 9147 queue_id = (entry->ring_id & 0x70) >> 4; 9148 9149 switch (me_id) { 9150 case 0: 9151 if (pipe_id == 0) 9152 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9153 else 9154 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9155 break; 9156 case 1: 9157 case 2: 9158 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9159 ring = &adev->gfx.compute_ring[i]; 9160 /* Per-queue interrupt is supported for MEC starting from VI. 9161 * The interrupt can only be enabled/disabled per pipe instead of per queue. 9162 */ 9163 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 9164 amdgpu_fence_process(ring); 9165 } 9166 break; 9167 } 9168 return 0; 9169 } 9170 9171 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9172 struct amdgpu_irq_src *source, 9173 unsigned type, 9174 enum amdgpu_interrupt_state state) 9175 { 9176 switch (state) { 9177 case AMDGPU_IRQ_STATE_DISABLE: 9178 case AMDGPU_IRQ_STATE_ENABLE: 9179 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9180 PRIV_REG_INT_ENABLE, 9181 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9182 break; 9183 default: 9184 break; 9185 } 9186 9187 return 0; 9188 } 9189 9190 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9191 struct amdgpu_irq_src *source, 9192 unsigned type, 9193 enum amdgpu_interrupt_state state) 9194 { 9195 switch (state) { 9196 case AMDGPU_IRQ_STATE_DISABLE: 9197 case AMDGPU_IRQ_STATE_ENABLE: 9198 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9199 PRIV_INSTR_INT_ENABLE, 9200 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9201 break; 9202 default: 9203 break; 9204 } 9205 9206 return 0; 9207 } 9208 9209 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9210 struct amdgpu_iv_entry *entry) 9211 { 9212 u8 me_id, pipe_id, queue_id; 9213 struct amdgpu_ring *ring; 9214 int i; 9215 9216 me_id = (entry->ring_id & 0x0c) >> 2; 9217 pipe_id = (entry->ring_id & 0x03) >> 0; 9218 queue_id = (entry->ring_id & 0x70) >> 4; 9219 9220 switch (me_id) { 9221 case 0: 9222 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9223 ring = &adev->gfx.gfx_ring[i]; 9224 /* we only enabled 1 gfx queue per pipe for now */ 9225 if (ring->me == me_id && ring->pipe == pipe_id) 9226 drm_sched_fault(&ring->sched); 9227 } 9228 break; 9229 case 1: 9230 case 2: 9231 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9232 ring = &adev->gfx.compute_ring[i]; 9233 if (ring->me == me_id && ring->pipe == pipe_id && 9234 ring->queue == queue_id) 9235 drm_sched_fault(&ring->sched); 9236 } 9237 break; 9238 default: 9239 BUG(); 9240 } 9241 } 9242 9243 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9244 struct amdgpu_irq_src *source, 9245 struct amdgpu_iv_entry *entry) 9246 { 9247 DRM_ERROR("Illegal register access in command stream\n"); 9248 gfx_v10_0_handle_priv_fault(adev, entry); 9249 return 0; 9250 } 9251 9252 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9253 struct amdgpu_irq_src *source, 9254 struct amdgpu_iv_entry *entry) 9255 { 9256 DRM_ERROR("Illegal instruction in command stream\n"); 9257 gfx_v10_0_handle_priv_fault(adev, entry); 9258 return 0; 9259 } 9260 9261 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9262 struct amdgpu_irq_src *src, 9263 unsigned int type, 9264 enum amdgpu_interrupt_state state) 9265 { 9266 uint32_t tmp, target; 9267 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9268 9269 if (ring->me == 1) 9270 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9271 else 9272 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9273 target += ring->pipe; 9274 9275 switch (type) { 9276 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9277 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9278 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9279 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9280 GENERIC2_INT_ENABLE, 0); 9281 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9282 9283 tmp = RREG32_SOC15_IP(GC, target); 9284 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9285 GENERIC2_INT_ENABLE, 0); 9286 WREG32_SOC15_IP(GC, target, tmp); 9287 } else { 9288 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9289 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9290 GENERIC2_INT_ENABLE, 1); 9291 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9292 9293 tmp = RREG32_SOC15_IP(GC, target); 9294 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9295 GENERIC2_INT_ENABLE, 1); 9296 WREG32_SOC15_IP(GC, target, tmp); 9297 } 9298 break; 9299 default: 9300 BUG(); /* kiq only support GENERIC2_INT now */ 9301 break; 9302 } 9303 return 0; 9304 } 9305 9306 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9307 struct amdgpu_irq_src *source, 9308 struct amdgpu_iv_entry *entry) 9309 { 9310 u8 me_id, pipe_id, queue_id; 9311 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9312 9313 me_id = (entry->ring_id & 0x0c) >> 2; 9314 pipe_id = (entry->ring_id & 0x03) >> 0; 9315 queue_id = (entry->ring_id & 0x70) >> 4; 9316 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9317 me_id, pipe_id, queue_id); 9318 9319 amdgpu_fence_process(ring); 9320 return 0; 9321 } 9322 9323 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9324 { 9325 const unsigned int gcr_cntl = 9326 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9327 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9328 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9329 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9330 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9331 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9332 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9333 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9334 9335 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9336 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9337 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9338 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9339 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9340 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9341 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9342 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9343 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9344 } 9345 9346 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9347 .name = "gfx_v10_0", 9348 .early_init = gfx_v10_0_early_init, 9349 .late_init = gfx_v10_0_late_init, 9350 .sw_init = gfx_v10_0_sw_init, 9351 .sw_fini = gfx_v10_0_sw_fini, 9352 .hw_init = gfx_v10_0_hw_init, 9353 .hw_fini = gfx_v10_0_hw_fini, 9354 .suspend = gfx_v10_0_suspend, 9355 .resume = gfx_v10_0_resume, 9356 .is_idle = gfx_v10_0_is_idle, 9357 .wait_for_idle = gfx_v10_0_wait_for_idle, 9358 .soft_reset = gfx_v10_0_soft_reset, 9359 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9360 .set_powergating_state = gfx_v10_0_set_powergating_state, 9361 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9362 }; 9363 9364 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9365 .type = AMDGPU_RING_TYPE_GFX, 9366 .align_mask = 0xff, 9367 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9368 .support_64bit_ptrs = true, 9369 .vmhub = AMDGPU_GFXHUB_0, 9370 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9371 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9372 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9373 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9374 5 + /* COND_EXEC */ 9375 7 + /* PIPELINE_SYNC */ 9376 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9377 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9378 2 + /* VM_FLUSH */ 9379 8 + /* FENCE for VM_FLUSH */ 9380 20 + /* GDS switch */ 9381 4 + /* double SWITCH_BUFFER, 9382 * the first COND_EXEC jump to the place 9383 * just prior to this double SWITCH_BUFFER 9384 */ 9385 5 + /* COND_EXEC */ 9386 7 + /* HDP_flush */ 9387 4 + /* VGT_flush */ 9388 14 + /* CE_META */ 9389 31 + /* DE_META */ 9390 3 + /* CNTX_CTRL */ 9391 5 + /* HDP_INVL */ 9392 8 + 8 + /* FENCE x2 */ 9393 2 + /* SWITCH_BUFFER */ 9394 8, /* gfx_v10_0_emit_mem_sync */ 9395 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9396 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9397 .emit_fence = gfx_v10_0_ring_emit_fence, 9398 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9399 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9400 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9401 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9402 .test_ring = gfx_v10_0_ring_test_ring, 9403 .test_ib = gfx_v10_0_ring_test_ib, 9404 .insert_nop = amdgpu_ring_insert_nop, 9405 .pad_ib = amdgpu_ring_generic_pad_ib, 9406 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9407 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9408 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9409 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9410 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9411 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9412 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9413 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9414 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9415 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9416 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9417 }; 9418 9419 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9420 .type = AMDGPU_RING_TYPE_COMPUTE, 9421 .align_mask = 0xff, 9422 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9423 .support_64bit_ptrs = true, 9424 .vmhub = AMDGPU_GFXHUB_0, 9425 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9426 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9427 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9428 .emit_frame_size = 9429 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9430 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9431 5 + /* hdp invalidate */ 9432 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9433 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9434 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9435 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9436 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9437 8, /* gfx_v10_0_emit_mem_sync */ 9438 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9439 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9440 .emit_fence = gfx_v10_0_ring_emit_fence, 9441 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9442 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9443 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9444 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9445 .test_ring = gfx_v10_0_ring_test_ring, 9446 .test_ib = gfx_v10_0_ring_test_ib, 9447 .insert_nop = amdgpu_ring_insert_nop, 9448 .pad_ib = amdgpu_ring_generic_pad_ib, 9449 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9450 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9451 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9452 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9453 }; 9454 9455 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9456 .type = AMDGPU_RING_TYPE_KIQ, 9457 .align_mask = 0xff, 9458 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9459 .support_64bit_ptrs = true, 9460 .vmhub = AMDGPU_GFXHUB_0, 9461 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9462 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9463 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9464 .emit_frame_size = 9465 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9466 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9467 5 + /*hdp invalidate */ 9468 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9469 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9470 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9471 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9472 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9473 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9474 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9475 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9476 .test_ring = gfx_v10_0_ring_test_ring, 9477 .test_ib = gfx_v10_0_ring_test_ib, 9478 .insert_nop = amdgpu_ring_insert_nop, 9479 .pad_ib = amdgpu_ring_generic_pad_ib, 9480 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9481 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9482 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9483 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9484 }; 9485 9486 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9487 { 9488 int i; 9489 9490 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9491 9492 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9493 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9494 9495 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9496 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9497 } 9498 9499 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9500 .set = gfx_v10_0_set_eop_interrupt_state, 9501 .process = gfx_v10_0_eop_irq, 9502 }; 9503 9504 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9505 .set = gfx_v10_0_set_priv_reg_fault_state, 9506 .process = gfx_v10_0_priv_reg_irq, 9507 }; 9508 9509 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9510 .set = gfx_v10_0_set_priv_inst_fault_state, 9511 .process = gfx_v10_0_priv_inst_irq, 9512 }; 9513 9514 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9515 .set = gfx_v10_0_kiq_set_interrupt_state, 9516 .process = gfx_v10_0_kiq_irq, 9517 }; 9518 9519 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9520 { 9521 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9522 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9523 9524 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9525 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9526 9527 adev->gfx.priv_reg_irq.num_types = 1; 9528 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9529 9530 adev->gfx.priv_inst_irq.num_types = 1; 9531 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9532 } 9533 9534 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9535 { 9536 switch (adev->ip_versions[GC_HWIP][0]) { 9537 case IP_VERSION(10, 1, 10): 9538 case IP_VERSION(10, 1, 1): 9539 case IP_VERSION(10, 1, 3): 9540 case IP_VERSION(10, 3, 2): 9541 case IP_VERSION(10, 3, 1): 9542 case IP_VERSION(10, 3, 4): 9543 case IP_VERSION(10, 3, 5): 9544 case IP_VERSION(10, 3, 3): 9545 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9546 break; 9547 case IP_VERSION(10, 1, 2): 9548 case IP_VERSION(10, 3, 0): 9549 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9550 break; 9551 default: 9552 break; 9553 } 9554 } 9555 9556 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9557 { 9558 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9559 adev->gfx.config.max_sh_per_se * 9560 adev->gfx.config.max_shader_engines; 9561 9562 adev->gds.gds_size = 0x10000; 9563 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9564 adev->gds.gws_size = 64; 9565 adev->gds.oa_size = 16; 9566 } 9567 9568 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9569 u32 bitmap) 9570 { 9571 u32 data; 9572 9573 if (!bitmap) 9574 return; 9575 9576 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9577 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9578 9579 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9580 } 9581 9582 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9583 { 9584 u32 disabled_mask = 9585 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9586 u32 efuse_setting = 0; 9587 u32 vbios_setting = 0; 9588 9589 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9590 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9591 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9592 9593 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9594 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9595 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9596 9597 disabled_mask |= efuse_setting | vbios_setting; 9598 9599 return (~disabled_mask); 9600 } 9601 9602 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9603 { 9604 u32 wgp_idx, wgp_active_bitmap; 9605 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9606 9607 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9608 cu_active_bitmap = 0; 9609 9610 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9611 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9612 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9613 if (wgp_active_bitmap & (1 << wgp_idx)) 9614 cu_active_bitmap |= cu_bitmap_per_wgp; 9615 } 9616 9617 return cu_active_bitmap; 9618 } 9619 9620 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9621 struct amdgpu_cu_info *cu_info) 9622 { 9623 int i, j, k, counter, active_cu_number = 0; 9624 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9625 unsigned disable_masks[4 * 2]; 9626 9627 if (!adev || !cu_info) 9628 return -EINVAL; 9629 9630 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9631 9632 mutex_lock(&adev->grbm_idx_mutex); 9633 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9634 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9635 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9636 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 9637 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) && 9638 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9639 continue; 9640 mask = 1; 9641 ao_bitmap = 0; 9642 counter = 0; 9643 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9644 if (i < 4 && j < 2) 9645 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9646 adev, disable_masks[i * 2 + j]); 9647 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9648 cu_info->bitmap[i][j] = bitmap; 9649 9650 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9651 if (bitmap & mask) { 9652 if (counter < adev->gfx.config.max_cu_per_sh) 9653 ao_bitmap |= mask; 9654 counter++; 9655 } 9656 mask <<= 1; 9657 } 9658 active_cu_number += counter; 9659 if (i < 2 && j < 2) 9660 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9661 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9662 } 9663 } 9664 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9665 mutex_unlock(&adev->grbm_idx_mutex); 9666 9667 cu_info->number = active_cu_number; 9668 cu_info->ao_cu_mask = ao_cu_mask; 9669 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9670 9671 return 0; 9672 } 9673 9674 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9675 { 9676 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9677 9678 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9679 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9680 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9681 9682 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9683 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9684 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9685 9686 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9687 adev->gfx.config.max_shader_engines); 9688 disabled_sa = efuse_setting | vbios_setting; 9689 disabled_sa &= max_sa_mask; 9690 9691 return disabled_sa; 9692 } 9693 9694 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9695 { 9696 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9697 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9698 9699 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9700 9701 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9702 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9703 max_shader_engines = adev->gfx.config.max_shader_engines; 9704 9705 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9706 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9707 disabled_sa_per_se &= max_sa_per_se_mask; 9708 if (disabled_sa_per_se == max_sa_per_se_mask) { 9709 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9710 break; 9711 } 9712 } 9713 } 9714 9715 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9716 { 9717 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9718 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9719 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9720 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9721 9722 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9723 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9724 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9725 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9726 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9727 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9728 9729 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9730 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9731 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9732 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9733 9734 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9735 9736 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9737 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9738 } 9739 9740 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9741 { 9742 .type = AMD_IP_BLOCK_TYPE_GFX, 9743 .major = 10, 9744 .minor = 0, 9745 .rev = 0, 9746 .funcs = &gfx_v10_0_ip_funcs, 9747 }; 9748