1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 114 115 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 121 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 125 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 127 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 129 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 131 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 134 135 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 137 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 139 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 141 #define mmCP_HYP_CE_UCODE_DATA 0x5819 142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 143 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 145 #define mmCP_HYP_ME_UCODE_DATA 0x5817 146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 147 148 #define mmCPG_PSP_DEBUG 0x5c10 149 #define mmCPG_PSP_DEBUG_BASE_IDX 1 150 #define mmCPC_PSP_DEBUG 0x5c11 151 #define mmCPC_PSP_DEBUG_BASE_IDX 1 152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 154 155 //CC_GC_SA_UNIT_DISABLE 156 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 160 //GC_USER_SA_UNIT_DISABLE 161 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //PA_SC_ENHANCE_3 166 #define mmPA_SC_ENHANCE_3 0x1085 167 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 170 171 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 173 174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 178 179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 181 182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 184 185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 187 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 191 192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 203 204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 206 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 210 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 217 218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 224 225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 231 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 238 239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 245 246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 252 253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 259 260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 266 267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 273 274 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 315 }; 316 317 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 318 /* Pending on emulation bring up */ 319 }; 320 321 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1374 }; 1375 1376 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1415 }; 1416 1417 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1460 }; 1461 1462 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1463 /* Pending on emulation bring up */ 1464 }; 1465 1466 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2087 }; 2088 2089 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2090 /* Pending on emulation bring up */ 2091 }; 2092 2093 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3146 }; 3147 3148 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3192 }; 3193 3194 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3195 /* Pending on emulation bring up */ 3196 }; 3197 3198 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3240 3241 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3243 }; 3244 3245 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3270 3271 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3273 }; 3274 3275 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3296 }; 3297 3298 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3335 }; 3336 3337 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3370 }; 3371 3372 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3407 }; 3408 3409 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3432 }; 3433 3434 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3457 }; 3458 3459 #define DEFAULT_SH_MEM_CONFIG \ 3460 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3461 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3462 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3463 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3464 3465 /* TODO: pending on golden setting value of gb address config */ 3466 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3467 3468 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3469 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3470 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3471 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3472 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3473 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3474 struct amdgpu_cu_info *cu_info); 3475 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3476 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3477 u32 sh_num, u32 instance, int xcc_id); 3478 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3479 3480 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3481 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3482 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3483 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3484 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3485 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3486 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3487 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3488 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3489 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3490 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3491 uint16_t pasid, uint32_t flush_type, 3492 bool all_hub, uint8_t dst_sel); 3493 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3494 unsigned int vmid); 3495 3496 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3497 { 3498 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3499 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3500 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3501 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3502 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3503 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3504 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3505 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3506 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3507 } 3508 3509 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3510 struct amdgpu_ring *ring) 3511 { 3512 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3513 uint64_t wptr_addr = ring->wptr_gpu_addr; 3514 uint32_t eng_sel = 0; 3515 3516 switch (ring->funcs->type) { 3517 case AMDGPU_RING_TYPE_COMPUTE: 3518 eng_sel = 0; 3519 break; 3520 case AMDGPU_RING_TYPE_GFX: 3521 eng_sel = 4; 3522 break; 3523 case AMDGPU_RING_TYPE_MES: 3524 eng_sel = 5; 3525 break; 3526 default: 3527 WARN_ON(1); 3528 } 3529 3530 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3531 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3532 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3533 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3534 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3535 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3536 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3537 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3538 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3539 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3540 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3541 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3542 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3543 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3544 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3545 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3546 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3547 } 3548 3549 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3550 struct amdgpu_ring *ring, 3551 enum amdgpu_unmap_queues_action action, 3552 u64 gpu_addr, u64 seq) 3553 { 3554 struct amdgpu_device *adev = kiq_ring->adev; 3555 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3556 3557 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 3558 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 3559 return; 3560 } 3561 3562 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3563 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3564 PACKET3_UNMAP_QUEUES_ACTION(action) | 3565 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3566 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3567 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3568 amdgpu_ring_write(kiq_ring, 3569 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3570 3571 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3572 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3573 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3574 amdgpu_ring_write(kiq_ring, seq); 3575 } else { 3576 amdgpu_ring_write(kiq_ring, 0); 3577 amdgpu_ring_write(kiq_ring, 0); 3578 amdgpu_ring_write(kiq_ring, 0); 3579 } 3580 } 3581 3582 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3583 struct amdgpu_ring *ring, 3584 u64 addr, 3585 u64 seq) 3586 { 3587 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3588 3589 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3590 amdgpu_ring_write(kiq_ring, 3591 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3592 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3593 PACKET3_QUERY_STATUS_COMMAND(2)); 3594 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3595 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3596 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3597 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3598 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3599 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3600 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3601 } 3602 3603 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3604 uint16_t pasid, uint32_t flush_type, 3605 bool all_hub) 3606 { 3607 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3608 } 3609 3610 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3611 .kiq_set_resources = gfx10_kiq_set_resources, 3612 .kiq_map_queues = gfx10_kiq_map_queues, 3613 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3614 .kiq_query_status = gfx10_kiq_query_status, 3615 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3616 .set_resources_size = 8, 3617 .map_queues_size = 7, 3618 .unmap_queues_size = 6, 3619 .query_status_size = 7, 3620 .invalidate_tlbs_size = 2, 3621 }; 3622 3623 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3624 { 3625 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3626 } 3627 3628 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3629 { 3630 switch (adev->ip_versions[GC_HWIP][0]) { 3631 case IP_VERSION(10, 1, 10): 3632 soc15_program_register_sequence(adev, 3633 golden_settings_gc_rlc_spm_10_0_nv10, 3634 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3635 break; 3636 case IP_VERSION(10, 1, 1): 3637 soc15_program_register_sequence(adev, 3638 golden_settings_gc_rlc_spm_10_1_nv14, 3639 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3640 break; 3641 case IP_VERSION(10, 1, 2): 3642 soc15_program_register_sequence(adev, 3643 golden_settings_gc_rlc_spm_10_1_2_nv12, 3644 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3645 break; 3646 default: 3647 break; 3648 } 3649 } 3650 3651 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3652 { 3653 switch (adev->ip_versions[GC_HWIP][0]) { 3654 case IP_VERSION(10, 1, 10): 3655 soc15_program_register_sequence(adev, 3656 golden_settings_gc_10_1, 3657 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3658 soc15_program_register_sequence(adev, 3659 golden_settings_gc_10_0_nv10, 3660 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3661 break; 3662 case IP_VERSION(10, 1, 1): 3663 soc15_program_register_sequence(adev, 3664 golden_settings_gc_10_1_1, 3665 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3666 soc15_program_register_sequence(adev, 3667 golden_settings_gc_10_1_nv14, 3668 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3669 break; 3670 case IP_VERSION(10, 1, 2): 3671 soc15_program_register_sequence(adev, 3672 golden_settings_gc_10_1_2, 3673 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3674 soc15_program_register_sequence(adev, 3675 golden_settings_gc_10_1_2_nv12, 3676 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3677 break; 3678 case IP_VERSION(10, 3, 0): 3679 soc15_program_register_sequence(adev, 3680 golden_settings_gc_10_3, 3681 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3682 soc15_program_register_sequence(adev, 3683 golden_settings_gc_10_3_sienna_cichlid, 3684 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3685 break; 3686 case IP_VERSION(10, 3, 2): 3687 soc15_program_register_sequence(adev, 3688 golden_settings_gc_10_3_2, 3689 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3690 break; 3691 case IP_VERSION(10, 3, 1): 3692 soc15_program_register_sequence(adev, 3693 golden_settings_gc_10_3_vangogh, 3694 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3695 break; 3696 case IP_VERSION(10, 3, 3): 3697 soc15_program_register_sequence(adev, 3698 golden_settings_gc_10_3_3, 3699 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3700 break; 3701 case IP_VERSION(10, 3, 4): 3702 soc15_program_register_sequence(adev, 3703 golden_settings_gc_10_3_4, 3704 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3705 break; 3706 case IP_VERSION(10, 3, 5): 3707 soc15_program_register_sequence(adev, 3708 golden_settings_gc_10_3_5, 3709 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3710 break; 3711 case IP_VERSION(10, 1, 3): 3712 case IP_VERSION(10, 1, 4): 3713 soc15_program_register_sequence(adev, 3714 golden_settings_gc_10_0_cyan_skillfish, 3715 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3716 break; 3717 case IP_VERSION(10, 3, 6): 3718 soc15_program_register_sequence(adev, 3719 golden_settings_gc_10_3_6, 3720 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3721 break; 3722 case IP_VERSION(10, 3, 7): 3723 soc15_program_register_sequence(adev, 3724 golden_settings_gc_10_3_7, 3725 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3726 break; 3727 default: 3728 break; 3729 } 3730 gfx_v10_0_init_spm_golden_registers(adev); 3731 } 3732 3733 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3734 bool wc, uint32_t reg, uint32_t val) 3735 { 3736 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3737 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3738 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3739 amdgpu_ring_write(ring, reg); 3740 amdgpu_ring_write(ring, 0); 3741 amdgpu_ring_write(ring, val); 3742 } 3743 3744 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3745 int mem_space, int opt, uint32_t addr0, 3746 uint32_t addr1, uint32_t ref, uint32_t mask, 3747 uint32_t inv) 3748 { 3749 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3750 amdgpu_ring_write(ring, 3751 /* memory (1) or register (0) */ 3752 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3753 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3754 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3755 WAIT_REG_MEM_ENGINE(eng_sel))); 3756 3757 if (mem_space) 3758 BUG_ON(addr0 & 0x3); /* Dword align */ 3759 amdgpu_ring_write(ring, addr0); 3760 amdgpu_ring_write(ring, addr1); 3761 amdgpu_ring_write(ring, ref); 3762 amdgpu_ring_write(ring, mask); 3763 amdgpu_ring_write(ring, inv); /* poll interval */ 3764 } 3765 3766 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3767 { 3768 struct amdgpu_device *adev = ring->adev; 3769 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3770 uint32_t tmp = 0; 3771 unsigned int i; 3772 int r; 3773 3774 WREG32(scratch, 0xCAFEDEAD); 3775 r = amdgpu_ring_alloc(ring, 3); 3776 if (r) { 3777 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3778 ring->idx, r); 3779 return r; 3780 } 3781 3782 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3783 amdgpu_ring_write(ring, scratch - 3784 PACKET3_SET_UCONFIG_REG_START); 3785 amdgpu_ring_write(ring, 0xDEADBEEF); 3786 amdgpu_ring_commit(ring); 3787 3788 for (i = 0; i < adev->usec_timeout; i++) { 3789 tmp = RREG32(scratch); 3790 if (tmp == 0xDEADBEEF) 3791 break; 3792 if (amdgpu_emu_mode == 1) 3793 msleep(1); 3794 else 3795 udelay(1); 3796 } 3797 3798 if (i >= adev->usec_timeout) 3799 r = -ETIMEDOUT; 3800 3801 return r; 3802 } 3803 3804 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3805 { 3806 struct amdgpu_device *adev = ring->adev; 3807 struct amdgpu_ib ib; 3808 struct dma_fence *f = NULL; 3809 unsigned int index; 3810 uint64_t gpu_addr; 3811 volatile uint32_t *cpu_ptr; 3812 long r; 3813 3814 memset(&ib, 0, sizeof(ib)); 3815 3816 if (ring->is_mes_queue) { 3817 uint32_t padding, offset; 3818 3819 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 3820 padding = amdgpu_mes_ctx_get_offs(ring, 3821 AMDGPU_MES_CTX_PADDING_OFFS); 3822 3823 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 3824 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 3825 3826 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 3827 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 3828 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 3829 } else { 3830 r = amdgpu_device_wb_get(adev, &index); 3831 if (r) 3832 return r; 3833 3834 gpu_addr = adev->wb.gpu_addr + (index * 4); 3835 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3836 cpu_ptr = &adev->wb.wb[index]; 3837 3838 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 3839 if (r) { 3840 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 3841 goto err1; 3842 } 3843 } 3844 3845 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3846 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3847 ib.ptr[2] = lower_32_bits(gpu_addr); 3848 ib.ptr[3] = upper_32_bits(gpu_addr); 3849 ib.ptr[4] = 0xDEADBEEF; 3850 ib.length_dw = 5; 3851 3852 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3853 if (r) 3854 goto err2; 3855 3856 r = dma_fence_wait_timeout(f, false, timeout); 3857 if (r == 0) { 3858 r = -ETIMEDOUT; 3859 goto err2; 3860 } else if (r < 0) { 3861 goto err2; 3862 } 3863 3864 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 3865 r = 0; 3866 else 3867 r = -EINVAL; 3868 err2: 3869 if (!ring->is_mes_queue) 3870 amdgpu_ib_free(adev, &ib, NULL); 3871 dma_fence_put(f); 3872 err1: 3873 if (!ring->is_mes_queue) 3874 amdgpu_device_wb_free(adev, index); 3875 return r; 3876 } 3877 3878 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3879 { 3880 amdgpu_ucode_release(&adev->gfx.pfp_fw); 3881 amdgpu_ucode_release(&adev->gfx.me_fw); 3882 amdgpu_ucode_release(&adev->gfx.ce_fw); 3883 amdgpu_ucode_release(&adev->gfx.rlc_fw); 3884 amdgpu_ucode_release(&adev->gfx.mec_fw); 3885 amdgpu_ucode_release(&adev->gfx.mec2_fw); 3886 3887 kfree(adev->gfx.rlc.register_list_format); 3888 } 3889 3890 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3891 { 3892 adev->gfx.cp_fw_write_wait = false; 3893 3894 switch (adev->ip_versions[GC_HWIP][0]) { 3895 case IP_VERSION(10, 1, 10): 3896 case IP_VERSION(10, 1, 2): 3897 case IP_VERSION(10, 1, 1): 3898 case IP_VERSION(10, 1, 3): 3899 case IP_VERSION(10, 1, 4): 3900 if ((adev->gfx.me_fw_version >= 0x00000046) && 3901 (adev->gfx.me_feature_version >= 27) && 3902 (adev->gfx.pfp_fw_version >= 0x00000068) && 3903 (adev->gfx.pfp_feature_version >= 27) && 3904 (adev->gfx.mec_fw_version >= 0x0000005b) && 3905 (adev->gfx.mec_feature_version >= 27)) 3906 adev->gfx.cp_fw_write_wait = true; 3907 break; 3908 case IP_VERSION(10, 3, 0): 3909 case IP_VERSION(10, 3, 2): 3910 case IP_VERSION(10, 3, 1): 3911 case IP_VERSION(10, 3, 4): 3912 case IP_VERSION(10, 3, 5): 3913 case IP_VERSION(10, 3, 6): 3914 case IP_VERSION(10, 3, 3): 3915 case IP_VERSION(10, 3, 7): 3916 adev->gfx.cp_fw_write_wait = true; 3917 break; 3918 default: 3919 break; 3920 } 3921 3922 if (!adev->gfx.cp_fw_write_wait) 3923 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3924 } 3925 3926 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3927 { 3928 bool ret = false; 3929 3930 switch (adev->pdev->revision) { 3931 case 0xc2: 3932 case 0xc3: 3933 ret = true; 3934 break; 3935 default: 3936 ret = false; 3937 break; 3938 } 3939 3940 return ret; 3941 } 3942 3943 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3944 { 3945 switch (adev->ip_versions[GC_HWIP][0]) { 3946 case IP_VERSION(10, 1, 10): 3947 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3948 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3949 break; 3950 default: 3951 break; 3952 } 3953 } 3954 3955 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3956 { 3957 char fw_name[40]; 3958 char ucode_prefix[30]; 3959 const char *wks = ""; 3960 int err; 3961 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3962 uint16_t version_major; 3963 uint16_t version_minor; 3964 3965 DRM_DEBUG("\n"); 3966 3967 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) && 3968 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 3969 wks = "_wks"; 3970 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 3971 3972 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 3973 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 3974 if (err) 3975 goto out; 3976 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 3977 3978 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks); 3979 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 3980 if (err) 3981 goto out; 3982 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 3983 3984 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 3985 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 3986 if (err) 3987 goto out; 3988 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 3989 3990 if (!amdgpu_sriov_vf(adev)) { 3991 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 3992 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 3993 /* don't check this. There are apparently firmwares in the wild with 3994 * incorrect size in the header 3995 */ 3996 if (err == -ENODEV) 3997 goto out; 3998 if (err) 3999 dev_dbg(adev->dev, 4000 "gfx10: amdgpu_ucode_request() failed \"%s\"\n", 4001 fw_name); 4002 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4003 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4004 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4005 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4006 if (err) 4007 goto out; 4008 } 4009 4010 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4011 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 4012 if (err) 4013 goto out; 4014 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4015 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4016 4017 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4018 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 4019 if (!err) { 4020 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4021 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4022 } else { 4023 err = 0; 4024 adev->gfx.mec2_fw = NULL; 4025 } 4026 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4027 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4028 4029 gfx_v10_0_check_fw_write_wait(adev); 4030 out: 4031 if (err) { 4032 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4033 amdgpu_ucode_release(&adev->gfx.me_fw); 4034 amdgpu_ucode_release(&adev->gfx.ce_fw); 4035 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4036 amdgpu_ucode_release(&adev->gfx.mec_fw); 4037 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4038 } 4039 4040 gfx_v10_0_check_gfxoff_flag(adev); 4041 4042 return err; 4043 } 4044 4045 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4046 { 4047 u32 count = 0; 4048 const struct cs_section_def *sect = NULL; 4049 const struct cs_extent_def *ext = NULL; 4050 4051 /* begin clear state */ 4052 count += 2; 4053 /* context control state */ 4054 count += 3; 4055 4056 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4057 for (ext = sect->section; ext->extent != NULL; ++ext) { 4058 if (sect->id == SECT_CONTEXT) 4059 count += 2 + ext->reg_count; 4060 else 4061 return 0; 4062 } 4063 } 4064 4065 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4066 count += 3; 4067 /* end clear state */ 4068 count += 2; 4069 /* clear state */ 4070 count += 2; 4071 4072 return count; 4073 } 4074 4075 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4076 volatile u32 *buffer) 4077 { 4078 u32 count = 0, i; 4079 const struct cs_section_def *sect = NULL; 4080 const struct cs_extent_def *ext = NULL; 4081 int ctx_reg_offset; 4082 4083 if (adev->gfx.rlc.cs_data == NULL) 4084 return; 4085 if (buffer == NULL) 4086 return; 4087 4088 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4089 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4090 4091 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4092 buffer[count++] = cpu_to_le32(0x80000000); 4093 buffer[count++] = cpu_to_le32(0x80000000); 4094 4095 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4096 for (ext = sect->section; ext->extent != NULL; ++ext) { 4097 if (sect->id == SECT_CONTEXT) { 4098 buffer[count++] = 4099 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4100 buffer[count++] = cpu_to_le32(ext->reg_index - 4101 PACKET3_SET_CONTEXT_REG_START); 4102 for (i = 0; i < ext->reg_count; i++) 4103 buffer[count++] = cpu_to_le32(ext->extent[i]); 4104 } else { 4105 return; 4106 } 4107 } 4108 } 4109 4110 ctx_reg_offset = 4111 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4112 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4113 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4114 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4115 4116 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4117 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4118 4119 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4120 buffer[count++] = cpu_to_le32(0); 4121 } 4122 4123 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4124 { 4125 /* clear state block */ 4126 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4127 &adev->gfx.rlc.clear_state_gpu_addr, 4128 (void **)&adev->gfx.rlc.cs_ptr); 4129 4130 /* jump table block */ 4131 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4132 &adev->gfx.rlc.cp_table_gpu_addr, 4133 (void **)&adev->gfx.rlc.cp_table_ptr); 4134 } 4135 4136 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4137 { 4138 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4139 4140 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4141 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4142 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4143 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4144 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4145 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4146 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4147 switch (adev->ip_versions[GC_HWIP][0]) { 4148 case IP_VERSION(10, 3, 0): 4149 reg_access_ctrl->spare_int = 4150 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4151 break; 4152 default: 4153 reg_access_ctrl->spare_int = 4154 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4155 break; 4156 } 4157 adev->gfx.rlc.rlcg_reg_access_supported = true; 4158 } 4159 4160 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4161 { 4162 const struct cs_section_def *cs_data; 4163 int r; 4164 4165 adev->gfx.rlc.cs_data = gfx10_cs_data; 4166 4167 cs_data = adev->gfx.rlc.cs_data; 4168 4169 if (cs_data) { 4170 /* init clear state block */ 4171 r = amdgpu_gfx_rlc_init_csb(adev); 4172 if (r) 4173 return r; 4174 } 4175 4176 return 0; 4177 } 4178 4179 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4180 { 4181 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4182 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4183 } 4184 4185 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4186 { 4187 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4188 4189 amdgpu_gfx_graphics_queue_acquire(adev); 4190 } 4191 4192 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4193 { 4194 int r; 4195 u32 *hpd; 4196 const __le32 *fw_data = NULL; 4197 unsigned int fw_size; 4198 u32 *fw = NULL; 4199 size_t mec_hpd_size; 4200 4201 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4202 4203 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4204 4205 /* take ownership of the relevant compute queues */ 4206 amdgpu_gfx_compute_queue_acquire(adev); 4207 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4208 4209 if (mec_hpd_size) { 4210 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4211 AMDGPU_GEM_DOMAIN_GTT, 4212 &adev->gfx.mec.hpd_eop_obj, 4213 &adev->gfx.mec.hpd_eop_gpu_addr, 4214 (void **)&hpd); 4215 if (r) { 4216 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4217 gfx_v10_0_mec_fini(adev); 4218 return r; 4219 } 4220 4221 memset(hpd, 0, mec_hpd_size); 4222 4223 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4224 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4225 } 4226 4227 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4228 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4229 4230 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4231 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4232 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4233 4234 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4235 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4236 &adev->gfx.mec.mec_fw_obj, 4237 &adev->gfx.mec.mec_fw_gpu_addr, 4238 (void **)&fw); 4239 if (r) { 4240 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4241 gfx_v10_0_mec_fini(adev); 4242 return r; 4243 } 4244 4245 memcpy(fw, fw_data, fw_size); 4246 4247 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4248 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4249 } 4250 4251 return 0; 4252 } 4253 4254 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4255 { 4256 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4257 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4258 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4259 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4260 } 4261 4262 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4263 uint32_t thread, uint32_t regno, 4264 uint32_t num, uint32_t *out) 4265 { 4266 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4267 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4268 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4269 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4270 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4271 while (num--) 4272 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4273 } 4274 4275 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4276 { 4277 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4278 * field when performing a select_se_sh so it should be 4279 * zero here 4280 */ 4281 WARN_ON(simd != 0); 4282 4283 /* type 2 wave data */ 4284 dst[(*no_fields)++] = 2; 4285 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4286 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4287 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4288 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4289 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4290 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4291 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4292 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4293 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4294 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4295 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4296 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4297 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4298 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4299 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4300 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4301 } 4302 4303 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4304 uint32_t wave, uint32_t start, 4305 uint32_t size, uint32_t *dst) 4306 { 4307 WARN_ON(simd != 0); 4308 4309 wave_read_regs( 4310 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4311 dst); 4312 } 4313 4314 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4315 uint32_t wave, uint32_t thread, 4316 uint32_t start, uint32_t size, 4317 uint32_t *dst) 4318 { 4319 wave_read_regs( 4320 adev, wave, thread, 4321 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4322 } 4323 4324 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4325 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4326 { 4327 nv_grbm_select(adev, me, pipe, q, vm); 4328 } 4329 4330 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4331 bool enable) 4332 { 4333 uint32_t data, def; 4334 4335 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4336 4337 if (enable) 4338 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4339 else 4340 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4341 4342 if (data != def) 4343 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4344 } 4345 4346 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4347 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4348 .select_se_sh = &gfx_v10_0_select_se_sh, 4349 .read_wave_data = &gfx_v10_0_read_wave_data, 4350 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4351 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4352 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4353 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4354 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4355 }; 4356 4357 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4358 { 4359 u32 gb_addr_config; 4360 4361 switch (adev->ip_versions[GC_HWIP][0]) { 4362 case IP_VERSION(10, 1, 10): 4363 case IP_VERSION(10, 1, 1): 4364 case IP_VERSION(10, 1, 2): 4365 adev->gfx.config.max_hw_contexts = 8; 4366 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4367 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4368 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4369 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4370 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4371 break; 4372 case IP_VERSION(10, 3, 0): 4373 case IP_VERSION(10, 3, 2): 4374 case IP_VERSION(10, 3, 1): 4375 case IP_VERSION(10, 3, 4): 4376 case IP_VERSION(10, 3, 5): 4377 case IP_VERSION(10, 3, 6): 4378 case IP_VERSION(10, 3, 3): 4379 case IP_VERSION(10, 3, 7): 4380 adev->gfx.config.max_hw_contexts = 8; 4381 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4382 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4383 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4384 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4385 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4386 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4387 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4388 break; 4389 case IP_VERSION(10, 1, 3): 4390 case IP_VERSION(10, 1, 4): 4391 adev->gfx.config.max_hw_contexts = 8; 4392 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4393 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4394 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4395 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4396 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4397 break; 4398 default: 4399 BUG(); 4400 break; 4401 } 4402 4403 adev->gfx.config.gb_addr_config = gb_addr_config; 4404 4405 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4406 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4407 GB_ADDR_CONFIG, NUM_PIPES); 4408 4409 adev->gfx.config.max_tile_pipes = 4410 adev->gfx.config.gb_addr_config_fields.num_pipes; 4411 4412 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4413 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4414 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4415 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4416 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4417 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4418 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4419 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4420 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4421 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4422 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4423 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4424 } 4425 4426 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4427 int me, int pipe, int queue) 4428 { 4429 struct amdgpu_ring *ring; 4430 unsigned int irq_type; 4431 unsigned int hw_prio; 4432 4433 ring = &adev->gfx.gfx_ring[ring_id]; 4434 4435 ring->me = me; 4436 ring->pipe = pipe; 4437 ring->queue = queue; 4438 4439 ring->ring_obj = NULL; 4440 ring->use_doorbell = true; 4441 4442 if (!ring_id) 4443 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4444 else 4445 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4446 ring->vm_hub = AMDGPU_GFXHUB(0); 4447 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4448 4449 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4450 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4451 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4452 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4453 hw_prio, NULL); 4454 } 4455 4456 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4457 int mec, int pipe, int queue) 4458 { 4459 unsigned int irq_type; 4460 struct amdgpu_ring *ring; 4461 unsigned int hw_prio; 4462 4463 ring = &adev->gfx.compute_ring[ring_id]; 4464 4465 /* mec0 is me1 */ 4466 ring->me = mec + 1; 4467 ring->pipe = pipe; 4468 ring->queue = queue; 4469 4470 ring->ring_obj = NULL; 4471 ring->use_doorbell = true; 4472 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4473 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4474 + (ring_id * GFX10_MEC_HPD_SIZE); 4475 ring->vm_hub = AMDGPU_GFXHUB(0); 4476 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4477 4478 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4479 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4480 + ring->pipe; 4481 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4482 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4483 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4484 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4485 hw_prio, NULL); 4486 } 4487 4488 static int gfx_v10_0_sw_init(void *handle) 4489 { 4490 int i, j, k, r, ring_id = 0; 4491 struct amdgpu_kiq *kiq; 4492 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4493 4494 switch (adev->ip_versions[GC_HWIP][0]) { 4495 case IP_VERSION(10, 1, 10): 4496 case IP_VERSION(10, 1, 1): 4497 case IP_VERSION(10, 1, 2): 4498 case IP_VERSION(10, 1, 3): 4499 case IP_VERSION(10, 1, 4): 4500 adev->gfx.me.num_me = 1; 4501 adev->gfx.me.num_pipe_per_me = 1; 4502 adev->gfx.me.num_queue_per_pipe = 1; 4503 adev->gfx.mec.num_mec = 2; 4504 adev->gfx.mec.num_pipe_per_mec = 4; 4505 adev->gfx.mec.num_queue_per_pipe = 8; 4506 break; 4507 case IP_VERSION(10, 3, 0): 4508 case IP_VERSION(10, 3, 2): 4509 case IP_VERSION(10, 3, 1): 4510 case IP_VERSION(10, 3, 4): 4511 case IP_VERSION(10, 3, 5): 4512 case IP_VERSION(10, 3, 6): 4513 case IP_VERSION(10, 3, 3): 4514 case IP_VERSION(10, 3, 7): 4515 adev->gfx.me.num_me = 1; 4516 adev->gfx.me.num_pipe_per_me = 1; 4517 adev->gfx.me.num_queue_per_pipe = 1; 4518 adev->gfx.mec.num_mec = 2; 4519 adev->gfx.mec.num_pipe_per_mec = 4; 4520 adev->gfx.mec.num_queue_per_pipe = 4; 4521 break; 4522 default: 4523 adev->gfx.me.num_me = 1; 4524 adev->gfx.me.num_pipe_per_me = 1; 4525 adev->gfx.me.num_queue_per_pipe = 1; 4526 adev->gfx.mec.num_mec = 1; 4527 adev->gfx.mec.num_pipe_per_mec = 4; 4528 adev->gfx.mec.num_queue_per_pipe = 8; 4529 break; 4530 } 4531 4532 /* KIQ event */ 4533 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4534 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4535 &adev->gfx.kiq[0].irq); 4536 if (r) 4537 return r; 4538 4539 /* EOP Event */ 4540 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4541 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4542 &adev->gfx.eop_irq); 4543 if (r) 4544 return r; 4545 4546 /* Privileged reg */ 4547 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4548 &adev->gfx.priv_reg_irq); 4549 if (r) 4550 return r; 4551 4552 /* Privileged inst */ 4553 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4554 &adev->gfx.priv_inst_irq); 4555 if (r) 4556 return r; 4557 4558 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4559 4560 gfx_v10_0_me_init(adev); 4561 4562 if (adev->gfx.rlc.funcs) { 4563 if (adev->gfx.rlc.funcs->init) { 4564 r = adev->gfx.rlc.funcs->init(adev); 4565 if (r) { 4566 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4567 return r; 4568 } 4569 } 4570 } 4571 4572 r = gfx_v10_0_mec_init(adev); 4573 if (r) { 4574 DRM_ERROR("Failed to init MEC BOs!\n"); 4575 return r; 4576 } 4577 4578 /* set up the gfx ring */ 4579 for (i = 0; i < adev->gfx.me.num_me; i++) { 4580 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4581 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4582 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4583 continue; 4584 4585 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4586 i, k, j); 4587 if (r) 4588 return r; 4589 ring_id++; 4590 } 4591 } 4592 } 4593 4594 ring_id = 0; 4595 /* set up the compute queues - allocate horizontally across pipes */ 4596 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4597 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4598 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4599 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4600 k, j)) 4601 continue; 4602 4603 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4604 i, k, j); 4605 if (r) 4606 return r; 4607 4608 ring_id++; 4609 } 4610 } 4611 } 4612 4613 if (!adev->enable_mes_kiq) { 4614 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4615 if (r) { 4616 DRM_ERROR("Failed to init KIQ BOs!\n"); 4617 return r; 4618 } 4619 4620 kiq = &adev->gfx.kiq[0]; 4621 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 4622 if (r) 4623 return r; 4624 } 4625 4626 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4627 if (r) 4628 return r; 4629 4630 /* allocate visible FB for rlc auto-loading fw */ 4631 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4632 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4633 if (r) 4634 return r; 4635 } 4636 4637 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4638 4639 gfx_v10_0_gpu_early_init(adev); 4640 4641 return 0; 4642 } 4643 4644 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4645 { 4646 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4647 &adev->gfx.pfp.pfp_fw_gpu_addr, 4648 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4649 } 4650 4651 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4652 { 4653 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4654 &adev->gfx.ce.ce_fw_gpu_addr, 4655 (void **)&adev->gfx.ce.ce_fw_ptr); 4656 } 4657 4658 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4659 { 4660 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4661 &adev->gfx.me.me_fw_gpu_addr, 4662 (void **)&adev->gfx.me.me_fw_ptr); 4663 } 4664 4665 static int gfx_v10_0_sw_fini(void *handle) 4666 { 4667 int i; 4668 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4669 4670 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4671 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4672 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4673 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4674 4675 amdgpu_gfx_mqd_sw_fini(adev, 0); 4676 4677 if (!adev->enable_mes_kiq) { 4678 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4679 amdgpu_gfx_kiq_fini(adev, 0); 4680 } 4681 4682 gfx_v10_0_pfp_fini(adev); 4683 gfx_v10_0_ce_fini(adev); 4684 gfx_v10_0_me_fini(adev); 4685 gfx_v10_0_rlc_fini(adev); 4686 gfx_v10_0_mec_fini(adev); 4687 4688 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4689 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4690 4691 gfx_v10_0_free_microcode(adev); 4692 4693 return 0; 4694 } 4695 4696 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4697 u32 sh_num, u32 instance, int xcc_id) 4698 { 4699 u32 data; 4700 4701 if (instance == 0xffffffff) 4702 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4703 INSTANCE_BROADCAST_WRITES, 1); 4704 else 4705 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4706 instance); 4707 4708 if (se_num == 0xffffffff) 4709 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4710 1); 4711 else 4712 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4713 4714 if (sh_num == 0xffffffff) 4715 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4716 1); 4717 else 4718 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4719 4720 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4721 } 4722 4723 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4724 { 4725 u32 data, mask; 4726 4727 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4728 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4729 4730 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4731 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4732 4733 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4734 adev->gfx.config.max_sh_per_se); 4735 4736 return (~data) & mask; 4737 } 4738 4739 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4740 { 4741 int i, j; 4742 u32 data; 4743 u32 active_rbs = 0; 4744 u32 bitmap; 4745 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4746 adev->gfx.config.max_sh_per_se; 4747 4748 mutex_lock(&adev->grbm_idx_mutex); 4749 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4750 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4751 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4752 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 4753 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 4754 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) && 4755 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4756 continue; 4757 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4758 data = gfx_v10_0_get_rb_active_bitmap(adev); 4759 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4760 rb_bitmap_width_per_sh); 4761 } 4762 } 4763 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4764 mutex_unlock(&adev->grbm_idx_mutex); 4765 4766 adev->gfx.config.backend_enable_mask = active_rbs; 4767 adev->gfx.config.num_rbs = hweight32(active_rbs); 4768 } 4769 4770 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4771 { 4772 uint32_t num_sc; 4773 uint32_t enabled_rb_per_sh; 4774 uint32_t active_rb_bitmap; 4775 uint32_t num_rb_per_sc; 4776 uint32_t num_packer_per_sc; 4777 uint32_t pa_sc_tile_steering_override; 4778 4779 /* for ASICs that integrates GFX v10.3 4780 * pa_sc_tile_steering_override should be set to 0 4781 */ 4782 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 4783 return 0; 4784 4785 /* init num_sc */ 4786 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4787 adev->gfx.config.num_sc_per_sh; 4788 /* init num_rb_per_sc */ 4789 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4790 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4791 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4792 /* init num_packer_per_sc */ 4793 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4794 4795 pa_sc_tile_steering_override = 0; 4796 pa_sc_tile_steering_override |= 4797 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4798 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4799 pa_sc_tile_steering_override |= 4800 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4801 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4802 pa_sc_tile_steering_override |= 4803 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4804 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4805 4806 return pa_sc_tile_steering_override; 4807 } 4808 4809 #define DEFAULT_SH_MEM_BASES (0x6000) 4810 4811 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 4812 uint32_t first_vmid, 4813 uint32_t last_vmid) 4814 { 4815 uint32_t data; 4816 uint32_t trap_config_vmid_mask = 0; 4817 int i; 4818 4819 /* Calculate trap config vmid mask */ 4820 for (i = first_vmid; i < last_vmid; i++) 4821 trap_config_vmid_mask |= (1 << i); 4822 4823 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 4824 VMID_SEL, trap_config_vmid_mask); 4825 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 4826 TRAP_EN, 1); 4827 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 4828 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 4829 4830 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 4831 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 4832 } 4833 4834 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4835 { 4836 int i; 4837 uint32_t sh_mem_bases; 4838 4839 /* 4840 * Configure apertures: 4841 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4842 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4843 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4844 */ 4845 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4846 4847 mutex_lock(&adev->srbm_mutex); 4848 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4849 nv_grbm_select(adev, 0, 0, 0, i); 4850 /* CP and shaders */ 4851 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4852 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4853 } 4854 nv_grbm_select(adev, 0, 0, 0, 0); 4855 mutex_unlock(&adev->srbm_mutex); 4856 4857 /* 4858 * Initialize all compute VMIDs to have no GDS, GWS, or OA 4859 * access. These should be enabled by FW for target VMIDs. 4860 */ 4861 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4862 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4863 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4864 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4865 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4866 } 4867 4868 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 4869 AMDGPU_NUM_VMID); 4870 } 4871 4872 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4873 { 4874 int vmid; 4875 4876 /* 4877 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4878 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4879 * the driver can enable them for graphics. VMID0 should maintain 4880 * access so that HWS firmware can save/restore entries. 4881 */ 4882 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4883 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4884 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4885 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4886 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4887 } 4888 } 4889 4890 4891 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4892 { 4893 int i, j, k; 4894 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4895 u32 tmp, wgp_active_bitmap = 0; 4896 u32 gcrd_targets_disable_tcp = 0; 4897 u32 utcl_invreq_disable = 0; 4898 /* 4899 * GCRD_TARGETS_DISABLE field contains 4900 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4901 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4902 */ 4903 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4904 2 * max_wgp_per_sh + /* TCP */ 4905 max_wgp_per_sh + /* SQC */ 4906 4); /* GL1C */ 4907 /* 4908 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4909 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4910 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4911 */ 4912 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4913 2 * max_wgp_per_sh + /* TCP */ 4914 2 * max_wgp_per_sh + /* SQC */ 4915 4 + /* RMI */ 4916 1); /* SQG */ 4917 4918 mutex_lock(&adev->grbm_idx_mutex); 4919 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4920 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4921 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4922 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4923 /* 4924 * Set corresponding TCP bits for the inactive WGPs in 4925 * GCRD_SA_TARGETS_DISABLE 4926 */ 4927 gcrd_targets_disable_tcp = 0; 4928 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4929 utcl_invreq_disable = 0; 4930 4931 for (k = 0; k < max_wgp_per_sh; k++) { 4932 if (!(wgp_active_bitmap & (1 << k))) { 4933 gcrd_targets_disable_tcp |= 3 << (2 * k); 4934 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 4935 utcl_invreq_disable |= (3 << (2 * k)) | 4936 (3 << (2 * (max_wgp_per_sh + k))); 4937 } 4938 } 4939 4940 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4941 /* only override TCP & SQC bits */ 4942 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 4943 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4944 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4945 4946 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4947 /* only override TCP & SQC bits */ 4948 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 4949 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4950 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4951 } 4952 } 4953 4954 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4955 mutex_unlock(&adev->grbm_idx_mutex); 4956 } 4957 4958 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4959 { 4960 /* TCCs are global (not instanced). */ 4961 uint32_t tcc_disable; 4962 4963 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 4964 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 4965 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 4966 } else { 4967 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4968 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4969 } 4970 4971 adev->gfx.config.tcc_disabled_mask = 4972 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4973 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4974 } 4975 4976 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4977 { 4978 u32 tmp; 4979 int i; 4980 4981 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4982 4983 gfx_v10_0_setup_rb(adev); 4984 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4985 gfx_v10_0_get_tcc_info(adev); 4986 adev->gfx.config.pa_sc_tile_steering_override = 4987 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4988 4989 /* XXX SH_MEM regs */ 4990 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4991 mutex_lock(&adev->srbm_mutex); 4992 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 4993 nv_grbm_select(adev, 0, 0, 0, i); 4994 /* CP and shaders */ 4995 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4996 if (i != 0) { 4997 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4998 (adev->gmc.private_aperture_start >> 48)); 4999 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5000 (adev->gmc.shared_aperture_start >> 48)); 5001 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5002 } 5003 } 5004 nv_grbm_select(adev, 0, 0, 0, 0); 5005 5006 mutex_unlock(&adev->srbm_mutex); 5007 5008 gfx_v10_0_init_compute_vmid(adev); 5009 gfx_v10_0_init_gds_vmid(adev); 5010 5011 } 5012 5013 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5014 bool enable) 5015 { 5016 u32 tmp; 5017 5018 if (amdgpu_sriov_vf(adev)) 5019 return; 5020 5021 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5022 5023 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5024 enable ? 1 : 0); 5025 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5026 enable ? 1 : 0); 5027 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5028 enable ? 1 : 0); 5029 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5030 enable ? 1 : 0); 5031 5032 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5033 } 5034 5035 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5036 { 5037 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5038 5039 /* csib */ 5040 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5041 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5042 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5043 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5044 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5045 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5046 } else { 5047 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5048 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5049 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5050 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5051 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5052 } 5053 return 0; 5054 } 5055 5056 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5057 { 5058 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5059 5060 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5061 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5062 } 5063 5064 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5065 { 5066 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5067 udelay(50); 5068 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5069 udelay(50); 5070 } 5071 5072 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5073 bool enable) 5074 { 5075 uint32_t rlc_pg_cntl; 5076 5077 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5078 5079 if (!enable) { 5080 /* RLC_PG_CNTL[23] = 0 (default) 5081 * RLC will wait for handshake acks with SMU 5082 * GFXOFF will be enabled 5083 * RLC_PG_CNTL[23] = 1 5084 * RLC will not issue any message to SMU 5085 * hence no handshake between SMU & RLC 5086 * GFXOFF will be disabled 5087 */ 5088 rlc_pg_cntl |= 0x800000; 5089 } else 5090 rlc_pg_cntl &= ~0x800000; 5091 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5092 } 5093 5094 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5095 { 5096 /* 5097 * TODO: enable rlc & smu handshake until smu 5098 * and gfxoff feature works as expected 5099 */ 5100 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5101 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5102 5103 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5104 udelay(50); 5105 } 5106 5107 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5108 { 5109 uint32_t tmp; 5110 5111 /* enable Save Restore Machine */ 5112 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5113 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5114 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5115 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5116 } 5117 5118 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5119 { 5120 const struct rlc_firmware_header_v2_0 *hdr; 5121 const __le32 *fw_data; 5122 unsigned int i, fw_size; 5123 5124 if (!adev->gfx.rlc_fw) 5125 return -EINVAL; 5126 5127 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5128 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5129 5130 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5131 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5132 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5133 5134 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5135 RLCG_UCODE_LOADING_START_ADDRESS); 5136 5137 for (i = 0; i < fw_size; i++) 5138 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5139 le32_to_cpup(fw_data++)); 5140 5141 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5142 5143 return 0; 5144 } 5145 5146 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5147 { 5148 int r; 5149 5150 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5151 adev->psp.autoload_supported) { 5152 5153 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5154 if (r) 5155 return r; 5156 5157 gfx_v10_0_init_csb(adev); 5158 5159 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5160 5161 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5162 gfx_v10_0_rlc_enable_srm(adev); 5163 } else { 5164 if (amdgpu_sriov_vf(adev)) { 5165 gfx_v10_0_init_csb(adev); 5166 return 0; 5167 } 5168 5169 adev->gfx.rlc.funcs->stop(adev); 5170 5171 /* disable CG */ 5172 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5173 5174 /* disable PG */ 5175 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5176 5177 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5178 /* legacy rlc firmware loading */ 5179 r = gfx_v10_0_rlc_load_microcode(adev); 5180 if (r) 5181 return r; 5182 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5183 /* rlc backdoor autoload firmware */ 5184 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5185 if (r) 5186 return r; 5187 } 5188 5189 gfx_v10_0_init_csb(adev); 5190 5191 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5192 5193 adev->gfx.rlc.funcs->start(adev); 5194 5195 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5196 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5197 if (r) 5198 return r; 5199 } 5200 } 5201 5202 return 0; 5203 } 5204 5205 static struct { 5206 FIRMWARE_ID id; 5207 unsigned int offset; 5208 unsigned int size; 5209 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5210 5211 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5212 { 5213 int ret; 5214 RLC_TABLE_OF_CONTENT *rlc_toc; 5215 5216 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5217 AMDGPU_GEM_DOMAIN_GTT, 5218 &adev->gfx.rlc.rlc_toc_bo, 5219 &adev->gfx.rlc.rlc_toc_gpu_addr, 5220 (void **)&adev->gfx.rlc.rlc_toc_buf); 5221 if (ret) { 5222 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5223 return ret; 5224 } 5225 5226 /* Copy toc from psp sos fw to rlc toc buffer */ 5227 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5228 5229 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5230 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5231 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5232 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5233 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5234 /* Offset needs 4KB alignment */ 5235 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5236 } 5237 5238 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5239 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5240 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5241 5242 rlc_toc++; 5243 } 5244 5245 return 0; 5246 } 5247 5248 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5249 { 5250 uint32_t total_size = 0; 5251 FIRMWARE_ID id; 5252 int ret; 5253 5254 ret = gfx_v10_0_parse_rlc_toc(adev); 5255 if (ret) { 5256 dev_err(adev->dev, "failed to parse rlc toc\n"); 5257 return 0; 5258 } 5259 5260 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5261 total_size += rlc_autoload_info[id].size; 5262 5263 /* In case the offset in rlc toc ucode is aligned */ 5264 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5265 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5266 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5267 5268 return total_size; 5269 } 5270 5271 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5272 { 5273 int r; 5274 uint32_t total_size; 5275 5276 total_size = gfx_v10_0_calc_toc_total_size(adev); 5277 5278 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5279 AMDGPU_GEM_DOMAIN_GTT, 5280 &adev->gfx.rlc.rlc_autoload_bo, 5281 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5282 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5283 if (r) { 5284 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5285 return r; 5286 } 5287 5288 return 0; 5289 } 5290 5291 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5292 { 5293 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5294 &adev->gfx.rlc.rlc_toc_gpu_addr, 5295 (void **)&adev->gfx.rlc.rlc_toc_buf); 5296 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5297 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5298 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5299 } 5300 5301 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5302 FIRMWARE_ID id, 5303 const void *fw_data, 5304 uint32_t fw_size) 5305 { 5306 uint32_t toc_offset; 5307 uint32_t toc_fw_size; 5308 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5309 5310 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5311 return; 5312 5313 toc_offset = rlc_autoload_info[id].offset; 5314 toc_fw_size = rlc_autoload_info[id].size; 5315 5316 if (fw_size == 0) 5317 fw_size = toc_fw_size; 5318 5319 if (fw_size > toc_fw_size) 5320 fw_size = toc_fw_size; 5321 5322 memcpy(ptr + toc_offset, fw_data, fw_size); 5323 5324 if (fw_size < toc_fw_size) 5325 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5326 } 5327 5328 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5329 { 5330 void *data; 5331 uint32_t size; 5332 5333 data = adev->gfx.rlc.rlc_toc_buf; 5334 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5335 5336 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5337 FIRMWARE_ID_RLC_TOC, 5338 data, size); 5339 } 5340 5341 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5342 { 5343 const __le32 *fw_data; 5344 uint32_t fw_size; 5345 const struct gfx_firmware_header_v1_0 *cp_hdr; 5346 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5347 5348 /* pfp ucode */ 5349 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5350 adev->gfx.pfp_fw->data; 5351 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5352 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5353 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5354 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5355 FIRMWARE_ID_CP_PFP, 5356 fw_data, fw_size); 5357 5358 /* ce ucode */ 5359 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5360 adev->gfx.ce_fw->data; 5361 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5362 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5363 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5364 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5365 FIRMWARE_ID_CP_CE, 5366 fw_data, fw_size); 5367 5368 /* me ucode */ 5369 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5370 adev->gfx.me_fw->data; 5371 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5372 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5373 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5374 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5375 FIRMWARE_ID_CP_ME, 5376 fw_data, fw_size); 5377 5378 /* rlc ucode */ 5379 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5380 adev->gfx.rlc_fw->data; 5381 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5382 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5383 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5384 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5385 FIRMWARE_ID_RLC_G_UCODE, 5386 fw_data, fw_size); 5387 5388 /* mec1 ucode */ 5389 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5390 adev->gfx.mec_fw->data; 5391 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5392 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5393 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5394 cp_hdr->jt_size * 4; 5395 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5396 FIRMWARE_ID_CP_MEC, 5397 fw_data, fw_size); 5398 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5399 } 5400 5401 /* Temporarily put sdma part here */ 5402 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5403 { 5404 const __le32 *fw_data; 5405 uint32_t fw_size; 5406 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5407 int i; 5408 5409 for (i = 0; i < adev->sdma.num_instances; i++) { 5410 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5411 adev->sdma.instance[i].fw->data; 5412 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5413 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5414 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5415 5416 if (i == 0) { 5417 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5418 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5419 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5420 FIRMWARE_ID_SDMA0_JT, 5421 (uint32_t *)fw_data + 5422 sdma_hdr->jt_offset, 5423 sdma_hdr->jt_size * 4); 5424 } else if (i == 1) { 5425 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5426 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5427 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5428 FIRMWARE_ID_SDMA1_JT, 5429 (uint32_t *)fw_data + 5430 sdma_hdr->jt_offset, 5431 sdma_hdr->jt_size * 4); 5432 } 5433 } 5434 } 5435 5436 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5437 { 5438 uint32_t rlc_g_offset, rlc_g_size, tmp; 5439 uint64_t gpu_addr; 5440 5441 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5442 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5443 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5444 5445 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5446 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5447 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5448 5449 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5450 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5451 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5452 5453 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5454 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5455 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5456 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5457 return -EINVAL; 5458 } 5459 5460 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5461 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5462 DRM_ERROR("RLC ROM should halt itself\n"); 5463 return -EINVAL; 5464 } 5465 5466 return 0; 5467 } 5468 5469 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5470 { 5471 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5472 uint32_t tmp; 5473 int i; 5474 uint64_t addr; 5475 5476 /* Trigger an invalidation of the L1 instruction caches */ 5477 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5478 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5479 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5480 5481 /* Wait for invalidation complete */ 5482 for (i = 0; i < usec_timeout; i++) { 5483 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5484 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5485 INVALIDATE_CACHE_COMPLETE)) 5486 break; 5487 udelay(1); 5488 } 5489 5490 if (i >= usec_timeout) { 5491 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5492 return -EINVAL; 5493 } 5494 5495 /* Program me ucode address into intruction cache address register */ 5496 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5497 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5498 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5499 lower_32_bits(addr) & 0xFFFFF000); 5500 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5501 upper_32_bits(addr)); 5502 5503 return 0; 5504 } 5505 5506 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5507 { 5508 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5509 uint32_t tmp; 5510 int i; 5511 uint64_t addr; 5512 5513 /* Trigger an invalidation of the L1 instruction caches */ 5514 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5515 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5516 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5517 5518 /* Wait for invalidation complete */ 5519 for (i = 0; i < usec_timeout; i++) { 5520 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5521 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5522 INVALIDATE_CACHE_COMPLETE)) 5523 break; 5524 udelay(1); 5525 } 5526 5527 if (i >= usec_timeout) { 5528 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5529 return -EINVAL; 5530 } 5531 5532 /* Program ce ucode address into intruction cache address register */ 5533 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5534 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5535 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5536 lower_32_bits(addr) & 0xFFFFF000); 5537 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5538 upper_32_bits(addr)); 5539 5540 return 0; 5541 } 5542 5543 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5544 { 5545 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5546 uint32_t tmp; 5547 int i; 5548 uint64_t addr; 5549 5550 /* Trigger an invalidation of the L1 instruction caches */ 5551 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5552 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5553 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5554 5555 /* Wait for invalidation complete */ 5556 for (i = 0; i < usec_timeout; i++) { 5557 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5558 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5559 INVALIDATE_CACHE_COMPLETE)) 5560 break; 5561 udelay(1); 5562 } 5563 5564 if (i >= usec_timeout) { 5565 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5566 return -EINVAL; 5567 } 5568 5569 /* Program pfp ucode address into intruction cache address register */ 5570 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5571 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5572 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5573 lower_32_bits(addr) & 0xFFFFF000); 5574 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5575 upper_32_bits(addr)); 5576 5577 return 0; 5578 } 5579 5580 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5581 { 5582 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5583 uint32_t tmp; 5584 int i; 5585 uint64_t addr; 5586 5587 /* Trigger an invalidation of the L1 instruction caches */ 5588 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5589 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5590 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5591 5592 /* Wait for invalidation complete */ 5593 for (i = 0; i < usec_timeout; i++) { 5594 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5595 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5596 INVALIDATE_CACHE_COMPLETE)) 5597 break; 5598 udelay(1); 5599 } 5600 5601 if (i >= usec_timeout) { 5602 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5603 return -EINVAL; 5604 } 5605 5606 /* Program mec1 ucode address into intruction cache address register */ 5607 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5608 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5609 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5610 lower_32_bits(addr) & 0xFFFFF000); 5611 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5612 upper_32_bits(addr)); 5613 5614 return 0; 5615 } 5616 5617 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5618 { 5619 uint32_t cp_status; 5620 uint32_t bootload_status; 5621 int i, r; 5622 5623 for (i = 0; i < adev->usec_timeout; i++) { 5624 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5625 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5626 if ((cp_status == 0) && 5627 (REG_GET_FIELD(bootload_status, 5628 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5629 break; 5630 } 5631 udelay(1); 5632 } 5633 5634 if (i >= adev->usec_timeout) { 5635 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5636 return -ETIMEDOUT; 5637 } 5638 5639 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5640 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5641 if (r) 5642 return r; 5643 5644 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5645 if (r) 5646 return r; 5647 5648 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5649 if (r) 5650 return r; 5651 5652 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5653 if (r) 5654 return r; 5655 } 5656 5657 return 0; 5658 } 5659 5660 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5661 { 5662 int i; 5663 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5664 5665 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5666 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5667 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5668 5669 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 5670 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5671 else 5672 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5673 5674 if (adev->job_hang && !enable) 5675 return 0; 5676 5677 for (i = 0; i < adev->usec_timeout; i++) { 5678 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5679 break; 5680 udelay(1); 5681 } 5682 5683 if (i >= adev->usec_timeout) 5684 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5685 5686 return 0; 5687 } 5688 5689 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5690 { 5691 int r; 5692 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5693 const __le32 *fw_data; 5694 unsigned int i, fw_size; 5695 uint32_t tmp; 5696 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5697 5698 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5699 adev->gfx.pfp_fw->data; 5700 5701 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5702 5703 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5704 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5705 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5706 5707 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5708 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5709 &adev->gfx.pfp.pfp_fw_obj, 5710 &adev->gfx.pfp.pfp_fw_gpu_addr, 5711 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5712 if (r) { 5713 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5714 gfx_v10_0_pfp_fini(adev); 5715 return r; 5716 } 5717 5718 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5719 5720 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5721 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5722 5723 /* Trigger an invalidation of the L1 instruction caches */ 5724 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5725 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5726 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5727 5728 /* Wait for invalidation complete */ 5729 for (i = 0; i < usec_timeout; i++) { 5730 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5731 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5732 INVALIDATE_CACHE_COMPLETE)) 5733 break; 5734 udelay(1); 5735 } 5736 5737 if (i >= usec_timeout) { 5738 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5739 return -EINVAL; 5740 } 5741 5742 if (amdgpu_emu_mode == 1) 5743 adev->hdp.funcs->flush_hdp(adev, NULL); 5744 5745 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5746 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5747 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5748 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5749 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5750 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5751 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5752 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5753 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5754 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5755 5756 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5757 5758 for (i = 0; i < pfp_hdr->jt_size; i++) 5759 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5760 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5761 5762 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5763 5764 return 0; 5765 } 5766 5767 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5768 { 5769 int r; 5770 const struct gfx_firmware_header_v1_0 *ce_hdr; 5771 const __le32 *fw_data; 5772 unsigned int i, fw_size; 5773 uint32_t tmp; 5774 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5775 5776 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5777 adev->gfx.ce_fw->data; 5778 5779 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5780 5781 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5782 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5783 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5784 5785 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5786 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5787 &adev->gfx.ce.ce_fw_obj, 5788 &adev->gfx.ce.ce_fw_gpu_addr, 5789 (void **)&adev->gfx.ce.ce_fw_ptr); 5790 if (r) { 5791 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5792 gfx_v10_0_ce_fini(adev); 5793 return r; 5794 } 5795 5796 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5797 5798 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5799 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5800 5801 /* Trigger an invalidation of the L1 instruction caches */ 5802 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5803 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5804 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5805 5806 /* Wait for invalidation complete */ 5807 for (i = 0; i < usec_timeout; i++) { 5808 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5809 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5810 INVALIDATE_CACHE_COMPLETE)) 5811 break; 5812 udelay(1); 5813 } 5814 5815 if (i >= usec_timeout) { 5816 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5817 return -EINVAL; 5818 } 5819 5820 if (amdgpu_emu_mode == 1) 5821 adev->hdp.funcs->flush_hdp(adev, NULL); 5822 5823 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5824 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5825 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5826 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5827 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5828 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5829 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5830 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5831 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5832 5833 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5834 5835 for (i = 0; i < ce_hdr->jt_size; i++) 5836 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5837 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5838 5839 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5840 5841 return 0; 5842 } 5843 5844 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5845 { 5846 int r; 5847 const struct gfx_firmware_header_v1_0 *me_hdr; 5848 const __le32 *fw_data; 5849 unsigned int i, fw_size; 5850 uint32_t tmp; 5851 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5852 5853 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5854 adev->gfx.me_fw->data; 5855 5856 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5857 5858 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5859 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5860 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5861 5862 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5863 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5864 &adev->gfx.me.me_fw_obj, 5865 &adev->gfx.me.me_fw_gpu_addr, 5866 (void **)&adev->gfx.me.me_fw_ptr); 5867 if (r) { 5868 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5869 gfx_v10_0_me_fini(adev); 5870 return r; 5871 } 5872 5873 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5874 5875 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5876 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5877 5878 /* Trigger an invalidation of the L1 instruction caches */ 5879 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5880 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5881 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5882 5883 /* Wait for invalidation complete */ 5884 for (i = 0; i < usec_timeout; i++) { 5885 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5886 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5887 INVALIDATE_CACHE_COMPLETE)) 5888 break; 5889 udelay(1); 5890 } 5891 5892 if (i >= usec_timeout) { 5893 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5894 return -EINVAL; 5895 } 5896 5897 if (amdgpu_emu_mode == 1) 5898 adev->hdp.funcs->flush_hdp(adev, NULL); 5899 5900 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5901 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5902 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5903 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5904 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5905 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5906 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5907 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5908 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5909 5910 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5911 5912 for (i = 0; i < me_hdr->jt_size; i++) 5913 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5914 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5915 5916 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5917 5918 return 0; 5919 } 5920 5921 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5922 { 5923 int r; 5924 5925 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5926 return -EINVAL; 5927 5928 gfx_v10_0_cp_gfx_enable(adev, false); 5929 5930 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5931 if (r) { 5932 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5933 return r; 5934 } 5935 5936 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5937 if (r) { 5938 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5939 return r; 5940 } 5941 5942 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5943 if (r) { 5944 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5945 return r; 5946 } 5947 5948 return 0; 5949 } 5950 5951 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5952 { 5953 struct amdgpu_ring *ring; 5954 const struct cs_section_def *sect = NULL; 5955 const struct cs_extent_def *ext = NULL; 5956 int r, i; 5957 int ctx_reg_offset; 5958 5959 /* init the CP */ 5960 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5961 adev->gfx.config.max_hw_contexts - 1); 5962 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5963 5964 gfx_v10_0_cp_gfx_enable(adev, true); 5965 5966 ring = &adev->gfx.gfx_ring[0]; 5967 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5968 if (r) { 5969 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5970 return r; 5971 } 5972 5973 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5974 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5975 5976 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5977 amdgpu_ring_write(ring, 0x80000000); 5978 amdgpu_ring_write(ring, 0x80000000); 5979 5980 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5981 for (ext = sect->section; ext->extent != NULL; ++ext) { 5982 if (sect->id == SECT_CONTEXT) { 5983 amdgpu_ring_write(ring, 5984 PACKET3(PACKET3_SET_CONTEXT_REG, 5985 ext->reg_count)); 5986 amdgpu_ring_write(ring, ext->reg_index - 5987 PACKET3_SET_CONTEXT_REG_START); 5988 for (i = 0; i < ext->reg_count; i++) 5989 amdgpu_ring_write(ring, ext->extent[i]); 5990 } 5991 } 5992 } 5993 5994 ctx_reg_offset = 5995 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5996 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5997 amdgpu_ring_write(ring, ctx_reg_offset); 5998 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5999 6000 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6001 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6002 6003 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6004 amdgpu_ring_write(ring, 0); 6005 6006 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6007 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6008 amdgpu_ring_write(ring, 0x8000); 6009 amdgpu_ring_write(ring, 0x8000); 6010 6011 amdgpu_ring_commit(ring); 6012 6013 /* submit cs packet to copy state 0 to next available state */ 6014 if (adev->gfx.num_gfx_rings > 1) { 6015 /* maximum supported gfx ring is 2 */ 6016 ring = &adev->gfx.gfx_ring[1]; 6017 r = amdgpu_ring_alloc(ring, 2); 6018 if (r) { 6019 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6020 return r; 6021 } 6022 6023 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6024 amdgpu_ring_write(ring, 0); 6025 6026 amdgpu_ring_commit(ring); 6027 } 6028 return 0; 6029 } 6030 6031 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6032 CP_PIPE_ID pipe) 6033 { 6034 u32 tmp; 6035 6036 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6037 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6038 6039 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6040 } 6041 6042 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6043 struct amdgpu_ring *ring) 6044 { 6045 u32 tmp; 6046 6047 if (!amdgpu_async_gfx_ring) { 6048 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6049 if (ring->use_doorbell) { 6050 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6051 DOORBELL_OFFSET, ring->doorbell_index); 6052 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6053 DOORBELL_EN, 1); 6054 } else { 6055 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6056 DOORBELL_EN, 0); 6057 } 6058 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6059 } 6060 switch (adev->ip_versions[GC_HWIP][0]) { 6061 case IP_VERSION(10, 3, 0): 6062 case IP_VERSION(10, 3, 2): 6063 case IP_VERSION(10, 3, 1): 6064 case IP_VERSION(10, 3, 4): 6065 case IP_VERSION(10, 3, 5): 6066 case IP_VERSION(10, 3, 6): 6067 case IP_VERSION(10, 3, 3): 6068 case IP_VERSION(10, 3, 7): 6069 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6070 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6071 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6072 6073 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6074 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6075 break; 6076 default: 6077 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6078 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6079 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6080 6081 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6082 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6083 break; 6084 } 6085 } 6086 6087 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6088 { 6089 struct amdgpu_ring *ring; 6090 u32 tmp; 6091 u32 rb_bufsz; 6092 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6093 6094 /* Set the write pointer delay */ 6095 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6096 6097 /* set the RB to use vmid 0 */ 6098 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6099 6100 /* Init gfx ring 0 for pipe 0 */ 6101 mutex_lock(&adev->srbm_mutex); 6102 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6103 6104 /* Set ring buffer size */ 6105 ring = &adev->gfx.gfx_ring[0]; 6106 rb_bufsz = order_base_2(ring->ring_size / 8); 6107 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6108 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6109 #ifdef __BIG_ENDIAN 6110 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6111 #endif 6112 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6113 6114 /* Initialize the ring buffer's write pointers */ 6115 ring->wptr = 0; 6116 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6117 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6118 6119 /* set the wb address wether it's enabled or not */ 6120 rptr_addr = ring->rptr_gpu_addr; 6121 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6122 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6123 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6124 6125 wptr_gpu_addr = ring->wptr_gpu_addr; 6126 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6127 lower_32_bits(wptr_gpu_addr)); 6128 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6129 upper_32_bits(wptr_gpu_addr)); 6130 6131 mdelay(1); 6132 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6133 6134 rb_addr = ring->gpu_addr >> 8; 6135 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6136 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6137 6138 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6139 6140 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6141 mutex_unlock(&adev->srbm_mutex); 6142 6143 /* Init gfx ring 1 for pipe 1 */ 6144 if (adev->gfx.num_gfx_rings > 1) { 6145 mutex_lock(&adev->srbm_mutex); 6146 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6147 /* maximum supported gfx ring is 2 */ 6148 ring = &adev->gfx.gfx_ring[1]; 6149 rb_bufsz = order_base_2(ring->ring_size / 8); 6150 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6151 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6152 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6153 /* Initialize the ring buffer's write pointers */ 6154 ring->wptr = 0; 6155 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6156 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6157 /* Set the wb address wether it's enabled or not */ 6158 rptr_addr = ring->rptr_gpu_addr; 6159 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6160 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6161 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6162 wptr_gpu_addr = ring->wptr_gpu_addr; 6163 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6164 lower_32_bits(wptr_gpu_addr)); 6165 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6166 upper_32_bits(wptr_gpu_addr)); 6167 6168 mdelay(1); 6169 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6170 6171 rb_addr = ring->gpu_addr >> 8; 6172 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6173 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6174 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6175 6176 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6177 mutex_unlock(&adev->srbm_mutex); 6178 } 6179 /* Switch to pipe 0 */ 6180 mutex_lock(&adev->srbm_mutex); 6181 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6182 mutex_unlock(&adev->srbm_mutex); 6183 6184 /* start the ring */ 6185 gfx_v10_0_cp_gfx_start(adev); 6186 6187 return 0; 6188 } 6189 6190 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6191 { 6192 if (enable) { 6193 switch (adev->ip_versions[GC_HWIP][0]) { 6194 case IP_VERSION(10, 3, 0): 6195 case IP_VERSION(10, 3, 2): 6196 case IP_VERSION(10, 3, 1): 6197 case IP_VERSION(10, 3, 4): 6198 case IP_VERSION(10, 3, 5): 6199 case IP_VERSION(10, 3, 6): 6200 case IP_VERSION(10, 3, 3): 6201 case IP_VERSION(10, 3, 7): 6202 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6203 break; 6204 default: 6205 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6206 break; 6207 } 6208 } else { 6209 switch (adev->ip_versions[GC_HWIP][0]) { 6210 case IP_VERSION(10, 3, 0): 6211 case IP_VERSION(10, 3, 2): 6212 case IP_VERSION(10, 3, 1): 6213 case IP_VERSION(10, 3, 4): 6214 case IP_VERSION(10, 3, 5): 6215 case IP_VERSION(10, 3, 6): 6216 case IP_VERSION(10, 3, 3): 6217 case IP_VERSION(10, 3, 7): 6218 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6219 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6220 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6221 break; 6222 default: 6223 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6224 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6225 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6226 break; 6227 } 6228 adev->gfx.kiq[0].ring.sched.ready = false; 6229 } 6230 udelay(50); 6231 } 6232 6233 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6234 { 6235 const struct gfx_firmware_header_v1_0 *mec_hdr; 6236 const __le32 *fw_data; 6237 unsigned int i; 6238 u32 tmp; 6239 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6240 6241 if (!adev->gfx.mec_fw) 6242 return -EINVAL; 6243 6244 gfx_v10_0_cp_compute_enable(adev, false); 6245 6246 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6247 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6248 6249 fw_data = (const __le32 *) 6250 (adev->gfx.mec_fw->data + 6251 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6252 6253 /* Trigger an invalidation of the L1 instruction caches */ 6254 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6255 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6256 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6257 6258 /* Wait for invalidation complete */ 6259 for (i = 0; i < usec_timeout; i++) { 6260 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6261 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6262 INVALIDATE_CACHE_COMPLETE)) 6263 break; 6264 udelay(1); 6265 } 6266 6267 if (i >= usec_timeout) { 6268 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6269 return -EINVAL; 6270 } 6271 6272 if (amdgpu_emu_mode == 1) 6273 adev->hdp.funcs->flush_hdp(adev, NULL); 6274 6275 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6276 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6277 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6278 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6279 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6280 6281 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6282 0xFFFFF000); 6283 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6284 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6285 6286 /* MEC1 */ 6287 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6288 6289 for (i = 0; i < mec_hdr->jt_size; i++) 6290 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6291 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6292 6293 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6294 6295 /* 6296 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6297 * different microcode than MEC1. 6298 */ 6299 6300 return 0; 6301 } 6302 6303 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6304 { 6305 uint32_t tmp; 6306 struct amdgpu_device *adev = ring->adev; 6307 6308 /* tell RLC which is KIQ queue */ 6309 switch (adev->ip_versions[GC_HWIP][0]) { 6310 case IP_VERSION(10, 3, 0): 6311 case IP_VERSION(10, 3, 2): 6312 case IP_VERSION(10, 3, 1): 6313 case IP_VERSION(10, 3, 4): 6314 case IP_VERSION(10, 3, 5): 6315 case IP_VERSION(10, 3, 6): 6316 case IP_VERSION(10, 3, 3): 6317 case IP_VERSION(10, 3, 7): 6318 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6319 tmp &= 0xffffff00; 6320 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6321 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6322 tmp |= 0x80; 6323 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6324 break; 6325 default: 6326 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6327 tmp &= 0xffffff00; 6328 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6329 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6330 tmp |= 0x80; 6331 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6332 break; 6333 } 6334 } 6335 6336 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6337 struct v10_gfx_mqd *mqd, 6338 struct amdgpu_mqd_prop *prop) 6339 { 6340 bool priority = 0; 6341 u32 tmp; 6342 6343 /* set up default queue priority level 6344 * 0x0 = low priority, 0x1 = high priority 6345 */ 6346 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6347 priority = 1; 6348 6349 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6350 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6351 mqd->cp_gfx_hqd_queue_priority = tmp; 6352 } 6353 6354 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6355 struct amdgpu_mqd_prop *prop) 6356 { 6357 struct v10_gfx_mqd *mqd = m; 6358 uint64_t hqd_gpu_addr, wb_gpu_addr; 6359 uint32_t tmp; 6360 uint32_t rb_bufsz; 6361 6362 /* set up gfx hqd wptr */ 6363 mqd->cp_gfx_hqd_wptr = 0; 6364 mqd->cp_gfx_hqd_wptr_hi = 0; 6365 6366 /* set the pointer to the MQD */ 6367 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6368 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6369 6370 /* set up mqd control */ 6371 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6372 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6373 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6374 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6375 mqd->cp_gfx_mqd_control = tmp; 6376 6377 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6378 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6379 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6380 mqd->cp_gfx_hqd_vmid = 0; 6381 6382 /* set up gfx queue priority */ 6383 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6384 6385 /* set up time quantum */ 6386 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6387 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6388 mqd->cp_gfx_hqd_quantum = tmp; 6389 6390 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6391 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6392 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6393 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6394 6395 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6396 wb_gpu_addr = prop->rptr_gpu_addr; 6397 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6398 mqd->cp_gfx_hqd_rptr_addr_hi = 6399 upper_32_bits(wb_gpu_addr) & 0xffff; 6400 6401 /* set up rb_wptr_poll addr */ 6402 wb_gpu_addr = prop->wptr_gpu_addr; 6403 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6404 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6405 6406 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6407 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6408 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6409 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6410 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6411 #ifdef __BIG_ENDIAN 6412 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6413 #endif 6414 mqd->cp_gfx_hqd_cntl = tmp; 6415 6416 /* set up cp_doorbell_control */ 6417 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6418 if (prop->use_doorbell) { 6419 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6420 DOORBELL_OFFSET, prop->doorbell_index); 6421 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6422 DOORBELL_EN, 1); 6423 } else 6424 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6425 DOORBELL_EN, 0); 6426 mqd->cp_rb_doorbell_control = tmp; 6427 6428 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6429 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6430 6431 /* active the queue */ 6432 mqd->cp_gfx_hqd_active = 1; 6433 6434 return 0; 6435 } 6436 6437 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6438 { 6439 struct amdgpu_device *adev = ring->adev; 6440 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6441 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6442 6443 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6444 memset((void *)mqd, 0, sizeof(*mqd)); 6445 mutex_lock(&adev->srbm_mutex); 6446 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6447 amdgpu_ring_init_mqd(ring); 6448 6449 /* 6450 * if there are 2 gfx rings, set the lower doorbell 6451 * range of the first ring, otherwise the range of 6452 * the second ring will override the first ring 6453 */ 6454 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6455 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6456 6457 nv_grbm_select(adev, 0, 0, 0, 0); 6458 mutex_unlock(&adev->srbm_mutex); 6459 if (adev->gfx.me.mqd_backup[mqd_idx]) 6460 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6461 } else { 6462 /* restore mqd with the backup copy */ 6463 if (adev->gfx.me.mqd_backup[mqd_idx]) 6464 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6465 /* reset the ring */ 6466 ring->wptr = 0; 6467 *ring->wptr_cpu_addr = 0; 6468 amdgpu_ring_clear_ring(ring); 6469 } 6470 6471 return 0; 6472 } 6473 6474 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6475 { 6476 int r, i; 6477 struct amdgpu_ring *ring; 6478 6479 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6480 ring = &adev->gfx.gfx_ring[i]; 6481 6482 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6483 if (unlikely(r != 0)) 6484 return r; 6485 6486 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6487 if (!r) { 6488 r = gfx_v10_0_gfx_init_queue(ring); 6489 amdgpu_bo_kunmap(ring->mqd_obj); 6490 ring->mqd_ptr = NULL; 6491 } 6492 amdgpu_bo_unreserve(ring->mqd_obj); 6493 if (r) 6494 return r; 6495 } 6496 6497 r = amdgpu_gfx_enable_kgq(adev, 0); 6498 if (r) 6499 return r; 6500 6501 return gfx_v10_0_cp_gfx_start(adev); 6502 } 6503 6504 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6505 struct amdgpu_mqd_prop *prop) 6506 { 6507 struct v10_compute_mqd *mqd = m; 6508 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6509 uint32_t tmp; 6510 6511 mqd->header = 0xC0310800; 6512 mqd->compute_pipelinestat_enable = 0x00000001; 6513 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6514 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6515 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6516 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6517 mqd->compute_misc_reserved = 0x00000003; 6518 6519 eop_base_addr = prop->eop_gpu_addr >> 8; 6520 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6521 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6522 6523 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6524 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6525 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6526 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6527 6528 mqd->cp_hqd_eop_control = tmp; 6529 6530 /* enable doorbell? */ 6531 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6532 6533 if (prop->use_doorbell) { 6534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6535 DOORBELL_OFFSET, prop->doorbell_index); 6536 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6537 DOORBELL_EN, 1); 6538 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6539 DOORBELL_SOURCE, 0); 6540 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6541 DOORBELL_HIT, 0); 6542 } else { 6543 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6544 DOORBELL_EN, 0); 6545 } 6546 6547 mqd->cp_hqd_pq_doorbell_control = tmp; 6548 6549 /* disable the queue if it's active */ 6550 mqd->cp_hqd_dequeue_request = 0; 6551 mqd->cp_hqd_pq_rptr = 0; 6552 mqd->cp_hqd_pq_wptr_lo = 0; 6553 mqd->cp_hqd_pq_wptr_hi = 0; 6554 6555 /* set the pointer to the MQD */ 6556 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6557 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6558 6559 /* set MQD vmid to 0 */ 6560 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6561 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6562 mqd->cp_mqd_control = tmp; 6563 6564 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6565 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6566 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6567 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6568 6569 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6570 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6571 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6572 (order_base_2(prop->queue_size / 4) - 1)); 6573 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6574 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6575 #ifdef __BIG_ENDIAN 6576 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6577 #endif 6578 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6579 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6580 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6581 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6582 mqd->cp_hqd_pq_control = tmp; 6583 6584 /* set the wb address whether it's enabled or not */ 6585 wb_gpu_addr = prop->rptr_gpu_addr; 6586 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6587 mqd->cp_hqd_pq_rptr_report_addr_hi = 6588 upper_32_bits(wb_gpu_addr) & 0xffff; 6589 6590 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6591 wb_gpu_addr = prop->wptr_gpu_addr; 6592 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6593 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6594 6595 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6596 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6597 6598 /* set the vmid for the queue */ 6599 mqd->cp_hqd_vmid = 0; 6600 6601 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6602 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6603 mqd->cp_hqd_persistent_state = tmp; 6604 6605 /* set MIN_IB_AVAIL_SIZE */ 6606 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6607 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6608 mqd->cp_hqd_ib_control = tmp; 6609 6610 /* set static priority for a compute queue/ring */ 6611 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6612 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6613 6614 mqd->cp_hqd_active = prop->hqd_active; 6615 6616 return 0; 6617 } 6618 6619 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6620 { 6621 struct amdgpu_device *adev = ring->adev; 6622 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6623 int j; 6624 6625 /* inactivate the queue */ 6626 if (amdgpu_sriov_vf(adev)) 6627 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6628 6629 /* disable wptr polling */ 6630 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6631 6632 /* disable the queue if it's active */ 6633 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6634 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6635 for (j = 0; j < adev->usec_timeout; j++) { 6636 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6637 break; 6638 udelay(1); 6639 } 6640 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6641 mqd->cp_hqd_dequeue_request); 6642 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6643 mqd->cp_hqd_pq_rptr); 6644 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6645 mqd->cp_hqd_pq_wptr_lo); 6646 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6647 mqd->cp_hqd_pq_wptr_hi); 6648 } 6649 6650 /* disable doorbells */ 6651 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6652 6653 /* write the EOP addr */ 6654 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6655 mqd->cp_hqd_eop_base_addr_lo); 6656 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6657 mqd->cp_hqd_eop_base_addr_hi); 6658 6659 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6660 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6661 mqd->cp_hqd_eop_control); 6662 6663 /* set the pointer to the MQD */ 6664 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6665 mqd->cp_mqd_base_addr_lo); 6666 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6667 mqd->cp_mqd_base_addr_hi); 6668 6669 /* set MQD vmid to 0 */ 6670 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6671 mqd->cp_mqd_control); 6672 6673 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6674 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6675 mqd->cp_hqd_pq_base_lo); 6676 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6677 mqd->cp_hqd_pq_base_hi); 6678 6679 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6680 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6681 mqd->cp_hqd_pq_control); 6682 6683 /* set the wb address whether it's enabled or not */ 6684 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6685 mqd->cp_hqd_pq_rptr_report_addr_lo); 6686 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6687 mqd->cp_hqd_pq_rptr_report_addr_hi); 6688 6689 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6690 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6691 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6692 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6693 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6694 6695 /* enable the doorbell if requested */ 6696 if (ring->use_doorbell) { 6697 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6698 (adev->doorbell_index.kiq * 2) << 2); 6699 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6700 (adev->doorbell_index.userqueue_end * 2) << 2); 6701 } 6702 6703 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6704 mqd->cp_hqd_pq_doorbell_control); 6705 6706 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6707 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6708 mqd->cp_hqd_pq_wptr_lo); 6709 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6710 mqd->cp_hqd_pq_wptr_hi); 6711 6712 /* set the vmid for the queue */ 6713 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6714 6715 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6716 mqd->cp_hqd_persistent_state); 6717 6718 /* activate the queue */ 6719 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6720 mqd->cp_hqd_active); 6721 6722 if (ring->use_doorbell) 6723 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6724 6725 return 0; 6726 } 6727 6728 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6729 { 6730 struct amdgpu_device *adev = ring->adev; 6731 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6732 6733 gfx_v10_0_kiq_setting(ring); 6734 6735 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6736 /* reset MQD to a clean status */ 6737 if (adev->gfx.kiq[0].mqd_backup) 6738 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 6739 6740 /* reset ring buffer */ 6741 ring->wptr = 0; 6742 amdgpu_ring_clear_ring(ring); 6743 6744 mutex_lock(&adev->srbm_mutex); 6745 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6746 gfx_v10_0_kiq_init_register(ring); 6747 nv_grbm_select(adev, 0, 0, 0, 0); 6748 mutex_unlock(&adev->srbm_mutex); 6749 } else { 6750 memset((void *)mqd, 0, sizeof(*mqd)); 6751 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 6752 amdgpu_ring_clear_ring(ring); 6753 mutex_lock(&adev->srbm_mutex); 6754 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6755 amdgpu_ring_init_mqd(ring); 6756 gfx_v10_0_kiq_init_register(ring); 6757 nv_grbm_select(adev, 0, 0, 0, 0); 6758 mutex_unlock(&adev->srbm_mutex); 6759 6760 if (adev->gfx.kiq[0].mqd_backup) 6761 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 6762 } 6763 6764 return 0; 6765 } 6766 6767 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6768 { 6769 struct amdgpu_device *adev = ring->adev; 6770 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6771 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6772 6773 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6774 memset((void *)mqd, 0, sizeof(*mqd)); 6775 mutex_lock(&adev->srbm_mutex); 6776 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6777 amdgpu_ring_init_mqd(ring); 6778 nv_grbm_select(adev, 0, 0, 0, 0); 6779 mutex_unlock(&adev->srbm_mutex); 6780 6781 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6782 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6783 } else { 6784 /* restore MQD to a clean status */ 6785 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6786 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6787 /* reset ring buffer */ 6788 ring->wptr = 0; 6789 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6790 amdgpu_ring_clear_ring(ring); 6791 } 6792 6793 return 0; 6794 } 6795 6796 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6797 { 6798 struct amdgpu_ring *ring; 6799 int r; 6800 6801 ring = &adev->gfx.kiq[0].ring; 6802 6803 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6804 if (unlikely(r != 0)) 6805 return r; 6806 6807 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6808 if (unlikely(r != 0)) { 6809 amdgpu_bo_unreserve(ring->mqd_obj); 6810 return r; 6811 } 6812 6813 gfx_v10_0_kiq_init_queue(ring); 6814 amdgpu_bo_kunmap(ring->mqd_obj); 6815 ring->mqd_ptr = NULL; 6816 amdgpu_bo_unreserve(ring->mqd_obj); 6817 return 0; 6818 } 6819 6820 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6821 { 6822 struct amdgpu_ring *ring = NULL; 6823 int r = 0, i; 6824 6825 gfx_v10_0_cp_compute_enable(adev, true); 6826 6827 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6828 ring = &adev->gfx.compute_ring[i]; 6829 6830 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6831 if (unlikely(r != 0)) 6832 goto done; 6833 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6834 if (!r) { 6835 r = gfx_v10_0_kcq_init_queue(ring); 6836 amdgpu_bo_kunmap(ring->mqd_obj); 6837 ring->mqd_ptr = NULL; 6838 } 6839 amdgpu_bo_unreserve(ring->mqd_obj); 6840 if (r) 6841 goto done; 6842 } 6843 6844 r = amdgpu_gfx_enable_kcq(adev, 0); 6845 done: 6846 return r; 6847 } 6848 6849 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6850 { 6851 int r, i; 6852 struct amdgpu_ring *ring; 6853 6854 if (!(adev->flags & AMD_IS_APU)) 6855 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6856 6857 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6858 /* legacy firmware loading */ 6859 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6860 if (r) 6861 return r; 6862 6863 r = gfx_v10_0_cp_compute_load_microcode(adev); 6864 if (r) 6865 return r; 6866 } 6867 6868 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 6869 r = amdgpu_mes_kiq_hw_init(adev); 6870 else 6871 r = gfx_v10_0_kiq_resume(adev); 6872 if (r) 6873 return r; 6874 6875 r = gfx_v10_0_kcq_resume(adev); 6876 if (r) 6877 return r; 6878 6879 if (!amdgpu_async_gfx_ring) { 6880 r = gfx_v10_0_cp_gfx_resume(adev); 6881 if (r) 6882 return r; 6883 } else { 6884 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6885 if (r) 6886 return r; 6887 } 6888 6889 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6890 ring = &adev->gfx.gfx_ring[i]; 6891 r = amdgpu_ring_test_helper(ring); 6892 if (r) 6893 return r; 6894 } 6895 6896 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6897 ring = &adev->gfx.compute_ring[i]; 6898 r = amdgpu_ring_test_helper(ring); 6899 if (r) 6900 return r; 6901 } 6902 6903 return 0; 6904 } 6905 6906 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6907 { 6908 gfx_v10_0_cp_gfx_enable(adev, enable); 6909 gfx_v10_0_cp_compute_enable(adev, enable); 6910 } 6911 6912 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6913 { 6914 uint32_t data, pattern = 0xDEADBEEF; 6915 6916 /* 6917 * check if mmVGT_ESGS_RING_SIZE_UMD 6918 * has been remapped to mmVGT_ESGS_RING_SIZE 6919 */ 6920 switch (adev->ip_versions[GC_HWIP][0]) { 6921 case IP_VERSION(10, 3, 0): 6922 case IP_VERSION(10, 3, 2): 6923 case IP_VERSION(10, 3, 4): 6924 case IP_VERSION(10, 3, 5): 6925 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6926 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6927 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6928 6929 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6930 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6931 return true; 6932 } 6933 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6934 break; 6935 case IP_VERSION(10, 3, 1): 6936 case IP_VERSION(10, 3, 3): 6937 case IP_VERSION(10, 3, 6): 6938 case IP_VERSION(10, 3, 7): 6939 return true; 6940 default: 6941 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6942 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 6943 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6944 6945 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 6946 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6947 return true; 6948 } 6949 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 6950 break; 6951 } 6952 6953 return false; 6954 } 6955 6956 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 6957 { 6958 uint32_t data; 6959 6960 if (amdgpu_sriov_vf(adev)) 6961 return; 6962 6963 /* 6964 * Initialize cam_index to 0 6965 * index will auto-inc after each data writing 6966 */ 6967 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 6968 6969 switch (adev->ip_versions[GC_HWIP][0]) { 6970 case IP_VERSION(10, 3, 0): 6971 case IP_VERSION(10, 3, 2): 6972 case IP_VERSION(10, 3, 1): 6973 case IP_VERSION(10, 3, 4): 6974 case IP_VERSION(10, 3, 5): 6975 case IP_VERSION(10, 3, 6): 6976 case IP_VERSION(10, 3, 3): 6977 case IP_VERSION(10, 3, 7): 6978 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 6979 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 6980 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6981 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 6982 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6983 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6984 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 6985 6986 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 6987 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 6988 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6989 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 6990 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6991 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6992 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 6993 6994 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 6995 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 6996 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6997 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 6998 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6999 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7000 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7001 7002 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7003 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7004 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7005 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7006 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7007 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7008 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7009 7010 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7011 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7012 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7013 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7014 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7015 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7016 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7017 7018 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7019 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7020 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7021 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7022 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7023 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7024 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7025 7026 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7027 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7028 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7029 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7030 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7031 break; 7032 default: 7033 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7034 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7035 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7036 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7037 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7038 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7039 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7040 7041 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7042 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7043 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7044 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7045 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7046 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7047 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7048 7049 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7050 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7051 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7052 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7053 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7054 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7055 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7056 7057 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7058 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7059 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7060 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7061 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7062 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7063 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7064 7065 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7066 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7067 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7068 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7069 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7070 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7071 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7072 7073 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7074 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7075 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7076 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7077 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7078 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7079 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7080 7081 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7082 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7083 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7084 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7085 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7086 break; 7087 } 7088 7089 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7090 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7091 } 7092 7093 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7094 { 7095 uint32_t data; 7096 7097 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7098 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7099 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7100 7101 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7102 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7103 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7104 } 7105 7106 static int gfx_v10_0_hw_init(void *handle) 7107 { 7108 int r; 7109 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7110 7111 if (!amdgpu_emu_mode) 7112 gfx_v10_0_init_golden_registers(adev); 7113 7114 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7115 /** 7116 * For gfx 10, rlc firmware loading relies on smu firmware is 7117 * loaded firstly, so in direct type, it has to load smc ucode 7118 * here before rlc. 7119 */ 7120 if (!(adev->flags & AMD_IS_APU)) { 7121 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7122 if (r) 7123 return r; 7124 } 7125 gfx_v10_0_disable_gpa_mode(adev); 7126 } 7127 7128 /* if GRBM CAM not remapped, set up the remapping */ 7129 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7130 gfx_v10_0_setup_grbm_cam_remapping(adev); 7131 7132 gfx_v10_0_constants_init(adev); 7133 7134 r = gfx_v10_0_rlc_resume(adev); 7135 if (r) 7136 return r; 7137 7138 /* 7139 * init golden registers and rlc resume may override some registers, 7140 * reconfig them here 7141 */ 7142 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) || 7143 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) || 7144 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 7145 gfx_v10_0_tcp_harvest(adev); 7146 7147 r = gfx_v10_0_cp_resume(adev); 7148 if (r) 7149 return r; 7150 7151 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 7152 gfx_v10_3_program_pbb_mode(adev); 7153 7154 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 7155 gfx_v10_3_set_power_brake_sequence(adev); 7156 7157 return r; 7158 } 7159 7160 static int gfx_v10_0_hw_fini(void *handle) 7161 { 7162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7163 7164 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7165 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7166 7167 if (!adev->no_hw_access) { 7168 if (amdgpu_async_gfx_ring) { 7169 if (amdgpu_gfx_disable_kgq(adev, 0)) 7170 DRM_ERROR("KGQ disable failed\n"); 7171 } 7172 7173 if (amdgpu_gfx_disable_kcq(adev, 0)) 7174 DRM_ERROR("KCQ disable failed\n"); 7175 } 7176 7177 if (amdgpu_sriov_vf(adev)) { 7178 gfx_v10_0_cp_gfx_enable(adev, false); 7179 /* Remove the steps of clearing KIQ position. 7180 * It causes GFX hang when another Win guest is rendering. 7181 */ 7182 return 0; 7183 } 7184 gfx_v10_0_cp_enable(adev, false); 7185 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7186 7187 return 0; 7188 } 7189 7190 static int gfx_v10_0_suspend(void *handle) 7191 { 7192 return gfx_v10_0_hw_fini(handle); 7193 } 7194 7195 static int gfx_v10_0_resume(void *handle) 7196 { 7197 return gfx_v10_0_hw_init(handle); 7198 } 7199 7200 static bool gfx_v10_0_is_idle(void *handle) 7201 { 7202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7203 7204 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7205 GRBM_STATUS, GUI_ACTIVE)) 7206 return false; 7207 else 7208 return true; 7209 } 7210 7211 static int gfx_v10_0_wait_for_idle(void *handle) 7212 { 7213 unsigned int i; 7214 u32 tmp; 7215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7216 7217 for (i = 0; i < adev->usec_timeout; i++) { 7218 /* read MC_STATUS */ 7219 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7220 GRBM_STATUS__GUI_ACTIVE_MASK; 7221 7222 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7223 return 0; 7224 udelay(1); 7225 } 7226 return -ETIMEDOUT; 7227 } 7228 7229 static int gfx_v10_0_soft_reset(void *handle) 7230 { 7231 u32 grbm_soft_reset = 0; 7232 u32 tmp; 7233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7234 7235 /* GRBM_STATUS */ 7236 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7237 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7238 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7239 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7240 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7241 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7242 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7243 GRBM_SOFT_RESET, SOFT_RESET_CP, 7244 1); 7245 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7246 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7247 1); 7248 } 7249 7250 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7251 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7252 GRBM_SOFT_RESET, SOFT_RESET_CP, 7253 1); 7254 } 7255 7256 /* GRBM_STATUS2 */ 7257 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7258 switch (adev->ip_versions[GC_HWIP][0]) { 7259 case IP_VERSION(10, 3, 0): 7260 case IP_VERSION(10, 3, 2): 7261 case IP_VERSION(10, 3, 1): 7262 case IP_VERSION(10, 3, 4): 7263 case IP_VERSION(10, 3, 5): 7264 case IP_VERSION(10, 3, 6): 7265 case IP_VERSION(10, 3, 3): 7266 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7267 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7268 GRBM_SOFT_RESET, 7269 SOFT_RESET_RLC, 7270 1); 7271 break; 7272 default: 7273 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7274 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7275 GRBM_SOFT_RESET, 7276 SOFT_RESET_RLC, 7277 1); 7278 break; 7279 } 7280 7281 if (grbm_soft_reset) { 7282 /* stop the rlc */ 7283 gfx_v10_0_rlc_stop(adev); 7284 7285 /* Disable GFX parsing/prefetching */ 7286 gfx_v10_0_cp_gfx_enable(adev, false); 7287 7288 /* Disable MEC parsing/prefetching */ 7289 gfx_v10_0_cp_compute_enable(adev, false); 7290 7291 if (grbm_soft_reset) { 7292 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7293 tmp |= grbm_soft_reset; 7294 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7295 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7296 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7297 7298 udelay(50); 7299 7300 tmp &= ~grbm_soft_reset; 7301 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7302 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7303 } 7304 7305 /* Wait a little for things to settle down */ 7306 udelay(50); 7307 } 7308 return 0; 7309 } 7310 7311 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7312 { 7313 uint64_t clock, clock_lo, clock_hi, hi_check; 7314 7315 switch (adev->ip_versions[GC_HWIP][0]) { 7316 case IP_VERSION(10, 3, 1): 7317 case IP_VERSION(10, 3, 3): 7318 case IP_VERSION(10, 3, 7): 7319 preempt_disable(); 7320 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7321 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7322 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7323 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7324 * roughly every 42 seconds. 7325 */ 7326 if (hi_check != clock_hi) { 7327 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7328 clock_hi = hi_check; 7329 } 7330 preempt_enable(); 7331 clock = clock_lo | (clock_hi << 32ULL); 7332 break; 7333 case IP_VERSION(10, 3, 6): 7334 preempt_disable(); 7335 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7336 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7337 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7338 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7339 * roughly every 42 seconds. 7340 */ 7341 if (hi_check != clock_hi) { 7342 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7343 clock_hi = hi_check; 7344 } 7345 preempt_enable(); 7346 clock = clock_lo | (clock_hi << 32ULL); 7347 break; 7348 default: 7349 preempt_disable(); 7350 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7351 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7352 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7353 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7354 * roughly every 42 seconds. 7355 */ 7356 if (hi_check != clock_hi) { 7357 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7358 clock_hi = hi_check; 7359 } 7360 preempt_enable(); 7361 clock = clock_lo | (clock_hi << 32ULL); 7362 break; 7363 } 7364 return clock; 7365 } 7366 7367 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7368 uint32_t vmid, 7369 uint32_t gds_base, uint32_t gds_size, 7370 uint32_t gws_base, uint32_t gws_size, 7371 uint32_t oa_base, uint32_t oa_size) 7372 { 7373 struct amdgpu_device *adev = ring->adev; 7374 7375 /* GDS Base */ 7376 gfx_v10_0_write_data_to_reg(ring, 0, false, 7377 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7378 gds_base); 7379 7380 /* GDS Size */ 7381 gfx_v10_0_write_data_to_reg(ring, 0, false, 7382 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7383 gds_size); 7384 7385 /* GWS */ 7386 gfx_v10_0_write_data_to_reg(ring, 0, false, 7387 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7388 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7389 7390 /* OA */ 7391 gfx_v10_0_write_data_to_reg(ring, 0, false, 7392 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7393 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7394 } 7395 7396 static int gfx_v10_0_early_init(void *handle) 7397 { 7398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7399 7400 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7401 7402 switch (adev->ip_versions[GC_HWIP][0]) { 7403 case IP_VERSION(10, 1, 10): 7404 case IP_VERSION(10, 1, 1): 7405 case IP_VERSION(10, 1, 2): 7406 case IP_VERSION(10, 1, 3): 7407 case IP_VERSION(10, 1, 4): 7408 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7409 break; 7410 case IP_VERSION(10, 3, 0): 7411 case IP_VERSION(10, 3, 2): 7412 case IP_VERSION(10, 3, 1): 7413 case IP_VERSION(10, 3, 4): 7414 case IP_VERSION(10, 3, 5): 7415 case IP_VERSION(10, 3, 6): 7416 case IP_VERSION(10, 3, 3): 7417 case IP_VERSION(10, 3, 7): 7418 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7419 break; 7420 default: 7421 break; 7422 } 7423 7424 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7425 AMDGPU_MAX_COMPUTE_RINGS); 7426 7427 gfx_v10_0_set_kiq_pm4_funcs(adev); 7428 gfx_v10_0_set_ring_funcs(adev); 7429 gfx_v10_0_set_irq_funcs(adev); 7430 gfx_v10_0_set_gds_init(adev); 7431 gfx_v10_0_set_rlc_funcs(adev); 7432 gfx_v10_0_set_mqd_funcs(adev); 7433 7434 /* init rlcg reg access ctrl */ 7435 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7436 7437 return gfx_v10_0_init_microcode(adev); 7438 } 7439 7440 static int gfx_v10_0_late_init(void *handle) 7441 { 7442 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7443 int r; 7444 7445 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7446 if (r) 7447 return r; 7448 7449 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7450 if (r) 7451 return r; 7452 7453 return 0; 7454 } 7455 7456 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7457 { 7458 uint32_t rlc_cntl; 7459 7460 /* if RLC is not enabled, do nothing */ 7461 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7462 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7463 } 7464 7465 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7466 { 7467 uint32_t data; 7468 unsigned int i; 7469 7470 data = RLC_SAFE_MODE__CMD_MASK; 7471 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7472 7473 switch (adev->ip_versions[GC_HWIP][0]) { 7474 case IP_VERSION(10, 3, 0): 7475 case IP_VERSION(10, 3, 2): 7476 case IP_VERSION(10, 3, 1): 7477 case IP_VERSION(10, 3, 4): 7478 case IP_VERSION(10, 3, 5): 7479 case IP_VERSION(10, 3, 6): 7480 case IP_VERSION(10, 3, 3): 7481 case IP_VERSION(10, 3, 7): 7482 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7483 7484 /* wait for RLC_SAFE_MODE */ 7485 for (i = 0; i < adev->usec_timeout; i++) { 7486 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7487 RLC_SAFE_MODE, CMD)) 7488 break; 7489 udelay(1); 7490 } 7491 break; 7492 default: 7493 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7494 7495 /* wait for RLC_SAFE_MODE */ 7496 for (i = 0; i < adev->usec_timeout; i++) { 7497 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7498 RLC_SAFE_MODE, CMD)) 7499 break; 7500 udelay(1); 7501 } 7502 break; 7503 } 7504 } 7505 7506 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7507 { 7508 uint32_t data; 7509 7510 data = RLC_SAFE_MODE__CMD_MASK; 7511 switch (adev->ip_versions[GC_HWIP][0]) { 7512 case IP_VERSION(10, 3, 0): 7513 case IP_VERSION(10, 3, 2): 7514 case IP_VERSION(10, 3, 1): 7515 case IP_VERSION(10, 3, 4): 7516 case IP_VERSION(10, 3, 5): 7517 case IP_VERSION(10, 3, 6): 7518 case IP_VERSION(10, 3, 3): 7519 case IP_VERSION(10, 3, 7): 7520 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7521 break; 7522 default: 7523 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7524 break; 7525 } 7526 } 7527 7528 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7529 bool enable) 7530 { 7531 uint32_t data, def; 7532 7533 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7534 return; 7535 7536 /* It is disabled by HW by default */ 7537 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7538 /* 0 - Disable some blocks' MGCG */ 7539 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7540 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7541 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7542 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7543 7544 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7545 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7546 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7547 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7548 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7549 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7550 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7551 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7552 7553 if (def != data) 7554 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7555 7556 /* MGLS is a global flag to control all MGLS in GFX */ 7557 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7558 /* 2 - RLC memory Light sleep */ 7559 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7560 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7561 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7562 if (def != data) 7563 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7564 } 7565 /* 3 - CP memory Light sleep */ 7566 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7567 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7568 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7569 if (def != data) 7570 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7571 } 7572 } 7573 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7574 /* 1 - MGCG_OVERRIDE */ 7575 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7576 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7577 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7578 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7579 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7580 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7581 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7582 if (def != data) 7583 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7584 7585 /* 2 - disable MGLS in CP */ 7586 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7587 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7588 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7589 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7590 } 7591 7592 /* 3 - disable MGLS in RLC */ 7593 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7594 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7595 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7596 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7597 } 7598 7599 } 7600 } 7601 7602 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7603 bool enable) 7604 { 7605 uint32_t data, def; 7606 7607 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7608 return; 7609 7610 /* Enable 3D CGCG/CGLS */ 7611 if (enable) { 7612 /* write cmd to clear cgcg/cgls ov */ 7613 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7614 7615 /* unset CGCG override */ 7616 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7617 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7618 7619 /* update CGCG and CGLS override bits */ 7620 if (def != data) 7621 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7622 7623 /* enable 3Dcgcg FSM(0x0000363f) */ 7624 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7625 data = 0; 7626 7627 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7628 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7629 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7630 7631 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7632 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7633 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7634 7635 if (def != data) 7636 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7637 7638 /* set IDLE_POLL_COUNT(0x00900100) */ 7639 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7640 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7641 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7642 if (def != data) 7643 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7644 } else { 7645 /* Disable CGCG/CGLS */ 7646 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7647 7648 /* disable cgcg, cgls should be disabled */ 7649 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7650 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7651 7652 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7653 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7654 7655 /* disable cgcg and cgls in FSM */ 7656 if (def != data) 7657 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7658 } 7659 } 7660 7661 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7662 bool enable) 7663 { 7664 uint32_t def, data; 7665 7666 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7667 return; 7668 7669 if (enable) { 7670 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7671 7672 /* unset CGCG override */ 7673 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7674 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7675 7676 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7677 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7678 7679 /* update CGCG and CGLS override bits */ 7680 if (def != data) 7681 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7682 7683 /* enable cgcg FSM(0x0000363F) */ 7684 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7685 data = 0; 7686 7687 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7688 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7689 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7690 7691 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7692 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7693 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7694 7695 if (def != data) 7696 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7697 7698 /* set IDLE_POLL_COUNT(0x00900100) */ 7699 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7700 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7701 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7702 if (def != data) 7703 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7704 } else { 7705 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7706 7707 /* reset CGCG/CGLS bits */ 7708 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7709 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7710 7711 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7712 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7713 7714 /* disable cgcg and cgls in FSM */ 7715 if (def != data) 7716 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7717 } 7718 } 7719 7720 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7721 bool enable) 7722 { 7723 uint32_t def, data; 7724 7725 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 7726 return; 7727 7728 if (enable) { 7729 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7730 /* unset FGCG override */ 7731 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7732 /* update FGCG override bits */ 7733 if (def != data) 7734 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7735 7736 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7737 /* unset RLC SRAM CLK GATER override */ 7738 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7739 /* update RLC SRAM CLK GATER override bits */ 7740 if (def != data) 7741 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7742 } else { 7743 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7744 /* reset FGCG bits */ 7745 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7746 /* disable FGCG*/ 7747 if (def != data) 7748 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7749 7750 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7751 /* reset RLC SRAM CLK GATER bits */ 7752 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7753 /* disable RLC SRAM CLK*/ 7754 if (def != data) 7755 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7756 } 7757 } 7758 7759 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 7760 { 7761 uint32_t reg_data = 0; 7762 uint32_t reg_idx = 0; 7763 uint32_t i; 7764 7765 const uint32_t tcp_ctrl_regs[] = { 7766 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7767 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7768 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7769 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7770 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7771 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7772 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7773 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7774 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7775 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7776 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 7777 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 7778 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7779 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7780 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7781 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7782 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7783 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7784 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7785 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7786 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7787 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7788 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 7789 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 7790 }; 7791 7792 const uint32_t tcp_ctrl_regs_nv12[] = { 7793 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7794 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7795 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7796 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7797 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7798 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7799 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7800 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7801 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7802 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7803 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7804 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7805 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7806 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7807 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7808 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7809 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7810 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7811 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7812 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7813 }; 7814 7815 const uint32_t sm_ctlr_regs[] = { 7816 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 7817 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 7818 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 7819 mmCGTS_SA1_QUAD1_SM_CTRL_REG 7820 }; 7821 7822 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 7823 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 7824 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7825 tcp_ctrl_regs_nv12[i]; 7826 reg_data = RREG32(reg_idx); 7827 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7828 WREG32(reg_idx, reg_data); 7829 } 7830 } else { 7831 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 7832 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7833 tcp_ctrl_regs[i]; 7834 reg_data = RREG32(reg_idx); 7835 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7836 WREG32(reg_idx, reg_data); 7837 } 7838 } 7839 7840 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 7841 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 7842 sm_ctlr_regs[i]; 7843 reg_data = RREG32(reg_idx); 7844 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 7845 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 7846 WREG32(reg_idx, reg_data); 7847 } 7848 } 7849 7850 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7851 bool enable) 7852 { 7853 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 7854 7855 if (enable) { 7856 /* enable FGCG firstly*/ 7857 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7858 /* CGCG/CGLS should be enabled after MGCG/MGLS 7859 * === MGCG + MGLS === 7860 */ 7861 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7862 /* === CGCG /CGLS for GFX 3D Only === */ 7863 gfx_v10_0_update_3d_clock_gating(adev, enable); 7864 /* === CGCG + CGLS === */ 7865 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7866 7867 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) || 7868 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) || 7869 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))) 7870 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 7871 } else { 7872 /* CGCG/CGLS should be disabled before MGCG/MGLS 7873 * === CGCG + CGLS === 7874 */ 7875 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7876 /* === CGCG /CGLS for GFX 3D Only === */ 7877 gfx_v10_0_update_3d_clock_gating(adev, enable); 7878 /* === MGCG + MGLS === */ 7879 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7880 /* disable fgcg at last*/ 7881 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7882 } 7883 7884 if (adev->cg_flags & 7885 (AMD_CG_SUPPORT_GFX_MGCG | 7886 AMD_CG_SUPPORT_GFX_CGLS | 7887 AMD_CG_SUPPORT_GFX_CGCG | 7888 AMD_CG_SUPPORT_GFX_3D_CGCG | 7889 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7890 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7891 7892 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 7893 7894 return 0; 7895 } 7896 7897 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 7898 unsigned int vmid) 7899 { 7900 u32 reg, data; 7901 7902 /* not for *_SOC15 */ 7903 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7904 if (amdgpu_sriov_is_pp_one_vf(adev)) 7905 data = RREG32_NO_KIQ(reg); 7906 else 7907 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 7908 7909 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7910 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7911 7912 if (amdgpu_sriov_is_pp_one_vf(adev)) 7913 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7914 else 7915 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7916 } 7917 7918 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid) 7919 { 7920 amdgpu_gfx_off_ctrl(adev, false); 7921 7922 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 7923 7924 amdgpu_gfx_off_ctrl(adev, true); 7925 } 7926 7927 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7928 uint32_t offset, 7929 struct soc15_reg_rlcg *entries, int arr_size) 7930 { 7931 int i; 7932 uint32_t reg; 7933 7934 if (!entries) 7935 return false; 7936 7937 for (i = 0; i < arr_size; i++) { 7938 const struct soc15_reg_rlcg *entry; 7939 7940 entry = &entries[i]; 7941 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7942 if (offset == reg) 7943 return true; 7944 } 7945 7946 return false; 7947 } 7948 7949 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7950 { 7951 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7952 } 7953 7954 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7955 { 7956 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7957 7958 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7959 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7960 else 7961 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7962 7963 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7964 7965 /* 7966 * CGPG enablement required and the register to program the hysteresis value 7967 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 7968 * in refclk count. Note that RLC FW is modified to take 16 bits from 7969 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 7970 * 7971 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 7972 * of CGPG enablement starting point. 7973 * Power/performance team will optimize it and might give a new value later. 7974 */ 7975 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 7976 switch (adev->ip_versions[GC_HWIP][0]) { 7977 case IP_VERSION(10, 3, 1): 7978 case IP_VERSION(10, 3, 3): 7979 case IP_VERSION(10, 3, 6): 7980 case IP_VERSION(10, 3, 7): 7981 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 7982 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 7983 break; 7984 default: 7985 break; 7986 } 7987 } 7988 } 7989 7990 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7991 { 7992 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 7993 7994 gfx_v10_cntl_power_gating(adev, enable); 7995 7996 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 7997 } 7998 7999 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8000 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8001 .set_safe_mode = gfx_v10_0_set_safe_mode, 8002 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8003 .init = gfx_v10_0_rlc_init, 8004 .get_csb_size = gfx_v10_0_get_csb_size, 8005 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8006 .resume = gfx_v10_0_rlc_resume, 8007 .stop = gfx_v10_0_rlc_stop, 8008 .reset = gfx_v10_0_rlc_reset, 8009 .start = gfx_v10_0_rlc_start, 8010 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8011 }; 8012 8013 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8014 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8015 .set_safe_mode = gfx_v10_0_set_safe_mode, 8016 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8017 .init = gfx_v10_0_rlc_init, 8018 .get_csb_size = gfx_v10_0_get_csb_size, 8019 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8020 .resume = gfx_v10_0_rlc_resume, 8021 .stop = gfx_v10_0_rlc_stop, 8022 .reset = gfx_v10_0_rlc_reset, 8023 .start = gfx_v10_0_rlc_start, 8024 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8025 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8026 }; 8027 8028 static int gfx_v10_0_set_powergating_state(void *handle, 8029 enum amd_powergating_state state) 8030 { 8031 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8032 bool enable = (state == AMD_PG_STATE_GATE); 8033 8034 if (amdgpu_sriov_vf(adev)) 8035 return 0; 8036 8037 switch (adev->ip_versions[GC_HWIP][0]) { 8038 case IP_VERSION(10, 1, 10): 8039 case IP_VERSION(10, 1, 1): 8040 case IP_VERSION(10, 1, 2): 8041 case IP_VERSION(10, 3, 0): 8042 case IP_VERSION(10, 3, 2): 8043 case IP_VERSION(10, 3, 4): 8044 case IP_VERSION(10, 3, 5): 8045 amdgpu_gfx_off_ctrl(adev, enable); 8046 break; 8047 case IP_VERSION(10, 3, 1): 8048 case IP_VERSION(10, 3, 3): 8049 case IP_VERSION(10, 3, 6): 8050 case IP_VERSION(10, 3, 7): 8051 if (!enable) 8052 amdgpu_gfx_off_ctrl(adev, false); 8053 8054 gfx_v10_cntl_pg(adev, enable); 8055 8056 if (enable) 8057 amdgpu_gfx_off_ctrl(adev, true); 8058 8059 break; 8060 default: 8061 break; 8062 } 8063 return 0; 8064 } 8065 8066 static int gfx_v10_0_set_clockgating_state(void *handle, 8067 enum amd_clockgating_state state) 8068 { 8069 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8070 8071 if (amdgpu_sriov_vf(adev)) 8072 return 0; 8073 8074 switch (adev->ip_versions[GC_HWIP][0]) { 8075 case IP_VERSION(10, 1, 10): 8076 case IP_VERSION(10, 1, 1): 8077 case IP_VERSION(10, 1, 2): 8078 case IP_VERSION(10, 3, 0): 8079 case IP_VERSION(10, 3, 2): 8080 case IP_VERSION(10, 3, 1): 8081 case IP_VERSION(10, 3, 4): 8082 case IP_VERSION(10, 3, 5): 8083 case IP_VERSION(10, 3, 6): 8084 case IP_VERSION(10, 3, 3): 8085 case IP_VERSION(10, 3, 7): 8086 gfx_v10_0_update_gfx_clock_gating(adev, 8087 state == AMD_CG_STATE_GATE); 8088 break; 8089 default: 8090 break; 8091 } 8092 return 0; 8093 } 8094 8095 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8096 { 8097 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8098 int data; 8099 8100 /* AMD_CG_SUPPORT_GFX_FGCG */ 8101 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8102 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8103 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8104 8105 /* AMD_CG_SUPPORT_GFX_MGCG */ 8106 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8107 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8108 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8109 8110 /* AMD_CG_SUPPORT_GFX_CGCG */ 8111 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8112 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8113 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8114 8115 /* AMD_CG_SUPPORT_GFX_CGLS */ 8116 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8117 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8118 8119 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8120 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8121 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8122 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8123 8124 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8125 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8126 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8127 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8128 8129 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8130 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8131 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8132 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8133 8134 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8135 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8136 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8137 } 8138 8139 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8140 { 8141 /* gfx10 is 32bit rptr*/ 8142 return *(uint32_t *)ring->rptr_cpu_addr; 8143 } 8144 8145 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8146 { 8147 struct amdgpu_device *adev = ring->adev; 8148 u64 wptr; 8149 8150 /* XXX check if swapping is necessary on BE */ 8151 if (ring->use_doorbell) { 8152 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8153 } else { 8154 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8155 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8156 } 8157 8158 return wptr; 8159 } 8160 8161 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8162 { 8163 struct amdgpu_device *adev = ring->adev; 8164 uint32_t *wptr_saved; 8165 uint32_t *is_queue_unmap; 8166 uint64_t aggregated_db_index; 8167 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 8168 uint64_t wptr_tmp; 8169 8170 if (ring->is_mes_queue) { 8171 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8172 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8173 sizeof(uint32_t)); 8174 aggregated_db_index = 8175 amdgpu_mes_get_aggregated_doorbell_index(adev, 8176 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8177 8178 wptr_tmp = ring->wptr & ring->buf_mask; 8179 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8180 *wptr_saved = wptr_tmp; 8181 /* assume doorbell always being used by mes mapped queue */ 8182 if (*is_queue_unmap) { 8183 WDOORBELL64(aggregated_db_index, wptr_tmp); 8184 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8185 } else { 8186 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8187 8188 if (*is_queue_unmap) 8189 WDOORBELL64(aggregated_db_index, wptr_tmp); 8190 } 8191 } else { 8192 if (ring->use_doorbell) { 8193 /* XXX check if swapping is necessary on BE */ 8194 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8195 ring->wptr); 8196 WDOORBELL64(ring->doorbell_index, ring->wptr); 8197 } else { 8198 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8199 lower_32_bits(ring->wptr)); 8200 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8201 upper_32_bits(ring->wptr)); 8202 } 8203 } 8204 } 8205 8206 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8207 { 8208 /* gfx10 hardware is 32bit rptr */ 8209 return *(uint32_t *)ring->rptr_cpu_addr; 8210 } 8211 8212 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8213 { 8214 u64 wptr; 8215 8216 /* XXX check if swapping is necessary on BE */ 8217 if (ring->use_doorbell) 8218 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8219 else 8220 BUG(); 8221 return wptr; 8222 } 8223 8224 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8225 { 8226 struct amdgpu_device *adev = ring->adev; 8227 uint32_t *wptr_saved; 8228 uint32_t *is_queue_unmap; 8229 uint64_t aggregated_db_index; 8230 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 8231 uint64_t wptr_tmp; 8232 8233 if (ring->is_mes_queue) { 8234 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8235 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8236 sizeof(uint32_t)); 8237 aggregated_db_index = 8238 amdgpu_mes_get_aggregated_doorbell_index(adev, 8239 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8240 8241 wptr_tmp = ring->wptr & ring->buf_mask; 8242 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8243 *wptr_saved = wptr_tmp; 8244 /* assume doorbell always used by mes mapped queue */ 8245 if (*is_queue_unmap) { 8246 WDOORBELL64(aggregated_db_index, wptr_tmp); 8247 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8248 } else { 8249 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8250 8251 if (*is_queue_unmap) 8252 WDOORBELL64(aggregated_db_index, wptr_tmp); 8253 } 8254 } else { 8255 /* XXX check if swapping is necessary on BE */ 8256 if (ring->use_doorbell) { 8257 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8258 ring->wptr); 8259 WDOORBELL64(ring->doorbell_index, ring->wptr); 8260 } else { 8261 BUG(); /* only DOORBELL method supported on gfx10 now */ 8262 } 8263 } 8264 } 8265 8266 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8267 { 8268 struct amdgpu_device *adev = ring->adev; 8269 u32 ref_and_mask, reg_mem_engine; 8270 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8271 8272 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8273 switch (ring->me) { 8274 case 1: 8275 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8276 break; 8277 case 2: 8278 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8279 break; 8280 default: 8281 return; 8282 } 8283 reg_mem_engine = 0; 8284 } else { 8285 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8286 reg_mem_engine = 1; /* pfp */ 8287 } 8288 8289 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8290 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8291 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8292 ref_and_mask, ref_and_mask, 0x20); 8293 } 8294 8295 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8296 struct amdgpu_job *job, 8297 struct amdgpu_ib *ib, 8298 uint32_t flags) 8299 { 8300 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8301 u32 header, control = 0; 8302 8303 if (ib->flags & AMDGPU_IB_FLAG_CE) 8304 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8305 else 8306 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8307 8308 control |= ib->length_dw | (vmid << 24); 8309 8310 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8311 control |= INDIRECT_BUFFER_PRE_ENB(1); 8312 8313 if (flags & AMDGPU_IB_PREEMPTED) 8314 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8315 8316 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8317 gfx_v10_0_ring_emit_de_meta(ring, 8318 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8319 } 8320 8321 if (ring->is_mes_queue) 8322 /* inherit vmid from mqd */ 8323 control |= 0x400000; 8324 8325 amdgpu_ring_write(ring, header); 8326 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8327 amdgpu_ring_write(ring, 8328 #ifdef __BIG_ENDIAN 8329 (2 << 0) | 8330 #endif 8331 lower_32_bits(ib->gpu_addr)); 8332 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8333 amdgpu_ring_write(ring, control); 8334 } 8335 8336 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8337 struct amdgpu_job *job, 8338 struct amdgpu_ib *ib, 8339 uint32_t flags) 8340 { 8341 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8342 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8343 8344 if (ring->is_mes_queue) 8345 /* inherit vmid from mqd */ 8346 control |= 0x40000000; 8347 8348 /* Currently, there is a high possibility to get wave ID mismatch 8349 * between ME and GDS, leading to a hw deadlock, because ME generates 8350 * different wave IDs than the GDS expects. This situation happens 8351 * randomly when at least 5 compute pipes use GDS ordered append. 8352 * The wave IDs generated by ME are also wrong after suspend/resume. 8353 * Those are probably bugs somewhere else in the kernel driver. 8354 * 8355 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8356 * GDS to 0 for this ring (me/pipe). 8357 */ 8358 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8359 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8360 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8361 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8362 } 8363 8364 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8365 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8366 amdgpu_ring_write(ring, 8367 #ifdef __BIG_ENDIAN 8368 (2 << 0) | 8369 #endif 8370 lower_32_bits(ib->gpu_addr)); 8371 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8372 amdgpu_ring_write(ring, control); 8373 } 8374 8375 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8376 u64 seq, unsigned int flags) 8377 { 8378 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8379 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8380 8381 /* RELEASE_MEM - flush caches, send int */ 8382 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8383 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8384 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8385 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8386 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8387 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8388 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8389 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8390 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8391 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8392 8393 /* 8394 * the address should be Qword aligned if 64bit write, Dword 8395 * aligned if only send 32bit data low (discard data high) 8396 */ 8397 if (write64bit) 8398 BUG_ON(addr & 0x7); 8399 else 8400 BUG_ON(addr & 0x3); 8401 amdgpu_ring_write(ring, lower_32_bits(addr)); 8402 amdgpu_ring_write(ring, upper_32_bits(addr)); 8403 amdgpu_ring_write(ring, lower_32_bits(seq)); 8404 amdgpu_ring_write(ring, upper_32_bits(seq)); 8405 amdgpu_ring_write(ring, ring->is_mes_queue ? 8406 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 8407 } 8408 8409 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8410 { 8411 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8412 uint32_t seq = ring->fence_drv.sync_seq; 8413 uint64_t addr = ring->fence_drv.gpu_addr; 8414 8415 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8416 upper_32_bits(addr), seq, 0xffffffff, 4); 8417 } 8418 8419 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8420 uint16_t pasid, uint32_t flush_type, 8421 bool all_hub, uint8_t dst_sel) 8422 { 8423 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8424 amdgpu_ring_write(ring, 8425 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8426 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8427 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8428 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8429 } 8430 8431 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8432 unsigned int vmid, uint64_t pd_addr) 8433 { 8434 if (ring->is_mes_queue) 8435 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 8436 else 8437 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8438 8439 /* compute doesn't have PFP */ 8440 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8441 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8442 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8443 amdgpu_ring_write(ring, 0x0); 8444 } 8445 } 8446 8447 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8448 u64 seq, unsigned int flags) 8449 { 8450 struct amdgpu_device *adev = ring->adev; 8451 8452 /* we only allocate 32bit for each seq wb address */ 8453 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8454 8455 /* write fence seq to the "addr" */ 8456 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8457 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8458 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8459 amdgpu_ring_write(ring, lower_32_bits(addr)); 8460 amdgpu_ring_write(ring, upper_32_bits(addr)); 8461 amdgpu_ring_write(ring, lower_32_bits(seq)); 8462 8463 if (flags & AMDGPU_FENCE_FLAG_INT) { 8464 /* set register to trigger INT */ 8465 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8466 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8467 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8468 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8469 amdgpu_ring_write(ring, 0); 8470 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8471 } 8472 } 8473 8474 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8475 { 8476 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8477 amdgpu_ring_write(ring, 0); 8478 } 8479 8480 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8481 uint32_t flags) 8482 { 8483 uint32_t dw2 = 0; 8484 8485 if (ring->adev->gfx.mcbp) 8486 gfx_v10_0_ring_emit_ce_meta(ring, 8487 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8488 8489 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8490 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8491 /* set load_global_config & load_global_uconfig */ 8492 dw2 |= 0x8001; 8493 /* set load_cs_sh_regs */ 8494 dw2 |= 0x01000000; 8495 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8496 dw2 |= 0x10002; 8497 8498 /* set load_ce_ram if preamble presented */ 8499 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8500 dw2 |= 0x10000000; 8501 } else { 8502 /* still load_ce_ram if this is the first time preamble presented 8503 * although there is no context switch happens. 8504 */ 8505 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8506 dw2 |= 0x10000000; 8507 } 8508 8509 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8510 amdgpu_ring_write(ring, dw2); 8511 amdgpu_ring_write(ring, 0); 8512 } 8513 8514 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8515 { 8516 unsigned int ret; 8517 8518 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8519 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8520 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8521 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8522 ret = ring->wptr & ring->buf_mask; 8523 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8524 8525 return ret; 8526 } 8527 8528 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset) 8529 { 8530 unsigned int cur; 8531 8532 BUG_ON(offset > ring->buf_mask); 8533 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8534 8535 cur = (ring->wptr - 1) & ring->buf_mask; 8536 if (likely(cur > offset)) 8537 ring->ring[offset] = cur - offset; 8538 else 8539 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8540 } 8541 8542 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8543 { 8544 int i, r = 0; 8545 struct amdgpu_device *adev = ring->adev; 8546 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8547 struct amdgpu_ring *kiq_ring = &kiq->ring; 8548 unsigned long flags; 8549 8550 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8551 return -EINVAL; 8552 8553 spin_lock_irqsave(&kiq->ring_lock, flags); 8554 8555 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8556 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8557 return -ENOMEM; 8558 } 8559 8560 /* assert preemption condition */ 8561 amdgpu_ring_set_preempt_cond_exec(ring, false); 8562 8563 /* assert IB preemption, emit the trailing fence */ 8564 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8565 ring->trail_fence_gpu_addr, 8566 ++ring->trail_seq); 8567 amdgpu_ring_commit(kiq_ring); 8568 8569 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8570 8571 /* poll the trailing fence */ 8572 for (i = 0; i < adev->usec_timeout; i++) { 8573 if (ring->trail_seq == 8574 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8575 break; 8576 udelay(1); 8577 } 8578 8579 if (i >= adev->usec_timeout) { 8580 r = -EINVAL; 8581 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8582 } 8583 8584 /* deassert preemption condition */ 8585 amdgpu_ring_set_preempt_cond_exec(ring, true); 8586 return r; 8587 } 8588 8589 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8590 { 8591 struct amdgpu_device *adev = ring->adev; 8592 struct v10_ce_ib_state ce_payload = {0}; 8593 uint64_t offset, ce_payload_gpu_addr; 8594 void *ce_payload_cpu_addr; 8595 int cnt; 8596 8597 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8598 8599 if (ring->is_mes_queue) { 8600 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8601 gfx[0].gfx_meta_data) + 8602 offsetof(struct v10_gfx_meta_data, ce_payload); 8603 ce_payload_gpu_addr = 8604 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8605 ce_payload_cpu_addr = 8606 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8607 } else { 8608 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8609 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8610 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8611 } 8612 8613 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8614 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8615 WRITE_DATA_DST_SEL(8) | 8616 WR_CONFIRM) | 8617 WRITE_DATA_CACHE_POLICY(0)); 8618 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8619 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8620 8621 if (resume) 8622 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8623 sizeof(ce_payload) >> 2); 8624 else 8625 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8626 sizeof(ce_payload) >> 2); 8627 } 8628 8629 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8630 { 8631 struct amdgpu_device *adev = ring->adev; 8632 struct v10_de_ib_state de_payload = {0}; 8633 uint64_t offset, gds_addr, de_payload_gpu_addr; 8634 void *de_payload_cpu_addr; 8635 int cnt; 8636 8637 if (ring->is_mes_queue) { 8638 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8639 gfx[0].gfx_meta_data) + 8640 offsetof(struct v10_gfx_meta_data, de_payload); 8641 de_payload_gpu_addr = 8642 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8643 de_payload_cpu_addr = 8644 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8645 8646 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8647 gfx[0].gds_backup) + 8648 offsetof(struct v10_gfx_meta_data, de_payload); 8649 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8650 } else { 8651 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8652 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8653 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8654 8655 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8656 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8657 PAGE_SIZE); 8658 } 8659 8660 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8661 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8662 8663 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8664 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8665 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8666 WRITE_DATA_DST_SEL(8) | 8667 WR_CONFIRM) | 8668 WRITE_DATA_CACHE_POLICY(0)); 8669 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8670 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8671 8672 if (resume) 8673 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8674 sizeof(de_payload) >> 2); 8675 else 8676 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8677 sizeof(de_payload) >> 2); 8678 } 8679 8680 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8681 bool secure) 8682 { 8683 uint32_t v = secure ? FRAME_TMZ : 0; 8684 8685 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8686 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8687 } 8688 8689 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8690 uint32_t reg_val_offs) 8691 { 8692 struct amdgpu_device *adev = ring->adev; 8693 8694 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8695 amdgpu_ring_write(ring, 0 | /* src: register*/ 8696 (5 << 8) | /* dst: memory */ 8697 (1 << 20)); /* write confirm */ 8698 amdgpu_ring_write(ring, reg); 8699 amdgpu_ring_write(ring, 0); 8700 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8701 reg_val_offs * 4)); 8702 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8703 reg_val_offs * 4)); 8704 } 8705 8706 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8707 uint32_t val) 8708 { 8709 uint32_t cmd = 0; 8710 8711 switch (ring->funcs->type) { 8712 case AMDGPU_RING_TYPE_GFX: 8713 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8714 break; 8715 case AMDGPU_RING_TYPE_KIQ: 8716 cmd = (1 << 16); /* no inc addr */ 8717 break; 8718 default: 8719 cmd = WR_CONFIRM; 8720 break; 8721 } 8722 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8723 amdgpu_ring_write(ring, cmd); 8724 amdgpu_ring_write(ring, reg); 8725 amdgpu_ring_write(ring, 0); 8726 amdgpu_ring_write(ring, val); 8727 } 8728 8729 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8730 uint32_t val, uint32_t mask) 8731 { 8732 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8733 } 8734 8735 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8736 uint32_t reg0, uint32_t reg1, 8737 uint32_t ref, uint32_t mask) 8738 { 8739 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8740 struct amdgpu_device *adev = ring->adev; 8741 bool fw_version_ok = false; 8742 8743 fw_version_ok = adev->gfx.cp_fw_write_wait; 8744 8745 if (fw_version_ok) 8746 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8747 ref, mask, 0x20); 8748 else 8749 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8750 ref, mask); 8751 } 8752 8753 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8754 unsigned int vmid) 8755 { 8756 struct amdgpu_device *adev = ring->adev; 8757 uint32_t value = 0; 8758 8759 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8760 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8761 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8762 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8763 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8764 } 8765 8766 static void 8767 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8768 uint32_t me, uint32_t pipe, 8769 enum amdgpu_interrupt_state state) 8770 { 8771 uint32_t cp_int_cntl, cp_int_cntl_reg; 8772 8773 if (!me) { 8774 switch (pipe) { 8775 case 0: 8776 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8777 break; 8778 case 1: 8779 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8780 break; 8781 default: 8782 DRM_DEBUG("invalid pipe %d\n", pipe); 8783 return; 8784 } 8785 } else { 8786 DRM_DEBUG("invalid me %d\n", me); 8787 return; 8788 } 8789 8790 switch (state) { 8791 case AMDGPU_IRQ_STATE_DISABLE: 8792 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8793 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8794 TIME_STAMP_INT_ENABLE, 0); 8795 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8796 break; 8797 case AMDGPU_IRQ_STATE_ENABLE: 8798 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8799 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8800 TIME_STAMP_INT_ENABLE, 1); 8801 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8802 break; 8803 default: 8804 break; 8805 } 8806 } 8807 8808 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8809 int me, int pipe, 8810 enum amdgpu_interrupt_state state) 8811 { 8812 u32 mec_int_cntl, mec_int_cntl_reg; 8813 8814 /* 8815 * amdgpu controls only the first MEC. That's why this function only 8816 * handles the setting of interrupts for this specific MEC. All other 8817 * pipes' interrupts are set by amdkfd. 8818 */ 8819 8820 if (me == 1) { 8821 switch (pipe) { 8822 case 0: 8823 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8824 break; 8825 case 1: 8826 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8827 break; 8828 case 2: 8829 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8830 break; 8831 case 3: 8832 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8833 break; 8834 default: 8835 DRM_DEBUG("invalid pipe %d\n", pipe); 8836 return; 8837 } 8838 } else { 8839 DRM_DEBUG("invalid me %d\n", me); 8840 return; 8841 } 8842 8843 switch (state) { 8844 case AMDGPU_IRQ_STATE_DISABLE: 8845 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8846 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8847 TIME_STAMP_INT_ENABLE, 0); 8848 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8849 break; 8850 case AMDGPU_IRQ_STATE_ENABLE: 8851 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8852 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8853 TIME_STAMP_INT_ENABLE, 1); 8854 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8855 break; 8856 default: 8857 break; 8858 } 8859 } 8860 8861 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8862 struct amdgpu_irq_src *src, 8863 unsigned int type, 8864 enum amdgpu_interrupt_state state) 8865 { 8866 switch (type) { 8867 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8868 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8869 break; 8870 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8871 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8872 break; 8873 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8874 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8875 break; 8876 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8877 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8878 break; 8879 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8880 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8881 break; 8882 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8883 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8884 break; 8885 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8886 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8887 break; 8888 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8889 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8890 break; 8891 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8892 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8893 break; 8894 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8895 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8896 break; 8897 default: 8898 break; 8899 } 8900 return 0; 8901 } 8902 8903 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8904 struct amdgpu_irq_src *source, 8905 struct amdgpu_iv_entry *entry) 8906 { 8907 int i; 8908 u8 me_id, pipe_id, queue_id; 8909 struct amdgpu_ring *ring; 8910 uint32_t mes_queue_id = entry->src_data[0]; 8911 8912 DRM_DEBUG("IH: CP EOP\n"); 8913 8914 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 8915 struct amdgpu_mes_queue *queue; 8916 8917 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 8918 8919 spin_lock(&adev->mes.queue_id_lock); 8920 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 8921 if (queue) { 8922 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 8923 amdgpu_fence_process(queue->ring); 8924 } 8925 spin_unlock(&adev->mes.queue_id_lock); 8926 } else { 8927 me_id = (entry->ring_id & 0x0c) >> 2; 8928 pipe_id = (entry->ring_id & 0x03) >> 0; 8929 queue_id = (entry->ring_id & 0x70) >> 4; 8930 8931 switch (me_id) { 8932 case 0: 8933 if (pipe_id == 0) 8934 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8935 else 8936 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8937 break; 8938 case 1: 8939 case 2: 8940 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8941 ring = &adev->gfx.compute_ring[i]; 8942 /* Per-queue interrupt is supported for MEC starting from VI. 8943 * The interrupt can only be enabled/disabled per pipe instead 8944 * of per queue. 8945 */ 8946 if ((ring->me == me_id) && 8947 (ring->pipe == pipe_id) && 8948 (ring->queue == queue_id)) 8949 amdgpu_fence_process(ring); 8950 } 8951 break; 8952 } 8953 } 8954 8955 return 0; 8956 } 8957 8958 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8959 struct amdgpu_irq_src *source, 8960 unsigned int type, 8961 enum amdgpu_interrupt_state state) 8962 { 8963 switch (state) { 8964 case AMDGPU_IRQ_STATE_DISABLE: 8965 case AMDGPU_IRQ_STATE_ENABLE: 8966 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8967 PRIV_REG_INT_ENABLE, 8968 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8969 break; 8970 default: 8971 break; 8972 } 8973 8974 return 0; 8975 } 8976 8977 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8978 struct amdgpu_irq_src *source, 8979 unsigned int type, 8980 enum amdgpu_interrupt_state state) 8981 { 8982 switch (state) { 8983 case AMDGPU_IRQ_STATE_DISABLE: 8984 case AMDGPU_IRQ_STATE_ENABLE: 8985 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8986 PRIV_INSTR_INT_ENABLE, 8987 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8988 break; 8989 default: 8990 break; 8991 } 8992 8993 return 0; 8994 } 8995 8996 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8997 struct amdgpu_iv_entry *entry) 8998 { 8999 u8 me_id, pipe_id, queue_id; 9000 struct amdgpu_ring *ring; 9001 int i; 9002 9003 me_id = (entry->ring_id & 0x0c) >> 2; 9004 pipe_id = (entry->ring_id & 0x03) >> 0; 9005 queue_id = (entry->ring_id & 0x70) >> 4; 9006 9007 switch (me_id) { 9008 case 0: 9009 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9010 ring = &adev->gfx.gfx_ring[i]; 9011 /* we only enabled 1 gfx queue per pipe for now */ 9012 if (ring->me == me_id && ring->pipe == pipe_id) 9013 drm_sched_fault(&ring->sched); 9014 } 9015 break; 9016 case 1: 9017 case 2: 9018 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9019 ring = &adev->gfx.compute_ring[i]; 9020 if (ring->me == me_id && ring->pipe == pipe_id && 9021 ring->queue == queue_id) 9022 drm_sched_fault(&ring->sched); 9023 } 9024 break; 9025 default: 9026 BUG(); 9027 } 9028 } 9029 9030 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9031 struct amdgpu_irq_src *source, 9032 struct amdgpu_iv_entry *entry) 9033 { 9034 DRM_ERROR("Illegal register access in command stream\n"); 9035 gfx_v10_0_handle_priv_fault(adev, entry); 9036 return 0; 9037 } 9038 9039 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9040 struct amdgpu_irq_src *source, 9041 struct amdgpu_iv_entry *entry) 9042 { 9043 DRM_ERROR("Illegal instruction in command stream\n"); 9044 gfx_v10_0_handle_priv_fault(adev, entry); 9045 return 0; 9046 } 9047 9048 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9049 struct amdgpu_irq_src *src, 9050 unsigned int type, 9051 enum amdgpu_interrupt_state state) 9052 { 9053 uint32_t tmp, target; 9054 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9055 9056 if (ring->me == 1) 9057 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9058 else 9059 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9060 target += ring->pipe; 9061 9062 switch (type) { 9063 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9064 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9065 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9066 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9067 GENERIC2_INT_ENABLE, 0); 9068 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9069 9070 tmp = RREG32_SOC15_IP(GC, target); 9071 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9072 GENERIC2_INT_ENABLE, 0); 9073 WREG32_SOC15_IP(GC, target, tmp); 9074 } else { 9075 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9076 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9077 GENERIC2_INT_ENABLE, 1); 9078 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9079 9080 tmp = RREG32_SOC15_IP(GC, target); 9081 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9082 GENERIC2_INT_ENABLE, 1); 9083 WREG32_SOC15_IP(GC, target, tmp); 9084 } 9085 break; 9086 default: 9087 BUG(); /* kiq only support GENERIC2_INT now */ 9088 break; 9089 } 9090 return 0; 9091 } 9092 9093 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9094 struct amdgpu_irq_src *source, 9095 struct amdgpu_iv_entry *entry) 9096 { 9097 u8 me_id, pipe_id, queue_id; 9098 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9099 9100 me_id = (entry->ring_id & 0x0c) >> 2; 9101 pipe_id = (entry->ring_id & 0x03) >> 0; 9102 queue_id = (entry->ring_id & 0x70) >> 4; 9103 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9104 me_id, pipe_id, queue_id); 9105 9106 amdgpu_fence_process(ring); 9107 return 0; 9108 } 9109 9110 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9111 { 9112 const unsigned int gcr_cntl = 9113 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9114 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9115 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9116 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9117 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9118 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9119 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9120 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9121 9122 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9123 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9124 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9125 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9126 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9127 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9128 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9129 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9130 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9131 } 9132 9133 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9134 .name = "gfx_v10_0", 9135 .early_init = gfx_v10_0_early_init, 9136 .late_init = gfx_v10_0_late_init, 9137 .sw_init = gfx_v10_0_sw_init, 9138 .sw_fini = gfx_v10_0_sw_fini, 9139 .hw_init = gfx_v10_0_hw_init, 9140 .hw_fini = gfx_v10_0_hw_fini, 9141 .suspend = gfx_v10_0_suspend, 9142 .resume = gfx_v10_0_resume, 9143 .is_idle = gfx_v10_0_is_idle, 9144 .wait_for_idle = gfx_v10_0_wait_for_idle, 9145 .soft_reset = gfx_v10_0_soft_reset, 9146 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9147 .set_powergating_state = gfx_v10_0_set_powergating_state, 9148 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9149 }; 9150 9151 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9152 .type = AMDGPU_RING_TYPE_GFX, 9153 .align_mask = 0xff, 9154 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9155 .support_64bit_ptrs = true, 9156 .secure_submission_supported = true, 9157 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9158 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9159 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9160 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9161 5 + /* COND_EXEC */ 9162 7 + /* PIPELINE_SYNC */ 9163 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9164 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9165 2 + /* VM_FLUSH */ 9166 8 + /* FENCE for VM_FLUSH */ 9167 20 + /* GDS switch */ 9168 4 + /* double SWITCH_BUFFER, 9169 * the first COND_EXEC jump to the place 9170 * just prior to this double SWITCH_BUFFER 9171 */ 9172 5 + /* COND_EXEC */ 9173 7 + /* HDP_flush */ 9174 4 + /* VGT_flush */ 9175 14 + /* CE_META */ 9176 31 + /* DE_META */ 9177 3 + /* CNTX_CTRL */ 9178 5 + /* HDP_INVL */ 9179 8 + 8 + /* FENCE x2 */ 9180 2 + /* SWITCH_BUFFER */ 9181 8, /* gfx_v10_0_emit_mem_sync */ 9182 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9183 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9184 .emit_fence = gfx_v10_0_ring_emit_fence, 9185 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9186 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9187 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9188 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9189 .test_ring = gfx_v10_0_ring_test_ring, 9190 .test_ib = gfx_v10_0_ring_test_ib, 9191 .insert_nop = amdgpu_ring_insert_nop, 9192 .pad_ib = amdgpu_ring_generic_pad_ib, 9193 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9194 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9195 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9196 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9197 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9198 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9199 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9200 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9201 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9202 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9203 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9204 }; 9205 9206 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9207 .type = AMDGPU_RING_TYPE_COMPUTE, 9208 .align_mask = 0xff, 9209 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9210 .support_64bit_ptrs = true, 9211 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9212 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9213 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9214 .emit_frame_size = 9215 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9216 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9217 5 + /* hdp invalidate */ 9218 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9219 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9220 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9221 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9222 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9223 8, /* gfx_v10_0_emit_mem_sync */ 9224 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9225 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9226 .emit_fence = gfx_v10_0_ring_emit_fence, 9227 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9228 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9229 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9230 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9231 .test_ring = gfx_v10_0_ring_test_ring, 9232 .test_ib = gfx_v10_0_ring_test_ib, 9233 .insert_nop = amdgpu_ring_insert_nop, 9234 .pad_ib = amdgpu_ring_generic_pad_ib, 9235 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9236 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9237 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9238 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9239 }; 9240 9241 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9242 .type = AMDGPU_RING_TYPE_KIQ, 9243 .align_mask = 0xff, 9244 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9245 .support_64bit_ptrs = true, 9246 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9247 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9248 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9249 .emit_frame_size = 9250 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9251 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9252 5 + /*hdp invalidate */ 9253 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9254 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9255 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9256 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9257 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9258 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9259 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9260 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9261 .test_ring = gfx_v10_0_ring_test_ring, 9262 .test_ib = gfx_v10_0_ring_test_ib, 9263 .insert_nop = amdgpu_ring_insert_nop, 9264 .pad_ib = amdgpu_ring_generic_pad_ib, 9265 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9266 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9267 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9268 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9269 }; 9270 9271 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9272 { 9273 int i; 9274 9275 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9276 9277 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9278 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9279 9280 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9281 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9282 } 9283 9284 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9285 .set = gfx_v10_0_set_eop_interrupt_state, 9286 .process = gfx_v10_0_eop_irq, 9287 }; 9288 9289 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9290 .set = gfx_v10_0_set_priv_reg_fault_state, 9291 .process = gfx_v10_0_priv_reg_irq, 9292 }; 9293 9294 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9295 .set = gfx_v10_0_set_priv_inst_fault_state, 9296 .process = gfx_v10_0_priv_inst_irq, 9297 }; 9298 9299 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9300 .set = gfx_v10_0_kiq_set_interrupt_state, 9301 .process = gfx_v10_0_kiq_irq, 9302 }; 9303 9304 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9305 { 9306 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9307 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9308 9309 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9310 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9311 9312 adev->gfx.priv_reg_irq.num_types = 1; 9313 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9314 9315 adev->gfx.priv_inst_irq.num_types = 1; 9316 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9317 } 9318 9319 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9320 { 9321 switch (adev->ip_versions[GC_HWIP][0]) { 9322 case IP_VERSION(10, 1, 10): 9323 case IP_VERSION(10, 1, 1): 9324 case IP_VERSION(10, 1, 3): 9325 case IP_VERSION(10, 1, 4): 9326 case IP_VERSION(10, 3, 2): 9327 case IP_VERSION(10, 3, 1): 9328 case IP_VERSION(10, 3, 4): 9329 case IP_VERSION(10, 3, 5): 9330 case IP_VERSION(10, 3, 6): 9331 case IP_VERSION(10, 3, 3): 9332 case IP_VERSION(10, 3, 7): 9333 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9334 break; 9335 case IP_VERSION(10, 1, 2): 9336 case IP_VERSION(10, 3, 0): 9337 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9338 break; 9339 default: 9340 break; 9341 } 9342 } 9343 9344 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9345 { 9346 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 9347 adev->gfx.config.max_sh_per_se * 9348 adev->gfx.config.max_shader_engines; 9349 9350 adev->gds.gds_size = 0x10000; 9351 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9352 adev->gds.gws_size = 64; 9353 adev->gds.oa_size = 16; 9354 } 9355 9356 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9357 { 9358 /* set gfx eng mqd */ 9359 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9360 sizeof(struct v10_gfx_mqd); 9361 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9362 gfx_v10_0_gfx_mqd_init; 9363 /* set compute eng mqd */ 9364 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9365 sizeof(struct v10_compute_mqd); 9366 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9367 gfx_v10_0_compute_mqd_init; 9368 } 9369 9370 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9371 u32 bitmap) 9372 { 9373 u32 data; 9374 9375 if (!bitmap) 9376 return; 9377 9378 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9379 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9380 9381 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9382 } 9383 9384 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9385 { 9386 u32 disabled_mask = 9387 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9388 u32 efuse_setting = 0; 9389 u32 vbios_setting = 0; 9390 9391 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9392 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9393 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9394 9395 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9396 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9397 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9398 9399 disabled_mask |= efuse_setting | vbios_setting; 9400 9401 return (~disabled_mask); 9402 } 9403 9404 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9405 { 9406 u32 wgp_idx, wgp_active_bitmap; 9407 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9408 9409 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9410 cu_active_bitmap = 0; 9411 9412 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9413 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9414 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9415 if (wgp_active_bitmap & (1 << wgp_idx)) 9416 cu_active_bitmap |= cu_bitmap_per_wgp; 9417 } 9418 9419 return cu_active_bitmap; 9420 } 9421 9422 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9423 struct amdgpu_cu_info *cu_info) 9424 { 9425 int i, j, k, counter, active_cu_number = 0; 9426 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9427 unsigned int disable_masks[4 * 2]; 9428 9429 if (!adev || !cu_info) 9430 return -EINVAL; 9431 9432 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9433 9434 mutex_lock(&adev->grbm_idx_mutex); 9435 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9436 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9437 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9438 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 9439 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 9440 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) || 9441 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) && 9442 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9443 continue; 9444 mask = 1; 9445 ao_bitmap = 0; 9446 counter = 0; 9447 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 9448 if (i < 4 && j < 2) 9449 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9450 adev, disable_masks[i * 2 + j]); 9451 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9452 cu_info->bitmap[0][i][j] = bitmap; 9453 9454 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9455 if (bitmap & mask) { 9456 if (counter < adev->gfx.config.max_cu_per_sh) 9457 ao_bitmap |= mask; 9458 counter++; 9459 } 9460 mask <<= 1; 9461 } 9462 active_cu_number += counter; 9463 if (i < 2 && j < 2) 9464 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9465 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9466 } 9467 } 9468 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 9469 mutex_unlock(&adev->grbm_idx_mutex); 9470 9471 cu_info->number = active_cu_number; 9472 cu_info->ao_cu_mask = ao_cu_mask; 9473 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9474 9475 return 0; 9476 } 9477 9478 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9479 { 9480 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9481 9482 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9483 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9484 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9485 9486 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9487 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9488 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9489 9490 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9491 adev->gfx.config.max_shader_engines); 9492 disabled_sa = efuse_setting | vbios_setting; 9493 disabled_sa &= max_sa_mask; 9494 9495 return disabled_sa; 9496 } 9497 9498 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9499 { 9500 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9501 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9502 9503 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9504 9505 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9506 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9507 max_shader_engines = adev->gfx.config.max_shader_engines; 9508 9509 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9510 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9511 disabled_sa_per_se &= max_sa_per_se_mask; 9512 if (disabled_sa_per_se == max_sa_per_se_mask) { 9513 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9514 break; 9515 } 9516 } 9517 } 9518 9519 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9520 { 9521 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9522 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9523 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9524 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9525 9526 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9527 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9528 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9529 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9530 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9531 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9532 9533 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9534 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9535 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9536 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9537 9538 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9539 9540 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9541 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9542 } 9543 9544 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 9545 .type = AMD_IP_BLOCK_TYPE_GFX, 9546 .major = 10, 9547 .minor = 0, 9548 .rev = 0, 9549 .funcs = &gfx_v10_0_ip_funcs, 9550 }; 9551