1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "smuio/smuio_11_0_0_offset.h" 39 #include "smuio/smuio_11_0_0_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "soc15_common.h" 47 #include "clearstate_gfx10.h" 48 #include "v10_structs.h" 49 #include "gfx_v10_0.h" 50 #include "nbio_v2_3.h" 51 52 /** 53 * Navi10 has two graphic rings to share each graphic pipe. 54 * 1. Primary ring 55 * 2. Async ring 56 */ 57 #define GFX10_NUM_GFX_RINGS_NV1X 1 58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 59 #define GFX10_MEC_HPD_SIZE 2048 60 61 #define F32_CE_PROGRAM_RAM_SIZE 65536 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 64 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 70 71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 73 74 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 76 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 101 102 #define mmCGTS_TCC_DISABLE_Vangogh 0x5006 103 #define mmCGTS_TCC_DISABLE_Vangogh_BASE_IDX 1 104 #define mmCGTS_USER_TCC_DISABLE_Vangogh 0x5007 105 #define mmCGTS_USER_TCC_DISABLE_Vangogh_BASE_IDX 1 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 107 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 109 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 110 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 111 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 113 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 115 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 116 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 117 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 118 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 119 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 120 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 121 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 122 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 123 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 124 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 125 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 126 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 127 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 128 129 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 131 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 133 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 135 #define mmCP_HYP_CE_UCODE_DATA 0x5819 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 137 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 139 #define mmCP_HYP_ME_UCODE_DATA 0x5817 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 141 142 #define mmCPG_PSP_DEBUG 0x5c10 143 #define mmCPG_PSP_DEBUG_BASE_IDX 1 144 #define mmCPC_PSP_DEBUG 0x5c11 145 #define mmCPC_PSP_DEBUG_BASE_IDX 1 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 148 149 //CC_GC_SA_UNIT_DISABLE 150 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 154 //GC_USER_SA_UNIT_DISABLE 155 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 159 //PA_SC_ENHANCE_3 160 #define mmPA_SC_ENHANCE_3 0x1085 161 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 164 165 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 167 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 172 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 175 176 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 177 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 178 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 179 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 180 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 181 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 182 183 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 184 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 185 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 186 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 187 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 188 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 189 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 190 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 191 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 192 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 193 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 194 195 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 196 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 197 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 198 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 199 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 200 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 201 202 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 203 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 204 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 205 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 206 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 208 209 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 210 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 211 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 212 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 213 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 214 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 215 216 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 217 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 218 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 219 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 220 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 221 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 222 223 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 224 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 225 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 226 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 227 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 229 230 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 231 { 232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 272 }; 273 274 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 275 { 276 /* Pending on emulation bring up */ 277 }; 278 279 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 280 { 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1333 }; 1334 1335 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1336 { 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1375 }; 1376 1377 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1378 { 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 1419 }; 1420 1421 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 1422 { 1423 static void *scratch_reg0; 1424 static void *scratch_reg1; 1425 static void *spare_int; 1426 uint32_t i = 0; 1427 uint32_t retries = 50000; 1428 1429 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 1430 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 1431 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 1432 1433 if (amdgpu_sriov_runtime(adev)) { 1434 pr_err("shouldn't call rlcg write register during runtime\n"); 1435 return; 1436 } 1437 1438 writel(v, scratch_reg0); 1439 writel(offset | 0x80000000, scratch_reg1); 1440 writel(1, spare_int); 1441 for (i = 0; i < retries; i++) { 1442 u32 tmp; 1443 1444 tmp = readl(scratch_reg1); 1445 if (!(tmp & 0x80000000)) 1446 break; 1447 1448 udelay(10); 1449 } 1450 1451 if (i >= retries) 1452 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 1453 } 1454 1455 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1456 { 1457 /* Pending on emulation bring up */ 1458 }; 1459 1460 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1461 { 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2082 }; 2083 2084 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2085 { 2086 /* Pending on emulation bring up */ 2087 }; 2088 2089 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2090 { 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3143 }; 3144 3145 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3146 { 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3189 }; 3190 3191 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3192 { 3193 /* Pending on emulation bring up */ 3194 }; 3195 3196 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3197 { 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3239 3240 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3242 }; 3243 3244 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3245 { 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3269 3270 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3272 }; 3273 3274 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3275 { 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3311 }; 3312 3313 #define DEFAULT_SH_MEM_CONFIG \ 3314 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3315 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3316 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3317 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3318 3319 3320 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3321 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3322 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3323 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3324 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3325 struct amdgpu_cu_info *cu_info); 3326 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3327 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3328 u32 sh_num, u32 instance); 3329 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3330 3331 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3332 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3333 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3334 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3335 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3336 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3337 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3338 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3339 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3340 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3341 3342 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3343 { 3344 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3345 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3346 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3347 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3348 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3349 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3350 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3351 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3352 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3353 } 3354 3355 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3356 struct amdgpu_ring *ring) 3357 { 3358 struct amdgpu_device *adev = kiq_ring->adev; 3359 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3360 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3361 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3362 3363 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3364 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3365 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3366 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3367 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3368 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3369 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3370 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3371 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3372 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3373 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3374 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3375 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3376 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3377 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3378 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3379 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3380 } 3381 3382 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3383 struct amdgpu_ring *ring, 3384 enum amdgpu_unmap_queues_action action, 3385 u64 gpu_addr, u64 seq) 3386 { 3387 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3388 3389 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3390 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3391 PACKET3_UNMAP_QUEUES_ACTION(action) | 3392 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3393 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3394 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3395 amdgpu_ring_write(kiq_ring, 3396 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3397 3398 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3399 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3400 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3401 amdgpu_ring_write(kiq_ring, seq); 3402 } else { 3403 amdgpu_ring_write(kiq_ring, 0); 3404 amdgpu_ring_write(kiq_ring, 0); 3405 amdgpu_ring_write(kiq_ring, 0); 3406 } 3407 } 3408 3409 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3410 struct amdgpu_ring *ring, 3411 u64 addr, 3412 u64 seq) 3413 { 3414 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3415 3416 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3417 amdgpu_ring_write(kiq_ring, 3418 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3419 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3420 PACKET3_QUERY_STATUS_COMMAND(2)); 3421 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3422 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3423 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3424 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3425 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3426 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3427 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3428 } 3429 3430 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3431 uint16_t pasid, uint32_t flush_type, 3432 bool all_hub) 3433 { 3434 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3435 amdgpu_ring_write(kiq_ring, 3436 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3437 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3438 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3439 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3440 } 3441 3442 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3443 .kiq_set_resources = gfx10_kiq_set_resources, 3444 .kiq_map_queues = gfx10_kiq_map_queues, 3445 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3446 .kiq_query_status = gfx10_kiq_query_status, 3447 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3448 .set_resources_size = 8, 3449 .map_queues_size = 7, 3450 .unmap_queues_size = 6, 3451 .query_status_size = 7, 3452 .invalidate_tlbs_size = 2, 3453 }; 3454 3455 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3456 { 3457 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3458 } 3459 3460 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3461 { 3462 switch (adev->asic_type) { 3463 case CHIP_NAVI10: 3464 soc15_program_register_sequence(adev, 3465 golden_settings_gc_rlc_spm_10_0_nv10, 3466 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3467 break; 3468 case CHIP_NAVI14: 3469 soc15_program_register_sequence(adev, 3470 golden_settings_gc_rlc_spm_10_1_nv14, 3471 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3472 break; 3473 case CHIP_NAVI12: 3474 soc15_program_register_sequence(adev, 3475 golden_settings_gc_rlc_spm_10_1_2_nv12, 3476 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3477 break; 3478 default: 3479 break; 3480 } 3481 } 3482 3483 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3484 { 3485 switch (adev->asic_type) { 3486 case CHIP_NAVI10: 3487 soc15_program_register_sequence(adev, 3488 golden_settings_gc_10_1, 3489 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3490 soc15_program_register_sequence(adev, 3491 golden_settings_gc_10_0_nv10, 3492 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3493 break; 3494 case CHIP_NAVI14: 3495 soc15_program_register_sequence(adev, 3496 golden_settings_gc_10_1_1, 3497 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3498 soc15_program_register_sequence(adev, 3499 golden_settings_gc_10_1_nv14, 3500 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3501 break; 3502 case CHIP_NAVI12: 3503 soc15_program_register_sequence(adev, 3504 golden_settings_gc_10_1_2, 3505 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3506 soc15_program_register_sequence(adev, 3507 golden_settings_gc_10_1_2_nv12, 3508 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3509 break; 3510 case CHIP_SIENNA_CICHLID: 3511 soc15_program_register_sequence(adev, 3512 golden_settings_gc_10_3, 3513 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3514 soc15_program_register_sequence(adev, 3515 golden_settings_gc_10_3_sienna_cichlid, 3516 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3517 break; 3518 case CHIP_NAVY_FLOUNDER: 3519 soc15_program_register_sequence(adev, 3520 golden_settings_gc_10_3_2, 3521 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3522 break; 3523 case CHIP_VANGOGH: 3524 soc15_program_register_sequence(adev, 3525 golden_settings_gc_10_3_vangogh, 3526 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3527 break; 3528 case CHIP_DIMGREY_CAVEFISH: 3529 soc15_program_register_sequence(adev, 3530 golden_settings_gc_10_3_4, 3531 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3532 break; 3533 default: 3534 break; 3535 } 3536 gfx_v10_0_init_spm_golden_registers(adev); 3537 } 3538 3539 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3540 { 3541 adev->gfx.scratch.num_reg = 8; 3542 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3543 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3544 } 3545 3546 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3547 bool wc, uint32_t reg, uint32_t val) 3548 { 3549 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3550 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3551 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3552 amdgpu_ring_write(ring, reg); 3553 amdgpu_ring_write(ring, 0); 3554 amdgpu_ring_write(ring, val); 3555 } 3556 3557 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3558 int mem_space, int opt, uint32_t addr0, 3559 uint32_t addr1, uint32_t ref, uint32_t mask, 3560 uint32_t inv) 3561 { 3562 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3563 amdgpu_ring_write(ring, 3564 /* memory (1) or register (0) */ 3565 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3566 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3567 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3568 WAIT_REG_MEM_ENGINE(eng_sel))); 3569 3570 if (mem_space) 3571 BUG_ON(addr0 & 0x3); /* Dword align */ 3572 amdgpu_ring_write(ring, addr0); 3573 amdgpu_ring_write(ring, addr1); 3574 amdgpu_ring_write(ring, ref); 3575 amdgpu_ring_write(ring, mask); 3576 amdgpu_ring_write(ring, inv); /* poll interval */ 3577 } 3578 3579 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3580 { 3581 struct amdgpu_device *adev = ring->adev; 3582 uint32_t scratch; 3583 uint32_t tmp = 0; 3584 unsigned i; 3585 int r; 3586 3587 r = amdgpu_gfx_scratch_get(adev, &scratch); 3588 if (r) { 3589 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3590 return r; 3591 } 3592 3593 WREG32(scratch, 0xCAFEDEAD); 3594 3595 r = amdgpu_ring_alloc(ring, 3); 3596 if (r) { 3597 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3598 ring->idx, r); 3599 amdgpu_gfx_scratch_free(adev, scratch); 3600 return r; 3601 } 3602 3603 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3604 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3605 amdgpu_ring_write(ring, 0xDEADBEEF); 3606 amdgpu_ring_commit(ring); 3607 3608 for (i = 0; i < adev->usec_timeout; i++) { 3609 tmp = RREG32(scratch); 3610 if (tmp == 0xDEADBEEF) 3611 break; 3612 if (amdgpu_emu_mode == 1) 3613 msleep(1); 3614 else 3615 udelay(1); 3616 } 3617 3618 if (i >= adev->usec_timeout) 3619 r = -ETIMEDOUT; 3620 3621 amdgpu_gfx_scratch_free(adev, scratch); 3622 3623 return r; 3624 } 3625 3626 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3627 { 3628 struct amdgpu_device *adev = ring->adev; 3629 struct amdgpu_ib ib; 3630 struct dma_fence *f = NULL; 3631 unsigned index; 3632 uint64_t gpu_addr; 3633 uint32_t tmp; 3634 long r; 3635 3636 r = amdgpu_device_wb_get(adev, &index); 3637 if (r) 3638 return r; 3639 3640 gpu_addr = adev->wb.gpu_addr + (index * 4); 3641 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3642 memset(&ib, 0, sizeof(ib)); 3643 r = amdgpu_ib_get(adev, NULL, 16, 3644 AMDGPU_IB_POOL_DIRECT, &ib); 3645 if (r) 3646 goto err1; 3647 3648 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3649 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3650 ib.ptr[2] = lower_32_bits(gpu_addr); 3651 ib.ptr[3] = upper_32_bits(gpu_addr); 3652 ib.ptr[4] = 0xDEADBEEF; 3653 ib.length_dw = 5; 3654 3655 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3656 if (r) 3657 goto err2; 3658 3659 r = dma_fence_wait_timeout(f, false, timeout); 3660 if (r == 0) { 3661 r = -ETIMEDOUT; 3662 goto err2; 3663 } else if (r < 0) { 3664 goto err2; 3665 } 3666 3667 tmp = adev->wb.wb[index]; 3668 if (tmp == 0xDEADBEEF) 3669 r = 0; 3670 else 3671 r = -EINVAL; 3672 err2: 3673 amdgpu_ib_free(adev, &ib, NULL); 3674 dma_fence_put(f); 3675 err1: 3676 amdgpu_device_wb_free(adev, index); 3677 return r; 3678 } 3679 3680 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3681 { 3682 release_firmware(adev->gfx.pfp_fw); 3683 adev->gfx.pfp_fw = NULL; 3684 release_firmware(adev->gfx.me_fw); 3685 adev->gfx.me_fw = NULL; 3686 release_firmware(adev->gfx.ce_fw); 3687 adev->gfx.ce_fw = NULL; 3688 release_firmware(adev->gfx.rlc_fw); 3689 adev->gfx.rlc_fw = NULL; 3690 release_firmware(adev->gfx.mec_fw); 3691 adev->gfx.mec_fw = NULL; 3692 release_firmware(adev->gfx.mec2_fw); 3693 adev->gfx.mec2_fw = NULL; 3694 3695 kfree(adev->gfx.rlc.register_list_format); 3696 } 3697 3698 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3699 { 3700 adev->gfx.cp_fw_write_wait = false; 3701 3702 switch (adev->asic_type) { 3703 case CHIP_NAVI10: 3704 case CHIP_NAVI12: 3705 case CHIP_NAVI14: 3706 if ((adev->gfx.me_fw_version >= 0x00000046) && 3707 (adev->gfx.me_feature_version >= 27) && 3708 (adev->gfx.pfp_fw_version >= 0x00000068) && 3709 (adev->gfx.pfp_feature_version >= 27) && 3710 (adev->gfx.mec_fw_version >= 0x0000005b) && 3711 (adev->gfx.mec_feature_version >= 27)) 3712 adev->gfx.cp_fw_write_wait = true; 3713 break; 3714 case CHIP_SIENNA_CICHLID: 3715 case CHIP_NAVY_FLOUNDER: 3716 case CHIP_VANGOGH: 3717 case CHIP_DIMGREY_CAVEFISH: 3718 adev->gfx.cp_fw_write_wait = true; 3719 break; 3720 default: 3721 break; 3722 } 3723 3724 if (!adev->gfx.cp_fw_write_wait) 3725 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3726 } 3727 3728 3729 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3730 { 3731 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3732 3733 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 3734 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 3735 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 3736 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 3737 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 3738 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 3739 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 3740 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 3741 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 3742 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 3743 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 3744 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 3745 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 3746 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 3747 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 3748 } 3749 3750 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 3751 { 3752 const struct rlc_firmware_header_v2_2 *rlc_hdr; 3753 3754 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 3755 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 3756 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 3757 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 3758 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 3759 } 3760 3761 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3762 { 3763 bool ret = false; 3764 3765 switch (adev->pdev->revision) { 3766 case 0xc2: 3767 case 0xc3: 3768 ret = true; 3769 break; 3770 default: 3771 ret = false; 3772 break; 3773 } 3774 3775 return ret ; 3776 } 3777 3778 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3779 { 3780 switch (adev->asic_type) { 3781 case CHIP_NAVI10: 3782 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3783 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3784 break; 3785 case CHIP_VANGOGH: 3786 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3787 break; 3788 default: 3789 break; 3790 } 3791 } 3792 3793 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3794 { 3795 const char *chip_name; 3796 char fw_name[40]; 3797 char wks[10]; 3798 int err; 3799 struct amdgpu_firmware_info *info = NULL; 3800 const struct common_firmware_header *header = NULL; 3801 const struct gfx_firmware_header_v1_0 *cp_hdr; 3802 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3803 unsigned int *tmp = NULL; 3804 unsigned int i = 0; 3805 uint16_t version_major; 3806 uint16_t version_minor; 3807 3808 DRM_DEBUG("\n"); 3809 3810 memset(wks, 0, sizeof(wks)); 3811 switch (adev->asic_type) { 3812 case CHIP_NAVI10: 3813 chip_name = "navi10"; 3814 break; 3815 case CHIP_NAVI14: 3816 chip_name = "navi14"; 3817 if (!(adev->pdev->device == 0x7340 && 3818 adev->pdev->revision != 0x00)) 3819 snprintf(wks, sizeof(wks), "_wks"); 3820 break; 3821 case CHIP_NAVI12: 3822 chip_name = "navi12"; 3823 break; 3824 case CHIP_SIENNA_CICHLID: 3825 chip_name = "sienna_cichlid"; 3826 break; 3827 case CHIP_NAVY_FLOUNDER: 3828 chip_name = "navy_flounder"; 3829 break; 3830 case CHIP_VANGOGH: 3831 chip_name = "vangogh"; 3832 break; 3833 case CHIP_DIMGREY_CAVEFISH: 3834 chip_name = "dimgrey_cavefish"; 3835 break; 3836 default: 3837 BUG(); 3838 } 3839 3840 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 3841 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 3842 if (err) 3843 goto out; 3844 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 3845 if (err) 3846 goto out; 3847 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3848 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3849 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3850 3851 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 3852 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 3853 if (err) 3854 goto out; 3855 err = amdgpu_ucode_validate(adev->gfx.me_fw); 3856 if (err) 3857 goto out; 3858 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3859 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3860 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3861 3862 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 3863 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 3864 if (err) 3865 goto out; 3866 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 3867 if (err) 3868 goto out; 3869 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3870 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3871 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3872 3873 if (!amdgpu_sriov_vf(adev)) { 3874 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 3875 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 3876 if (err) 3877 goto out; 3878 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 3879 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3880 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 3881 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 3882 3883 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 3884 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 3885 adev->gfx.rlc.save_and_restore_offset = 3886 le32_to_cpu(rlc_hdr->save_and_restore_offset); 3887 adev->gfx.rlc.clear_state_descriptor_offset = 3888 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 3889 adev->gfx.rlc.avail_scratch_ram_locations = 3890 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 3891 adev->gfx.rlc.reg_restore_list_size = 3892 le32_to_cpu(rlc_hdr->reg_restore_list_size); 3893 adev->gfx.rlc.reg_list_format_start = 3894 le32_to_cpu(rlc_hdr->reg_list_format_start); 3895 adev->gfx.rlc.reg_list_format_separate_start = 3896 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 3897 adev->gfx.rlc.starting_offsets_start = 3898 le32_to_cpu(rlc_hdr->starting_offsets_start); 3899 adev->gfx.rlc.reg_list_format_size_bytes = 3900 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 3901 adev->gfx.rlc.reg_list_size_bytes = 3902 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 3903 adev->gfx.rlc.register_list_format = 3904 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 3905 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 3906 if (!adev->gfx.rlc.register_list_format) { 3907 err = -ENOMEM; 3908 goto out; 3909 } 3910 3911 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3912 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 3913 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 3914 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 3915 3916 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 3917 3918 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3919 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 3920 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 3921 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 3922 3923 if (version_major == 2) { 3924 if (version_minor >= 1) 3925 gfx_v10_0_init_rlc_ext_microcode(adev); 3926 if (version_minor == 2) 3927 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 3928 } 3929 } 3930 3931 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 3932 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 3933 if (err) 3934 goto out; 3935 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 3936 if (err) 3937 goto out; 3938 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3939 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3940 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3941 3942 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 3943 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 3944 if (!err) { 3945 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 3946 if (err) 3947 goto out; 3948 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 3949 adev->gfx.mec2_fw->data; 3950 adev->gfx.mec2_fw_version = 3951 le32_to_cpu(cp_hdr->header.ucode_version); 3952 adev->gfx.mec2_feature_version = 3953 le32_to_cpu(cp_hdr->ucode_feature_version); 3954 } else { 3955 err = 0; 3956 adev->gfx.mec2_fw = NULL; 3957 } 3958 3959 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 3960 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 3961 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 3962 info->fw = adev->gfx.pfp_fw; 3963 header = (const struct common_firmware_header *)info->fw->data; 3964 adev->firmware.fw_size += 3965 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3966 3967 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 3968 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 3969 info->fw = adev->gfx.me_fw; 3970 header = (const struct common_firmware_header *)info->fw->data; 3971 adev->firmware.fw_size += 3972 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3973 3974 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 3975 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 3976 info->fw = adev->gfx.ce_fw; 3977 header = (const struct common_firmware_header *)info->fw->data; 3978 adev->firmware.fw_size += 3979 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3980 3981 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 3982 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 3983 info->fw = adev->gfx.rlc_fw; 3984 if (info->fw) { 3985 header = (const struct common_firmware_header *)info->fw->data; 3986 adev->firmware.fw_size += 3987 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3988 } 3989 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 3990 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 3991 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 3992 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 3993 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 3994 info->fw = adev->gfx.rlc_fw; 3995 adev->firmware.fw_size += 3996 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 3997 3998 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 3999 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 4000 info->fw = adev->gfx.rlc_fw; 4001 adev->firmware.fw_size += 4002 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 4003 4004 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 4005 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 4006 info->fw = adev->gfx.rlc_fw; 4007 adev->firmware.fw_size += 4008 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 4009 4010 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 4011 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 4012 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 4013 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 4014 info->fw = adev->gfx.rlc_fw; 4015 adev->firmware.fw_size += 4016 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4017 4018 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4019 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4020 info->fw = adev->gfx.rlc_fw; 4021 adev->firmware.fw_size += 4022 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4023 } 4024 } 4025 4026 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4027 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4028 info->fw = adev->gfx.mec_fw; 4029 header = (const struct common_firmware_header *)info->fw->data; 4030 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4031 adev->firmware.fw_size += 4032 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4033 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4034 4035 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4036 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4037 info->fw = adev->gfx.mec_fw; 4038 adev->firmware.fw_size += 4039 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4040 4041 if (adev->gfx.mec2_fw) { 4042 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4043 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4044 info->fw = adev->gfx.mec2_fw; 4045 header = (const struct common_firmware_header *)info->fw->data; 4046 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4047 adev->firmware.fw_size += 4048 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4049 le32_to_cpu(cp_hdr->jt_size) * 4, 4050 PAGE_SIZE); 4051 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4052 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4053 info->fw = adev->gfx.mec2_fw; 4054 adev->firmware.fw_size += 4055 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4056 PAGE_SIZE); 4057 } 4058 } 4059 4060 gfx_v10_0_check_fw_write_wait(adev); 4061 out: 4062 if (err) { 4063 dev_err(adev->dev, 4064 "gfx10: Failed to load firmware \"%s\"\n", 4065 fw_name); 4066 release_firmware(adev->gfx.pfp_fw); 4067 adev->gfx.pfp_fw = NULL; 4068 release_firmware(adev->gfx.me_fw); 4069 adev->gfx.me_fw = NULL; 4070 release_firmware(adev->gfx.ce_fw); 4071 adev->gfx.ce_fw = NULL; 4072 release_firmware(adev->gfx.rlc_fw); 4073 adev->gfx.rlc_fw = NULL; 4074 release_firmware(adev->gfx.mec_fw); 4075 adev->gfx.mec_fw = NULL; 4076 release_firmware(adev->gfx.mec2_fw); 4077 adev->gfx.mec2_fw = NULL; 4078 } 4079 4080 gfx_v10_0_check_gfxoff_flag(adev); 4081 4082 return err; 4083 } 4084 4085 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4086 { 4087 u32 count = 0; 4088 const struct cs_section_def *sect = NULL; 4089 const struct cs_extent_def *ext = NULL; 4090 4091 /* begin clear state */ 4092 count += 2; 4093 /* context control state */ 4094 count += 3; 4095 4096 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4097 for (ext = sect->section; ext->extent != NULL; ++ext) { 4098 if (sect->id == SECT_CONTEXT) 4099 count += 2 + ext->reg_count; 4100 else 4101 return 0; 4102 } 4103 } 4104 4105 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4106 count += 3; 4107 /* end clear state */ 4108 count += 2; 4109 /* clear state */ 4110 count += 2; 4111 4112 return count; 4113 } 4114 4115 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4116 volatile u32 *buffer) 4117 { 4118 u32 count = 0, i; 4119 const struct cs_section_def *sect = NULL; 4120 const struct cs_extent_def *ext = NULL; 4121 int ctx_reg_offset; 4122 4123 if (adev->gfx.rlc.cs_data == NULL) 4124 return; 4125 if (buffer == NULL) 4126 return; 4127 4128 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4129 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4130 4131 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4132 buffer[count++] = cpu_to_le32(0x80000000); 4133 buffer[count++] = cpu_to_le32(0x80000000); 4134 4135 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4136 for (ext = sect->section; ext->extent != NULL; ++ext) { 4137 if (sect->id == SECT_CONTEXT) { 4138 buffer[count++] = 4139 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4140 buffer[count++] = cpu_to_le32(ext->reg_index - 4141 PACKET3_SET_CONTEXT_REG_START); 4142 for (i = 0; i < ext->reg_count; i++) 4143 buffer[count++] = cpu_to_le32(ext->extent[i]); 4144 } else { 4145 return; 4146 } 4147 } 4148 } 4149 4150 ctx_reg_offset = 4151 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4152 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4153 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4154 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4155 4156 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4157 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4158 4159 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4160 buffer[count++] = cpu_to_le32(0); 4161 } 4162 4163 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4164 { 4165 /* clear state block */ 4166 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4167 &adev->gfx.rlc.clear_state_gpu_addr, 4168 (void **)&adev->gfx.rlc.cs_ptr); 4169 4170 /* jump table block */ 4171 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4172 &adev->gfx.rlc.cp_table_gpu_addr, 4173 (void **)&adev->gfx.rlc.cp_table_ptr); 4174 } 4175 4176 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4177 { 4178 const struct cs_section_def *cs_data; 4179 int r; 4180 4181 adev->gfx.rlc.cs_data = gfx10_cs_data; 4182 4183 cs_data = adev->gfx.rlc.cs_data; 4184 4185 if (cs_data) { 4186 /* init clear state block */ 4187 r = amdgpu_gfx_rlc_init_csb(adev); 4188 if (r) 4189 return r; 4190 } 4191 4192 /* init spm vmid with 0xf */ 4193 if (adev->gfx.rlc.funcs->update_spm_vmid) 4194 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4195 4196 return 0; 4197 } 4198 4199 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4200 { 4201 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4202 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4203 } 4204 4205 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4206 { 4207 int r; 4208 4209 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4210 4211 amdgpu_gfx_graphics_queue_acquire(adev); 4212 4213 r = gfx_v10_0_init_microcode(adev); 4214 if (r) 4215 DRM_ERROR("Failed to load gfx firmware!\n"); 4216 4217 return r; 4218 } 4219 4220 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4221 { 4222 int r; 4223 u32 *hpd; 4224 const __le32 *fw_data = NULL; 4225 unsigned fw_size; 4226 u32 *fw = NULL; 4227 size_t mec_hpd_size; 4228 4229 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4230 4231 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4232 4233 /* take ownership of the relevant compute queues */ 4234 amdgpu_gfx_compute_queue_acquire(adev); 4235 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4236 4237 if (mec_hpd_size) { 4238 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4239 AMDGPU_GEM_DOMAIN_GTT, 4240 &adev->gfx.mec.hpd_eop_obj, 4241 &adev->gfx.mec.hpd_eop_gpu_addr, 4242 (void **)&hpd); 4243 if (r) { 4244 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4245 gfx_v10_0_mec_fini(adev); 4246 return r; 4247 } 4248 4249 memset(hpd, 0, mec_hpd_size); 4250 4251 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4252 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4253 } 4254 4255 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4256 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4257 4258 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4259 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4260 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4261 4262 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4263 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4264 &adev->gfx.mec.mec_fw_obj, 4265 &adev->gfx.mec.mec_fw_gpu_addr, 4266 (void **)&fw); 4267 if (r) { 4268 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4269 gfx_v10_0_mec_fini(adev); 4270 return r; 4271 } 4272 4273 memcpy(fw, fw_data, fw_size); 4274 4275 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4276 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4277 } 4278 4279 return 0; 4280 } 4281 4282 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4283 { 4284 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4285 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4286 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4287 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4288 } 4289 4290 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4291 uint32_t thread, uint32_t regno, 4292 uint32_t num, uint32_t *out) 4293 { 4294 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4295 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4296 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4297 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4298 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4299 while (num--) 4300 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4301 } 4302 4303 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4304 { 4305 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4306 * field when performing a select_se_sh so it should be 4307 * zero here */ 4308 WARN_ON(simd != 0); 4309 4310 /* type 2 wave data */ 4311 dst[(*no_fields)++] = 2; 4312 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4313 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4314 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4315 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4316 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4317 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4318 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4319 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4320 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4321 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4322 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4323 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4324 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4325 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4326 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4327 } 4328 4329 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4330 uint32_t wave, uint32_t start, 4331 uint32_t size, uint32_t *dst) 4332 { 4333 WARN_ON(simd != 0); 4334 4335 wave_read_regs( 4336 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4337 dst); 4338 } 4339 4340 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4341 uint32_t wave, uint32_t thread, 4342 uint32_t start, uint32_t size, 4343 uint32_t *dst) 4344 { 4345 wave_read_regs( 4346 adev, wave, thread, 4347 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4348 } 4349 4350 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4351 u32 me, u32 pipe, u32 q, u32 vm) 4352 { 4353 nv_grbm_select(adev, me, pipe, q, vm); 4354 } 4355 4356 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4357 bool enable) 4358 { 4359 uint32_t data, def; 4360 4361 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4362 4363 if (enable) 4364 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4365 else 4366 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4367 4368 if (data != def) 4369 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4370 } 4371 4372 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4373 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4374 .select_se_sh = &gfx_v10_0_select_se_sh, 4375 .read_wave_data = &gfx_v10_0_read_wave_data, 4376 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4377 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4378 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4379 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4380 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4381 }; 4382 4383 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4384 { 4385 u32 gb_addr_config; 4386 4387 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4388 4389 switch (adev->asic_type) { 4390 case CHIP_NAVI10: 4391 case CHIP_NAVI14: 4392 case CHIP_NAVI12: 4393 adev->gfx.config.max_hw_contexts = 8; 4394 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4395 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4396 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4397 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4398 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4399 break; 4400 case CHIP_SIENNA_CICHLID: 4401 case CHIP_NAVY_FLOUNDER: 4402 case CHIP_VANGOGH: 4403 case CHIP_DIMGREY_CAVEFISH: 4404 adev->gfx.config.max_hw_contexts = 8; 4405 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4406 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4407 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4408 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4409 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4410 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4411 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4412 break; 4413 default: 4414 BUG(); 4415 break; 4416 } 4417 4418 adev->gfx.config.gb_addr_config = gb_addr_config; 4419 4420 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4421 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4422 GB_ADDR_CONFIG, NUM_PIPES); 4423 4424 adev->gfx.config.max_tile_pipes = 4425 adev->gfx.config.gb_addr_config_fields.num_pipes; 4426 4427 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4428 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4429 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4430 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4431 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4432 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4433 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4434 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4435 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4436 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4437 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4438 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4439 } 4440 4441 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4442 int me, int pipe, int queue) 4443 { 4444 int r; 4445 struct amdgpu_ring *ring; 4446 unsigned int irq_type; 4447 4448 ring = &adev->gfx.gfx_ring[ring_id]; 4449 4450 ring->me = me; 4451 ring->pipe = pipe; 4452 ring->queue = queue; 4453 4454 ring->ring_obj = NULL; 4455 ring->use_doorbell = true; 4456 4457 if (!ring_id) 4458 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4459 else 4460 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4461 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4462 4463 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4464 r = amdgpu_ring_init(adev, ring, 1024, 4465 &adev->gfx.eop_irq, irq_type, 4466 AMDGPU_RING_PRIO_DEFAULT); 4467 if (r) 4468 return r; 4469 return 0; 4470 } 4471 4472 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4473 int mec, int pipe, int queue) 4474 { 4475 int r; 4476 unsigned irq_type; 4477 struct amdgpu_ring *ring; 4478 unsigned int hw_prio; 4479 4480 ring = &adev->gfx.compute_ring[ring_id]; 4481 4482 /* mec0 is me1 */ 4483 ring->me = mec + 1; 4484 ring->pipe = pipe; 4485 ring->queue = queue; 4486 4487 ring->ring_obj = NULL; 4488 ring->use_doorbell = true; 4489 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4490 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4491 + (ring_id * GFX10_MEC_HPD_SIZE); 4492 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4493 4494 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4495 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4496 + ring->pipe; 4497 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 4498 ring->queue) ? 4499 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4500 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4501 r = amdgpu_ring_init(adev, ring, 1024, 4502 &adev->gfx.eop_irq, irq_type, hw_prio); 4503 if (r) 4504 return r; 4505 4506 return 0; 4507 } 4508 4509 static int gfx_v10_0_sw_init(void *handle) 4510 { 4511 int i, j, k, r, ring_id = 0; 4512 struct amdgpu_kiq *kiq; 4513 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4514 4515 switch (adev->asic_type) { 4516 case CHIP_NAVI10: 4517 case CHIP_NAVI14: 4518 case CHIP_NAVI12: 4519 adev->gfx.me.num_me = 1; 4520 adev->gfx.me.num_pipe_per_me = 1; 4521 adev->gfx.me.num_queue_per_pipe = 1; 4522 adev->gfx.mec.num_mec = 2; 4523 adev->gfx.mec.num_pipe_per_mec = 4; 4524 adev->gfx.mec.num_queue_per_pipe = 8; 4525 break; 4526 case CHIP_SIENNA_CICHLID: 4527 case CHIP_NAVY_FLOUNDER: 4528 case CHIP_VANGOGH: 4529 case CHIP_DIMGREY_CAVEFISH: 4530 adev->gfx.me.num_me = 1; 4531 adev->gfx.me.num_pipe_per_me = 1; 4532 adev->gfx.me.num_queue_per_pipe = 1; 4533 adev->gfx.mec.num_mec = 2; 4534 adev->gfx.mec.num_pipe_per_mec = 4; 4535 adev->gfx.mec.num_queue_per_pipe = 4; 4536 break; 4537 default: 4538 adev->gfx.me.num_me = 1; 4539 adev->gfx.me.num_pipe_per_me = 1; 4540 adev->gfx.me.num_queue_per_pipe = 1; 4541 adev->gfx.mec.num_mec = 1; 4542 adev->gfx.mec.num_pipe_per_mec = 4; 4543 adev->gfx.mec.num_queue_per_pipe = 8; 4544 break; 4545 } 4546 4547 /* KIQ event */ 4548 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4549 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4550 &adev->gfx.kiq.irq); 4551 if (r) 4552 return r; 4553 4554 /* EOP Event */ 4555 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4556 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4557 &adev->gfx.eop_irq); 4558 if (r) 4559 return r; 4560 4561 /* Privileged reg */ 4562 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4563 &adev->gfx.priv_reg_irq); 4564 if (r) 4565 return r; 4566 4567 /* Privileged inst */ 4568 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4569 &adev->gfx.priv_inst_irq); 4570 if (r) 4571 return r; 4572 4573 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4574 4575 gfx_v10_0_scratch_init(adev); 4576 4577 r = gfx_v10_0_me_init(adev); 4578 if (r) 4579 return r; 4580 4581 r = gfx_v10_0_rlc_init(adev); 4582 if (r) { 4583 DRM_ERROR("Failed to init rlc BOs!\n"); 4584 return r; 4585 } 4586 4587 r = gfx_v10_0_mec_init(adev); 4588 if (r) { 4589 DRM_ERROR("Failed to init MEC BOs!\n"); 4590 return r; 4591 } 4592 4593 /* set up the gfx ring */ 4594 for (i = 0; i < adev->gfx.me.num_me; i++) { 4595 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4596 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4597 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4598 continue; 4599 4600 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4601 i, k, j); 4602 if (r) 4603 return r; 4604 ring_id++; 4605 } 4606 } 4607 } 4608 4609 ring_id = 0; 4610 /* set up the compute queues - allocate horizontally across pipes */ 4611 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4612 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4613 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4614 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4615 j)) 4616 continue; 4617 4618 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4619 i, k, j); 4620 if (r) 4621 return r; 4622 4623 ring_id++; 4624 } 4625 } 4626 } 4627 4628 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4629 if (r) { 4630 DRM_ERROR("Failed to init KIQ BOs!\n"); 4631 return r; 4632 } 4633 4634 kiq = &adev->gfx.kiq; 4635 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4636 if (r) 4637 return r; 4638 4639 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4640 if (r) 4641 return r; 4642 4643 /* allocate visible FB for rlc auto-loading fw */ 4644 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4645 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4646 if (r) 4647 return r; 4648 } 4649 4650 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4651 4652 gfx_v10_0_gpu_early_init(adev); 4653 4654 return 0; 4655 } 4656 4657 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4658 { 4659 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4660 &adev->gfx.pfp.pfp_fw_gpu_addr, 4661 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4662 } 4663 4664 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4665 { 4666 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4667 &adev->gfx.ce.ce_fw_gpu_addr, 4668 (void **)&adev->gfx.ce.ce_fw_ptr); 4669 } 4670 4671 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4672 { 4673 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4674 &adev->gfx.me.me_fw_gpu_addr, 4675 (void **)&adev->gfx.me.me_fw_ptr); 4676 } 4677 4678 static int gfx_v10_0_sw_fini(void *handle) 4679 { 4680 int i; 4681 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4682 4683 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4684 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4685 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4686 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4687 4688 amdgpu_gfx_mqd_sw_fini(adev); 4689 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4690 amdgpu_gfx_kiq_fini(adev); 4691 4692 gfx_v10_0_pfp_fini(adev); 4693 gfx_v10_0_ce_fini(adev); 4694 gfx_v10_0_me_fini(adev); 4695 gfx_v10_0_rlc_fini(adev); 4696 gfx_v10_0_mec_fini(adev); 4697 4698 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4699 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4700 4701 gfx_v10_0_free_microcode(adev); 4702 4703 return 0; 4704 } 4705 4706 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4707 u32 sh_num, u32 instance) 4708 { 4709 u32 data; 4710 4711 if (instance == 0xffffffff) 4712 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4713 INSTANCE_BROADCAST_WRITES, 1); 4714 else 4715 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4716 instance); 4717 4718 if (se_num == 0xffffffff) 4719 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4720 1); 4721 else 4722 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4723 4724 if (sh_num == 0xffffffff) 4725 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4726 1); 4727 else 4728 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4729 4730 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4731 } 4732 4733 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4734 { 4735 u32 data, mask; 4736 4737 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4738 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4739 4740 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4741 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4742 4743 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4744 adev->gfx.config.max_sh_per_se); 4745 4746 return (~data) & mask; 4747 } 4748 4749 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4750 { 4751 int i, j; 4752 u32 data; 4753 u32 active_rbs = 0; 4754 u32 bitmap; 4755 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4756 adev->gfx.config.max_sh_per_se; 4757 4758 mutex_lock(&adev->grbm_idx_mutex); 4759 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4760 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4761 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4762 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 4763 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4764 continue; 4765 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4766 data = gfx_v10_0_get_rb_active_bitmap(adev); 4767 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4768 rb_bitmap_width_per_sh); 4769 } 4770 } 4771 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4772 mutex_unlock(&adev->grbm_idx_mutex); 4773 4774 adev->gfx.config.backend_enable_mask = active_rbs; 4775 adev->gfx.config.num_rbs = hweight32(active_rbs); 4776 } 4777 4778 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4779 { 4780 uint32_t num_sc; 4781 uint32_t enabled_rb_per_sh; 4782 uint32_t active_rb_bitmap; 4783 uint32_t num_rb_per_sc; 4784 uint32_t num_packer_per_sc; 4785 uint32_t pa_sc_tile_steering_override; 4786 4787 /* for ASICs that integrates GFX v10.3 4788 * pa_sc_tile_steering_override should be set to 0 */ 4789 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 4790 return 0; 4791 4792 /* init num_sc */ 4793 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4794 adev->gfx.config.num_sc_per_sh; 4795 /* init num_rb_per_sc */ 4796 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4797 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4798 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4799 /* init num_packer_per_sc */ 4800 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4801 4802 pa_sc_tile_steering_override = 0; 4803 pa_sc_tile_steering_override |= 4804 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4805 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4806 pa_sc_tile_steering_override |= 4807 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4808 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4809 pa_sc_tile_steering_override |= 4810 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4811 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4812 4813 return pa_sc_tile_steering_override; 4814 } 4815 4816 #define DEFAULT_SH_MEM_BASES (0x6000) 4817 4818 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4819 { 4820 int i; 4821 uint32_t sh_mem_bases; 4822 4823 /* 4824 * Configure apertures: 4825 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4826 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4827 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4828 */ 4829 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4830 4831 mutex_lock(&adev->srbm_mutex); 4832 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4833 nv_grbm_select(adev, 0, 0, 0, i); 4834 /* CP and shaders */ 4835 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4836 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4837 } 4838 nv_grbm_select(adev, 0, 0, 0, 0); 4839 mutex_unlock(&adev->srbm_mutex); 4840 4841 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4842 acccess. These should be enabled by FW for target VMIDs. */ 4843 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4844 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4845 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4846 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4847 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4848 } 4849 } 4850 4851 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4852 { 4853 int vmid; 4854 4855 /* 4856 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4857 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4858 * the driver can enable them for graphics. VMID0 should maintain 4859 * access so that HWS firmware can save/restore entries. 4860 */ 4861 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4862 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4863 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4864 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4865 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4866 } 4867 } 4868 4869 4870 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4871 { 4872 int i, j, k; 4873 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4874 u32 tmp, wgp_active_bitmap = 0; 4875 u32 gcrd_targets_disable_tcp = 0; 4876 u32 utcl_invreq_disable = 0; 4877 /* 4878 * GCRD_TARGETS_DISABLE field contains 4879 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4880 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4881 */ 4882 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4883 2 * max_wgp_per_sh + /* TCP */ 4884 max_wgp_per_sh + /* SQC */ 4885 4); /* GL1C */ 4886 /* 4887 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4888 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4889 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4890 */ 4891 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4892 2 * max_wgp_per_sh + /* TCP */ 4893 2 * max_wgp_per_sh + /* SQC */ 4894 4 + /* RMI */ 4895 1); /* SQG */ 4896 4897 if (adev->asic_type == CHIP_NAVI10 || 4898 adev->asic_type == CHIP_NAVI14 || 4899 adev->asic_type == CHIP_NAVI12) { 4900 mutex_lock(&adev->grbm_idx_mutex); 4901 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4902 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4903 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4904 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4905 /* 4906 * Set corresponding TCP bits for the inactive WGPs in 4907 * GCRD_SA_TARGETS_DISABLE 4908 */ 4909 gcrd_targets_disable_tcp = 0; 4910 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4911 utcl_invreq_disable = 0; 4912 4913 for (k = 0; k < max_wgp_per_sh; k++) { 4914 if (!(wgp_active_bitmap & (1 << k))) { 4915 gcrd_targets_disable_tcp |= 3 << (2 * k); 4916 utcl_invreq_disable |= (3 << (2 * k)) | 4917 (3 << (2 * (max_wgp_per_sh + k))); 4918 } 4919 } 4920 4921 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4922 /* only override TCP & SQC bits */ 4923 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 4924 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4925 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4926 4927 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4928 /* only override TCP bits */ 4929 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 4930 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4931 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4932 } 4933 } 4934 4935 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4936 mutex_unlock(&adev->grbm_idx_mutex); 4937 } 4938 } 4939 4940 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4941 { 4942 /* TCCs are global (not instanced). */ 4943 uint32_t tcc_disable; 4944 4945 switch (adev->asic_type) { 4946 case CHIP_VANGOGH: 4947 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_Vangogh) | 4948 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_Vangogh); 4949 break; 4950 default: 4951 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4952 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4953 break; 4954 } 4955 4956 adev->gfx.config.tcc_disabled_mask = 4957 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4958 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4959 } 4960 4961 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4962 { 4963 u32 tmp; 4964 int i; 4965 4966 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4967 4968 gfx_v10_0_setup_rb(adev); 4969 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4970 gfx_v10_0_get_tcc_info(adev); 4971 adev->gfx.config.pa_sc_tile_steering_override = 4972 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4973 4974 /* XXX SH_MEM regs */ 4975 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4976 mutex_lock(&adev->srbm_mutex); 4977 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 4978 nv_grbm_select(adev, 0, 0, 0, i); 4979 /* CP and shaders */ 4980 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4981 if (i != 0) { 4982 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4983 (adev->gmc.private_aperture_start >> 48)); 4984 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4985 (adev->gmc.shared_aperture_start >> 48)); 4986 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4987 } 4988 } 4989 nv_grbm_select(adev, 0, 0, 0, 0); 4990 4991 mutex_unlock(&adev->srbm_mutex); 4992 4993 gfx_v10_0_init_compute_vmid(adev); 4994 gfx_v10_0_init_gds_vmid(adev); 4995 4996 } 4997 4998 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 4999 bool enable) 5000 { 5001 u32 tmp; 5002 5003 if (amdgpu_sriov_vf(adev)) 5004 return; 5005 5006 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5007 5008 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5009 enable ? 1 : 0); 5010 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5011 enable ? 1 : 0); 5012 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5013 enable ? 1 : 0); 5014 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5015 enable ? 1 : 0); 5016 5017 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5018 } 5019 5020 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5021 { 5022 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5023 5024 /* csib */ 5025 if (adev->asic_type == CHIP_NAVI12) { 5026 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5027 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5028 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5029 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5030 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5031 } else { 5032 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5033 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5034 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5035 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5036 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5037 } 5038 return 0; 5039 } 5040 5041 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5042 { 5043 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5044 5045 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5046 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5047 } 5048 5049 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5050 { 5051 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5052 udelay(50); 5053 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5054 udelay(50); 5055 } 5056 5057 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5058 bool enable) 5059 { 5060 uint32_t rlc_pg_cntl; 5061 5062 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5063 5064 if (!enable) { 5065 /* RLC_PG_CNTL[23] = 0 (default) 5066 * RLC will wait for handshake acks with SMU 5067 * GFXOFF will be enabled 5068 * RLC_PG_CNTL[23] = 1 5069 * RLC will not issue any message to SMU 5070 * hence no handshake between SMU & RLC 5071 * GFXOFF will be disabled 5072 */ 5073 rlc_pg_cntl |= 0x800000; 5074 } else 5075 rlc_pg_cntl &= ~0x800000; 5076 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5077 } 5078 5079 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5080 { 5081 /* TODO: enable rlc & smu handshake until smu 5082 * and gfxoff feature works as expected */ 5083 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5084 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5085 5086 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5087 udelay(50); 5088 } 5089 5090 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5091 { 5092 uint32_t tmp; 5093 5094 /* enable Save Restore Machine */ 5095 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 5096 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5097 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5098 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 5099 } 5100 5101 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5102 { 5103 const struct rlc_firmware_header_v2_0 *hdr; 5104 const __le32 *fw_data; 5105 unsigned i, fw_size; 5106 5107 if (!adev->gfx.rlc_fw) 5108 return -EINVAL; 5109 5110 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5111 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5112 5113 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5114 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5115 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5116 5117 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5118 RLCG_UCODE_LOADING_START_ADDRESS); 5119 5120 for (i = 0; i < fw_size; i++) 5121 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5122 le32_to_cpup(fw_data++)); 5123 5124 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5125 5126 return 0; 5127 } 5128 5129 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5130 { 5131 int r; 5132 5133 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 5134 5135 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5136 if (r) 5137 return r; 5138 5139 gfx_v10_0_init_csb(adev); 5140 5141 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5142 gfx_v10_0_rlc_enable_srm(adev); 5143 } else { 5144 if (amdgpu_sriov_vf(adev)) { 5145 gfx_v10_0_init_csb(adev); 5146 return 0; 5147 } 5148 5149 adev->gfx.rlc.funcs->stop(adev); 5150 5151 /* disable CG */ 5152 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5153 5154 /* disable PG */ 5155 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5156 5157 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5158 /* legacy rlc firmware loading */ 5159 r = gfx_v10_0_rlc_load_microcode(adev); 5160 if (r) 5161 return r; 5162 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5163 /* rlc backdoor autoload firmware */ 5164 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5165 if (r) 5166 return r; 5167 } 5168 5169 gfx_v10_0_init_csb(adev); 5170 5171 adev->gfx.rlc.funcs->start(adev); 5172 5173 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5174 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5175 if (r) 5176 return r; 5177 } 5178 } 5179 return 0; 5180 } 5181 5182 static struct { 5183 FIRMWARE_ID id; 5184 unsigned int offset; 5185 unsigned int size; 5186 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5187 5188 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5189 { 5190 int ret; 5191 RLC_TABLE_OF_CONTENT *rlc_toc; 5192 5193 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 5194 AMDGPU_GEM_DOMAIN_GTT, 5195 &adev->gfx.rlc.rlc_toc_bo, 5196 &adev->gfx.rlc.rlc_toc_gpu_addr, 5197 (void **)&adev->gfx.rlc.rlc_toc_buf); 5198 if (ret) { 5199 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5200 return ret; 5201 } 5202 5203 /* Copy toc from psp sos fw to rlc toc buffer */ 5204 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 5205 5206 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5207 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5208 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5209 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5210 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5211 /* Offset needs 4KB alignment */ 5212 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5213 } 5214 5215 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5216 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5217 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5218 5219 rlc_toc++; 5220 } 5221 5222 return 0; 5223 } 5224 5225 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5226 { 5227 uint32_t total_size = 0; 5228 FIRMWARE_ID id; 5229 int ret; 5230 5231 ret = gfx_v10_0_parse_rlc_toc(adev); 5232 if (ret) { 5233 dev_err(adev->dev, "failed to parse rlc toc\n"); 5234 return 0; 5235 } 5236 5237 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5238 total_size += rlc_autoload_info[id].size; 5239 5240 /* In case the offset in rlc toc ucode is aligned */ 5241 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5242 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5243 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5244 5245 return total_size; 5246 } 5247 5248 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5249 { 5250 int r; 5251 uint32_t total_size; 5252 5253 total_size = gfx_v10_0_calc_toc_total_size(adev); 5254 5255 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5256 AMDGPU_GEM_DOMAIN_GTT, 5257 &adev->gfx.rlc.rlc_autoload_bo, 5258 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5259 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5260 if (r) { 5261 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5262 return r; 5263 } 5264 5265 return 0; 5266 } 5267 5268 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5269 { 5270 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5271 &adev->gfx.rlc.rlc_toc_gpu_addr, 5272 (void **)&adev->gfx.rlc.rlc_toc_buf); 5273 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5274 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5275 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5276 } 5277 5278 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5279 FIRMWARE_ID id, 5280 const void *fw_data, 5281 uint32_t fw_size) 5282 { 5283 uint32_t toc_offset; 5284 uint32_t toc_fw_size; 5285 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5286 5287 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5288 return; 5289 5290 toc_offset = rlc_autoload_info[id].offset; 5291 toc_fw_size = rlc_autoload_info[id].size; 5292 5293 if (fw_size == 0) 5294 fw_size = toc_fw_size; 5295 5296 if (fw_size > toc_fw_size) 5297 fw_size = toc_fw_size; 5298 5299 memcpy(ptr + toc_offset, fw_data, fw_size); 5300 5301 if (fw_size < toc_fw_size) 5302 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5303 } 5304 5305 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5306 { 5307 void *data; 5308 uint32_t size; 5309 5310 data = adev->gfx.rlc.rlc_toc_buf; 5311 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5312 5313 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5314 FIRMWARE_ID_RLC_TOC, 5315 data, size); 5316 } 5317 5318 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5319 { 5320 const __le32 *fw_data; 5321 uint32_t fw_size; 5322 const struct gfx_firmware_header_v1_0 *cp_hdr; 5323 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5324 5325 /* pfp ucode */ 5326 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5327 adev->gfx.pfp_fw->data; 5328 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5329 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5330 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5331 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5332 FIRMWARE_ID_CP_PFP, 5333 fw_data, fw_size); 5334 5335 /* ce ucode */ 5336 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5337 adev->gfx.ce_fw->data; 5338 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5339 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5340 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5341 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5342 FIRMWARE_ID_CP_CE, 5343 fw_data, fw_size); 5344 5345 /* me ucode */ 5346 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5347 adev->gfx.me_fw->data; 5348 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5349 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5350 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5351 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5352 FIRMWARE_ID_CP_ME, 5353 fw_data, fw_size); 5354 5355 /* rlc ucode */ 5356 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5357 adev->gfx.rlc_fw->data; 5358 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5359 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5360 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5361 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5362 FIRMWARE_ID_RLC_G_UCODE, 5363 fw_data, fw_size); 5364 5365 /* mec1 ucode */ 5366 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5367 adev->gfx.mec_fw->data; 5368 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5369 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5370 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5371 cp_hdr->jt_size * 4; 5372 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5373 FIRMWARE_ID_CP_MEC, 5374 fw_data, fw_size); 5375 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5376 } 5377 5378 /* Temporarily put sdma part here */ 5379 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5380 { 5381 const __le32 *fw_data; 5382 uint32_t fw_size; 5383 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5384 int i; 5385 5386 for (i = 0; i < adev->sdma.num_instances; i++) { 5387 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5388 adev->sdma.instance[i].fw->data; 5389 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5390 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5391 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5392 5393 if (i == 0) { 5394 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5395 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5396 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5397 FIRMWARE_ID_SDMA0_JT, 5398 (uint32_t *)fw_data + 5399 sdma_hdr->jt_offset, 5400 sdma_hdr->jt_size * 4); 5401 } else if (i == 1) { 5402 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5403 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5404 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5405 FIRMWARE_ID_SDMA1_JT, 5406 (uint32_t *)fw_data + 5407 sdma_hdr->jt_offset, 5408 sdma_hdr->jt_size * 4); 5409 } 5410 } 5411 } 5412 5413 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5414 { 5415 uint32_t rlc_g_offset, rlc_g_size, tmp; 5416 uint64_t gpu_addr; 5417 5418 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5419 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5420 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5421 5422 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5423 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5424 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5425 5426 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5427 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5428 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5429 5430 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5431 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5432 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5433 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5434 return -EINVAL; 5435 } 5436 5437 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5438 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5439 DRM_ERROR("RLC ROM should halt itself\n"); 5440 return -EINVAL; 5441 } 5442 5443 return 0; 5444 } 5445 5446 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5447 { 5448 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5449 uint32_t tmp; 5450 int i; 5451 uint64_t addr; 5452 5453 /* Trigger an invalidation of the L1 instruction caches */ 5454 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5455 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5456 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5457 5458 /* Wait for invalidation complete */ 5459 for (i = 0; i < usec_timeout; i++) { 5460 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5461 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5462 INVALIDATE_CACHE_COMPLETE)) 5463 break; 5464 udelay(1); 5465 } 5466 5467 if (i >= usec_timeout) { 5468 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5469 return -EINVAL; 5470 } 5471 5472 /* Program me ucode address into intruction cache address register */ 5473 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5474 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5475 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5476 lower_32_bits(addr) & 0xFFFFF000); 5477 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5478 upper_32_bits(addr)); 5479 5480 return 0; 5481 } 5482 5483 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5484 { 5485 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5486 uint32_t tmp; 5487 int i; 5488 uint64_t addr; 5489 5490 /* Trigger an invalidation of the L1 instruction caches */ 5491 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5492 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5493 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5494 5495 /* Wait for invalidation complete */ 5496 for (i = 0; i < usec_timeout; i++) { 5497 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5498 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5499 INVALIDATE_CACHE_COMPLETE)) 5500 break; 5501 udelay(1); 5502 } 5503 5504 if (i >= usec_timeout) { 5505 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5506 return -EINVAL; 5507 } 5508 5509 /* Program ce ucode address into intruction cache address register */ 5510 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5511 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5512 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5513 lower_32_bits(addr) & 0xFFFFF000); 5514 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5515 upper_32_bits(addr)); 5516 5517 return 0; 5518 } 5519 5520 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5521 { 5522 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5523 uint32_t tmp; 5524 int i; 5525 uint64_t addr; 5526 5527 /* Trigger an invalidation of the L1 instruction caches */ 5528 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5529 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5530 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5531 5532 /* Wait for invalidation complete */ 5533 for (i = 0; i < usec_timeout; i++) { 5534 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5535 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5536 INVALIDATE_CACHE_COMPLETE)) 5537 break; 5538 udelay(1); 5539 } 5540 5541 if (i >= usec_timeout) { 5542 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5543 return -EINVAL; 5544 } 5545 5546 /* Program pfp ucode address into intruction cache address register */ 5547 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5548 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5549 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5550 lower_32_bits(addr) & 0xFFFFF000); 5551 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5552 upper_32_bits(addr)); 5553 5554 return 0; 5555 } 5556 5557 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5558 { 5559 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5560 uint32_t tmp; 5561 int i; 5562 uint64_t addr; 5563 5564 /* Trigger an invalidation of the L1 instruction caches */ 5565 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5566 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5567 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5568 5569 /* Wait for invalidation complete */ 5570 for (i = 0; i < usec_timeout; i++) { 5571 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5572 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5573 INVALIDATE_CACHE_COMPLETE)) 5574 break; 5575 udelay(1); 5576 } 5577 5578 if (i >= usec_timeout) { 5579 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5580 return -EINVAL; 5581 } 5582 5583 /* Program mec1 ucode address into intruction cache address register */ 5584 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5585 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5586 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5587 lower_32_bits(addr) & 0xFFFFF000); 5588 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5589 upper_32_bits(addr)); 5590 5591 return 0; 5592 } 5593 5594 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5595 { 5596 uint32_t cp_status; 5597 uint32_t bootload_status; 5598 int i, r; 5599 5600 for (i = 0; i < adev->usec_timeout; i++) { 5601 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5602 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5603 if ((cp_status == 0) && 5604 (REG_GET_FIELD(bootload_status, 5605 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5606 break; 5607 } 5608 udelay(1); 5609 } 5610 5611 if (i >= adev->usec_timeout) { 5612 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5613 return -ETIMEDOUT; 5614 } 5615 5616 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5617 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5618 if (r) 5619 return r; 5620 5621 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5622 if (r) 5623 return r; 5624 5625 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5626 if (r) 5627 return r; 5628 5629 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5630 if (r) 5631 return r; 5632 } 5633 5634 return 0; 5635 } 5636 5637 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5638 { 5639 int i; 5640 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5641 5642 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5643 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5644 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5645 5646 if (adev->asic_type == CHIP_NAVI12) { 5647 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5648 } else { 5649 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5650 } 5651 5652 for (i = 0; i < adev->usec_timeout; i++) { 5653 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5654 break; 5655 udelay(1); 5656 } 5657 5658 if (i >= adev->usec_timeout) 5659 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5660 5661 return 0; 5662 } 5663 5664 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5665 { 5666 int r; 5667 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5668 const __le32 *fw_data; 5669 unsigned i, fw_size; 5670 uint32_t tmp; 5671 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5672 5673 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5674 adev->gfx.pfp_fw->data; 5675 5676 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5677 5678 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5679 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5680 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5681 5682 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5683 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5684 &adev->gfx.pfp.pfp_fw_obj, 5685 &adev->gfx.pfp.pfp_fw_gpu_addr, 5686 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5687 if (r) { 5688 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5689 gfx_v10_0_pfp_fini(adev); 5690 return r; 5691 } 5692 5693 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5694 5695 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5696 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5697 5698 /* Trigger an invalidation of the L1 instruction caches */ 5699 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5700 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5701 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5702 5703 /* Wait for invalidation complete */ 5704 for (i = 0; i < usec_timeout; i++) { 5705 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5706 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5707 INVALIDATE_CACHE_COMPLETE)) 5708 break; 5709 udelay(1); 5710 } 5711 5712 if (i >= usec_timeout) { 5713 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5714 return -EINVAL; 5715 } 5716 5717 if (amdgpu_emu_mode == 1) 5718 adev->nbio.funcs->hdp_flush(adev, NULL); 5719 5720 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5721 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5722 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5723 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5724 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5725 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5726 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5727 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5728 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5729 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5730 5731 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5732 5733 for (i = 0; i < pfp_hdr->jt_size; i++) 5734 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5735 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5736 5737 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5738 5739 return 0; 5740 } 5741 5742 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5743 { 5744 int r; 5745 const struct gfx_firmware_header_v1_0 *ce_hdr; 5746 const __le32 *fw_data; 5747 unsigned i, fw_size; 5748 uint32_t tmp; 5749 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5750 5751 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5752 adev->gfx.ce_fw->data; 5753 5754 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5755 5756 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5757 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5758 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5759 5760 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5761 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5762 &adev->gfx.ce.ce_fw_obj, 5763 &adev->gfx.ce.ce_fw_gpu_addr, 5764 (void **)&adev->gfx.ce.ce_fw_ptr); 5765 if (r) { 5766 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5767 gfx_v10_0_ce_fini(adev); 5768 return r; 5769 } 5770 5771 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5772 5773 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5774 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5775 5776 /* Trigger an invalidation of the L1 instruction caches */ 5777 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5778 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5779 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5780 5781 /* Wait for invalidation complete */ 5782 for (i = 0; i < usec_timeout; i++) { 5783 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5784 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5785 INVALIDATE_CACHE_COMPLETE)) 5786 break; 5787 udelay(1); 5788 } 5789 5790 if (i >= usec_timeout) { 5791 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5792 return -EINVAL; 5793 } 5794 5795 if (amdgpu_emu_mode == 1) 5796 adev->nbio.funcs->hdp_flush(adev, NULL); 5797 5798 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5799 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5800 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5801 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5802 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5803 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5804 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5805 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5806 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5807 5808 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5809 5810 for (i = 0; i < ce_hdr->jt_size; i++) 5811 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5812 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5813 5814 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5815 5816 return 0; 5817 } 5818 5819 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5820 { 5821 int r; 5822 const struct gfx_firmware_header_v1_0 *me_hdr; 5823 const __le32 *fw_data; 5824 unsigned i, fw_size; 5825 uint32_t tmp; 5826 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5827 5828 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5829 adev->gfx.me_fw->data; 5830 5831 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5832 5833 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5834 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5835 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5836 5837 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5838 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5839 &adev->gfx.me.me_fw_obj, 5840 &adev->gfx.me.me_fw_gpu_addr, 5841 (void **)&adev->gfx.me.me_fw_ptr); 5842 if (r) { 5843 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5844 gfx_v10_0_me_fini(adev); 5845 return r; 5846 } 5847 5848 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5849 5850 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5851 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5852 5853 /* Trigger an invalidation of the L1 instruction caches */ 5854 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5855 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5856 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5857 5858 /* Wait for invalidation complete */ 5859 for (i = 0; i < usec_timeout; i++) { 5860 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5861 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5862 INVALIDATE_CACHE_COMPLETE)) 5863 break; 5864 udelay(1); 5865 } 5866 5867 if (i >= usec_timeout) { 5868 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5869 return -EINVAL; 5870 } 5871 5872 if (amdgpu_emu_mode == 1) 5873 adev->nbio.funcs->hdp_flush(adev, NULL); 5874 5875 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5876 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5877 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5878 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5879 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5880 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5881 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5882 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5883 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5884 5885 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5886 5887 for (i = 0; i < me_hdr->jt_size; i++) 5888 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5889 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5890 5891 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5892 5893 return 0; 5894 } 5895 5896 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5897 { 5898 int r; 5899 5900 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5901 return -EINVAL; 5902 5903 gfx_v10_0_cp_gfx_enable(adev, false); 5904 5905 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5906 if (r) { 5907 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5908 return r; 5909 } 5910 5911 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5912 if (r) { 5913 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5914 return r; 5915 } 5916 5917 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5918 if (r) { 5919 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5920 return r; 5921 } 5922 5923 return 0; 5924 } 5925 5926 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5927 { 5928 struct amdgpu_ring *ring; 5929 const struct cs_section_def *sect = NULL; 5930 const struct cs_extent_def *ext = NULL; 5931 int r, i; 5932 int ctx_reg_offset; 5933 5934 /* init the CP */ 5935 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5936 adev->gfx.config.max_hw_contexts - 1); 5937 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5938 5939 gfx_v10_0_cp_gfx_enable(adev, true); 5940 5941 ring = &adev->gfx.gfx_ring[0]; 5942 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5943 if (r) { 5944 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5945 return r; 5946 } 5947 5948 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5949 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5950 5951 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5952 amdgpu_ring_write(ring, 0x80000000); 5953 amdgpu_ring_write(ring, 0x80000000); 5954 5955 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5956 for (ext = sect->section; ext->extent != NULL; ++ext) { 5957 if (sect->id == SECT_CONTEXT) { 5958 amdgpu_ring_write(ring, 5959 PACKET3(PACKET3_SET_CONTEXT_REG, 5960 ext->reg_count)); 5961 amdgpu_ring_write(ring, ext->reg_index - 5962 PACKET3_SET_CONTEXT_REG_START); 5963 for (i = 0; i < ext->reg_count; i++) 5964 amdgpu_ring_write(ring, ext->extent[i]); 5965 } 5966 } 5967 } 5968 5969 ctx_reg_offset = 5970 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5971 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5972 amdgpu_ring_write(ring, ctx_reg_offset); 5973 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5974 5975 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5976 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5977 5978 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5979 amdgpu_ring_write(ring, 0); 5980 5981 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 5982 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 5983 amdgpu_ring_write(ring, 0x8000); 5984 amdgpu_ring_write(ring, 0x8000); 5985 5986 amdgpu_ring_commit(ring); 5987 5988 /* submit cs packet to copy state 0 to next available state */ 5989 if (adev->gfx.num_gfx_rings > 1) { 5990 /* maximum supported gfx ring is 2 */ 5991 ring = &adev->gfx.gfx_ring[1]; 5992 r = amdgpu_ring_alloc(ring, 2); 5993 if (r) { 5994 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5995 return r; 5996 } 5997 5998 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5999 amdgpu_ring_write(ring, 0); 6000 6001 amdgpu_ring_commit(ring); 6002 } 6003 return 0; 6004 } 6005 6006 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6007 CP_PIPE_ID pipe) 6008 { 6009 u32 tmp; 6010 6011 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6012 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6013 6014 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6015 } 6016 6017 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6018 struct amdgpu_ring *ring) 6019 { 6020 u32 tmp; 6021 6022 if (!amdgpu_async_gfx_ring) { 6023 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6024 if (ring->use_doorbell) { 6025 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6026 DOORBELL_OFFSET, ring->doorbell_index); 6027 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6028 DOORBELL_EN, 1); 6029 } else { 6030 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6031 DOORBELL_EN, 0); 6032 } 6033 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6034 } 6035 switch (adev->asic_type) { 6036 case CHIP_SIENNA_CICHLID: 6037 case CHIP_NAVY_FLOUNDER: 6038 case CHIP_VANGOGH: 6039 case CHIP_DIMGREY_CAVEFISH: 6040 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6041 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6042 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6043 6044 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6045 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6046 break; 6047 default: 6048 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6049 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6050 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6051 6052 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6053 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6054 break; 6055 } 6056 } 6057 6058 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6059 { 6060 struct amdgpu_ring *ring; 6061 u32 tmp; 6062 u32 rb_bufsz; 6063 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6064 u32 i; 6065 6066 /* Set the write pointer delay */ 6067 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6068 6069 /* set the RB to use vmid 0 */ 6070 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6071 6072 /* Init gfx ring 0 for pipe 0 */ 6073 mutex_lock(&adev->srbm_mutex); 6074 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6075 6076 /* Set ring buffer size */ 6077 ring = &adev->gfx.gfx_ring[0]; 6078 rb_bufsz = order_base_2(ring->ring_size / 8); 6079 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6080 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6081 #ifdef __BIG_ENDIAN 6082 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6083 #endif 6084 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6085 6086 /* Initialize the ring buffer's write pointers */ 6087 ring->wptr = 0; 6088 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6089 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6090 6091 /* set the wb address wether it's enabled or not */ 6092 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6093 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6094 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6095 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6096 6097 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6098 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6099 lower_32_bits(wptr_gpu_addr)); 6100 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6101 upper_32_bits(wptr_gpu_addr)); 6102 6103 mdelay(1); 6104 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6105 6106 rb_addr = ring->gpu_addr >> 8; 6107 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6108 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6109 6110 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6111 6112 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6113 mutex_unlock(&adev->srbm_mutex); 6114 6115 /* Init gfx ring 1 for pipe 1 */ 6116 if (adev->gfx.num_gfx_rings > 1) { 6117 mutex_lock(&adev->srbm_mutex); 6118 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6119 /* maximum supported gfx ring is 2 */ 6120 ring = &adev->gfx.gfx_ring[1]; 6121 rb_bufsz = order_base_2(ring->ring_size / 8); 6122 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6123 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6124 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6125 /* Initialize the ring buffer's write pointers */ 6126 ring->wptr = 0; 6127 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6128 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6129 /* Set the wb address wether it's enabled or not */ 6130 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6131 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6132 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6133 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6134 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6135 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6136 lower_32_bits(wptr_gpu_addr)); 6137 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6138 upper_32_bits(wptr_gpu_addr)); 6139 6140 mdelay(1); 6141 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6142 6143 rb_addr = ring->gpu_addr >> 8; 6144 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6145 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6146 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6147 6148 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6149 mutex_unlock(&adev->srbm_mutex); 6150 } 6151 /* Switch to pipe 0 */ 6152 mutex_lock(&adev->srbm_mutex); 6153 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6154 mutex_unlock(&adev->srbm_mutex); 6155 6156 /* start the ring */ 6157 gfx_v10_0_cp_gfx_start(adev); 6158 6159 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6160 ring = &adev->gfx.gfx_ring[i]; 6161 ring->sched.ready = true; 6162 } 6163 6164 return 0; 6165 } 6166 6167 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6168 { 6169 if (enable) { 6170 switch (adev->asic_type) { 6171 case CHIP_SIENNA_CICHLID: 6172 case CHIP_NAVY_FLOUNDER: 6173 case CHIP_VANGOGH: 6174 case CHIP_DIMGREY_CAVEFISH: 6175 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6176 break; 6177 default: 6178 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6179 break; 6180 } 6181 } else { 6182 switch (adev->asic_type) { 6183 case CHIP_SIENNA_CICHLID: 6184 case CHIP_NAVY_FLOUNDER: 6185 case CHIP_VANGOGH: 6186 case CHIP_DIMGREY_CAVEFISH: 6187 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6188 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6189 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6190 break; 6191 default: 6192 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6193 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6194 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6195 break; 6196 } 6197 adev->gfx.kiq.ring.sched.ready = false; 6198 } 6199 udelay(50); 6200 } 6201 6202 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6203 { 6204 const struct gfx_firmware_header_v1_0 *mec_hdr; 6205 const __le32 *fw_data; 6206 unsigned i; 6207 u32 tmp; 6208 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6209 6210 if (!adev->gfx.mec_fw) 6211 return -EINVAL; 6212 6213 gfx_v10_0_cp_compute_enable(adev, false); 6214 6215 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6216 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6217 6218 fw_data = (const __le32 *) 6219 (adev->gfx.mec_fw->data + 6220 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6221 6222 /* Trigger an invalidation of the L1 instruction caches */ 6223 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6224 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6225 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6226 6227 /* Wait for invalidation complete */ 6228 for (i = 0; i < usec_timeout; i++) { 6229 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6230 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6231 INVALIDATE_CACHE_COMPLETE)) 6232 break; 6233 udelay(1); 6234 } 6235 6236 if (i >= usec_timeout) { 6237 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6238 return -EINVAL; 6239 } 6240 6241 if (amdgpu_emu_mode == 1) 6242 adev->nbio.funcs->hdp_flush(adev, NULL); 6243 6244 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6245 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6246 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6247 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6248 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6249 6250 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6251 0xFFFFF000); 6252 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6253 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6254 6255 /* MEC1 */ 6256 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6257 6258 for (i = 0; i < mec_hdr->jt_size; i++) 6259 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6260 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6261 6262 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6263 6264 /* 6265 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6266 * different microcode than MEC1. 6267 */ 6268 6269 return 0; 6270 } 6271 6272 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6273 { 6274 uint32_t tmp; 6275 struct amdgpu_device *adev = ring->adev; 6276 6277 /* tell RLC which is KIQ queue */ 6278 switch (adev->asic_type) { 6279 case CHIP_SIENNA_CICHLID: 6280 case CHIP_NAVY_FLOUNDER: 6281 case CHIP_VANGOGH: 6282 case CHIP_DIMGREY_CAVEFISH: 6283 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6284 tmp &= 0xffffff00; 6285 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6286 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6287 tmp |= 0x80; 6288 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6289 break; 6290 default: 6291 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6292 tmp &= 0xffffff00; 6293 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6294 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6295 tmp |= 0x80; 6296 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6297 break; 6298 } 6299 } 6300 6301 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6302 { 6303 struct amdgpu_device *adev = ring->adev; 6304 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6305 uint64_t hqd_gpu_addr, wb_gpu_addr; 6306 uint32_t tmp; 6307 uint32_t rb_bufsz; 6308 6309 /* set up gfx hqd wptr */ 6310 mqd->cp_gfx_hqd_wptr = 0; 6311 mqd->cp_gfx_hqd_wptr_hi = 0; 6312 6313 /* set the pointer to the MQD */ 6314 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6315 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6316 6317 /* set up mqd control */ 6318 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6319 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6320 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6321 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6322 mqd->cp_gfx_mqd_control = tmp; 6323 6324 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6325 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6326 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6327 mqd->cp_gfx_hqd_vmid = 0; 6328 6329 /* set up default queue priority level 6330 * 0x0 = low priority, 0x1 = high priority */ 6331 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6332 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6333 mqd->cp_gfx_hqd_queue_priority = tmp; 6334 6335 /* set up time quantum */ 6336 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6337 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6338 mqd->cp_gfx_hqd_quantum = tmp; 6339 6340 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6341 hqd_gpu_addr = ring->gpu_addr >> 8; 6342 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6343 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6344 6345 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6346 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6347 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6348 mqd->cp_gfx_hqd_rptr_addr_hi = 6349 upper_32_bits(wb_gpu_addr) & 0xffff; 6350 6351 /* set up rb_wptr_poll addr */ 6352 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6353 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6354 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6355 6356 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6357 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6358 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6359 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6360 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6361 #ifdef __BIG_ENDIAN 6362 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6363 #endif 6364 mqd->cp_gfx_hqd_cntl = tmp; 6365 6366 /* set up cp_doorbell_control */ 6367 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6368 if (ring->use_doorbell) { 6369 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6370 DOORBELL_OFFSET, ring->doorbell_index); 6371 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6372 DOORBELL_EN, 1); 6373 } else 6374 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6375 DOORBELL_EN, 0); 6376 mqd->cp_rb_doorbell_control = tmp; 6377 6378 /*if there are 2 gfx rings, set the lower doorbell range of the first ring, 6379 *otherwise the range of the second ring will override the first ring */ 6380 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6381 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6382 6383 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6384 ring->wptr = 0; 6385 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6386 6387 /* active the queue */ 6388 mqd->cp_gfx_hqd_active = 1; 6389 6390 return 0; 6391 } 6392 6393 #ifdef BRING_UP_DEBUG 6394 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6395 { 6396 struct amdgpu_device *adev = ring->adev; 6397 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6398 6399 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6400 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6401 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6402 6403 /* set GFX_MQD_BASE */ 6404 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6405 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6406 6407 /* set GFX_MQD_CONTROL */ 6408 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6409 6410 /* set GFX_HQD_VMID to 0 */ 6411 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6412 6413 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6414 mqd->cp_gfx_hqd_queue_priority); 6415 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6416 6417 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6418 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6419 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6420 6421 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6422 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6423 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6424 6425 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6426 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6427 6428 /* set RB_WPTR_POLL_ADDR */ 6429 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6430 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6431 6432 /* set RB_DOORBELL_CONTROL */ 6433 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6434 6435 /* active the queue */ 6436 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6437 6438 return 0; 6439 } 6440 #endif 6441 6442 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6443 { 6444 struct amdgpu_device *adev = ring->adev; 6445 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6446 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6447 6448 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6449 memset((void *)mqd, 0, sizeof(*mqd)); 6450 mutex_lock(&adev->srbm_mutex); 6451 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6452 gfx_v10_0_gfx_mqd_init(ring); 6453 #ifdef BRING_UP_DEBUG 6454 gfx_v10_0_gfx_queue_init_register(ring); 6455 #endif 6456 nv_grbm_select(adev, 0, 0, 0, 0); 6457 mutex_unlock(&adev->srbm_mutex); 6458 if (adev->gfx.me.mqd_backup[mqd_idx]) 6459 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6460 } else if (amdgpu_in_reset(adev)) { 6461 /* reset mqd with the backup copy */ 6462 if (adev->gfx.me.mqd_backup[mqd_idx]) 6463 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6464 /* reset the ring */ 6465 ring->wptr = 0; 6466 adev->wb.wb[ring->wptr_offs] = 0; 6467 amdgpu_ring_clear_ring(ring); 6468 #ifdef BRING_UP_DEBUG 6469 mutex_lock(&adev->srbm_mutex); 6470 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6471 gfx_v10_0_gfx_queue_init_register(ring); 6472 nv_grbm_select(adev, 0, 0, 0, 0); 6473 mutex_unlock(&adev->srbm_mutex); 6474 #endif 6475 } else { 6476 amdgpu_ring_clear_ring(ring); 6477 } 6478 6479 return 0; 6480 } 6481 6482 #ifndef BRING_UP_DEBUG 6483 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6484 { 6485 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6486 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6487 int r, i; 6488 6489 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6490 return -EINVAL; 6491 6492 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6493 adev->gfx.num_gfx_rings); 6494 if (r) { 6495 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6496 return r; 6497 } 6498 6499 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6500 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6501 6502 return amdgpu_ring_test_helper(kiq_ring); 6503 } 6504 #endif 6505 6506 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6507 { 6508 int r, i; 6509 struct amdgpu_ring *ring; 6510 6511 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6512 ring = &adev->gfx.gfx_ring[i]; 6513 6514 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6515 if (unlikely(r != 0)) 6516 goto done; 6517 6518 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6519 if (!r) { 6520 r = gfx_v10_0_gfx_init_queue(ring); 6521 amdgpu_bo_kunmap(ring->mqd_obj); 6522 ring->mqd_ptr = NULL; 6523 } 6524 amdgpu_bo_unreserve(ring->mqd_obj); 6525 if (r) 6526 goto done; 6527 } 6528 #ifndef BRING_UP_DEBUG 6529 r = gfx_v10_0_kiq_enable_kgq(adev); 6530 if (r) 6531 goto done; 6532 #endif 6533 r = gfx_v10_0_cp_gfx_start(adev); 6534 if (r) 6535 goto done; 6536 6537 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6538 ring = &adev->gfx.gfx_ring[i]; 6539 ring->sched.ready = true; 6540 } 6541 done: 6542 return r; 6543 } 6544 6545 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6546 { 6547 struct amdgpu_device *adev = ring->adev; 6548 6549 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6550 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 6551 ring->queue)) { 6552 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6553 mqd->cp_hqd_queue_priority = 6554 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6555 } 6556 } 6557 } 6558 6559 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6560 { 6561 struct amdgpu_device *adev = ring->adev; 6562 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6563 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6564 uint32_t tmp; 6565 6566 mqd->header = 0xC0310800; 6567 mqd->compute_pipelinestat_enable = 0x00000001; 6568 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6569 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6570 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6571 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6572 mqd->compute_misc_reserved = 0x00000003; 6573 6574 eop_base_addr = ring->eop_gpu_addr >> 8; 6575 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6576 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6577 6578 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6579 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6580 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6581 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6582 6583 mqd->cp_hqd_eop_control = tmp; 6584 6585 /* enable doorbell? */ 6586 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6587 6588 if (ring->use_doorbell) { 6589 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6590 DOORBELL_OFFSET, ring->doorbell_index); 6591 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6592 DOORBELL_EN, 1); 6593 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6594 DOORBELL_SOURCE, 0); 6595 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6596 DOORBELL_HIT, 0); 6597 } else { 6598 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6599 DOORBELL_EN, 0); 6600 } 6601 6602 mqd->cp_hqd_pq_doorbell_control = tmp; 6603 6604 /* disable the queue if it's active */ 6605 ring->wptr = 0; 6606 mqd->cp_hqd_dequeue_request = 0; 6607 mqd->cp_hqd_pq_rptr = 0; 6608 mqd->cp_hqd_pq_wptr_lo = 0; 6609 mqd->cp_hqd_pq_wptr_hi = 0; 6610 6611 /* set the pointer to the MQD */ 6612 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6613 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6614 6615 /* set MQD vmid to 0 */ 6616 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6617 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6618 mqd->cp_mqd_control = tmp; 6619 6620 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6621 hqd_gpu_addr = ring->gpu_addr >> 8; 6622 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6623 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6624 6625 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6626 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6627 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6628 (order_base_2(ring->ring_size / 4) - 1)); 6629 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6630 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6631 #ifdef __BIG_ENDIAN 6632 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6633 #endif 6634 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6635 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6636 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6637 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6638 mqd->cp_hqd_pq_control = tmp; 6639 6640 /* set the wb address whether it's enabled or not */ 6641 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6642 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6643 mqd->cp_hqd_pq_rptr_report_addr_hi = 6644 upper_32_bits(wb_gpu_addr) & 0xffff; 6645 6646 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6647 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6648 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6649 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6650 6651 tmp = 0; 6652 /* enable the doorbell if requested */ 6653 if (ring->use_doorbell) { 6654 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6655 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6656 DOORBELL_OFFSET, ring->doorbell_index); 6657 6658 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6659 DOORBELL_EN, 1); 6660 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6661 DOORBELL_SOURCE, 0); 6662 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6663 DOORBELL_HIT, 0); 6664 } 6665 6666 mqd->cp_hqd_pq_doorbell_control = tmp; 6667 6668 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6669 ring->wptr = 0; 6670 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6671 6672 /* set the vmid for the queue */ 6673 mqd->cp_hqd_vmid = 0; 6674 6675 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6676 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6677 mqd->cp_hqd_persistent_state = tmp; 6678 6679 /* set MIN_IB_AVAIL_SIZE */ 6680 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6681 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6682 mqd->cp_hqd_ib_control = tmp; 6683 6684 /* set static priority for a compute queue/ring */ 6685 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6686 6687 /* map_queues packet doesn't need activate the queue, 6688 * so only kiq need set this field. 6689 */ 6690 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6691 mqd->cp_hqd_active = 1; 6692 6693 return 0; 6694 } 6695 6696 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6697 { 6698 struct amdgpu_device *adev = ring->adev; 6699 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6700 int j; 6701 6702 /* inactivate the queue */ 6703 if (amdgpu_sriov_vf(adev)) 6704 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6705 6706 /* disable wptr polling */ 6707 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6708 6709 /* write the EOP addr */ 6710 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6711 mqd->cp_hqd_eop_base_addr_lo); 6712 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6713 mqd->cp_hqd_eop_base_addr_hi); 6714 6715 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6716 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6717 mqd->cp_hqd_eop_control); 6718 6719 /* enable doorbell? */ 6720 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6721 mqd->cp_hqd_pq_doorbell_control); 6722 6723 /* disable the queue if it's active */ 6724 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6725 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6726 for (j = 0; j < adev->usec_timeout; j++) { 6727 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6728 break; 6729 udelay(1); 6730 } 6731 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6732 mqd->cp_hqd_dequeue_request); 6733 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6734 mqd->cp_hqd_pq_rptr); 6735 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6736 mqd->cp_hqd_pq_wptr_lo); 6737 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6738 mqd->cp_hqd_pq_wptr_hi); 6739 } 6740 6741 /* set the pointer to the MQD */ 6742 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6743 mqd->cp_mqd_base_addr_lo); 6744 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6745 mqd->cp_mqd_base_addr_hi); 6746 6747 /* set MQD vmid to 0 */ 6748 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6749 mqd->cp_mqd_control); 6750 6751 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6752 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6753 mqd->cp_hqd_pq_base_lo); 6754 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6755 mqd->cp_hqd_pq_base_hi); 6756 6757 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6758 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6759 mqd->cp_hqd_pq_control); 6760 6761 /* set the wb address whether it's enabled or not */ 6762 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6763 mqd->cp_hqd_pq_rptr_report_addr_lo); 6764 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6765 mqd->cp_hqd_pq_rptr_report_addr_hi); 6766 6767 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6768 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6769 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6770 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6771 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6772 6773 /* enable the doorbell if requested */ 6774 if (ring->use_doorbell) { 6775 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6776 (adev->doorbell_index.kiq * 2) << 2); 6777 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6778 (adev->doorbell_index.userqueue_end * 2) << 2); 6779 } 6780 6781 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6782 mqd->cp_hqd_pq_doorbell_control); 6783 6784 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6785 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6786 mqd->cp_hqd_pq_wptr_lo); 6787 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6788 mqd->cp_hqd_pq_wptr_hi); 6789 6790 /* set the vmid for the queue */ 6791 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6792 6793 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6794 mqd->cp_hqd_persistent_state); 6795 6796 /* activate the queue */ 6797 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6798 mqd->cp_hqd_active); 6799 6800 if (ring->use_doorbell) 6801 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6802 6803 return 0; 6804 } 6805 6806 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6807 { 6808 struct amdgpu_device *adev = ring->adev; 6809 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6810 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6811 6812 gfx_v10_0_kiq_setting(ring); 6813 6814 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6815 /* reset MQD to a clean status */ 6816 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6817 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6818 6819 /* reset ring buffer */ 6820 ring->wptr = 0; 6821 amdgpu_ring_clear_ring(ring); 6822 6823 mutex_lock(&adev->srbm_mutex); 6824 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6825 gfx_v10_0_kiq_init_register(ring); 6826 nv_grbm_select(adev, 0, 0, 0, 0); 6827 mutex_unlock(&adev->srbm_mutex); 6828 } else { 6829 memset((void *)mqd, 0, sizeof(*mqd)); 6830 mutex_lock(&adev->srbm_mutex); 6831 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6832 gfx_v10_0_compute_mqd_init(ring); 6833 gfx_v10_0_kiq_init_register(ring); 6834 nv_grbm_select(adev, 0, 0, 0, 0); 6835 mutex_unlock(&adev->srbm_mutex); 6836 6837 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6838 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6839 } 6840 6841 return 0; 6842 } 6843 6844 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6845 { 6846 struct amdgpu_device *adev = ring->adev; 6847 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6848 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6849 6850 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6851 memset((void *)mqd, 0, sizeof(*mqd)); 6852 mutex_lock(&adev->srbm_mutex); 6853 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6854 gfx_v10_0_compute_mqd_init(ring); 6855 nv_grbm_select(adev, 0, 0, 0, 0); 6856 mutex_unlock(&adev->srbm_mutex); 6857 6858 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6859 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6860 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6861 /* reset MQD to a clean status */ 6862 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6863 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6864 6865 /* reset ring buffer */ 6866 ring->wptr = 0; 6867 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 6868 amdgpu_ring_clear_ring(ring); 6869 } else { 6870 amdgpu_ring_clear_ring(ring); 6871 } 6872 6873 return 0; 6874 } 6875 6876 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6877 { 6878 struct amdgpu_ring *ring; 6879 int r; 6880 6881 ring = &adev->gfx.kiq.ring; 6882 6883 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6884 if (unlikely(r != 0)) 6885 return r; 6886 6887 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6888 if (unlikely(r != 0)) 6889 return r; 6890 6891 gfx_v10_0_kiq_init_queue(ring); 6892 amdgpu_bo_kunmap(ring->mqd_obj); 6893 ring->mqd_ptr = NULL; 6894 amdgpu_bo_unreserve(ring->mqd_obj); 6895 ring->sched.ready = true; 6896 return 0; 6897 } 6898 6899 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6900 { 6901 struct amdgpu_ring *ring = NULL; 6902 int r = 0, i; 6903 6904 gfx_v10_0_cp_compute_enable(adev, true); 6905 6906 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6907 ring = &adev->gfx.compute_ring[i]; 6908 6909 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6910 if (unlikely(r != 0)) 6911 goto done; 6912 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6913 if (!r) { 6914 r = gfx_v10_0_kcq_init_queue(ring); 6915 amdgpu_bo_kunmap(ring->mqd_obj); 6916 ring->mqd_ptr = NULL; 6917 } 6918 amdgpu_bo_unreserve(ring->mqd_obj); 6919 if (r) 6920 goto done; 6921 } 6922 6923 r = amdgpu_gfx_enable_kcq(adev); 6924 done: 6925 return r; 6926 } 6927 6928 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6929 { 6930 int r, i; 6931 struct amdgpu_ring *ring; 6932 6933 if (!(adev->flags & AMD_IS_APU)) 6934 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6935 6936 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6937 /* legacy firmware loading */ 6938 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6939 if (r) 6940 return r; 6941 6942 r = gfx_v10_0_cp_compute_load_microcode(adev); 6943 if (r) 6944 return r; 6945 } 6946 6947 r = gfx_v10_0_kiq_resume(adev); 6948 if (r) 6949 return r; 6950 6951 r = gfx_v10_0_kcq_resume(adev); 6952 if (r) 6953 return r; 6954 6955 if (!amdgpu_async_gfx_ring) { 6956 r = gfx_v10_0_cp_gfx_resume(adev); 6957 if (r) 6958 return r; 6959 } else { 6960 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6961 if (r) 6962 return r; 6963 } 6964 6965 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6966 ring = &adev->gfx.gfx_ring[i]; 6967 r = amdgpu_ring_test_helper(ring); 6968 if (r) 6969 return r; 6970 } 6971 6972 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6973 ring = &adev->gfx.compute_ring[i]; 6974 r = amdgpu_ring_test_helper(ring); 6975 if (r) 6976 return r; 6977 } 6978 6979 return 0; 6980 } 6981 6982 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6983 { 6984 gfx_v10_0_cp_gfx_enable(adev, enable); 6985 gfx_v10_0_cp_compute_enable(adev, enable); 6986 } 6987 6988 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6989 { 6990 uint32_t data, pattern = 0xDEADBEEF; 6991 6992 /* check if mmVGT_ESGS_RING_SIZE_UMD 6993 * has been remapped to mmVGT_ESGS_RING_SIZE */ 6994 switch (adev->asic_type) { 6995 case CHIP_SIENNA_CICHLID: 6996 case CHIP_NAVY_FLOUNDER: 6997 case CHIP_DIMGREY_CAVEFISH: 6998 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6999 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7000 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7001 7002 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7003 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 7004 return true; 7005 } else { 7006 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7007 return false; 7008 } 7009 break; 7010 case CHIP_VANGOGH: 7011 return true; 7012 default: 7013 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7014 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7015 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7016 7017 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7018 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7019 return true; 7020 } else { 7021 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7022 return false; 7023 } 7024 break; 7025 } 7026 } 7027 7028 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7029 { 7030 uint32_t data; 7031 7032 /* initialize cam_index to 0 7033 * index will auto-inc after each data writting */ 7034 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7035 7036 switch (adev->asic_type) { 7037 case CHIP_SIENNA_CICHLID: 7038 case CHIP_NAVY_FLOUNDER: 7039 case CHIP_VANGOGH: 7040 case CHIP_DIMGREY_CAVEFISH: 7041 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7042 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7043 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7044 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7045 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7046 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7047 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7048 7049 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7050 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7051 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7052 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7053 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7054 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7055 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7056 7057 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7058 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7059 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7060 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7061 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7062 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7063 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7064 7065 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7066 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7067 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7068 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7069 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7070 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7071 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7072 7073 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7074 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7075 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7076 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7077 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7078 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7079 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7080 7081 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7082 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7083 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7084 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7085 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7086 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7087 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7088 7089 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7090 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7091 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7092 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7093 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7094 break; 7095 default: 7096 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7097 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7098 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7099 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7100 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7101 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7102 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7103 7104 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7105 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7106 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7107 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7108 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7109 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7110 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7111 7112 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7113 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7114 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7115 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7116 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7117 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7118 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7119 7120 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7121 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7122 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7123 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7124 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7125 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7126 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7127 7128 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7129 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7130 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7131 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7132 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7133 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7134 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7135 7136 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7137 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7138 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7139 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7140 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7141 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7142 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7143 7144 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7145 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7146 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7147 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7148 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7149 break; 7150 } 7151 7152 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7153 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7154 } 7155 7156 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7157 { 7158 uint32_t data; 7159 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7160 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7161 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7162 7163 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7164 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7165 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7166 } 7167 7168 static int gfx_v10_0_hw_init(void *handle) 7169 { 7170 int r; 7171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7172 7173 if (!amdgpu_emu_mode) 7174 gfx_v10_0_init_golden_registers(adev); 7175 7176 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7177 /** 7178 * For gfx 10, rlc firmware loading relies on smu firmware is 7179 * loaded firstly, so in direct type, it has to load smc ucode 7180 * here before rlc. 7181 */ 7182 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) { 7183 r = smu_load_microcode(&adev->smu); 7184 if (r) 7185 return r; 7186 7187 r = smu_check_fw_status(&adev->smu); 7188 if (r) { 7189 pr_err("SMC firmware status is not correct\n"); 7190 return r; 7191 } 7192 } 7193 gfx_v10_0_disable_gpa_mode(adev); 7194 } 7195 7196 /* if GRBM CAM not remapped, set up the remapping */ 7197 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7198 gfx_v10_0_setup_grbm_cam_remapping(adev); 7199 7200 gfx_v10_0_constants_init(adev); 7201 7202 r = gfx_v10_0_rlc_resume(adev); 7203 if (r) 7204 return r; 7205 7206 /* 7207 * init golden registers and rlc resume may override some registers, 7208 * reconfig them here 7209 */ 7210 gfx_v10_0_tcp_harvest(adev); 7211 7212 r = gfx_v10_0_cp_resume(adev); 7213 if (r) 7214 return r; 7215 7216 if (adev->asic_type == CHIP_SIENNA_CICHLID) 7217 gfx_v10_3_program_pbb_mode(adev); 7218 7219 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 7220 gfx_v10_3_set_power_brake_sequence(adev); 7221 7222 return r; 7223 } 7224 7225 #ifndef BRING_UP_DEBUG 7226 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7227 { 7228 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7229 struct amdgpu_ring *kiq_ring = &kiq->ring; 7230 int i; 7231 7232 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7233 return -EINVAL; 7234 7235 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7236 adev->gfx.num_gfx_rings)) 7237 return -ENOMEM; 7238 7239 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7240 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7241 PREEMPT_QUEUES, 0, 0); 7242 7243 return amdgpu_ring_test_helper(kiq_ring); 7244 } 7245 #endif 7246 7247 static int gfx_v10_0_hw_fini(void *handle) 7248 { 7249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7250 int r; 7251 uint32_t tmp; 7252 7253 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7254 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7255 7256 if (!adev->in_pci_err_recovery) { 7257 #ifndef BRING_UP_DEBUG 7258 if (amdgpu_async_gfx_ring) { 7259 r = gfx_v10_0_kiq_disable_kgq(adev); 7260 if (r) 7261 DRM_ERROR("KGQ disable failed\n"); 7262 } 7263 #endif 7264 if (amdgpu_gfx_disable_kcq(adev)) 7265 DRM_ERROR("KCQ disable failed\n"); 7266 } 7267 7268 if (amdgpu_sriov_vf(adev)) { 7269 gfx_v10_0_cp_gfx_enable(adev, false); 7270 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7271 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7272 tmp &= 0xffffff00; 7273 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7274 7275 return 0; 7276 } 7277 gfx_v10_0_cp_enable(adev, false); 7278 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7279 7280 return 0; 7281 } 7282 7283 static int gfx_v10_0_suspend(void *handle) 7284 { 7285 return gfx_v10_0_hw_fini(handle); 7286 } 7287 7288 static int gfx_v10_0_resume(void *handle) 7289 { 7290 return gfx_v10_0_hw_init(handle); 7291 } 7292 7293 static bool gfx_v10_0_is_idle(void *handle) 7294 { 7295 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7296 7297 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7298 GRBM_STATUS, GUI_ACTIVE)) 7299 return false; 7300 else 7301 return true; 7302 } 7303 7304 static int gfx_v10_0_wait_for_idle(void *handle) 7305 { 7306 unsigned i; 7307 u32 tmp; 7308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7309 7310 for (i = 0; i < adev->usec_timeout; i++) { 7311 /* read MC_STATUS */ 7312 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7313 GRBM_STATUS__GUI_ACTIVE_MASK; 7314 7315 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7316 return 0; 7317 udelay(1); 7318 } 7319 return -ETIMEDOUT; 7320 } 7321 7322 static int gfx_v10_0_soft_reset(void *handle) 7323 { 7324 u32 grbm_soft_reset = 0; 7325 u32 tmp; 7326 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7327 7328 /* GRBM_STATUS */ 7329 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7330 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7331 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7332 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7333 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7334 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7335 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7336 GRBM_SOFT_RESET, SOFT_RESET_CP, 7337 1); 7338 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7339 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7340 1); 7341 } 7342 7343 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7344 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7345 GRBM_SOFT_RESET, SOFT_RESET_CP, 7346 1); 7347 } 7348 7349 /* GRBM_STATUS2 */ 7350 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7351 switch (adev->asic_type) { 7352 case CHIP_SIENNA_CICHLID: 7353 case CHIP_NAVY_FLOUNDER: 7354 case CHIP_VANGOGH: 7355 case CHIP_DIMGREY_CAVEFISH: 7356 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7357 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7358 GRBM_SOFT_RESET, 7359 SOFT_RESET_RLC, 7360 1); 7361 break; 7362 default: 7363 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7364 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7365 GRBM_SOFT_RESET, 7366 SOFT_RESET_RLC, 7367 1); 7368 break; 7369 } 7370 7371 if (grbm_soft_reset) { 7372 /* stop the rlc */ 7373 gfx_v10_0_rlc_stop(adev); 7374 7375 /* Disable GFX parsing/prefetching */ 7376 gfx_v10_0_cp_gfx_enable(adev, false); 7377 7378 /* Disable MEC parsing/prefetching */ 7379 gfx_v10_0_cp_compute_enable(adev, false); 7380 7381 if (grbm_soft_reset) { 7382 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7383 tmp |= grbm_soft_reset; 7384 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7385 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7386 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7387 7388 udelay(50); 7389 7390 tmp &= ~grbm_soft_reset; 7391 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7392 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7393 } 7394 7395 /* Wait a little for things to settle down */ 7396 udelay(50); 7397 } 7398 return 0; 7399 } 7400 7401 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7402 { 7403 uint64_t clock; 7404 7405 amdgpu_gfx_off_ctrl(adev, false); 7406 mutex_lock(&adev->gfx.gpu_clock_mutex); 7407 switch (adev->asic_type) { 7408 case CHIP_VANGOGH: 7409 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) | 7410 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL); 7411 break; 7412 default: 7413 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 7414 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 7415 break; 7416 } 7417 mutex_unlock(&adev->gfx.gpu_clock_mutex); 7418 amdgpu_gfx_off_ctrl(adev, true); 7419 return clock; 7420 } 7421 7422 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7423 uint32_t vmid, 7424 uint32_t gds_base, uint32_t gds_size, 7425 uint32_t gws_base, uint32_t gws_size, 7426 uint32_t oa_base, uint32_t oa_size) 7427 { 7428 struct amdgpu_device *adev = ring->adev; 7429 7430 /* GDS Base */ 7431 gfx_v10_0_write_data_to_reg(ring, 0, false, 7432 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7433 gds_base); 7434 7435 /* GDS Size */ 7436 gfx_v10_0_write_data_to_reg(ring, 0, false, 7437 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7438 gds_size); 7439 7440 /* GWS */ 7441 gfx_v10_0_write_data_to_reg(ring, 0, false, 7442 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7443 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7444 7445 /* OA */ 7446 gfx_v10_0_write_data_to_reg(ring, 0, false, 7447 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7448 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7449 } 7450 7451 static int gfx_v10_0_early_init(void *handle) 7452 { 7453 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7454 7455 switch (adev->asic_type) { 7456 case CHIP_NAVI10: 7457 case CHIP_NAVI14: 7458 case CHIP_NAVI12: 7459 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7460 break; 7461 case CHIP_SIENNA_CICHLID: 7462 case CHIP_NAVY_FLOUNDER: 7463 case CHIP_VANGOGH: 7464 case CHIP_DIMGREY_CAVEFISH: 7465 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7466 break; 7467 default: 7468 break; 7469 } 7470 7471 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7472 AMDGPU_MAX_COMPUTE_RINGS); 7473 7474 gfx_v10_0_set_kiq_pm4_funcs(adev); 7475 gfx_v10_0_set_ring_funcs(adev); 7476 gfx_v10_0_set_irq_funcs(adev); 7477 gfx_v10_0_set_gds_init(adev); 7478 gfx_v10_0_set_rlc_funcs(adev); 7479 7480 return 0; 7481 } 7482 7483 static int gfx_v10_0_late_init(void *handle) 7484 { 7485 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7486 int r; 7487 7488 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7489 if (r) 7490 return r; 7491 7492 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7493 if (r) 7494 return r; 7495 7496 return 0; 7497 } 7498 7499 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7500 { 7501 uint32_t rlc_cntl; 7502 7503 /* if RLC is not enabled, do nothing */ 7504 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7505 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7506 } 7507 7508 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7509 { 7510 uint32_t data; 7511 unsigned i; 7512 7513 data = RLC_SAFE_MODE__CMD_MASK; 7514 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7515 7516 switch (adev->asic_type) { 7517 case CHIP_SIENNA_CICHLID: 7518 case CHIP_NAVY_FLOUNDER: 7519 case CHIP_VANGOGH: 7520 case CHIP_DIMGREY_CAVEFISH: 7521 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7522 7523 /* wait for RLC_SAFE_MODE */ 7524 for (i = 0; i < adev->usec_timeout; i++) { 7525 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7526 RLC_SAFE_MODE, CMD)) 7527 break; 7528 udelay(1); 7529 } 7530 break; 7531 default: 7532 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7533 7534 /* wait for RLC_SAFE_MODE */ 7535 for (i = 0; i < adev->usec_timeout; i++) { 7536 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7537 RLC_SAFE_MODE, CMD)) 7538 break; 7539 udelay(1); 7540 } 7541 break; 7542 } 7543 } 7544 7545 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7546 { 7547 uint32_t data; 7548 7549 data = RLC_SAFE_MODE__CMD_MASK; 7550 switch (adev->asic_type) { 7551 case CHIP_SIENNA_CICHLID: 7552 case CHIP_NAVY_FLOUNDER: 7553 case CHIP_VANGOGH: 7554 case CHIP_DIMGREY_CAVEFISH: 7555 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7556 break; 7557 default: 7558 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7559 break; 7560 } 7561 } 7562 7563 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7564 bool enable) 7565 { 7566 uint32_t data, def; 7567 7568 /* It is disabled by HW by default */ 7569 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7570 /* 0 - Disable some blocks' MGCG */ 7571 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7572 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7573 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7574 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7575 7576 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7577 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7578 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7579 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7580 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7581 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7582 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7583 7584 if (def != data) 7585 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7586 7587 /* MGLS is a global flag to control all MGLS in GFX */ 7588 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7589 /* 2 - RLC memory Light sleep */ 7590 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7591 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7592 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7593 if (def != data) 7594 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7595 } 7596 /* 3 - CP memory Light sleep */ 7597 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7598 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7599 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7600 if (def != data) 7601 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7602 } 7603 } 7604 } else { 7605 /* 1 - MGCG_OVERRIDE */ 7606 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7607 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7608 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7609 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7610 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 7611 if (def != data) 7612 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7613 7614 /* 2 - disable MGLS in CP */ 7615 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7616 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7617 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7618 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7619 } 7620 7621 /* 3 - disable MGLS in RLC */ 7622 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7623 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7624 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7625 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7626 } 7627 7628 } 7629 } 7630 7631 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7632 bool enable) 7633 { 7634 uint32_t data, def; 7635 7636 /* Enable 3D CGCG/CGLS */ 7637 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 7638 /* write cmd to clear cgcg/cgls ov */ 7639 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7640 /* unset CGCG override */ 7641 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7642 /* update CGCG and CGLS override bits */ 7643 if (def != data) 7644 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7645 /* enable 3Dcgcg FSM(0x0000363f) */ 7646 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7647 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7648 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7649 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7650 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7651 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7652 if (def != data) 7653 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7654 7655 /* set IDLE_POLL_COUNT(0x00900100) */ 7656 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7657 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7658 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7659 if (def != data) 7660 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7661 } else { 7662 /* Disable CGCG/CGLS */ 7663 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7664 /* disable cgcg, cgls should be disabled */ 7665 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 7666 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 7667 /* disable cgcg and cgls in FSM */ 7668 if (def != data) 7669 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7670 } 7671 } 7672 7673 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7674 bool enable) 7675 { 7676 uint32_t def, data; 7677 7678 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 7679 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7680 /* unset CGCG override */ 7681 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7682 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7683 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7684 else 7685 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7686 /* update CGCG and CGLS override bits */ 7687 if (def != data) 7688 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7689 7690 /* enable cgcg FSM(0x0000363F) */ 7691 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7692 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7693 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7694 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7695 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7696 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7697 if (def != data) 7698 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7699 7700 /* set IDLE_POLL_COUNT(0x00900100) */ 7701 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7702 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7703 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7704 if (def != data) 7705 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7706 } else { 7707 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7708 /* reset CGCG/CGLS bits */ 7709 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 7710 /* disable cgcg and cgls in FSM */ 7711 if (def != data) 7712 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7713 } 7714 } 7715 7716 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7717 bool enable) 7718 { 7719 uint32_t def, data; 7720 7721 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) { 7722 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7723 /* unset FGCG override */ 7724 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7725 /* update FGCG override bits */ 7726 if (def != data) 7727 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7728 7729 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7730 /* unset RLC SRAM CLK GATER override */ 7731 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7732 /* update RLC SRAM CLK GATER override bits */ 7733 if (def != data) 7734 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7735 } else { 7736 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7737 /* reset FGCG bits */ 7738 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7739 /* disable FGCG*/ 7740 if (def != data) 7741 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7742 7743 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7744 /* reset RLC SRAM CLK GATER bits */ 7745 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7746 /* disable RLC SRAM CLK*/ 7747 if (def != data) 7748 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7749 } 7750 } 7751 7752 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7753 bool enable) 7754 { 7755 amdgpu_gfx_rlc_enter_safe_mode(adev); 7756 7757 if (enable) { 7758 /* enable FGCG firstly*/ 7759 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7760 /* CGCG/CGLS should be enabled after MGCG/MGLS 7761 * === MGCG + MGLS === 7762 */ 7763 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7764 /* === CGCG /CGLS for GFX 3D Only === */ 7765 gfx_v10_0_update_3d_clock_gating(adev, enable); 7766 /* === CGCG + CGLS === */ 7767 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7768 } else { 7769 /* CGCG/CGLS should be disabled before MGCG/MGLS 7770 * === CGCG + CGLS === 7771 */ 7772 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7773 /* === CGCG /CGLS for GFX 3D Only === */ 7774 gfx_v10_0_update_3d_clock_gating(adev, enable); 7775 /* === MGCG + MGLS === */ 7776 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7777 /* disable fgcg at last*/ 7778 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7779 } 7780 7781 if (adev->cg_flags & 7782 (AMD_CG_SUPPORT_GFX_MGCG | 7783 AMD_CG_SUPPORT_GFX_CGLS | 7784 AMD_CG_SUPPORT_GFX_CGCG | 7785 AMD_CG_SUPPORT_GFX_3D_CGCG | 7786 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7787 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7788 7789 amdgpu_gfx_rlc_exit_safe_mode(adev); 7790 7791 return 0; 7792 } 7793 7794 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 7795 { 7796 u32 reg, data; 7797 7798 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7799 if (amdgpu_sriov_is_pp_one_vf(adev)) 7800 data = RREG32_NO_KIQ(reg); 7801 else 7802 data = RREG32(reg); 7803 7804 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7805 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7806 7807 if (amdgpu_sriov_is_pp_one_vf(adev)) 7808 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7809 else 7810 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7811 } 7812 7813 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7814 uint32_t offset, 7815 struct soc15_reg_rlcg *entries, int arr_size) 7816 { 7817 int i; 7818 uint32_t reg; 7819 7820 if (!entries) 7821 return false; 7822 7823 for (i = 0; i < arr_size; i++) { 7824 const struct soc15_reg_rlcg *entry; 7825 7826 entry = &entries[i]; 7827 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7828 if (offset == reg) 7829 return true; 7830 } 7831 7832 return false; 7833 } 7834 7835 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7836 { 7837 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7838 } 7839 7840 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7841 { 7842 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7843 7844 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7845 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7846 else 7847 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7848 7849 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7850 } 7851 7852 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7853 { 7854 amdgpu_gfx_rlc_enter_safe_mode(adev); 7855 7856 gfx_v10_cntl_power_gating(adev, enable); 7857 7858 amdgpu_gfx_rlc_exit_safe_mode(adev); 7859 } 7860 7861 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 7862 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7863 .set_safe_mode = gfx_v10_0_set_safe_mode, 7864 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7865 .init = gfx_v10_0_rlc_init, 7866 .get_csb_size = gfx_v10_0_get_csb_size, 7867 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7868 .resume = gfx_v10_0_rlc_resume, 7869 .stop = gfx_v10_0_rlc_stop, 7870 .reset = gfx_v10_0_rlc_reset, 7871 .start = gfx_v10_0_rlc_start, 7872 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7873 }; 7874 7875 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 7876 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7877 .set_safe_mode = gfx_v10_0_set_safe_mode, 7878 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7879 .init = gfx_v10_0_rlc_init, 7880 .get_csb_size = gfx_v10_0_get_csb_size, 7881 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7882 .resume = gfx_v10_0_rlc_resume, 7883 .stop = gfx_v10_0_rlc_stop, 7884 .reset = gfx_v10_0_rlc_reset, 7885 .start = gfx_v10_0_rlc_start, 7886 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7887 .rlcg_wreg = gfx_v10_rlcg_wreg, 7888 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 7889 }; 7890 7891 static int gfx_v10_0_set_powergating_state(void *handle, 7892 enum amd_powergating_state state) 7893 { 7894 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7895 bool enable = (state == AMD_PG_STATE_GATE); 7896 7897 if (amdgpu_sriov_vf(adev)) 7898 return 0; 7899 7900 switch (adev->asic_type) { 7901 case CHIP_NAVI10: 7902 case CHIP_NAVI14: 7903 case CHIP_NAVI12: 7904 case CHIP_SIENNA_CICHLID: 7905 case CHIP_NAVY_FLOUNDER: 7906 case CHIP_DIMGREY_CAVEFISH: 7907 amdgpu_gfx_off_ctrl(adev, enable); 7908 break; 7909 case CHIP_VANGOGH: 7910 gfx_v10_cntl_pg(adev, enable); 7911 break; 7912 default: 7913 break; 7914 } 7915 return 0; 7916 } 7917 7918 static int gfx_v10_0_set_clockgating_state(void *handle, 7919 enum amd_clockgating_state state) 7920 { 7921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7922 7923 if (amdgpu_sriov_vf(adev)) 7924 return 0; 7925 7926 switch (adev->asic_type) { 7927 case CHIP_NAVI10: 7928 case CHIP_NAVI14: 7929 case CHIP_NAVI12: 7930 case CHIP_SIENNA_CICHLID: 7931 case CHIP_NAVY_FLOUNDER: 7932 case CHIP_VANGOGH: 7933 case CHIP_DIMGREY_CAVEFISH: 7934 gfx_v10_0_update_gfx_clock_gating(adev, 7935 state == AMD_CG_STATE_GATE); 7936 break; 7937 default: 7938 break; 7939 } 7940 return 0; 7941 } 7942 7943 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 7944 { 7945 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7946 int data; 7947 7948 /* AMD_CG_SUPPORT_GFX_FGCG */ 7949 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7950 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 7951 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 7952 7953 /* AMD_CG_SUPPORT_GFX_MGCG */ 7954 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7955 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 7956 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 7957 7958 /* AMD_CG_SUPPORT_GFX_CGCG */ 7959 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 7960 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 7961 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 7962 7963 /* AMD_CG_SUPPORT_GFX_CGLS */ 7964 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 7965 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 7966 7967 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 7968 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 7969 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 7970 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 7971 7972 /* AMD_CG_SUPPORT_GFX_CP_LS */ 7973 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 7974 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 7975 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 7976 7977 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 7978 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 7979 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 7980 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 7981 7982 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 7983 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 7984 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 7985 } 7986 7987 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 7988 { 7989 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 7990 } 7991 7992 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 7993 { 7994 struct amdgpu_device *adev = ring->adev; 7995 u64 wptr; 7996 7997 /* XXX check if swapping is necessary on BE */ 7998 if (ring->use_doorbell) { 7999 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 8000 } else { 8001 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8002 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8003 } 8004 8005 return wptr; 8006 } 8007 8008 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8009 { 8010 struct amdgpu_device *adev = ring->adev; 8011 8012 if (ring->use_doorbell) { 8013 /* XXX check if swapping is necessary on BE */ 8014 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8015 WDOORBELL64(ring->doorbell_index, ring->wptr); 8016 } else { 8017 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 8018 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 8019 } 8020 } 8021 8022 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8023 { 8024 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 8025 } 8026 8027 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8028 { 8029 u64 wptr; 8030 8031 /* XXX check if swapping is necessary on BE */ 8032 if (ring->use_doorbell) 8033 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 8034 else 8035 BUG(); 8036 return wptr; 8037 } 8038 8039 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8040 { 8041 struct amdgpu_device *adev = ring->adev; 8042 8043 /* XXX check if swapping is necessary on BE */ 8044 if (ring->use_doorbell) { 8045 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8046 WDOORBELL64(ring->doorbell_index, ring->wptr); 8047 } else { 8048 BUG(); /* only DOORBELL method supported on gfx10 now */ 8049 } 8050 } 8051 8052 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8053 { 8054 struct amdgpu_device *adev = ring->adev; 8055 u32 ref_and_mask, reg_mem_engine; 8056 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8057 8058 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8059 switch (ring->me) { 8060 case 1: 8061 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8062 break; 8063 case 2: 8064 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8065 break; 8066 default: 8067 return; 8068 } 8069 reg_mem_engine = 0; 8070 } else { 8071 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8072 reg_mem_engine = 1; /* pfp */ 8073 } 8074 8075 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8076 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8077 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8078 ref_and_mask, ref_and_mask, 0x20); 8079 } 8080 8081 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8082 struct amdgpu_job *job, 8083 struct amdgpu_ib *ib, 8084 uint32_t flags) 8085 { 8086 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8087 u32 header, control = 0; 8088 8089 if (ib->flags & AMDGPU_IB_FLAG_CE) 8090 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8091 else 8092 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8093 8094 control |= ib->length_dw | (vmid << 24); 8095 8096 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8097 control |= INDIRECT_BUFFER_PRE_ENB(1); 8098 8099 if (flags & AMDGPU_IB_PREEMPTED) 8100 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8101 8102 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8103 gfx_v10_0_ring_emit_de_meta(ring, 8104 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8105 } 8106 8107 amdgpu_ring_write(ring, header); 8108 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8109 amdgpu_ring_write(ring, 8110 #ifdef __BIG_ENDIAN 8111 (2 << 0) | 8112 #endif 8113 lower_32_bits(ib->gpu_addr)); 8114 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8115 amdgpu_ring_write(ring, control); 8116 } 8117 8118 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8119 struct amdgpu_job *job, 8120 struct amdgpu_ib *ib, 8121 uint32_t flags) 8122 { 8123 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8124 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8125 8126 /* Currently, there is a high possibility to get wave ID mismatch 8127 * between ME and GDS, leading to a hw deadlock, because ME generates 8128 * different wave IDs than the GDS expects. This situation happens 8129 * randomly when at least 5 compute pipes use GDS ordered append. 8130 * The wave IDs generated by ME are also wrong after suspend/resume. 8131 * Those are probably bugs somewhere else in the kernel driver. 8132 * 8133 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8134 * GDS to 0 for this ring (me/pipe). 8135 */ 8136 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8137 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8138 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8139 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8140 } 8141 8142 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8143 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8144 amdgpu_ring_write(ring, 8145 #ifdef __BIG_ENDIAN 8146 (2 << 0) | 8147 #endif 8148 lower_32_bits(ib->gpu_addr)); 8149 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8150 amdgpu_ring_write(ring, control); 8151 } 8152 8153 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8154 u64 seq, unsigned flags) 8155 { 8156 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8157 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8158 8159 /* RELEASE_MEM - flush caches, send int */ 8160 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8161 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8162 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8163 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8164 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8165 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8166 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8167 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8168 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8169 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8170 8171 /* 8172 * the address should be Qword aligned if 64bit write, Dword 8173 * aligned if only send 32bit data low (discard data high) 8174 */ 8175 if (write64bit) 8176 BUG_ON(addr & 0x7); 8177 else 8178 BUG_ON(addr & 0x3); 8179 amdgpu_ring_write(ring, lower_32_bits(addr)); 8180 amdgpu_ring_write(ring, upper_32_bits(addr)); 8181 amdgpu_ring_write(ring, lower_32_bits(seq)); 8182 amdgpu_ring_write(ring, upper_32_bits(seq)); 8183 amdgpu_ring_write(ring, 0); 8184 } 8185 8186 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8187 { 8188 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8189 uint32_t seq = ring->fence_drv.sync_seq; 8190 uint64_t addr = ring->fence_drv.gpu_addr; 8191 8192 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8193 upper_32_bits(addr), seq, 0xffffffff, 4); 8194 } 8195 8196 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8197 unsigned vmid, uint64_t pd_addr) 8198 { 8199 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8200 8201 /* compute doesn't have PFP */ 8202 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8203 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8204 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8205 amdgpu_ring_write(ring, 0x0); 8206 } 8207 } 8208 8209 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8210 u64 seq, unsigned int flags) 8211 { 8212 struct amdgpu_device *adev = ring->adev; 8213 8214 /* we only allocate 32bit for each seq wb address */ 8215 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8216 8217 /* write fence seq to the "addr" */ 8218 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8219 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8220 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8221 amdgpu_ring_write(ring, lower_32_bits(addr)); 8222 amdgpu_ring_write(ring, upper_32_bits(addr)); 8223 amdgpu_ring_write(ring, lower_32_bits(seq)); 8224 8225 if (flags & AMDGPU_FENCE_FLAG_INT) { 8226 /* set register to trigger INT */ 8227 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8228 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8229 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8230 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8231 amdgpu_ring_write(ring, 0); 8232 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8233 } 8234 } 8235 8236 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8237 { 8238 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8239 amdgpu_ring_write(ring, 0); 8240 } 8241 8242 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8243 uint32_t flags) 8244 { 8245 uint32_t dw2 = 0; 8246 8247 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8248 gfx_v10_0_ring_emit_ce_meta(ring, 8249 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8250 8251 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8252 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8253 /* set load_global_config & load_global_uconfig */ 8254 dw2 |= 0x8001; 8255 /* set load_cs_sh_regs */ 8256 dw2 |= 0x01000000; 8257 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8258 dw2 |= 0x10002; 8259 8260 /* set load_ce_ram if preamble presented */ 8261 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8262 dw2 |= 0x10000000; 8263 } else { 8264 /* still load_ce_ram if this is the first time preamble presented 8265 * although there is no context switch happens. 8266 */ 8267 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8268 dw2 |= 0x10000000; 8269 } 8270 8271 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8272 amdgpu_ring_write(ring, dw2); 8273 amdgpu_ring_write(ring, 0); 8274 } 8275 8276 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8277 { 8278 unsigned ret; 8279 8280 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8281 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8282 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8283 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8284 ret = ring->wptr & ring->buf_mask; 8285 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8286 8287 return ret; 8288 } 8289 8290 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8291 { 8292 unsigned cur; 8293 BUG_ON(offset > ring->buf_mask); 8294 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8295 8296 cur = (ring->wptr - 1) & ring->buf_mask; 8297 if (likely(cur > offset)) 8298 ring->ring[offset] = cur - offset; 8299 else 8300 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8301 } 8302 8303 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8304 { 8305 int i, r = 0; 8306 struct amdgpu_device *adev = ring->adev; 8307 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8308 struct amdgpu_ring *kiq_ring = &kiq->ring; 8309 unsigned long flags; 8310 8311 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8312 return -EINVAL; 8313 8314 spin_lock_irqsave(&kiq->ring_lock, flags); 8315 8316 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8317 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8318 return -ENOMEM; 8319 } 8320 8321 /* assert preemption condition */ 8322 amdgpu_ring_set_preempt_cond_exec(ring, false); 8323 8324 /* assert IB preemption, emit the trailing fence */ 8325 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8326 ring->trail_fence_gpu_addr, 8327 ++ring->trail_seq); 8328 amdgpu_ring_commit(kiq_ring); 8329 8330 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8331 8332 /* poll the trailing fence */ 8333 for (i = 0; i < adev->usec_timeout; i++) { 8334 if (ring->trail_seq == 8335 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8336 break; 8337 udelay(1); 8338 } 8339 8340 if (i >= adev->usec_timeout) { 8341 r = -EINVAL; 8342 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8343 } 8344 8345 /* deassert preemption condition */ 8346 amdgpu_ring_set_preempt_cond_exec(ring, true); 8347 return r; 8348 } 8349 8350 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8351 { 8352 struct amdgpu_device *adev = ring->adev; 8353 struct v10_ce_ib_state ce_payload = {0}; 8354 uint64_t csa_addr; 8355 int cnt; 8356 8357 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8358 csa_addr = amdgpu_csa_vaddr(ring->adev); 8359 8360 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8361 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8362 WRITE_DATA_DST_SEL(8) | 8363 WR_CONFIRM) | 8364 WRITE_DATA_CACHE_POLICY(0)); 8365 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8366 offsetof(struct v10_gfx_meta_data, ce_payload))); 8367 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8368 offsetof(struct v10_gfx_meta_data, ce_payload))); 8369 8370 if (resume) 8371 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8372 offsetof(struct v10_gfx_meta_data, 8373 ce_payload), 8374 sizeof(ce_payload) >> 2); 8375 else 8376 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8377 sizeof(ce_payload) >> 2); 8378 } 8379 8380 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8381 { 8382 struct amdgpu_device *adev = ring->adev; 8383 struct v10_de_ib_state de_payload = {0}; 8384 uint64_t csa_addr, gds_addr; 8385 int cnt; 8386 8387 csa_addr = amdgpu_csa_vaddr(ring->adev); 8388 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8389 PAGE_SIZE); 8390 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8391 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8392 8393 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8394 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8395 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8396 WRITE_DATA_DST_SEL(8) | 8397 WR_CONFIRM) | 8398 WRITE_DATA_CACHE_POLICY(0)); 8399 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8400 offsetof(struct v10_gfx_meta_data, de_payload))); 8401 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8402 offsetof(struct v10_gfx_meta_data, de_payload))); 8403 8404 if (resume) 8405 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8406 offsetof(struct v10_gfx_meta_data, 8407 de_payload), 8408 sizeof(de_payload) >> 2); 8409 else 8410 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8411 sizeof(de_payload) >> 2); 8412 } 8413 8414 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8415 bool secure) 8416 { 8417 uint32_t v = secure ? FRAME_TMZ : 0; 8418 8419 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8420 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8421 } 8422 8423 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8424 uint32_t reg_val_offs) 8425 { 8426 struct amdgpu_device *adev = ring->adev; 8427 8428 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8429 amdgpu_ring_write(ring, 0 | /* src: register*/ 8430 (5 << 8) | /* dst: memory */ 8431 (1 << 20)); /* write confirm */ 8432 amdgpu_ring_write(ring, reg); 8433 amdgpu_ring_write(ring, 0); 8434 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8435 reg_val_offs * 4)); 8436 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8437 reg_val_offs * 4)); 8438 } 8439 8440 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8441 uint32_t val) 8442 { 8443 uint32_t cmd = 0; 8444 8445 switch (ring->funcs->type) { 8446 case AMDGPU_RING_TYPE_GFX: 8447 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8448 break; 8449 case AMDGPU_RING_TYPE_KIQ: 8450 cmd = (1 << 16); /* no inc addr */ 8451 break; 8452 default: 8453 cmd = WR_CONFIRM; 8454 break; 8455 } 8456 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8457 amdgpu_ring_write(ring, cmd); 8458 amdgpu_ring_write(ring, reg); 8459 amdgpu_ring_write(ring, 0); 8460 amdgpu_ring_write(ring, val); 8461 } 8462 8463 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8464 uint32_t val, uint32_t mask) 8465 { 8466 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8467 } 8468 8469 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8470 uint32_t reg0, uint32_t reg1, 8471 uint32_t ref, uint32_t mask) 8472 { 8473 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8474 struct amdgpu_device *adev = ring->adev; 8475 bool fw_version_ok = false; 8476 8477 fw_version_ok = adev->gfx.cp_fw_write_wait; 8478 8479 if (fw_version_ok) 8480 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8481 ref, mask, 0x20); 8482 else 8483 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8484 ref, mask); 8485 } 8486 8487 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8488 unsigned vmid) 8489 { 8490 struct amdgpu_device *adev = ring->adev; 8491 uint32_t value = 0; 8492 8493 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8494 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8495 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8496 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8497 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8498 } 8499 8500 static void 8501 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8502 uint32_t me, uint32_t pipe, 8503 enum amdgpu_interrupt_state state) 8504 { 8505 uint32_t cp_int_cntl, cp_int_cntl_reg; 8506 8507 if (!me) { 8508 switch (pipe) { 8509 case 0: 8510 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8511 break; 8512 case 1: 8513 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8514 break; 8515 default: 8516 DRM_DEBUG("invalid pipe %d\n", pipe); 8517 return; 8518 } 8519 } else { 8520 DRM_DEBUG("invalid me %d\n", me); 8521 return; 8522 } 8523 8524 switch (state) { 8525 case AMDGPU_IRQ_STATE_DISABLE: 8526 cp_int_cntl = RREG32(cp_int_cntl_reg); 8527 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8528 TIME_STAMP_INT_ENABLE, 0); 8529 WREG32(cp_int_cntl_reg, cp_int_cntl); 8530 break; 8531 case AMDGPU_IRQ_STATE_ENABLE: 8532 cp_int_cntl = RREG32(cp_int_cntl_reg); 8533 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8534 TIME_STAMP_INT_ENABLE, 1); 8535 WREG32(cp_int_cntl_reg, cp_int_cntl); 8536 break; 8537 default: 8538 break; 8539 } 8540 } 8541 8542 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8543 int me, int pipe, 8544 enum amdgpu_interrupt_state state) 8545 { 8546 u32 mec_int_cntl, mec_int_cntl_reg; 8547 8548 /* 8549 * amdgpu controls only the first MEC. That's why this function only 8550 * handles the setting of interrupts for this specific MEC. All other 8551 * pipes' interrupts are set by amdkfd. 8552 */ 8553 8554 if (me == 1) { 8555 switch (pipe) { 8556 case 0: 8557 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8558 break; 8559 case 1: 8560 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8561 break; 8562 case 2: 8563 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8564 break; 8565 case 3: 8566 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8567 break; 8568 default: 8569 DRM_DEBUG("invalid pipe %d\n", pipe); 8570 return; 8571 } 8572 } else { 8573 DRM_DEBUG("invalid me %d\n", me); 8574 return; 8575 } 8576 8577 switch (state) { 8578 case AMDGPU_IRQ_STATE_DISABLE: 8579 mec_int_cntl = RREG32(mec_int_cntl_reg); 8580 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8581 TIME_STAMP_INT_ENABLE, 0); 8582 WREG32(mec_int_cntl_reg, mec_int_cntl); 8583 break; 8584 case AMDGPU_IRQ_STATE_ENABLE: 8585 mec_int_cntl = RREG32(mec_int_cntl_reg); 8586 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8587 TIME_STAMP_INT_ENABLE, 1); 8588 WREG32(mec_int_cntl_reg, mec_int_cntl); 8589 break; 8590 default: 8591 break; 8592 } 8593 } 8594 8595 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8596 struct amdgpu_irq_src *src, 8597 unsigned type, 8598 enum amdgpu_interrupt_state state) 8599 { 8600 switch (type) { 8601 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8602 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8603 break; 8604 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8605 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8606 break; 8607 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8608 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8609 break; 8610 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8611 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8612 break; 8613 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8614 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8615 break; 8616 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8617 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8618 break; 8619 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8620 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8621 break; 8622 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8623 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8624 break; 8625 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8626 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8627 break; 8628 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8629 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8630 break; 8631 default: 8632 break; 8633 } 8634 return 0; 8635 } 8636 8637 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8638 struct amdgpu_irq_src *source, 8639 struct amdgpu_iv_entry *entry) 8640 { 8641 int i; 8642 u8 me_id, pipe_id, queue_id; 8643 struct amdgpu_ring *ring; 8644 8645 DRM_DEBUG("IH: CP EOP\n"); 8646 me_id = (entry->ring_id & 0x0c) >> 2; 8647 pipe_id = (entry->ring_id & 0x03) >> 0; 8648 queue_id = (entry->ring_id & 0x70) >> 4; 8649 8650 switch (me_id) { 8651 case 0: 8652 if (pipe_id == 0) 8653 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8654 else 8655 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8656 break; 8657 case 1: 8658 case 2: 8659 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8660 ring = &adev->gfx.compute_ring[i]; 8661 /* Per-queue interrupt is supported for MEC starting from VI. 8662 * The interrupt can only be enabled/disabled per pipe instead of per queue. 8663 */ 8664 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 8665 amdgpu_fence_process(ring); 8666 } 8667 break; 8668 } 8669 return 0; 8670 } 8671 8672 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8673 struct amdgpu_irq_src *source, 8674 unsigned type, 8675 enum amdgpu_interrupt_state state) 8676 { 8677 switch (state) { 8678 case AMDGPU_IRQ_STATE_DISABLE: 8679 case AMDGPU_IRQ_STATE_ENABLE: 8680 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8681 PRIV_REG_INT_ENABLE, 8682 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8683 break; 8684 default: 8685 break; 8686 } 8687 8688 return 0; 8689 } 8690 8691 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8692 struct amdgpu_irq_src *source, 8693 unsigned type, 8694 enum amdgpu_interrupt_state state) 8695 { 8696 switch (state) { 8697 case AMDGPU_IRQ_STATE_DISABLE: 8698 case AMDGPU_IRQ_STATE_ENABLE: 8699 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8700 PRIV_INSTR_INT_ENABLE, 8701 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8702 break; 8703 default: 8704 break; 8705 } 8706 8707 return 0; 8708 } 8709 8710 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8711 struct amdgpu_iv_entry *entry) 8712 { 8713 u8 me_id, pipe_id, queue_id; 8714 struct amdgpu_ring *ring; 8715 int i; 8716 8717 me_id = (entry->ring_id & 0x0c) >> 2; 8718 pipe_id = (entry->ring_id & 0x03) >> 0; 8719 queue_id = (entry->ring_id & 0x70) >> 4; 8720 8721 switch (me_id) { 8722 case 0: 8723 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 8724 ring = &adev->gfx.gfx_ring[i]; 8725 /* we only enabled 1 gfx queue per pipe for now */ 8726 if (ring->me == me_id && ring->pipe == pipe_id) 8727 drm_sched_fault(&ring->sched); 8728 } 8729 break; 8730 case 1: 8731 case 2: 8732 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8733 ring = &adev->gfx.compute_ring[i]; 8734 if (ring->me == me_id && ring->pipe == pipe_id && 8735 ring->queue == queue_id) 8736 drm_sched_fault(&ring->sched); 8737 } 8738 break; 8739 default: 8740 BUG(); 8741 } 8742 } 8743 8744 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 8745 struct amdgpu_irq_src *source, 8746 struct amdgpu_iv_entry *entry) 8747 { 8748 DRM_ERROR("Illegal register access in command stream\n"); 8749 gfx_v10_0_handle_priv_fault(adev, entry); 8750 return 0; 8751 } 8752 8753 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 8754 struct amdgpu_irq_src *source, 8755 struct amdgpu_iv_entry *entry) 8756 { 8757 DRM_ERROR("Illegal instruction in command stream\n"); 8758 gfx_v10_0_handle_priv_fault(adev, entry); 8759 return 0; 8760 } 8761 8762 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 8763 struct amdgpu_irq_src *src, 8764 unsigned int type, 8765 enum amdgpu_interrupt_state state) 8766 { 8767 uint32_t tmp, target; 8768 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8769 8770 if (ring->me == 1) 8771 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8772 else 8773 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 8774 target += ring->pipe; 8775 8776 switch (type) { 8777 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 8778 if (state == AMDGPU_IRQ_STATE_DISABLE) { 8779 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8780 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8781 GENERIC2_INT_ENABLE, 0); 8782 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8783 8784 tmp = RREG32(target); 8785 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8786 GENERIC2_INT_ENABLE, 0); 8787 WREG32(target, tmp); 8788 } else { 8789 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8790 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8791 GENERIC2_INT_ENABLE, 1); 8792 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8793 8794 tmp = RREG32(target); 8795 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8796 GENERIC2_INT_ENABLE, 1); 8797 WREG32(target, tmp); 8798 } 8799 break; 8800 default: 8801 BUG(); /* kiq only support GENERIC2_INT now */ 8802 break; 8803 } 8804 return 0; 8805 } 8806 8807 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 8808 struct amdgpu_irq_src *source, 8809 struct amdgpu_iv_entry *entry) 8810 { 8811 u8 me_id, pipe_id, queue_id; 8812 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8813 8814 me_id = (entry->ring_id & 0x0c) >> 2; 8815 pipe_id = (entry->ring_id & 0x03) >> 0; 8816 queue_id = (entry->ring_id & 0x70) >> 4; 8817 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 8818 me_id, pipe_id, queue_id); 8819 8820 amdgpu_fence_process(ring); 8821 return 0; 8822 } 8823 8824 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 8825 { 8826 const unsigned int gcr_cntl = 8827 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 8828 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 8829 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 8830 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 8831 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 8832 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 8833 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 8834 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 8835 8836 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 8837 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 8838 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 8839 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 8840 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 8841 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 8842 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 8843 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 8844 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 8845 } 8846 8847 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 8848 .name = "gfx_v10_0", 8849 .early_init = gfx_v10_0_early_init, 8850 .late_init = gfx_v10_0_late_init, 8851 .sw_init = gfx_v10_0_sw_init, 8852 .sw_fini = gfx_v10_0_sw_fini, 8853 .hw_init = gfx_v10_0_hw_init, 8854 .hw_fini = gfx_v10_0_hw_fini, 8855 .suspend = gfx_v10_0_suspend, 8856 .resume = gfx_v10_0_resume, 8857 .is_idle = gfx_v10_0_is_idle, 8858 .wait_for_idle = gfx_v10_0_wait_for_idle, 8859 .soft_reset = gfx_v10_0_soft_reset, 8860 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 8861 .set_powergating_state = gfx_v10_0_set_powergating_state, 8862 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 8863 }; 8864 8865 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 8866 .type = AMDGPU_RING_TYPE_GFX, 8867 .align_mask = 0xff, 8868 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8869 .support_64bit_ptrs = true, 8870 .vmhub = AMDGPU_GFXHUB_0, 8871 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 8872 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 8873 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 8874 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 8875 5 + /* COND_EXEC */ 8876 7 + /* PIPELINE_SYNC */ 8877 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8878 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8879 2 + /* VM_FLUSH */ 8880 8 + /* FENCE for VM_FLUSH */ 8881 20 + /* GDS switch */ 8882 4 + /* double SWITCH_BUFFER, 8883 * the first COND_EXEC jump to the place 8884 * just prior to this double SWITCH_BUFFER 8885 */ 8886 5 + /* COND_EXEC */ 8887 7 + /* HDP_flush */ 8888 4 + /* VGT_flush */ 8889 14 + /* CE_META */ 8890 31 + /* DE_META */ 8891 3 + /* CNTX_CTRL */ 8892 5 + /* HDP_INVL */ 8893 8 + 8 + /* FENCE x2 */ 8894 2 + /* SWITCH_BUFFER */ 8895 8, /* gfx_v10_0_emit_mem_sync */ 8896 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 8897 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 8898 .emit_fence = gfx_v10_0_ring_emit_fence, 8899 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8900 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8901 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8902 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8903 .test_ring = gfx_v10_0_ring_test_ring, 8904 .test_ib = gfx_v10_0_ring_test_ib, 8905 .insert_nop = amdgpu_ring_insert_nop, 8906 .pad_ib = amdgpu_ring_generic_pad_ib, 8907 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 8908 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 8909 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 8910 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 8911 .preempt_ib = gfx_v10_0_ring_preempt_ib, 8912 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 8913 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8914 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8915 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8916 .soft_recovery = gfx_v10_0_ring_soft_recovery, 8917 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8918 }; 8919 8920 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 8921 .type = AMDGPU_RING_TYPE_COMPUTE, 8922 .align_mask = 0xff, 8923 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8924 .support_64bit_ptrs = true, 8925 .vmhub = AMDGPU_GFXHUB_0, 8926 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8927 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8928 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8929 .emit_frame_size = 8930 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8931 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8932 5 + /* hdp invalidate */ 8933 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8934 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8935 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8936 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8937 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 8938 8, /* gfx_v10_0_emit_mem_sync */ 8939 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8940 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8941 .emit_fence = gfx_v10_0_ring_emit_fence, 8942 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8943 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8944 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8945 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8946 .test_ring = gfx_v10_0_ring_test_ring, 8947 .test_ib = gfx_v10_0_ring_test_ib, 8948 .insert_nop = amdgpu_ring_insert_nop, 8949 .pad_ib = amdgpu_ring_generic_pad_ib, 8950 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8951 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8952 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8953 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8954 }; 8955 8956 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 8957 .type = AMDGPU_RING_TYPE_KIQ, 8958 .align_mask = 0xff, 8959 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8960 .support_64bit_ptrs = true, 8961 .vmhub = AMDGPU_GFXHUB_0, 8962 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8963 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8964 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8965 .emit_frame_size = 8966 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8967 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8968 5 + /*hdp invalidate */ 8969 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8970 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8971 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8972 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8973 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 8974 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8975 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8976 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 8977 .test_ring = gfx_v10_0_ring_test_ring, 8978 .test_ib = gfx_v10_0_ring_test_ib, 8979 .insert_nop = amdgpu_ring_insert_nop, 8980 .pad_ib = amdgpu_ring_generic_pad_ib, 8981 .emit_rreg = gfx_v10_0_ring_emit_rreg, 8982 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8983 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8984 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8985 }; 8986 8987 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 8988 { 8989 int i; 8990 8991 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 8992 8993 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 8994 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 8995 8996 for (i = 0; i < adev->gfx.num_compute_rings; i++) 8997 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 8998 } 8999 9000 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9001 .set = gfx_v10_0_set_eop_interrupt_state, 9002 .process = gfx_v10_0_eop_irq, 9003 }; 9004 9005 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9006 .set = gfx_v10_0_set_priv_reg_fault_state, 9007 .process = gfx_v10_0_priv_reg_irq, 9008 }; 9009 9010 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9011 .set = gfx_v10_0_set_priv_inst_fault_state, 9012 .process = gfx_v10_0_priv_inst_irq, 9013 }; 9014 9015 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9016 .set = gfx_v10_0_kiq_set_interrupt_state, 9017 .process = gfx_v10_0_kiq_irq, 9018 }; 9019 9020 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9021 { 9022 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9023 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9024 9025 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9026 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9027 9028 adev->gfx.priv_reg_irq.num_types = 1; 9029 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9030 9031 adev->gfx.priv_inst_irq.num_types = 1; 9032 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9033 } 9034 9035 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9036 { 9037 switch (adev->asic_type) { 9038 case CHIP_NAVI10: 9039 case CHIP_NAVI14: 9040 case CHIP_SIENNA_CICHLID: 9041 case CHIP_NAVY_FLOUNDER: 9042 case CHIP_VANGOGH: 9043 case CHIP_DIMGREY_CAVEFISH: 9044 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9045 break; 9046 case CHIP_NAVI12: 9047 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9048 break; 9049 default: 9050 break; 9051 } 9052 } 9053 9054 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9055 { 9056 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9057 adev->gfx.config.max_sh_per_se * 9058 adev->gfx.config.max_shader_engines; 9059 9060 adev->gds.gds_size = 0x10000; 9061 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9062 adev->gds.gws_size = 64; 9063 adev->gds.oa_size = 16; 9064 } 9065 9066 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9067 u32 bitmap) 9068 { 9069 u32 data; 9070 9071 if (!bitmap) 9072 return; 9073 9074 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9075 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9076 9077 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9078 } 9079 9080 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9081 { 9082 u32 data, wgp_bitmask; 9083 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9084 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9085 9086 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9087 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9088 9089 wgp_bitmask = 9090 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9091 9092 return (~data) & wgp_bitmask; 9093 } 9094 9095 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9096 { 9097 u32 wgp_idx, wgp_active_bitmap; 9098 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9099 9100 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9101 cu_active_bitmap = 0; 9102 9103 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9104 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9105 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9106 if (wgp_active_bitmap & (1 << wgp_idx)) 9107 cu_active_bitmap |= cu_bitmap_per_wgp; 9108 } 9109 9110 return cu_active_bitmap; 9111 } 9112 9113 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9114 struct amdgpu_cu_info *cu_info) 9115 { 9116 int i, j, k, counter, active_cu_number = 0; 9117 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9118 unsigned disable_masks[4 * 2]; 9119 9120 if (!adev || !cu_info) 9121 return -EINVAL; 9122 9123 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9124 9125 mutex_lock(&adev->grbm_idx_mutex); 9126 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9127 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9128 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9129 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 9130 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9131 continue; 9132 mask = 1; 9133 ao_bitmap = 0; 9134 counter = 0; 9135 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9136 if (i < 4 && j < 2) 9137 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9138 adev, disable_masks[i * 2 + j]); 9139 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9140 cu_info->bitmap[i][j] = bitmap; 9141 9142 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9143 if (bitmap & mask) { 9144 if (counter < adev->gfx.config.max_cu_per_sh) 9145 ao_bitmap |= mask; 9146 counter++; 9147 } 9148 mask <<= 1; 9149 } 9150 active_cu_number += counter; 9151 if (i < 2 && j < 2) 9152 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9153 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9154 } 9155 } 9156 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9157 mutex_unlock(&adev->grbm_idx_mutex); 9158 9159 cu_info->number = active_cu_number; 9160 cu_info->ao_cu_mask = ao_cu_mask; 9161 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9162 9163 return 0; 9164 } 9165 9166 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9167 { 9168 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9169 9170 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9171 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9172 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9173 9174 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9175 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9176 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9177 9178 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9179 adev->gfx.config.max_shader_engines); 9180 disabled_sa = efuse_setting | vbios_setting; 9181 disabled_sa &= max_sa_mask; 9182 9183 return disabled_sa; 9184 } 9185 9186 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9187 { 9188 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9189 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9190 9191 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9192 9193 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9194 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9195 max_shader_engines = adev->gfx.config.max_shader_engines; 9196 9197 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9198 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9199 disabled_sa_per_se &= max_sa_per_se_mask; 9200 if (disabled_sa_per_se == max_sa_per_se_mask) { 9201 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9202 break; 9203 } 9204 } 9205 } 9206 9207 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9208 { 9209 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9210 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9211 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9212 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9213 9214 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9215 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9216 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9217 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9218 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9219 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9220 9221 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9222 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9223 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9224 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9225 9226 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9227 9228 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9229 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9230 } 9231 9232 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9233 { 9234 .type = AMD_IP_BLOCK_TYPE_GFX, 9235 .major = 10, 9236 .minor = 0, 9237 .rev = 0, 9238 .funcs = &gfx_v10_0_ip_funcs, 9239 }; 9240