1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "nv.h"
33 #include "nvd.h"
34 
35 #include "gc/gc_10_1_0_offset.h"
36 #include "gc/gc_10_1_0_sh_mask.h"
37 #include "smuio/smuio_11_0_0_offset.h"
38 #include "smuio/smuio_11_0_0_sh_mask.h"
39 #include "navi10_enum.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41 
42 #include "soc15.h"
43 #include "soc15d.h"
44 #include "soc15_common.h"
45 #include "clearstate_gfx10.h"
46 #include "v10_structs.h"
47 #include "gfx_v10_0.h"
48 #include "nbio_v2_3.h"
49 
50 /*
51  * Navi10 has two graphic rings to share each graphic pipe.
52  * 1. Primary ring
53  * 2. Async ring
54  */
55 #define GFX10_NUM_GFX_RINGS_NV1X	1
56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	2
57 #define GFX10_MEC_HPD_SIZE	2048
58 
59 #define F32_CE_PROGRAM_RAM_SIZE		65536
60 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
61 
62 #define mmCGTT_GS_NGG_CLK_CTRL	0x5087
63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68 
69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
71 
72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
76 
77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
79 #define mmRLC_SAFE_MODE_Sienna_Cichlid			0x4ca0
80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX		1
81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid		0x4ca1
82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX	1
83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid			0x11ec
84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX		0
85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid		0x0fc1
86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid		0x0fc2
88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid			0x0fc3
90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid		0x0fc4
92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX	0
93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid		0x0fc5
94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX	0
95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid		0x0fc6
96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX	0
97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT	0x1a
98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK	0x04000000L
99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK	0x00000FFCL
100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT	0x2
101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK	0x00000FFCL
102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
104 
105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
109 
110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
114 
115 #define mmSPI_CONFIG_CNTL_1_Vangogh		 0x2441
116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX	 1
117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
121 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
123 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
125 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
127 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
129 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
131 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
134 
135 #define mmCP_HYP_PFP_UCODE_ADDR			0x5814
136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1
137 #define mmCP_HYP_PFP_UCODE_DATA			0x5815
138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX	1
139 #define mmCP_HYP_CE_UCODE_ADDR			0x5818
140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX		1
141 #define mmCP_HYP_CE_UCODE_DATA			0x5819
142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX		1
143 #define mmCP_HYP_ME_UCODE_ADDR			0x5816
144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX		1
145 #define mmCP_HYP_ME_UCODE_DATA			0x5817
146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX		1
147 
148 #define mmCPG_PSP_DEBUG				0x5c10
149 #define mmCPG_PSP_DEBUG_BASE_IDX		1
150 #define mmCPC_PSP_DEBUG				0x5c11
151 #define mmCPC_PSP_DEBUG_BASE_IDX		1
152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
154 
155 //CC_GC_SA_UNIT_DISABLE
156 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK		0x0000FF00L
160 //GC_USER_SA_UNIT_DISABLE
161 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK	0x0000FF00L
165 //PA_SC_ENHANCE_3
166 #define mmPA_SC_ENHANCE_3                       0x1085
167 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
170 
171 #define mmCGTT_SPI_CS_CLK_CTRL			0x507c
172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
173 
174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid		0x16f3
175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0
176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0
178 
179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
181 
182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
184 
185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
187 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
191 
192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
199 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
203 
204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
206 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
210 
211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
217 
218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
224 
225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
231 
232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
238 
239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
245 
246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
252 
253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
259 
260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
266 
267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
273 
274 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
275 {
276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
316 };
317 
318 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
319 {
320 	/* Pending on emulation bring up */
321 };
322 
323 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
324 {
325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1377 };
1378 
1379 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1380 {
1381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1419 };
1420 
1421 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1422 {
1423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1465 };
1466 
1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1468 {
1469 	/* Pending on emulation bring up */
1470 };
1471 
1472 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1473 {
1474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2094 };
2095 
2096 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2097 {
2098 	/* Pending on emulation bring up */
2099 };
2100 
2101 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2102 {
2103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3155 };
3156 
3157 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3158 {
3159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3167 	SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3202 };
3203 
3204 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3205 {
3206 	/* Pending on emulation bring up */
3207 };
3208 
3209 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3210 {
3211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3252 
3253 	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3255 };
3256 
3257 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3258 {
3259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3283 
3284 	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3286 };
3287 
3288 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3289 {
3290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3310 };
3311 
3312 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3313 {
3314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3350 };
3351 
3352 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3385 };
3386 
3387 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3422 };
3423 
3424 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
3425 {
3426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3448 };
3449 
3450 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3473 };
3474 
3475 #define DEFAULT_SH_MEM_CONFIG \
3476 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3477 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3478 	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3479 	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3480 
3481 /* TODO: pending on golden setting value of gb address config */
3482 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3483 
3484 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3485 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3486 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3487 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3488 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3489 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3490 				 struct amdgpu_cu_info *cu_info);
3491 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3493 				   u32 sh_num, u32 instance);
3494 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3495 
3496 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3497 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3498 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3499 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3500 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3501 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3502 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3503 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3504 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3505 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3506 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3507 					   uint16_t pasid, uint32_t flush_type,
3508 					   bool all_hub, uint8_t dst_sel);
3509 
3510 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3511 {
3512 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3513 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3514 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
3515 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
3516 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
3517 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
3518 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
3519 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
3520 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
3521 }
3522 
3523 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3524 				 struct amdgpu_ring *ring)
3525 {
3526 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3527 	uint64_t wptr_addr = ring->wptr_gpu_addr;
3528 	uint32_t eng_sel = 0;
3529 
3530 	switch (ring->funcs->type) {
3531 	case AMDGPU_RING_TYPE_COMPUTE:
3532 		eng_sel = 0;
3533 		break;
3534 	case AMDGPU_RING_TYPE_GFX:
3535 		eng_sel = 4;
3536 		break;
3537 	case AMDGPU_RING_TYPE_MES:
3538 		eng_sel = 5;
3539 		break;
3540 	default:
3541 		WARN_ON(1);
3542 	}
3543 
3544 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3545 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3546 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3547 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3548 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3549 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3550 			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3551 			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3552 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3553 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3554 			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3555 			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3556 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3557 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3558 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3559 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3560 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3561 }
3562 
3563 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3564 				   struct amdgpu_ring *ring,
3565 				   enum amdgpu_unmap_queues_action action,
3566 				   u64 gpu_addr, u64 seq)
3567 {
3568 	struct amdgpu_device *adev = kiq_ring->adev;
3569 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3570 
3571 	if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) {
3572 		amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3573 		return;
3574 	}
3575 
3576 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3577 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3578 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
3579 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3580 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3581 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3582 	amdgpu_ring_write(kiq_ring,
3583 		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3584 
3585 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
3586 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3587 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3588 		amdgpu_ring_write(kiq_ring, seq);
3589 	} else {
3590 		amdgpu_ring_write(kiq_ring, 0);
3591 		amdgpu_ring_write(kiq_ring, 0);
3592 		amdgpu_ring_write(kiq_ring, 0);
3593 	}
3594 }
3595 
3596 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3597 				   struct amdgpu_ring *ring,
3598 				   u64 addr,
3599 				   u64 seq)
3600 {
3601 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3602 
3603 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3604 	amdgpu_ring_write(kiq_ring,
3605 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3606 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3607 			  PACKET3_QUERY_STATUS_COMMAND(2));
3608 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3609 			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3610 			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3611 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3612 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3613 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3614 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3615 }
3616 
3617 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3618 				uint16_t pasid, uint32_t flush_type,
3619 				bool all_hub)
3620 {
3621 	gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3622 }
3623 
3624 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3625 	.kiq_set_resources = gfx10_kiq_set_resources,
3626 	.kiq_map_queues = gfx10_kiq_map_queues,
3627 	.kiq_unmap_queues = gfx10_kiq_unmap_queues,
3628 	.kiq_query_status = gfx10_kiq_query_status,
3629 	.kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3630 	.set_resources_size = 8,
3631 	.map_queues_size = 7,
3632 	.unmap_queues_size = 6,
3633 	.query_status_size = 7,
3634 	.invalidate_tlbs_size = 2,
3635 };
3636 
3637 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3638 {
3639 	adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3640 }
3641 
3642 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3643 {
3644 	switch (adev->ip_versions[GC_HWIP][0]) {
3645 	case IP_VERSION(10, 1, 10):
3646 		soc15_program_register_sequence(adev,
3647 						golden_settings_gc_rlc_spm_10_0_nv10,
3648 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3649 		break;
3650 	case IP_VERSION(10, 1, 1):
3651 		soc15_program_register_sequence(adev,
3652 						golden_settings_gc_rlc_spm_10_1_nv14,
3653 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3654 		break;
3655 	case IP_VERSION(10, 1, 2):
3656 		soc15_program_register_sequence(adev,
3657 						golden_settings_gc_rlc_spm_10_1_2_nv12,
3658 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3659 		break;
3660 	default:
3661 		break;
3662 	}
3663 }
3664 
3665 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3666 {
3667 	switch (adev->ip_versions[GC_HWIP][0]) {
3668 	case IP_VERSION(10, 1, 10):
3669 		soc15_program_register_sequence(adev,
3670 						golden_settings_gc_10_1,
3671 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3672 		soc15_program_register_sequence(adev,
3673 						golden_settings_gc_10_0_nv10,
3674 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3675 		break;
3676 	case IP_VERSION(10, 1, 1):
3677 		soc15_program_register_sequence(adev,
3678 						golden_settings_gc_10_1_1,
3679 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3680 		soc15_program_register_sequence(adev,
3681 						golden_settings_gc_10_1_nv14,
3682 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3683 		break;
3684 	case IP_VERSION(10, 1, 2):
3685 		soc15_program_register_sequence(adev,
3686 						golden_settings_gc_10_1_2,
3687 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3688 		soc15_program_register_sequence(adev,
3689 						golden_settings_gc_10_1_2_nv12,
3690 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3691 		break;
3692 	case IP_VERSION(10, 3, 0):
3693 		soc15_program_register_sequence(adev,
3694 						golden_settings_gc_10_3,
3695 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3696 		soc15_program_register_sequence(adev,
3697 						golden_settings_gc_10_3_sienna_cichlid,
3698 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3699 		break;
3700 	case IP_VERSION(10, 3, 2):
3701 		soc15_program_register_sequence(adev,
3702 						golden_settings_gc_10_3_2,
3703 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3704 		break;
3705 	case IP_VERSION(10, 3, 1):
3706 		soc15_program_register_sequence(adev,
3707 						golden_settings_gc_10_3_vangogh,
3708 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3709 		break;
3710 	case IP_VERSION(10, 3, 3):
3711 		soc15_program_register_sequence(adev,
3712 						golden_settings_gc_10_3_3,
3713 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3714 		break;
3715 	case IP_VERSION(10, 3, 4):
3716 		soc15_program_register_sequence(adev,
3717                                                 golden_settings_gc_10_3_4,
3718                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3719 		break;
3720 	case IP_VERSION(10, 3, 5):
3721 		soc15_program_register_sequence(adev,
3722 						golden_settings_gc_10_3_5,
3723 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3724 		break;
3725 	case IP_VERSION(10, 1, 3):
3726 	case IP_VERSION(10, 1, 4):
3727 		soc15_program_register_sequence(adev,
3728 						golden_settings_gc_10_0_cyan_skillfish,
3729 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3730 		break;
3731 	case IP_VERSION(10, 3, 6):
3732 		soc15_program_register_sequence(adev,
3733 						golden_settings_gc_10_3_6,
3734 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3735 		break;
3736 	case IP_VERSION(10, 3, 7):
3737 		soc15_program_register_sequence(adev,
3738 						golden_settings_gc_10_3_7,
3739 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3740 		break;
3741 	default:
3742 		break;
3743 	}
3744 	gfx_v10_0_init_spm_golden_registers(adev);
3745 }
3746 
3747 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3748 				       bool wc, uint32_t reg, uint32_t val)
3749 {
3750 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3751 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3752 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3753 	amdgpu_ring_write(ring, reg);
3754 	amdgpu_ring_write(ring, 0);
3755 	amdgpu_ring_write(ring, val);
3756 }
3757 
3758 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3759 				  int mem_space, int opt, uint32_t addr0,
3760 				  uint32_t addr1, uint32_t ref, uint32_t mask,
3761 				  uint32_t inv)
3762 {
3763 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3764 	amdgpu_ring_write(ring,
3765 			  /* memory (1) or register (0) */
3766 			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3767 			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
3768 			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3769 			   WAIT_REG_MEM_ENGINE(eng_sel)));
3770 
3771 	if (mem_space)
3772 		BUG_ON(addr0 & 0x3); /* Dword align */
3773 	amdgpu_ring_write(ring, addr0);
3774 	amdgpu_ring_write(ring, addr1);
3775 	amdgpu_ring_write(ring, ref);
3776 	amdgpu_ring_write(ring, mask);
3777 	amdgpu_ring_write(ring, inv); /* poll interval */
3778 }
3779 
3780 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3781 {
3782 	struct amdgpu_device *adev = ring->adev;
3783 	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3784 	uint32_t tmp = 0;
3785 	unsigned i;
3786 	int r;
3787 
3788 	WREG32(scratch, 0xCAFEDEAD);
3789 	r = amdgpu_ring_alloc(ring, 3);
3790 	if (r) {
3791 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3792 			  ring->idx, r);
3793 		return r;
3794 	}
3795 
3796 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3797 	amdgpu_ring_write(ring, scratch -
3798 			  PACKET3_SET_UCONFIG_REG_START);
3799 	amdgpu_ring_write(ring, 0xDEADBEEF);
3800 	amdgpu_ring_commit(ring);
3801 
3802 	for (i = 0; i < adev->usec_timeout; i++) {
3803 		tmp = RREG32(scratch);
3804 		if (tmp == 0xDEADBEEF)
3805 			break;
3806 		if (amdgpu_emu_mode == 1)
3807 			msleep(1);
3808 		else
3809 			udelay(1);
3810 	}
3811 
3812 	if (i >= adev->usec_timeout)
3813 		r = -ETIMEDOUT;
3814 
3815 	return r;
3816 }
3817 
3818 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3819 {
3820 	struct amdgpu_device *adev = ring->adev;
3821 	struct amdgpu_ib ib;
3822 	struct dma_fence *f = NULL;
3823 	unsigned index;
3824 	uint64_t gpu_addr;
3825 	volatile uint32_t *cpu_ptr;
3826 	long r;
3827 
3828 	memset(&ib, 0, sizeof(ib));
3829 
3830 	if (ring->is_mes_queue) {
3831 		uint32_t padding, offset;
3832 
3833 		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3834 		padding = amdgpu_mes_ctx_get_offs(ring,
3835 						  AMDGPU_MES_CTX_PADDING_OFFS);
3836 
3837 		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
3838 		ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
3839 
3840 		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
3841 		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
3842 		*cpu_ptr = cpu_to_le32(0xCAFEDEAD);
3843 	} else {
3844 		r = amdgpu_device_wb_get(adev, &index);
3845 		if (r)
3846 			return r;
3847 
3848 		gpu_addr = adev->wb.gpu_addr + (index * 4);
3849 		adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3850 		cpu_ptr = &adev->wb.wb[index];
3851 
3852 		r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
3853 		if (r) {
3854 			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3855 			goto err1;
3856 		}
3857 	}
3858 
3859 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3860 	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3861 	ib.ptr[2] = lower_32_bits(gpu_addr);
3862 	ib.ptr[3] = upper_32_bits(gpu_addr);
3863 	ib.ptr[4] = 0xDEADBEEF;
3864 	ib.length_dw = 5;
3865 
3866 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3867 	if (r)
3868 		goto err2;
3869 
3870 	r = dma_fence_wait_timeout(f, false, timeout);
3871 	if (r == 0) {
3872 		r = -ETIMEDOUT;
3873 		goto err2;
3874 	} else if (r < 0) {
3875 		goto err2;
3876 	}
3877 
3878 	if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3879 		r = 0;
3880 	else
3881 		r = -EINVAL;
3882 err2:
3883 	if (!ring->is_mes_queue)
3884 		amdgpu_ib_free(adev, &ib, NULL);
3885 	dma_fence_put(f);
3886 err1:
3887 	if (!ring->is_mes_queue)
3888 		amdgpu_device_wb_free(adev, index);
3889 	return r;
3890 }
3891 
3892 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3893 {
3894 	release_firmware(adev->gfx.pfp_fw);
3895 	adev->gfx.pfp_fw = NULL;
3896 	release_firmware(adev->gfx.me_fw);
3897 	adev->gfx.me_fw = NULL;
3898 	release_firmware(adev->gfx.ce_fw);
3899 	adev->gfx.ce_fw = NULL;
3900 	release_firmware(adev->gfx.rlc_fw);
3901 	adev->gfx.rlc_fw = NULL;
3902 	release_firmware(adev->gfx.mec_fw);
3903 	adev->gfx.mec_fw = NULL;
3904 	release_firmware(adev->gfx.mec2_fw);
3905 	adev->gfx.mec2_fw = NULL;
3906 
3907 	kfree(adev->gfx.rlc.register_list_format);
3908 }
3909 
3910 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3911 {
3912 	adev->gfx.cp_fw_write_wait = false;
3913 
3914 	switch (adev->ip_versions[GC_HWIP][0]) {
3915 	case IP_VERSION(10, 1, 10):
3916 	case IP_VERSION(10, 1, 2):
3917 	case IP_VERSION(10, 1, 1):
3918 	case IP_VERSION(10, 1, 3):
3919 	case IP_VERSION(10, 1, 4):
3920 		if ((adev->gfx.me_fw_version >= 0x00000046) &&
3921 		    (adev->gfx.me_feature_version >= 27) &&
3922 		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
3923 		    (adev->gfx.pfp_feature_version >= 27) &&
3924 		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
3925 		    (adev->gfx.mec_feature_version >= 27))
3926 			adev->gfx.cp_fw_write_wait = true;
3927 		break;
3928 	case IP_VERSION(10, 3, 0):
3929 	case IP_VERSION(10, 3, 2):
3930 	case IP_VERSION(10, 3, 1):
3931 	case IP_VERSION(10, 3, 4):
3932 	case IP_VERSION(10, 3, 5):
3933 	case IP_VERSION(10, 3, 6):
3934 	case IP_VERSION(10, 3, 3):
3935 	case IP_VERSION(10, 3, 7):
3936 		adev->gfx.cp_fw_write_wait = true;
3937 		break;
3938 	default:
3939 		break;
3940 	}
3941 
3942 	if (!adev->gfx.cp_fw_write_wait)
3943 		DRM_WARN_ONCE("CP firmware version too old, please update!");
3944 }
3945 
3946 
3947 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3948 {
3949 	const struct rlc_firmware_header_v2_1 *rlc_hdr;
3950 
3951 	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3952 	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3953 	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3954 	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3955 	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3956 	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3957 	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3958 	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3959 	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3960 	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3961 	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3962 	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3963 	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3964 	adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3965 			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3966 }
3967 
3968 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3969 {
3970 	const struct rlc_firmware_header_v2_2 *rlc_hdr;
3971 
3972 	rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3973 	adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3974 	adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3975 	adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3976 	adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3977 }
3978 
3979 static void gfx_v10_0_init_tap_delays_microcode(struct amdgpu_device *adev)
3980 {
3981 	const struct rlc_firmware_header_v2_4 *rlc_hdr;
3982 
3983 	rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;
3984 	adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);
3985 	adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);
3986 	adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);
3987 	adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);
3988 	adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);
3989 	adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);
3990 	adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);
3991 	adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);
3992 	adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);
3993 	adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);
3994 }
3995 
3996 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3997 {
3998 	bool ret = false;
3999 
4000 	switch (adev->pdev->revision) {
4001 	case 0xc2:
4002 	case 0xc3:
4003 		ret = true;
4004 		break;
4005 	default:
4006 		ret = false;
4007 		break;
4008 	}
4009 
4010 	return ret ;
4011 }
4012 
4013 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4014 {
4015 	switch (adev->ip_versions[GC_HWIP][0]) {
4016 	case IP_VERSION(10, 1, 10):
4017 		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4018 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4019 		break;
4020 	default:
4021 		break;
4022 	}
4023 }
4024 
4025 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4026 {
4027 	const char *chip_name;
4028 	char fw_name[40];
4029 	char *wks = "";
4030 	int err;
4031 	struct amdgpu_firmware_info *info = NULL;
4032 	const struct common_firmware_header *header = NULL;
4033 	const struct gfx_firmware_header_v1_0 *cp_hdr;
4034 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
4035 	unsigned int *tmp = NULL;
4036 	unsigned int i = 0;
4037 	uint16_t version_major;
4038 	uint16_t version_minor;
4039 
4040 	DRM_DEBUG("\n");
4041 
4042 	switch (adev->ip_versions[GC_HWIP][0]) {
4043 	case IP_VERSION(10, 1, 10):
4044 		chip_name = "navi10";
4045 		break;
4046 	case IP_VERSION(10, 1, 1):
4047 		chip_name = "navi14";
4048 		if (!(adev->pdev->device == 0x7340 &&
4049 		      adev->pdev->revision != 0x00))
4050 			wks = "_wks";
4051 		break;
4052 	case IP_VERSION(10, 1, 2):
4053 		chip_name = "navi12";
4054 		break;
4055 	case IP_VERSION(10, 3, 0):
4056 		chip_name = "sienna_cichlid";
4057 		break;
4058 	case IP_VERSION(10, 3, 2):
4059 		chip_name = "navy_flounder";
4060 		break;
4061 	case IP_VERSION(10, 3, 1):
4062 		chip_name = "vangogh";
4063 		break;
4064 	case IP_VERSION(10, 3, 4):
4065 		chip_name = "dimgrey_cavefish";
4066 		break;
4067 	case IP_VERSION(10, 3, 5):
4068 		chip_name = "beige_goby";
4069 		break;
4070 	case IP_VERSION(10, 3, 3):
4071 		chip_name = "yellow_carp";
4072 		break;
4073 	case IP_VERSION(10, 3, 6):
4074 		chip_name = "gc_10_3_6";
4075 		break;
4076 	case IP_VERSION(10, 1, 3):
4077 	case IP_VERSION(10, 1, 4):
4078 		chip_name = "cyan_skillfish2";
4079 		break;
4080 	case IP_VERSION(10, 3, 7):
4081 		chip_name = "gc_10_3_7";
4082 		break;
4083 	default:
4084 		BUG();
4085 	}
4086 
4087 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4088 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4089 	if (err)
4090 		goto out;
4091 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4092 	if (err)
4093 		goto out;
4094 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4095 	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4096 	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4097 
4098 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4099 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4100 	if (err)
4101 		goto out;
4102 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
4103 	if (err)
4104 		goto out;
4105 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4106 	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4107 	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4108 
4109 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4110 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4111 	if (err)
4112 		goto out;
4113 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4114 	if (err)
4115 		goto out;
4116 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4117 	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4118 	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4119 
4120 	if (!amdgpu_sriov_vf(adev)) {
4121 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4122 		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4123 		if (err)
4124 			goto out;
4125 		err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4126 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4127 		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4128 		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4129 
4130 		adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4131 		adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4132 		adev->gfx.rlc.save_and_restore_offset =
4133 			le32_to_cpu(rlc_hdr->save_and_restore_offset);
4134 		adev->gfx.rlc.clear_state_descriptor_offset =
4135 			le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4136 		adev->gfx.rlc.avail_scratch_ram_locations =
4137 			le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4138 		adev->gfx.rlc.reg_restore_list_size =
4139 			le32_to_cpu(rlc_hdr->reg_restore_list_size);
4140 		adev->gfx.rlc.reg_list_format_start =
4141 			le32_to_cpu(rlc_hdr->reg_list_format_start);
4142 		adev->gfx.rlc.reg_list_format_separate_start =
4143 			le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4144 		adev->gfx.rlc.starting_offsets_start =
4145 			le32_to_cpu(rlc_hdr->starting_offsets_start);
4146 		adev->gfx.rlc.reg_list_format_size_bytes =
4147 			le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4148 		adev->gfx.rlc.reg_list_size_bytes =
4149 			le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4150 		adev->gfx.rlc.register_list_format =
4151 			kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4152 					adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4153 		if (!adev->gfx.rlc.register_list_format) {
4154 			err = -ENOMEM;
4155 			goto out;
4156 		}
4157 
4158 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4159 							   le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4160 		for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4161 			adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
4162 
4163 		adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4164 
4165 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4166 							   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4167 		for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4168 			adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4169 
4170 		if (version_major == 2) {
4171 			if (version_minor >= 1)
4172 				gfx_v10_0_init_rlc_ext_microcode(adev);
4173 			if (version_minor >= 2)
4174 				gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4175 			if (version_minor == 4) {
4176 				gfx_v10_0_init_tap_delays_microcode(adev);
4177 			}
4178 		}
4179 	}
4180 
4181 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4182 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4183 	if (err)
4184 		goto out;
4185 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4186 	if (err)
4187 		goto out;
4188 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4189 	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4190 	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4191 
4192 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4193 	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4194 	if (!err) {
4195 		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4196 		if (err)
4197 			goto out;
4198 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4199 		adev->gfx.mec2_fw->data;
4200 		adev->gfx.mec2_fw_version =
4201 		le32_to_cpu(cp_hdr->header.ucode_version);
4202 		adev->gfx.mec2_feature_version =
4203 		le32_to_cpu(cp_hdr->ucode_feature_version);
4204 	} else {
4205 		err = 0;
4206 		adev->gfx.mec2_fw = NULL;
4207 	}
4208 
4209 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4210 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4211 		info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4212 		info->fw = adev->gfx.pfp_fw;
4213 		header = (const struct common_firmware_header *)info->fw->data;
4214 		adev->firmware.fw_size +=
4215 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4216 
4217 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4218 		info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4219 		info->fw = adev->gfx.me_fw;
4220 		header = (const struct common_firmware_header *)info->fw->data;
4221 		adev->firmware.fw_size +=
4222 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4223 
4224 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4225 		info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4226 		info->fw = adev->gfx.ce_fw;
4227 		header = (const struct common_firmware_header *)info->fw->data;
4228 		adev->firmware.fw_size +=
4229 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4230 
4231 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4232 		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4233 		info->fw = adev->gfx.rlc_fw;
4234 		if (info->fw) {
4235 			header = (const struct common_firmware_header *)info->fw->data;
4236 			adev->firmware.fw_size +=
4237 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4238 		}
4239 		if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4240 		    adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4241 		    adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4242 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4243 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4244 			info->fw = adev->gfx.rlc_fw;
4245 			adev->firmware.fw_size +=
4246 				ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4247 
4248 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4249 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4250 			info->fw = adev->gfx.rlc_fw;
4251 			adev->firmware.fw_size +=
4252 				ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4253 
4254 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4255 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4256 			info->fw = adev->gfx.rlc_fw;
4257 			adev->firmware.fw_size +=
4258 				ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4259 
4260 			if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4261 			    adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4262 				info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4263 				info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4264 				info->fw = adev->gfx.rlc_fw;
4265 				adev->firmware.fw_size +=
4266 					ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4267 
4268 				info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4269 				info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4270 				info->fw = adev->gfx.rlc_fw;
4271 				adev->firmware.fw_size +=
4272 					ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4273 			}
4274 
4275 		}
4276 
4277 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];
4278 		info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;
4279 		info->fw = adev->gfx.rlc_fw;
4280 		adev->firmware.fw_size +=
4281 			ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);
4282 
4283 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];
4284 		info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;
4285 		info->fw = adev->gfx.rlc_fw;
4286 		adev->firmware.fw_size +=
4287 			ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);
4288 
4289 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];
4290 		info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;
4291 		info->fw = adev->gfx.rlc_fw;
4292 		adev->firmware.fw_size +=
4293 			ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);
4294 
4295 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];
4296 		info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;
4297 		info->fw = adev->gfx.rlc_fw;
4298 		adev->firmware.fw_size +=
4299 			ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);
4300 
4301 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];
4302 		info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;
4303 		info->fw = adev->gfx.rlc_fw;
4304 		adev->firmware.fw_size +=
4305 			ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);
4306 
4307 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4308 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4309 		info->fw = adev->gfx.mec_fw;
4310 		header = (const struct common_firmware_header *)info->fw->data;
4311 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4312 		adev->firmware.fw_size +=
4313 			ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4314 			      le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4315 
4316 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4317 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4318 		info->fw = adev->gfx.mec_fw;
4319 		adev->firmware.fw_size +=
4320 			ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4321 
4322 		if (adev->gfx.mec2_fw) {
4323 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4324 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4325 			info->fw = adev->gfx.mec2_fw;
4326 			header = (const struct common_firmware_header *)info->fw->data;
4327 			cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4328 			adev->firmware.fw_size +=
4329 				ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4330 				      le32_to_cpu(cp_hdr->jt_size) * 4,
4331 				      PAGE_SIZE);
4332 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4333 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4334 			info->fw = adev->gfx.mec2_fw;
4335 			adev->firmware.fw_size +=
4336 				ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4337 				      PAGE_SIZE);
4338 		}
4339 	}
4340 
4341 	gfx_v10_0_check_fw_write_wait(adev);
4342 out:
4343 	if (err) {
4344 		dev_err(adev->dev,
4345 			"gfx10: Failed to load firmware \"%s\"\n",
4346 			fw_name);
4347 		release_firmware(adev->gfx.pfp_fw);
4348 		adev->gfx.pfp_fw = NULL;
4349 		release_firmware(adev->gfx.me_fw);
4350 		adev->gfx.me_fw = NULL;
4351 		release_firmware(adev->gfx.ce_fw);
4352 		adev->gfx.ce_fw = NULL;
4353 		release_firmware(adev->gfx.rlc_fw);
4354 		adev->gfx.rlc_fw = NULL;
4355 		release_firmware(adev->gfx.mec_fw);
4356 		adev->gfx.mec_fw = NULL;
4357 		release_firmware(adev->gfx.mec2_fw);
4358 		adev->gfx.mec2_fw = NULL;
4359 	}
4360 
4361 	gfx_v10_0_check_gfxoff_flag(adev);
4362 
4363 	return err;
4364 }
4365 
4366 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4367 {
4368 	u32 count = 0;
4369 	const struct cs_section_def *sect = NULL;
4370 	const struct cs_extent_def *ext = NULL;
4371 
4372 	/* begin clear state */
4373 	count += 2;
4374 	/* context control state */
4375 	count += 3;
4376 
4377 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4378 		for (ext = sect->section; ext->extent != NULL; ++ext) {
4379 			if (sect->id == SECT_CONTEXT)
4380 				count += 2 + ext->reg_count;
4381 			else
4382 				return 0;
4383 		}
4384 	}
4385 
4386 	/* set PA_SC_TILE_STEERING_OVERRIDE */
4387 	count += 3;
4388 	/* end clear state */
4389 	count += 2;
4390 	/* clear state */
4391 	count += 2;
4392 
4393 	return count;
4394 }
4395 
4396 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4397 				    volatile u32 *buffer)
4398 {
4399 	u32 count = 0, i;
4400 	const struct cs_section_def *sect = NULL;
4401 	const struct cs_extent_def *ext = NULL;
4402 	int ctx_reg_offset;
4403 
4404 	if (adev->gfx.rlc.cs_data == NULL)
4405 		return;
4406 	if (buffer == NULL)
4407 		return;
4408 
4409 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4410 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4411 
4412 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4413 	buffer[count++] = cpu_to_le32(0x80000000);
4414 	buffer[count++] = cpu_to_le32(0x80000000);
4415 
4416 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4417 		for (ext = sect->section; ext->extent != NULL; ++ext) {
4418 			if (sect->id == SECT_CONTEXT) {
4419 				buffer[count++] =
4420 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4421 				buffer[count++] = cpu_to_le32(ext->reg_index -
4422 						PACKET3_SET_CONTEXT_REG_START);
4423 				for (i = 0; i < ext->reg_count; i++)
4424 					buffer[count++] = cpu_to_le32(ext->extent[i]);
4425 			} else {
4426 				return;
4427 			}
4428 		}
4429 	}
4430 
4431 	ctx_reg_offset =
4432 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4433 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4434 	buffer[count++] = cpu_to_le32(ctx_reg_offset);
4435 	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4436 
4437 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4438 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4439 
4440 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4441 	buffer[count++] = cpu_to_le32(0);
4442 }
4443 
4444 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4445 {
4446 	/* clear state block */
4447 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4448 			&adev->gfx.rlc.clear_state_gpu_addr,
4449 			(void **)&adev->gfx.rlc.cs_ptr);
4450 
4451 	/* jump table block */
4452 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4453 			&adev->gfx.rlc.cp_table_gpu_addr,
4454 			(void **)&adev->gfx.rlc.cp_table_ptr);
4455 }
4456 
4457 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4458 {
4459 	struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4460 
4461 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
4462 	reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4463 	reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4464 	reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4465 	reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4466 	reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4467 	reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4468 	switch (adev->ip_versions[GC_HWIP][0]) {
4469 		case IP_VERSION(10, 3, 0):
4470 			reg_access_ctrl->spare_int =
4471 				SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4472 			break;
4473 		default:
4474 			reg_access_ctrl->spare_int =
4475 				SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4476 			break;
4477 	}
4478 	adev->gfx.rlc.rlcg_reg_access_supported = true;
4479 }
4480 
4481 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4482 {
4483 	const struct cs_section_def *cs_data;
4484 	int r;
4485 
4486 	adev->gfx.rlc.cs_data = gfx10_cs_data;
4487 
4488 	cs_data = adev->gfx.rlc.cs_data;
4489 
4490 	if (cs_data) {
4491 		/* init clear state block */
4492 		r = amdgpu_gfx_rlc_init_csb(adev);
4493 		if (r)
4494 			return r;
4495 	}
4496 
4497 	/* init spm vmid with 0xf */
4498 	if (adev->gfx.rlc.funcs->update_spm_vmid)
4499 		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4500 
4501 
4502 	return 0;
4503 }
4504 
4505 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4506 {
4507 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4508 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4509 }
4510 
4511 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4512 {
4513 	int r;
4514 
4515 	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4516 
4517 	amdgpu_gfx_graphics_queue_acquire(adev);
4518 
4519 	r = gfx_v10_0_init_microcode(adev);
4520 	if (r)
4521 		DRM_ERROR("Failed to load gfx firmware!\n");
4522 
4523 	return r;
4524 }
4525 
4526 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4527 {
4528 	int r;
4529 	u32 *hpd;
4530 	const __le32 *fw_data = NULL;
4531 	unsigned fw_size;
4532 	u32 *fw = NULL;
4533 	size_t mec_hpd_size;
4534 
4535 	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4536 
4537 	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4538 
4539 	/* take ownership of the relevant compute queues */
4540 	amdgpu_gfx_compute_queue_acquire(adev);
4541 	mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4542 
4543 	if (mec_hpd_size) {
4544 		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4545 					      AMDGPU_GEM_DOMAIN_GTT,
4546 					      &adev->gfx.mec.hpd_eop_obj,
4547 					      &adev->gfx.mec.hpd_eop_gpu_addr,
4548 					      (void **)&hpd);
4549 		if (r) {
4550 			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4551 			gfx_v10_0_mec_fini(adev);
4552 			return r;
4553 		}
4554 
4555 		memset(hpd, 0, mec_hpd_size);
4556 
4557 		amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4558 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4559 	}
4560 
4561 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4562 		mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4563 
4564 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4565 			 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4566 		fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4567 
4568 		r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4569 					      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4570 					      &adev->gfx.mec.mec_fw_obj,
4571 					      &adev->gfx.mec.mec_fw_gpu_addr,
4572 					      (void **)&fw);
4573 		if (r) {
4574 			dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4575 			gfx_v10_0_mec_fini(adev);
4576 			return r;
4577 		}
4578 
4579 		memcpy(fw, fw_data, fw_size);
4580 
4581 		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4582 		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4583 	}
4584 
4585 	return 0;
4586 }
4587 
4588 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4589 {
4590 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4591 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4592 		(address << SQ_IND_INDEX__INDEX__SHIFT));
4593 	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4594 }
4595 
4596 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4597 			   uint32_t thread, uint32_t regno,
4598 			   uint32_t num, uint32_t *out)
4599 {
4600 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4601 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4602 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
4603 		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4604 		(SQ_IND_INDEX__AUTO_INCR_MASK));
4605 	while (num--)
4606 		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4607 }
4608 
4609 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4610 {
4611 	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4612 	 * field when performing a select_se_sh so it should be
4613 	 * zero here */
4614 	WARN_ON(simd != 0);
4615 
4616 	/* type 2 wave data */
4617 	dst[(*no_fields)++] = 2;
4618 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4619 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4620 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4621 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4622 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4623 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4624 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4625 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4626 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4627 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4628 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4629 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4630 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4631 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4632 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4633 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4634 }
4635 
4636 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4637 				     uint32_t wave, uint32_t start,
4638 				     uint32_t size, uint32_t *dst)
4639 {
4640 	WARN_ON(simd != 0);
4641 
4642 	wave_read_regs(
4643 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4644 		dst);
4645 }
4646 
4647 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4648 				      uint32_t wave, uint32_t thread,
4649 				      uint32_t start, uint32_t size,
4650 				      uint32_t *dst)
4651 {
4652 	wave_read_regs(
4653 		adev, wave, thread,
4654 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4655 }
4656 
4657 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4658 				       u32 me, u32 pipe, u32 q, u32 vm)
4659 {
4660 	nv_grbm_select(adev, me, pipe, q, vm);
4661 }
4662 
4663 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4664 					  bool enable)
4665 {
4666 	uint32_t data, def;
4667 
4668 	data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4669 
4670 	if (enable)
4671 		data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4672 	else
4673 		data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4674 
4675 	if (data != def)
4676 		WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4677 }
4678 
4679 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4680 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4681 	.select_se_sh = &gfx_v10_0_select_se_sh,
4682 	.read_wave_data = &gfx_v10_0_read_wave_data,
4683 	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4684 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4685 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4686 	.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4687 	.update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4688 };
4689 
4690 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4691 {
4692 	u32 gb_addr_config;
4693 
4694 	adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4695 
4696 	switch (adev->ip_versions[GC_HWIP][0]) {
4697 	case IP_VERSION(10, 1, 10):
4698 	case IP_VERSION(10, 1, 1):
4699 	case IP_VERSION(10, 1, 2):
4700 		adev->gfx.config.max_hw_contexts = 8;
4701 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4702 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4703 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4704 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4705 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4706 		break;
4707 	case IP_VERSION(10, 3, 0):
4708 	case IP_VERSION(10, 3, 2):
4709 	case IP_VERSION(10, 3, 1):
4710 	case IP_VERSION(10, 3, 4):
4711 	case IP_VERSION(10, 3, 5):
4712 	case IP_VERSION(10, 3, 6):
4713 	case IP_VERSION(10, 3, 3):
4714 	case IP_VERSION(10, 3, 7):
4715 		adev->gfx.config.max_hw_contexts = 8;
4716 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4717 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4718 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4719 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4720 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4721 		adev->gfx.config.gb_addr_config_fields.num_pkrs =
4722 			1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4723 		break;
4724 	case IP_VERSION(10, 1, 3):
4725 	case IP_VERSION(10, 1, 4):
4726 		adev->gfx.config.max_hw_contexts = 8;
4727 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4728 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4729 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4730 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4731 		gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4732 		break;
4733 	default:
4734 		BUG();
4735 		break;
4736 	}
4737 
4738 	adev->gfx.config.gb_addr_config = gb_addr_config;
4739 
4740 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4741 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4742 				      GB_ADDR_CONFIG, NUM_PIPES);
4743 
4744 	adev->gfx.config.max_tile_pipes =
4745 		adev->gfx.config.gb_addr_config_fields.num_pipes;
4746 
4747 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4748 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4749 				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4750 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4751 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4752 				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
4753 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4754 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4755 				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4756 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4757 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4758 				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4759 }
4760 
4761 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4762 				   int me, int pipe, int queue)
4763 {
4764 	struct amdgpu_ring *ring;
4765 	unsigned int irq_type;
4766 	unsigned int hw_prio;
4767 
4768 	ring = &adev->gfx.gfx_ring[ring_id];
4769 
4770 	ring->me = me;
4771 	ring->pipe = pipe;
4772 	ring->queue = queue;
4773 
4774 	ring->ring_obj = NULL;
4775 	ring->use_doorbell = true;
4776 
4777 	if (!ring_id)
4778 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4779 	else
4780 		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4781 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4782 
4783 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4784 	hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4785 			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4786 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4787 				hw_prio, NULL);
4788 }
4789 
4790 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4791 				       int mec, int pipe, int queue)
4792 {
4793 	unsigned irq_type;
4794 	struct amdgpu_ring *ring;
4795 	unsigned int hw_prio;
4796 
4797 	ring = &adev->gfx.compute_ring[ring_id];
4798 
4799 	/* mec0 is me1 */
4800 	ring->me = mec + 1;
4801 	ring->pipe = pipe;
4802 	ring->queue = queue;
4803 
4804 	ring->ring_obj = NULL;
4805 	ring->use_doorbell = true;
4806 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4807 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4808 				+ (ring_id * GFX10_MEC_HPD_SIZE);
4809 	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4810 
4811 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4812 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4813 		+ ring->pipe;
4814 	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4815 			AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4816 	/* type-2 packets are deprecated on MEC, use type-3 instead */
4817 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4818 			     hw_prio, NULL);
4819 }
4820 
4821 static int gfx_v10_0_sw_init(void *handle)
4822 {
4823 	int i, j, k, r, ring_id = 0;
4824 	struct amdgpu_kiq *kiq;
4825 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4826 
4827 	switch (adev->ip_versions[GC_HWIP][0]) {
4828 	case IP_VERSION(10, 1, 10):
4829 	case IP_VERSION(10, 1, 1):
4830 	case IP_VERSION(10, 1, 2):
4831 	case IP_VERSION(10, 1, 3):
4832 	case IP_VERSION(10, 1, 4):
4833 		adev->gfx.me.num_me = 1;
4834 		adev->gfx.me.num_pipe_per_me = 1;
4835 		adev->gfx.me.num_queue_per_pipe = 1;
4836 		adev->gfx.mec.num_mec = 2;
4837 		adev->gfx.mec.num_pipe_per_mec = 4;
4838 		adev->gfx.mec.num_queue_per_pipe = 8;
4839 		break;
4840 	case IP_VERSION(10, 3, 0):
4841 	case IP_VERSION(10, 3, 2):
4842 	case IP_VERSION(10, 3, 1):
4843 	case IP_VERSION(10, 3, 4):
4844 	case IP_VERSION(10, 3, 5):
4845 	case IP_VERSION(10, 3, 6):
4846 	case IP_VERSION(10, 3, 3):
4847 	case IP_VERSION(10, 3, 7):
4848 		adev->gfx.me.num_me = 1;
4849 		adev->gfx.me.num_pipe_per_me = 1;
4850 		adev->gfx.me.num_queue_per_pipe = 1;
4851 		adev->gfx.mec.num_mec = 2;
4852 		adev->gfx.mec.num_pipe_per_mec = 4;
4853 		adev->gfx.mec.num_queue_per_pipe = 4;
4854 		break;
4855 	default:
4856 		adev->gfx.me.num_me = 1;
4857 		adev->gfx.me.num_pipe_per_me = 1;
4858 		adev->gfx.me.num_queue_per_pipe = 1;
4859 		adev->gfx.mec.num_mec = 1;
4860 		adev->gfx.mec.num_pipe_per_mec = 4;
4861 		adev->gfx.mec.num_queue_per_pipe = 8;
4862 		break;
4863 	}
4864 
4865 	/* KIQ event */
4866 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4867 			      GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4868 			      &adev->gfx.kiq.irq);
4869 	if (r)
4870 		return r;
4871 
4872 	/* EOP Event */
4873 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4874 			      GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4875 			      &adev->gfx.eop_irq);
4876 	if (r)
4877 		return r;
4878 
4879 	/* Privileged reg */
4880 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4881 			      &adev->gfx.priv_reg_irq);
4882 	if (r)
4883 		return r;
4884 
4885 	/* Privileged inst */
4886 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4887 			      &adev->gfx.priv_inst_irq);
4888 	if (r)
4889 		return r;
4890 
4891 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4892 
4893 	r = gfx_v10_0_me_init(adev);
4894 	if (r)
4895 		return r;
4896 
4897 	if (adev->gfx.rlc.funcs) {
4898 		if (adev->gfx.rlc.funcs->init) {
4899 			r = adev->gfx.rlc.funcs->init(adev);
4900 			if (r) {
4901 				dev_err(adev->dev, "Failed to init rlc BOs!\n");
4902 				return r;
4903 			}
4904 		}
4905 	}
4906 
4907 	r = gfx_v10_0_mec_init(adev);
4908 	if (r) {
4909 		DRM_ERROR("Failed to init MEC BOs!\n");
4910 		return r;
4911 	}
4912 
4913 	/* set up the gfx ring */
4914 	for (i = 0; i < adev->gfx.me.num_me; i++) {
4915 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4916 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4917 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4918 					continue;
4919 
4920 				r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4921 							    i, k, j);
4922 				if (r)
4923 					return r;
4924 				ring_id++;
4925 			}
4926 		}
4927 	}
4928 
4929 	ring_id = 0;
4930 	/* set up the compute queues - allocate horizontally across pipes */
4931 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4932 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4933 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4934 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4935 								     j))
4936 					continue;
4937 
4938 				r = gfx_v10_0_compute_ring_init(adev, ring_id,
4939 								i, k, j);
4940 				if (r)
4941 					return r;
4942 
4943 				ring_id++;
4944 			}
4945 		}
4946 	}
4947 
4948 	if (!adev->enable_mes_kiq) {
4949 		r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4950 		if (r) {
4951 			DRM_ERROR("Failed to init KIQ BOs!\n");
4952 			return r;
4953 		}
4954 
4955 		kiq = &adev->gfx.kiq;
4956 		r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4957 		if (r)
4958 			return r;
4959 	}
4960 
4961 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4962 	if (r)
4963 		return r;
4964 
4965 	/* allocate visible FB for rlc auto-loading fw */
4966 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4967 		r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4968 		if (r)
4969 			return r;
4970 	}
4971 
4972 	adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4973 
4974 	gfx_v10_0_gpu_early_init(adev);
4975 
4976 	return 0;
4977 }
4978 
4979 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4980 {
4981 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4982 			      &adev->gfx.pfp.pfp_fw_gpu_addr,
4983 			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
4984 }
4985 
4986 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4987 {
4988 	amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4989 			      &adev->gfx.ce.ce_fw_gpu_addr,
4990 			      (void **)&adev->gfx.ce.ce_fw_ptr);
4991 }
4992 
4993 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4994 {
4995 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4996 			      &adev->gfx.me.me_fw_gpu_addr,
4997 			      (void **)&adev->gfx.me.me_fw_ptr);
4998 }
4999 
5000 static int gfx_v10_0_sw_fini(void *handle)
5001 {
5002 	int i;
5003 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5004 
5005 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5006 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
5007 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
5008 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
5009 
5010 	amdgpu_gfx_mqd_sw_fini(adev);
5011 
5012 	if (!adev->enable_mes_kiq) {
5013 		amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
5014 		amdgpu_gfx_kiq_fini(adev);
5015 	}
5016 
5017 	gfx_v10_0_pfp_fini(adev);
5018 	gfx_v10_0_ce_fini(adev);
5019 	gfx_v10_0_me_fini(adev);
5020 	gfx_v10_0_rlc_fini(adev);
5021 	gfx_v10_0_mec_fini(adev);
5022 
5023 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
5024 		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
5025 
5026 	gfx_v10_0_free_microcode(adev);
5027 
5028 	return 0;
5029 }
5030 
5031 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
5032 				   u32 sh_num, u32 instance)
5033 {
5034 	u32 data;
5035 
5036 	if (instance == 0xffffffff)
5037 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
5038 				     INSTANCE_BROADCAST_WRITES, 1);
5039 	else
5040 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
5041 				     instance);
5042 
5043 	if (se_num == 0xffffffff)
5044 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
5045 				     1);
5046 	else
5047 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
5048 
5049 	if (sh_num == 0xffffffff)
5050 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
5051 				     1);
5052 	else
5053 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
5054 
5055 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
5056 }
5057 
5058 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
5059 {
5060 	u32 data, mask;
5061 
5062 	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
5063 	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
5064 
5065 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
5066 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
5067 
5068 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
5069 					 adev->gfx.config.max_sh_per_se);
5070 
5071 	return (~data) & mask;
5072 }
5073 
5074 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5075 {
5076 	int i, j;
5077 	u32 data;
5078 	u32 active_rbs = 0;
5079 	u32 bitmap;
5080 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5081 					adev->gfx.config.max_sh_per_se;
5082 
5083 	mutex_lock(&adev->grbm_idx_mutex);
5084 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5085 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5086 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
5087 			if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
5088 				(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
5089 				(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
5090 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5091 				continue;
5092 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5093 			data = gfx_v10_0_get_rb_active_bitmap(adev);
5094 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5095 					       rb_bitmap_width_per_sh);
5096 		}
5097 	}
5098 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5099 	mutex_unlock(&adev->grbm_idx_mutex);
5100 
5101 	adev->gfx.config.backend_enable_mask = active_rbs;
5102 	adev->gfx.config.num_rbs = hweight32(active_rbs);
5103 }
5104 
5105 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5106 {
5107 	uint32_t num_sc;
5108 	uint32_t enabled_rb_per_sh;
5109 	uint32_t active_rb_bitmap;
5110 	uint32_t num_rb_per_sc;
5111 	uint32_t num_packer_per_sc;
5112 	uint32_t pa_sc_tile_steering_override;
5113 
5114 	/* for ASICs that integrates GFX v10.3
5115 	 * pa_sc_tile_steering_override should be set to 0 */
5116 	if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
5117 		return 0;
5118 
5119 	/* init num_sc */
5120 	num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5121 			adev->gfx.config.num_sc_per_sh;
5122 	/* init num_rb_per_sc */
5123 	active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5124 	enabled_rb_per_sh = hweight32(active_rb_bitmap);
5125 	num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5126 	/* init num_packer_per_sc */
5127 	num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5128 
5129 	pa_sc_tile_steering_override = 0;
5130 	pa_sc_tile_steering_override |=
5131 		(order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5132 		PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5133 	pa_sc_tile_steering_override |=
5134 		(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5135 		PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5136 	pa_sc_tile_steering_override |=
5137 		(order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5138 		PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5139 
5140 	return pa_sc_tile_steering_override;
5141 }
5142 
5143 #define DEFAULT_SH_MEM_BASES	(0x6000)
5144 
5145 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5146 {
5147 	int i;
5148 	uint32_t sh_mem_bases;
5149 
5150 	/*
5151 	 * Configure apertures:
5152 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5153 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5154 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5155 	 */
5156 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5157 
5158 	mutex_lock(&adev->srbm_mutex);
5159 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5160 		nv_grbm_select(adev, 0, 0, 0, i);
5161 		/* CP and shaders */
5162 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5163 		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5164 	}
5165 	nv_grbm_select(adev, 0, 0, 0, 0);
5166 	mutex_unlock(&adev->srbm_mutex);
5167 
5168 	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
5169 	   access. These should be enabled by FW for target VMIDs. */
5170 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5171 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5172 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5173 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5174 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5175 	}
5176 }
5177 
5178 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5179 {
5180 	int vmid;
5181 
5182 	/*
5183 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5184 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
5185 	 * the driver can enable them for graphics. VMID0 should maintain
5186 	 * access so that HWS firmware can save/restore entries.
5187 	 */
5188 	for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5189 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5190 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5191 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5192 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5193 	}
5194 }
5195 
5196 
5197 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5198 {
5199 	int i, j, k;
5200 	int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5201 	u32 tmp, wgp_active_bitmap = 0;
5202 	u32 gcrd_targets_disable_tcp = 0;
5203 	u32 utcl_invreq_disable = 0;
5204 	/*
5205 	 * GCRD_TARGETS_DISABLE field contains
5206 	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5207 	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5208 	 */
5209 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5210 		2 * max_wgp_per_sh + /* TCP */
5211 		max_wgp_per_sh + /* SQC */
5212 		4); /* GL1C */
5213 	/*
5214 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
5215 	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5216 	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5217 	 */
5218 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5219 		2 * max_wgp_per_sh + /* TCP */
5220 		2 * max_wgp_per_sh + /* SQC */
5221 		4 + /* RMI */
5222 		1); /* SQG */
5223 
5224 	mutex_lock(&adev->grbm_idx_mutex);
5225 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5226 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5227 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5228 			wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5229 			/*
5230 			 * Set corresponding TCP bits for the inactive WGPs in
5231 			 * GCRD_SA_TARGETS_DISABLE
5232 			 */
5233 			gcrd_targets_disable_tcp = 0;
5234 			/* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5235 			utcl_invreq_disable = 0;
5236 
5237 			for (k = 0; k < max_wgp_per_sh; k++) {
5238 				if (!(wgp_active_bitmap & (1 << k))) {
5239 					gcrd_targets_disable_tcp |= 3 << (2 * k);
5240 					gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5241 					utcl_invreq_disable |= (3 << (2 * k)) |
5242 						(3 << (2 * (max_wgp_per_sh + k)));
5243 				}
5244 			}
5245 
5246 			tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5247 			/* only override TCP & SQC bits */
5248 			tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5249 			tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5250 			WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5251 
5252 			tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5253 			/* only override TCP & SQC bits */
5254 			tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5255 			tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5256 			WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5257 		}
5258 	}
5259 
5260 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5261 	mutex_unlock(&adev->grbm_idx_mutex);
5262 }
5263 
5264 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5265 {
5266 	/* TCCs are global (not instanced). */
5267 	uint32_t tcc_disable;
5268 
5269 	if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
5270 		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5271 			      RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5272 	} else {
5273 		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5274 			      RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5275 	}
5276 
5277 	adev->gfx.config.tcc_disabled_mask =
5278 		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5279 		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5280 }
5281 
5282 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5283 {
5284 	u32 tmp;
5285 	int i;
5286 
5287 	WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5288 
5289 	gfx_v10_0_setup_rb(adev);
5290 	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5291 	gfx_v10_0_get_tcc_info(adev);
5292 	adev->gfx.config.pa_sc_tile_steering_override =
5293 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5294 
5295 	/* XXX SH_MEM regs */
5296 	/* where to put LDS, scratch, GPUVM in FSA64 space */
5297 	mutex_lock(&adev->srbm_mutex);
5298 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5299 		nv_grbm_select(adev, 0, 0, 0, i);
5300 		/* CP and shaders */
5301 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5302 		if (i != 0) {
5303 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5304 				(adev->gmc.private_aperture_start >> 48));
5305 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5306 				(adev->gmc.shared_aperture_start >> 48));
5307 			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5308 		}
5309 	}
5310 	nv_grbm_select(adev, 0, 0, 0, 0);
5311 
5312 	mutex_unlock(&adev->srbm_mutex);
5313 
5314 	gfx_v10_0_init_compute_vmid(adev);
5315 	gfx_v10_0_init_gds_vmid(adev);
5316 
5317 }
5318 
5319 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5320 					       bool enable)
5321 {
5322 	u32 tmp;
5323 
5324 	if (amdgpu_sriov_vf(adev))
5325 		return;
5326 
5327 	tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5328 
5329 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5330 			    enable ? 1 : 0);
5331 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5332 			    enable ? 1 : 0);
5333 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5334 			    enable ? 1 : 0);
5335 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5336 			    enable ? 1 : 0);
5337 
5338 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5339 }
5340 
5341 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5342 {
5343 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5344 
5345 	/* csib */
5346 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5347 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5348 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
5349 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5350 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5351 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5352 	} else {
5353 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5354 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
5355 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5356 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5357 		WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5358 	}
5359 	return 0;
5360 }
5361 
5362 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5363 {
5364 	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5365 
5366 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5367 	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5368 }
5369 
5370 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5371 {
5372 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5373 	udelay(50);
5374 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5375 	udelay(50);
5376 }
5377 
5378 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5379 					     bool enable)
5380 {
5381 	uint32_t rlc_pg_cntl;
5382 
5383 	rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5384 
5385 	if (!enable) {
5386 		/* RLC_PG_CNTL[23] = 0 (default)
5387 		 * RLC will wait for handshake acks with SMU
5388 		 * GFXOFF will be enabled
5389 		 * RLC_PG_CNTL[23] = 1
5390 		 * RLC will not issue any message to SMU
5391 		 * hence no handshake between SMU & RLC
5392 		 * GFXOFF will be disabled
5393 		 */
5394 		rlc_pg_cntl |= 0x800000;
5395 	} else
5396 		rlc_pg_cntl &= ~0x800000;
5397 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5398 }
5399 
5400 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5401 {
5402 	/* TODO: enable rlc & smu handshake until smu
5403 	 * and gfxoff feature works as expected */
5404 	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5405 		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5406 
5407 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5408 	udelay(50);
5409 }
5410 
5411 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5412 {
5413 	uint32_t tmp;
5414 
5415 	/* enable Save Restore Machine */
5416 	tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5417 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5418 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5419 	WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5420 }
5421 
5422 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5423 {
5424 	const struct rlc_firmware_header_v2_0 *hdr;
5425 	const __le32 *fw_data;
5426 	unsigned i, fw_size;
5427 
5428 	if (!adev->gfx.rlc_fw)
5429 		return -EINVAL;
5430 
5431 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5432 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
5433 
5434 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5435 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5436 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5437 
5438 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5439 		     RLCG_UCODE_LOADING_START_ADDRESS);
5440 
5441 	for (i = 0; i < fw_size; i++)
5442 		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5443 			     le32_to_cpup(fw_data++));
5444 
5445 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5446 
5447 	return 0;
5448 }
5449 
5450 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5451 {
5452 	int r;
5453 
5454 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5455 		adev->psp.autoload_supported) {
5456 
5457 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5458 		if (r)
5459 			return r;
5460 
5461 		gfx_v10_0_init_csb(adev);
5462 
5463 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5464 			gfx_v10_0_rlc_enable_srm(adev);
5465 	} else {
5466 		if (amdgpu_sriov_vf(adev)) {
5467 			gfx_v10_0_init_csb(adev);
5468 			return 0;
5469 		}
5470 
5471 		adev->gfx.rlc.funcs->stop(adev);
5472 
5473 		/* disable CG */
5474 		WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5475 
5476 		/* disable PG */
5477 		WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5478 
5479 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5480 			/* legacy rlc firmware loading */
5481 			r = gfx_v10_0_rlc_load_microcode(adev);
5482 			if (r)
5483 				return r;
5484 		} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5485 			/* rlc backdoor autoload firmware */
5486 			r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5487 			if (r)
5488 				return r;
5489 		}
5490 
5491 		gfx_v10_0_init_csb(adev);
5492 
5493 		adev->gfx.rlc.funcs->start(adev);
5494 
5495 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5496 			r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5497 			if (r)
5498 				return r;
5499 		}
5500 	}
5501 	return 0;
5502 }
5503 
5504 static struct {
5505 	FIRMWARE_ID	id;
5506 	unsigned int	offset;
5507 	unsigned int	size;
5508 } rlc_autoload_info[FIRMWARE_ID_MAX];
5509 
5510 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5511 {
5512 	int ret;
5513 	RLC_TABLE_OF_CONTENT *rlc_toc;
5514 
5515 	ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5516 					AMDGPU_GEM_DOMAIN_GTT,
5517 					&adev->gfx.rlc.rlc_toc_bo,
5518 					&adev->gfx.rlc.rlc_toc_gpu_addr,
5519 					(void **)&adev->gfx.rlc.rlc_toc_buf);
5520 	if (ret) {
5521 		dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5522 		return ret;
5523 	}
5524 
5525 	/* Copy toc from psp sos fw to rlc toc buffer */
5526 	memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5527 
5528 	rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5529 	while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5530 		(rlc_toc->id < FIRMWARE_ID_MAX)) {
5531 		if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5532 		    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5533 			/* Offset needs 4KB alignment */
5534 			rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5535 		}
5536 
5537 		rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5538 		rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5539 		rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5540 
5541 		rlc_toc++;
5542 	}
5543 
5544 	return 0;
5545 }
5546 
5547 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5548 {
5549 	uint32_t total_size = 0;
5550 	FIRMWARE_ID id;
5551 	int ret;
5552 
5553 	ret = gfx_v10_0_parse_rlc_toc(adev);
5554 	if (ret) {
5555 		dev_err(adev->dev, "failed to parse rlc toc\n");
5556 		return 0;
5557 	}
5558 
5559 	for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5560 		total_size += rlc_autoload_info[id].size;
5561 
5562 	/* In case the offset in rlc toc ucode is aligned */
5563 	if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5564 		total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5565 				rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5566 
5567 	return total_size;
5568 }
5569 
5570 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5571 {
5572 	int r;
5573 	uint32_t total_size;
5574 
5575 	total_size = gfx_v10_0_calc_toc_total_size(adev);
5576 
5577 	r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5578 				      AMDGPU_GEM_DOMAIN_GTT,
5579 				      &adev->gfx.rlc.rlc_autoload_bo,
5580 				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5581 				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5582 	if (r) {
5583 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5584 		return r;
5585 	}
5586 
5587 	return 0;
5588 }
5589 
5590 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5591 {
5592 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5593 			      &adev->gfx.rlc.rlc_toc_gpu_addr,
5594 			      (void **)&adev->gfx.rlc.rlc_toc_buf);
5595 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5596 			      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5597 			      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5598 }
5599 
5600 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5601 						       FIRMWARE_ID id,
5602 						       const void *fw_data,
5603 						       uint32_t fw_size)
5604 {
5605 	uint32_t toc_offset;
5606 	uint32_t toc_fw_size;
5607 	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5608 
5609 	if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5610 		return;
5611 
5612 	toc_offset = rlc_autoload_info[id].offset;
5613 	toc_fw_size = rlc_autoload_info[id].size;
5614 
5615 	if (fw_size == 0)
5616 		fw_size = toc_fw_size;
5617 
5618 	if (fw_size > toc_fw_size)
5619 		fw_size = toc_fw_size;
5620 
5621 	memcpy(ptr + toc_offset, fw_data, fw_size);
5622 
5623 	if (fw_size < toc_fw_size)
5624 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5625 }
5626 
5627 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5628 {
5629 	void *data;
5630 	uint32_t size;
5631 
5632 	data = adev->gfx.rlc.rlc_toc_buf;
5633 	size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5634 
5635 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5636 						   FIRMWARE_ID_RLC_TOC,
5637 						   data, size);
5638 }
5639 
5640 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5641 {
5642 	const __le32 *fw_data;
5643 	uint32_t fw_size;
5644 	const struct gfx_firmware_header_v1_0 *cp_hdr;
5645 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
5646 
5647 	/* pfp ucode */
5648 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5649 		adev->gfx.pfp_fw->data;
5650 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5651 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5652 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5653 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5654 						   FIRMWARE_ID_CP_PFP,
5655 						   fw_data, fw_size);
5656 
5657 	/* ce ucode */
5658 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5659 		adev->gfx.ce_fw->data;
5660 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5661 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5662 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5663 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5664 						   FIRMWARE_ID_CP_CE,
5665 						   fw_data, fw_size);
5666 
5667 	/* me ucode */
5668 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5669 		adev->gfx.me_fw->data;
5670 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5671 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5672 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5673 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5674 						   FIRMWARE_ID_CP_ME,
5675 						   fw_data, fw_size);
5676 
5677 	/* rlc ucode */
5678 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5679 		adev->gfx.rlc_fw->data;
5680 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5681 		le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5682 	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5683 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5684 						   FIRMWARE_ID_RLC_G_UCODE,
5685 						   fw_data, fw_size);
5686 
5687 	/* mec1 ucode */
5688 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5689 		adev->gfx.mec_fw->data;
5690 	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5691 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5692 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5693 		cp_hdr->jt_size * 4;
5694 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5695 						   FIRMWARE_ID_CP_MEC,
5696 						   fw_data, fw_size);
5697 	/* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5698 }
5699 
5700 /* Temporarily put sdma part here */
5701 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5702 {
5703 	const __le32 *fw_data;
5704 	uint32_t fw_size;
5705 	const struct sdma_firmware_header_v1_0 *sdma_hdr;
5706 	int i;
5707 
5708 	for (i = 0; i < adev->sdma.num_instances; i++) {
5709 		sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5710 			adev->sdma.instance[i].fw->data;
5711 		fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5712 			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5713 		fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5714 
5715 		if (i == 0) {
5716 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5717 				FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5718 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5719 				FIRMWARE_ID_SDMA0_JT,
5720 				(uint32_t *)fw_data +
5721 				sdma_hdr->jt_offset,
5722 				sdma_hdr->jt_size * 4);
5723 		} else if (i == 1) {
5724 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5725 				FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5726 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5727 				FIRMWARE_ID_SDMA1_JT,
5728 				(uint32_t *)fw_data +
5729 				sdma_hdr->jt_offset,
5730 				sdma_hdr->jt_size * 4);
5731 		}
5732 	}
5733 }
5734 
5735 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5736 {
5737 	uint32_t rlc_g_offset, rlc_g_size, tmp;
5738 	uint64_t gpu_addr;
5739 
5740 	gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5741 	gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5742 	gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5743 
5744 	rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5745 	rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5746 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5747 
5748 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5749 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5750 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5751 
5752 	tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5753 	if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5754 		   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5755 		DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5756 		return -EINVAL;
5757 	}
5758 
5759 	tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5760 	if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5761 		DRM_ERROR("RLC ROM should halt itself\n");
5762 		return -EINVAL;
5763 	}
5764 
5765 	return 0;
5766 }
5767 
5768 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5769 {
5770 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5771 	uint32_t tmp;
5772 	int i;
5773 	uint64_t addr;
5774 
5775 	/* Trigger an invalidation of the L1 instruction caches */
5776 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5777 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5778 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5779 
5780 	/* Wait for invalidation complete */
5781 	for (i = 0; i < usec_timeout; i++) {
5782 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5783 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5784 			INVALIDATE_CACHE_COMPLETE))
5785 			break;
5786 		udelay(1);
5787 	}
5788 
5789 	if (i >= usec_timeout) {
5790 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5791 		return -EINVAL;
5792 	}
5793 
5794 	/* Program me ucode address into intruction cache address register */
5795 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5796 		rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5797 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5798 			lower_32_bits(addr) & 0xFFFFF000);
5799 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5800 			upper_32_bits(addr));
5801 
5802 	return 0;
5803 }
5804 
5805 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5806 {
5807 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5808 	uint32_t tmp;
5809 	int i;
5810 	uint64_t addr;
5811 
5812 	/* Trigger an invalidation of the L1 instruction caches */
5813 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5814 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5815 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5816 
5817 	/* Wait for invalidation complete */
5818 	for (i = 0; i < usec_timeout; i++) {
5819 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5820 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5821 			INVALIDATE_CACHE_COMPLETE))
5822 			break;
5823 		udelay(1);
5824 	}
5825 
5826 	if (i >= usec_timeout) {
5827 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5828 		return -EINVAL;
5829 	}
5830 
5831 	/* Program ce ucode address into intruction cache address register */
5832 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5833 		rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5834 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5835 			lower_32_bits(addr) & 0xFFFFF000);
5836 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5837 			upper_32_bits(addr));
5838 
5839 	return 0;
5840 }
5841 
5842 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5843 {
5844 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5845 	uint32_t tmp;
5846 	int i;
5847 	uint64_t addr;
5848 
5849 	/* Trigger an invalidation of the L1 instruction caches */
5850 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5851 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5852 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5853 
5854 	/* Wait for invalidation complete */
5855 	for (i = 0; i < usec_timeout; i++) {
5856 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5857 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5858 			INVALIDATE_CACHE_COMPLETE))
5859 			break;
5860 		udelay(1);
5861 	}
5862 
5863 	if (i >= usec_timeout) {
5864 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5865 		return -EINVAL;
5866 	}
5867 
5868 	/* Program pfp ucode address into intruction cache address register */
5869 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5870 		rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5871 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5872 			lower_32_bits(addr) & 0xFFFFF000);
5873 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5874 			upper_32_bits(addr));
5875 
5876 	return 0;
5877 }
5878 
5879 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5880 {
5881 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5882 	uint32_t tmp;
5883 	int i;
5884 	uint64_t addr;
5885 
5886 	/* Trigger an invalidation of the L1 instruction caches */
5887 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5888 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5889 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5890 
5891 	/* Wait for invalidation complete */
5892 	for (i = 0; i < usec_timeout; i++) {
5893 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5894 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5895 			INVALIDATE_CACHE_COMPLETE))
5896 			break;
5897 		udelay(1);
5898 	}
5899 
5900 	if (i >= usec_timeout) {
5901 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5902 		return -EINVAL;
5903 	}
5904 
5905 	/* Program mec1 ucode address into intruction cache address register */
5906 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5907 		rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5908 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5909 			lower_32_bits(addr) & 0xFFFFF000);
5910 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5911 			upper_32_bits(addr));
5912 
5913 	return 0;
5914 }
5915 
5916 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5917 {
5918 	uint32_t cp_status;
5919 	uint32_t bootload_status;
5920 	int i, r;
5921 
5922 	for (i = 0; i < adev->usec_timeout; i++) {
5923 		cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5924 		bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5925 		if ((cp_status == 0) &&
5926 		    (REG_GET_FIELD(bootload_status,
5927 			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5928 			break;
5929 		}
5930 		udelay(1);
5931 	}
5932 
5933 	if (i >= adev->usec_timeout) {
5934 		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5935 		return -ETIMEDOUT;
5936 	}
5937 
5938 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5939 		r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5940 		if (r)
5941 			return r;
5942 
5943 		r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5944 		if (r)
5945 			return r;
5946 
5947 		r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5948 		if (r)
5949 			return r;
5950 
5951 		r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5952 		if (r)
5953 			return r;
5954 	}
5955 
5956 	return 0;
5957 }
5958 
5959 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5960 {
5961 	int i;
5962 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5963 
5964 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5965 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5966 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5967 
5968 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5969 		WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5970 	} else {
5971 		WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5972 	}
5973 
5974 	for (i = 0; i < adev->usec_timeout; i++) {
5975 		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5976 			break;
5977 		udelay(1);
5978 	}
5979 
5980 	if (i >= adev->usec_timeout)
5981 		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5982 
5983 	return 0;
5984 }
5985 
5986 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5987 {
5988 	int r;
5989 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
5990 	const __le32 *fw_data;
5991 	unsigned i, fw_size;
5992 	uint32_t tmp;
5993 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5994 
5995 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5996 		adev->gfx.pfp_fw->data;
5997 
5998 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5999 
6000 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
6001 		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
6002 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
6003 
6004 	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
6005 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6006 				      &adev->gfx.pfp.pfp_fw_obj,
6007 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
6008 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
6009 	if (r) {
6010 		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
6011 		gfx_v10_0_pfp_fini(adev);
6012 		return r;
6013 	}
6014 
6015 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
6016 
6017 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
6018 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
6019 
6020 	/* Trigger an invalidation of the L1 instruction caches */
6021 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6022 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6023 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
6024 
6025 	/* Wait for invalidation complete */
6026 	for (i = 0; i < usec_timeout; i++) {
6027 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6028 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
6029 			INVALIDATE_CACHE_COMPLETE))
6030 			break;
6031 		udelay(1);
6032 	}
6033 
6034 	if (i >= usec_timeout) {
6035 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6036 		return -EINVAL;
6037 	}
6038 
6039 	if (amdgpu_emu_mode == 1)
6040 		adev->hdp.funcs->flush_hdp(adev, NULL);
6041 
6042 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
6043 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
6044 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
6045 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
6046 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6047 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
6048 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
6049 		adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
6050 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6051 		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6052 
6053 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6054 
6055 	for (i = 0; i < pfp_hdr->jt_size; i++)
6056 		WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6057 			     le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6058 
6059 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6060 
6061 	return 0;
6062 }
6063 
6064 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6065 {
6066 	int r;
6067 	const struct gfx_firmware_header_v1_0 *ce_hdr;
6068 	const __le32 *fw_data;
6069 	unsigned i, fw_size;
6070 	uint32_t tmp;
6071 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
6072 
6073 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6074 		adev->gfx.ce_fw->data;
6075 
6076 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6077 
6078 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6079 		le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6080 	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6081 
6082 	r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6083 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6084 				      &adev->gfx.ce.ce_fw_obj,
6085 				      &adev->gfx.ce.ce_fw_gpu_addr,
6086 				      (void **)&adev->gfx.ce.ce_fw_ptr);
6087 	if (r) {
6088 		dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6089 		gfx_v10_0_ce_fini(adev);
6090 		return r;
6091 	}
6092 
6093 	memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6094 
6095 	amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6096 	amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6097 
6098 	/* Trigger an invalidation of the L1 instruction caches */
6099 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6100 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6101 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6102 
6103 	/* Wait for invalidation complete */
6104 	for (i = 0; i < usec_timeout; i++) {
6105 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6106 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6107 			INVALIDATE_CACHE_COMPLETE))
6108 			break;
6109 		udelay(1);
6110 	}
6111 
6112 	if (i >= usec_timeout) {
6113 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6114 		return -EINVAL;
6115 	}
6116 
6117 	if (amdgpu_emu_mode == 1)
6118 		adev->hdp.funcs->flush_hdp(adev, NULL);
6119 
6120 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6121 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6122 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6123 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6124 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6125 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6126 		adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6127 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6128 		upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6129 
6130 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6131 
6132 	for (i = 0; i < ce_hdr->jt_size; i++)
6133 		WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6134 			     le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6135 
6136 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6137 
6138 	return 0;
6139 }
6140 
6141 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6142 {
6143 	int r;
6144 	const struct gfx_firmware_header_v1_0 *me_hdr;
6145 	const __le32 *fw_data;
6146 	unsigned i, fw_size;
6147 	uint32_t tmp;
6148 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
6149 
6150 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
6151 		adev->gfx.me_fw->data;
6152 
6153 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6154 
6155 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6156 		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6157 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6158 
6159 	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6160 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6161 				      &adev->gfx.me.me_fw_obj,
6162 				      &adev->gfx.me.me_fw_gpu_addr,
6163 				      (void **)&adev->gfx.me.me_fw_ptr);
6164 	if (r) {
6165 		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6166 		gfx_v10_0_me_fini(adev);
6167 		return r;
6168 	}
6169 
6170 	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6171 
6172 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6173 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6174 
6175 	/* Trigger an invalidation of the L1 instruction caches */
6176 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6177 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6178 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6179 
6180 	/* Wait for invalidation complete */
6181 	for (i = 0; i < usec_timeout; i++) {
6182 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6183 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6184 			INVALIDATE_CACHE_COMPLETE))
6185 			break;
6186 		udelay(1);
6187 	}
6188 
6189 	if (i >= usec_timeout) {
6190 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6191 		return -EINVAL;
6192 	}
6193 
6194 	if (amdgpu_emu_mode == 1)
6195 		adev->hdp.funcs->flush_hdp(adev, NULL);
6196 
6197 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6198 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6199 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6200 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6201 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6202 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6203 		adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6204 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6205 		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6206 
6207 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6208 
6209 	for (i = 0; i < me_hdr->jt_size; i++)
6210 		WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6211 			     le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6212 
6213 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6214 
6215 	return 0;
6216 }
6217 
6218 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6219 {
6220 	int r;
6221 
6222 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6223 		return -EINVAL;
6224 
6225 	gfx_v10_0_cp_gfx_enable(adev, false);
6226 
6227 	r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6228 	if (r) {
6229 		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6230 		return r;
6231 	}
6232 
6233 	r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6234 	if (r) {
6235 		dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6236 		return r;
6237 	}
6238 
6239 	r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6240 	if (r) {
6241 		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6242 		return r;
6243 	}
6244 
6245 	return 0;
6246 }
6247 
6248 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6249 {
6250 	struct amdgpu_ring *ring;
6251 	const struct cs_section_def *sect = NULL;
6252 	const struct cs_extent_def *ext = NULL;
6253 	int r, i;
6254 	int ctx_reg_offset;
6255 
6256 	/* init the CP */
6257 	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6258 		     adev->gfx.config.max_hw_contexts - 1);
6259 	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6260 
6261 	gfx_v10_0_cp_gfx_enable(adev, true);
6262 
6263 	ring = &adev->gfx.gfx_ring[0];
6264 	r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6265 	if (r) {
6266 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6267 		return r;
6268 	}
6269 
6270 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6271 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6272 
6273 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6274 	amdgpu_ring_write(ring, 0x80000000);
6275 	amdgpu_ring_write(ring, 0x80000000);
6276 
6277 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6278 		for (ext = sect->section; ext->extent != NULL; ++ext) {
6279 			if (sect->id == SECT_CONTEXT) {
6280 				amdgpu_ring_write(ring,
6281 						  PACKET3(PACKET3_SET_CONTEXT_REG,
6282 							  ext->reg_count));
6283 				amdgpu_ring_write(ring, ext->reg_index -
6284 						  PACKET3_SET_CONTEXT_REG_START);
6285 				for (i = 0; i < ext->reg_count; i++)
6286 					amdgpu_ring_write(ring, ext->extent[i]);
6287 			}
6288 		}
6289 	}
6290 
6291 	ctx_reg_offset =
6292 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6293 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6294 	amdgpu_ring_write(ring, ctx_reg_offset);
6295 	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6296 
6297 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6298 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6299 
6300 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6301 	amdgpu_ring_write(ring, 0);
6302 
6303 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6304 	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6305 	amdgpu_ring_write(ring, 0x8000);
6306 	amdgpu_ring_write(ring, 0x8000);
6307 
6308 	amdgpu_ring_commit(ring);
6309 
6310 	/* submit cs packet to copy state 0 to next available state */
6311 	if (adev->gfx.num_gfx_rings > 1) {
6312 		/* maximum supported gfx ring is 2 */
6313 		ring = &adev->gfx.gfx_ring[1];
6314 		r = amdgpu_ring_alloc(ring, 2);
6315 		if (r) {
6316 			DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6317 			return r;
6318 		}
6319 
6320 		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6321 		amdgpu_ring_write(ring, 0);
6322 
6323 		amdgpu_ring_commit(ring);
6324 	}
6325 	return 0;
6326 }
6327 
6328 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6329 					 CP_PIPE_ID pipe)
6330 {
6331 	u32 tmp;
6332 
6333 	tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6334 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6335 
6336 	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6337 }
6338 
6339 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6340 					  struct amdgpu_ring *ring)
6341 {
6342 	u32 tmp;
6343 
6344 	if (!amdgpu_async_gfx_ring) {
6345 		tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6346 		if (ring->use_doorbell) {
6347 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6348 						DOORBELL_OFFSET, ring->doorbell_index);
6349 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6350 						DOORBELL_EN, 1);
6351 		} else {
6352 			tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6353 						DOORBELL_EN, 0);
6354 		}
6355 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6356 	}
6357 	switch (adev->ip_versions[GC_HWIP][0]) {
6358 	case IP_VERSION(10, 3, 0):
6359 	case IP_VERSION(10, 3, 2):
6360 	case IP_VERSION(10, 3, 1):
6361 	case IP_VERSION(10, 3, 4):
6362 	case IP_VERSION(10, 3, 5):
6363 	case IP_VERSION(10, 3, 6):
6364 	case IP_VERSION(10, 3, 3):
6365 	case IP_VERSION(10, 3, 7):
6366 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6367 				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6368 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6369 
6370 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6371 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6372 		break;
6373 	default:
6374 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6375 				    DOORBELL_RANGE_LOWER, ring->doorbell_index);
6376 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6377 
6378 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6379 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6380 		break;
6381 	}
6382 }
6383 
6384 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6385 {
6386 	struct amdgpu_ring *ring;
6387 	u32 tmp;
6388 	u32 rb_bufsz;
6389 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
6390 	u32 i;
6391 
6392 	/* Set the write pointer delay */
6393 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6394 
6395 	/* set the RB to use vmid 0 */
6396 	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6397 
6398 	/* Init gfx ring 0 for pipe 0 */
6399 	mutex_lock(&adev->srbm_mutex);
6400 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6401 
6402 	/* Set ring buffer size */
6403 	ring = &adev->gfx.gfx_ring[0];
6404 	rb_bufsz = order_base_2(ring->ring_size / 8);
6405 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6406 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6407 #ifdef __BIG_ENDIAN
6408 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6409 #endif
6410 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6411 
6412 	/* Initialize the ring buffer's write pointers */
6413 	ring->wptr = 0;
6414 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6415 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6416 
6417 	/* set the wb address wether it's enabled or not */
6418 	rptr_addr = ring->rptr_gpu_addr;
6419 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6420 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6421 		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6422 
6423 	wptr_gpu_addr = ring->wptr_gpu_addr;
6424 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6425 		     lower_32_bits(wptr_gpu_addr));
6426 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6427 		     upper_32_bits(wptr_gpu_addr));
6428 
6429 	mdelay(1);
6430 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6431 
6432 	rb_addr = ring->gpu_addr >> 8;
6433 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6434 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6435 
6436 	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6437 
6438 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6439 	mutex_unlock(&adev->srbm_mutex);
6440 
6441 	/* Init gfx ring 1 for pipe 1 */
6442 	if (adev->gfx.num_gfx_rings > 1) {
6443 		mutex_lock(&adev->srbm_mutex);
6444 		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6445 		/* maximum supported gfx ring is 2 */
6446 		ring = &adev->gfx.gfx_ring[1];
6447 		rb_bufsz = order_base_2(ring->ring_size / 8);
6448 		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6449 		tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6450 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6451 		/* Initialize the ring buffer's write pointers */
6452 		ring->wptr = 0;
6453 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6454 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6455 		/* Set the wb address wether it's enabled or not */
6456 		rptr_addr = ring->rptr_gpu_addr;
6457 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6458 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6459 			     CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6460 		wptr_gpu_addr = ring->wptr_gpu_addr;
6461 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6462 			     lower_32_bits(wptr_gpu_addr));
6463 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6464 			     upper_32_bits(wptr_gpu_addr));
6465 
6466 		mdelay(1);
6467 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6468 
6469 		rb_addr = ring->gpu_addr >> 8;
6470 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6471 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6472 		WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6473 
6474 		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6475 		mutex_unlock(&adev->srbm_mutex);
6476 	}
6477 	/* Switch to pipe 0 */
6478 	mutex_lock(&adev->srbm_mutex);
6479 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6480 	mutex_unlock(&adev->srbm_mutex);
6481 
6482 	/* start the ring */
6483 	gfx_v10_0_cp_gfx_start(adev);
6484 
6485 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6486 		ring = &adev->gfx.gfx_ring[i];
6487 		ring->sched.ready = true;
6488 	}
6489 
6490 	return 0;
6491 }
6492 
6493 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6494 {
6495 	if (enable) {
6496 		switch (adev->ip_versions[GC_HWIP][0]) {
6497 		case IP_VERSION(10, 3, 0):
6498 		case IP_VERSION(10, 3, 2):
6499 		case IP_VERSION(10, 3, 1):
6500 		case IP_VERSION(10, 3, 4):
6501 		case IP_VERSION(10, 3, 5):
6502 		case IP_VERSION(10, 3, 6):
6503 		case IP_VERSION(10, 3, 3):
6504 		case IP_VERSION(10, 3, 7):
6505 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6506 			break;
6507 		default:
6508 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6509 			break;
6510 		}
6511 	} else {
6512 		switch (adev->ip_versions[GC_HWIP][0]) {
6513 		case IP_VERSION(10, 3, 0):
6514 		case IP_VERSION(10, 3, 2):
6515 		case IP_VERSION(10, 3, 1):
6516 		case IP_VERSION(10, 3, 4):
6517 		case IP_VERSION(10, 3, 5):
6518 		case IP_VERSION(10, 3, 6):
6519 		case IP_VERSION(10, 3, 3):
6520 		case IP_VERSION(10, 3, 7):
6521 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6522 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6523 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6524 			break;
6525 		default:
6526 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6527 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6528 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6529 			break;
6530 		}
6531 		adev->gfx.kiq.ring.sched.ready = false;
6532 	}
6533 	udelay(50);
6534 }
6535 
6536 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6537 {
6538 	const struct gfx_firmware_header_v1_0 *mec_hdr;
6539 	const __le32 *fw_data;
6540 	unsigned i;
6541 	u32 tmp;
6542 	u32 usec_timeout = 50000; /* Wait for 50 ms */
6543 
6544 	if (!adev->gfx.mec_fw)
6545 		return -EINVAL;
6546 
6547 	gfx_v10_0_cp_compute_enable(adev, false);
6548 
6549 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6550 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6551 
6552 	fw_data = (const __le32 *)
6553 		(adev->gfx.mec_fw->data +
6554 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6555 
6556 	/* Trigger an invalidation of the L1 instruction caches */
6557 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6558 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6559 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6560 
6561 	/* Wait for invalidation complete */
6562 	for (i = 0; i < usec_timeout; i++) {
6563 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6564 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6565 				       INVALIDATE_CACHE_COMPLETE))
6566 			break;
6567 		udelay(1);
6568 	}
6569 
6570 	if (i >= usec_timeout) {
6571 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6572 		return -EINVAL;
6573 	}
6574 
6575 	if (amdgpu_emu_mode == 1)
6576 		adev->hdp.funcs->flush_hdp(adev, NULL);
6577 
6578 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6579 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6580 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6581 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6582 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6583 
6584 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6585 		     0xFFFFF000);
6586 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6587 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6588 
6589 	/* MEC1 */
6590 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6591 
6592 	for (i = 0; i < mec_hdr->jt_size; i++)
6593 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6594 			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6595 
6596 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6597 
6598 	/*
6599 	 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6600 	 * different microcode than MEC1.
6601 	 */
6602 
6603 	return 0;
6604 }
6605 
6606 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6607 {
6608 	uint32_t tmp;
6609 	struct amdgpu_device *adev = ring->adev;
6610 
6611 	/* tell RLC which is KIQ queue */
6612 	switch (adev->ip_versions[GC_HWIP][0]) {
6613 	case IP_VERSION(10, 3, 0):
6614 	case IP_VERSION(10, 3, 2):
6615 	case IP_VERSION(10, 3, 1):
6616 	case IP_VERSION(10, 3, 4):
6617 	case IP_VERSION(10, 3, 5):
6618 	case IP_VERSION(10, 3, 6):
6619 	case IP_VERSION(10, 3, 3):
6620 	case IP_VERSION(10, 3, 7):
6621 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6622 		tmp &= 0xffffff00;
6623 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6624 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6625 		tmp |= 0x80;
6626 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6627 		break;
6628 	default:
6629 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6630 		tmp &= 0xffffff00;
6631 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6632 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6633 		tmp |= 0x80;
6634 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6635 		break;
6636 	}
6637 }
6638 
6639 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6640 					   struct v10_gfx_mqd *mqd,
6641 					   struct amdgpu_mqd_prop *prop)
6642 {
6643 	bool priority = 0;
6644 	u32 tmp;
6645 
6646 	/* set up default queue priority level
6647 	 * 0x0 = low priority, 0x1 = high priority
6648 	 */
6649 	if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6650 		priority = 1;
6651 
6652 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6653 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6654 	mqd->cp_gfx_hqd_queue_priority = tmp;
6655 }
6656 
6657 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6658 				  struct amdgpu_mqd_prop *prop)
6659 {
6660 	struct v10_gfx_mqd *mqd = m;
6661 	uint64_t hqd_gpu_addr, wb_gpu_addr;
6662 	uint32_t tmp;
6663 	uint32_t rb_bufsz;
6664 
6665 	/* set up gfx hqd wptr */
6666 	mqd->cp_gfx_hqd_wptr = 0;
6667 	mqd->cp_gfx_hqd_wptr_hi = 0;
6668 
6669 	/* set the pointer to the MQD */
6670 	mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6671 	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6672 
6673 	/* set up mqd control */
6674 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6675 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6676 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6677 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6678 	mqd->cp_gfx_mqd_control = tmp;
6679 
6680 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6681 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6682 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6683 	mqd->cp_gfx_hqd_vmid = 0;
6684 
6685 	/* set up gfx queue priority */
6686 	gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6687 
6688 	/* set up time quantum */
6689 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6690 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6691 	mqd->cp_gfx_hqd_quantum = tmp;
6692 
6693 	/* set up gfx hqd base. this is similar as CP_RB_BASE */
6694 	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6695 	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6696 	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6697 
6698 	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6699 	wb_gpu_addr = prop->rptr_gpu_addr;
6700 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6701 	mqd->cp_gfx_hqd_rptr_addr_hi =
6702 		upper_32_bits(wb_gpu_addr) & 0xffff;
6703 
6704 	/* set up rb_wptr_poll addr */
6705 	wb_gpu_addr = prop->wptr_gpu_addr;
6706 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6707 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6708 
6709 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6710 	rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6711 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6712 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6713 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6714 #ifdef __BIG_ENDIAN
6715 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6716 #endif
6717 	mqd->cp_gfx_hqd_cntl = tmp;
6718 
6719 	/* set up cp_doorbell_control */
6720 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6721 	if (prop->use_doorbell) {
6722 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6723 				    DOORBELL_OFFSET, prop->doorbell_index);
6724 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6725 				    DOORBELL_EN, 1);
6726 	} else
6727 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6728 				    DOORBELL_EN, 0);
6729 	mqd->cp_rb_doorbell_control = tmp;
6730 
6731 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6732 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6733 
6734 	/* active the queue */
6735 	mqd->cp_gfx_hqd_active = 1;
6736 
6737 	return 0;
6738 }
6739 
6740 #ifdef BRING_UP_DEBUG
6741 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6742 {
6743 	struct amdgpu_device *adev = ring->adev;
6744 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6745 
6746 	/* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6747 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6748 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6749 
6750 	/* set GFX_MQD_BASE */
6751 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6752 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6753 
6754 	/* set GFX_MQD_CONTROL */
6755 	WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6756 
6757 	/* set GFX_HQD_VMID to 0 */
6758 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6759 
6760 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6761 			mqd->cp_gfx_hqd_queue_priority);
6762 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6763 
6764 	/* set GFX_HQD_BASE, similar as CP_RB_BASE */
6765 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6766 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6767 
6768 	/* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6769 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6770 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6771 
6772 	/* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6773 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6774 
6775 	/* set RB_WPTR_POLL_ADDR */
6776 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6777 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6778 
6779 	/* set RB_DOORBELL_CONTROL */
6780 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6781 
6782 	/* active the queue */
6783 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6784 
6785 	return 0;
6786 }
6787 #endif
6788 
6789 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6790 {
6791 	struct amdgpu_device *adev = ring->adev;
6792 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6793 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6794 
6795 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6796 		memset((void *)mqd, 0, sizeof(*mqd));
6797 		mutex_lock(&adev->srbm_mutex);
6798 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6799 		amdgpu_ring_init_mqd(ring);
6800 
6801 		/*
6802 		 * if there are 2 gfx rings, set the lower doorbell
6803 		 * range of the first ring, otherwise the range of
6804 		 * the second ring will override the first ring
6805 		 */
6806 		if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6807 			gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6808 
6809 #ifdef BRING_UP_DEBUG
6810 		gfx_v10_0_gfx_queue_init_register(ring);
6811 #endif
6812 		nv_grbm_select(adev, 0, 0, 0, 0);
6813 		mutex_unlock(&adev->srbm_mutex);
6814 		if (adev->gfx.me.mqd_backup[mqd_idx])
6815 			memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6816 	} else if (amdgpu_in_reset(adev)) {
6817 		/* reset mqd with the backup copy */
6818 		if (adev->gfx.me.mqd_backup[mqd_idx])
6819 			memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6820 		/* reset the ring */
6821 		ring->wptr = 0;
6822 		*ring->wptr_cpu_addr = 0;
6823 		amdgpu_ring_clear_ring(ring);
6824 #ifdef BRING_UP_DEBUG
6825 		mutex_lock(&adev->srbm_mutex);
6826 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6827 		gfx_v10_0_gfx_queue_init_register(ring);
6828 		nv_grbm_select(adev, 0, 0, 0, 0);
6829 		mutex_unlock(&adev->srbm_mutex);
6830 #endif
6831 	} else {
6832 		amdgpu_ring_clear_ring(ring);
6833 	}
6834 
6835 	return 0;
6836 }
6837 
6838 #ifndef BRING_UP_DEBUG
6839 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6840 {
6841 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6842 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6843 	int r, i;
6844 
6845 	if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6846 		return -EINVAL;
6847 
6848 	r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6849 					adev->gfx.num_gfx_rings);
6850 	if (r) {
6851 		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6852 		return r;
6853 	}
6854 
6855 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6856 		kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6857 
6858 	return amdgpu_ring_test_helper(kiq_ring);
6859 }
6860 #endif
6861 
6862 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6863 {
6864 	int r, i;
6865 	struct amdgpu_ring *ring;
6866 
6867 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6868 		ring = &adev->gfx.gfx_ring[i];
6869 
6870 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
6871 		if (unlikely(r != 0))
6872 			goto done;
6873 
6874 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6875 		if (!r) {
6876 			r = gfx_v10_0_gfx_init_queue(ring);
6877 			amdgpu_bo_kunmap(ring->mqd_obj);
6878 			ring->mqd_ptr = NULL;
6879 		}
6880 		amdgpu_bo_unreserve(ring->mqd_obj);
6881 		if (r)
6882 			goto done;
6883 	}
6884 #ifndef BRING_UP_DEBUG
6885 	r = gfx_v10_0_kiq_enable_kgq(adev);
6886 	if (r)
6887 		goto done;
6888 #endif
6889 	r = gfx_v10_0_cp_gfx_start(adev);
6890 	if (r)
6891 		goto done;
6892 
6893 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6894 		ring = &adev->gfx.gfx_ring[i];
6895 		ring->sched.ready = true;
6896 	}
6897 done:
6898 	return r;
6899 }
6900 
6901 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6902 				      struct amdgpu_mqd_prop *prop)
6903 {
6904 	struct v10_compute_mqd *mqd = m;
6905 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6906 	uint32_t tmp;
6907 
6908 	mqd->header = 0xC0310800;
6909 	mqd->compute_pipelinestat_enable = 0x00000001;
6910 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6911 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6912 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6913 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6914 	mqd->compute_misc_reserved = 0x00000003;
6915 
6916 	eop_base_addr = prop->eop_gpu_addr >> 8;
6917 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6918 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6919 
6920 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6921 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6922 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6923 			(order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6924 
6925 	mqd->cp_hqd_eop_control = tmp;
6926 
6927 	/* enable doorbell? */
6928 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6929 
6930 	if (prop->use_doorbell) {
6931 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6932 				    DOORBELL_OFFSET, prop->doorbell_index);
6933 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6934 				    DOORBELL_EN, 1);
6935 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6936 				    DOORBELL_SOURCE, 0);
6937 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6938 				    DOORBELL_HIT, 0);
6939 	} else {
6940 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6941 				    DOORBELL_EN, 0);
6942 	}
6943 
6944 	mqd->cp_hqd_pq_doorbell_control = tmp;
6945 
6946 	/* disable the queue if it's active */
6947 	mqd->cp_hqd_dequeue_request = 0;
6948 	mqd->cp_hqd_pq_rptr = 0;
6949 	mqd->cp_hqd_pq_wptr_lo = 0;
6950 	mqd->cp_hqd_pq_wptr_hi = 0;
6951 
6952 	/* set the pointer to the MQD */
6953 	mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6954 	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6955 
6956 	/* set MQD vmid to 0 */
6957 	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6958 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6959 	mqd->cp_mqd_control = tmp;
6960 
6961 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6962 	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6963 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6964 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6965 
6966 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6967 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6968 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6969 			    (order_base_2(prop->queue_size / 4) - 1));
6970 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6971 			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6972 #ifdef __BIG_ENDIAN
6973 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6974 #endif
6975 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6976 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6977 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6978 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6979 	mqd->cp_hqd_pq_control = tmp;
6980 
6981 	/* set the wb address whether it's enabled or not */
6982 	wb_gpu_addr = prop->rptr_gpu_addr;
6983 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6984 	mqd->cp_hqd_pq_rptr_report_addr_hi =
6985 		upper_32_bits(wb_gpu_addr) & 0xffff;
6986 
6987 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6988 	wb_gpu_addr = prop->wptr_gpu_addr;
6989 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6990 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6991 
6992 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6993 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6994 
6995 	/* set the vmid for the queue */
6996 	mqd->cp_hqd_vmid = 0;
6997 
6998 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6999 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
7000 	mqd->cp_hqd_persistent_state = tmp;
7001 
7002 	/* set MIN_IB_AVAIL_SIZE */
7003 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
7004 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
7005 	mqd->cp_hqd_ib_control = tmp;
7006 
7007 	/* set static priority for a compute queue/ring */
7008 	mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
7009 	mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
7010 
7011 	mqd->cp_hqd_active = prop->hqd_active;
7012 
7013 	return 0;
7014 }
7015 
7016 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
7017 {
7018 	struct amdgpu_device *adev = ring->adev;
7019 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
7020 	int j;
7021 
7022 	/* inactivate the queue */
7023 	if (amdgpu_sriov_vf(adev))
7024 		WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
7025 
7026 	/* disable wptr polling */
7027 	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
7028 
7029 	/* disable the queue if it's active */
7030 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
7031 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
7032 		for (j = 0; j < adev->usec_timeout; j++) {
7033 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
7034 				break;
7035 			udelay(1);
7036 		}
7037 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
7038 		       mqd->cp_hqd_dequeue_request);
7039 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
7040 		       mqd->cp_hqd_pq_rptr);
7041 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7042 		       mqd->cp_hqd_pq_wptr_lo);
7043 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7044 		       mqd->cp_hqd_pq_wptr_hi);
7045 	}
7046 
7047 	/* disable doorbells */
7048 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
7049 
7050 	/* write the EOP addr */
7051 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
7052 	       mqd->cp_hqd_eop_base_addr_lo);
7053 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
7054 	       mqd->cp_hqd_eop_base_addr_hi);
7055 
7056 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
7057 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
7058 	       mqd->cp_hqd_eop_control);
7059 
7060 	/* set the pointer to the MQD */
7061 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
7062 	       mqd->cp_mqd_base_addr_lo);
7063 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
7064 	       mqd->cp_mqd_base_addr_hi);
7065 
7066 	/* set MQD vmid to 0 */
7067 	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
7068 	       mqd->cp_mqd_control);
7069 
7070 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7071 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7072 	       mqd->cp_hqd_pq_base_lo);
7073 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7074 	       mqd->cp_hqd_pq_base_hi);
7075 
7076 	/* set up the HQD, this is similar to CP_RB0_CNTL */
7077 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7078 	       mqd->cp_hqd_pq_control);
7079 
7080 	/* set the wb address whether it's enabled or not */
7081 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7082 		mqd->cp_hqd_pq_rptr_report_addr_lo);
7083 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7084 		mqd->cp_hqd_pq_rptr_report_addr_hi);
7085 
7086 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7087 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7088 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
7089 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7090 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
7091 
7092 	/* enable the doorbell if requested */
7093 	if (ring->use_doorbell) {
7094 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7095 			(adev->doorbell_index.kiq * 2) << 2);
7096 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7097 			(adev->doorbell_index.userqueue_end * 2) << 2);
7098 	}
7099 
7100 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7101 	       mqd->cp_hqd_pq_doorbell_control);
7102 
7103 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7104 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7105 	       mqd->cp_hqd_pq_wptr_lo);
7106 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7107 	       mqd->cp_hqd_pq_wptr_hi);
7108 
7109 	/* set the vmid for the queue */
7110 	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7111 
7112 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7113 	       mqd->cp_hqd_persistent_state);
7114 
7115 	/* activate the queue */
7116 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7117 	       mqd->cp_hqd_active);
7118 
7119 	if (ring->use_doorbell)
7120 		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7121 
7122 	return 0;
7123 }
7124 
7125 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7126 {
7127 	struct amdgpu_device *adev = ring->adev;
7128 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
7129 	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
7130 
7131 	gfx_v10_0_kiq_setting(ring);
7132 
7133 	if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7134 		/* reset MQD to a clean status */
7135 		if (adev->gfx.mec.mqd_backup[mqd_idx])
7136 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7137 
7138 		/* reset ring buffer */
7139 		ring->wptr = 0;
7140 		amdgpu_ring_clear_ring(ring);
7141 
7142 		mutex_lock(&adev->srbm_mutex);
7143 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7144 		gfx_v10_0_kiq_init_register(ring);
7145 		nv_grbm_select(adev, 0, 0, 0, 0);
7146 		mutex_unlock(&adev->srbm_mutex);
7147 	} else {
7148 		memset((void *)mqd, 0, sizeof(*mqd));
7149 		mutex_lock(&adev->srbm_mutex);
7150 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7151 		amdgpu_ring_init_mqd(ring);
7152 		gfx_v10_0_kiq_init_register(ring);
7153 		nv_grbm_select(adev, 0, 0, 0, 0);
7154 		mutex_unlock(&adev->srbm_mutex);
7155 
7156 		if (adev->gfx.mec.mqd_backup[mqd_idx])
7157 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7158 	}
7159 
7160 	return 0;
7161 }
7162 
7163 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
7164 {
7165 	struct amdgpu_device *adev = ring->adev;
7166 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
7167 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
7168 
7169 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
7170 		memset((void *)mqd, 0, sizeof(*mqd));
7171 		mutex_lock(&adev->srbm_mutex);
7172 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7173 		amdgpu_ring_init_mqd(ring);
7174 		nv_grbm_select(adev, 0, 0, 0, 0);
7175 		mutex_unlock(&adev->srbm_mutex);
7176 
7177 		if (adev->gfx.mec.mqd_backup[mqd_idx])
7178 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7179 	} else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7180 		/* reset MQD to a clean status */
7181 		if (adev->gfx.mec.mqd_backup[mqd_idx])
7182 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7183 
7184 		/* reset ring buffer */
7185 		ring->wptr = 0;
7186 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7187 		amdgpu_ring_clear_ring(ring);
7188 	} else {
7189 		amdgpu_ring_clear_ring(ring);
7190 	}
7191 
7192 	return 0;
7193 }
7194 
7195 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7196 {
7197 	struct amdgpu_ring *ring;
7198 	int r;
7199 
7200 	ring = &adev->gfx.kiq.ring;
7201 
7202 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
7203 	if (unlikely(r != 0))
7204 		return r;
7205 
7206 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7207 	if (unlikely(r != 0))
7208 		return r;
7209 
7210 	gfx_v10_0_kiq_init_queue(ring);
7211 	amdgpu_bo_kunmap(ring->mqd_obj);
7212 	ring->mqd_ptr = NULL;
7213 	amdgpu_bo_unreserve(ring->mqd_obj);
7214 	ring->sched.ready = true;
7215 	return 0;
7216 }
7217 
7218 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7219 {
7220 	struct amdgpu_ring *ring = NULL;
7221 	int r = 0, i;
7222 
7223 	gfx_v10_0_cp_compute_enable(adev, true);
7224 
7225 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7226 		ring = &adev->gfx.compute_ring[i];
7227 
7228 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
7229 		if (unlikely(r != 0))
7230 			goto done;
7231 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7232 		if (!r) {
7233 			r = gfx_v10_0_kcq_init_queue(ring);
7234 			amdgpu_bo_kunmap(ring->mqd_obj);
7235 			ring->mqd_ptr = NULL;
7236 		}
7237 		amdgpu_bo_unreserve(ring->mqd_obj);
7238 		if (r)
7239 			goto done;
7240 	}
7241 
7242 	r = amdgpu_gfx_enable_kcq(adev);
7243 done:
7244 	return r;
7245 }
7246 
7247 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7248 {
7249 	int r, i;
7250 	struct amdgpu_ring *ring;
7251 
7252 	if (!(adev->flags & AMD_IS_APU))
7253 		gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7254 
7255 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7256 		/* legacy firmware loading */
7257 		r = gfx_v10_0_cp_gfx_load_microcode(adev);
7258 		if (r)
7259 			return r;
7260 
7261 		r = gfx_v10_0_cp_compute_load_microcode(adev);
7262 		if (r)
7263 			return r;
7264 	}
7265 
7266 	if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
7267 		r = amdgpu_mes_kiq_hw_init(adev);
7268 	else
7269 		r = gfx_v10_0_kiq_resume(adev);
7270 	if (r)
7271 		return r;
7272 
7273 	r = gfx_v10_0_kcq_resume(adev);
7274 	if (r)
7275 		return r;
7276 
7277 	if (!amdgpu_async_gfx_ring) {
7278 		r = gfx_v10_0_cp_gfx_resume(adev);
7279 		if (r)
7280 			return r;
7281 	} else {
7282 		r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7283 		if (r)
7284 			return r;
7285 	}
7286 
7287 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7288 		ring = &adev->gfx.gfx_ring[i];
7289 		r = amdgpu_ring_test_helper(ring);
7290 		if (r)
7291 			return r;
7292 	}
7293 
7294 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7295 		ring = &adev->gfx.compute_ring[i];
7296 		r = amdgpu_ring_test_helper(ring);
7297 		if (r)
7298 			return r;
7299 	}
7300 
7301 	return 0;
7302 }
7303 
7304 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7305 {
7306 	gfx_v10_0_cp_gfx_enable(adev, enable);
7307 	gfx_v10_0_cp_compute_enable(adev, enable);
7308 }
7309 
7310 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7311 {
7312 	uint32_t data, pattern = 0xDEADBEEF;
7313 
7314 	/* check if mmVGT_ESGS_RING_SIZE_UMD
7315 	 * has been remapped to mmVGT_ESGS_RING_SIZE */
7316 	switch (adev->ip_versions[GC_HWIP][0]) {
7317 	case IP_VERSION(10, 3, 0):
7318 	case IP_VERSION(10, 3, 2):
7319 	case IP_VERSION(10, 3, 4):
7320 	case IP_VERSION(10, 3, 5):
7321 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7322 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7323 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7324 
7325 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7326 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7327 			return true;
7328 		} else {
7329 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7330 			return false;
7331 		}
7332 		break;
7333 	case IP_VERSION(10, 3, 1):
7334 	case IP_VERSION(10, 3, 3):
7335 	case IP_VERSION(10, 3, 6):
7336 	case IP_VERSION(10, 3, 7):
7337 		return true;
7338 	default:
7339 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7340 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7341 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7342 
7343 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7344 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7345 			return true;
7346 		} else {
7347 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7348 			return false;
7349 		}
7350 		break;
7351 	}
7352 }
7353 
7354 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7355 {
7356 	uint32_t data;
7357 
7358 	if (amdgpu_sriov_vf(adev))
7359 		return;
7360 
7361 	/* initialize cam_index to 0
7362 	 * index will auto-inc after each data writting */
7363 	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7364 
7365 	switch (adev->ip_versions[GC_HWIP][0]) {
7366 	case IP_VERSION(10, 3, 0):
7367 	case IP_VERSION(10, 3, 2):
7368 	case IP_VERSION(10, 3, 1):
7369 	case IP_VERSION(10, 3, 4):
7370 	case IP_VERSION(10, 3, 5):
7371 	case IP_VERSION(10, 3, 6):
7372 	case IP_VERSION(10, 3, 3):
7373 	case IP_VERSION(10, 3, 7):
7374 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7375 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7376 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7377 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7378 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7379 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7380 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7381 
7382 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7383 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7384 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7385 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7386 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7387 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7388 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7389 
7390 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7391 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7392 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7393 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7394 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7395 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7396 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7397 
7398 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7399 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7400 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7401 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7402 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7403 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7404 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7405 
7406 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7407 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7408 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7409 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7410 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7411 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7412 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7413 
7414 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7415 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7416 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7417 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7418 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7419 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7420 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7421 
7422 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7423 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7424 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7425 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7426 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7427 		break;
7428 	default:
7429 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7430 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7431 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7432 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7433 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7434 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7435 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7436 
7437 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7438 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7439 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7440 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7441 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7442 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7443 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7444 
7445 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7446 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7447 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7448 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7449 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7450 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7451 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7452 
7453 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7454 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7455 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7456 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7457 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7458 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7459 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7460 
7461 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7462 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7463 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7464 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7465 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7466 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7467 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7468 
7469 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7470 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7471 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7472 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7473 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7474 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7475 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7476 
7477 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7478 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7479 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7480 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7481 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7482 		break;
7483 	}
7484 
7485 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7486 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7487 }
7488 
7489 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7490 {
7491 	uint32_t data;
7492 	data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7493 	data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7494 	WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7495 
7496 	data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7497 	data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7498 	WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7499 }
7500 
7501 static int gfx_v10_0_hw_init(void *handle)
7502 {
7503 	int r;
7504 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7505 
7506 	if (!amdgpu_emu_mode)
7507 		gfx_v10_0_init_golden_registers(adev);
7508 
7509 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7510 		/**
7511 		 * For gfx 10, rlc firmware loading relies on smu firmware is
7512 		 * loaded firstly, so in direct type, it has to load smc ucode
7513 		 * here before rlc.
7514 		 */
7515 		if (!(adev->flags & AMD_IS_APU)) {
7516 			r = amdgpu_pm_load_smu_firmware(adev, NULL);
7517 			if (r)
7518 				return r;
7519 		}
7520 		gfx_v10_0_disable_gpa_mode(adev);
7521 	}
7522 
7523 	/* if GRBM CAM not remapped, set up the remapping */
7524 	if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7525 		gfx_v10_0_setup_grbm_cam_remapping(adev);
7526 
7527 	gfx_v10_0_constants_init(adev);
7528 
7529 	r = gfx_v10_0_rlc_resume(adev);
7530 	if (r)
7531 		return r;
7532 
7533 	/*
7534 	 * init golden registers and rlc resume may override some registers,
7535 	 * reconfig them here
7536 	 */
7537 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
7538 	    adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
7539 	    adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
7540 		gfx_v10_0_tcp_harvest(adev);
7541 
7542 	r = gfx_v10_0_cp_resume(adev);
7543 	if (r)
7544 		return r;
7545 
7546 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
7547 		gfx_v10_3_program_pbb_mode(adev);
7548 
7549 	if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
7550 		gfx_v10_3_set_power_brake_sequence(adev);
7551 
7552 	return r;
7553 }
7554 
7555 #ifndef BRING_UP_DEBUG
7556 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7557 {
7558 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7559 	struct amdgpu_ring *kiq_ring = &kiq->ring;
7560 	int i;
7561 
7562 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7563 		return -EINVAL;
7564 
7565 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7566 					adev->gfx.num_gfx_rings))
7567 		return -ENOMEM;
7568 
7569 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7570 		kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7571 					   PREEMPT_QUEUES, 0, 0);
7572 
7573 	return amdgpu_ring_test_helper(kiq_ring);
7574 }
7575 #endif
7576 
7577 static int gfx_v10_0_hw_fini(void *handle)
7578 {
7579 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7580 	int r;
7581 	uint32_t tmp;
7582 
7583 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7584 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7585 
7586 	if (!adev->no_hw_access) {
7587 #ifndef BRING_UP_DEBUG
7588 		if (amdgpu_async_gfx_ring) {
7589 			r = gfx_v10_0_kiq_disable_kgq(adev);
7590 			if (r)
7591 				DRM_ERROR("KGQ disable failed\n");
7592 		}
7593 #endif
7594 		if (amdgpu_gfx_disable_kcq(adev))
7595 			DRM_ERROR("KCQ disable failed\n");
7596 	}
7597 
7598 	if (amdgpu_sriov_vf(adev)) {
7599 		gfx_v10_0_cp_gfx_enable(adev, false);
7600 		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7601 		if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
7602 			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7603 			tmp &= 0xffffff00;
7604 			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7605 		} else {
7606 			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7607 			tmp &= 0xffffff00;
7608 			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7609 		}
7610 
7611 		return 0;
7612 	}
7613 	gfx_v10_0_cp_enable(adev, false);
7614 	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7615 
7616 	return 0;
7617 }
7618 
7619 static int gfx_v10_0_suspend(void *handle)
7620 {
7621 	return gfx_v10_0_hw_fini(handle);
7622 }
7623 
7624 static int gfx_v10_0_resume(void *handle)
7625 {
7626 	return gfx_v10_0_hw_init(handle);
7627 }
7628 
7629 static bool gfx_v10_0_is_idle(void *handle)
7630 {
7631 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7632 
7633 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7634 				GRBM_STATUS, GUI_ACTIVE))
7635 		return false;
7636 	else
7637 		return true;
7638 }
7639 
7640 static int gfx_v10_0_wait_for_idle(void *handle)
7641 {
7642 	unsigned i;
7643 	u32 tmp;
7644 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7645 
7646 	for (i = 0; i < adev->usec_timeout; i++) {
7647 		/* read MC_STATUS */
7648 		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7649 			GRBM_STATUS__GUI_ACTIVE_MASK;
7650 
7651 		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7652 			return 0;
7653 		udelay(1);
7654 	}
7655 	return -ETIMEDOUT;
7656 }
7657 
7658 static int gfx_v10_0_soft_reset(void *handle)
7659 {
7660 	u32 grbm_soft_reset = 0;
7661 	u32 tmp;
7662 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7663 
7664 	/* GRBM_STATUS */
7665 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7666 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7667 		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7668 		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7669 		   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7670 		   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7671 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7672 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7673 						1);
7674 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7675 						GRBM_SOFT_RESET, SOFT_RESET_GFX,
7676 						1);
7677 	}
7678 
7679 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7680 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7681 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7682 						1);
7683 	}
7684 
7685 	/* GRBM_STATUS2 */
7686 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7687 	switch (adev->ip_versions[GC_HWIP][0]) {
7688 	case IP_VERSION(10, 3, 0):
7689 	case IP_VERSION(10, 3, 2):
7690 	case IP_VERSION(10, 3, 1):
7691 	case IP_VERSION(10, 3, 4):
7692 	case IP_VERSION(10, 3, 5):
7693 	case IP_VERSION(10, 3, 6):
7694 	case IP_VERSION(10, 3, 3):
7695 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7696 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7697 							GRBM_SOFT_RESET,
7698 							SOFT_RESET_RLC,
7699 							1);
7700 		break;
7701 	default:
7702 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7703 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7704 							GRBM_SOFT_RESET,
7705 							SOFT_RESET_RLC,
7706 							1);
7707 		break;
7708 	}
7709 
7710 	if (grbm_soft_reset) {
7711 		/* stop the rlc */
7712 		gfx_v10_0_rlc_stop(adev);
7713 
7714 		/* Disable GFX parsing/prefetching */
7715 		gfx_v10_0_cp_gfx_enable(adev, false);
7716 
7717 		/* Disable MEC parsing/prefetching */
7718 		gfx_v10_0_cp_compute_enable(adev, false);
7719 
7720 		if (grbm_soft_reset) {
7721 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7722 			tmp |= grbm_soft_reset;
7723 			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7724 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7725 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7726 
7727 			udelay(50);
7728 
7729 			tmp &= ~grbm_soft_reset;
7730 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7731 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7732 		}
7733 
7734 		/* Wait a little for things to settle down */
7735 		udelay(50);
7736 	}
7737 	return 0;
7738 }
7739 
7740 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7741 {
7742 	uint64_t clock, clock_lo, clock_hi, hi_check;
7743 
7744 	switch (adev->ip_versions[GC_HWIP][0]) {
7745 	case IP_VERSION(10, 3, 1):
7746 	case IP_VERSION(10, 3, 3):
7747 	case IP_VERSION(10, 3, 7):
7748 		preempt_disable();
7749 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7750 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7751 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7752 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7753 		 * roughly every 42 seconds.
7754 		 */
7755 		if (hi_check != clock_hi) {
7756 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7757 			clock_hi = hi_check;
7758 		}
7759 		preempt_enable();
7760 		clock = clock_lo | (clock_hi << 32ULL);
7761 		break;
7762 	case IP_VERSION(10, 3, 6):
7763 		preempt_disable();
7764 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7765 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7766 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7767 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7768 		 * roughly every 42 seconds.
7769 		 */
7770 		if (hi_check != clock_hi) {
7771 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7772 			clock_hi = hi_check;
7773 		}
7774 		preempt_enable();
7775 		clock = clock_lo | (clock_hi << 32ULL);
7776 		break;
7777 	default:
7778 		preempt_disable();
7779 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7780 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7781 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7782 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7783 		 * roughly every 42 seconds.
7784 		 */
7785 		if (hi_check != clock_hi) {
7786 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7787 			clock_hi = hi_check;
7788 		}
7789 		preempt_enable();
7790 		clock = clock_lo | (clock_hi << 32ULL);
7791 		break;
7792 	}
7793 	return clock;
7794 }
7795 
7796 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7797 					   uint32_t vmid,
7798 					   uint32_t gds_base, uint32_t gds_size,
7799 					   uint32_t gws_base, uint32_t gws_size,
7800 					   uint32_t oa_base, uint32_t oa_size)
7801 {
7802 	struct amdgpu_device *adev = ring->adev;
7803 
7804 	/* GDS Base */
7805 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7806 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7807 				    gds_base);
7808 
7809 	/* GDS Size */
7810 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7811 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7812 				    gds_size);
7813 
7814 	/* GWS */
7815 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7816 				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7817 				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7818 
7819 	/* OA */
7820 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7821 				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7822 				    (1 << (oa_size + oa_base)) - (1 << oa_base));
7823 }
7824 
7825 static int gfx_v10_0_early_init(void *handle)
7826 {
7827 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7828 
7829 	switch (adev->ip_versions[GC_HWIP][0]) {
7830 	case IP_VERSION(10, 1, 10):
7831 	case IP_VERSION(10, 1, 1):
7832 	case IP_VERSION(10, 1, 2):
7833 	case IP_VERSION(10, 1, 3):
7834 	case IP_VERSION(10, 1, 4):
7835 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7836 		break;
7837 	case IP_VERSION(10, 3, 0):
7838 	case IP_VERSION(10, 3, 2):
7839 	case IP_VERSION(10, 3, 1):
7840 	case IP_VERSION(10, 3, 4):
7841 	case IP_VERSION(10, 3, 5):
7842 	case IP_VERSION(10, 3, 6):
7843 	case IP_VERSION(10, 3, 3):
7844 	case IP_VERSION(10, 3, 7):
7845 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7846 		break;
7847 	default:
7848 		break;
7849 	}
7850 
7851 	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7852 					  AMDGPU_MAX_COMPUTE_RINGS);
7853 
7854 	gfx_v10_0_set_kiq_pm4_funcs(adev);
7855 	gfx_v10_0_set_ring_funcs(adev);
7856 	gfx_v10_0_set_irq_funcs(adev);
7857 	gfx_v10_0_set_gds_init(adev);
7858 	gfx_v10_0_set_rlc_funcs(adev);
7859 	gfx_v10_0_set_mqd_funcs(adev);
7860 
7861 	/* init rlcg reg access ctrl */
7862 	gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7863 
7864 	return 0;
7865 }
7866 
7867 static int gfx_v10_0_late_init(void *handle)
7868 {
7869 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7870 	int r;
7871 
7872 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7873 	if (r)
7874 		return r;
7875 
7876 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7877 	if (r)
7878 		return r;
7879 
7880 	return 0;
7881 }
7882 
7883 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7884 {
7885 	uint32_t rlc_cntl;
7886 
7887 	/* if RLC is not enabled, do nothing */
7888 	rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7889 	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7890 }
7891 
7892 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7893 {
7894 	uint32_t data;
7895 	unsigned i;
7896 
7897 	data = RLC_SAFE_MODE__CMD_MASK;
7898 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7899 
7900 	switch (adev->ip_versions[GC_HWIP][0]) {
7901 	case IP_VERSION(10, 3, 0):
7902 	case IP_VERSION(10, 3, 2):
7903 	case IP_VERSION(10, 3, 1):
7904 	case IP_VERSION(10, 3, 4):
7905 	case IP_VERSION(10, 3, 5):
7906 	case IP_VERSION(10, 3, 6):
7907 	case IP_VERSION(10, 3, 3):
7908 	case IP_VERSION(10, 3, 7):
7909 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7910 
7911 		/* wait for RLC_SAFE_MODE */
7912 		for (i = 0; i < adev->usec_timeout; i++) {
7913 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7914 					   RLC_SAFE_MODE, CMD))
7915 				break;
7916 			udelay(1);
7917 		}
7918 		break;
7919 	default:
7920 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7921 
7922 		/* wait for RLC_SAFE_MODE */
7923 		for (i = 0; i < adev->usec_timeout; i++) {
7924 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7925 					   RLC_SAFE_MODE, CMD))
7926 				break;
7927 			udelay(1);
7928 		}
7929 		break;
7930 	}
7931 }
7932 
7933 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7934 {
7935 	uint32_t data;
7936 
7937 	data = RLC_SAFE_MODE__CMD_MASK;
7938 	switch (adev->ip_versions[GC_HWIP][0]) {
7939 	case IP_VERSION(10, 3, 0):
7940 	case IP_VERSION(10, 3, 2):
7941 	case IP_VERSION(10, 3, 1):
7942 	case IP_VERSION(10, 3, 4):
7943 	case IP_VERSION(10, 3, 5):
7944 	case IP_VERSION(10, 3, 6):
7945 	case IP_VERSION(10, 3, 3):
7946 	case IP_VERSION(10, 3, 7):
7947 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7948 		break;
7949 	default:
7950 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7951 		break;
7952 	}
7953 }
7954 
7955 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7956 						      bool enable)
7957 {
7958 	uint32_t data, def;
7959 
7960 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7961 		return;
7962 
7963 	/* It is disabled by HW by default */
7964 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7965 		/* 0 - Disable some blocks' MGCG */
7966 		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7967 		WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7968 		WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7969 		WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7970 
7971 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
7972 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7973 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7974 			  RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7975 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7976 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7977 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7978 			  RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7979 
7980 		if (def != data)
7981 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7982 
7983 		/* MGLS is a global flag to control all MGLS in GFX */
7984 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7985 			/* 2 - RLC memory Light sleep */
7986 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7987 				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7988 				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7989 				if (def != data)
7990 					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7991 			}
7992 			/* 3 - CP memory Light sleep */
7993 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7994 				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7995 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7996 				if (def != data)
7997 					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7998 			}
7999 		}
8000 	} else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
8001 		/* 1 - MGCG_OVERRIDE */
8002 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8003 		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
8004 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
8005 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
8006 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
8007 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
8008 			 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
8009 		if (def != data)
8010 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8011 
8012 		/* 2 - disable MGLS in CP */
8013 		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
8014 		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
8015 			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
8016 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
8017 		}
8018 
8019 		/* 3 - disable MGLS in RLC */
8020 		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
8021 		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
8022 			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
8023 			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
8024 		}
8025 
8026 	}
8027 }
8028 
8029 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
8030 					   bool enable)
8031 {
8032 	uint32_t data, def;
8033 
8034 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
8035 		return;
8036 
8037 	/* Enable 3D CGCG/CGLS */
8038 	if (enable) {
8039 		/* write cmd to clear cgcg/cgls ov */
8040 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8041 
8042 		/* unset CGCG override */
8043 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8044 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
8045 
8046 		/* update CGCG and CGLS override bits */
8047 		if (def != data)
8048 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8049 
8050 		/* enable 3Dcgcg FSM(0x0000363f) */
8051 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8052 		data = 0;
8053 
8054 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8055 			data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8056 				RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8057 
8058 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8059 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8060 				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8061 
8062 		if (def != data)
8063 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8064 
8065 		/* set IDLE_POLL_COUNT(0x00900100) */
8066 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8067 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8068 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8069 		if (def != data)
8070 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8071 	} else {
8072 		/* Disable CGCG/CGLS */
8073 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8074 
8075 		/* disable cgcg, cgls should be disabled */
8076 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8077 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8078 
8079 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8080 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8081 
8082 		/* disable cgcg and cgls in FSM */
8083 		if (def != data)
8084 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8085 	}
8086 }
8087 
8088 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8089 						      bool enable)
8090 {
8091 	uint32_t def, data;
8092 
8093 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8094 		return;
8095 
8096 	if (enable) {
8097 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8098 
8099 		/* unset CGCG override */
8100 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8101 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8102 
8103 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8104 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8105 
8106 		/* update CGCG and CGLS override bits */
8107 		if (def != data)
8108 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8109 
8110 		/* enable cgcg FSM(0x0000363F) */
8111 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8112 		data = 0;
8113 
8114 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8115 			data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8116 				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8117 
8118 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8119 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8120 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8121 
8122 		if (def != data)
8123 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8124 
8125 		/* set IDLE_POLL_COUNT(0x00900100) */
8126 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8127 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8128 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8129 		if (def != data)
8130 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8131 	} else {
8132 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8133 
8134 		/* reset CGCG/CGLS bits */
8135 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8136 			data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8137 
8138 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8139 			data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8140 
8141 		/* disable cgcg and cgls in FSM */
8142 		if (def != data)
8143 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8144 	}
8145 }
8146 
8147 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8148 						      bool enable)
8149 {
8150 	uint32_t def, data;
8151 
8152 	if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8153 		return;
8154 
8155 	if (enable) {
8156 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8157 		/* unset FGCG override */
8158 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8159 		/* update FGCG override bits */
8160 		if (def != data)
8161 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8162 
8163 		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8164 		/* unset RLC SRAM CLK GATER override */
8165 		data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8166 		/* update RLC SRAM CLK GATER override bits */
8167 		if (def != data)
8168 			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8169 	} else {
8170 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8171 		/* reset FGCG bits */
8172 		data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8173 		/* disable FGCG*/
8174 		if (def != data)
8175 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8176 
8177 		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8178 		/* reset RLC SRAM CLK GATER bits */
8179 		data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8180 		/* disable RLC SRAM CLK*/
8181 		if (def != data)
8182 			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8183 	}
8184 }
8185 
8186 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8187 {
8188 	uint32_t reg_data = 0;
8189 	uint32_t reg_idx = 0;
8190 	uint32_t i;
8191 
8192 	const uint32_t tcp_ctrl_regs[] = {
8193 		mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8194 		mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8195 		mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8196 		mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8197 		mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8198 		mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8199 		mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8200 		mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8201 		mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8202 		mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8203 		mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8204 		mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8205 		mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8206 		mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8207 		mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8208 		mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8209 		mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8210 		mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8211 		mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8212 		mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8213 		mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8214 		mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8215 		mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8216 		mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8217 	};
8218 
8219 	const uint32_t tcp_ctrl_regs_nv12[] = {
8220 		mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8221 		mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8222 		mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8223 		mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8224 		mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8225 		mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8226 		mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8227 		mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8228 		mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8229 		mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8230 		mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8231 		mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8232 		mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8233 		mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8234 		mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8235 		mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8236 		mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8237 		mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8238 		mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8239 		mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8240 	};
8241 
8242 	const uint32_t sm_ctlr_regs[] = {
8243 		mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8244 		mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8245 		mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8246 		mmCGTS_SA1_QUAD1_SM_CTRL_REG
8247 	};
8248 
8249 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
8250 		for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8251 			reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8252 				  tcp_ctrl_regs_nv12[i];
8253 			reg_data = RREG32(reg_idx);
8254 			reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8255 			WREG32(reg_idx, reg_data);
8256 		}
8257 	} else {
8258 		for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8259 			reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8260 				  tcp_ctrl_regs[i];
8261 			reg_data = RREG32(reg_idx);
8262 			reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8263 			WREG32(reg_idx, reg_data);
8264 		}
8265 	}
8266 
8267 	for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8268 		reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8269 			  sm_ctlr_regs[i];
8270 		reg_data = RREG32(reg_idx);
8271 		reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8272 		reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8273 		WREG32(reg_idx, reg_data);
8274 	}
8275 }
8276 
8277 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8278 					    bool enable)
8279 {
8280 	amdgpu_gfx_rlc_enter_safe_mode(adev);
8281 
8282 	if (enable) {
8283 		/* enable FGCG firstly*/
8284 		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8285 		/* CGCG/CGLS should be enabled after MGCG/MGLS
8286 		 * ===  MGCG + MGLS ===
8287 		 */
8288 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8289 		/* ===  CGCG /CGLS for GFX 3D Only === */
8290 		gfx_v10_0_update_3d_clock_gating(adev, enable);
8291 		/* ===  CGCG + CGLS === */
8292 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8293 
8294 		if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) ||
8295 		    (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) ||
8296 		    (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)))
8297 			gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8298 	} else {
8299 		/* CGCG/CGLS should be disabled before MGCG/MGLS
8300 		 * ===  CGCG + CGLS ===
8301 		 */
8302 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8303 		/* ===  CGCG /CGLS for GFX 3D Only === */
8304 		gfx_v10_0_update_3d_clock_gating(adev, enable);
8305 		/* ===  MGCG + MGLS === */
8306 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8307 		/* disable fgcg at last*/
8308 		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8309 	}
8310 
8311 	if (adev->cg_flags &
8312 	    (AMD_CG_SUPPORT_GFX_MGCG |
8313 	     AMD_CG_SUPPORT_GFX_CGLS |
8314 	     AMD_CG_SUPPORT_GFX_CGCG |
8315 	     AMD_CG_SUPPORT_GFX_3D_CGCG |
8316 	     AMD_CG_SUPPORT_GFX_3D_CGLS))
8317 		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8318 
8319 	amdgpu_gfx_rlc_exit_safe_mode(adev);
8320 
8321 	return 0;
8322 }
8323 
8324 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8325 {
8326 	u32 reg, data;
8327 
8328 	amdgpu_gfx_off_ctrl(adev, false);
8329 
8330 	/* not for *_SOC15 */
8331 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8332 	if (amdgpu_sriov_is_pp_one_vf(adev))
8333 		data = RREG32_NO_KIQ(reg);
8334 	else
8335 		data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8336 
8337 	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8338 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8339 
8340 	if (amdgpu_sriov_is_pp_one_vf(adev))
8341 		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8342 	else
8343 		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8344 
8345 	amdgpu_gfx_off_ctrl(adev, true);
8346 }
8347 
8348 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8349 					uint32_t offset,
8350 					struct soc15_reg_rlcg *entries, int arr_size)
8351 {
8352 	int i;
8353 	uint32_t reg;
8354 
8355 	if (!entries)
8356 		return false;
8357 
8358 	for (i = 0; i < arr_size; i++) {
8359 		const struct soc15_reg_rlcg *entry;
8360 
8361 		entry = &entries[i];
8362 		reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8363 		if (offset == reg)
8364 			return true;
8365 	}
8366 
8367 	return false;
8368 }
8369 
8370 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8371 {
8372 	return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8373 }
8374 
8375 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8376 {
8377 	u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8378 
8379 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8380 		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8381 	else
8382 		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8383 
8384 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8385 
8386 	/*
8387 	 * CGPG enablement required and the register to program the hysteresis value
8388 	 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8389 	 * in refclk count. Note that RLC FW is modified to take 16 bits from
8390 	 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8391 	 *
8392 	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8393 	 * of CGPG enablement starting point.
8394 	 * Power/performance team will optimize it and might give a new value later.
8395 	 */
8396 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8397 		switch (adev->ip_versions[GC_HWIP][0]) {
8398 		case IP_VERSION(10, 3, 1):
8399 		case IP_VERSION(10, 3, 3):
8400 		case IP_VERSION(10, 3, 6):
8401 		case IP_VERSION(10, 3, 7):
8402 			data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8403 			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8404 			break;
8405 		default:
8406 			break;
8407 		}
8408 	}
8409 }
8410 
8411 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8412 {
8413 	amdgpu_gfx_rlc_enter_safe_mode(adev);
8414 
8415 	gfx_v10_cntl_power_gating(adev, enable);
8416 
8417 	amdgpu_gfx_rlc_exit_safe_mode(adev);
8418 }
8419 
8420 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8421 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8422 	.set_safe_mode = gfx_v10_0_set_safe_mode,
8423 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
8424 	.init = gfx_v10_0_rlc_init,
8425 	.get_csb_size = gfx_v10_0_get_csb_size,
8426 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
8427 	.resume = gfx_v10_0_rlc_resume,
8428 	.stop = gfx_v10_0_rlc_stop,
8429 	.reset = gfx_v10_0_rlc_reset,
8430 	.start = gfx_v10_0_rlc_start,
8431 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
8432 };
8433 
8434 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8435 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8436 	.set_safe_mode = gfx_v10_0_set_safe_mode,
8437 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
8438 	.init = gfx_v10_0_rlc_init,
8439 	.get_csb_size = gfx_v10_0_get_csb_size,
8440 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
8441 	.resume = gfx_v10_0_rlc_resume,
8442 	.stop = gfx_v10_0_rlc_stop,
8443 	.reset = gfx_v10_0_rlc_reset,
8444 	.start = gfx_v10_0_rlc_start,
8445 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
8446 	.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8447 };
8448 
8449 static int gfx_v10_0_set_powergating_state(void *handle,
8450 					  enum amd_powergating_state state)
8451 {
8452 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8453 	bool enable = (state == AMD_PG_STATE_GATE);
8454 
8455 	if (amdgpu_sriov_vf(adev))
8456 		return 0;
8457 
8458 	switch (adev->ip_versions[GC_HWIP][0]) {
8459 	case IP_VERSION(10, 1, 10):
8460 	case IP_VERSION(10, 1, 1):
8461 	case IP_VERSION(10, 1, 2):
8462 	case IP_VERSION(10, 3, 0):
8463 	case IP_VERSION(10, 3, 2):
8464 	case IP_VERSION(10, 3, 4):
8465 	case IP_VERSION(10, 3, 5):
8466 		amdgpu_gfx_off_ctrl(adev, enable);
8467 		break;
8468 	case IP_VERSION(10, 3, 1):
8469 	case IP_VERSION(10, 3, 3):
8470 	case IP_VERSION(10, 3, 6):
8471 	case IP_VERSION(10, 3, 7):
8472 		gfx_v10_cntl_pg(adev, enable);
8473 		amdgpu_gfx_off_ctrl(adev, enable);
8474 		break;
8475 	default:
8476 		break;
8477 	}
8478 	return 0;
8479 }
8480 
8481 static int gfx_v10_0_set_clockgating_state(void *handle,
8482 					  enum amd_clockgating_state state)
8483 {
8484 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8485 
8486 	if (amdgpu_sriov_vf(adev))
8487 		return 0;
8488 
8489 	switch (adev->ip_versions[GC_HWIP][0]) {
8490 	case IP_VERSION(10, 1, 10):
8491 	case IP_VERSION(10, 1, 1):
8492 	case IP_VERSION(10, 1, 2):
8493 	case IP_VERSION(10, 3, 0):
8494 	case IP_VERSION(10, 3, 2):
8495 	case IP_VERSION(10, 3, 1):
8496 	case IP_VERSION(10, 3, 4):
8497 	case IP_VERSION(10, 3, 5):
8498 	case IP_VERSION(10, 3, 6):
8499 	case IP_VERSION(10, 3, 3):
8500 	case IP_VERSION(10, 3, 7):
8501 		gfx_v10_0_update_gfx_clock_gating(adev,
8502 						 state == AMD_CG_STATE_GATE);
8503 		break;
8504 	default:
8505 		break;
8506 	}
8507 	return 0;
8508 }
8509 
8510 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8511 {
8512 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8513 	int data;
8514 
8515 	/* AMD_CG_SUPPORT_GFX_FGCG */
8516 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8517 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8518 		*flags |= AMD_CG_SUPPORT_GFX_FGCG;
8519 
8520 	/* AMD_CG_SUPPORT_GFX_MGCG */
8521 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8522 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8523 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
8524 
8525 	/* AMD_CG_SUPPORT_GFX_CGCG */
8526 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8527 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8528 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
8529 
8530 	/* AMD_CG_SUPPORT_GFX_CGLS */
8531 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8532 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
8533 
8534 	/* AMD_CG_SUPPORT_GFX_RLC_LS */
8535 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8536 	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8537 		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8538 
8539 	/* AMD_CG_SUPPORT_GFX_CP_LS */
8540 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8541 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8542 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8543 
8544 	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
8545 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8546 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8547 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8548 
8549 	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
8550 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8551 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8552 }
8553 
8554 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8555 {
8556 	/* gfx10 is 32bit rptr*/
8557 	return *(uint32_t *)ring->rptr_cpu_addr;
8558 }
8559 
8560 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8561 {
8562 	struct amdgpu_device *adev = ring->adev;
8563 	u64 wptr;
8564 
8565 	/* XXX check if swapping is necessary on BE */
8566 	if (ring->use_doorbell) {
8567 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8568 	} else {
8569 		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8570 		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8571 	}
8572 
8573 	return wptr;
8574 }
8575 
8576 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8577 {
8578 	struct amdgpu_device *adev = ring->adev;
8579 	uint32_t *wptr_saved;
8580 	uint32_t *is_queue_unmap;
8581 	uint64_t aggregated_db_index;
8582 	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
8583 	uint64_t wptr_tmp;
8584 
8585 	if (ring->is_mes_queue) {
8586 		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8587 		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8588 					      sizeof(uint32_t));
8589 		aggregated_db_index =
8590 			amdgpu_mes_get_aggregated_doorbell_index(adev,
8591 			AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8592 
8593 		wptr_tmp = ring->wptr & ring->buf_mask;
8594 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8595 		*wptr_saved = wptr_tmp;
8596 		/* assume doorbell always being used by mes mapped queue */
8597 		if (*is_queue_unmap) {
8598 			WDOORBELL64(aggregated_db_index, wptr_tmp);
8599 			WDOORBELL64(ring->doorbell_index, wptr_tmp);
8600 		} else {
8601 			WDOORBELL64(ring->doorbell_index, wptr_tmp);
8602 
8603 			if (*is_queue_unmap)
8604 				WDOORBELL64(aggregated_db_index, wptr_tmp);
8605 		}
8606 	} else {
8607 		if (ring->use_doorbell) {
8608 			/* XXX check if swapping is necessary on BE */
8609 			atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8610 				     ring->wptr);
8611 			WDOORBELL64(ring->doorbell_index, ring->wptr);
8612 		} else {
8613 			WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8614 				     lower_32_bits(ring->wptr));
8615 			WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8616 				     upper_32_bits(ring->wptr));
8617 		}
8618 	}
8619 }
8620 
8621 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8622 {
8623 	/* gfx10 hardware is 32bit rptr */
8624 	return *(uint32_t *)ring->rptr_cpu_addr;
8625 }
8626 
8627 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8628 {
8629 	u64 wptr;
8630 
8631 	/* XXX check if swapping is necessary on BE */
8632 	if (ring->use_doorbell)
8633 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8634 	else
8635 		BUG();
8636 	return wptr;
8637 }
8638 
8639 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8640 {
8641 	struct amdgpu_device *adev = ring->adev;
8642 	uint32_t *wptr_saved;
8643 	uint32_t *is_queue_unmap;
8644 	uint64_t aggregated_db_index;
8645 	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
8646 	uint64_t wptr_tmp;
8647 
8648 	if (ring->is_mes_queue) {
8649 		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8650 		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8651 					      sizeof(uint32_t));
8652 		aggregated_db_index =
8653 			amdgpu_mes_get_aggregated_doorbell_index(adev,
8654 			AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8655 
8656 		wptr_tmp = ring->wptr & ring->buf_mask;
8657 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8658 		*wptr_saved = wptr_tmp;
8659 		/* assume doorbell always used by mes mapped queue */
8660 		if (*is_queue_unmap) {
8661 			WDOORBELL64(aggregated_db_index, wptr_tmp);
8662 			WDOORBELL64(ring->doorbell_index, wptr_tmp);
8663 		} else {
8664 			WDOORBELL64(ring->doorbell_index, wptr_tmp);
8665 
8666 			if (*is_queue_unmap)
8667 				WDOORBELL64(aggregated_db_index, wptr_tmp);
8668 		}
8669 	} else {
8670 		/* XXX check if swapping is necessary on BE */
8671 		if (ring->use_doorbell) {
8672 			atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8673 				     ring->wptr);
8674 			WDOORBELL64(ring->doorbell_index, ring->wptr);
8675 		} else {
8676 			BUG(); /* only DOORBELL method supported on gfx10 now */
8677 		}
8678 	}
8679 }
8680 
8681 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8682 {
8683 	struct amdgpu_device *adev = ring->adev;
8684 	u32 ref_and_mask, reg_mem_engine;
8685 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8686 
8687 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8688 		switch (ring->me) {
8689 		case 1:
8690 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8691 			break;
8692 		case 2:
8693 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8694 			break;
8695 		default:
8696 			return;
8697 		}
8698 		reg_mem_engine = 0;
8699 	} else {
8700 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8701 		reg_mem_engine = 1; /* pfp */
8702 	}
8703 
8704 	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8705 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8706 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8707 			       ref_and_mask, ref_and_mask, 0x20);
8708 }
8709 
8710 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8711 				       struct amdgpu_job *job,
8712 				       struct amdgpu_ib *ib,
8713 				       uint32_t flags)
8714 {
8715 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8716 	u32 header, control = 0;
8717 
8718 	if (ib->flags & AMDGPU_IB_FLAG_CE)
8719 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8720 	else
8721 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8722 
8723 	control |= ib->length_dw | (vmid << 24);
8724 
8725 	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8726 		control |= INDIRECT_BUFFER_PRE_ENB(1);
8727 
8728 		if (flags & AMDGPU_IB_PREEMPTED)
8729 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
8730 
8731 		if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8732 			gfx_v10_0_ring_emit_de_meta(ring,
8733 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8734 	}
8735 
8736 	if (ring->is_mes_queue)
8737 		/* inherit vmid from mqd */
8738 		control |= 0x400000;
8739 
8740 	amdgpu_ring_write(ring, header);
8741 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8742 	amdgpu_ring_write(ring,
8743 #ifdef __BIG_ENDIAN
8744 		(2 << 0) |
8745 #endif
8746 		lower_32_bits(ib->gpu_addr));
8747 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8748 	amdgpu_ring_write(ring, control);
8749 }
8750 
8751 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8752 					   struct amdgpu_job *job,
8753 					   struct amdgpu_ib *ib,
8754 					   uint32_t flags)
8755 {
8756 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8757 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8758 
8759 	if (ring->is_mes_queue)
8760 		/* inherit vmid from mqd */
8761 		control |= 0x40000000;
8762 
8763 	/* Currently, there is a high possibility to get wave ID mismatch
8764 	 * between ME and GDS, leading to a hw deadlock, because ME generates
8765 	 * different wave IDs than the GDS expects. This situation happens
8766 	 * randomly when at least 5 compute pipes use GDS ordered append.
8767 	 * The wave IDs generated by ME are also wrong after suspend/resume.
8768 	 * Those are probably bugs somewhere else in the kernel driver.
8769 	 *
8770 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8771 	 * GDS to 0 for this ring (me/pipe).
8772 	 */
8773 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8774 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8775 		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8776 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8777 	}
8778 
8779 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8780 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8781 	amdgpu_ring_write(ring,
8782 #ifdef __BIG_ENDIAN
8783 				(2 << 0) |
8784 #endif
8785 				lower_32_bits(ib->gpu_addr));
8786 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8787 	amdgpu_ring_write(ring, control);
8788 }
8789 
8790 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8791 				     u64 seq, unsigned flags)
8792 {
8793 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8794 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8795 
8796 	/* RELEASE_MEM - flush caches, send int */
8797 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8798 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8799 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
8800 				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8801 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
8802 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8803 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8804 				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8805 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8806 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8807 
8808 	/*
8809 	 * the address should be Qword aligned if 64bit write, Dword
8810 	 * aligned if only send 32bit data low (discard data high)
8811 	 */
8812 	if (write64bit)
8813 		BUG_ON(addr & 0x7);
8814 	else
8815 		BUG_ON(addr & 0x3);
8816 	amdgpu_ring_write(ring, lower_32_bits(addr));
8817 	amdgpu_ring_write(ring, upper_32_bits(addr));
8818 	amdgpu_ring_write(ring, lower_32_bits(seq));
8819 	amdgpu_ring_write(ring, upper_32_bits(seq));
8820 	amdgpu_ring_write(ring, ring->is_mes_queue ?
8821 			 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8822 }
8823 
8824 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8825 {
8826 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8827 	uint32_t seq = ring->fence_drv.sync_seq;
8828 	uint64_t addr = ring->fence_drv.gpu_addr;
8829 
8830 	gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8831 			       upper_32_bits(addr), seq, 0xffffffff, 4);
8832 }
8833 
8834 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8835 				   uint16_t pasid, uint32_t flush_type,
8836 				   bool all_hub, uint8_t dst_sel)
8837 {
8838 	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8839 	amdgpu_ring_write(ring,
8840 			  PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8841 			  PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8842 			  PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8843 			  PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8844 }
8845 
8846 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8847 					 unsigned vmid, uint64_t pd_addr)
8848 {
8849 	if (ring->is_mes_queue)
8850 		gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
8851 	else
8852 		amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8853 
8854 	/* compute doesn't have PFP */
8855 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8856 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
8857 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8858 		amdgpu_ring_write(ring, 0x0);
8859 	}
8860 }
8861 
8862 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8863 					  u64 seq, unsigned int flags)
8864 {
8865 	struct amdgpu_device *adev = ring->adev;
8866 
8867 	/* we only allocate 32bit for each seq wb address */
8868 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8869 
8870 	/* write fence seq to the "addr" */
8871 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8872 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8873 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8874 	amdgpu_ring_write(ring, lower_32_bits(addr));
8875 	amdgpu_ring_write(ring, upper_32_bits(addr));
8876 	amdgpu_ring_write(ring, lower_32_bits(seq));
8877 
8878 	if (flags & AMDGPU_FENCE_FLAG_INT) {
8879 		/* set register to trigger INT */
8880 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8881 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8882 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8883 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8884 		amdgpu_ring_write(ring, 0);
8885 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8886 	}
8887 }
8888 
8889 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8890 {
8891 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8892 	amdgpu_ring_write(ring, 0);
8893 }
8894 
8895 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8896 					 uint32_t flags)
8897 {
8898 	uint32_t dw2 = 0;
8899 
8900 	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8901 		gfx_v10_0_ring_emit_ce_meta(ring,
8902 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8903 
8904 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8905 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8906 		/* set load_global_config & load_global_uconfig */
8907 		dw2 |= 0x8001;
8908 		/* set load_cs_sh_regs */
8909 		dw2 |= 0x01000000;
8910 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
8911 		dw2 |= 0x10002;
8912 
8913 		/* set load_ce_ram if preamble presented */
8914 		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8915 			dw2 |= 0x10000000;
8916 	} else {
8917 		/* still load_ce_ram if this is the first time preamble presented
8918 		 * although there is no context switch happens.
8919 		 */
8920 		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8921 			dw2 |= 0x10000000;
8922 	}
8923 
8924 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8925 	amdgpu_ring_write(ring, dw2);
8926 	amdgpu_ring_write(ring, 0);
8927 }
8928 
8929 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8930 {
8931 	unsigned ret;
8932 
8933 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8934 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8935 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8936 	amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8937 	ret = ring->wptr & ring->buf_mask;
8938 	amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8939 
8940 	return ret;
8941 }
8942 
8943 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8944 {
8945 	unsigned cur;
8946 	BUG_ON(offset > ring->buf_mask);
8947 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
8948 
8949 	cur = (ring->wptr - 1) & ring->buf_mask;
8950 	if (likely(cur > offset))
8951 		ring->ring[offset] = cur - offset;
8952 	else
8953 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8954 }
8955 
8956 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8957 {
8958 	int i, r = 0;
8959 	struct amdgpu_device *adev = ring->adev;
8960 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8961 	struct amdgpu_ring *kiq_ring = &kiq->ring;
8962 	unsigned long flags;
8963 
8964 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8965 		return -EINVAL;
8966 
8967 	spin_lock_irqsave(&kiq->ring_lock, flags);
8968 
8969 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8970 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
8971 		return -ENOMEM;
8972 	}
8973 
8974 	/* assert preemption condition */
8975 	amdgpu_ring_set_preempt_cond_exec(ring, false);
8976 
8977 	/* assert IB preemption, emit the trailing fence */
8978 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8979 				   ring->trail_fence_gpu_addr,
8980 				   ++ring->trail_seq);
8981 	amdgpu_ring_commit(kiq_ring);
8982 
8983 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
8984 
8985 	/* poll the trailing fence */
8986 	for (i = 0; i < adev->usec_timeout; i++) {
8987 		if (ring->trail_seq ==
8988 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8989 			break;
8990 		udelay(1);
8991 	}
8992 
8993 	if (i >= adev->usec_timeout) {
8994 		r = -EINVAL;
8995 		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8996 	}
8997 
8998 	/* deassert preemption condition */
8999 	amdgpu_ring_set_preempt_cond_exec(ring, true);
9000 	return r;
9001 }
9002 
9003 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
9004 {
9005 	struct amdgpu_device *adev = ring->adev;
9006 	struct v10_ce_ib_state ce_payload = {0};
9007 	uint64_t offset, ce_payload_gpu_addr;
9008 	void *ce_payload_cpu_addr;
9009 	int cnt;
9010 
9011 	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
9012 
9013 	if (ring->is_mes_queue) {
9014 		offset = offsetof(struct amdgpu_mes_ctx_meta_data,
9015 				  gfx[0].gfx_meta_data) +
9016 			offsetof(struct v10_gfx_meta_data, ce_payload);
9017 		ce_payload_gpu_addr =
9018 			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
9019 		ce_payload_cpu_addr =
9020 			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
9021 	} else {
9022 		offset = offsetof(struct v10_gfx_meta_data, ce_payload);
9023 		ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
9024 		ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
9025 	}
9026 
9027 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
9028 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
9029 				 WRITE_DATA_DST_SEL(8) |
9030 				 WR_CONFIRM) |
9031 				 WRITE_DATA_CACHE_POLICY(0));
9032 	amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
9033 	amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
9034 
9035 	if (resume)
9036 		amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
9037 					   sizeof(ce_payload) >> 2);
9038 	else
9039 		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
9040 					   sizeof(ce_payload) >> 2);
9041 }
9042 
9043 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
9044 {
9045 	struct amdgpu_device *adev = ring->adev;
9046 	struct v10_de_ib_state de_payload = {0};
9047 	uint64_t offset, gds_addr, de_payload_gpu_addr;
9048 	void *de_payload_cpu_addr;
9049 	int cnt;
9050 
9051 	if (ring->is_mes_queue) {
9052 		offset = offsetof(struct amdgpu_mes_ctx_meta_data,
9053 				  gfx[0].gfx_meta_data) +
9054 			offsetof(struct v10_gfx_meta_data, de_payload);
9055 		de_payload_gpu_addr =
9056 			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
9057 		de_payload_cpu_addr =
9058 			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
9059 
9060 		offset = offsetof(struct amdgpu_mes_ctx_meta_data,
9061 				  gfx[0].gds_backup) +
9062 			offsetof(struct v10_gfx_meta_data, de_payload);
9063 		gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
9064 	} else {
9065 		offset = offsetof(struct v10_gfx_meta_data, de_payload);
9066 		de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
9067 		de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
9068 
9069 		gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
9070 				 AMDGPU_CSA_SIZE - adev->gds.gds_size,
9071 				 PAGE_SIZE);
9072 	}
9073 
9074 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
9075 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
9076 
9077 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
9078 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
9079 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
9080 				 WRITE_DATA_DST_SEL(8) |
9081 				 WR_CONFIRM) |
9082 				 WRITE_DATA_CACHE_POLICY(0));
9083 	amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
9084 	amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
9085 
9086 	if (resume)
9087 		amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
9088 					   sizeof(de_payload) >> 2);
9089 	else
9090 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
9091 					   sizeof(de_payload) >> 2);
9092 }
9093 
9094 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
9095 				    bool secure)
9096 {
9097 	uint32_t v = secure ? FRAME_TMZ : 0;
9098 
9099 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
9100 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
9101 }
9102 
9103 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
9104 				     uint32_t reg_val_offs)
9105 {
9106 	struct amdgpu_device *adev = ring->adev;
9107 
9108 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
9109 	amdgpu_ring_write(ring, 0 |	/* src: register*/
9110 				(5 << 8) |	/* dst: memory */
9111 				(1 << 20));	/* write confirm */
9112 	amdgpu_ring_write(ring, reg);
9113 	amdgpu_ring_write(ring, 0);
9114 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
9115 				reg_val_offs * 4));
9116 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
9117 				reg_val_offs * 4));
9118 }
9119 
9120 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
9121 				   uint32_t val)
9122 {
9123 	uint32_t cmd = 0;
9124 
9125 	switch (ring->funcs->type) {
9126 	case AMDGPU_RING_TYPE_GFX:
9127 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
9128 		break;
9129 	case AMDGPU_RING_TYPE_KIQ:
9130 		cmd = (1 << 16); /* no inc addr */
9131 		break;
9132 	default:
9133 		cmd = WR_CONFIRM;
9134 		break;
9135 	}
9136 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
9137 	amdgpu_ring_write(ring, cmd);
9138 	amdgpu_ring_write(ring, reg);
9139 	amdgpu_ring_write(ring, 0);
9140 	amdgpu_ring_write(ring, val);
9141 }
9142 
9143 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
9144 					uint32_t val, uint32_t mask)
9145 {
9146 	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
9147 }
9148 
9149 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
9150 						   uint32_t reg0, uint32_t reg1,
9151 						   uint32_t ref, uint32_t mask)
9152 {
9153 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
9154 	struct amdgpu_device *adev = ring->adev;
9155 	bool fw_version_ok = false;
9156 
9157 	fw_version_ok = adev->gfx.cp_fw_write_wait;
9158 
9159 	if (fw_version_ok)
9160 		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
9161 				       ref, mask, 0x20);
9162 	else
9163 		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
9164 							   ref, mask);
9165 }
9166 
9167 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
9168 					 unsigned vmid)
9169 {
9170 	struct amdgpu_device *adev = ring->adev;
9171 	uint32_t value = 0;
9172 
9173 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
9174 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9175 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9176 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9177 	WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9178 }
9179 
9180 static void
9181 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9182 				      uint32_t me, uint32_t pipe,
9183 				      enum amdgpu_interrupt_state state)
9184 {
9185 	uint32_t cp_int_cntl, cp_int_cntl_reg;
9186 
9187 	if (!me) {
9188 		switch (pipe) {
9189 		case 0:
9190 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9191 			break;
9192 		case 1:
9193 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9194 			break;
9195 		default:
9196 			DRM_DEBUG("invalid pipe %d\n", pipe);
9197 			return;
9198 		}
9199 	} else {
9200 		DRM_DEBUG("invalid me %d\n", me);
9201 		return;
9202 	}
9203 
9204 	switch (state) {
9205 	case AMDGPU_IRQ_STATE_DISABLE:
9206 		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9207 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9208 					    TIME_STAMP_INT_ENABLE, 0);
9209 		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9210 		break;
9211 	case AMDGPU_IRQ_STATE_ENABLE:
9212 		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9213 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9214 					    TIME_STAMP_INT_ENABLE, 1);
9215 		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9216 		break;
9217 	default:
9218 		break;
9219 	}
9220 }
9221 
9222 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9223 						     int me, int pipe,
9224 						     enum amdgpu_interrupt_state state)
9225 {
9226 	u32 mec_int_cntl, mec_int_cntl_reg;
9227 
9228 	/*
9229 	 * amdgpu controls only the first MEC. That's why this function only
9230 	 * handles the setting of interrupts for this specific MEC. All other
9231 	 * pipes' interrupts are set by amdkfd.
9232 	 */
9233 
9234 	if (me == 1) {
9235 		switch (pipe) {
9236 		case 0:
9237 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9238 			break;
9239 		case 1:
9240 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9241 			break;
9242 		case 2:
9243 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9244 			break;
9245 		case 3:
9246 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9247 			break;
9248 		default:
9249 			DRM_DEBUG("invalid pipe %d\n", pipe);
9250 			return;
9251 		}
9252 	} else {
9253 		DRM_DEBUG("invalid me %d\n", me);
9254 		return;
9255 	}
9256 
9257 	switch (state) {
9258 	case AMDGPU_IRQ_STATE_DISABLE:
9259 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9260 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9261 					     TIME_STAMP_INT_ENABLE, 0);
9262 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9263 		break;
9264 	case AMDGPU_IRQ_STATE_ENABLE:
9265 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9266 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9267 					     TIME_STAMP_INT_ENABLE, 1);
9268 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9269 		break;
9270 	default:
9271 		break;
9272 	}
9273 }
9274 
9275 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9276 					    struct amdgpu_irq_src *src,
9277 					    unsigned type,
9278 					    enum amdgpu_interrupt_state state)
9279 {
9280 	switch (type) {
9281 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9282 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9283 		break;
9284 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9285 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9286 		break;
9287 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9288 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9289 		break;
9290 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9291 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9292 		break;
9293 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9294 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9295 		break;
9296 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9297 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9298 		break;
9299 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9300 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9301 		break;
9302 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9303 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9304 		break;
9305 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9306 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9307 		break;
9308 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9309 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9310 		break;
9311 	default:
9312 		break;
9313 	}
9314 	return 0;
9315 }
9316 
9317 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9318 			     struct amdgpu_irq_src *source,
9319 			     struct amdgpu_iv_entry *entry)
9320 {
9321 	int i;
9322 	u8 me_id, pipe_id, queue_id;
9323 	struct amdgpu_ring *ring;
9324 	uint32_t mes_queue_id = entry->src_data[0];
9325 
9326 	DRM_DEBUG("IH: CP EOP\n");
9327 
9328 	if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
9329 		struct amdgpu_mes_queue *queue;
9330 
9331 		mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
9332 
9333 		spin_lock(&adev->mes.queue_id_lock);
9334 		queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
9335 		if (queue) {
9336 			DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
9337 			amdgpu_fence_process(queue->ring);
9338 		}
9339 		spin_unlock(&adev->mes.queue_id_lock);
9340 	} else {
9341 		me_id = (entry->ring_id & 0x0c) >> 2;
9342 		pipe_id = (entry->ring_id & 0x03) >> 0;
9343 		queue_id = (entry->ring_id & 0x70) >> 4;
9344 
9345 		switch (me_id) {
9346 		case 0:
9347 			if (pipe_id == 0)
9348 				amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9349 			else
9350 				amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9351 			break;
9352 		case 1:
9353 		case 2:
9354 			for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9355 				ring = &adev->gfx.compute_ring[i];
9356 				/* Per-queue interrupt is supported for MEC starting from VI.
9357 				 * The interrupt can only be enabled/disabled per pipe instead
9358 				 * of per queue.
9359 				 */
9360 				if ((ring->me == me_id) &&
9361 				    (ring->pipe == pipe_id) &&
9362 				    (ring->queue == queue_id))
9363 					amdgpu_fence_process(ring);
9364 			}
9365 			break;
9366 		}
9367 	}
9368 
9369 	return 0;
9370 }
9371 
9372 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9373 					      struct amdgpu_irq_src *source,
9374 					      unsigned type,
9375 					      enum amdgpu_interrupt_state state)
9376 {
9377 	switch (state) {
9378 	case AMDGPU_IRQ_STATE_DISABLE:
9379 	case AMDGPU_IRQ_STATE_ENABLE:
9380 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9381 			       PRIV_REG_INT_ENABLE,
9382 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9383 		break;
9384 	default:
9385 		break;
9386 	}
9387 
9388 	return 0;
9389 }
9390 
9391 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9392 					       struct amdgpu_irq_src *source,
9393 					       unsigned type,
9394 					       enum amdgpu_interrupt_state state)
9395 {
9396 	switch (state) {
9397 	case AMDGPU_IRQ_STATE_DISABLE:
9398 	case AMDGPU_IRQ_STATE_ENABLE:
9399 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9400 			       PRIV_INSTR_INT_ENABLE,
9401 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9402 		break;
9403 	default:
9404 		break;
9405 	}
9406 
9407 	return 0;
9408 }
9409 
9410 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9411 					struct amdgpu_iv_entry *entry)
9412 {
9413 	u8 me_id, pipe_id, queue_id;
9414 	struct amdgpu_ring *ring;
9415 	int i;
9416 
9417 	me_id = (entry->ring_id & 0x0c) >> 2;
9418 	pipe_id = (entry->ring_id & 0x03) >> 0;
9419 	queue_id = (entry->ring_id & 0x70) >> 4;
9420 
9421 	switch (me_id) {
9422 	case 0:
9423 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9424 			ring = &adev->gfx.gfx_ring[i];
9425 			/* we only enabled 1 gfx queue per pipe for now */
9426 			if (ring->me == me_id && ring->pipe == pipe_id)
9427 				drm_sched_fault(&ring->sched);
9428 		}
9429 		break;
9430 	case 1:
9431 	case 2:
9432 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9433 			ring = &adev->gfx.compute_ring[i];
9434 			if (ring->me == me_id && ring->pipe == pipe_id &&
9435 			    ring->queue == queue_id)
9436 				drm_sched_fault(&ring->sched);
9437 		}
9438 		break;
9439 	default:
9440 		BUG();
9441 	}
9442 }
9443 
9444 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9445 				  struct amdgpu_irq_src *source,
9446 				  struct amdgpu_iv_entry *entry)
9447 {
9448 	DRM_ERROR("Illegal register access in command stream\n");
9449 	gfx_v10_0_handle_priv_fault(adev, entry);
9450 	return 0;
9451 }
9452 
9453 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9454 				   struct amdgpu_irq_src *source,
9455 				   struct amdgpu_iv_entry *entry)
9456 {
9457 	DRM_ERROR("Illegal instruction in command stream\n");
9458 	gfx_v10_0_handle_priv_fault(adev, entry);
9459 	return 0;
9460 }
9461 
9462 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9463 					     struct amdgpu_irq_src *src,
9464 					     unsigned int type,
9465 					     enum amdgpu_interrupt_state state)
9466 {
9467 	uint32_t tmp, target;
9468 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9469 
9470 	if (ring->me == 1)
9471 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9472 	else
9473 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9474 	target += ring->pipe;
9475 
9476 	switch (type) {
9477 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9478 		if (state == AMDGPU_IRQ_STATE_DISABLE) {
9479 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9480 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9481 					    GENERIC2_INT_ENABLE, 0);
9482 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9483 
9484 			tmp = RREG32_SOC15_IP(GC, target);
9485 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9486 					    GENERIC2_INT_ENABLE, 0);
9487 			WREG32_SOC15_IP(GC, target, tmp);
9488 		} else {
9489 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9490 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9491 					    GENERIC2_INT_ENABLE, 1);
9492 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9493 
9494 			tmp = RREG32_SOC15_IP(GC, target);
9495 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9496 					    GENERIC2_INT_ENABLE, 1);
9497 			WREG32_SOC15_IP(GC, target, tmp);
9498 		}
9499 		break;
9500 	default:
9501 		BUG(); /* kiq only support GENERIC2_INT now */
9502 		break;
9503 	}
9504 	return 0;
9505 }
9506 
9507 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9508 			     struct amdgpu_irq_src *source,
9509 			     struct amdgpu_iv_entry *entry)
9510 {
9511 	u8 me_id, pipe_id, queue_id;
9512 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9513 
9514 	me_id = (entry->ring_id & 0x0c) >> 2;
9515 	pipe_id = (entry->ring_id & 0x03) >> 0;
9516 	queue_id = (entry->ring_id & 0x70) >> 4;
9517 	DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9518 		   me_id, pipe_id, queue_id);
9519 
9520 	amdgpu_fence_process(ring);
9521 	return 0;
9522 }
9523 
9524 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9525 {
9526 	const unsigned int gcr_cntl =
9527 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9528 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9529 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9530 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9531 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9532 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9533 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9534 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9535 
9536 	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9537 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9538 	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9539 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9540 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9541 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9542 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9543 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9544 	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9545 }
9546 
9547 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9548 	.name = "gfx_v10_0",
9549 	.early_init = gfx_v10_0_early_init,
9550 	.late_init = gfx_v10_0_late_init,
9551 	.sw_init = gfx_v10_0_sw_init,
9552 	.sw_fini = gfx_v10_0_sw_fini,
9553 	.hw_init = gfx_v10_0_hw_init,
9554 	.hw_fini = gfx_v10_0_hw_fini,
9555 	.suspend = gfx_v10_0_suspend,
9556 	.resume = gfx_v10_0_resume,
9557 	.is_idle = gfx_v10_0_is_idle,
9558 	.wait_for_idle = gfx_v10_0_wait_for_idle,
9559 	.soft_reset = gfx_v10_0_soft_reset,
9560 	.set_clockgating_state = gfx_v10_0_set_clockgating_state,
9561 	.set_powergating_state = gfx_v10_0_set_powergating_state,
9562 	.get_clockgating_state = gfx_v10_0_get_clockgating_state,
9563 };
9564 
9565 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9566 	.type = AMDGPU_RING_TYPE_GFX,
9567 	.align_mask = 0xff,
9568 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9569 	.support_64bit_ptrs = true,
9570 	.secure_submission_supported = true,
9571 	.vmhub = AMDGPU_GFXHUB_0,
9572 	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9573 	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9574 	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9575 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
9576 		5 + /* COND_EXEC */
9577 		7 + /* PIPELINE_SYNC */
9578 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9579 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9580 		2 + /* VM_FLUSH */
9581 		8 + /* FENCE for VM_FLUSH */
9582 		20 + /* GDS switch */
9583 		4 + /* double SWITCH_BUFFER,
9584 		     * the first COND_EXEC jump to the place
9585 		     * just prior to this double SWITCH_BUFFER
9586 		     */
9587 		5 + /* COND_EXEC */
9588 		7 + /* HDP_flush */
9589 		4 + /* VGT_flush */
9590 		14 + /*	CE_META */
9591 		31 + /*	DE_META */
9592 		3 + /* CNTX_CTRL */
9593 		5 + /* HDP_INVL */
9594 		8 + 8 + /* FENCE x2 */
9595 		2 + /* SWITCH_BUFFER */
9596 		8, /* gfx_v10_0_emit_mem_sync */
9597 	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
9598 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9599 	.emit_fence = gfx_v10_0_ring_emit_fence,
9600 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9601 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9602 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9603 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9604 	.test_ring = gfx_v10_0_ring_test_ring,
9605 	.test_ib = gfx_v10_0_ring_test_ib,
9606 	.insert_nop = amdgpu_ring_insert_nop,
9607 	.pad_ib = amdgpu_ring_generic_pad_ib,
9608 	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9609 	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9610 	.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9611 	.patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9612 	.preempt_ib = gfx_v10_0_ring_preempt_ib,
9613 	.emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9614 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9615 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9616 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9617 	.soft_recovery = gfx_v10_0_ring_soft_recovery,
9618 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
9619 };
9620 
9621 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9622 	.type = AMDGPU_RING_TYPE_COMPUTE,
9623 	.align_mask = 0xff,
9624 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9625 	.support_64bit_ptrs = true,
9626 	.vmhub = AMDGPU_GFXHUB_0,
9627 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
9628 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
9629 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
9630 	.emit_frame_size =
9631 		20 + /* gfx_v10_0_ring_emit_gds_switch */
9632 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
9633 		5 + /* hdp invalidate */
9634 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9635 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9636 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9637 		2 + /* gfx_v10_0_ring_emit_vm_flush */
9638 		8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9639 		8, /* gfx_v10_0_emit_mem_sync */
9640 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
9641 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
9642 	.emit_fence = gfx_v10_0_ring_emit_fence,
9643 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9644 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9645 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9646 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9647 	.test_ring = gfx_v10_0_ring_test_ring,
9648 	.test_ib = gfx_v10_0_ring_test_ib,
9649 	.insert_nop = amdgpu_ring_insert_nop,
9650 	.pad_ib = amdgpu_ring_generic_pad_ib,
9651 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9652 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9653 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9654 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
9655 };
9656 
9657 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9658 	.type = AMDGPU_RING_TYPE_KIQ,
9659 	.align_mask = 0xff,
9660 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
9661 	.support_64bit_ptrs = true,
9662 	.vmhub = AMDGPU_GFXHUB_0,
9663 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
9664 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
9665 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
9666 	.emit_frame_size =
9667 		20 + /* gfx_v10_0_ring_emit_gds_switch */
9668 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
9669 		5 + /*hdp invalidate */
9670 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9671 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9672 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9673 		2 + /* gfx_v10_0_ring_emit_vm_flush */
9674 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9675 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
9676 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
9677 	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9678 	.test_ring = gfx_v10_0_ring_test_ring,
9679 	.test_ib = gfx_v10_0_ring_test_ib,
9680 	.insert_nop = amdgpu_ring_insert_nop,
9681 	.pad_ib = amdgpu_ring_generic_pad_ib,
9682 	.emit_rreg = gfx_v10_0_ring_emit_rreg,
9683 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
9684 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9685 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9686 };
9687 
9688 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9689 {
9690 	int i;
9691 
9692 	adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9693 
9694 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9695 		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9696 
9697 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
9698 		adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9699 }
9700 
9701 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9702 	.set = gfx_v10_0_set_eop_interrupt_state,
9703 	.process = gfx_v10_0_eop_irq,
9704 };
9705 
9706 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9707 	.set = gfx_v10_0_set_priv_reg_fault_state,
9708 	.process = gfx_v10_0_priv_reg_irq,
9709 };
9710 
9711 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9712 	.set = gfx_v10_0_set_priv_inst_fault_state,
9713 	.process = gfx_v10_0_priv_inst_irq,
9714 };
9715 
9716 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9717 	.set = gfx_v10_0_kiq_set_interrupt_state,
9718 	.process = gfx_v10_0_kiq_irq,
9719 };
9720 
9721 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9722 {
9723 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9724 	adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9725 
9726 	adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9727 	adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9728 
9729 	adev->gfx.priv_reg_irq.num_types = 1;
9730 	adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9731 
9732 	adev->gfx.priv_inst_irq.num_types = 1;
9733 	adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9734 }
9735 
9736 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9737 {
9738 	switch (adev->ip_versions[GC_HWIP][0]) {
9739 	case IP_VERSION(10, 1, 10):
9740 	case IP_VERSION(10, 1, 1):
9741 	case IP_VERSION(10, 1, 3):
9742 	case IP_VERSION(10, 1, 4):
9743 	case IP_VERSION(10, 3, 2):
9744 	case IP_VERSION(10, 3, 1):
9745 	case IP_VERSION(10, 3, 4):
9746 	case IP_VERSION(10, 3, 5):
9747 	case IP_VERSION(10, 3, 6):
9748 	case IP_VERSION(10, 3, 3):
9749 	case IP_VERSION(10, 3, 7):
9750 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9751 		break;
9752 	case IP_VERSION(10, 1, 2):
9753 	case IP_VERSION(10, 3, 0):
9754 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9755 		break;
9756 	default:
9757 		break;
9758 	}
9759 }
9760 
9761 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9762 {
9763 	unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9764 			    adev->gfx.config.max_sh_per_se *
9765 			    adev->gfx.config.max_shader_engines;
9766 
9767 	adev->gds.gds_size = 0x10000;
9768 	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9769 	adev->gds.gws_size = 64;
9770 	adev->gds.oa_size = 16;
9771 }
9772 
9773 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9774 {
9775 	/* set gfx eng mqd */
9776 	adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9777 		sizeof(struct v10_gfx_mqd);
9778 	adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9779 		gfx_v10_0_gfx_mqd_init;
9780 	/* set compute eng mqd */
9781 	adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9782 		sizeof(struct v10_compute_mqd);
9783 	adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9784 		gfx_v10_0_compute_mqd_init;
9785 }
9786 
9787 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9788 							  u32 bitmap)
9789 {
9790 	u32 data;
9791 
9792 	if (!bitmap)
9793 		return;
9794 
9795 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9796 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9797 
9798 	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9799 }
9800 
9801 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9802 {
9803 	u32 disabled_mask =
9804 		~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9805 	u32 efuse_setting = 0;
9806 	u32 vbios_setting = 0;
9807 
9808 	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9809 	efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9810 	efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9811 
9812 	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9813 	vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9814 	vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9815 
9816 	disabled_mask |= efuse_setting | vbios_setting;
9817 
9818 	return (~disabled_mask);
9819 }
9820 
9821 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9822 {
9823 	u32 wgp_idx, wgp_active_bitmap;
9824 	u32 cu_bitmap_per_wgp, cu_active_bitmap;
9825 
9826 	wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9827 	cu_active_bitmap = 0;
9828 
9829 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9830 		/* if there is one WGP enabled, it means 2 CUs will be enabled */
9831 		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9832 		if (wgp_active_bitmap & (1 << wgp_idx))
9833 			cu_active_bitmap |= cu_bitmap_per_wgp;
9834 	}
9835 
9836 	return cu_active_bitmap;
9837 }
9838 
9839 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9840 				 struct amdgpu_cu_info *cu_info)
9841 {
9842 	int i, j, k, counter, active_cu_number = 0;
9843 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9844 	unsigned disable_masks[4 * 2];
9845 
9846 	if (!adev || !cu_info)
9847 		return -EINVAL;
9848 
9849 	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9850 
9851 	mutex_lock(&adev->grbm_idx_mutex);
9852 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9853 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9854 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
9855 			if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
9856 			     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
9857 			     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
9858 			     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
9859 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9860 				continue;
9861 			mask = 1;
9862 			ao_bitmap = 0;
9863 			counter = 0;
9864 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9865 			if (i < 4 && j < 2)
9866 				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9867 					adev, disable_masks[i * 2 + j]);
9868 			bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9869 			cu_info->bitmap[i][j] = bitmap;
9870 
9871 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9872 				if (bitmap & mask) {
9873 					if (counter < adev->gfx.config.max_cu_per_sh)
9874 						ao_bitmap |= mask;
9875 					counter++;
9876 				}
9877 				mask <<= 1;
9878 			}
9879 			active_cu_number += counter;
9880 			if (i < 2 && j < 2)
9881 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9882 			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9883 		}
9884 	}
9885 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9886 	mutex_unlock(&adev->grbm_idx_mutex);
9887 
9888 	cu_info->number = active_cu_number;
9889 	cu_info->ao_cu_mask = ao_cu_mask;
9890 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9891 
9892 	return 0;
9893 }
9894 
9895 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9896 {
9897 	uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9898 
9899 	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9900 	efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9901 	efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9902 
9903 	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9904 	vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9905 	vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9906 
9907 	max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9908 						adev->gfx.config.max_shader_engines);
9909 	disabled_sa = efuse_setting | vbios_setting;
9910 	disabled_sa &= max_sa_mask;
9911 
9912 	return disabled_sa;
9913 }
9914 
9915 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9916 {
9917 	uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9918 	uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9919 
9920 	disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9921 
9922 	max_sa_per_se = adev->gfx.config.max_sh_per_se;
9923 	max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9924 	max_shader_engines = adev->gfx.config.max_shader_engines;
9925 
9926 	for (se_index = 0; max_shader_engines > se_index; se_index++) {
9927 		disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9928 		disabled_sa_per_se &= max_sa_per_se_mask;
9929 		if (disabled_sa_per_se == max_sa_per_se_mask) {
9930 			WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9931 			break;
9932 		}
9933 	}
9934 }
9935 
9936 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9937 {
9938 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9939 		     (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9940 		     (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9941 		     (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9942 
9943 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9944 	WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9945 		     (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9946 		     (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9947 		     (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9948 		     (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9949 
9950 	WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9951 		     (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9952 		     (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9953 		     (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9954 
9955 	WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9956 
9957 	WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9958 		     (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9959 }
9960 
9961 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9962 {
9963 	.type = AMD_IP_BLOCK_TYPE_GFX,
9964 	.major = 10,
9965 	.minor = 0,
9966 	.rev = 0,
9967 	.funcs = &gfx_v10_0_ip_funcs,
9968 };
9969