1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "amdgpu_psp.h" 28 #include "amdgpu_smu.h" 29 #include "nv.h" 30 #include "nvd.h" 31 32 #include "gc/gc_10_1_0_offset.h" 33 #include "gc/gc_10_1_0_sh_mask.h" 34 #include "navi10_enum.h" 35 #include "hdp/hdp_5_0_0_offset.h" 36 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 37 38 #include "soc15.h" 39 #include "soc15_common.h" 40 #include "clearstate_gfx10.h" 41 #include "v10_structs.h" 42 #include "gfx_v10_0.h" 43 #include "nbio_v2_3.h" 44 45 /** 46 * Navi10 has two graphic rings to share each graphic pipe. 47 * 1. Primary ring 48 * 2. Async ring 49 * 50 * In bring-up phase, it just used primary ring so set gfx ring number as 1 at 51 * first. 52 */ 53 #define GFX10_NUM_GFX_RINGS 2 54 #define GFX10_MEC_HPD_SIZE 2048 55 56 #define F32_CE_PROGRAM_RAM_SIZE 65536 57 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 58 59 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 60 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 61 62 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 63 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 64 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 65 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 66 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 67 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 68 69 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 70 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 71 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 72 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 73 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 74 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 75 76 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 77 { 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100), 81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 115 }; 116 117 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 118 { 119 /* Pending on emulation bring up */ 120 }; 121 122 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 123 { 124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000043), 142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000), 160 }; 161 162 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 163 { 164 /* Pending on emulation bring up */ 165 }; 166 167 #define DEFAULT_SH_MEM_CONFIG \ 168 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 169 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 170 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 171 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 172 173 174 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 175 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 176 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 177 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 178 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 179 struct amdgpu_cu_info *cu_info); 180 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 181 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 182 u32 sh_num, u32 instance); 183 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 184 185 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 186 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 187 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 188 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 189 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 190 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 191 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start); 192 193 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 194 { 195 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 196 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 197 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 198 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 199 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 200 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 201 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 202 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 203 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 204 } 205 206 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 207 struct amdgpu_ring *ring) 208 { 209 struct amdgpu_device *adev = kiq_ring->adev; 210 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 211 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 212 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 213 214 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 215 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 216 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 217 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 218 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 219 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 220 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 221 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 222 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 223 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 224 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 225 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 226 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 227 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 228 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 229 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 230 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 231 } 232 233 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 234 struct amdgpu_ring *ring, 235 enum amdgpu_unmap_queues_action action, 236 u64 gpu_addr, u64 seq) 237 { 238 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 239 240 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 241 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 242 PACKET3_UNMAP_QUEUES_ACTION(action) | 243 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 244 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 245 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 246 amdgpu_ring_write(kiq_ring, 247 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 248 249 if (action == PREEMPT_QUEUES_NO_UNMAP) { 250 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 251 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 252 amdgpu_ring_write(kiq_ring, seq); 253 } else { 254 amdgpu_ring_write(kiq_ring, 0); 255 amdgpu_ring_write(kiq_ring, 0); 256 amdgpu_ring_write(kiq_ring, 0); 257 } 258 } 259 260 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 261 struct amdgpu_ring *ring, 262 u64 addr, 263 u64 seq) 264 { 265 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 266 267 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 268 amdgpu_ring_write(kiq_ring, 269 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 270 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 271 PACKET3_QUERY_STATUS_COMMAND(2)); 272 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 273 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 274 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 275 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 276 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 277 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 278 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 279 } 280 281 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 282 .kiq_set_resources = gfx10_kiq_set_resources, 283 .kiq_map_queues = gfx10_kiq_map_queues, 284 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 285 .kiq_query_status = gfx10_kiq_query_status, 286 .set_resources_size = 8, 287 .map_queues_size = 7, 288 .unmap_queues_size = 6, 289 .query_status_size = 7, 290 }; 291 292 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 293 { 294 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 295 } 296 297 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 298 { 299 switch (adev->asic_type) { 300 case CHIP_NAVI10: 301 soc15_program_register_sequence(adev, 302 golden_settings_gc_10_1, 303 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 304 soc15_program_register_sequence(adev, 305 golden_settings_gc_10_0_nv10, 306 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 307 break; 308 case CHIP_NAVI14: 309 soc15_program_register_sequence(adev, 310 golden_settings_gc_10_1_1, 311 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 312 soc15_program_register_sequence(adev, 313 golden_settings_gc_10_1_nv14, 314 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 315 break; 316 default: 317 break; 318 } 319 } 320 321 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 322 { 323 adev->gfx.scratch.num_reg = 8; 324 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 325 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 326 } 327 328 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 329 bool wc, uint32_t reg, uint32_t val) 330 { 331 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 332 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 333 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 334 amdgpu_ring_write(ring, reg); 335 amdgpu_ring_write(ring, 0); 336 amdgpu_ring_write(ring, val); 337 } 338 339 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 340 int mem_space, int opt, uint32_t addr0, 341 uint32_t addr1, uint32_t ref, uint32_t mask, 342 uint32_t inv) 343 { 344 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 345 amdgpu_ring_write(ring, 346 /* memory (1) or register (0) */ 347 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 348 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 349 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 350 WAIT_REG_MEM_ENGINE(eng_sel))); 351 352 if (mem_space) 353 BUG_ON(addr0 & 0x3); /* Dword align */ 354 amdgpu_ring_write(ring, addr0); 355 amdgpu_ring_write(ring, addr1); 356 amdgpu_ring_write(ring, ref); 357 amdgpu_ring_write(ring, mask); 358 amdgpu_ring_write(ring, inv); /* poll interval */ 359 } 360 361 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 362 { 363 struct amdgpu_device *adev = ring->adev; 364 uint32_t scratch; 365 uint32_t tmp = 0; 366 unsigned i; 367 int r; 368 369 r = amdgpu_gfx_scratch_get(adev, &scratch); 370 if (r) { 371 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 372 return r; 373 } 374 375 WREG32(scratch, 0xCAFEDEAD); 376 377 r = amdgpu_ring_alloc(ring, 3); 378 if (r) { 379 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 380 ring->idx, r); 381 amdgpu_gfx_scratch_free(adev, scratch); 382 return r; 383 } 384 385 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 386 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 387 amdgpu_ring_write(ring, 0xDEADBEEF); 388 amdgpu_ring_commit(ring); 389 390 for (i = 0; i < adev->usec_timeout; i++) { 391 tmp = RREG32(scratch); 392 if (tmp == 0xDEADBEEF) 393 break; 394 if (amdgpu_emu_mode == 1) 395 msleep(1); 396 else 397 DRM_UDELAY(1); 398 } 399 if (i < adev->usec_timeout) { 400 if (amdgpu_emu_mode == 1) 401 DRM_INFO("ring test on %d succeeded in %d msecs\n", 402 ring->idx, i); 403 else 404 DRM_INFO("ring test on %d succeeded in %d usecs\n", 405 ring->idx, i); 406 } else { 407 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 408 ring->idx, scratch, tmp); 409 r = -EINVAL; 410 } 411 amdgpu_gfx_scratch_free(adev, scratch); 412 413 return r; 414 } 415 416 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 417 { 418 struct amdgpu_device *adev = ring->adev; 419 struct amdgpu_ib ib; 420 struct dma_fence *f = NULL; 421 uint32_t scratch; 422 uint32_t tmp = 0; 423 long r; 424 425 r = amdgpu_gfx_scratch_get(adev, &scratch); 426 if (r) { 427 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 428 return r; 429 } 430 431 WREG32(scratch, 0xCAFEDEAD); 432 433 memset(&ib, 0, sizeof(ib)); 434 r = amdgpu_ib_get(adev, NULL, 256, &ib); 435 if (r) { 436 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 437 goto err1; 438 } 439 440 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 441 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 442 ib.ptr[2] = 0xDEADBEEF; 443 ib.length_dw = 3; 444 445 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 446 if (r) 447 goto err2; 448 449 r = dma_fence_wait_timeout(f, false, timeout); 450 if (r == 0) { 451 DRM_ERROR("amdgpu: IB test timed out.\n"); 452 r = -ETIMEDOUT; 453 goto err2; 454 } else if (r < 0) { 455 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 456 goto err2; 457 } 458 459 tmp = RREG32(scratch); 460 if (tmp == 0xDEADBEEF) { 461 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 462 r = 0; 463 } else { 464 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 465 scratch, tmp); 466 r = -EINVAL; 467 } 468 err2: 469 amdgpu_ib_free(adev, &ib, NULL); 470 dma_fence_put(f); 471 err1: 472 amdgpu_gfx_scratch_free(adev, scratch); 473 474 return r; 475 } 476 477 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 478 { 479 release_firmware(adev->gfx.pfp_fw); 480 adev->gfx.pfp_fw = NULL; 481 release_firmware(adev->gfx.me_fw); 482 adev->gfx.me_fw = NULL; 483 release_firmware(adev->gfx.ce_fw); 484 adev->gfx.ce_fw = NULL; 485 release_firmware(adev->gfx.rlc_fw); 486 adev->gfx.rlc_fw = NULL; 487 release_firmware(adev->gfx.mec_fw); 488 adev->gfx.mec_fw = NULL; 489 release_firmware(adev->gfx.mec2_fw); 490 adev->gfx.mec2_fw = NULL; 491 492 kfree(adev->gfx.rlc.register_list_format); 493 } 494 495 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 496 { 497 const struct rlc_firmware_header_v2_1 *rlc_hdr; 498 499 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 500 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 501 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 502 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 503 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 504 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 505 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 506 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 507 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 508 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 509 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 510 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 511 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 512 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 513 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 514 } 515 516 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 517 { 518 switch (adev->asic_type) { 519 case CHIP_NAVI10: 520 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 521 break; 522 default: 523 break; 524 } 525 } 526 527 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 528 { 529 const char *chip_name; 530 char fw_name[30]; 531 int err; 532 struct amdgpu_firmware_info *info = NULL; 533 const struct common_firmware_header *header = NULL; 534 const struct gfx_firmware_header_v1_0 *cp_hdr; 535 const struct rlc_firmware_header_v2_0 *rlc_hdr; 536 unsigned int *tmp = NULL; 537 unsigned int i = 0; 538 uint16_t version_major; 539 uint16_t version_minor; 540 541 DRM_DEBUG("\n"); 542 543 switch (adev->asic_type) { 544 case CHIP_NAVI10: 545 chip_name = "navi10"; 546 break; 547 case CHIP_NAVI14: 548 chip_name = "navi14"; 549 break; 550 default: 551 BUG(); 552 } 553 554 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 555 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 556 if (err) 557 goto out; 558 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 559 if (err) 560 goto out; 561 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 562 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 563 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 564 565 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 566 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 567 if (err) 568 goto out; 569 err = amdgpu_ucode_validate(adev->gfx.me_fw); 570 if (err) 571 goto out; 572 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 573 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 574 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 575 576 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 577 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 578 if (err) 579 goto out; 580 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 581 if (err) 582 goto out; 583 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 584 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 585 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 586 587 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 588 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 589 if (err) 590 goto out; 591 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 592 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 593 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 594 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 595 if (version_major == 2 && version_minor == 1) 596 adev->gfx.rlc.is_rlc_v2_1 = true; 597 598 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 599 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 600 adev->gfx.rlc.save_and_restore_offset = 601 le32_to_cpu(rlc_hdr->save_and_restore_offset); 602 adev->gfx.rlc.clear_state_descriptor_offset = 603 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 604 adev->gfx.rlc.avail_scratch_ram_locations = 605 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 606 adev->gfx.rlc.reg_restore_list_size = 607 le32_to_cpu(rlc_hdr->reg_restore_list_size); 608 adev->gfx.rlc.reg_list_format_start = 609 le32_to_cpu(rlc_hdr->reg_list_format_start); 610 adev->gfx.rlc.reg_list_format_separate_start = 611 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 612 adev->gfx.rlc.starting_offsets_start = 613 le32_to_cpu(rlc_hdr->starting_offsets_start); 614 adev->gfx.rlc.reg_list_format_size_bytes = 615 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 616 adev->gfx.rlc.reg_list_size_bytes = 617 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 618 adev->gfx.rlc.register_list_format = 619 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 620 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 621 if (!adev->gfx.rlc.register_list_format) { 622 err = -ENOMEM; 623 goto out; 624 } 625 626 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 627 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 628 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 629 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 630 631 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 632 633 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 634 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 635 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 636 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 637 638 if (adev->gfx.rlc.is_rlc_v2_1) 639 gfx_v10_0_init_rlc_ext_microcode(adev); 640 641 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 642 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 643 if (err) 644 goto out; 645 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 646 if (err) 647 goto out; 648 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 649 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 650 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 651 652 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 653 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 654 if (!err) { 655 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 656 if (err) 657 goto out; 658 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 659 adev->gfx.mec2_fw->data; 660 adev->gfx.mec2_fw_version = 661 le32_to_cpu(cp_hdr->header.ucode_version); 662 adev->gfx.mec2_feature_version = 663 le32_to_cpu(cp_hdr->ucode_feature_version); 664 } else { 665 err = 0; 666 adev->gfx.mec2_fw = NULL; 667 } 668 669 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 670 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 671 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 672 info->fw = adev->gfx.pfp_fw; 673 header = (const struct common_firmware_header *)info->fw->data; 674 adev->firmware.fw_size += 675 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 676 677 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 678 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 679 info->fw = adev->gfx.me_fw; 680 header = (const struct common_firmware_header *)info->fw->data; 681 adev->firmware.fw_size += 682 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 683 684 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 685 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 686 info->fw = adev->gfx.ce_fw; 687 header = (const struct common_firmware_header *)info->fw->data; 688 adev->firmware.fw_size += 689 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 690 691 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 692 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 693 info->fw = adev->gfx.rlc_fw; 694 header = (const struct common_firmware_header *)info->fw->data; 695 adev->firmware.fw_size += 696 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 697 698 if (adev->gfx.rlc.is_rlc_v2_1 && 699 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 700 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 701 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 702 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 703 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 704 info->fw = adev->gfx.rlc_fw; 705 adev->firmware.fw_size += 706 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 707 708 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 709 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 710 info->fw = adev->gfx.rlc_fw; 711 adev->firmware.fw_size += 712 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 713 714 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 715 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 716 info->fw = adev->gfx.rlc_fw; 717 adev->firmware.fw_size += 718 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 719 } 720 721 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 722 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 723 info->fw = adev->gfx.mec_fw; 724 header = (const struct common_firmware_header *)info->fw->data; 725 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 726 adev->firmware.fw_size += 727 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 728 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 729 730 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 731 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 732 info->fw = adev->gfx.mec_fw; 733 adev->firmware.fw_size += 734 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 735 736 if (adev->gfx.mec2_fw) { 737 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 738 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 739 info->fw = adev->gfx.mec2_fw; 740 header = (const struct common_firmware_header *)info->fw->data; 741 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 742 adev->firmware.fw_size += 743 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 744 le32_to_cpu(cp_hdr->jt_size) * 4, 745 PAGE_SIZE); 746 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 747 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 748 info->fw = adev->gfx.mec2_fw; 749 adev->firmware.fw_size += 750 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 751 PAGE_SIZE); 752 } 753 } 754 755 out: 756 if (err) { 757 dev_err(adev->dev, 758 "gfx10: Failed to load firmware \"%s\"\n", 759 fw_name); 760 release_firmware(adev->gfx.pfp_fw); 761 adev->gfx.pfp_fw = NULL; 762 release_firmware(adev->gfx.me_fw); 763 adev->gfx.me_fw = NULL; 764 release_firmware(adev->gfx.ce_fw); 765 adev->gfx.ce_fw = NULL; 766 release_firmware(adev->gfx.rlc_fw); 767 adev->gfx.rlc_fw = NULL; 768 release_firmware(adev->gfx.mec_fw); 769 adev->gfx.mec_fw = NULL; 770 release_firmware(adev->gfx.mec2_fw); 771 adev->gfx.mec2_fw = NULL; 772 } 773 774 gfx_v10_0_check_gfxoff_flag(adev); 775 776 return err; 777 } 778 779 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 780 { 781 u32 count = 0; 782 const struct cs_section_def *sect = NULL; 783 const struct cs_extent_def *ext = NULL; 784 785 /* begin clear state */ 786 count += 2; 787 /* context control state */ 788 count += 3; 789 790 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 791 for (ext = sect->section; ext->extent != NULL; ++ext) { 792 if (sect->id == SECT_CONTEXT) 793 count += 2 + ext->reg_count; 794 else 795 return 0; 796 } 797 } 798 799 /* set PA_SC_TILE_STEERING_OVERRIDE */ 800 count += 3; 801 /* end clear state */ 802 count += 2; 803 /* clear state */ 804 count += 2; 805 806 return count; 807 } 808 809 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 810 volatile u32 *buffer) 811 { 812 u32 count = 0, i; 813 const struct cs_section_def *sect = NULL; 814 const struct cs_extent_def *ext = NULL; 815 int ctx_reg_offset; 816 817 if (adev->gfx.rlc.cs_data == NULL) 818 return; 819 if (buffer == NULL) 820 return; 821 822 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 823 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 824 825 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 826 buffer[count++] = cpu_to_le32(0x80000000); 827 buffer[count++] = cpu_to_le32(0x80000000); 828 829 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 830 for (ext = sect->section; ext->extent != NULL; ++ext) { 831 if (sect->id == SECT_CONTEXT) { 832 buffer[count++] = 833 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 834 buffer[count++] = cpu_to_le32(ext->reg_index - 835 PACKET3_SET_CONTEXT_REG_START); 836 for (i = 0; i < ext->reg_count; i++) 837 buffer[count++] = cpu_to_le32(ext->extent[i]); 838 } else { 839 return; 840 } 841 } 842 } 843 844 ctx_reg_offset = 845 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 846 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 847 buffer[count++] = cpu_to_le32(ctx_reg_offset); 848 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 849 850 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 851 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 852 853 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 854 buffer[count++] = cpu_to_le32(0); 855 } 856 857 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 858 { 859 /* clear state block */ 860 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 861 &adev->gfx.rlc.clear_state_gpu_addr, 862 (void **)&adev->gfx.rlc.cs_ptr); 863 864 /* jump table block */ 865 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 866 &adev->gfx.rlc.cp_table_gpu_addr, 867 (void **)&adev->gfx.rlc.cp_table_ptr); 868 } 869 870 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 871 { 872 const struct cs_section_def *cs_data; 873 int r; 874 875 adev->gfx.rlc.cs_data = gfx10_cs_data; 876 877 cs_data = adev->gfx.rlc.cs_data; 878 879 if (cs_data) { 880 /* init clear state block */ 881 r = amdgpu_gfx_rlc_init_csb(adev); 882 if (r) 883 return r; 884 } 885 886 return 0; 887 } 888 889 static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev) 890 { 891 int r; 892 893 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 894 if (unlikely(r != 0)) 895 return r; 896 897 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, 898 AMDGPU_GEM_DOMAIN_VRAM); 899 if (!r) 900 adev->gfx.rlc.clear_state_gpu_addr = 901 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); 902 903 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 904 905 return r; 906 } 907 908 static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev) 909 { 910 int r; 911 912 if (!adev->gfx.rlc.clear_state_obj) 913 return; 914 915 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); 916 if (likely(r == 0)) { 917 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 918 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 919 } 920 } 921 922 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 923 { 924 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 925 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 926 } 927 928 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 929 { 930 int r; 931 932 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 933 934 amdgpu_gfx_graphics_queue_acquire(adev); 935 936 r = gfx_v10_0_init_microcode(adev); 937 if (r) 938 DRM_ERROR("Failed to load gfx firmware!\n"); 939 940 return r; 941 } 942 943 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 944 { 945 int r; 946 u32 *hpd; 947 const __le32 *fw_data = NULL; 948 unsigned fw_size; 949 u32 *fw = NULL; 950 size_t mec_hpd_size; 951 952 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 953 954 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 955 956 /* take ownership of the relevant compute queues */ 957 amdgpu_gfx_compute_queue_acquire(adev); 958 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 959 960 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 961 AMDGPU_GEM_DOMAIN_GTT, 962 &adev->gfx.mec.hpd_eop_obj, 963 &adev->gfx.mec.hpd_eop_gpu_addr, 964 (void **)&hpd); 965 if (r) { 966 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 967 gfx_v10_0_mec_fini(adev); 968 return r; 969 } 970 971 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 972 973 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 974 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 975 976 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 977 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 978 979 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 980 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 981 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 982 983 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 984 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 985 &adev->gfx.mec.mec_fw_obj, 986 &adev->gfx.mec.mec_fw_gpu_addr, 987 (void **)&fw); 988 if (r) { 989 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 990 gfx_v10_0_mec_fini(adev); 991 return r; 992 } 993 994 memcpy(fw, fw_data, fw_size); 995 996 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 997 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 998 } 999 1000 return 0; 1001 } 1002 1003 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1004 { 1005 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1006 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1007 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1008 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1009 } 1010 1011 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1012 uint32_t thread, uint32_t regno, 1013 uint32_t num, uint32_t *out) 1014 { 1015 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1016 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1017 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1018 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1019 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1020 while (num--) 1021 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1022 } 1023 1024 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1025 { 1026 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 1027 * field when performing a select_se_sh so it should be 1028 * zero here */ 1029 WARN_ON(simd != 0); 1030 1031 /* type 2 wave data */ 1032 dst[(*no_fields)++] = 2; 1033 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1034 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1035 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1036 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1037 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1038 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1039 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1040 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 1041 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1042 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1043 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1044 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1045 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1046 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1047 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1048 } 1049 1050 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1051 uint32_t wave, uint32_t start, 1052 uint32_t size, uint32_t *dst) 1053 { 1054 WARN_ON(simd != 0); 1055 1056 wave_read_regs( 1057 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1058 dst); 1059 } 1060 1061 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1062 uint32_t wave, uint32_t thread, 1063 uint32_t start, uint32_t size, 1064 uint32_t *dst) 1065 { 1066 wave_read_regs( 1067 adev, wave, thread, 1068 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1069 } 1070 1071 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 1072 u32 me, u32 pipe, u32 q, u32 vm) 1073 { 1074 nv_grbm_select(adev, me, pipe, q, vm); 1075 } 1076 1077 1078 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 1079 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 1080 .select_se_sh = &gfx_v10_0_select_se_sh, 1081 .read_wave_data = &gfx_v10_0_read_wave_data, 1082 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 1083 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 1084 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 1085 }; 1086 1087 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 1088 { 1089 u32 gb_addr_config; 1090 1091 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 1092 1093 switch (adev->asic_type) { 1094 case CHIP_NAVI10: 1095 adev->gfx.config.max_hw_contexts = 8; 1096 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1097 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1098 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1099 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1100 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1101 break; 1102 case CHIP_NAVI14: 1103 adev->gfx.config.max_hw_contexts = 8; 1104 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1105 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1106 adev->gfx.config.sc_hiz_tile_fifo_size = 0x0; 1107 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1108 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1109 break; 1110 default: 1111 BUG(); 1112 break; 1113 } 1114 1115 adev->gfx.config.gb_addr_config = gb_addr_config; 1116 1117 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1118 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1119 GB_ADDR_CONFIG, NUM_PIPES); 1120 1121 adev->gfx.config.max_tile_pipes = 1122 adev->gfx.config.gb_addr_config_fields.num_pipes; 1123 1124 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1125 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1126 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 1127 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1128 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1129 GB_ADDR_CONFIG, NUM_RB_PER_SE); 1130 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1131 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1132 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 1133 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1134 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1135 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 1136 } 1137 1138 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1139 int me, int pipe, int queue) 1140 { 1141 int r; 1142 struct amdgpu_ring *ring; 1143 unsigned int irq_type; 1144 1145 ring = &adev->gfx.gfx_ring[ring_id]; 1146 1147 ring->me = me; 1148 ring->pipe = pipe; 1149 ring->queue = queue; 1150 1151 ring->ring_obj = NULL; 1152 ring->use_doorbell = true; 1153 1154 if (!ring_id) 1155 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1156 else 1157 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1158 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1159 1160 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1161 r = amdgpu_ring_init(adev, ring, 1024, 1162 &adev->gfx.eop_irq, irq_type); 1163 if (r) 1164 return r; 1165 return 0; 1166 } 1167 1168 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1169 int mec, int pipe, int queue) 1170 { 1171 int r; 1172 unsigned irq_type; 1173 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1174 1175 ring = &adev->gfx.compute_ring[ring_id]; 1176 1177 /* mec0 is me1 */ 1178 ring->me = mec + 1; 1179 ring->pipe = pipe; 1180 ring->queue = queue; 1181 1182 ring->ring_obj = NULL; 1183 ring->use_doorbell = true; 1184 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1185 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1186 + (ring_id * GFX10_MEC_HPD_SIZE); 1187 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1188 1189 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1190 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1191 + ring->pipe; 1192 1193 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1194 r = amdgpu_ring_init(adev, ring, 1024, 1195 &adev->gfx.eop_irq, irq_type); 1196 if (r) 1197 return r; 1198 1199 return 0; 1200 } 1201 1202 static int gfx_v10_0_sw_init(void *handle) 1203 { 1204 int i, j, k, r, ring_id = 0; 1205 struct amdgpu_kiq *kiq; 1206 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1207 1208 switch (adev->asic_type) { 1209 case CHIP_NAVI10: 1210 case CHIP_NAVI14: 1211 adev->gfx.me.num_me = 1; 1212 adev->gfx.me.num_pipe_per_me = 2; 1213 adev->gfx.me.num_queue_per_pipe = 1; 1214 adev->gfx.mec.num_mec = 2; 1215 adev->gfx.mec.num_pipe_per_mec = 4; 1216 adev->gfx.mec.num_queue_per_pipe = 8; 1217 break; 1218 default: 1219 adev->gfx.me.num_me = 1; 1220 adev->gfx.me.num_pipe_per_me = 1; 1221 adev->gfx.me.num_queue_per_pipe = 1; 1222 adev->gfx.mec.num_mec = 1; 1223 adev->gfx.mec.num_pipe_per_mec = 4; 1224 adev->gfx.mec.num_queue_per_pipe = 8; 1225 break; 1226 } 1227 1228 /* KIQ event */ 1229 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1230 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 1231 &adev->gfx.kiq.irq); 1232 if (r) 1233 return r; 1234 1235 /* EOP Event */ 1236 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1237 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 1238 &adev->gfx.eop_irq); 1239 if (r) 1240 return r; 1241 1242 /* Privileged reg */ 1243 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 1244 &adev->gfx.priv_reg_irq); 1245 if (r) 1246 return r; 1247 1248 /* Privileged inst */ 1249 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 1250 &adev->gfx.priv_inst_irq); 1251 if (r) 1252 return r; 1253 1254 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1255 1256 gfx_v10_0_scratch_init(adev); 1257 1258 r = gfx_v10_0_me_init(adev); 1259 if (r) 1260 return r; 1261 1262 r = gfx_v10_0_rlc_init(adev); 1263 if (r) { 1264 DRM_ERROR("Failed to init rlc BOs!\n"); 1265 return r; 1266 } 1267 1268 r = gfx_v10_0_mec_init(adev); 1269 if (r) { 1270 DRM_ERROR("Failed to init MEC BOs!\n"); 1271 return r; 1272 } 1273 1274 /* set up the gfx ring */ 1275 for (i = 0; i < adev->gfx.me.num_me; i++) { 1276 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1277 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1278 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1279 continue; 1280 1281 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 1282 i, k, j); 1283 if (r) 1284 return r; 1285 ring_id++; 1286 } 1287 } 1288 } 1289 1290 ring_id = 0; 1291 /* set up the compute queues - allocate horizontally across pipes */ 1292 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1293 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1294 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1295 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1296 j)) 1297 continue; 1298 1299 r = gfx_v10_0_compute_ring_init(adev, ring_id, 1300 i, k, j); 1301 if (r) 1302 return r; 1303 1304 ring_id++; 1305 } 1306 } 1307 } 1308 1309 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 1310 if (r) { 1311 DRM_ERROR("Failed to init KIQ BOs!\n"); 1312 return r; 1313 } 1314 1315 kiq = &adev->gfx.kiq; 1316 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1317 if (r) 1318 return r; 1319 1320 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 1321 if (r) 1322 return r; 1323 1324 /* allocate visible FB for rlc auto-loading fw */ 1325 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1326 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 1327 if (r) 1328 return r; 1329 } 1330 1331 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 1332 1333 gfx_v10_0_gpu_early_init(adev); 1334 1335 return 0; 1336 } 1337 1338 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 1339 { 1340 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1341 &adev->gfx.pfp.pfp_fw_gpu_addr, 1342 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1343 } 1344 1345 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 1346 { 1347 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 1348 &adev->gfx.ce.ce_fw_gpu_addr, 1349 (void **)&adev->gfx.ce.ce_fw_ptr); 1350 } 1351 1352 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 1353 { 1354 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1355 &adev->gfx.me.me_fw_gpu_addr, 1356 (void **)&adev->gfx.me.me_fw_ptr); 1357 } 1358 1359 static int gfx_v10_0_sw_fini(void *handle) 1360 { 1361 int i; 1362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1363 1364 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1365 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1366 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1367 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1368 1369 amdgpu_gfx_mqd_sw_fini(adev); 1370 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1371 amdgpu_gfx_kiq_fini(adev); 1372 1373 gfx_v10_0_pfp_fini(adev); 1374 gfx_v10_0_ce_fini(adev); 1375 gfx_v10_0_me_fini(adev); 1376 gfx_v10_0_rlc_fini(adev); 1377 gfx_v10_0_mec_fini(adev); 1378 1379 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1380 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 1381 1382 gfx_v10_0_free_microcode(adev); 1383 1384 return 0; 1385 } 1386 1387 1388 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev) 1389 { 1390 /* TODO */ 1391 } 1392 1393 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1394 u32 sh_num, u32 instance) 1395 { 1396 u32 data; 1397 1398 if (instance == 0xffffffff) 1399 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1400 INSTANCE_BROADCAST_WRITES, 1); 1401 else 1402 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1403 instance); 1404 1405 if (se_num == 0xffffffff) 1406 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1407 1); 1408 else 1409 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1410 1411 if (sh_num == 0xffffffff) 1412 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1413 1); 1414 else 1415 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1416 1417 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1418 } 1419 1420 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1421 { 1422 u32 data, mask; 1423 1424 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1425 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1426 1427 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1428 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1429 1430 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1431 adev->gfx.config.max_sh_per_se); 1432 1433 return (~data) & mask; 1434 } 1435 1436 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 1437 { 1438 int i, j; 1439 u32 data; 1440 u32 active_rbs = 0; 1441 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1442 adev->gfx.config.max_sh_per_se; 1443 1444 mutex_lock(&adev->grbm_idx_mutex); 1445 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1446 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1447 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1448 data = gfx_v10_0_get_rb_active_bitmap(adev); 1449 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1450 rb_bitmap_width_per_sh); 1451 } 1452 } 1453 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1454 mutex_unlock(&adev->grbm_idx_mutex); 1455 1456 adev->gfx.config.backend_enable_mask = active_rbs; 1457 adev->gfx.config.num_rbs = hweight32(active_rbs); 1458 } 1459 1460 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 1461 { 1462 uint32_t num_sc; 1463 uint32_t enabled_rb_per_sh; 1464 uint32_t active_rb_bitmap; 1465 uint32_t num_rb_per_sc; 1466 uint32_t num_packer_per_sc; 1467 uint32_t pa_sc_tile_steering_override; 1468 1469 /* init num_sc */ 1470 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 1471 adev->gfx.config.num_sc_per_sh; 1472 /* init num_rb_per_sc */ 1473 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 1474 enabled_rb_per_sh = hweight32(active_rb_bitmap); 1475 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 1476 /* init num_packer_per_sc */ 1477 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 1478 1479 pa_sc_tile_steering_override = 0; 1480 pa_sc_tile_steering_override |= 1481 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 1482 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 1483 pa_sc_tile_steering_override |= 1484 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 1485 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 1486 pa_sc_tile_steering_override |= 1487 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 1488 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 1489 1490 return pa_sc_tile_steering_override; 1491 } 1492 1493 #define DEFAULT_SH_MEM_BASES (0x6000) 1494 #define FIRST_COMPUTE_VMID (8) 1495 #define LAST_COMPUTE_VMID (16) 1496 1497 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 1498 { 1499 int i; 1500 uint32_t sh_mem_bases; 1501 1502 /* 1503 * Configure apertures: 1504 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1505 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1506 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1507 */ 1508 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1509 1510 mutex_lock(&adev->srbm_mutex); 1511 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1512 nv_grbm_select(adev, 0, 0, 0, i); 1513 /* CP and shaders */ 1514 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1515 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1516 } 1517 nv_grbm_select(adev, 0, 0, 0, 0); 1518 mutex_unlock(&adev->srbm_mutex); 1519 } 1520 1521 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 1522 { 1523 int i, j, k; 1524 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 1525 u32 tmp, wgp_active_bitmap = 0; 1526 u32 gcrd_targets_disable_tcp = 0; 1527 u32 utcl_invreq_disable = 0; 1528 /* 1529 * GCRD_TARGETS_DISABLE field contains 1530 * for Navi10: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 1531 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 1532 */ 1533 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 1534 2 * max_wgp_per_sh + /* TCP */ 1535 max_wgp_per_sh + /* SQC */ 1536 4); /* GL1C */ 1537 /* 1538 * UTCL1_UTCL0_INVREQ_DISABLE field contains 1539 * for Navi10: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 1540 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 1541 */ 1542 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 1543 2 * max_wgp_per_sh + /* TCP */ 1544 2 * max_wgp_per_sh + /* SQC */ 1545 4 + /* RMI */ 1546 1); /* SQG */ 1547 1548 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_NAVI14) { 1549 mutex_lock(&adev->grbm_idx_mutex); 1550 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1551 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1552 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1553 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 1554 /* 1555 * Set corresponding TCP bits for the inactive WGPs in 1556 * GCRD_SA_TARGETS_DISABLE 1557 */ 1558 gcrd_targets_disable_tcp = 0; 1559 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 1560 utcl_invreq_disable = 0; 1561 1562 for (k = 0; k < max_wgp_per_sh; k++) { 1563 if (!(wgp_active_bitmap & (1 << k))) { 1564 gcrd_targets_disable_tcp |= 3 << (2 * k); 1565 utcl_invreq_disable |= (3 << (2 * k)) | 1566 (3 << (2 * (max_wgp_per_sh + k))); 1567 } 1568 } 1569 1570 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 1571 /* only override TCP & SQC bits */ 1572 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 1573 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 1574 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 1575 1576 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 1577 /* only override TCP bits */ 1578 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 1579 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 1580 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 1581 } 1582 } 1583 1584 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1585 mutex_unlock(&adev->grbm_idx_mutex); 1586 } 1587 } 1588 1589 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 1590 { 1591 u32 tmp; 1592 int i; 1593 1594 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1595 1596 gfx_v10_0_tiling_mode_table_init(adev); 1597 1598 gfx_v10_0_setup_rb(adev); 1599 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 1600 adev->gfx.config.pa_sc_tile_steering_override = 1601 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 1602 1603 /* XXX SH_MEM regs */ 1604 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1605 mutex_lock(&adev->srbm_mutex); 1606 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) { 1607 nv_grbm_select(adev, 0, 0, 0, i); 1608 /* CP and shaders */ 1609 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1610 if (i != 0) { 1611 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1612 (adev->gmc.private_aperture_start >> 48)); 1613 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1614 (adev->gmc.shared_aperture_start >> 48)); 1615 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1616 } 1617 } 1618 nv_grbm_select(adev, 0, 0, 0, 0); 1619 1620 mutex_unlock(&adev->srbm_mutex); 1621 1622 gfx_v10_0_init_compute_vmid(adev); 1623 1624 } 1625 1626 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1627 bool enable) 1628 { 1629 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1630 1631 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1632 enable ? 1 : 0); 1633 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1634 enable ? 1 : 0); 1635 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1636 enable ? 1 : 0); 1637 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1638 enable ? 1 : 0); 1639 1640 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1641 } 1642 1643 static void gfx_v10_0_init_csb(struct amdgpu_device *adev) 1644 { 1645 /* csib */ 1646 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 1647 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1648 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 1649 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1650 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1651 } 1652 1653 static void gfx_v10_0_init_pg(struct amdgpu_device *adev) 1654 { 1655 gfx_v10_0_init_csb(adev); 1656 1657 amdgpu_gmc_flush_gpu_tlb(adev, 0, 0); 1658 1659 /* TODO: init power gating */ 1660 return; 1661 } 1662 1663 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 1664 { 1665 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 1666 1667 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1668 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 1669 } 1670 1671 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 1672 { 1673 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1674 udelay(50); 1675 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1676 udelay(50); 1677 } 1678 1679 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1680 bool enable) 1681 { 1682 uint32_t rlc_pg_cntl; 1683 1684 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 1685 1686 if (!enable) { 1687 /* RLC_PG_CNTL[23] = 0 (default) 1688 * RLC will wait for handshake acks with SMU 1689 * GFXOFF will be enabled 1690 * RLC_PG_CNTL[23] = 1 1691 * RLC will not issue any message to SMU 1692 * hence no handshake between SMU & RLC 1693 * GFXOFF will be disabled 1694 */ 1695 rlc_pg_cntl |= 0x80000; 1696 } else 1697 rlc_pg_cntl &= ~0x80000; 1698 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 1699 } 1700 1701 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 1702 { 1703 /* TODO: enable rlc & smu handshake until smu 1704 * and gfxoff feature works as expected */ 1705 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1706 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 1707 1708 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1709 udelay(50); 1710 } 1711 1712 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 1713 { 1714 uint32_t tmp; 1715 1716 /* enable Save Restore Machine */ 1717 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1718 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1719 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1720 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1721 } 1722 1723 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 1724 { 1725 const struct rlc_firmware_header_v2_0 *hdr; 1726 const __le32 *fw_data; 1727 unsigned i, fw_size; 1728 1729 if (!adev->gfx.rlc_fw) 1730 return -EINVAL; 1731 1732 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1733 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1734 1735 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1736 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1737 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1738 1739 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 1740 RLCG_UCODE_LOADING_START_ADDRESS); 1741 1742 for (i = 0; i < fw_size; i++) 1743 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 1744 le32_to_cpup(fw_data++)); 1745 1746 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1747 1748 return 0; 1749 } 1750 1751 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 1752 { 1753 int r; 1754 1755 if (amdgpu_sriov_vf(adev)) 1756 return 0; 1757 1758 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1759 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1760 if (r) 1761 return r; 1762 gfx_v10_0_init_pg(adev); 1763 1764 /* enable RLC SRM */ 1765 gfx_v10_0_rlc_enable_srm(adev); 1766 1767 } else { 1768 adev->gfx.rlc.funcs->stop(adev); 1769 1770 /* disable CG */ 1771 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 1772 1773 /* disable PG */ 1774 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 1775 1776 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1777 /* legacy rlc firmware loading */ 1778 r = gfx_v10_0_rlc_load_microcode(adev); 1779 if (r) 1780 return r; 1781 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1782 /* rlc backdoor autoload firmware */ 1783 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 1784 if (r) 1785 return r; 1786 } 1787 1788 gfx_v10_0_init_pg(adev); 1789 adev->gfx.rlc.funcs->start(adev); 1790 1791 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1792 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1793 if (r) 1794 return r; 1795 } 1796 } 1797 return 0; 1798 } 1799 1800 static struct { 1801 FIRMWARE_ID id; 1802 unsigned int offset; 1803 unsigned int size; 1804 } rlc_autoload_info[FIRMWARE_ID_MAX]; 1805 1806 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 1807 { 1808 int ret; 1809 RLC_TABLE_OF_CONTENT *rlc_toc; 1810 1811 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 1812 AMDGPU_GEM_DOMAIN_GTT, 1813 &adev->gfx.rlc.rlc_toc_bo, 1814 &adev->gfx.rlc.rlc_toc_gpu_addr, 1815 (void **)&adev->gfx.rlc.rlc_toc_buf); 1816 if (ret) { 1817 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 1818 return ret; 1819 } 1820 1821 /* Copy toc from psp sos fw to rlc toc buffer */ 1822 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 1823 1824 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 1825 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 1826 (rlc_toc->id < FIRMWARE_ID_MAX)) { 1827 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 1828 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 1829 /* Offset needs 4KB alignment */ 1830 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 1831 } 1832 1833 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 1834 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 1835 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 1836 1837 rlc_toc++; 1838 }; 1839 1840 return 0; 1841 } 1842 1843 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 1844 { 1845 uint32_t total_size = 0; 1846 FIRMWARE_ID id; 1847 int ret; 1848 1849 ret = gfx_v10_0_parse_rlc_toc(adev); 1850 if (ret) { 1851 dev_err(adev->dev, "failed to parse rlc toc\n"); 1852 return 0; 1853 } 1854 1855 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 1856 total_size += rlc_autoload_info[id].size; 1857 1858 /* In case the offset in rlc toc ucode is aligned */ 1859 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 1860 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 1861 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 1862 1863 return total_size; 1864 } 1865 1866 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 1867 { 1868 int r; 1869 uint32_t total_size; 1870 1871 total_size = gfx_v10_0_calc_toc_total_size(adev); 1872 1873 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 1874 AMDGPU_GEM_DOMAIN_GTT, 1875 &adev->gfx.rlc.rlc_autoload_bo, 1876 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1877 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1878 if (r) { 1879 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1880 return r; 1881 } 1882 1883 return 0; 1884 } 1885 1886 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 1887 { 1888 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 1889 &adev->gfx.rlc.rlc_toc_gpu_addr, 1890 (void **)&adev->gfx.rlc.rlc_toc_buf); 1891 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1892 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1893 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1894 } 1895 1896 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1897 FIRMWARE_ID id, 1898 const void *fw_data, 1899 uint32_t fw_size) 1900 { 1901 uint32_t toc_offset; 1902 uint32_t toc_fw_size; 1903 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1904 1905 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 1906 return; 1907 1908 toc_offset = rlc_autoload_info[id].offset; 1909 toc_fw_size = rlc_autoload_info[id].size; 1910 1911 if (fw_size == 0) 1912 fw_size = toc_fw_size; 1913 1914 if (fw_size > toc_fw_size) 1915 fw_size = toc_fw_size; 1916 1917 memcpy(ptr + toc_offset, fw_data, fw_size); 1918 1919 if (fw_size < toc_fw_size) 1920 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1921 } 1922 1923 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1924 { 1925 void *data; 1926 uint32_t size; 1927 1928 data = adev->gfx.rlc.rlc_toc_buf; 1929 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 1930 1931 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 1932 FIRMWARE_ID_RLC_TOC, 1933 data, size); 1934 } 1935 1936 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1937 { 1938 const __le32 *fw_data; 1939 uint32_t fw_size; 1940 const struct gfx_firmware_header_v1_0 *cp_hdr; 1941 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1942 1943 /* pfp ucode */ 1944 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1945 adev->gfx.pfp_fw->data; 1946 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1947 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1948 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1949 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 1950 FIRMWARE_ID_CP_PFP, 1951 fw_data, fw_size); 1952 1953 /* ce ucode */ 1954 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1955 adev->gfx.ce_fw->data; 1956 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 1957 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1958 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1959 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 1960 FIRMWARE_ID_CP_CE, 1961 fw_data, fw_size); 1962 1963 /* me ucode */ 1964 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1965 adev->gfx.me_fw->data; 1966 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1967 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1968 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1969 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 1970 FIRMWARE_ID_CP_ME, 1971 fw_data, fw_size); 1972 1973 /* rlc ucode */ 1974 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1975 adev->gfx.rlc_fw->data; 1976 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1977 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1978 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1979 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 1980 FIRMWARE_ID_RLC_G_UCODE, 1981 fw_data, fw_size); 1982 1983 /* mec1 ucode */ 1984 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1985 adev->gfx.mec_fw->data; 1986 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1987 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1988 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1989 cp_hdr->jt_size * 4; 1990 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 1991 FIRMWARE_ID_CP_MEC, 1992 fw_data, fw_size); 1993 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 1994 } 1995 1996 /* Temporarily put sdma part here */ 1997 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1998 { 1999 const __le32 *fw_data; 2000 uint32_t fw_size; 2001 const struct sdma_firmware_header_v1_0 *sdma_hdr; 2002 int i; 2003 2004 for (i = 0; i < adev->sdma.num_instances; i++) { 2005 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 2006 adev->sdma.instance[i].fw->data; 2007 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 2008 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 2009 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 2010 2011 if (i == 0) { 2012 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2013 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 2014 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2015 FIRMWARE_ID_SDMA0_JT, 2016 (uint32_t *)fw_data + 2017 sdma_hdr->jt_offset, 2018 sdma_hdr->jt_size * 4); 2019 } else if (i == 1) { 2020 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2021 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 2022 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2023 FIRMWARE_ID_SDMA1_JT, 2024 (uint32_t *)fw_data + 2025 sdma_hdr->jt_offset, 2026 sdma_hdr->jt_size * 4); 2027 } 2028 } 2029 } 2030 2031 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 2032 { 2033 uint32_t rlc_g_offset, rlc_g_size, tmp; 2034 uint64_t gpu_addr; 2035 2036 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 2037 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 2038 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 2039 2040 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 2041 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 2042 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 2043 2044 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 2045 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 2046 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 2047 2048 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 2049 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 2050 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 2051 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 2052 return -EINVAL; 2053 } 2054 2055 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 2056 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2057 DRM_ERROR("RLC ROM should halt itself\n"); 2058 return -EINVAL; 2059 } 2060 2061 return 0; 2062 } 2063 2064 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 2065 { 2066 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2067 uint32_t tmp; 2068 int i; 2069 uint64_t addr; 2070 2071 /* Trigger an invalidation of the L1 instruction caches */ 2072 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2073 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2074 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2075 2076 /* Wait for invalidation complete */ 2077 for (i = 0; i < usec_timeout; i++) { 2078 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2079 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2080 INVALIDATE_CACHE_COMPLETE)) 2081 break; 2082 udelay(1); 2083 } 2084 2085 if (i >= usec_timeout) { 2086 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2087 return -EINVAL; 2088 } 2089 2090 /* Program me ucode address into intruction cache address register */ 2091 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2092 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 2093 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2094 lower_32_bits(addr) & 0xFFFFF000); 2095 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2096 upper_32_bits(addr)); 2097 2098 return 0; 2099 } 2100 2101 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 2102 { 2103 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2104 uint32_t tmp; 2105 int i; 2106 uint64_t addr; 2107 2108 /* Trigger an invalidation of the L1 instruction caches */ 2109 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2110 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2111 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2112 2113 /* Wait for invalidation complete */ 2114 for (i = 0; i < usec_timeout; i++) { 2115 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2116 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2117 INVALIDATE_CACHE_COMPLETE)) 2118 break; 2119 udelay(1); 2120 } 2121 2122 if (i >= usec_timeout) { 2123 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2124 return -EINVAL; 2125 } 2126 2127 /* Program ce ucode address into intruction cache address register */ 2128 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2129 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 2130 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2131 lower_32_bits(addr) & 0xFFFFF000); 2132 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2133 upper_32_bits(addr)); 2134 2135 return 0; 2136 } 2137 2138 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 2139 { 2140 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2141 uint32_t tmp; 2142 int i; 2143 uint64_t addr; 2144 2145 /* Trigger an invalidation of the L1 instruction caches */ 2146 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2147 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2148 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2149 2150 /* Wait for invalidation complete */ 2151 for (i = 0; i < usec_timeout; i++) { 2152 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2153 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2154 INVALIDATE_CACHE_COMPLETE)) 2155 break; 2156 udelay(1); 2157 } 2158 2159 if (i >= usec_timeout) { 2160 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2161 return -EINVAL; 2162 } 2163 2164 /* Program pfp ucode address into intruction cache address register */ 2165 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2166 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 2167 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2168 lower_32_bits(addr) & 0xFFFFF000); 2169 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2170 upper_32_bits(addr)); 2171 2172 return 0; 2173 } 2174 2175 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 2176 { 2177 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2178 uint32_t tmp; 2179 int i; 2180 uint64_t addr; 2181 2182 /* Trigger an invalidation of the L1 instruction caches */ 2183 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2184 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2185 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2186 2187 /* Wait for invalidation complete */ 2188 for (i = 0; i < usec_timeout; i++) { 2189 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2190 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2191 INVALIDATE_CACHE_COMPLETE)) 2192 break; 2193 udelay(1); 2194 } 2195 2196 if (i >= usec_timeout) { 2197 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2198 return -EINVAL; 2199 } 2200 2201 /* Program mec1 ucode address into intruction cache address register */ 2202 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2203 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 2204 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2205 lower_32_bits(addr) & 0xFFFFF000); 2206 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2207 upper_32_bits(addr)); 2208 2209 return 0; 2210 } 2211 2212 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2213 { 2214 uint32_t cp_status; 2215 uint32_t bootload_status; 2216 int i, r; 2217 2218 for (i = 0; i < adev->usec_timeout; i++) { 2219 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 2220 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 2221 if ((cp_status == 0) && 2222 (REG_GET_FIELD(bootload_status, 2223 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2224 break; 2225 } 2226 udelay(1); 2227 } 2228 2229 if (i >= adev->usec_timeout) { 2230 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2231 return -ETIMEDOUT; 2232 } 2233 2234 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2235 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 2236 if (r) 2237 return r; 2238 2239 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 2240 if (r) 2241 return r; 2242 2243 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 2244 if (r) 2245 return r; 2246 2247 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 2248 if (r) 2249 return r; 2250 } 2251 2252 return 0; 2253 } 2254 2255 static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2256 { 2257 int i; 2258 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2259 2260 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2261 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2262 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2263 if (!enable) { 2264 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2265 adev->gfx.gfx_ring[i].sched.ready = false; 2266 } 2267 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2268 udelay(50); 2269 } 2270 2271 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2272 { 2273 int r; 2274 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2275 const __le32 *fw_data; 2276 unsigned i, fw_size; 2277 uint32_t tmp; 2278 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2279 2280 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2281 adev->gfx.pfp_fw->data; 2282 2283 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2284 2285 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2286 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2287 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2288 2289 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2290 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2291 &adev->gfx.pfp.pfp_fw_obj, 2292 &adev->gfx.pfp.pfp_fw_gpu_addr, 2293 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2294 if (r) { 2295 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2296 gfx_v10_0_pfp_fini(adev); 2297 return r; 2298 } 2299 2300 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2301 2302 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2303 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2304 2305 /* Trigger an invalidation of the L1 instruction caches */ 2306 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2307 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2308 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2309 2310 /* Wait for invalidation complete */ 2311 for (i = 0; i < usec_timeout; i++) { 2312 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2313 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2314 INVALIDATE_CACHE_COMPLETE)) 2315 break; 2316 udelay(1); 2317 } 2318 2319 if (i >= usec_timeout) { 2320 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2321 return -EINVAL; 2322 } 2323 2324 if (amdgpu_emu_mode == 1) 2325 adev->nbio_funcs->hdp_flush(adev, NULL); 2326 2327 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 2328 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2329 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2330 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2331 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2332 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 2333 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2334 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 2335 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2336 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2337 2338 return 0; 2339 } 2340 2341 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 2342 { 2343 int r; 2344 const struct gfx_firmware_header_v1_0 *ce_hdr; 2345 const __le32 *fw_data; 2346 unsigned i, fw_size; 2347 uint32_t tmp; 2348 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2349 2350 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2351 adev->gfx.ce_fw->data; 2352 2353 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2354 2355 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2356 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2357 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 2358 2359 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 2360 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2361 &adev->gfx.ce.ce_fw_obj, 2362 &adev->gfx.ce.ce_fw_gpu_addr, 2363 (void **)&adev->gfx.ce.ce_fw_ptr); 2364 if (r) { 2365 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 2366 gfx_v10_0_ce_fini(adev); 2367 return r; 2368 } 2369 2370 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 2371 2372 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 2373 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 2374 2375 /* Trigger an invalidation of the L1 instruction caches */ 2376 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2377 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2378 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2379 2380 /* Wait for invalidation complete */ 2381 for (i = 0; i < usec_timeout; i++) { 2382 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2383 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2384 INVALIDATE_CACHE_COMPLETE)) 2385 break; 2386 udelay(1); 2387 } 2388 2389 if (i >= usec_timeout) { 2390 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2391 return -EINVAL; 2392 } 2393 2394 if (amdgpu_emu_mode == 1) 2395 adev->nbio_funcs->hdp_flush(adev, NULL); 2396 2397 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 2398 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 2399 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 2400 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 2401 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2402 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2403 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 2404 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2405 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 2406 2407 return 0; 2408 } 2409 2410 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2411 { 2412 int r; 2413 const struct gfx_firmware_header_v1_0 *me_hdr; 2414 const __le32 *fw_data; 2415 unsigned i, fw_size; 2416 uint32_t tmp; 2417 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2418 2419 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2420 adev->gfx.me_fw->data; 2421 2422 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2423 2424 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2425 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2426 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2427 2428 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2429 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2430 &adev->gfx.me.me_fw_obj, 2431 &adev->gfx.me.me_fw_gpu_addr, 2432 (void **)&adev->gfx.me.me_fw_ptr); 2433 if (r) { 2434 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2435 gfx_v10_0_me_fini(adev); 2436 return r; 2437 } 2438 2439 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2440 2441 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2442 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2443 2444 /* Trigger an invalidation of the L1 instruction caches */ 2445 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2446 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2447 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2448 2449 /* Wait for invalidation complete */ 2450 for (i = 0; i < usec_timeout; i++) { 2451 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2452 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2453 INVALIDATE_CACHE_COMPLETE)) 2454 break; 2455 udelay(1); 2456 } 2457 2458 if (i >= usec_timeout) { 2459 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2460 return -EINVAL; 2461 } 2462 2463 if (amdgpu_emu_mode == 1) 2464 adev->nbio_funcs->hdp_flush(adev, NULL); 2465 2466 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 2467 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2468 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2469 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2470 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2471 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2472 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 2473 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2474 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2475 2476 return 0; 2477 } 2478 2479 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2480 { 2481 int r; 2482 2483 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2484 return -EINVAL; 2485 2486 gfx_v10_0_cp_gfx_enable(adev, false); 2487 2488 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 2489 if (r) { 2490 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2491 return r; 2492 } 2493 2494 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 2495 if (r) { 2496 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 2497 return r; 2498 } 2499 2500 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 2501 if (r) { 2502 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2503 return r; 2504 } 2505 2506 return 0; 2507 } 2508 2509 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 2510 { 2511 struct amdgpu_ring *ring; 2512 const struct cs_section_def *sect = NULL; 2513 const struct cs_extent_def *ext = NULL; 2514 int r, i; 2515 int ctx_reg_offset; 2516 2517 /* init the CP */ 2518 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 2519 adev->gfx.config.max_hw_contexts - 1); 2520 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2521 2522 gfx_v10_0_cp_gfx_enable(adev, true); 2523 2524 ring = &adev->gfx.gfx_ring[0]; 2525 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 2526 if (r) { 2527 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2528 return r; 2529 } 2530 2531 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2532 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2533 2534 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2535 amdgpu_ring_write(ring, 0x80000000); 2536 amdgpu_ring_write(ring, 0x80000000); 2537 2538 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 2539 for (ext = sect->section; ext->extent != NULL; ++ext) { 2540 if (sect->id == SECT_CONTEXT) { 2541 amdgpu_ring_write(ring, 2542 PACKET3(PACKET3_SET_CONTEXT_REG, 2543 ext->reg_count)); 2544 amdgpu_ring_write(ring, ext->reg_index - 2545 PACKET3_SET_CONTEXT_REG_START); 2546 for (i = 0; i < ext->reg_count; i++) 2547 amdgpu_ring_write(ring, ext->extent[i]); 2548 } 2549 } 2550 } 2551 2552 ctx_reg_offset = 2553 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 2554 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2555 amdgpu_ring_write(ring, ctx_reg_offset); 2556 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 2557 2558 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2559 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2560 2561 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2562 amdgpu_ring_write(ring, 0); 2563 2564 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2565 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2566 amdgpu_ring_write(ring, 0x8000); 2567 amdgpu_ring_write(ring, 0x8000); 2568 2569 amdgpu_ring_commit(ring); 2570 2571 /* submit cs packet to copy state 0 to next available state */ 2572 ring = &adev->gfx.gfx_ring[1]; 2573 r = amdgpu_ring_alloc(ring, 2); 2574 if (r) { 2575 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2576 return r; 2577 } 2578 2579 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2580 amdgpu_ring_write(ring, 0); 2581 2582 amdgpu_ring_commit(ring); 2583 2584 return 0; 2585 } 2586 2587 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2588 CP_PIPE_ID pipe) 2589 { 2590 u32 tmp; 2591 2592 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 2593 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2594 2595 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 2596 } 2597 2598 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2599 struct amdgpu_ring *ring) 2600 { 2601 u32 tmp; 2602 2603 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2604 if (ring->use_doorbell) { 2605 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2606 DOORBELL_OFFSET, ring->doorbell_index); 2607 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2608 DOORBELL_EN, 1); 2609 } else { 2610 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2611 DOORBELL_EN, 0); 2612 } 2613 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2614 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2615 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2616 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2617 2618 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2619 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2620 } 2621 2622 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 2623 { 2624 struct amdgpu_ring *ring; 2625 u32 tmp; 2626 u32 rb_bufsz; 2627 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2628 u32 i; 2629 2630 /* Set the write pointer delay */ 2631 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2632 2633 /* set the RB to use vmid 0 */ 2634 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2635 2636 /* Init gfx ring 0 for pipe 0 */ 2637 mutex_lock(&adev->srbm_mutex); 2638 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2639 mutex_unlock(&adev->srbm_mutex); 2640 /* Set ring buffer size */ 2641 ring = &adev->gfx.gfx_ring[0]; 2642 rb_bufsz = order_base_2(ring->ring_size / 8); 2643 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2644 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2645 #ifdef __BIG_ENDIAN 2646 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2647 #endif 2648 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2649 2650 /* Initialize the ring buffer's write pointers */ 2651 ring->wptr = 0; 2652 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2653 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2654 2655 /* set the wb address wether it's enabled or not */ 2656 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2657 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2658 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2659 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2660 2661 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2662 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2663 lower_32_bits(wptr_gpu_addr)); 2664 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2665 upper_32_bits(wptr_gpu_addr)); 2666 2667 mdelay(1); 2668 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2669 2670 rb_addr = ring->gpu_addr >> 8; 2671 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2672 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2673 2674 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 2675 2676 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2677 2678 /* Init gfx ring 1 for pipe 1 */ 2679 mutex_lock(&adev->srbm_mutex); 2680 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 2681 mutex_unlock(&adev->srbm_mutex); 2682 ring = &adev->gfx.gfx_ring[1]; 2683 rb_bufsz = order_base_2(ring->ring_size / 8); 2684 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 2685 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 2686 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2687 /* Initialize the ring buffer's write pointers */ 2688 ring->wptr = 0; 2689 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2690 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 2691 /* Set the wb address wether it's enabled or not */ 2692 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2693 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2694 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2695 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2696 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2697 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2698 lower_32_bits(wptr_gpu_addr)); 2699 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2700 upper_32_bits(wptr_gpu_addr)); 2701 2702 mdelay(1); 2703 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2704 2705 rb_addr = ring->gpu_addr >> 8; 2706 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 2707 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 2708 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 2709 2710 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2711 2712 /* Switch to pipe 0 */ 2713 mutex_lock(&adev->srbm_mutex); 2714 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2715 mutex_unlock(&adev->srbm_mutex); 2716 2717 /* start the ring */ 2718 gfx_v10_0_cp_gfx_start(adev); 2719 2720 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2721 ring = &adev->gfx.gfx_ring[i]; 2722 ring->sched.ready = true; 2723 } 2724 2725 return 0; 2726 } 2727 2728 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2729 { 2730 int i; 2731 2732 if (enable) { 2733 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2734 } else { 2735 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2736 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 2737 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2738 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2739 adev->gfx.compute_ring[i].sched.ready = false; 2740 adev->gfx.kiq.ring.sched.ready = false; 2741 } 2742 udelay(50); 2743 } 2744 2745 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2746 { 2747 const struct gfx_firmware_header_v1_0 *mec_hdr; 2748 const __le32 *fw_data; 2749 unsigned i; 2750 u32 tmp; 2751 u32 usec_timeout = 50000; /* Wait for 50 ms */ 2752 2753 if (!adev->gfx.mec_fw) 2754 return -EINVAL; 2755 2756 gfx_v10_0_cp_compute_enable(adev, false); 2757 2758 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2759 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2760 2761 fw_data = (const __le32 *) 2762 (adev->gfx.mec_fw->data + 2763 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2764 2765 /* Trigger an invalidation of the L1 instruction caches */ 2766 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2767 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2768 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2769 2770 /* Wait for invalidation complete */ 2771 for (i = 0; i < usec_timeout; i++) { 2772 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2773 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2774 INVALIDATE_CACHE_COMPLETE)) 2775 break; 2776 udelay(1); 2777 } 2778 2779 if (i >= usec_timeout) { 2780 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2781 return -EINVAL; 2782 } 2783 2784 if (amdgpu_emu_mode == 1) 2785 adev->nbio_funcs->hdp_flush(adev, NULL); 2786 2787 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 2788 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2789 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2790 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2791 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2792 2793 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 2794 0xFFFFF000); 2795 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2796 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2797 2798 /* MEC1 */ 2799 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 2800 2801 for (i = 0; i < mec_hdr->jt_size; i++) 2802 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2803 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2804 2805 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 2806 2807 /* 2808 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 2809 * different microcode than MEC1. 2810 */ 2811 2812 return 0; 2813 } 2814 2815 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 2816 { 2817 uint32_t tmp; 2818 struct amdgpu_device *adev = ring->adev; 2819 2820 /* tell RLC which is KIQ queue */ 2821 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2822 tmp &= 0xffffff00; 2823 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2824 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2825 tmp |= 0x80; 2826 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2827 } 2828 2829 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 2830 { 2831 struct amdgpu_device *adev = ring->adev; 2832 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 2833 uint64_t hqd_gpu_addr, wb_gpu_addr; 2834 uint32_t tmp; 2835 uint32_t rb_bufsz; 2836 2837 /* set up gfx hqd wptr */ 2838 mqd->cp_gfx_hqd_wptr = 0; 2839 mqd->cp_gfx_hqd_wptr_hi = 0; 2840 2841 /* set the pointer to the MQD */ 2842 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 2843 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2844 2845 /* set up mqd control */ 2846 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 2847 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2848 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2849 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2850 mqd->cp_gfx_mqd_control = tmp; 2851 2852 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2853 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 2854 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2855 mqd->cp_gfx_hqd_vmid = 0; 2856 2857 /* set up default queue priority level 2858 * 0x0 = low priority, 0x1 = high priority */ 2859 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 2860 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2861 mqd->cp_gfx_hqd_queue_priority = tmp; 2862 2863 /* set up time quantum */ 2864 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 2865 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2866 mqd->cp_gfx_hqd_quantum = tmp; 2867 2868 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2869 hqd_gpu_addr = ring->gpu_addr >> 8; 2870 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2871 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2872 2873 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2874 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2875 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2876 mqd->cp_gfx_hqd_rptr_addr_hi = 2877 upper_32_bits(wb_gpu_addr) & 0xffff; 2878 2879 /* set up rb_wptr_poll addr */ 2880 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2881 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2882 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2883 2884 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2885 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 2886 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 2887 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2888 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2889 #ifdef __BIG_ENDIAN 2890 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2891 #endif 2892 mqd->cp_gfx_hqd_cntl = tmp; 2893 2894 /* set up cp_doorbell_control */ 2895 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2896 if (ring->use_doorbell) { 2897 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2898 DOORBELL_OFFSET, ring->doorbell_index); 2899 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2900 DOORBELL_EN, 1); 2901 } else 2902 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2903 DOORBELL_EN, 0); 2904 mqd->cp_rb_doorbell_control = tmp; 2905 2906 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2907 ring->wptr = 0; 2908 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 2909 2910 /* active the queue */ 2911 mqd->cp_gfx_hqd_active = 1; 2912 2913 return 0; 2914 } 2915 2916 #ifdef BRING_UP_DEBUG 2917 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 2918 { 2919 struct amdgpu_device *adev = ring->adev; 2920 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 2921 2922 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 2923 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 2924 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 2925 2926 /* set GFX_MQD_BASE */ 2927 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 2928 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 2929 2930 /* set GFX_MQD_CONTROL */ 2931 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 2932 2933 /* set GFX_HQD_VMID to 0 */ 2934 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 2935 2936 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 2937 mqd->cp_gfx_hqd_queue_priority); 2938 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 2939 2940 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 2941 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 2942 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 2943 2944 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 2945 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 2946 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 2947 2948 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 2949 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 2950 2951 /* set RB_WPTR_POLL_ADDR */ 2952 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 2953 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 2954 2955 /* set RB_DOORBELL_CONTROL */ 2956 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 2957 2958 /* active the queue */ 2959 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 2960 2961 return 0; 2962 } 2963 #endif 2964 2965 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 2966 { 2967 struct amdgpu_device *adev = ring->adev; 2968 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 2969 2970 if (!adev->in_gpu_reset && !adev->in_suspend) { 2971 memset((void *)mqd, 0, sizeof(*mqd)); 2972 mutex_lock(&adev->srbm_mutex); 2973 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2974 gfx_v10_0_gfx_mqd_init(ring); 2975 #ifdef BRING_UP_DEBUG 2976 gfx_v10_0_gfx_queue_init_register(ring); 2977 #endif 2978 nv_grbm_select(adev, 0, 0, 0, 0); 2979 mutex_unlock(&adev->srbm_mutex); 2980 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]) 2981 memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd)); 2982 } else if (adev->in_gpu_reset) { 2983 /* reset mqd with the backup copy */ 2984 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]) 2985 memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd)); 2986 /* reset the ring */ 2987 ring->wptr = 0; 2988 amdgpu_ring_clear_ring(ring); 2989 #ifdef BRING_UP_DEBUG 2990 mutex_lock(&adev->srbm_mutex); 2991 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2992 gfx_v10_0_gfx_queue_init_register(ring); 2993 nv_grbm_select(adev, 0, 0, 0, 0); 2994 mutex_unlock(&adev->srbm_mutex); 2995 #endif 2996 } else { 2997 amdgpu_ring_clear_ring(ring); 2998 } 2999 3000 return 0; 3001 } 3002 3003 #ifndef BRING_UP_DEBUG 3004 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 3005 { 3006 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3007 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3008 int r, i; 3009 3010 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3011 return -EINVAL; 3012 3013 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3014 adev->gfx.num_gfx_rings); 3015 if (r) { 3016 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3017 return r; 3018 } 3019 3020 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3021 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3022 3023 r = amdgpu_ring_test_ring(kiq_ring); 3024 if (r) { 3025 DRM_ERROR("kfq enable failed\n"); 3026 kiq_ring->sched.ready = false; 3027 } 3028 return r; 3029 } 3030 #endif 3031 3032 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3033 { 3034 int r, i; 3035 struct amdgpu_ring *ring; 3036 3037 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3038 ring = &adev->gfx.gfx_ring[i]; 3039 3040 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3041 if (unlikely(r != 0)) 3042 goto done; 3043 3044 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3045 if (!r) { 3046 r = gfx_v10_0_gfx_init_queue(ring); 3047 amdgpu_bo_kunmap(ring->mqd_obj); 3048 ring->mqd_ptr = NULL; 3049 } 3050 amdgpu_bo_unreserve(ring->mqd_obj); 3051 if (r) 3052 goto done; 3053 } 3054 #ifndef BRING_UP_DEBUG 3055 r = gfx_v10_0_kiq_enable_kgq(adev); 3056 if (r) 3057 goto done; 3058 #endif 3059 r = gfx_v10_0_cp_gfx_start(adev); 3060 if (r) 3061 goto done; 3062 3063 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3064 ring = &adev->gfx.gfx_ring[i]; 3065 ring->sched.ready = true; 3066 } 3067 done: 3068 return r; 3069 } 3070 3071 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 3072 { 3073 struct amdgpu_device *adev = ring->adev; 3074 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3075 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3076 uint32_t tmp; 3077 3078 mqd->header = 0xC0310800; 3079 mqd->compute_pipelinestat_enable = 0x00000001; 3080 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3081 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3082 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3083 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3084 mqd->compute_misc_reserved = 0x00000003; 3085 3086 eop_base_addr = ring->eop_gpu_addr >> 8; 3087 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3088 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3089 3090 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3091 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3092 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3093 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 3094 3095 mqd->cp_hqd_eop_control = tmp; 3096 3097 /* enable doorbell? */ 3098 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3099 3100 if (ring->use_doorbell) { 3101 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3102 DOORBELL_OFFSET, ring->doorbell_index); 3103 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3104 DOORBELL_EN, 1); 3105 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3106 DOORBELL_SOURCE, 0); 3107 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3108 DOORBELL_HIT, 0); 3109 } else { 3110 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3111 DOORBELL_EN, 0); 3112 } 3113 3114 mqd->cp_hqd_pq_doorbell_control = tmp; 3115 3116 /* disable the queue if it's active */ 3117 ring->wptr = 0; 3118 mqd->cp_hqd_dequeue_request = 0; 3119 mqd->cp_hqd_pq_rptr = 0; 3120 mqd->cp_hqd_pq_wptr_lo = 0; 3121 mqd->cp_hqd_pq_wptr_hi = 0; 3122 3123 /* set the pointer to the MQD */ 3124 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3125 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3126 3127 /* set MQD vmid to 0 */ 3128 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3129 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3130 mqd->cp_mqd_control = tmp; 3131 3132 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3133 hqd_gpu_addr = ring->gpu_addr >> 8; 3134 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3135 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3136 3137 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3138 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3139 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3140 (order_base_2(ring->ring_size / 4) - 1)); 3141 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3142 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3143 #ifdef __BIG_ENDIAN 3144 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3145 #endif 3146 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3147 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3148 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3149 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3150 mqd->cp_hqd_pq_control = tmp; 3151 3152 /* set the wb address whether it's enabled or not */ 3153 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3154 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3155 mqd->cp_hqd_pq_rptr_report_addr_hi = 3156 upper_32_bits(wb_gpu_addr) & 0xffff; 3157 3158 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3159 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3160 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3161 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3162 3163 tmp = 0; 3164 /* enable the doorbell if requested */ 3165 if (ring->use_doorbell) { 3166 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3167 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3168 DOORBELL_OFFSET, ring->doorbell_index); 3169 3170 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3171 DOORBELL_EN, 1); 3172 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3173 DOORBELL_SOURCE, 0); 3174 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3175 DOORBELL_HIT, 0); 3176 } 3177 3178 mqd->cp_hqd_pq_doorbell_control = tmp; 3179 3180 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3181 ring->wptr = 0; 3182 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3183 3184 /* set the vmid for the queue */ 3185 mqd->cp_hqd_vmid = 0; 3186 3187 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3188 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3189 mqd->cp_hqd_persistent_state = tmp; 3190 3191 /* set MIN_IB_AVAIL_SIZE */ 3192 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3193 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3194 mqd->cp_hqd_ib_control = tmp; 3195 3196 /* activate the queue */ 3197 mqd->cp_hqd_active = 1; 3198 3199 return 0; 3200 } 3201 3202 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 3203 { 3204 struct amdgpu_device *adev = ring->adev; 3205 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3206 int j; 3207 3208 /* disable wptr polling */ 3209 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3210 3211 /* write the EOP addr */ 3212 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3213 mqd->cp_hqd_eop_base_addr_lo); 3214 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3215 mqd->cp_hqd_eop_base_addr_hi); 3216 3217 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3218 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 3219 mqd->cp_hqd_eop_control); 3220 3221 /* enable doorbell? */ 3222 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3223 mqd->cp_hqd_pq_doorbell_control); 3224 3225 /* disable the queue if it's active */ 3226 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3227 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3228 for (j = 0; j < adev->usec_timeout; j++) { 3229 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3230 break; 3231 udelay(1); 3232 } 3233 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3234 mqd->cp_hqd_dequeue_request); 3235 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 3236 mqd->cp_hqd_pq_rptr); 3237 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3238 mqd->cp_hqd_pq_wptr_lo); 3239 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3240 mqd->cp_hqd_pq_wptr_hi); 3241 } 3242 3243 /* set the pointer to the MQD */ 3244 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 3245 mqd->cp_mqd_base_addr_lo); 3246 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3247 mqd->cp_mqd_base_addr_hi); 3248 3249 /* set MQD vmid to 0 */ 3250 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 3251 mqd->cp_mqd_control); 3252 3253 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3254 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 3255 mqd->cp_hqd_pq_base_lo); 3256 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 3257 mqd->cp_hqd_pq_base_hi); 3258 3259 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3260 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 3261 mqd->cp_hqd_pq_control); 3262 3263 /* set the wb address whether it's enabled or not */ 3264 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3265 mqd->cp_hqd_pq_rptr_report_addr_lo); 3266 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3267 mqd->cp_hqd_pq_rptr_report_addr_hi); 3268 3269 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3270 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3271 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3272 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3273 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3274 3275 /* enable the doorbell if requested */ 3276 if (ring->use_doorbell) { 3277 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3278 (adev->doorbell_index.kiq * 2) << 2); 3279 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3280 (adev->doorbell_index.userqueue_end * 2) << 2); 3281 } 3282 3283 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3284 mqd->cp_hqd_pq_doorbell_control); 3285 3286 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3287 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3288 mqd->cp_hqd_pq_wptr_lo); 3289 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3290 mqd->cp_hqd_pq_wptr_hi); 3291 3292 /* set the vmid for the queue */ 3293 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3294 3295 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3296 mqd->cp_hqd_persistent_state); 3297 3298 /* activate the queue */ 3299 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 3300 mqd->cp_hqd_active); 3301 3302 if (ring->use_doorbell) 3303 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3304 3305 return 0; 3306 } 3307 3308 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 3309 { 3310 struct amdgpu_device *adev = ring->adev; 3311 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3312 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3313 3314 gfx_v10_0_kiq_setting(ring); 3315 3316 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3317 /* reset MQD to a clean status */ 3318 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3319 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3320 3321 /* reset ring buffer */ 3322 ring->wptr = 0; 3323 amdgpu_ring_clear_ring(ring); 3324 3325 mutex_lock(&adev->srbm_mutex); 3326 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3327 gfx_v10_0_kiq_init_register(ring); 3328 nv_grbm_select(adev, 0, 0, 0, 0); 3329 mutex_unlock(&adev->srbm_mutex); 3330 } else { 3331 memset((void *)mqd, 0, sizeof(*mqd)); 3332 mutex_lock(&adev->srbm_mutex); 3333 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3334 gfx_v10_0_compute_mqd_init(ring); 3335 gfx_v10_0_kiq_init_register(ring); 3336 nv_grbm_select(adev, 0, 0, 0, 0); 3337 mutex_unlock(&adev->srbm_mutex); 3338 3339 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3340 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3341 } 3342 3343 return 0; 3344 } 3345 3346 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 3347 { 3348 struct amdgpu_device *adev = ring->adev; 3349 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3350 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3351 3352 if (!adev->in_gpu_reset && !adev->in_suspend) { 3353 memset((void *)mqd, 0, sizeof(*mqd)); 3354 mutex_lock(&adev->srbm_mutex); 3355 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3356 gfx_v10_0_compute_mqd_init(ring); 3357 nv_grbm_select(adev, 0, 0, 0, 0); 3358 mutex_unlock(&adev->srbm_mutex); 3359 3360 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3361 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3362 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3363 /* reset MQD to a clean status */ 3364 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3365 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3366 3367 /* reset ring buffer */ 3368 ring->wptr = 0; 3369 amdgpu_ring_clear_ring(ring); 3370 } else { 3371 amdgpu_ring_clear_ring(ring); 3372 } 3373 3374 return 0; 3375 } 3376 3377 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 3378 { 3379 struct amdgpu_ring *ring; 3380 int r; 3381 3382 ring = &adev->gfx.kiq.ring; 3383 3384 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3385 if (unlikely(r != 0)) 3386 return r; 3387 3388 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3389 if (unlikely(r != 0)) 3390 return r; 3391 3392 gfx_v10_0_kiq_init_queue(ring); 3393 amdgpu_bo_kunmap(ring->mqd_obj); 3394 ring->mqd_ptr = NULL; 3395 amdgpu_bo_unreserve(ring->mqd_obj); 3396 ring->sched.ready = true; 3397 return 0; 3398 } 3399 3400 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 3401 { 3402 struct amdgpu_ring *ring = NULL; 3403 int r = 0, i; 3404 3405 gfx_v10_0_cp_compute_enable(adev, true); 3406 3407 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3408 ring = &adev->gfx.compute_ring[i]; 3409 3410 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3411 if (unlikely(r != 0)) 3412 goto done; 3413 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3414 if (!r) { 3415 r = gfx_v10_0_kcq_init_queue(ring); 3416 amdgpu_bo_kunmap(ring->mqd_obj); 3417 ring->mqd_ptr = NULL; 3418 } 3419 amdgpu_bo_unreserve(ring->mqd_obj); 3420 if (r) 3421 goto done; 3422 } 3423 3424 r = amdgpu_gfx_enable_kcq(adev); 3425 done: 3426 return r; 3427 } 3428 3429 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 3430 { 3431 int r, i; 3432 struct amdgpu_ring *ring; 3433 3434 if (!(adev->flags & AMD_IS_APU)) 3435 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3436 3437 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3438 /* legacy firmware loading */ 3439 r = gfx_v10_0_cp_gfx_load_microcode(adev); 3440 if (r) 3441 return r; 3442 3443 r = gfx_v10_0_cp_compute_load_microcode(adev); 3444 if (r) 3445 return r; 3446 } 3447 3448 r = gfx_v10_0_kiq_resume(adev); 3449 if (r) 3450 return r; 3451 3452 r = gfx_v10_0_kcq_resume(adev); 3453 if (r) 3454 return r; 3455 3456 if (!amdgpu_async_gfx_ring) { 3457 r = gfx_v10_0_cp_gfx_resume(adev); 3458 if (r) 3459 return r; 3460 } else { 3461 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 3462 if (r) 3463 return r; 3464 } 3465 3466 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3467 ring = &adev->gfx.gfx_ring[i]; 3468 DRM_INFO("gfx %d ring me %d pipe %d q %d\n", 3469 i, ring->me, ring->pipe, ring->queue); 3470 r = amdgpu_ring_test_ring(ring); 3471 if (r) { 3472 ring->sched.ready = false; 3473 return r; 3474 } 3475 } 3476 3477 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3478 ring = &adev->gfx.compute_ring[i]; 3479 ring->sched.ready = true; 3480 DRM_INFO("compute ring %d mec %d pipe %d q %d\n", 3481 i, ring->me, ring->pipe, ring->queue); 3482 r = amdgpu_ring_test_ring(ring); 3483 if (r) 3484 ring->sched.ready = false; 3485 } 3486 3487 return 0; 3488 } 3489 3490 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 3491 { 3492 gfx_v10_0_cp_gfx_enable(adev, enable); 3493 gfx_v10_0_cp_compute_enable(adev, enable); 3494 } 3495 3496 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 3497 { 3498 uint32_t data, pattern = 0xDEADBEEF; 3499 3500 /* check if mmVGT_ESGS_RING_SIZE_UMD 3501 * has been remapped to mmVGT_ESGS_RING_SIZE */ 3502 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 3503 3504 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 3505 3506 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 3507 3508 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 3509 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 3510 return true; 3511 } else { 3512 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 3513 return false; 3514 } 3515 } 3516 3517 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 3518 { 3519 uint32_t data; 3520 3521 /* initialize cam_index to 0 3522 * index will auto-inc after each data writting */ 3523 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 3524 3525 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 3526 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 3527 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3528 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 3529 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3530 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3531 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3532 3533 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 3534 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 3535 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3536 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 3537 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3538 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3539 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3540 3541 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 3542 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 3543 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3544 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 3545 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3546 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3547 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3548 3549 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 3550 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 3551 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3552 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 3553 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3554 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3555 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3556 3557 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 3558 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 3559 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3560 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 3561 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3562 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3563 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3564 3565 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 3566 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 3567 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3568 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 3569 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3570 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3571 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3572 3573 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 3574 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 3575 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3576 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 3577 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3578 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3579 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3580 } 3581 3582 static int gfx_v10_0_hw_init(void *handle) 3583 { 3584 int r; 3585 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3586 3587 r = gfx_v10_0_csb_vram_pin(adev); 3588 if (r) 3589 return r; 3590 3591 if (!amdgpu_emu_mode) 3592 gfx_v10_0_init_golden_registers(adev); 3593 3594 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3595 /** 3596 * For gfx 10, rlc firmware loading relies on smu firmware is 3597 * loaded firstly, so in direct type, it has to load smc ucode 3598 * here before rlc. 3599 */ 3600 r = smu_load_microcode(&adev->smu); 3601 if (r) 3602 return r; 3603 3604 r = smu_check_fw_status(&adev->smu); 3605 if (r) { 3606 pr_err("SMC firmware status is not correct\n"); 3607 return r; 3608 } 3609 } 3610 3611 /* if GRBM CAM not remapped, set up the remapping */ 3612 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 3613 gfx_v10_0_setup_grbm_cam_remapping(adev); 3614 3615 gfx_v10_0_constants_init(adev); 3616 3617 r = gfx_v10_0_rlc_resume(adev); 3618 if (r) 3619 return r; 3620 3621 /* 3622 * init golden registers and rlc resume may override some registers, 3623 * reconfig them here 3624 */ 3625 gfx_v10_0_tcp_harvest(adev); 3626 3627 r = gfx_v10_0_cp_resume(adev); 3628 if (r) 3629 return r; 3630 3631 return r; 3632 } 3633 3634 #ifndef BRING_UP_DEBUG 3635 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 3636 { 3637 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3638 struct amdgpu_ring *kiq_ring = &kiq->ring; 3639 int i; 3640 3641 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3642 return -EINVAL; 3643 3644 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 3645 adev->gfx.num_gfx_rings)) 3646 return -ENOMEM; 3647 3648 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3649 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 3650 PREEMPT_QUEUES, 0, 0); 3651 3652 return amdgpu_ring_test_ring(kiq_ring); 3653 } 3654 #endif 3655 3656 static int gfx_v10_0_hw_fini(void *handle) 3657 { 3658 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3659 int r; 3660 3661 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3662 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3663 #ifndef BRING_UP_DEBUG 3664 if (amdgpu_async_gfx_ring) { 3665 r = gfx_v10_0_kiq_disable_kgq(adev); 3666 if (r) 3667 DRM_ERROR("KGQ disable failed\n"); 3668 } 3669 #endif 3670 if (amdgpu_gfx_disable_kcq(adev)) 3671 DRM_ERROR("KCQ disable failed\n"); 3672 if (amdgpu_sriov_vf(adev)) { 3673 pr_debug("For SRIOV client, shouldn't do anything.\n"); 3674 return 0; 3675 } 3676 gfx_v10_0_cp_enable(adev, false); 3677 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3678 gfx_v10_0_csb_vram_unpin(adev); 3679 3680 return 0; 3681 } 3682 3683 static int gfx_v10_0_suspend(void *handle) 3684 { 3685 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3686 3687 adev->in_suspend = true; 3688 return gfx_v10_0_hw_fini(adev); 3689 } 3690 3691 static int gfx_v10_0_resume(void *handle) 3692 { 3693 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3694 int r; 3695 3696 r = gfx_v10_0_hw_init(adev); 3697 adev->in_suspend = false; 3698 return r; 3699 } 3700 3701 static bool gfx_v10_0_is_idle(void *handle) 3702 { 3703 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3704 3705 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3706 GRBM_STATUS, GUI_ACTIVE)) 3707 return false; 3708 else 3709 return true; 3710 } 3711 3712 static int gfx_v10_0_wait_for_idle(void *handle) 3713 { 3714 unsigned i; 3715 u32 tmp; 3716 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3717 3718 for (i = 0; i < adev->usec_timeout; i++) { 3719 /* read MC_STATUS */ 3720 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 3721 GRBM_STATUS__GUI_ACTIVE_MASK; 3722 3723 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3724 return 0; 3725 udelay(1); 3726 } 3727 return -ETIMEDOUT; 3728 } 3729 3730 static int gfx_v10_0_soft_reset(void *handle) 3731 { 3732 u32 grbm_soft_reset = 0; 3733 u32 tmp; 3734 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3735 3736 /* GRBM_STATUS */ 3737 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3738 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3739 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3740 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 3741 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 3742 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK 3743 | GRBM_STATUS__BCI_BUSY_MASK)) { 3744 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3745 GRBM_SOFT_RESET, SOFT_RESET_CP, 3746 1); 3747 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3748 GRBM_SOFT_RESET, SOFT_RESET_GFX, 3749 1); 3750 } 3751 3752 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3753 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3754 GRBM_SOFT_RESET, SOFT_RESET_CP, 3755 1); 3756 } 3757 3758 /* GRBM_STATUS2 */ 3759 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3760 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3761 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3762 GRBM_SOFT_RESET, SOFT_RESET_RLC, 3763 1); 3764 3765 if (grbm_soft_reset) { 3766 /* stop the rlc */ 3767 gfx_v10_0_rlc_stop(adev); 3768 3769 /* Disable GFX parsing/prefetching */ 3770 gfx_v10_0_cp_gfx_enable(adev, false); 3771 3772 /* Disable MEC parsing/prefetching */ 3773 gfx_v10_0_cp_compute_enable(adev, false); 3774 3775 if (grbm_soft_reset) { 3776 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3777 tmp |= grbm_soft_reset; 3778 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3779 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3780 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3781 3782 udelay(50); 3783 3784 tmp &= ~grbm_soft_reset; 3785 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3786 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3787 } 3788 3789 /* Wait a little for things to settle down */ 3790 udelay(50); 3791 } 3792 return 0; 3793 } 3794 3795 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3796 { 3797 uint64_t clock; 3798 3799 mutex_lock(&adev->gfx.gpu_clock_mutex); 3800 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3801 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3802 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3803 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3804 return clock; 3805 } 3806 3807 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3808 uint32_t vmid, 3809 uint32_t gds_base, uint32_t gds_size, 3810 uint32_t gws_base, uint32_t gws_size, 3811 uint32_t oa_base, uint32_t oa_size) 3812 { 3813 struct amdgpu_device *adev = ring->adev; 3814 3815 /* GDS Base */ 3816 gfx_v10_0_write_data_to_reg(ring, 0, false, 3817 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 3818 gds_base); 3819 3820 /* GDS Size */ 3821 gfx_v10_0_write_data_to_reg(ring, 0, false, 3822 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 3823 gds_size); 3824 3825 /* GWS */ 3826 gfx_v10_0_write_data_to_reg(ring, 0, false, 3827 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 3828 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3829 3830 /* OA */ 3831 gfx_v10_0_write_data_to_reg(ring, 0, false, 3832 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 3833 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3834 } 3835 3836 static int gfx_v10_0_early_init(void *handle) 3837 { 3838 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3839 3840 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS; 3841 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 3842 3843 gfx_v10_0_set_kiq_pm4_funcs(adev); 3844 gfx_v10_0_set_ring_funcs(adev); 3845 gfx_v10_0_set_irq_funcs(adev); 3846 gfx_v10_0_set_gds_init(adev); 3847 gfx_v10_0_set_rlc_funcs(adev); 3848 3849 return 0; 3850 } 3851 3852 static int gfx_v10_0_late_init(void *handle) 3853 { 3854 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3855 int r; 3856 3857 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3858 if (r) 3859 return r; 3860 3861 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3862 if (r) 3863 return r; 3864 3865 return 0; 3866 } 3867 3868 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 3869 { 3870 uint32_t rlc_cntl; 3871 3872 /* if RLC is not enabled, do nothing */ 3873 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3874 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3875 } 3876 3877 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 3878 { 3879 uint32_t data; 3880 unsigned i; 3881 3882 data = RLC_SAFE_MODE__CMD_MASK; 3883 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3884 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3885 3886 /* wait for RLC_SAFE_MODE */ 3887 for (i = 0; i < adev->usec_timeout; i++) { 3888 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3889 break; 3890 udelay(1); 3891 } 3892 } 3893 3894 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 3895 { 3896 uint32_t data; 3897 3898 data = RLC_SAFE_MODE__CMD_MASK; 3899 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3900 } 3901 3902 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3903 bool enable) 3904 { 3905 uint32_t data, def; 3906 3907 /* It is disabled by HW by default */ 3908 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3909 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3910 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3911 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3912 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3913 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3914 3915 /* only for Vega10 & Raven1 */ 3916 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 3917 3918 if (def != data) 3919 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3920 3921 /* MGLS is a global flag to control all MGLS in GFX */ 3922 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3923 /* 2 - RLC memory Light sleep */ 3924 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 3925 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3926 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3927 if (def != data) 3928 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3929 } 3930 /* 3 - CP memory Light sleep */ 3931 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3932 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3933 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3934 if (def != data) 3935 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3936 } 3937 } 3938 } else { 3939 /* 1 - MGCG_OVERRIDE */ 3940 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3941 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3942 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3943 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3944 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3945 if (def != data) 3946 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3947 3948 /* 2 - disable MGLS in RLC */ 3949 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3950 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3951 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3952 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3953 } 3954 3955 /* 3 - disable MGLS in CP */ 3956 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3957 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3958 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3959 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3960 } 3961 } 3962 } 3963 3964 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 3965 bool enable) 3966 { 3967 uint32_t data, def; 3968 3969 /* Enable 3D CGCG/CGLS */ 3970 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3971 /* write cmd to clear cgcg/cgls ov */ 3972 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3973 /* unset CGCG override */ 3974 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3975 /* update CGCG and CGLS override bits */ 3976 if (def != data) 3977 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3978 /* enable 3Dcgcg FSM(0x0000363f) */ 3979 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3980 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3981 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3982 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3983 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3984 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3985 if (def != data) 3986 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3987 3988 /* set IDLE_POLL_COUNT(0x00900100) */ 3989 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3990 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3991 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3992 if (def != data) 3993 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3994 } else { 3995 /* Disable CGCG/CGLS */ 3996 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3997 /* disable cgcg, cgls should be disabled */ 3998 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 3999 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4000 /* disable cgcg and cgls in FSM */ 4001 if (def != data) 4002 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4003 } 4004 } 4005 4006 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4007 bool enable) 4008 { 4009 uint32_t def, data; 4010 4011 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4012 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4013 /* unset CGCG override */ 4014 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4015 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4016 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4017 else 4018 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4019 /* update CGCG and CGLS override bits */ 4020 if (def != data) 4021 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4022 4023 /* enable cgcg FSM(0x0000363F) */ 4024 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4025 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4026 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4027 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4028 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4029 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4030 if (def != data) 4031 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4032 4033 /* set IDLE_POLL_COUNT(0x00900100) */ 4034 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4035 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4036 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4037 if (def != data) 4038 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4039 } else { 4040 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4041 /* reset CGCG/CGLS bits */ 4042 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4043 /* disable cgcg and cgls in FSM */ 4044 if (def != data) 4045 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4046 } 4047 } 4048 4049 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4050 bool enable) 4051 { 4052 amdgpu_gfx_rlc_enter_safe_mode(adev); 4053 4054 if (enable) { 4055 /* CGCG/CGLS should be enabled after MGCG/MGLS 4056 * === MGCG + MGLS === 4057 */ 4058 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4059 /* === CGCG /CGLS for GFX 3D Only === */ 4060 gfx_v10_0_update_3d_clock_gating(adev, enable); 4061 /* === CGCG + CGLS === */ 4062 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4063 } else { 4064 /* CGCG/CGLS should be disabled before MGCG/MGLS 4065 * === CGCG + CGLS === 4066 */ 4067 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4068 /* === CGCG /CGLS for GFX 3D Only === */ 4069 gfx_v10_0_update_3d_clock_gating(adev, enable); 4070 /* === MGCG + MGLS === */ 4071 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4072 } 4073 4074 if (adev->cg_flags & 4075 (AMD_CG_SUPPORT_GFX_MGCG | 4076 AMD_CG_SUPPORT_GFX_CGLS | 4077 AMD_CG_SUPPORT_GFX_CGCG | 4078 AMD_CG_SUPPORT_GFX_CGLS | 4079 AMD_CG_SUPPORT_GFX_3D_CGCG | 4080 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4081 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 4082 4083 amdgpu_gfx_rlc_exit_safe_mode(adev); 4084 4085 return 0; 4086 } 4087 4088 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 4089 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 4090 .set_safe_mode = gfx_v10_0_set_safe_mode, 4091 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 4092 .init = gfx_v10_0_rlc_init, 4093 .get_csb_size = gfx_v10_0_get_csb_size, 4094 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 4095 .resume = gfx_v10_0_rlc_resume, 4096 .stop = gfx_v10_0_rlc_stop, 4097 .reset = gfx_v10_0_rlc_reset, 4098 .start = gfx_v10_0_rlc_start 4099 }; 4100 4101 static int gfx_v10_0_set_powergating_state(void *handle, 4102 enum amd_powergating_state state) 4103 { 4104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4105 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 4106 switch (adev->asic_type) { 4107 case CHIP_NAVI10: 4108 case CHIP_NAVI14: 4109 if (!enable) { 4110 amdgpu_gfx_off_ctrl(adev, false); 4111 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 4112 } else 4113 amdgpu_gfx_off_ctrl(adev, true); 4114 break; 4115 default: 4116 break; 4117 } 4118 return 0; 4119 } 4120 4121 static int gfx_v10_0_set_clockgating_state(void *handle, 4122 enum amd_clockgating_state state) 4123 { 4124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4125 4126 switch (adev->asic_type) { 4127 case CHIP_NAVI10: 4128 case CHIP_NAVI14: 4129 gfx_v10_0_update_gfx_clock_gating(adev, 4130 state == AMD_CG_STATE_GATE ? true : false); 4131 break; 4132 default: 4133 break; 4134 } 4135 return 0; 4136 } 4137 4138 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 4139 { 4140 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4141 int data; 4142 4143 /* AMD_CG_SUPPORT_GFX_MGCG */ 4144 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4145 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4146 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4147 4148 /* AMD_CG_SUPPORT_GFX_CGCG */ 4149 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4150 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4151 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4152 4153 /* AMD_CG_SUPPORT_GFX_CGLS */ 4154 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4155 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4156 4157 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 4158 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4159 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 4160 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 4161 4162 /* AMD_CG_SUPPORT_GFX_CP_LS */ 4163 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4164 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 4165 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 4166 4167 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4168 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4169 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4170 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4171 4172 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4173 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4174 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4175 } 4176 4177 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4178 { 4179 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 4180 } 4181 4182 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4183 { 4184 struct amdgpu_device *adev = ring->adev; 4185 u64 wptr; 4186 4187 /* XXX check if swapping is necessary on BE */ 4188 if (ring->use_doorbell) { 4189 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 4190 } else { 4191 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 4192 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 4193 } 4194 4195 return wptr; 4196 } 4197 4198 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4199 { 4200 struct amdgpu_device *adev = ring->adev; 4201 4202 if (ring->use_doorbell) { 4203 /* XXX check if swapping is necessary on BE */ 4204 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4205 WDOORBELL64(ring->doorbell_index, ring->wptr); 4206 } else { 4207 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4208 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 4209 } 4210 } 4211 4212 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4213 { 4214 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 4215 } 4216 4217 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4218 { 4219 u64 wptr; 4220 4221 /* XXX check if swapping is necessary on BE */ 4222 if (ring->use_doorbell) 4223 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 4224 else 4225 BUG(); 4226 return wptr; 4227 } 4228 4229 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4230 { 4231 struct amdgpu_device *adev = ring->adev; 4232 4233 /* XXX check if swapping is necessary on BE */ 4234 if (ring->use_doorbell) { 4235 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4236 WDOORBELL64(ring->doorbell_index, ring->wptr); 4237 } else { 4238 BUG(); /* only DOORBELL method supported on gfx10 now */ 4239 } 4240 } 4241 4242 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4243 { 4244 struct amdgpu_device *adev = ring->adev; 4245 u32 ref_and_mask, reg_mem_engine; 4246 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 4247 4248 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4249 switch (ring->me) { 4250 case 1: 4251 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4252 break; 4253 case 2: 4254 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4255 break; 4256 default: 4257 return; 4258 } 4259 reg_mem_engine = 0; 4260 } else { 4261 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4262 reg_mem_engine = 1; /* pfp */ 4263 } 4264 4265 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4266 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 4267 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 4268 ref_and_mask, ref_and_mask, 0x20); 4269 } 4270 4271 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4272 struct amdgpu_job *job, 4273 struct amdgpu_ib *ib, 4274 uint32_t flags) 4275 { 4276 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4277 u32 header, control = 0; 4278 4279 /* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS. 4280 * This resets the wave ID counters. (needed by transform feedback) 4281 * TODO: This might only be needed on a VMID switch when we change 4282 * the GDS OA mapping, not sure. 4283 */ 4284 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4285 amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID); 4286 amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id); 4287 4288 if (ib->flags & AMDGPU_IB_FLAG_CE) 4289 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 4290 else 4291 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4292 4293 control |= ib->length_dw | (vmid << 24); 4294 4295 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 4296 control |= INDIRECT_BUFFER_PRE_ENB(1); 4297 4298 if (flags & AMDGPU_IB_PREEMPTED) 4299 control |= INDIRECT_BUFFER_PRE_RESUME(1); 4300 4301 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 4302 gfx_v10_0_ring_emit_de_meta(ring, 4303 flags & AMDGPU_IB_PREEMPTED ? true : false); 4304 } 4305 4306 amdgpu_ring_write(ring, header); 4307 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4308 amdgpu_ring_write(ring, 4309 #ifdef __BIG_ENDIAN 4310 (2 << 0) | 4311 #endif 4312 lower_32_bits(ib->gpu_addr)); 4313 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4314 amdgpu_ring_write(ring, control); 4315 } 4316 4317 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4318 struct amdgpu_job *job, 4319 struct amdgpu_ib *ib, 4320 uint32_t flags) 4321 { 4322 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4323 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4324 4325 /* Currently, there is a high possibility to get wave ID mismatch 4326 * between ME and GDS, leading to a hw deadlock, because ME generates 4327 * different wave IDs than the GDS expects. This situation happens 4328 * randomly when at least 5 compute pipes use GDS ordered append. 4329 * The wave IDs generated by ME are also wrong after suspend/resume. 4330 * Those are probably bugs somewhere else in the kernel driver. 4331 * 4332 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 4333 * GDS to 0 for this ring (me/pipe). 4334 */ 4335 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 4336 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4337 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 4338 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 4339 } 4340 4341 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4342 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4343 amdgpu_ring_write(ring, 4344 #ifdef __BIG_ENDIAN 4345 (2 << 0) | 4346 #endif 4347 lower_32_bits(ib->gpu_addr)); 4348 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4349 amdgpu_ring_write(ring, control); 4350 } 4351 4352 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4353 u64 seq, unsigned flags) 4354 { 4355 struct amdgpu_device *adev = ring->adev; 4356 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4357 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4358 4359 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 4360 if (adev->pdev->device == 0x50) 4361 int_sel = false; 4362 4363 /* RELEASE_MEM - flush caches, send int */ 4364 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4365 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4366 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4367 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 4368 PACKET3_RELEASE_MEM_GCR_GLM_WB | 4369 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4370 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4371 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4372 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4373 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4374 4375 /* 4376 * the address should be Qword aligned if 64bit write, Dword 4377 * aligned if only send 32bit data low (discard data high) 4378 */ 4379 if (write64bit) 4380 BUG_ON(addr & 0x7); 4381 else 4382 BUG_ON(addr & 0x3); 4383 amdgpu_ring_write(ring, lower_32_bits(addr)); 4384 amdgpu_ring_write(ring, upper_32_bits(addr)); 4385 amdgpu_ring_write(ring, lower_32_bits(seq)); 4386 amdgpu_ring_write(ring, upper_32_bits(seq)); 4387 amdgpu_ring_write(ring, 0); 4388 } 4389 4390 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4391 { 4392 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4393 uint32_t seq = ring->fence_drv.sync_seq; 4394 uint64_t addr = ring->fence_drv.gpu_addr; 4395 4396 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4397 upper_32_bits(addr), seq, 0xffffffff, 4); 4398 } 4399 4400 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4401 unsigned vmid, uint64_t pd_addr) 4402 { 4403 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4404 4405 /* compute doesn't have PFP */ 4406 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4407 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4408 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4409 amdgpu_ring_write(ring, 0x0); 4410 } 4411 } 4412 4413 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4414 u64 seq, unsigned int flags) 4415 { 4416 struct amdgpu_device *adev = ring->adev; 4417 4418 /* we only allocate 32bit for each seq wb address */ 4419 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4420 4421 /* write fence seq to the "addr" */ 4422 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4423 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4424 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4425 amdgpu_ring_write(ring, lower_32_bits(addr)); 4426 amdgpu_ring_write(ring, upper_32_bits(addr)); 4427 amdgpu_ring_write(ring, lower_32_bits(seq)); 4428 4429 if (flags & AMDGPU_FENCE_FLAG_INT) { 4430 /* set register to trigger INT */ 4431 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4432 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4433 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4434 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 4435 amdgpu_ring_write(ring, 0); 4436 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4437 } 4438 } 4439 4440 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 4441 { 4442 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4443 amdgpu_ring_write(ring, 0); 4444 } 4445 4446 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 4447 { 4448 uint32_t dw2 = 0; 4449 4450 if (amdgpu_mcbp) 4451 gfx_v10_0_ring_emit_ce_meta(ring, 4452 flags & AMDGPU_IB_PREEMPTED ? true : false); 4453 4454 gfx_v10_0_ring_emit_tmz(ring, true); 4455 4456 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4457 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4458 /* set load_global_config & load_global_uconfig */ 4459 dw2 |= 0x8001; 4460 /* set load_cs_sh_regs */ 4461 dw2 |= 0x01000000; 4462 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4463 dw2 |= 0x10002; 4464 4465 /* set load_ce_ram if preamble presented */ 4466 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 4467 dw2 |= 0x10000000; 4468 } else { 4469 /* still load_ce_ram if this is the first time preamble presented 4470 * although there is no context switch happens. 4471 */ 4472 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 4473 dw2 |= 0x10000000; 4474 } 4475 4476 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4477 amdgpu_ring_write(ring, dw2); 4478 amdgpu_ring_write(ring, 0); 4479 } 4480 4481 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 4482 { 4483 unsigned ret; 4484 4485 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4486 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 4487 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 4488 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 4489 ret = ring->wptr & ring->buf_mask; 4490 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 4491 4492 return ret; 4493 } 4494 4495 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 4496 { 4497 unsigned cur; 4498 BUG_ON(offset > ring->buf_mask); 4499 BUG_ON(ring->ring[offset] != 0x55aa55aa); 4500 4501 cur = (ring->wptr - 1) & ring->buf_mask; 4502 if (likely(cur > offset)) 4503 ring->ring[offset] = cur - offset; 4504 else 4505 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 4506 } 4507 4508 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 4509 { 4510 int i, r = 0; 4511 struct amdgpu_device *adev = ring->adev; 4512 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4513 struct amdgpu_ring *kiq_ring = &kiq->ring; 4514 4515 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4516 return -EINVAL; 4517 4518 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) 4519 return -ENOMEM; 4520 4521 /* assert preemption condition */ 4522 amdgpu_ring_set_preempt_cond_exec(ring, false); 4523 4524 /* assert IB preemption, emit the trailing fence */ 4525 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4526 ring->trail_fence_gpu_addr, 4527 ++ring->trail_seq); 4528 amdgpu_ring_commit(kiq_ring); 4529 4530 /* poll the trailing fence */ 4531 for (i = 0; i < adev->usec_timeout; i++) { 4532 if (ring->trail_seq == 4533 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4534 break; 4535 DRM_UDELAY(1); 4536 } 4537 4538 if (i >= adev->usec_timeout) { 4539 r = -EINVAL; 4540 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4541 } 4542 4543 /* deassert preemption condition */ 4544 amdgpu_ring_set_preempt_cond_exec(ring, true); 4545 return r; 4546 } 4547 4548 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 4549 { 4550 struct amdgpu_device *adev = ring->adev; 4551 struct v10_ce_ib_state ce_payload = {0}; 4552 uint64_t csa_addr; 4553 int cnt; 4554 4555 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 4556 csa_addr = amdgpu_csa_vaddr(ring->adev); 4557 4558 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4559 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 4560 WRITE_DATA_DST_SEL(8) | 4561 WR_CONFIRM) | 4562 WRITE_DATA_CACHE_POLICY(0)); 4563 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4564 offsetof(struct v10_gfx_meta_data, ce_payload))); 4565 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4566 offsetof(struct v10_gfx_meta_data, ce_payload))); 4567 4568 if (resume) 4569 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4570 offsetof(struct v10_gfx_meta_data, 4571 ce_payload), 4572 sizeof(ce_payload) >> 2); 4573 else 4574 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 4575 sizeof(ce_payload) >> 2); 4576 } 4577 4578 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 4579 { 4580 struct amdgpu_device *adev = ring->adev; 4581 struct v10_de_ib_state de_payload = {0}; 4582 uint64_t csa_addr, gds_addr; 4583 int cnt; 4584 4585 csa_addr = amdgpu_csa_vaddr(ring->adev); 4586 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 4587 PAGE_SIZE); 4588 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 4589 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 4590 4591 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 4592 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4593 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 4594 WRITE_DATA_DST_SEL(8) | 4595 WR_CONFIRM) | 4596 WRITE_DATA_CACHE_POLICY(0)); 4597 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4598 offsetof(struct v10_gfx_meta_data, de_payload))); 4599 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4600 offsetof(struct v10_gfx_meta_data, de_payload))); 4601 4602 if (resume) 4603 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4604 offsetof(struct v10_gfx_meta_data, 4605 de_payload), 4606 sizeof(de_payload) >> 2); 4607 else 4608 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 4609 sizeof(de_payload) >> 2); 4610 } 4611 4612 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 4613 { 4614 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4615 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 4616 } 4617 4618 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 4619 { 4620 struct amdgpu_device *adev = ring->adev; 4621 4622 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4623 amdgpu_ring_write(ring, 0 | /* src: register*/ 4624 (5 << 8) | /* dst: memory */ 4625 (1 << 20)); /* write confirm */ 4626 amdgpu_ring_write(ring, reg); 4627 amdgpu_ring_write(ring, 0); 4628 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4629 adev->virt.reg_val_offs * 4)); 4630 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4631 adev->virt.reg_val_offs * 4)); 4632 } 4633 4634 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 4635 uint32_t val) 4636 { 4637 uint32_t cmd = 0; 4638 4639 switch (ring->funcs->type) { 4640 case AMDGPU_RING_TYPE_GFX: 4641 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4642 break; 4643 case AMDGPU_RING_TYPE_KIQ: 4644 cmd = (1 << 16); /* no inc addr */ 4645 break; 4646 default: 4647 cmd = WR_CONFIRM; 4648 break; 4649 } 4650 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4651 amdgpu_ring_write(ring, cmd); 4652 amdgpu_ring_write(ring, reg); 4653 amdgpu_ring_write(ring, 0); 4654 amdgpu_ring_write(ring, val); 4655 } 4656 4657 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4658 uint32_t val, uint32_t mask) 4659 { 4660 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4661 } 4662 4663 static void 4664 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4665 uint32_t me, uint32_t pipe, 4666 enum amdgpu_interrupt_state state) 4667 { 4668 uint32_t cp_int_cntl, cp_int_cntl_reg; 4669 4670 if (!me) { 4671 switch (pipe) { 4672 case 0: 4673 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 4674 break; 4675 case 1: 4676 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 4677 break; 4678 default: 4679 DRM_DEBUG("invalid pipe %d\n", pipe); 4680 return; 4681 } 4682 } else { 4683 DRM_DEBUG("invalid me %d\n", me); 4684 return; 4685 } 4686 4687 switch (state) { 4688 case AMDGPU_IRQ_STATE_DISABLE: 4689 cp_int_cntl = RREG32(cp_int_cntl_reg); 4690 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4691 TIME_STAMP_INT_ENABLE, 0); 4692 WREG32(cp_int_cntl_reg, cp_int_cntl); 4693 case AMDGPU_IRQ_STATE_ENABLE: 4694 cp_int_cntl = RREG32(cp_int_cntl_reg); 4695 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4696 TIME_STAMP_INT_ENABLE, 1); 4697 WREG32(cp_int_cntl_reg, cp_int_cntl); 4698 break; 4699 default: 4700 break; 4701 } 4702 } 4703 4704 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4705 int me, int pipe, 4706 enum amdgpu_interrupt_state state) 4707 { 4708 u32 mec_int_cntl, mec_int_cntl_reg; 4709 4710 /* 4711 * amdgpu controls only the first MEC. That's why this function only 4712 * handles the setting of interrupts for this specific MEC. All other 4713 * pipes' interrupts are set by amdkfd. 4714 */ 4715 4716 if (me == 1) { 4717 switch (pipe) { 4718 case 0: 4719 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4720 break; 4721 case 1: 4722 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 4723 break; 4724 case 2: 4725 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 4726 break; 4727 case 3: 4728 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 4729 break; 4730 default: 4731 DRM_DEBUG("invalid pipe %d\n", pipe); 4732 return; 4733 } 4734 } else { 4735 DRM_DEBUG("invalid me %d\n", me); 4736 return; 4737 } 4738 4739 switch (state) { 4740 case AMDGPU_IRQ_STATE_DISABLE: 4741 mec_int_cntl = RREG32(mec_int_cntl_reg); 4742 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4743 TIME_STAMP_INT_ENABLE, 0); 4744 WREG32(mec_int_cntl_reg, mec_int_cntl); 4745 break; 4746 case AMDGPU_IRQ_STATE_ENABLE: 4747 mec_int_cntl = RREG32(mec_int_cntl_reg); 4748 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4749 TIME_STAMP_INT_ENABLE, 1); 4750 WREG32(mec_int_cntl_reg, mec_int_cntl); 4751 break; 4752 default: 4753 break; 4754 } 4755 } 4756 4757 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4758 struct amdgpu_irq_src *src, 4759 unsigned type, 4760 enum amdgpu_interrupt_state state) 4761 { 4762 switch (type) { 4763 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4764 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4765 break; 4766 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4767 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4768 break; 4769 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4770 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4771 break; 4772 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4773 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4774 break; 4775 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4776 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4777 break; 4778 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4779 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4780 break; 4781 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4782 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4783 break; 4784 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4785 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4786 break; 4787 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4788 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4789 break; 4790 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4791 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4792 break; 4793 default: 4794 break; 4795 } 4796 return 0; 4797 } 4798 4799 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 4800 struct amdgpu_irq_src *source, 4801 struct amdgpu_iv_entry *entry) 4802 { 4803 int i; 4804 u8 me_id, pipe_id, queue_id; 4805 struct amdgpu_ring *ring; 4806 4807 DRM_DEBUG("IH: CP EOP\n"); 4808 me_id = (entry->ring_id & 0x0c) >> 2; 4809 pipe_id = (entry->ring_id & 0x03) >> 0; 4810 queue_id = (entry->ring_id & 0x70) >> 4; 4811 4812 switch (me_id) { 4813 case 0: 4814 if (pipe_id == 0) 4815 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4816 else 4817 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4818 break; 4819 case 1: 4820 case 2: 4821 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4822 ring = &adev->gfx.compute_ring[i]; 4823 /* Per-queue interrupt is supported for MEC starting from VI. 4824 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4825 */ 4826 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4827 amdgpu_fence_process(ring); 4828 } 4829 break; 4830 } 4831 return 0; 4832 } 4833 4834 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4835 struct amdgpu_irq_src *source, 4836 unsigned type, 4837 enum amdgpu_interrupt_state state) 4838 { 4839 switch (state) { 4840 case AMDGPU_IRQ_STATE_DISABLE: 4841 case AMDGPU_IRQ_STATE_ENABLE: 4842 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4843 PRIV_REG_INT_ENABLE, 4844 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4845 break; 4846 default: 4847 break; 4848 } 4849 4850 return 0; 4851 } 4852 4853 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4854 struct amdgpu_irq_src *source, 4855 unsigned type, 4856 enum amdgpu_interrupt_state state) 4857 { 4858 switch (state) { 4859 case AMDGPU_IRQ_STATE_DISABLE: 4860 case AMDGPU_IRQ_STATE_ENABLE: 4861 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4862 PRIV_INSTR_INT_ENABLE, 4863 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4864 default: 4865 break; 4866 } 4867 4868 return 0; 4869 } 4870 4871 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 4872 struct amdgpu_iv_entry *entry) 4873 { 4874 u8 me_id, pipe_id, queue_id; 4875 struct amdgpu_ring *ring; 4876 int i; 4877 4878 me_id = (entry->ring_id & 0x0c) >> 2; 4879 pipe_id = (entry->ring_id & 0x03) >> 0; 4880 queue_id = (entry->ring_id & 0x70) >> 4; 4881 4882 switch (me_id) { 4883 case 0: 4884 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4885 ring = &adev->gfx.gfx_ring[i]; 4886 /* we only enabled 1 gfx queue per pipe for now */ 4887 if (ring->me == me_id && ring->pipe == pipe_id) 4888 drm_sched_fault(&ring->sched); 4889 } 4890 break; 4891 case 1: 4892 case 2: 4893 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4894 ring = &adev->gfx.compute_ring[i]; 4895 if (ring->me == me_id && ring->pipe == pipe_id && 4896 ring->queue == queue_id) 4897 drm_sched_fault(&ring->sched); 4898 } 4899 break; 4900 default: 4901 BUG(); 4902 } 4903 } 4904 4905 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 4906 struct amdgpu_irq_src *source, 4907 struct amdgpu_iv_entry *entry) 4908 { 4909 DRM_ERROR("Illegal register access in command stream\n"); 4910 gfx_v10_0_handle_priv_fault(adev, entry); 4911 return 0; 4912 } 4913 4914 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 4915 struct amdgpu_irq_src *source, 4916 struct amdgpu_iv_entry *entry) 4917 { 4918 DRM_ERROR("Illegal instruction in command stream\n"); 4919 gfx_v10_0_handle_priv_fault(adev, entry); 4920 return 0; 4921 } 4922 4923 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 4924 struct amdgpu_irq_src *src, 4925 unsigned int type, 4926 enum amdgpu_interrupt_state state) 4927 { 4928 uint32_t tmp, target; 4929 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4930 4931 if (ring->me == 1) 4932 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4933 else 4934 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 4935 target += ring->pipe; 4936 4937 switch (type) { 4938 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 4939 if (state == AMDGPU_IRQ_STATE_DISABLE) { 4940 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4941 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4942 GENERIC2_INT_ENABLE, 0); 4943 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4944 4945 tmp = RREG32(target); 4946 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4947 GENERIC2_INT_ENABLE, 0); 4948 WREG32(target, tmp); 4949 } else { 4950 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4951 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4952 GENERIC2_INT_ENABLE, 1); 4953 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4954 4955 tmp = RREG32(target); 4956 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4957 GENERIC2_INT_ENABLE, 1); 4958 WREG32(target, tmp); 4959 } 4960 break; 4961 default: 4962 BUG(); /* kiq only support GENERIC2_INT now */ 4963 break; 4964 } 4965 return 0; 4966 } 4967 4968 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 4969 struct amdgpu_irq_src *source, 4970 struct amdgpu_iv_entry *entry) 4971 { 4972 u8 me_id, pipe_id, queue_id; 4973 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4974 4975 me_id = (entry->ring_id & 0x0c) >> 2; 4976 pipe_id = (entry->ring_id & 0x03) >> 0; 4977 queue_id = (entry->ring_id & 0x70) >> 4; 4978 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 4979 me_id, pipe_id, queue_id); 4980 4981 amdgpu_fence_process(ring); 4982 return 0; 4983 } 4984 4985 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 4986 .name = "gfx_v10_0", 4987 .early_init = gfx_v10_0_early_init, 4988 .late_init = gfx_v10_0_late_init, 4989 .sw_init = gfx_v10_0_sw_init, 4990 .sw_fini = gfx_v10_0_sw_fini, 4991 .hw_init = gfx_v10_0_hw_init, 4992 .hw_fini = gfx_v10_0_hw_fini, 4993 .suspend = gfx_v10_0_suspend, 4994 .resume = gfx_v10_0_resume, 4995 .is_idle = gfx_v10_0_is_idle, 4996 .wait_for_idle = gfx_v10_0_wait_for_idle, 4997 .soft_reset = gfx_v10_0_soft_reset, 4998 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 4999 .set_powergating_state = gfx_v10_0_set_powergating_state, 5000 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 5001 }; 5002 5003 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 5004 .type = AMDGPU_RING_TYPE_GFX, 5005 .align_mask = 0xff, 5006 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5007 .support_64bit_ptrs = true, 5008 .vmhub = AMDGPU_GFXHUB, 5009 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 5010 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 5011 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 5012 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5013 5 + /* COND_EXEC */ 5014 7 + /* PIPELINE_SYNC */ 5015 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5016 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5017 2 + /* VM_FLUSH */ 5018 8 + /* FENCE for VM_FLUSH */ 5019 20 + /* GDS switch */ 5020 4 + /* double SWITCH_BUFFER, 5021 * the first COND_EXEC jump to the place 5022 * just prior to this double SWITCH_BUFFER 5023 */ 5024 5 + /* COND_EXEC */ 5025 7 + /* HDP_flush */ 5026 4 + /* VGT_flush */ 5027 14 + /* CE_META */ 5028 31 + /* DE_META */ 5029 3 + /* CNTX_CTRL */ 5030 5 + /* HDP_INVL */ 5031 8 + 8 + /* FENCE x2 */ 5032 2, /* SWITCH_BUFFER */ 5033 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_gfx */ 5034 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 5035 .emit_fence = gfx_v10_0_ring_emit_fence, 5036 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5037 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5038 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5039 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5040 .test_ring = gfx_v10_0_ring_test_ring, 5041 .test_ib = gfx_v10_0_ring_test_ib, 5042 .insert_nop = amdgpu_ring_insert_nop, 5043 .pad_ib = amdgpu_ring_generic_pad_ib, 5044 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 5045 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 5046 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 5047 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 5048 .preempt_ib = gfx_v10_0_ring_preempt_ib, 5049 .emit_tmz = gfx_v10_0_ring_emit_tmz, 5050 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5051 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5052 }; 5053 5054 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 5055 .type = AMDGPU_RING_TYPE_COMPUTE, 5056 .align_mask = 0xff, 5057 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5058 .support_64bit_ptrs = true, 5059 .vmhub = AMDGPU_GFXHUB, 5060 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5061 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5062 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5063 .emit_frame_size = 5064 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5065 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5066 5 + /* hdp invalidate */ 5067 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5068 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5069 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5070 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5071 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 5072 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5073 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5074 .emit_fence = gfx_v10_0_ring_emit_fence, 5075 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5076 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5077 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5078 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5079 .test_ring = gfx_v10_0_ring_test_ring, 5080 .test_ib = gfx_v10_0_ring_test_ib, 5081 .insert_nop = amdgpu_ring_insert_nop, 5082 .pad_ib = amdgpu_ring_generic_pad_ib, 5083 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5084 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5085 }; 5086 5087 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 5088 .type = AMDGPU_RING_TYPE_KIQ, 5089 .align_mask = 0xff, 5090 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5091 .support_64bit_ptrs = true, 5092 .vmhub = AMDGPU_GFXHUB, 5093 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5094 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5095 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5096 .emit_frame_size = 5097 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5098 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5099 5 + /*hdp invalidate */ 5100 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5101 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5102 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5103 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5104 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5105 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5106 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5107 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 5108 .test_ring = gfx_v10_0_ring_test_ring, 5109 .test_ib = gfx_v10_0_ring_test_ib, 5110 .insert_nop = amdgpu_ring_insert_nop, 5111 .pad_ib = amdgpu_ring_generic_pad_ib, 5112 .emit_rreg = gfx_v10_0_ring_emit_rreg, 5113 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5114 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5115 }; 5116 5117 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 5118 { 5119 int i; 5120 5121 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 5122 5123 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5124 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 5125 5126 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5127 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 5128 } 5129 5130 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 5131 .set = gfx_v10_0_set_eop_interrupt_state, 5132 .process = gfx_v10_0_eop_irq, 5133 }; 5134 5135 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 5136 .set = gfx_v10_0_set_priv_reg_fault_state, 5137 .process = gfx_v10_0_priv_reg_irq, 5138 }; 5139 5140 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 5141 .set = gfx_v10_0_set_priv_inst_fault_state, 5142 .process = gfx_v10_0_priv_inst_irq, 5143 }; 5144 5145 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 5146 .set = gfx_v10_0_kiq_set_interrupt_state, 5147 .process = gfx_v10_0_kiq_irq, 5148 }; 5149 5150 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 5151 { 5152 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5153 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 5154 5155 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 5156 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 5157 5158 adev->gfx.priv_reg_irq.num_types = 1; 5159 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 5160 5161 adev->gfx.priv_inst_irq.num_types = 1; 5162 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 5163 } 5164 5165 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 5166 { 5167 switch (adev->asic_type) { 5168 case CHIP_NAVI10: 5169 case CHIP_NAVI14: 5170 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 5171 break; 5172 default: 5173 break; 5174 } 5175 } 5176 5177 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 5178 { 5179 /* init asic gds info */ 5180 switch (adev->asic_type) { 5181 case CHIP_NAVI10: 5182 default: 5183 adev->gds.gds_size = 0x10000; 5184 adev->gds.gds_compute_max_wave_id = 0x4ff; 5185 adev->gds.vgt_gs_max_wave_id = 0x3ff; 5186 break; 5187 } 5188 5189 adev->gds.gws_size = 64; 5190 adev->gds.oa_size = 16; 5191 } 5192 5193 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5194 u32 bitmap) 5195 { 5196 u32 data; 5197 5198 if (!bitmap) 5199 return; 5200 5201 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5202 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5203 5204 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 5205 } 5206 5207 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5208 { 5209 u32 data, wgp_bitmask; 5210 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 5211 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 5212 5213 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5214 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5215 5216 wgp_bitmask = 5217 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5218 5219 return (~data) & wgp_bitmask; 5220 } 5221 5222 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5223 { 5224 u32 wgp_idx, wgp_active_bitmap; 5225 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5226 5227 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5228 cu_active_bitmap = 0; 5229 5230 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5231 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5232 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5233 if (wgp_active_bitmap & (1 << wgp_idx)) 5234 cu_active_bitmap |= cu_bitmap_per_wgp; 5235 } 5236 5237 return cu_active_bitmap; 5238 } 5239 5240 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 5241 struct amdgpu_cu_info *cu_info) 5242 { 5243 int i, j, k, counter, active_cu_number = 0; 5244 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5245 unsigned disable_masks[4 * 2]; 5246 5247 if (!adev || !cu_info) 5248 return -EINVAL; 5249 5250 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5251 5252 mutex_lock(&adev->grbm_idx_mutex); 5253 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5254 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5255 mask = 1; 5256 ao_bitmap = 0; 5257 counter = 0; 5258 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5259 if (i < 4 && j < 2) 5260 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 5261 adev, disable_masks[i * 2 + j]); 5262 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 5263 cu_info->bitmap[i][j] = bitmap; 5264 5265 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5266 if (bitmap & mask) { 5267 if (counter < adev->gfx.config.max_cu_per_sh) 5268 ao_bitmap |= mask; 5269 counter++; 5270 } 5271 mask <<= 1; 5272 } 5273 active_cu_number += counter; 5274 if (i < 2 && j < 2) 5275 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5276 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5277 } 5278 } 5279 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5280 mutex_unlock(&adev->grbm_idx_mutex); 5281 5282 cu_info->number = active_cu_number; 5283 cu_info->ao_cu_mask = ao_cu_mask; 5284 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5285 5286 return 0; 5287 } 5288 5289 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 5290 { 5291 .type = AMD_IP_BLOCK_TYPE_GFX, 5292 .major = 10, 5293 .minor = 0, 5294 .rev = 0, 5295 .funcs = &gfx_v10_0_ip_funcs, 5296 }; 5297