1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 114 115 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 121 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 125 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 127 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 129 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 131 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 134 135 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 137 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 139 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 141 #define mmCP_HYP_CE_UCODE_DATA 0x5819 142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 143 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 145 #define mmCP_HYP_ME_UCODE_DATA 0x5817 146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 147 148 #define mmCPG_PSP_DEBUG 0x5c10 149 #define mmCPG_PSP_DEBUG_BASE_IDX 1 150 #define mmCPC_PSP_DEBUG 0x5c11 151 #define mmCPC_PSP_DEBUG_BASE_IDX 1 152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 154 155 //CC_GC_SA_UNIT_DISABLE 156 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 160 //GC_USER_SA_UNIT_DISABLE 161 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //PA_SC_ENHANCE_3 166 #define mmPA_SC_ENHANCE_3 0x1085 167 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 170 171 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 173 174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 178 179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 181 182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 184 185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 187 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 191 192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 203 204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 206 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 210 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 217 218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 224 225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 231 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 238 239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 245 246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 252 253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 259 260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 266 267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 273 274 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 315 }; 316 317 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 318 /* Pending on emulation bring up */ 319 }; 320 321 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1374 }; 1375 1376 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1415 }; 1416 1417 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1460 }; 1461 1462 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1463 /* Pending on emulation bring up */ 1464 }; 1465 1466 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2087 }; 2088 2089 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2090 /* Pending on emulation bring up */ 2091 }; 2092 2093 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3146 }; 3147 3148 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3192 }; 3193 3194 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3195 /* Pending on emulation bring up */ 3196 }; 3197 3198 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3240 3241 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3243 }; 3244 3245 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3270 3271 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3273 }; 3274 3275 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3296 }; 3297 3298 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3335 }; 3336 3337 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3370 }; 3371 3372 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3407 }; 3408 3409 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3432 }; 3433 3434 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3457 }; 3458 3459 #define DEFAULT_SH_MEM_CONFIG \ 3460 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3461 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3462 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3463 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3464 3465 /* TODO: pending on golden setting value of gb address config */ 3466 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3467 3468 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3469 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3470 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3471 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3472 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3473 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3474 struct amdgpu_cu_info *cu_info); 3475 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3476 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3477 u32 sh_num, u32 instance, int xcc_id); 3478 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3479 3480 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3481 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3482 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3483 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3484 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3485 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3486 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3487 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3488 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3489 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3490 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3491 uint16_t pasid, uint32_t flush_type, 3492 bool all_hub, uint8_t dst_sel); 3493 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3494 unsigned int vmid); 3495 3496 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3497 { 3498 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3499 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3500 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3501 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3502 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3503 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3504 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3505 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3506 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3507 } 3508 3509 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3510 struct amdgpu_ring *ring) 3511 { 3512 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3513 uint64_t wptr_addr = ring->wptr_gpu_addr; 3514 uint32_t eng_sel = 0; 3515 3516 switch (ring->funcs->type) { 3517 case AMDGPU_RING_TYPE_COMPUTE: 3518 eng_sel = 0; 3519 break; 3520 case AMDGPU_RING_TYPE_GFX: 3521 eng_sel = 4; 3522 break; 3523 case AMDGPU_RING_TYPE_MES: 3524 eng_sel = 5; 3525 break; 3526 default: 3527 WARN_ON(1); 3528 } 3529 3530 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3531 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3532 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3533 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3534 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3535 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3536 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3537 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3538 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3539 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3540 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3541 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3542 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3543 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3544 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3545 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3546 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3547 } 3548 3549 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3550 struct amdgpu_ring *ring, 3551 enum amdgpu_unmap_queues_action action, 3552 u64 gpu_addr, u64 seq) 3553 { 3554 struct amdgpu_device *adev = kiq_ring->adev; 3555 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3556 3557 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 3558 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 3559 return; 3560 } 3561 3562 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3563 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3564 PACKET3_UNMAP_QUEUES_ACTION(action) | 3565 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3566 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3567 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3568 amdgpu_ring_write(kiq_ring, 3569 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3570 3571 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3572 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3573 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3574 amdgpu_ring_write(kiq_ring, seq); 3575 } else { 3576 amdgpu_ring_write(kiq_ring, 0); 3577 amdgpu_ring_write(kiq_ring, 0); 3578 amdgpu_ring_write(kiq_ring, 0); 3579 } 3580 } 3581 3582 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3583 struct amdgpu_ring *ring, 3584 u64 addr, 3585 u64 seq) 3586 { 3587 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3588 3589 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3590 amdgpu_ring_write(kiq_ring, 3591 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3592 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3593 PACKET3_QUERY_STATUS_COMMAND(2)); 3594 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3595 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3596 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3597 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3598 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3599 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3600 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3601 } 3602 3603 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3604 uint16_t pasid, uint32_t flush_type, 3605 bool all_hub) 3606 { 3607 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3608 } 3609 3610 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3611 .kiq_set_resources = gfx10_kiq_set_resources, 3612 .kiq_map_queues = gfx10_kiq_map_queues, 3613 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3614 .kiq_query_status = gfx10_kiq_query_status, 3615 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3616 .set_resources_size = 8, 3617 .map_queues_size = 7, 3618 .unmap_queues_size = 6, 3619 .query_status_size = 7, 3620 .invalidate_tlbs_size = 2, 3621 }; 3622 3623 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3624 { 3625 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3626 } 3627 3628 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3629 { 3630 switch (adev->ip_versions[GC_HWIP][0]) { 3631 case IP_VERSION(10, 1, 10): 3632 soc15_program_register_sequence(adev, 3633 golden_settings_gc_rlc_spm_10_0_nv10, 3634 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3635 break; 3636 case IP_VERSION(10, 1, 1): 3637 soc15_program_register_sequence(adev, 3638 golden_settings_gc_rlc_spm_10_1_nv14, 3639 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3640 break; 3641 case IP_VERSION(10, 1, 2): 3642 soc15_program_register_sequence(adev, 3643 golden_settings_gc_rlc_spm_10_1_2_nv12, 3644 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3645 break; 3646 default: 3647 break; 3648 } 3649 } 3650 3651 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3652 { 3653 switch (adev->ip_versions[GC_HWIP][0]) { 3654 case IP_VERSION(10, 1, 10): 3655 soc15_program_register_sequence(adev, 3656 golden_settings_gc_10_1, 3657 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3658 soc15_program_register_sequence(adev, 3659 golden_settings_gc_10_0_nv10, 3660 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3661 break; 3662 case IP_VERSION(10, 1, 1): 3663 soc15_program_register_sequence(adev, 3664 golden_settings_gc_10_1_1, 3665 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3666 soc15_program_register_sequence(adev, 3667 golden_settings_gc_10_1_nv14, 3668 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3669 break; 3670 case IP_VERSION(10, 1, 2): 3671 soc15_program_register_sequence(adev, 3672 golden_settings_gc_10_1_2, 3673 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3674 soc15_program_register_sequence(adev, 3675 golden_settings_gc_10_1_2_nv12, 3676 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3677 break; 3678 case IP_VERSION(10, 3, 0): 3679 soc15_program_register_sequence(adev, 3680 golden_settings_gc_10_3, 3681 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3682 soc15_program_register_sequence(adev, 3683 golden_settings_gc_10_3_sienna_cichlid, 3684 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3685 break; 3686 case IP_VERSION(10, 3, 2): 3687 soc15_program_register_sequence(adev, 3688 golden_settings_gc_10_3_2, 3689 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3690 break; 3691 case IP_VERSION(10, 3, 1): 3692 soc15_program_register_sequence(adev, 3693 golden_settings_gc_10_3_vangogh, 3694 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3695 break; 3696 case IP_VERSION(10, 3, 3): 3697 soc15_program_register_sequence(adev, 3698 golden_settings_gc_10_3_3, 3699 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3700 break; 3701 case IP_VERSION(10, 3, 4): 3702 soc15_program_register_sequence(adev, 3703 golden_settings_gc_10_3_4, 3704 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3705 break; 3706 case IP_VERSION(10, 3, 5): 3707 soc15_program_register_sequence(adev, 3708 golden_settings_gc_10_3_5, 3709 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3710 break; 3711 case IP_VERSION(10, 1, 3): 3712 case IP_VERSION(10, 1, 4): 3713 soc15_program_register_sequence(adev, 3714 golden_settings_gc_10_0_cyan_skillfish, 3715 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3716 break; 3717 case IP_VERSION(10, 3, 6): 3718 soc15_program_register_sequence(adev, 3719 golden_settings_gc_10_3_6, 3720 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3721 break; 3722 case IP_VERSION(10, 3, 7): 3723 soc15_program_register_sequence(adev, 3724 golden_settings_gc_10_3_7, 3725 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3726 break; 3727 default: 3728 break; 3729 } 3730 gfx_v10_0_init_spm_golden_registers(adev); 3731 } 3732 3733 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3734 bool wc, uint32_t reg, uint32_t val) 3735 { 3736 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3737 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3738 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3739 amdgpu_ring_write(ring, reg); 3740 amdgpu_ring_write(ring, 0); 3741 amdgpu_ring_write(ring, val); 3742 } 3743 3744 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3745 int mem_space, int opt, uint32_t addr0, 3746 uint32_t addr1, uint32_t ref, uint32_t mask, 3747 uint32_t inv) 3748 { 3749 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3750 amdgpu_ring_write(ring, 3751 /* memory (1) or register (0) */ 3752 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3753 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3754 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3755 WAIT_REG_MEM_ENGINE(eng_sel))); 3756 3757 if (mem_space) 3758 BUG_ON(addr0 & 0x3); /* Dword align */ 3759 amdgpu_ring_write(ring, addr0); 3760 amdgpu_ring_write(ring, addr1); 3761 amdgpu_ring_write(ring, ref); 3762 amdgpu_ring_write(ring, mask); 3763 amdgpu_ring_write(ring, inv); /* poll interval */ 3764 } 3765 3766 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3767 { 3768 struct amdgpu_device *adev = ring->adev; 3769 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3770 uint32_t tmp = 0; 3771 unsigned int i; 3772 int r; 3773 3774 WREG32(scratch, 0xCAFEDEAD); 3775 r = amdgpu_ring_alloc(ring, 3); 3776 if (r) { 3777 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3778 ring->idx, r); 3779 return r; 3780 } 3781 3782 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3783 amdgpu_ring_write(ring, scratch - 3784 PACKET3_SET_UCONFIG_REG_START); 3785 amdgpu_ring_write(ring, 0xDEADBEEF); 3786 amdgpu_ring_commit(ring); 3787 3788 for (i = 0; i < adev->usec_timeout; i++) { 3789 tmp = RREG32(scratch); 3790 if (tmp == 0xDEADBEEF) 3791 break; 3792 if (amdgpu_emu_mode == 1) 3793 msleep(1); 3794 else 3795 udelay(1); 3796 } 3797 3798 if (i >= adev->usec_timeout) 3799 r = -ETIMEDOUT; 3800 3801 return r; 3802 } 3803 3804 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3805 { 3806 struct amdgpu_device *adev = ring->adev; 3807 struct amdgpu_ib ib; 3808 struct dma_fence *f = NULL; 3809 unsigned int index; 3810 uint64_t gpu_addr; 3811 volatile uint32_t *cpu_ptr; 3812 long r; 3813 3814 memset(&ib, 0, sizeof(ib)); 3815 3816 if (ring->is_mes_queue) { 3817 uint32_t padding, offset; 3818 3819 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 3820 padding = amdgpu_mes_ctx_get_offs(ring, 3821 AMDGPU_MES_CTX_PADDING_OFFS); 3822 3823 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 3824 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 3825 3826 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 3827 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 3828 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 3829 } else { 3830 r = amdgpu_device_wb_get(adev, &index); 3831 if (r) 3832 return r; 3833 3834 gpu_addr = adev->wb.gpu_addr + (index * 4); 3835 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3836 cpu_ptr = &adev->wb.wb[index]; 3837 3838 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 3839 if (r) { 3840 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 3841 goto err1; 3842 } 3843 } 3844 3845 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3846 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3847 ib.ptr[2] = lower_32_bits(gpu_addr); 3848 ib.ptr[3] = upper_32_bits(gpu_addr); 3849 ib.ptr[4] = 0xDEADBEEF; 3850 ib.length_dw = 5; 3851 3852 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3853 if (r) 3854 goto err2; 3855 3856 r = dma_fence_wait_timeout(f, false, timeout); 3857 if (r == 0) { 3858 r = -ETIMEDOUT; 3859 goto err2; 3860 } else if (r < 0) { 3861 goto err2; 3862 } 3863 3864 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 3865 r = 0; 3866 else 3867 r = -EINVAL; 3868 err2: 3869 if (!ring->is_mes_queue) 3870 amdgpu_ib_free(adev, &ib, NULL); 3871 dma_fence_put(f); 3872 err1: 3873 if (!ring->is_mes_queue) 3874 amdgpu_device_wb_free(adev, index); 3875 return r; 3876 } 3877 3878 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3879 { 3880 amdgpu_ucode_release(&adev->gfx.pfp_fw); 3881 amdgpu_ucode_release(&adev->gfx.me_fw); 3882 amdgpu_ucode_release(&adev->gfx.ce_fw); 3883 amdgpu_ucode_release(&adev->gfx.rlc_fw); 3884 amdgpu_ucode_release(&adev->gfx.mec_fw); 3885 amdgpu_ucode_release(&adev->gfx.mec2_fw); 3886 3887 kfree(adev->gfx.rlc.register_list_format); 3888 } 3889 3890 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3891 { 3892 adev->gfx.cp_fw_write_wait = false; 3893 3894 switch (adev->ip_versions[GC_HWIP][0]) { 3895 case IP_VERSION(10, 1, 10): 3896 case IP_VERSION(10, 1, 2): 3897 case IP_VERSION(10, 1, 1): 3898 case IP_VERSION(10, 1, 3): 3899 case IP_VERSION(10, 1, 4): 3900 if ((adev->gfx.me_fw_version >= 0x00000046) && 3901 (adev->gfx.me_feature_version >= 27) && 3902 (adev->gfx.pfp_fw_version >= 0x00000068) && 3903 (adev->gfx.pfp_feature_version >= 27) && 3904 (adev->gfx.mec_fw_version >= 0x0000005b) && 3905 (adev->gfx.mec_feature_version >= 27)) 3906 adev->gfx.cp_fw_write_wait = true; 3907 break; 3908 case IP_VERSION(10, 3, 0): 3909 case IP_VERSION(10, 3, 2): 3910 case IP_VERSION(10, 3, 1): 3911 case IP_VERSION(10, 3, 4): 3912 case IP_VERSION(10, 3, 5): 3913 case IP_VERSION(10, 3, 6): 3914 case IP_VERSION(10, 3, 3): 3915 case IP_VERSION(10, 3, 7): 3916 adev->gfx.cp_fw_write_wait = true; 3917 break; 3918 default: 3919 break; 3920 } 3921 3922 if (!adev->gfx.cp_fw_write_wait) 3923 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3924 } 3925 3926 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3927 { 3928 bool ret = false; 3929 3930 switch (adev->pdev->revision) { 3931 case 0xc2: 3932 case 0xc3: 3933 ret = true; 3934 break; 3935 default: 3936 ret = false; 3937 break; 3938 } 3939 3940 return ret; 3941 } 3942 3943 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3944 { 3945 switch (adev->ip_versions[GC_HWIP][0]) { 3946 case IP_VERSION(10, 1, 10): 3947 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3948 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3949 break; 3950 default: 3951 break; 3952 } 3953 } 3954 3955 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3956 { 3957 char fw_name[40]; 3958 char ucode_prefix[30]; 3959 const char *wks = ""; 3960 int err; 3961 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3962 uint16_t version_major; 3963 uint16_t version_minor; 3964 3965 DRM_DEBUG("\n"); 3966 3967 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) && 3968 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 3969 wks = "_wks"; 3970 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 3971 3972 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 3973 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 3974 if (err) 3975 goto out; 3976 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 3977 3978 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks); 3979 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 3980 if (err) 3981 goto out; 3982 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 3983 3984 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 3985 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 3986 if (err) 3987 goto out; 3988 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 3989 3990 if (!amdgpu_sriov_vf(adev)) { 3991 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 3992 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 3993 if (err) 3994 goto out; 3995 3996 /* don't validate this firmware. There are apparently firmwares 3997 * in the wild with incorrect size in the header 3998 */ 3999 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4000 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4001 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4002 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4003 if (err) 4004 goto out; 4005 } 4006 4007 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4008 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 4009 if (err) 4010 goto out; 4011 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4012 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4013 4014 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4015 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 4016 if (!err) { 4017 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4018 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4019 } else { 4020 err = 0; 4021 adev->gfx.mec2_fw = NULL; 4022 } 4023 4024 gfx_v10_0_check_fw_write_wait(adev); 4025 out: 4026 if (err) { 4027 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4028 amdgpu_ucode_release(&adev->gfx.me_fw); 4029 amdgpu_ucode_release(&adev->gfx.ce_fw); 4030 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4031 amdgpu_ucode_release(&adev->gfx.mec_fw); 4032 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4033 } 4034 4035 gfx_v10_0_check_gfxoff_flag(adev); 4036 4037 return err; 4038 } 4039 4040 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4041 { 4042 u32 count = 0; 4043 const struct cs_section_def *sect = NULL; 4044 const struct cs_extent_def *ext = NULL; 4045 4046 /* begin clear state */ 4047 count += 2; 4048 /* context control state */ 4049 count += 3; 4050 4051 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4052 for (ext = sect->section; ext->extent != NULL; ++ext) { 4053 if (sect->id == SECT_CONTEXT) 4054 count += 2 + ext->reg_count; 4055 else 4056 return 0; 4057 } 4058 } 4059 4060 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4061 count += 3; 4062 /* end clear state */ 4063 count += 2; 4064 /* clear state */ 4065 count += 2; 4066 4067 return count; 4068 } 4069 4070 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4071 volatile u32 *buffer) 4072 { 4073 u32 count = 0, i; 4074 const struct cs_section_def *sect = NULL; 4075 const struct cs_extent_def *ext = NULL; 4076 int ctx_reg_offset; 4077 4078 if (adev->gfx.rlc.cs_data == NULL) 4079 return; 4080 if (buffer == NULL) 4081 return; 4082 4083 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4084 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4085 4086 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4087 buffer[count++] = cpu_to_le32(0x80000000); 4088 buffer[count++] = cpu_to_le32(0x80000000); 4089 4090 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4091 for (ext = sect->section; ext->extent != NULL; ++ext) { 4092 if (sect->id == SECT_CONTEXT) { 4093 buffer[count++] = 4094 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4095 buffer[count++] = cpu_to_le32(ext->reg_index - 4096 PACKET3_SET_CONTEXT_REG_START); 4097 for (i = 0; i < ext->reg_count; i++) 4098 buffer[count++] = cpu_to_le32(ext->extent[i]); 4099 } else { 4100 return; 4101 } 4102 } 4103 } 4104 4105 ctx_reg_offset = 4106 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4107 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4108 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4109 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4110 4111 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4112 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4113 4114 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4115 buffer[count++] = cpu_to_le32(0); 4116 } 4117 4118 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4119 { 4120 /* clear state block */ 4121 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4122 &adev->gfx.rlc.clear_state_gpu_addr, 4123 (void **)&adev->gfx.rlc.cs_ptr); 4124 4125 /* jump table block */ 4126 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4127 &adev->gfx.rlc.cp_table_gpu_addr, 4128 (void **)&adev->gfx.rlc.cp_table_ptr); 4129 } 4130 4131 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4132 { 4133 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4134 4135 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4136 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4137 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4138 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4139 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4140 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4141 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4142 switch (adev->ip_versions[GC_HWIP][0]) { 4143 case IP_VERSION(10, 3, 0): 4144 reg_access_ctrl->spare_int = 4145 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4146 break; 4147 default: 4148 reg_access_ctrl->spare_int = 4149 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4150 break; 4151 } 4152 adev->gfx.rlc.rlcg_reg_access_supported = true; 4153 } 4154 4155 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4156 { 4157 const struct cs_section_def *cs_data; 4158 int r; 4159 4160 adev->gfx.rlc.cs_data = gfx10_cs_data; 4161 4162 cs_data = adev->gfx.rlc.cs_data; 4163 4164 if (cs_data) { 4165 /* init clear state block */ 4166 r = amdgpu_gfx_rlc_init_csb(adev); 4167 if (r) 4168 return r; 4169 } 4170 4171 return 0; 4172 } 4173 4174 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4175 { 4176 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4177 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4178 } 4179 4180 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4181 { 4182 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4183 4184 amdgpu_gfx_graphics_queue_acquire(adev); 4185 } 4186 4187 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4188 { 4189 int r; 4190 u32 *hpd; 4191 const __le32 *fw_data = NULL; 4192 unsigned int fw_size; 4193 u32 *fw = NULL; 4194 size_t mec_hpd_size; 4195 4196 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4197 4198 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4199 4200 /* take ownership of the relevant compute queues */ 4201 amdgpu_gfx_compute_queue_acquire(adev); 4202 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4203 4204 if (mec_hpd_size) { 4205 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4206 AMDGPU_GEM_DOMAIN_GTT, 4207 &adev->gfx.mec.hpd_eop_obj, 4208 &adev->gfx.mec.hpd_eop_gpu_addr, 4209 (void **)&hpd); 4210 if (r) { 4211 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4212 gfx_v10_0_mec_fini(adev); 4213 return r; 4214 } 4215 4216 memset(hpd, 0, mec_hpd_size); 4217 4218 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4219 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4220 } 4221 4222 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4223 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4224 4225 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4226 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4227 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4228 4229 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4230 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4231 &adev->gfx.mec.mec_fw_obj, 4232 &adev->gfx.mec.mec_fw_gpu_addr, 4233 (void **)&fw); 4234 if (r) { 4235 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4236 gfx_v10_0_mec_fini(adev); 4237 return r; 4238 } 4239 4240 memcpy(fw, fw_data, fw_size); 4241 4242 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4243 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4244 } 4245 4246 return 0; 4247 } 4248 4249 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4250 { 4251 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4252 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4253 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4254 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4255 } 4256 4257 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4258 uint32_t thread, uint32_t regno, 4259 uint32_t num, uint32_t *out) 4260 { 4261 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4262 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4263 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4264 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4265 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4266 while (num--) 4267 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4268 } 4269 4270 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4271 { 4272 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4273 * field when performing a select_se_sh so it should be 4274 * zero here 4275 */ 4276 WARN_ON(simd != 0); 4277 4278 /* type 2 wave data */ 4279 dst[(*no_fields)++] = 2; 4280 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4281 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4282 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4283 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4284 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4285 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4286 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4287 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4288 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4289 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4290 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4291 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4292 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4293 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4294 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4295 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4296 } 4297 4298 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4299 uint32_t wave, uint32_t start, 4300 uint32_t size, uint32_t *dst) 4301 { 4302 WARN_ON(simd != 0); 4303 4304 wave_read_regs( 4305 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4306 dst); 4307 } 4308 4309 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4310 uint32_t wave, uint32_t thread, 4311 uint32_t start, uint32_t size, 4312 uint32_t *dst) 4313 { 4314 wave_read_regs( 4315 adev, wave, thread, 4316 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4317 } 4318 4319 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4320 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4321 { 4322 nv_grbm_select(adev, me, pipe, q, vm); 4323 } 4324 4325 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4326 bool enable) 4327 { 4328 uint32_t data, def; 4329 4330 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4331 4332 if (enable) 4333 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4334 else 4335 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4336 4337 if (data != def) 4338 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4339 } 4340 4341 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4342 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4343 .select_se_sh = &gfx_v10_0_select_se_sh, 4344 .read_wave_data = &gfx_v10_0_read_wave_data, 4345 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4346 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4347 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4348 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4349 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4350 }; 4351 4352 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4353 { 4354 u32 gb_addr_config; 4355 4356 switch (adev->ip_versions[GC_HWIP][0]) { 4357 case IP_VERSION(10, 1, 10): 4358 case IP_VERSION(10, 1, 1): 4359 case IP_VERSION(10, 1, 2): 4360 adev->gfx.config.max_hw_contexts = 8; 4361 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4362 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4363 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4364 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4365 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4366 break; 4367 case IP_VERSION(10, 3, 0): 4368 case IP_VERSION(10, 3, 2): 4369 case IP_VERSION(10, 3, 1): 4370 case IP_VERSION(10, 3, 4): 4371 case IP_VERSION(10, 3, 5): 4372 case IP_VERSION(10, 3, 6): 4373 case IP_VERSION(10, 3, 3): 4374 case IP_VERSION(10, 3, 7): 4375 adev->gfx.config.max_hw_contexts = 8; 4376 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4377 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4378 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4379 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4380 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4381 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4382 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4383 break; 4384 case IP_VERSION(10, 1, 3): 4385 case IP_VERSION(10, 1, 4): 4386 adev->gfx.config.max_hw_contexts = 8; 4387 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4388 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4389 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4390 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4391 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4392 break; 4393 default: 4394 BUG(); 4395 break; 4396 } 4397 4398 adev->gfx.config.gb_addr_config = gb_addr_config; 4399 4400 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4401 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4402 GB_ADDR_CONFIG, NUM_PIPES); 4403 4404 adev->gfx.config.max_tile_pipes = 4405 adev->gfx.config.gb_addr_config_fields.num_pipes; 4406 4407 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4408 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4409 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4410 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4411 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4412 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4413 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4414 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4415 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4416 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4417 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4418 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4419 } 4420 4421 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4422 int me, int pipe, int queue) 4423 { 4424 struct amdgpu_ring *ring; 4425 unsigned int irq_type; 4426 unsigned int hw_prio; 4427 4428 ring = &adev->gfx.gfx_ring[ring_id]; 4429 4430 ring->me = me; 4431 ring->pipe = pipe; 4432 ring->queue = queue; 4433 4434 ring->ring_obj = NULL; 4435 ring->use_doorbell = true; 4436 4437 if (!ring_id) 4438 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4439 else 4440 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4441 ring->vm_hub = AMDGPU_GFXHUB(0); 4442 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4443 4444 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4445 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4446 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4447 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4448 hw_prio, NULL); 4449 } 4450 4451 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4452 int mec, int pipe, int queue) 4453 { 4454 unsigned int irq_type; 4455 struct amdgpu_ring *ring; 4456 unsigned int hw_prio; 4457 4458 ring = &adev->gfx.compute_ring[ring_id]; 4459 4460 /* mec0 is me1 */ 4461 ring->me = mec + 1; 4462 ring->pipe = pipe; 4463 ring->queue = queue; 4464 4465 ring->ring_obj = NULL; 4466 ring->use_doorbell = true; 4467 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4468 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4469 + (ring_id * GFX10_MEC_HPD_SIZE); 4470 ring->vm_hub = AMDGPU_GFXHUB(0); 4471 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4472 4473 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4474 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4475 + ring->pipe; 4476 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4477 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4478 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4479 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4480 hw_prio, NULL); 4481 } 4482 4483 static int gfx_v10_0_sw_init(void *handle) 4484 { 4485 int i, j, k, r, ring_id = 0; 4486 struct amdgpu_kiq *kiq; 4487 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4488 4489 switch (adev->ip_versions[GC_HWIP][0]) { 4490 case IP_VERSION(10, 1, 10): 4491 case IP_VERSION(10, 1, 1): 4492 case IP_VERSION(10, 1, 2): 4493 case IP_VERSION(10, 1, 3): 4494 case IP_VERSION(10, 1, 4): 4495 adev->gfx.me.num_me = 1; 4496 adev->gfx.me.num_pipe_per_me = 1; 4497 adev->gfx.me.num_queue_per_pipe = 1; 4498 adev->gfx.mec.num_mec = 2; 4499 adev->gfx.mec.num_pipe_per_mec = 4; 4500 adev->gfx.mec.num_queue_per_pipe = 8; 4501 break; 4502 case IP_VERSION(10, 3, 0): 4503 case IP_VERSION(10, 3, 2): 4504 case IP_VERSION(10, 3, 1): 4505 case IP_VERSION(10, 3, 4): 4506 case IP_VERSION(10, 3, 5): 4507 case IP_VERSION(10, 3, 6): 4508 case IP_VERSION(10, 3, 3): 4509 case IP_VERSION(10, 3, 7): 4510 adev->gfx.me.num_me = 1; 4511 adev->gfx.me.num_pipe_per_me = 1; 4512 adev->gfx.me.num_queue_per_pipe = 1; 4513 adev->gfx.mec.num_mec = 2; 4514 adev->gfx.mec.num_pipe_per_mec = 4; 4515 adev->gfx.mec.num_queue_per_pipe = 4; 4516 break; 4517 default: 4518 adev->gfx.me.num_me = 1; 4519 adev->gfx.me.num_pipe_per_me = 1; 4520 adev->gfx.me.num_queue_per_pipe = 1; 4521 adev->gfx.mec.num_mec = 1; 4522 adev->gfx.mec.num_pipe_per_mec = 4; 4523 adev->gfx.mec.num_queue_per_pipe = 8; 4524 break; 4525 } 4526 4527 /* KIQ event */ 4528 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4529 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4530 &adev->gfx.kiq[0].irq); 4531 if (r) 4532 return r; 4533 4534 /* EOP Event */ 4535 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4536 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4537 &adev->gfx.eop_irq); 4538 if (r) 4539 return r; 4540 4541 /* Privileged reg */ 4542 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4543 &adev->gfx.priv_reg_irq); 4544 if (r) 4545 return r; 4546 4547 /* Privileged inst */ 4548 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4549 &adev->gfx.priv_inst_irq); 4550 if (r) 4551 return r; 4552 4553 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4554 4555 gfx_v10_0_me_init(adev); 4556 4557 if (adev->gfx.rlc.funcs) { 4558 if (adev->gfx.rlc.funcs->init) { 4559 r = adev->gfx.rlc.funcs->init(adev); 4560 if (r) { 4561 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4562 return r; 4563 } 4564 } 4565 } 4566 4567 r = gfx_v10_0_mec_init(adev); 4568 if (r) { 4569 DRM_ERROR("Failed to init MEC BOs!\n"); 4570 return r; 4571 } 4572 4573 /* set up the gfx ring */ 4574 for (i = 0; i < adev->gfx.me.num_me; i++) { 4575 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4576 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4577 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4578 continue; 4579 4580 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4581 i, k, j); 4582 if (r) 4583 return r; 4584 ring_id++; 4585 } 4586 } 4587 } 4588 4589 ring_id = 0; 4590 /* set up the compute queues - allocate horizontally across pipes */ 4591 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4592 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4593 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4594 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4595 k, j)) 4596 continue; 4597 4598 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4599 i, k, j); 4600 if (r) 4601 return r; 4602 4603 ring_id++; 4604 } 4605 } 4606 } 4607 4608 if (!adev->enable_mes_kiq) { 4609 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4610 if (r) { 4611 DRM_ERROR("Failed to init KIQ BOs!\n"); 4612 return r; 4613 } 4614 4615 kiq = &adev->gfx.kiq[0]; 4616 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 4617 if (r) 4618 return r; 4619 } 4620 4621 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4622 if (r) 4623 return r; 4624 4625 /* allocate visible FB for rlc auto-loading fw */ 4626 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4627 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4628 if (r) 4629 return r; 4630 } 4631 4632 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4633 4634 gfx_v10_0_gpu_early_init(adev); 4635 4636 return 0; 4637 } 4638 4639 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4640 { 4641 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4642 &adev->gfx.pfp.pfp_fw_gpu_addr, 4643 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4644 } 4645 4646 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4647 { 4648 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4649 &adev->gfx.ce.ce_fw_gpu_addr, 4650 (void **)&adev->gfx.ce.ce_fw_ptr); 4651 } 4652 4653 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4654 { 4655 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4656 &adev->gfx.me.me_fw_gpu_addr, 4657 (void **)&adev->gfx.me.me_fw_ptr); 4658 } 4659 4660 static int gfx_v10_0_sw_fini(void *handle) 4661 { 4662 int i; 4663 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4664 4665 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4666 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4667 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4668 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4669 4670 amdgpu_gfx_mqd_sw_fini(adev, 0); 4671 4672 if (!adev->enable_mes_kiq) { 4673 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4674 amdgpu_gfx_kiq_fini(adev, 0); 4675 } 4676 4677 gfx_v10_0_pfp_fini(adev); 4678 gfx_v10_0_ce_fini(adev); 4679 gfx_v10_0_me_fini(adev); 4680 gfx_v10_0_rlc_fini(adev); 4681 gfx_v10_0_mec_fini(adev); 4682 4683 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4684 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4685 4686 gfx_v10_0_free_microcode(adev); 4687 4688 return 0; 4689 } 4690 4691 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4692 u32 sh_num, u32 instance, int xcc_id) 4693 { 4694 u32 data; 4695 4696 if (instance == 0xffffffff) 4697 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4698 INSTANCE_BROADCAST_WRITES, 1); 4699 else 4700 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4701 instance); 4702 4703 if (se_num == 0xffffffff) 4704 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4705 1); 4706 else 4707 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4708 4709 if (sh_num == 0xffffffff) 4710 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4711 1); 4712 else 4713 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4714 4715 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4716 } 4717 4718 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4719 { 4720 u32 data, mask; 4721 4722 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4723 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4724 4725 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4726 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4727 4728 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4729 adev->gfx.config.max_sh_per_se); 4730 4731 return (~data) & mask; 4732 } 4733 4734 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4735 { 4736 int i, j; 4737 u32 data; 4738 u32 active_rbs = 0; 4739 u32 bitmap; 4740 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4741 adev->gfx.config.max_sh_per_se; 4742 4743 mutex_lock(&adev->grbm_idx_mutex); 4744 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4745 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4746 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4747 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 4748 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 4749 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) && 4750 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4751 continue; 4752 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4753 data = gfx_v10_0_get_rb_active_bitmap(adev); 4754 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4755 rb_bitmap_width_per_sh); 4756 } 4757 } 4758 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4759 mutex_unlock(&adev->grbm_idx_mutex); 4760 4761 adev->gfx.config.backend_enable_mask = active_rbs; 4762 adev->gfx.config.num_rbs = hweight32(active_rbs); 4763 } 4764 4765 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4766 { 4767 uint32_t num_sc; 4768 uint32_t enabled_rb_per_sh; 4769 uint32_t active_rb_bitmap; 4770 uint32_t num_rb_per_sc; 4771 uint32_t num_packer_per_sc; 4772 uint32_t pa_sc_tile_steering_override; 4773 4774 /* for ASICs that integrates GFX v10.3 4775 * pa_sc_tile_steering_override should be set to 0 4776 */ 4777 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 4778 return 0; 4779 4780 /* init num_sc */ 4781 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4782 adev->gfx.config.num_sc_per_sh; 4783 /* init num_rb_per_sc */ 4784 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4785 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4786 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4787 /* init num_packer_per_sc */ 4788 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4789 4790 pa_sc_tile_steering_override = 0; 4791 pa_sc_tile_steering_override |= 4792 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4793 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4794 pa_sc_tile_steering_override |= 4795 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4796 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4797 pa_sc_tile_steering_override |= 4798 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4799 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4800 4801 return pa_sc_tile_steering_override; 4802 } 4803 4804 #define DEFAULT_SH_MEM_BASES (0x6000) 4805 4806 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 4807 uint32_t first_vmid, 4808 uint32_t last_vmid) 4809 { 4810 uint32_t data; 4811 uint32_t trap_config_vmid_mask = 0; 4812 int i; 4813 4814 /* Calculate trap config vmid mask */ 4815 for (i = first_vmid; i < last_vmid; i++) 4816 trap_config_vmid_mask |= (1 << i); 4817 4818 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 4819 VMID_SEL, trap_config_vmid_mask); 4820 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 4821 TRAP_EN, 1); 4822 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 4823 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 4824 4825 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 4826 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 4827 } 4828 4829 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4830 { 4831 int i; 4832 uint32_t sh_mem_bases; 4833 4834 /* 4835 * Configure apertures: 4836 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4837 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4838 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4839 */ 4840 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4841 4842 mutex_lock(&adev->srbm_mutex); 4843 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4844 nv_grbm_select(adev, 0, 0, 0, i); 4845 /* CP and shaders */ 4846 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4847 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4848 } 4849 nv_grbm_select(adev, 0, 0, 0, 0); 4850 mutex_unlock(&adev->srbm_mutex); 4851 4852 /* 4853 * Initialize all compute VMIDs to have no GDS, GWS, or OA 4854 * access. These should be enabled by FW for target VMIDs. 4855 */ 4856 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4857 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4858 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4859 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4860 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4861 } 4862 4863 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 4864 AMDGPU_NUM_VMID); 4865 } 4866 4867 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4868 { 4869 int vmid; 4870 4871 /* 4872 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4873 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4874 * the driver can enable them for graphics. VMID0 should maintain 4875 * access so that HWS firmware can save/restore entries. 4876 */ 4877 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4878 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4879 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4880 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4881 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4882 } 4883 } 4884 4885 4886 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4887 { 4888 int i, j, k; 4889 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4890 u32 tmp, wgp_active_bitmap = 0; 4891 u32 gcrd_targets_disable_tcp = 0; 4892 u32 utcl_invreq_disable = 0; 4893 /* 4894 * GCRD_TARGETS_DISABLE field contains 4895 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4896 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4897 */ 4898 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4899 2 * max_wgp_per_sh + /* TCP */ 4900 max_wgp_per_sh + /* SQC */ 4901 4); /* GL1C */ 4902 /* 4903 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4904 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4905 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4906 */ 4907 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4908 2 * max_wgp_per_sh + /* TCP */ 4909 2 * max_wgp_per_sh + /* SQC */ 4910 4 + /* RMI */ 4911 1); /* SQG */ 4912 4913 mutex_lock(&adev->grbm_idx_mutex); 4914 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4915 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4916 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4917 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4918 /* 4919 * Set corresponding TCP bits for the inactive WGPs in 4920 * GCRD_SA_TARGETS_DISABLE 4921 */ 4922 gcrd_targets_disable_tcp = 0; 4923 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4924 utcl_invreq_disable = 0; 4925 4926 for (k = 0; k < max_wgp_per_sh; k++) { 4927 if (!(wgp_active_bitmap & (1 << k))) { 4928 gcrd_targets_disable_tcp |= 3 << (2 * k); 4929 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 4930 utcl_invreq_disable |= (3 << (2 * k)) | 4931 (3 << (2 * (max_wgp_per_sh + k))); 4932 } 4933 } 4934 4935 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4936 /* only override TCP & SQC bits */ 4937 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 4938 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4939 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4940 4941 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4942 /* only override TCP & SQC bits */ 4943 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 4944 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4945 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4946 } 4947 } 4948 4949 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4950 mutex_unlock(&adev->grbm_idx_mutex); 4951 } 4952 4953 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4954 { 4955 /* TCCs are global (not instanced). */ 4956 uint32_t tcc_disable; 4957 4958 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 4959 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 4960 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 4961 } else { 4962 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4963 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4964 } 4965 4966 adev->gfx.config.tcc_disabled_mask = 4967 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4968 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4969 } 4970 4971 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4972 { 4973 u32 tmp; 4974 int i; 4975 4976 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4977 4978 gfx_v10_0_setup_rb(adev); 4979 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4980 gfx_v10_0_get_tcc_info(adev); 4981 adev->gfx.config.pa_sc_tile_steering_override = 4982 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4983 4984 /* XXX SH_MEM regs */ 4985 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4986 mutex_lock(&adev->srbm_mutex); 4987 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 4988 nv_grbm_select(adev, 0, 0, 0, i); 4989 /* CP and shaders */ 4990 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4991 if (i != 0) { 4992 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4993 (adev->gmc.private_aperture_start >> 48)); 4994 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4995 (adev->gmc.shared_aperture_start >> 48)); 4996 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4997 } 4998 } 4999 nv_grbm_select(adev, 0, 0, 0, 0); 5000 5001 mutex_unlock(&adev->srbm_mutex); 5002 5003 gfx_v10_0_init_compute_vmid(adev); 5004 gfx_v10_0_init_gds_vmid(adev); 5005 5006 } 5007 5008 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5009 bool enable) 5010 { 5011 u32 tmp; 5012 5013 if (amdgpu_sriov_vf(adev)) 5014 return; 5015 5016 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5017 5018 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5019 enable ? 1 : 0); 5020 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5021 enable ? 1 : 0); 5022 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5023 enable ? 1 : 0); 5024 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5025 enable ? 1 : 0); 5026 5027 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5028 } 5029 5030 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5031 { 5032 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5033 5034 /* csib */ 5035 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5036 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5037 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5038 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5039 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5040 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5041 } else { 5042 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5043 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5044 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5045 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5046 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5047 } 5048 return 0; 5049 } 5050 5051 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5052 { 5053 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5054 5055 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5056 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5057 } 5058 5059 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5060 { 5061 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5062 udelay(50); 5063 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5064 udelay(50); 5065 } 5066 5067 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5068 bool enable) 5069 { 5070 uint32_t rlc_pg_cntl; 5071 5072 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5073 5074 if (!enable) { 5075 /* RLC_PG_CNTL[23] = 0 (default) 5076 * RLC will wait for handshake acks with SMU 5077 * GFXOFF will be enabled 5078 * RLC_PG_CNTL[23] = 1 5079 * RLC will not issue any message to SMU 5080 * hence no handshake between SMU & RLC 5081 * GFXOFF will be disabled 5082 */ 5083 rlc_pg_cntl |= 0x800000; 5084 } else 5085 rlc_pg_cntl &= ~0x800000; 5086 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5087 } 5088 5089 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5090 { 5091 /* 5092 * TODO: enable rlc & smu handshake until smu 5093 * and gfxoff feature works as expected 5094 */ 5095 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5096 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5097 5098 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5099 udelay(50); 5100 } 5101 5102 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5103 { 5104 uint32_t tmp; 5105 5106 /* enable Save Restore Machine */ 5107 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5108 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5109 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5110 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5111 } 5112 5113 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5114 { 5115 const struct rlc_firmware_header_v2_0 *hdr; 5116 const __le32 *fw_data; 5117 unsigned int i, fw_size; 5118 5119 if (!adev->gfx.rlc_fw) 5120 return -EINVAL; 5121 5122 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5123 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5124 5125 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5126 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5127 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5128 5129 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5130 RLCG_UCODE_LOADING_START_ADDRESS); 5131 5132 for (i = 0; i < fw_size; i++) 5133 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5134 le32_to_cpup(fw_data++)); 5135 5136 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5137 5138 return 0; 5139 } 5140 5141 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5142 { 5143 int r; 5144 5145 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5146 adev->psp.autoload_supported) { 5147 5148 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5149 if (r) 5150 return r; 5151 5152 gfx_v10_0_init_csb(adev); 5153 5154 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5155 5156 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5157 gfx_v10_0_rlc_enable_srm(adev); 5158 } else { 5159 if (amdgpu_sriov_vf(adev)) { 5160 gfx_v10_0_init_csb(adev); 5161 return 0; 5162 } 5163 5164 adev->gfx.rlc.funcs->stop(adev); 5165 5166 /* disable CG */ 5167 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5168 5169 /* disable PG */ 5170 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5171 5172 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5173 /* legacy rlc firmware loading */ 5174 r = gfx_v10_0_rlc_load_microcode(adev); 5175 if (r) 5176 return r; 5177 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5178 /* rlc backdoor autoload firmware */ 5179 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5180 if (r) 5181 return r; 5182 } 5183 5184 gfx_v10_0_init_csb(adev); 5185 5186 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5187 5188 adev->gfx.rlc.funcs->start(adev); 5189 5190 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5191 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5192 if (r) 5193 return r; 5194 } 5195 } 5196 5197 return 0; 5198 } 5199 5200 static struct { 5201 FIRMWARE_ID id; 5202 unsigned int offset; 5203 unsigned int size; 5204 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5205 5206 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5207 { 5208 int ret; 5209 RLC_TABLE_OF_CONTENT *rlc_toc; 5210 5211 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5212 AMDGPU_GEM_DOMAIN_GTT, 5213 &adev->gfx.rlc.rlc_toc_bo, 5214 &adev->gfx.rlc.rlc_toc_gpu_addr, 5215 (void **)&adev->gfx.rlc.rlc_toc_buf); 5216 if (ret) { 5217 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5218 return ret; 5219 } 5220 5221 /* Copy toc from psp sos fw to rlc toc buffer */ 5222 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5223 5224 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5225 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5226 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5227 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5228 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5229 /* Offset needs 4KB alignment */ 5230 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5231 } 5232 5233 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5234 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5235 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5236 5237 rlc_toc++; 5238 } 5239 5240 return 0; 5241 } 5242 5243 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5244 { 5245 uint32_t total_size = 0; 5246 FIRMWARE_ID id; 5247 int ret; 5248 5249 ret = gfx_v10_0_parse_rlc_toc(adev); 5250 if (ret) { 5251 dev_err(adev->dev, "failed to parse rlc toc\n"); 5252 return 0; 5253 } 5254 5255 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5256 total_size += rlc_autoload_info[id].size; 5257 5258 /* In case the offset in rlc toc ucode is aligned */ 5259 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5260 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5261 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5262 5263 return total_size; 5264 } 5265 5266 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5267 { 5268 int r; 5269 uint32_t total_size; 5270 5271 total_size = gfx_v10_0_calc_toc_total_size(adev); 5272 5273 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5274 AMDGPU_GEM_DOMAIN_GTT, 5275 &adev->gfx.rlc.rlc_autoload_bo, 5276 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5277 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5278 if (r) { 5279 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5280 return r; 5281 } 5282 5283 return 0; 5284 } 5285 5286 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5287 { 5288 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5289 &adev->gfx.rlc.rlc_toc_gpu_addr, 5290 (void **)&adev->gfx.rlc.rlc_toc_buf); 5291 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5292 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5293 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5294 } 5295 5296 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5297 FIRMWARE_ID id, 5298 const void *fw_data, 5299 uint32_t fw_size) 5300 { 5301 uint32_t toc_offset; 5302 uint32_t toc_fw_size; 5303 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5304 5305 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5306 return; 5307 5308 toc_offset = rlc_autoload_info[id].offset; 5309 toc_fw_size = rlc_autoload_info[id].size; 5310 5311 if (fw_size == 0) 5312 fw_size = toc_fw_size; 5313 5314 if (fw_size > toc_fw_size) 5315 fw_size = toc_fw_size; 5316 5317 memcpy(ptr + toc_offset, fw_data, fw_size); 5318 5319 if (fw_size < toc_fw_size) 5320 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5321 } 5322 5323 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5324 { 5325 void *data; 5326 uint32_t size; 5327 5328 data = adev->gfx.rlc.rlc_toc_buf; 5329 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5330 5331 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5332 FIRMWARE_ID_RLC_TOC, 5333 data, size); 5334 } 5335 5336 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5337 { 5338 const __le32 *fw_data; 5339 uint32_t fw_size; 5340 const struct gfx_firmware_header_v1_0 *cp_hdr; 5341 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5342 5343 /* pfp ucode */ 5344 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5345 adev->gfx.pfp_fw->data; 5346 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5347 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5348 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5349 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5350 FIRMWARE_ID_CP_PFP, 5351 fw_data, fw_size); 5352 5353 /* ce ucode */ 5354 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5355 adev->gfx.ce_fw->data; 5356 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5357 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5358 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5359 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5360 FIRMWARE_ID_CP_CE, 5361 fw_data, fw_size); 5362 5363 /* me ucode */ 5364 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5365 adev->gfx.me_fw->data; 5366 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5367 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5368 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5369 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5370 FIRMWARE_ID_CP_ME, 5371 fw_data, fw_size); 5372 5373 /* rlc ucode */ 5374 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5375 adev->gfx.rlc_fw->data; 5376 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5377 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5378 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5379 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5380 FIRMWARE_ID_RLC_G_UCODE, 5381 fw_data, fw_size); 5382 5383 /* mec1 ucode */ 5384 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5385 adev->gfx.mec_fw->data; 5386 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5387 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5388 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5389 cp_hdr->jt_size * 4; 5390 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5391 FIRMWARE_ID_CP_MEC, 5392 fw_data, fw_size); 5393 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5394 } 5395 5396 /* Temporarily put sdma part here */ 5397 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5398 { 5399 const __le32 *fw_data; 5400 uint32_t fw_size; 5401 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5402 int i; 5403 5404 for (i = 0; i < adev->sdma.num_instances; i++) { 5405 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5406 adev->sdma.instance[i].fw->data; 5407 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5408 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5409 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5410 5411 if (i == 0) { 5412 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5413 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5414 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5415 FIRMWARE_ID_SDMA0_JT, 5416 (uint32_t *)fw_data + 5417 sdma_hdr->jt_offset, 5418 sdma_hdr->jt_size * 4); 5419 } else if (i == 1) { 5420 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5421 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5422 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5423 FIRMWARE_ID_SDMA1_JT, 5424 (uint32_t *)fw_data + 5425 sdma_hdr->jt_offset, 5426 sdma_hdr->jt_size * 4); 5427 } 5428 } 5429 } 5430 5431 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5432 { 5433 uint32_t rlc_g_offset, rlc_g_size, tmp; 5434 uint64_t gpu_addr; 5435 5436 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5437 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5438 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5439 5440 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5441 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5442 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5443 5444 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5445 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5446 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5447 5448 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5449 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5450 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5451 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5452 return -EINVAL; 5453 } 5454 5455 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5456 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5457 DRM_ERROR("RLC ROM should halt itself\n"); 5458 return -EINVAL; 5459 } 5460 5461 return 0; 5462 } 5463 5464 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5465 { 5466 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5467 uint32_t tmp; 5468 int i; 5469 uint64_t addr; 5470 5471 /* Trigger an invalidation of the L1 instruction caches */ 5472 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5473 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5474 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5475 5476 /* Wait for invalidation complete */ 5477 for (i = 0; i < usec_timeout; i++) { 5478 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5479 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5480 INVALIDATE_CACHE_COMPLETE)) 5481 break; 5482 udelay(1); 5483 } 5484 5485 if (i >= usec_timeout) { 5486 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5487 return -EINVAL; 5488 } 5489 5490 /* Program me ucode address into intruction cache address register */ 5491 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5492 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5493 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5494 lower_32_bits(addr) & 0xFFFFF000); 5495 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5496 upper_32_bits(addr)); 5497 5498 return 0; 5499 } 5500 5501 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5502 { 5503 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5504 uint32_t tmp; 5505 int i; 5506 uint64_t addr; 5507 5508 /* Trigger an invalidation of the L1 instruction caches */ 5509 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5510 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5511 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5512 5513 /* Wait for invalidation complete */ 5514 for (i = 0; i < usec_timeout; i++) { 5515 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5516 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5517 INVALIDATE_CACHE_COMPLETE)) 5518 break; 5519 udelay(1); 5520 } 5521 5522 if (i >= usec_timeout) { 5523 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5524 return -EINVAL; 5525 } 5526 5527 /* Program ce ucode address into intruction cache address register */ 5528 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5529 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5530 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5531 lower_32_bits(addr) & 0xFFFFF000); 5532 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5533 upper_32_bits(addr)); 5534 5535 return 0; 5536 } 5537 5538 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5539 { 5540 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5541 uint32_t tmp; 5542 int i; 5543 uint64_t addr; 5544 5545 /* Trigger an invalidation of the L1 instruction caches */ 5546 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5547 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5548 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5549 5550 /* Wait for invalidation complete */ 5551 for (i = 0; i < usec_timeout; i++) { 5552 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5553 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5554 INVALIDATE_CACHE_COMPLETE)) 5555 break; 5556 udelay(1); 5557 } 5558 5559 if (i >= usec_timeout) { 5560 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5561 return -EINVAL; 5562 } 5563 5564 /* Program pfp ucode address into intruction cache address register */ 5565 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5566 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5567 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5568 lower_32_bits(addr) & 0xFFFFF000); 5569 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5570 upper_32_bits(addr)); 5571 5572 return 0; 5573 } 5574 5575 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5576 { 5577 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5578 uint32_t tmp; 5579 int i; 5580 uint64_t addr; 5581 5582 /* Trigger an invalidation of the L1 instruction caches */ 5583 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5584 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5585 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5586 5587 /* Wait for invalidation complete */ 5588 for (i = 0; i < usec_timeout; i++) { 5589 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5590 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5591 INVALIDATE_CACHE_COMPLETE)) 5592 break; 5593 udelay(1); 5594 } 5595 5596 if (i >= usec_timeout) { 5597 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5598 return -EINVAL; 5599 } 5600 5601 /* Program mec1 ucode address into intruction cache address register */ 5602 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5603 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5604 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5605 lower_32_bits(addr) & 0xFFFFF000); 5606 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5607 upper_32_bits(addr)); 5608 5609 return 0; 5610 } 5611 5612 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5613 { 5614 uint32_t cp_status; 5615 uint32_t bootload_status; 5616 int i, r; 5617 5618 for (i = 0; i < adev->usec_timeout; i++) { 5619 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5620 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5621 if ((cp_status == 0) && 5622 (REG_GET_FIELD(bootload_status, 5623 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5624 break; 5625 } 5626 udelay(1); 5627 } 5628 5629 if (i >= adev->usec_timeout) { 5630 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5631 return -ETIMEDOUT; 5632 } 5633 5634 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5635 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5636 if (r) 5637 return r; 5638 5639 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5640 if (r) 5641 return r; 5642 5643 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5644 if (r) 5645 return r; 5646 5647 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5648 if (r) 5649 return r; 5650 } 5651 5652 return 0; 5653 } 5654 5655 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5656 { 5657 int i; 5658 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5659 5660 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5661 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5662 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5663 5664 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 5665 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5666 else 5667 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5668 5669 if (adev->job_hang && !enable) 5670 return 0; 5671 5672 for (i = 0; i < adev->usec_timeout; i++) { 5673 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5674 break; 5675 udelay(1); 5676 } 5677 5678 if (i >= adev->usec_timeout) 5679 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5680 5681 return 0; 5682 } 5683 5684 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5685 { 5686 int r; 5687 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5688 const __le32 *fw_data; 5689 unsigned int i, fw_size; 5690 uint32_t tmp; 5691 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5692 5693 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5694 adev->gfx.pfp_fw->data; 5695 5696 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5697 5698 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5699 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5700 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5701 5702 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5703 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5704 &adev->gfx.pfp.pfp_fw_obj, 5705 &adev->gfx.pfp.pfp_fw_gpu_addr, 5706 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5707 if (r) { 5708 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5709 gfx_v10_0_pfp_fini(adev); 5710 return r; 5711 } 5712 5713 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5714 5715 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5716 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5717 5718 /* Trigger an invalidation of the L1 instruction caches */ 5719 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5720 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5721 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5722 5723 /* Wait for invalidation complete */ 5724 for (i = 0; i < usec_timeout; i++) { 5725 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5726 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5727 INVALIDATE_CACHE_COMPLETE)) 5728 break; 5729 udelay(1); 5730 } 5731 5732 if (i >= usec_timeout) { 5733 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5734 return -EINVAL; 5735 } 5736 5737 if (amdgpu_emu_mode == 1) 5738 adev->hdp.funcs->flush_hdp(adev, NULL); 5739 5740 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5741 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5742 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5743 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5744 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5745 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5746 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5747 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5748 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5749 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5750 5751 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5752 5753 for (i = 0; i < pfp_hdr->jt_size; i++) 5754 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5755 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5756 5757 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5758 5759 return 0; 5760 } 5761 5762 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5763 { 5764 int r; 5765 const struct gfx_firmware_header_v1_0 *ce_hdr; 5766 const __le32 *fw_data; 5767 unsigned int i, fw_size; 5768 uint32_t tmp; 5769 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5770 5771 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5772 adev->gfx.ce_fw->data; 5773 5774 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5775 5776 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5777 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5778 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5779 5780 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5781 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5782 &adev->gfx.ce.ce_fw_obj, 5783 &adev->gfx.ce.ce_fw_gpu_addr, 5784 (void **)&adev->gfx.ce.ce_fw_ptr); 5785 if (r) { 5786 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5787 gfx_v10_0_ce_fini(adev); 5788 return r; 5789 } 5790 5791 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5792 5793 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5794 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5795 5796 /* Trigger an invalidation of the L1 instruction caches */ 5797 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5798 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5799 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5800 5801 /* Wait for invalidation complete */ 5802 for (i = 0; i < usec_timeout; i++) { 5803 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5804 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5805 INVALIDATE_CACHE_COMPLETE)) 5806 break; 5807 udelay(1); 5808 } 5809 5810 if (i >= usec_timeout) { 5811 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5812 return -EINVAL; 5813 } 5814 5815 if (amdgpu_emu_mode == 1) 5816 adev->hdp.funcs->flush_hdp(adev, NULL); 5817 5818 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5819 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5820 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5821 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5822 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5823 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5824 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5825 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5826 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5827 5828 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5829 5830 for (i = 0; i < ce_hdr->jt_size; i++) 5831 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5832 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5833 5834 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5835 5836 return 0; 5837 } 5838 5839 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5840 { 5841 int r; 5842 const struct gfx_firmware_header_v1_0 *me_hdr; 5843 const __le32 *fw_data; 5844 unsigned int i, fw_size; 5845 uint32_t tmp; 5846 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5847 5848 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5849 adev->gfx.me_fw->data; 5850 5851 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5852 5853 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5854 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5855 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5856 5857 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5858 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5859 &adev->gfx.me.me_fw_obj, 5860 &adev->gfx.me.me_fw_gpu_addr, 5861 (void **)&adev->gfx.me.me_fw_ptr); 5862 if (r) { 5863 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5864 gfx_v10_0_me_fini(adev); 5865 return r; 5866 } 5867 5868 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5869 5870 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5871 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5872 5873 /* Trigger an invalidation of the L1 instruction caches */ 5874 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5875 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5876 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5877 5878 /* Wait for invalidation complete */ 5879 for (i = 0; i < usec_timeout; i++) { 5880 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5881 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5882 INVALIDATE_CACHE_COMPLETE)) 5883 break; 5884 udelay(1); 5885 } 5886 5887 if (i >= usec_timeout) { 5888 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5889 return -EINVAL; 5890 } 5891 5892 if (amdgpu_emu_mode == 1) 5893 adev->hdp.funcs->flush_hdp(adev, NULL); 5894 5895 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5896 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5897 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5898 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5899 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5900 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5901 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5902 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5903 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5904 5905 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5906 5907 for (i = 0; i < me_hdr->jt_size; i++) 5908 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5909 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5910 5911 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5912 5913 return 0; 5914 } 5915 5916 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5917 { 5918 int r; 5919 5920 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5921 return -EINVAL; 5922 5923 gfx_v10_0_cp_gfx_enable(adev, false); 5924 5925 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5926 if (r) { 5927 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5928 return r; 5929 } 5930 5931 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5932 if (r) { 5933 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5934 return r; 5935 } 5936 5937 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5938 if (r) { 5939 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5940 return r; 5941 } 5942 5943 return 0; 5944 } 5945 5946 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5947 { 5948 struct amdgpu_ring *ring; 5949 const struct cs_section_def *sect = NULL; 5950 const struct cs_extent_def *ext = NULL; 5951 int r, i; 5952 int ctx_reg_offset; 5953 5954 /* init the CP */ 5955 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5956 adev->gfx.config.max_hw_contexts - 1); 5957 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5958 5959 gfx_v10_0_cp_gfx_enable(adev, true); 5960 5961 ring = &adev->gfx.gfx_ring[0]; 5962 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5963 if (r) { 5964 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5965 return r; 5966 } 5967 5968 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5969 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5970 5971 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5972 amdgpu_ring_write(ring, 0x80000000); 5973 amdgpu_ring_write(ring, 0x80000000); 5974 5975 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5976 for (ext = sect->section; ext->extent != NULL; ++ext) { 5977 if (sect->id == SECT_CONTEXT) { 5978 amdgpu_ring_write(ring, 5979 PACKET3(PACKET3_SET_CONTEXT_REG, 5980 ext->reg_count)); 5981 amdgpu_ring_write(ring, ext->reg_index - 5982 PACKET3_SET_CONTEXT_REG_START); 5983 for (i = 0; i < ext->reg_count; i++) 5984 amdgpu_ring_write(ring, ext->extent[i]); 5985 } 5986 } 5987 } 5988 5989 ctx_reg_offset = 5990 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5991 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5992 amdgpu_ring_write(ring, ctx_reg_offset); 5993 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5994 5995 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5996 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5997 5998 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5999 amdgpu_ring_write(ring, 0); 6000 6001 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6002 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6003 amdgpu_ring_write(ring, 0x8000); 6004 amdgpu_ring_write(ring, 0x8000); 6005 6006 amdgpu_ring_commit(ring); 6007 6008 /* submit cs packet to copy state 0 to next available state */ 6009 if (adev->gfx.num_gfx_rings > 1) { 6010 /* maximum supported gfx ring is 2 */ 6011 ring = &adev->gfx.gfx_ring[1]; 6012 r = amdgpu_ring_alloc(ring, 2); 6013 if (r) { 6014 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6015 return r; 6016 } 6017 6018 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6019 amdgpu_ring_write(ring, 0); 6020 6021 amdgpu_ring_commit(ring); 6022 } 6023 return 0; 6024 } 6025 6026 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6027 CP_PIPE_ID pipe) 6028 { 6029 u32 tmp; 6030 6031 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6032 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6033 6034 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6035 } 6036 6037 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6038 struct amdgpu_ring *ring) 6039 { 6040 u32 tmp; 6041 6042 if (!amdgpu_async_gfx_ring) { 6043 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6044 if (ring->use_doorbell) { 6045 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6046 DOORBELL_OFFSET, ring->doorbell_index); 6047 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6048 DOORBELL_EN, 1); 6049 } else { 6050 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6051 DOORBELL_EN, 0); 6052 } 6053 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6054 } 6055 switch (adev->ip_versions[GC_HWIP][0]) { 6056 case IP_VERSION(10, 3, 0): 6057 case IP_VERSION(10, 3, 2): 6058 case IP_VERSION(10, 3, 1): 6059 case IP_VERSION(10, 3, 4): 6060 case IP_VERSION(10, 3, 5): 6061 case IP_VERSION(10, 3, 6): 6062 case IP_VERSION(10, 3, 3): 6063 case IP_VERSION(10, 3, 7): 6064 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6065 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6066 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6067 6068 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6069 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6070 break; 6071 default: 6072 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6073 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6074 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6075 6076 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6077 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6078 break; 6079 } 6080 } 6081 6082 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6083 { 6084 struct amdgpu_ring *ring; 6085 u32 tmp; 6086 u32 rb_bufsz; 6087 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6088 6089 /* Set the write pointer delay */ 6090 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6091 6092 /* set the RB to use vmid 0 */ 6093 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6094 6095 /* Init gfx ring 0 for pipe 0 */ 6096 mutex_lock(&adev->srbm_mutex); 6097 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6098 6099 /* Set ring buffer size */ 6100 ring = &adev->gfx.gfx_ring[0]; 6101 rb_bufsz = order_base_2(ring->ring_size / 8); 6102 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6103 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6104 #ifdef __BIG_ENDIAN 6105 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6106 #endif 6107 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6108 6109 /* Initialize the ring buffer's write pointers */ 6110 ring->wptr = 0; 6111 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6112 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6113 6114 /* set the wb address wether it's enabled or not */ 6115 rptr_addr = ring->rptr_gpu_addr; 6116 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6117 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6118 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6119 6120 wptr_gpu_addr = ring->wptr_gpu_addr; 6121 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6122 lower_32_bits(wptr_gpu_addr)); 6123 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6124 upper_32_bits(wptr_gpu_addr)); 6125 6126 mdelay(1); 6127 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6128 6129 rb_addr = ring->gpu_addr >> 8; 6130 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6131 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6132 6133 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6134 6135 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6136 mutex_unlock(&adev->srbm_mutex); 6137 6138 /* Init gfx ring 1 for pipe 1 */ 6139 if (adev->gfx.num_gfx_rings > 1) { 6140 mutex_lock(&adev->srbm_mutex); 6141 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6142 /* maximum supported gfx ring is 2 */ 6143 ring = &adev->gfx.gfx_ring[1]; 6144 rb_bufsz = order_base_2(ring->ring_size / 8); 6145 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6146 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6147 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6148 /* Initialize the ring buffer's write pointers */ 6149 ring->wptr = 0; 6150 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6151 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6152 /* Set the wb address wether it's enabled or not */ 6153 rptr_addr = ring->rptr_gpu_addr; 6154 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6155 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6156 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6157 wptr_gpu_addr = ring->wptr_gpu_addr; 6158 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6159 lower_32_bits(wptr_gpu_addr)); 6160 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6161 upper_32_bits(wptr_gpu_addr)); 6162 6163 mdelay(1); 6164 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6165 6166 rb_addr = ring->gpu_addr >> 8; 6167 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6168 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6169 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6170 6171 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6172 mutex_unlock(&adev->srbm_mutex); 6173 } 6174 /* Switch to pipe 0 */ 6175 mutex_lock(&adev->srbm_mutex); 6176 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6177 mutex_unlock(&adev->srbm_mutex); 6178 6179 /* start the ring */ 6180 gfx_v10_0_cp_gfx_start(adev); 6181 6182 return 0; 6183 } 6184 6185 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6186 { 6187 if (enable) { 6188 switch (adev->ip_versions[GC_HWIP][0]) { 6189 case IP_VERSION(10, 3, 0): 6190 case IP_VERSION(10, 3, 2): 6191 case IP_VERSION(10, 3, 1): 6192 case IP_VERSION(10, 3, 4): 6193 case IP_VERSION(10, 3, 5): 6194 case IP_VERSION(10, 3, 6): 6195 case IP_VERSION(10, 3, 3): 6196 case IP_VERSION(10, 3, 7): 6197 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6198 break; 6199 default: 6200 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6201 break; 6202 } 6203 } else { 6204 switch (adev->ip_versions[GC_HWIP][0]) { 6205 case IP_VERSION(10, 3, 0): 6206 case IP_VERSION(10, 3, 2): 6207 case IP_VERSION(10, 3, 1): 6208 case IP_VERSION(10, 3, 4): 6209 case IP_VERSION(10, 3, 5): 6210 case IP_VERSION(10, 3, 6): 6211 case IP_VERSION(10, 3, 3): 6212 case IP_VERSION(10, 3, 7): 6213 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6214 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6215 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6216 break; 6217 default: 6218 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6219 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6220 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6221 break; 6222 } 6223 adev->gfx.kiq[0].ring.sched.ready = false; 6224 } 6225 udelay(50); 6226 } 6227 6228 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6229 { 6230 const struct gfx_firmware_header_v1_0 *mec_hdr; 6231 const __le32 *fw_data; 6232 unsigned int i; 6233 u32 tmp; 6234 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6235 6236 if (!adev->gfx.mec_fw) 6237 return -EINVAL; 6238 6239 gfx_v10_0_cp_compute_enable(adev, false); 6240 6241 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6242 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6243 6244 fw_data = (const __le32 *) 6245 (adev->gfx.mec_fw->data + 6246 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6247 6248 /* Trigger an invalidation of the L1 instruction caches */ 6249 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6250 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6251 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6252 6253 /* Wait for invalidation complete */ 6254 for (i = 0; i < usec_timeout; i++) { 6255 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6256 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6257 INVALIDATE_CACHE_COMPLETE)) 6258 break; 6259 udelay(1); 6260 } 6261 6262 if (i >= usec_timeout) { 6263 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6264 return -EINVAL; 6265 } 6266 6267 if (amdgpu_emu_mode == 1) 6268 adev->hdp.funcs->flush_hdp(adev, NULL); 6269 6270 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6271 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6272 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6273 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6274 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6275 6276 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6277 0xFFFFF000); 6278 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6279 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6280 6281 /* MEC1 */ 6282 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6283 6284 for (i = 0; i < mec_hdr->jt_size; i++) 6285 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6286 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6287 6288 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6289 6290 /* 6291 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6292 * different microcode than MEC1. 6293 */ 6294 6295 return 0; 6296 } 6297 6298 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6299 { 6300 uint32_t tmp; 6301 struct amdgpu_device *adev = ring->adev; 6302 6303 /* tell RLC which is KIQ queue */ 6304 switch (adev->ip_versions[GC_HWIP][0]) { 6305 case IP_VERSION(10, 3, 0): 6306 case IP_VERSION(10, 3, 2): 6307 case IP_VERSION(10, 3, 1): 6308 case IP_VERSION(10, 3, 4): 6309 case IP_VERSION(10, 3, 5): 6310 case IP_VERSION(10, 3, 6): 6311 case IP_VERSION(10, 3, 3): 6312 case IP_VERSION(10, 3, 7): 6313 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6314 tmp &= 0xffffff00; 6315 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6316 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6317 tmp |= 0x80; 6318 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6319 break; 6320 default: 6321 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6322 tmp &= 0xffffff00; 6323 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6324 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6325 tmp |= 0x80; 6326 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6327 break; 6328 } 6329 } 6330 6331 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6332 struct v10_gfx_mqd *mqd, 6333 struct amdgpu_mqd_prop *prop) 6334 { 6335 bool priority = 0; 6336 u32 tmp; 6337 6338 /* set up default queue priority level 6339 * 0x0 = low priority, 0x1 = high priority 6340 */ 6341 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6342 priority = 1; 6343 6344 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6345 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6346 mqd->cp_gfx_hqd_queue_priority = tmp; 6347 } 6348 6349 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6350 struct amdgpu_mqd_prop *prop) 6351 { 6352 struct v10_gfx_mqd *mqd = m; 6353 uint64_t hqd_gpu_addr, wb_gpu_addr; 6354 uint32_t tmp; 6355 uint32_t rb_bufsz; 6356 6357 /* set up gfx hqd wptr */ 6358 mqd->cp_gfx_hqd_wptr = 0; 6359 mqd->cp_gfx_hqd_wptr_hi = 0; 6360 6361 /* set the pointer to the MQD */ 6362 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6363 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6364 6365 /* set up mqd control */ 6366 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6367 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6368 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6369 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6370 mqd->cp_gfx_mqd_control = tmp; 6371 6372 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6373 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6374 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6375 mqd->cp_gfx_hqd_vmid = 0; 6376 6377 /* set up gfx queue priority */ 6378 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6379 6380 /* set up time quantum */ 6381 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6382 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6383 mqd->cp_gfx_hqd_quantum = tmp; 6384 6385 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6386 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6387 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6388 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6389 6390 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6391 wb_gpu_addr = prop->rptr_gpu_addr; 6392 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6393 mqd->cp_gfx_hqd_rptr_addr_hi = 6394 upper_32_bits(wb_gpu_addr) & 0xffff; 6395 6396 /* set up rb_wptr_poll addr */ 6397 wb_gpu_addr = prop->wptr_gpu_addr; 6398 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6399 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6400 6401 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6402 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6403 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6404 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6405 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6406 #ifdef __BIG_ENDIAN 6407 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6408 #endif 6409 mqd->cp_gfx_hqd_cntl = tmp; 6410 6411 /* set up cp_doorbell_control */ 6412 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6413 if (prop->use_doorbell) { 6414 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6415 DOORBELL_OFFSET, prop->doorbell_index); 6416 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6417 DOORBELL_EN, 1); 6418 } else 6419 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6420 DOORBELL_EN, 0); 6421 mqd->cp_rb_doorbell_control = tmp; 6422 6423 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6424 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6425 6426 /* active the queue */ 6427 mqd->cp_gfx_hqd_active = 1; 6428 6429 return 0; 6430 } 6431 6432 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6433 { 6434 struct amdgpu_device *adev = ring->adev; 6435 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6436 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6437 6438 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6439 memset((void *)mqd, 0, sizeof(*mqd)); 6440 mutex_lock(&adev->srbm_mutex); 6441 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6442 amdgpu_ring_init_mqd(ring); 6443 6444 /* 6445 * if there are 2 gfx rings, set the lower doorbell 6446 * range of the first ring, otherwise the range of 6447 * the second ring will override the first ring 6448 */ 6449 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6450 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6451 6452 nv_grbm_select(adev, 0, 0, 0, 0); 6453 mutex_unlock(&adev->srbm_mutex); 6454 if (adev->gfx.me.mqd_backup[mqd_idx]) 6455 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6456 } else { 6457 /* restore mqd with the backup copy */ 6458 if (adev->gfx.me.mqd_backup[mqd_idx]) 6459 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6460 /* reset the ring */ 6461 ring->wptr = 0; 6462 *ring->wptr_cpu_addr = 0; 6463 amdgpu_ring_clear_ring(ring); 6464 } 6465 6466 return 0; 6467 } 6468 6469 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6470 { 6471 int r, i; 6472 struct amdgpu_ring *ring; 6473 6474 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6475 ring = &adev->gfx.gfx_ring[i]; 6476 6477 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6478 if (unlikely(r != 0)) 6479 return r; 6480 6481 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6482 if (!r) { 6483 r = gfx_v10_0_gfx_init_queue(ring); 6484 amdgpu_bo_kunmap(ring->mqd_obj); 6485 ring->mqd_ptr = NULL; 6486 } 6487 amdgpu_bo_unreserve(ring->mqd_obj); 6488 if (r) 6489 return r; 6490 } 6491 6492 r = amdgpu_gfx_enable_kgq(adev, 0); 6493 if (r) 6494 return r; 6495 6496 return gfx_v10_0_cp_gfx_start(adev); 6497 } 6498 6499 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6500 struct amdgpu_mqd_prop *prop) 6501 { 6502 struct v10_compute_mqd *mqd = m; 6503 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6504 uint32_t tmp; 6505 6506 mqd->header = 0xC0310800; 6507 mqd->compute_pipelinestat_enable = 0x00000001; 6508 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6509 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6510 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6511 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6512 mqd->compute_misc_reserved = 0x00000003; 6513 6514 eop_base_addr = prop->eop_gpu_addr >> 8; 6515 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6516 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6517 6518 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6519 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6520 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6521 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6522 6523 mqd->cp_hqd_eop_control = tmp; 6524 6525 /* enable doorbell? */ 6526 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6527 6528 if (prop->use_doorbell) { 6529 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6530 DOORBELL_OFFSET, prop->doorbell_index); 6531 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6532 DOORBELL_EN, 1); 6533 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6534 DOORBELL_SOURCE, 0); 6535 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6536 DOORBELL_HIT, 0); 6537 } else { 6538 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6539 DOORBELL_EN, 0); 6540 } 6541 6542 mqd->cp_hqd_pq_doorbell_control = tmp; 6543 6544 /* disable the queue if it's active */ 6545 mqd->cp_hqd_dequeue_request = 0; 6546 mqd->cp_hqd_pq_rptr = 0; 6547 mqd->cp_hqd_pq_wptr_lo = 0; 6548 mqd->cp_hqd_pq_wptr_hi = 0; 6549 6550 /* set the pointer to the MQD */ 6551 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6552 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6553 6554 /* set MQD vmid to 0 */ 6555 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6556 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6557 mqd->cp_mqd_control = tmp; 6558 6559 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6560 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6561 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6562 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6563 6564 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6565 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6566 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6567 (order_base_2(prop->queue_size / 4) - 1)); 6568 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6569 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6570 #ifdef __BIG_ENDIAN 6571 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6572 #endif 6573 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6574 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6575 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6576 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6577 mqd->cp_hqd_pq_control = tmp; 6578 6579 /* set the wb address whether it's enabled or not */ 6580 wb_gpu_addr = prop->rptr_gpu_addr; 6581 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6582 mqd->cp_hqd_pq_rptr_report_addr_hi = 6583 upper_32_bits(wb_gpu_addr) & 0xffff; 6584 6585 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6586 wb_gpu_addr = prop->wptr_gpu_addr; 6587 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6588 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6589 6590 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6591 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6592 6593 /* set the vmid for the queue */ 6594 mqd->cp_hqd_vmid = 0; 6595 6596 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6597 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6598 mqd->cp_hqd_persistent_state = tmp; 6599 6600 /* set MIN_IB_AVAIL_SIZE */ 6601 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6602 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6603 mqd->cp_hqd_ib_control = tmp; 6604 6605 /* set static priority for a compute queue/ring */ 6606 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6607 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6608 6609 mqd->cp_hqd_active = prop->hqd_active; 6610 6611 return 0; 6612 } 6613 6614 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6615 { 6616 struct amdgpu_device *adev = ring->adev; 6617 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6618 int j; 6619 6620 /* inactivate the queue */ 6621 if (amdgpu_sriov_vf(adev)) 6622 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6623 6624 /* disable wptr polling */ 6625 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6626 6627 /* disable the queue if it's active */ 6628 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6629 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6630 for (j = 0; j < adev->usec_timeout; j++) { 6631 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6632 break; 6633 udelay(1); 6634 } 6635 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6636 mqd->cp_hqd_dequeue_request); 6637 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6638 mqd->cp_hqd_pq_rptr); 6639 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6640 mqd->cp_hqd_pq_wptr_lo); 6641 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6642 mqd->cp_hqd_pq_wptr_hi); 6643 } 6644 6645 /* disable doorbells */ 6646 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6647 6648 /* write the EOP addr */ 6649 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6650 mqd->cp_hqd_eop_base_addr_lo); 6651 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6652 mqd->cp_hqd_eop_base_addr_hi); 6653 6654 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6655 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6656 mqd->cp_hqd_eop_control); 6657 6658 /* set the pointer to the MQD */ 6659 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6660 mqd->cp_mqd_base_addr_lo); 6661 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6662 mqd->cp_mqd_base_addr_hi); 6663 6664 /* set MQD vmid to 0 */ 6665 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6666 mqd->cp_mqd_control); 6667 6668 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6669 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6670 mqd->cp_hqd_pq_base_lo); 6671 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6672 mqd->cp_hqd_pq_base_hi); 6673 6674 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6675 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6676 mqd->cp_hqd_pq_control); 6677 6678 /* set the wb address whether it's enabled or not */ 6679 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6680 mqd->cp_hqd_pq_rptr_report_addr_lo); 6681 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6682 mqd->cp_hqd_pq_rptr_report_addr_hi); 6683 6684 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6685 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6686 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6687 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6688 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6689 6690 /* enable the doorbell if requested */ 6691 if (ring->use_doorbell) { 6692 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6693 (adev->doorbell_index.kiq * 2) << 2); 6694 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6695 (adev->doorbell_index.userqueue_end * 2) << 2); 6696 } 6697 6698 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6699 mqd->cp_hqd_pq_doorbell_control); 6700 6701 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6702 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6703 mqd->cp_hqd_pq_wptr_lo); 6704 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6705 mqd->cp_hqd_pq_wptr_hi); 6706 6707 /* set the vmid for the queue */ 6708 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6709 6710 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6711 mqd->cp_hqd_persistent_state); 6712 6713 /* activate the queue */ 6714 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6715 mqd->cp_hqd_active); 6716 6717 if (ring->use_doorbell) 6718 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6719 6720 return 0; 6721 } 6722 6723 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6724 { 6725 struct amdgpu_device *adev = ring->adev; 6726 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6727 6728 gfx_v10_0_kiq_setting(ring); 6729 6730 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6731 /* reset MQD to a clean status */ 6732 if (adev->gfx.kiq[0].mqd_backup) 6733 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 6734 6735 /* reset ring buffer */ 6736 ring->wptr = 0; 6737 amdgpu_ring_clear_ring(ring); 6738 6739 mutex_lock(&adev->srbm_mutex); 6740 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6741 gfx_v10_0_kiq_init_register(ring); 6742 nv_grbm_select(adev, 0, 0, 0, 0); 6743 mutex_unlock(&adev->srbm_mutex); 6744 } else { 6745 memset((void *)mqd, 0, sizeof(*mqd)); 6746 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 6747 amdgpu_ring_clear_ring(ring); 6748 mutex_lock(&adev->srbm_mutex); 6749 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6750 amdgpu_ring_init_mqd(ring); 6751 gfx_v10_0_kiq_init_register(ring); 6752 nv_grbm_select(adev, 0, 0, 0, 0); 6753 mutex_unlock(&adev->srbm_mutex); 6754 6755 if (adev->gfx.kiq[0].mqd_backup) 6756 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 6757 } 6758 6759 return 0; 6760 } 6761 6762 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6763 { 6764 struct amdgpu_device *adev = ring->adev; 6765 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6766 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6767 6768 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6769 memset((void *)mqd, 0, sizeof(*mqd)); 6770 mutex_lock(&adev->srbm_mutex); 6771 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6772 amdgpu_ring_init_mqd(ring); 6773 nv_grbm_select(adev, 0, 0, 0, 0); 6774 mutex_unlock(&adev->srbm_mutex); 6775 6776 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6777 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6778 } else { 6779 /* restore MQD to a clean status */ 6780 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6781 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6782 /* reset ring buffer */ 6783 ring->wptr = 0; 6784 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6785 amdgpu_ring_clear_ring(ring); 6786 } 6787 6788 return 0; 6789 } 6790 6791 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6792 { 6793 struct amdgpu_ring *ring; 6794 int r; 6795 6796 ring = &adev->gfx.kiq[0].ring; 6797 6798 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6799 if (unlikely(r != 0)) 6800 return r; 6801 6802 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6803 if (unlikely(r != 0)) { 6804 amdgpu_bo_unreserve(ring->mqd_obj); 6805 return r; 6806 } 6807 6808 gfx_v10_0_kiq_init_queue(ring); 6809 amdgpu_bo_kunmap(ring->mqd_obj); 6810 ring->mqd_ptr = NULL; 6811 amdgpu_bo_unreserve(ring->mqd_obj); 6812 return 0; 6813 } 6814 6815 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6816 { 6817 struct amdgpu_ring *ring = NULL; 6818 int r = 0, i; 6819 6820 gfx_v10_0_cp_compute_enable(adev, true); 6821 6822 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6823 ring = &adev->gfx.compute_ring[i]; 6824 6825 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6826 if (unlikely(r != 0)) 6827 goto done; 6828 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6829 if (!r) { 6830 r = gfx_v10_0_kcq_init_queue(ring); 6831 amdgpu_bo_kunmap(ring->mqd_obj); 6832 ring->mqd_ptr = NULL; 6833 } 6834 amdgpu_bo_unreserve(ring->mqd_obj); 6835 if (r) 6836 goto done; 6837 } 6838 6839 r = amdgpu_gfx_enable_kcq(adev, 0); 6840 done: 6841 return r; 6842 } 6843 6844 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6845 { 6846 int r, i; 6847 struct amdgpu_ring *ring; 6848 6849 if (!(adev->flags & AMD_IS_APU)) 6850 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6851 6852 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6853 /* legacy firmware loading */ 6854 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6855 if (r) 6856 return r; 6857 6858 r = gfx_v10_0_cp_compute_load_microcode(adev); 6859 if (r) 6860 return r; 6861 } 6862 6863 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 6864 r = amdgpu_mes_kiq_hw_init(adev); 6865 else 6866 r = gfx_v10_0_kiq_resume(adev); 6867 if (r) 6868 return r; 6869 6870 r = gfx_v10_0_kcq_resume(adev); 6871 if (r) 6872 return r; 6873 6874 if (!amdgpu_async_gfx_ring) { 6875 r = gfx_v10_0_cp_gfx_resume(adev); 6876 if (r) 6877 return r; 6878 } else { 6879 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6880 if (r) 6881 return r; 6882 } 6883 6884 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6885 ring = &adev->gfx.gfx_ring[i]; 6886 r = amdgpu_ring_test_helper(ring); 6887 if (r) 6888 return r; 6889 } 6890 6891 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6892 ring = &adev->gfx.compute_ring[i]; 6893 r = amdgpu_ring_test_helper(ring); 6894 if (r) 6895 return r; 6896 } 6897 6898 return 0; 6899 } 6900 6901 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6902 { 6903 gfx_v10_0_cp_gfx_enable(adev, enable); 6904 gfx_v10_0_cp_compute_enable(adev, enable); 6905 } 6906 6907 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6908 { 6909 uint32_t data, pattern = 0xDEADBEEF; 6910 6911 /* 6912 * check if mmVGT_ESGS_RING_SIZE_UMD 6913 * has been remapped to mmVGT_ESGS_RING_SIZE 6914 */ 6915 switch (adev->ip_versions[GC_HWIP][0]) { 6916 case IP_VERSION(10, 3, 0): 6917 case IP_VERSION(10, 3, 2): 6918 case IP_VERSION(10, 3, 4): 6919 case IP_VERSION(10, 3, 5): 6920 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6921 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6922 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6923 6924 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6925 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6926 return true; 6927 } 6928 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6929 break; 6930 case IP_VERSION(10, 3, 1): 6931 case IP_VERSION(10, 3, 3): 6932 case IP_VERSION(10, 3, 6): 6933 case IP_VERSION(10, 3, 7): 6934 return true; 6935 default: 6936 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6937 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 6938 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6939 6940 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 6941 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6942 return true; 6943 } 6944 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 6945 break; 6946 } 6947 6948 return false; 6949 } 6950 6951 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 6952 { 6953 uint32_t data; 6954 6955 if (amdgpu_sriov_vf(adev)) 6956 return; 6957 6958 /* 6959 * Initialize cam_index to 0 6960 * index will auto-inc after each data writing 6961 */ 6962 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 6963 6964 switch (adev->ip_versions[GC_HWIP][0]) { 6965 case IP_VERSION(10, 3, 0): 6966 case IP_VERSION(10, 3, 2): 6967 case IP_VERSION(10, 3, 1): 6968 case IP_VERSION(10, 3, 4): 6969 case IP_VERSION(10, 3, 5): 6970 case IP_VERSION(10, 3, 6): 6971 case IP_VERSION(10, 3, 3): 6972 case IP_VERSION(10, 3, 7): 6973 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 6974 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 6975 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6976 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 6977 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6978 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6979 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 6980 6981 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 6982 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 6983 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6984 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 6985 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6986 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6987 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 6988 6989 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 6990 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 6991 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6992 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 6993 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6994 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6995 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 6996 6997 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 6998 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 6999 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7000 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7001 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7002 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7003 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7004 7005 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7006 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7007 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7008 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7009 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7010 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7011 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7012 7013 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7014 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7015 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7016 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7017 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7018 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7019 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7020 7021 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7022 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7023 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7024 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7025 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7026 break; 7027 default: 7028 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7029 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7030 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7031 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7032 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7033 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7034 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7035 7036 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7037 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7038 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7039 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7040 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7041 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7042 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7043 7044 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7045 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7046 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7047 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7048 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7049 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7050 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7051 7052 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7053 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7054 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7055 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7056 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7057 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7058 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7059 7060 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7061 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7062 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7063 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7064 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7065 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7066 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7067 7068 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7069 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7070 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7071 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7072 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7073 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7074 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7075 7076 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7077 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7078 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7079 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7080 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7081 break; 7082 } 7083 7084 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7085 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7086 } 7087 7088 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7089 { 7090 uint32_t data; 7091 7092 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7093 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7094 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7095 7096 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7097 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7098 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7099 } 7100 7101 static int gfx_v10_0_hw_init(void *handle) 7102 { 7103 int r; 7104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7105 7106 if (!amdgpu_emu_mode) 7107 gfx_v10_0_init_golden_registers(adev); 7108 7109 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7110 /** 7111 * For gfx 10, rlc firmware loading relies on smu firmware is 7112 * loaded firstly, so in direct type, it has to load smc ucode 7113 * here before rlc. 7114 */ 7115 if (!(adev->flags & AMD_IS_APU)) { 7116 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7117 if (r) 7118 return r; 7119 } 7120 gfx_v10_0_disable_gpa_mode(adev); 7121 } 7122 7123 /* if GRBM CAM not remapped, set up the remapping */ 7124 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7125 gfx_v10_0_setup_grbm_cam_remapping(adev); 7126 7127 gfx_v10_0_constants_init(adev); 7128 7129 r = gfx_v10_0_rlc_resume(adev); 7130 if (r) 7131 return r; 7132 7133 /* 7134 * init golden registers and rlc resume may override some registers, 7135 * reconfig them here 7136 */ 7137 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) || 7138 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) || 7139 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 7140 gfx_v10_0_tcp_harvest(adev); 7141 7142 r = gfx_v10_0_cp_resume(adev); 7143 if (r) 7144 return r; 7145 7146 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 7147 gfx_v10_3_program_pbb_mode(adev); 7148 7149 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 7150 gfx_v10_3_set_power_brake_sequence(adev); 7151 7152 return r; 7153 } 7154 7155 static int gfx_v10_0_hw_fini(void *handle) 7156 { 7157 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7158 7159 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7160 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7161 7162 if (!adev->no_hw_access) { 7163 if (amdgpu_async_gfx_ring) { 7164 if (amdgpu_gfx_disable_kgq(adev, 0)) 7165 DRM_ERROR("KGQ disable failed\n"); 7166 } 7167 7168 if (amdgpu_gfx_disable_kcq(adev, 0)) 7169 DRM_ERROR("KCQ disable failed\n"); 7170 } 7171 7172 if (amdgpu_sriov_vf(adev)) { 7173 gfx_v10_0_cp_gfx_enable(adev, false); 7174 /* Remove the steps of clearing KIQ position. 7175 * It causes GFX hang when another Win guest is rendering. 7176 */ 7177 return 0; 7178 } 7179 gfx_v10_0_cp_enable(adev, false); 7180 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7181 7182 return 0; 7183 } 7184 7185 static int gfx_v10_0_suspend(void *handle) 7186 { 7187 return gfx_v10_0_hw_fini(handle); 7188 } 7189 7190 static int gfx_v10_0_resume(void *handle) 7191 { 7192 return gfx_v10_0_hw_init(handle); 7193 } 7194 7195 static bool gfx_v10_0_is_idle(void *handle) 7196 { 7197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7198 7199 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7200 GRBM_STATUS, GUI_ACTIVE)) 7201 return false; 7202 else 7203 return true; 7204 } 7205 7206 static int gfx_v10_0_wait_for_idle(void *handle) 7207 { 7208 unsigned int i; 7209 u32 tmp; 7210 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7211 7212 for (i = 0; i < adev->usec_timeout; i++) { 7213 /* read MC_STATUS */ 7214 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7215 GRBM_STATUS__GUI_ACTIVE_MASK; 7216 7217 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7218 return 0; 7219 udelay(1); 7220 } 7221 return -ETIMEDOUT; 7222 } 7223 7224 static int gfx_v10_0_soft_reset(void *handle) 7225 { 7226 u32 grbm_soft_reset = 0; 7227 u32 tmp; 7228 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7229 7230 /* GRBM_STATUS */ 7231 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7232 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7233 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7234 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7235 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7236 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7237 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7238 GRBM_SOFT_RESET, SOFT_RESET_CP, 7239 1); 7240 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7241 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7242 1); 7243 } 7244 7245 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7246 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7247 GRBM_SOFT_RESET, SOFT_RESET_CP, 7248 1); 7249 } 7250 7251 /* GRBM_STATUS2 */ 7252 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7253 switch (adev->ip_versions[GC_HWIP][0]) { 7254 case IP_VERSION(10, 3, 0): 7255 case IP_VERSION(10, 3, 2): 7256 case IP_VERSION(10, 3, 1): 7257 case IP_VERSION(10, 3, 4): 7258 case IP_VERSION(10, 3, 5): 7259 case IP_VERSION(10, 3, 6): 7260 case IP_VERSION(10, 3, 3): 7261 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7262 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7263 GRBM_SOFT_RESET, 7264 SOFT_RESET_RLC, 7265 1); 7266 break; 7267 default: 7268 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7269 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7270 GRBM_SOFT_RESET, 7271 SOFT_RESET_RLC, 7272 1); 7273 break; 7274 } 7275 7276 if (grbm_soft_reset) { 7277 /* stop the rlc */ 7278 gfx_v10_0_rlc_stop(adev); 7279 7280 /* Disable GFX parsing/prefetching */ 7281 gfx_v10_0_cp_gfx_enable(adev, false); 7282 7283 /* Disable MEC parsing/prefetching */ 7284 gfx_v10_0_cp_compute_enable(adev, false); 7285 7286 if (grbm_soft_reset) { 7287 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7288 tmp |= grbm_soft_reset; 7289 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7290 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7291 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7292 7293 udelay(50); 7294 7295 tmp &= ~grbm_soft_reset; 7296 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7297 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7298 } 7299 7300 /* Wait a little for things to settle down */ 7301 udelay(50); 7302 } 7303 return 0; 7304 } 7305 7306 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7307 { 7308 uint64_t clock, clock_lo, clock_hi, hi_check; 7309 7310 switch (adev->ip_versions[GC_HWIP][0]) { 7311 case IP_VERSION(10, 3, 1): 7312 case IP_VERSION(10, 3, 3): 7313 case IP_VERSION(10, 3, 7): 7314 preempt_disable(); 7315 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7316 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7317 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7318 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7319 * roughly every 42 seconds. 7320 */ 7321 if (hi_check != clock_hi) { 7322 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7323 clock_hi = hi_check; 7324 } 7325 preempt_enable(); 7326 clock = clock_lo | (clock_hi << 32ULL); 7327 break; 7328 case IP_VERSION(10, 3, 6): 7329 preempt_disable(); 7330 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7331 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7332 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7333 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7334 * roughly every 42 seconds. 7335 */ 7336 if (hi_check != clock_hi) { 7337 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7338 clock_hi = hi_check; 7339 } 7340 preempt_enable(); 7341 clock = clock_lo | (clock_hi << 32ULL); 7342 break; 7343 default: 7344 preempt_disable(); 7345 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7346 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7347 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7348 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7349 * roughly every 42 seconds. 7350 */ 7351 if (hi_check != clock_hi) { 7352 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7353 clock_hi = hi_check; 7354 } 7355 preempt_enable(); 7356 clock = clock_lo | (clock_hi << 32ULL); 7357 break; 7358 } 7359 return clock; 7360 } 7361 7362 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7363 uint32_t vmid, 7364 uint32_t gds_base, uint32_t gds_size, 7365 uint32_t gws_base, uint32_t gws_size, 7366 uint32_t oa_base, uint32_t oa_size) 7367 { 7368 struct amdgpu_device *adev = ring->adev; 7369 7370 /* GDS Base */ 7371 gfx_v10_0_write_data_to_reg(ring, 0, false, 7372 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7373 gds_base); 7374 7375 /* GDS Size */ 7376 gfx_v10_0_write_data_to_reg(ring, 0, false, 7377 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7378 gds_size); 7379 7380 /* GWS */ 7381 gfx_v10_0_write_data_to_reg(ring, 0, false, 7382 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7383 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7384 7385 /* OA */ 7386 gfx_v10_0_write_data_to_reg(ring, 0, false, 7387 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7388 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7389 } 7390 7391 static int gfx_v10_0_early_init(void *handle) 7392 { 7393 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7394 7395 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7396 7397 switch (adev->ip_versions[GC_HWIP][0]) { 7398 case IP_VERSION(10, 1, 10): 7399 case IP_VERSION(10, 1, 1): 7400 case IP_VERSION(10, 1, 2): 7401 case IP_VERSION(10, 1, 3): 7402 case IP_VERSION(10, 1, 4): 7403 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7404 break; 7405 case IP_VERSION(10, 3, 0): 7406 case IP_VERSION(10, 3, 2): 7407 case IP_VERSION(10, 3, 1): 7408 case IP_VERSION(10, 3, 4): 7409 case IP_VERSION(10, 3, 5): 7410 case IP_VERSION(10, 3, 6): 7411 case IP_VERSION(10, 3, 3): 7412 case IP_VERSION(10, 3, 7): 7413 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7414 break; 7415 default: 7416 break; 7417 } 7418 7419 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7420 AMDGPU_MAX_COMPUTE_RINGS); 7421 7422 gfx_v10_0_set_kiq_pm4_funcs(adev); 7423 gfx_v10_0_set_ring_funcs(adev); 7424 gfx_v10_0_set_irq_funcs(adev); 7425 gfx_v10_0_set_gds_init(adev); 7426 gfx_v10_0_set_rlc_funcs(adev); 7427 gfx_v10_0_set_mqd_funcs(adev); 7428 7429 /* init rlcg reg access ctrl */ 7430 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7431 7432 return gfx_v10_0_init_microcode(adev); 7433 } 7434 7435 static int gfx_v10_0_late_init(void *handle) 7436 { 7437 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7438 int r; 7439 7440 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7441 if (r) 7442 return r; 7443 7444 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7445 if (r) 7446 return r; 7447 7448 return 0; 7449 } 7450 7451 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7452 { 7453 uint32_t rlc_cntl; 7454 7455 /* if RLC is not enabled, do nothing */ 7456 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7457 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7458 } 7459 7460 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7461 { 7462 uint32_t data; 7463 unsigned int i; 7464 7465 data = RLC_SAFE_MODE__CMD_MASK; 7466 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7467 7468 switch (adev->ip_versions[GC_HWIP][0]) { 7469 case IP_VERSION(10, 3, 0): 7470 case IP_VERSION(10, 3, 2): 7471 case IP_VERSION(10, 3, 1): 7472 case IP_VERSION(10, 3, 4): 7473 case IP_VERSION(10, 3, 5): 7474 case IP_VERSION(10, 3, 6): 7475 case IP_VERSION(10, 3, 3): 7476 case IP_VERSION(10, 3, 7): 7477 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7478 7479 /* wait for RLC_SAFE_MODE */ 7480 for (i = 0; i < adev->usec_timeout; i++) { 7481 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7482 RLC_SAFE_MODE, CMD)) 7483 break; 7484 udelay(1); 7485 } 7486 break; 7487 default: 7488 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7489 7490 /* wait for RLC_SAFE_MODE */ 7491 for (i = 0; i < adev->usec_timeout; i++) { 7492 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7493 RLC_SAFE_MODE, CMD)) 7494 break; 7495 udelay(1); 7496 } 7497 break; 7498 } 7499 } 7500 7501 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7502 { 7503 uint32_t data; 7504 7505 data = RLC_SAFE_MODE__CMD_MASK; 7506 switch (adev->ip_versions[GC_HWIP][0]) { 7507 case IP_VERSION(10, 3, 0): 7508 case IP_VERSION(10, 3, 2): 7509 case IP_VERSION(10, 3, 1): 7510 case IP_VERSION(10, 3, 4): 7511 case IP_VERSION(10, 3, 5): 7512 case IP_VERSION(10, 3, 6): 7513 case IP_VERSION(10, 3, 3): 7514 case IP_VERSION(10, 3, 7): 7515 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7516 break; 7517 default: 7518 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7519 break; 7520 } 7521 } 7522 7523 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7524 bool enable) 7525 { 7526 uint32_t data, def; 7527 7528 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7529 return; 7530 7531 /* It is disabled by HW by default */ 7532 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7533 /* 0 - Disable some blocks' MGCG */ 7534 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7535 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7536 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7537 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7538 7539 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7540 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7541 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7542 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7543 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7544 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7545 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7546 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7547 7548 if (def != data) 7549 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7550 7551 /* MGLS is a global flag to control all MGLS in GFX */ 7552 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7553 /* 2 - RLC memory Light sleep */ 7554 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7555 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7556 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7557 if (def != data) 7558 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7559 } 7560 /* 3 - CP memory Light sleep */ 7561 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7562 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7563 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7564 if (def != data) 7565 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7566 } 7567 } 7568 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7569 /* 1 - MGCG_OVERRIDE */ 7570 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7571 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7572 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7573 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7574 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7575 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7576 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7577 if (def != data) 7578 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7579 7580 /* 2 - disable MGLS in CP */ 7581 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7582 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7583 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7584 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7585 } 7586 7587 /* 3 - disable MGLS in RLC */ 7588 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7589 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7590 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7591 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7592 } 7593 7594 } 7595 } 7596 7597 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7598 bool enable) 7599 { 7600 uint32_t data, def; 7601 7602 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7603 return; 7604 7605 /* Enable 3D CGCG/CGLS */ 7606 if (enable) { 7607 /* write cmd to clear cgcg/cgls ov */ 7608 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7609 7610 /* unset CGCG override */ 7611 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7612 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7613 7614 /* update CGCG and CGLS override bits */ 7615 if (def != data) 7616 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7617 7618 /* enable 3Dcgcg FSM(0x0000363f) */ 7619 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7620 data = 0; 7621 7622 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7623 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7624 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7625 7626 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7627 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7628 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7629 7630 if (def != data) 7631 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7632 7633 /* set IDLE_POLL_COUNT(0x00900100) */ 7634 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7635 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7636 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7637 if (def != data) 7638 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7639 } else { 7640 /* Disable CGCG/CGLS */ 7641 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7642 7643 /* disable cgcg, cgls should be disabled */ 7644 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7645 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7646 7647 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7648 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7649 7650 /* disable cgcg and cgls in FSM */ 7651 if (def != data) 7652 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7653 } 7654 } 7655 7656 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7657 bool enable) 7658 { 7659 uint32_t def, data; 7660 7661 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7662 return; 7663 7664 if (enable) { 7665 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7666 7667 /* unset CGCG override */ 7668 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7669 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7670 7671 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7672 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7673 7674 /* update CGCG and CGLS override bits */ 7675 if (def != data) 7676 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7677 7678 /* enable cgcg FSM(0x0000363F) */ 7679 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7680 data = 0; 7681 7682 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7683 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7684 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7685 7686 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7687 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7688 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7689 7690 if (def != data) 7691 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7692 7693 /* set IDLE_POLL_COUNT(0x00900100) */ 7694 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7695 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7696 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7697 if (def != data) 7698 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7699 } else { 7700 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7701 7702 /* reset CGCG/CGLS bits */ 7703 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7704 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7705 7706 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7707 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7708 7709 /* disable cgcg and cgls in FSM */ 7710 if (def != data) 7711 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7712 } 7713 } 7714 7715 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7716 bool enable) 7717 { 7718 uint32_t def, data; 7719 7720 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 7721 return; 7722 7723 if (enable) { 7724 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7725 /* unset FGCG override */ 7726 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7727 /* update FGCG override bits */ 7728 if (def != data) 7729 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7730 7731 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7732 /* unset RLC SRAM CLK GATER override */ 7733 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7734 /* update RLC SRAM CLK GATER override bits */ 7735 if (def != data) 7736 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7737 } else { 7738 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7739 /* reset FGCG bits */ 7740 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7741 /* disable FGCG*/ 7742 if (def != data) 7743 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7744 7745 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7746 /* reset RLC SRAM CLK GATER bits */ 7747 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7748 /* disable RLC SRAM CLK*/ 7749 if (def != data) 7750 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7751 } 7752 } 7753 7754 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 7755 { 7756 uint32_t reg_data = 0; 7757 uint32_t reg_idx = 0; 7758 uint32_t i; 7759 7760 const uint32_t tcp_ctrl_regs[] = { 7761 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7762 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7763 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7764 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7765 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7766 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7767 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7768 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7769 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7770 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7771 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 7772 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 7773 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7774 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7775 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7776 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7777 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7778 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7779 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7780 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7781 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7782 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7783 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 7784 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 7785 }; 7786 7787 const uint32_t tcp_ctrl_regs_nv12[] = { 7788 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7789 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7790 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7791 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7792 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7793 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7794 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7795 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7796 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7797 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7798 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7799 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7800 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7801 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7802 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7803 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7804 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7805 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7806 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7807 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7808 }; 7809 7810 const uint32_t sm_ctlr_regs[] = { 7811 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 7812 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 7813 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 7814 mmCGTS_SA1_QUAD1_SM_CTRL_REG 7815 }; 7816 7817 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 7818 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 7819 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7820 tcp_ctrl_regs_nv12[i]; 7821 reg_data = RREG32(reg_idx); 7822 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7823 WREG32(reg_idx, reg_data); 7824 } 7825 } else { 7826 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 7827 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7828 tcp_ctrl_regs[i]; 7829 reg_data = RREG32(reg_idx); 7830 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7831 WREG32(reg_idx, reg_data); 7832 } 7833 } 7834 7835 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 7836 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 7837 sm_ctlr_regs[i]; 7838 reg_data = RREG32(reg_idx); 7839 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 7840 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 7841 WREG32(reg_idx, reg_data); 7842 } 7843 } 7844 7845 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7846 bool enable) 7847 { 7848 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 7849 7850 if (enable) { 7851 /* enable FGCG firstly*/ 7852 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7853 /* CGCG/CGLS should be enabled after MGCG/MGLS 7854 * === MGCG + MGLS === 7855 */ 7856 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7857 /* === CGCG /CGLS for GFX 3D Only === */ 7858 gfx_v10_0_update_3d_clock_gating(adev, enable); 7859 /* === CGCG + CGLS === */ 7860 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7861 7862 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) || 7863 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) || 7864 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))) 7865 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 7866 } else { 7867 /* CGCG/CGLS should be disabled before MGCG/MGLS 7868 * === CGCG + CGLS === 7869 */ 7870 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7871 /* === CGCG /CGLS for GFX 3D Only === */ 7872 gfx_v10_0_update_3d_clock_gating(adev, enable); 7873 /* === MGCG + MGLS === */ 7874 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7875 /* disable fgcg at last*/ 7876 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7877 } 7878 7879 if (adev->cg_flags & 7880 (AMD_CG_SUPPORT_GFX_MGCG | 7881 AMD_CG_SUPPORT_GFX_CGLS | 7882 AMD_CG_SUPPORT_GFX_CGCG | 7883 AMD_CG_SUPPORT_GFX_3D_CGCG | 7884 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7885 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7886 7887 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 7888 7889 return 0; 7890 } 7891 7892 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 7893 unsigned int vmid) 7894 { 7895 u32 reg, data; 7896 7897 /* not for *_SOC15 */ 7898 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7899 if (amdgpu_sriov_is_pp_one_vf(adev)) 7900 data = RREG32_NO_KIQ(reg); 7901 else 7902 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 7903 7904 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7905 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7906 7907 if (amdgpu_sriov_is_pp_one_vf(adev)) 7908 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7909 else 7910 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7911 } 7912 7913 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid) 7914 { 7915 amdgpu_gfx_off_ctrl(adev, false); 7916 7917 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 7918 7919 amdgpu_gfx_off_ctrl(adev, true); 7920 } 7921 7922 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7923 uint32_t offset, 7924 struct soc15_reg_rlcg *entries, int arr_size) 7925 { 7926 int i; 7927 uint32_t reg; 7928 7929 if (!entries) 7930 return false; 7931 7932 for (i = 0; i < arr_size; i++) { 7933 const struct soc15_reg_rlcg *entry; 7934 7935 entry = &entries[i]; 7936 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7937 if (offset == reg) 7938 return true; 7939 } 7940 7941 return false; 7942 } 7943 7944 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7945 { 7946 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7947 } 7948 7949 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7950 { 7951 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7952 7953 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7954 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7955 else 7956 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7957 7958 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7959 7960 /* 7961 * CGPG enablement required and the register to program the hysteresis value 7962 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 7963 * in refclk count. Note that RLC FW is modified to take 16 bits from 7964 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 7965 * 7966 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 7967 * of CGPG enablement starting point. 7968 * Power/performance team will optimize it and might give a new value later. 7969 */ 7970 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 7971 switch (adev->ip_versions[GC_HWIP][0]) { 7972 case IP_VERSION(10, 3, 1): 7973 case IP_VERSION(10, 3, 3): 7974 case IP_VERSION(10, 3, 6): 7975 case IP_VERSION(10, 3, 7): 7976 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 7977 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 7978 break; 7979 default: 7980 break; 7981 } 7982 } 7983 } 7984 7985 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7986 { 7987 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 7988 7989 gfx_v10_cntl_power_gating(adev, enable); 7990 7991 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 7992 } 7993 7994 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 7995 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7996 .set_safe_mode = gfx_v10_0_set_safe_mode, 7997 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7998 .init = gfx_v10_0_rlc_init, 7999 .get_csb_size = gfx_v10_0_get_csb_size, 8000 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8001 .resume = gfx_v10_0_rlc_resume, 8002 .stop = gfx_v10_0_rlc_stop, 8003 .reset = gfx_v10_0_rlc_reset, 8004 .start = gfx_v10_0_rlc_start, 8005 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8006 }; 8007 8008 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8009 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8010 .set_safe_mode = gfx_v10_0_set_safe_mode, 8011 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8012 .init = gfx_v10_0_rlc_init, 8013 .get_csb_size = gfx_v10_0_get_csb_size, 8014 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8015 .resume = gfx_v10_0_rlc_resume, 8016 .stop = gfx_v10_0_rlc_stop, 8017 .reset = gfx_v10_0_rlc_reset, 8018 .start = gfx_v10_0_rlc_start, 8019 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8020 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8021 }; 8022 8023 static int gfx_v10_0_set_powergating_state(void *handle, 8024 enum amd_powergating_state state) 8025 { 8026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8027 bool enable = (state == AMD_PG_STATE_GATE); 8028 8029 if (amdgpu_sriov_vf(adev)) 8030 return 0; 8031 8032 switch (adev->ip_versions[GC_HWIP][0]) { 8033 case IP_VERSION(10, 1, 10): 8034 case IP_VERSION(10, 1, 1): 8035 case IP_VERSION(10, 1, 2): 8036 case IP_VERSION(10, 3, 0): 8037 case IP_VERSION(10, 3, 2): 8038 case IP_VERSION(10, 3, 4): 8039 case IP_VERSION(10, 3, 5): 8040 amdgpu_gfx_off_ctrl(adev, enable); 8041 break; 8042 case IP_VERSION(10, 3, 1): 8043 case IP_VERSION(10, 3, 3): 8044 case IP_VERSION(10, 3, 6): 8045 case IP_VERSION(10, 3, 7): 8046 if (!enable) 8047 amdgpu_gfx_off_ctrl(adev, false); 8048 8049 gfx_v10_cntl_pg(adev, enable); 8050 8051 if (enable) 8052 amdgpu_gfx_off_ctrl(adev, true); 8053 8054 break; 8055 default: 8056 break; 8057 } 8058 return 0; 8059 } 8060 8061 static int gfx_v10_0_set_clockgating_state(void *handle, 8062 enum amd_clockgating_state state) 8063 { 8064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8065 8066 if (amdgpu_sriov_vf(adev)) 8067 return 0; 8068 8069 switch (adev->ip_versions[GC_HWIP][0]) { 8070 case IP_VERSION(10, 1, 10): 8071 case IP_VERSION(10, 1, 1): 8072 case IP_VERSION(10, 1, 2): 8073 case IP_VERSION(10, 3, 0): 8074 case IP_VERSION(10, 3, 2): 8075 case IP_VERSION(10, 3, 1): 8076 case IP_VERSION(10, 3, 4): 8077 case IP_VERSION(10, 3, 5): 8078 case IP_VERSION(10, 3, 6): 8079 case IP_VERSION(10, 3, 3): 8080 case IP_VERSION(10, 3, 7): 8081 gfx_v10_0_update_gfx_clock_gating(adev, 8082 state == AMD_CG_STATE_GATE); 8083 break; 8084 default: 8085 break; 8086 } 8087 return 0; 8088 } 8089 8090 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8091 { 8092 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8093 int data; 8094 8095 /* AMD_CG_SUPPORT_GFX_FGCG */ 8096 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8097 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8098 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8099 8100 /* AMD_CG_SUPPORT_GFX_MGCG */ 8101 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8102 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8103 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8104 8105 /* AMD_CG_SUPPORT_GFX_CGCG */ 8106 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8107 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8108 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8109 8110 /* AMD_CG_SUPPORT_GFX_CGLS */ 8111 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8112 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8113 8114 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8115 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8116 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8117 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8118 8119 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8120 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8121 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8122 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8123 8124 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8125 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8126 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8127 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8128 8129 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8130 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8131 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8132 } 8133 8134 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8135 { 8136 /* gfx10 is 32bit rptr*/ 8137 return *(uint32_t *)ring->rptr_cpu_addr; 8138 } 8139 8140 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8141 { 8142 struct amdgpu_device *adev = ring->adev; 8143 u64 wptr; 8144 8145 /* XXX check if swapping is necessary on BE */ 8146 if (ring->use_doorbell) { 8147 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8148 } else { 8149 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8150 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8151 } 8152 8153 return wptr; 8154 } 8155 8156 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8157 { 8158 struct amdgpu_device *adev = ring->adev; 8159 uint32_t *wptr_saved; 8160 uint32_t *is_queue_unmap; 8161 uint64_t aggregated_db_index; 8162 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 8163 uint64_t wptr_tmp; 8164 8165 if (ring->is_mes_queue) { 8166 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8167 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8168 sizeof(uint32_t)); 8169 aggregated_db_index = 8170 amdgpu_mes_get_aggregated_doorbell_index(adev, 8171 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8172 8173 wptr_tmp = ring->wptr & ring->buf_mask; 8174 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8175 *wptr_saved = wptr_tmp; 8176 /* assume doorbell always being used by mes mapped queue */ 8177 if (*is_queue_unmap) { 8178 WDOORBELL64(aggregated_db_index, wptr_tmp); 8179 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8180 } else { 8181 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8182 8183 if (*is_queue_unmap) 8184 WDOORBELL64(aggregated_db_index, wptr_tmp); 8185 } 8186 } else { 8187 if (ring->use_doorbell) { 8188 /* XXX check if swapping is necessary on BE */ 8189 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8190 ring->wptr); 8191 WDOORBELL64(ring->doorbell_index, ring->wptr); 8192 } else { 8193 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8194 lower_32_bits(ring->wptr)); 8195 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8196 upper_32_bits(ring->wptr)); 8197 } 8198 } 8199 } 8200 8201 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8202 { 8203 /* gfx10 hardware is 32bit rptr */ 8204 return *(uint32_t *)ring->rptr_cpu_addr; 8205 } 8206 8207 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8208 { 8209 u64 wptr; 8210 8211 /* XXX check if swapping is necessary on BE */ 8212 if (ring->use_doorbell) 8213 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8214 else 8215 BUG(); 8216 return wptr; 8217 } 8218 8219 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8220 { 8221 struct amdgpu_device *adev = ring->adev; 8222 uint32_t *wptr_saved; 8223 uint32_t *is_queue_unmap; 8224 uint64_t aggregated_db_index; 8225 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 8226 uint64_t wptr_tmp; 8227 8228 if (ring->is_mes_queue) { 8229 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8230 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8231 sizeof(uint32_t)); 8232 aggregated_db_index = 8233 amdgpu_mes_get_aggregated_doorbell_index(adev, 8234 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8235 8236 wptr_tmp = ring->wptr & ring->buf_mask; 8237 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8238 *wptr_saved = wptr_tmp; 8239 /* assume doorbell always used by mes mapped queue */ 8240 if (*is_queue_unmap) { 8241 WDOORBELL64(aggregated_db_index, wptr_tmp); 8242 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8243 } else { 8244 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8245 8246 if (*is_queue_unmap) 8247 WDOORBELL64(aggregated_db_index, wptr_tmp); 8248 } 8249 } else { 8250 /* XXX check if swapping is necessary on BE */ 8251 if (ring->use_doorbell) { 8252 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8253 ring->wptr); 8254 WDOORBELL64(ring->doorbell_index, ring->wptr); 8255 } else { 8256 BUG(); /* only DOORBELL method supported on gfx10 now */ 8257 } 8258 } 8259 } 8260 8261 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8262 { 8263 struct amdgpu_device *adev = ring->adev; 8264 u32 ref_and_mask, reg_mem_engine; 8265 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8266 8267 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8268 switch (ring->me) { 8269 case 1: 8270 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8271 break; 8272 case 2: 8273 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8274 break; 8275 default: 8276 return; 8277 } 8278 reg_mem_engine = 0; 8279 } else { 8280 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8281 reg_mem_engine = 1; /* pfp */ 8282 } 8283 8284 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8285 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8286 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8287 ref_and_mask, ref_and_mask, 0x20); 8288 } 8289 8290 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8291 struct amdgpu_job *job, 8292 struct amdgpu_ib *ib, 8293 uint32_t flags) 8294 { 8295 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8296 u32 header, control = 0; 8297 8298 if (ib->flags & AMDGPU_IB_FLAG_CE) 8299 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8300 else 8301 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8302 8303 control |= ib->length_dw | (vmid << 24); 8304 8305 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8306 control |= INDIRECT_BUFFER_PRE_ENB(1); 8307 8308 if (flags & AMDGPU_IB_PREEMPTED) 8309 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8310 8311 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8312 gfx_v10_0_ring_emit_de_meta(ring, 8313 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8314 } 8315 8316 if (ring->is_mes_queue) 8317 /* inherit vmid from mqd */ 8318 control |= 0x400000; 8319 8320 amdgpu_ring_write(ring, header); 8321 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8322 amdgpu_ring_write(ring, 8323 #ifdef __BIG_ENDIAN 8324 (2 << 0) | 8325 #endif 8326 lower_32_bits(ib->gpu_addr)); 8327 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8328 amdgpu_ring_write(ring, control); 8329 } 8330 8331 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8332 struct amdgpu_job *job, 8333 struct amdgpu_ib *ib, 8334 uint32_t flags) 8335 { 8336 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8337 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8338 8339 if (ring->is_mes_queue) 8340 /* inherit vmid from mqd */ 8341 control |= 0x40000000; 8342 8343 /* Currently, there is a high possibility to get wave ID mismatch 8344 * between ME and GDS, leading to a hw deadlock, because ME generates 8345 * different wave IDs than the GDS expects. This situation happens 8346 * randomly when at least 5 compute pipes use GDS ordered append. 8347 * The wave IDs generated by ME are also wrong after suspend/resume. 8348 * Those are probably bugs somewhere else in the kernel driver. 8349 * 8350 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8351 * GDS to 0 for this ring (me/pipe). 8352 */ 8353 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8354 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8355 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8356 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8357 } 8358 8359 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8360 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8361 amdgpu_ring_write(ring, 8362 #ifdef __BIG_ENDIAN 8363 (2 << 0) | 8364 #endif 8365 lower_32_bits(ib->gpu_addr)); 8366 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8367 amdgpu_ring_write(ring, control); 8368 } 8369 8370 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8371 u64 seq, unsigned int flags) 8372 { 8373 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8374 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8375 8376 /* RELEASE_MEM - flush caches, send int */ 8377 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8378 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8379 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8380 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8381 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8382 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8383 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8384 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8385 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8386 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8387 8388 /* 8389 * the address should be Qword aligned if 64bit write, Dword 8390 * aligned if only send 32bit data low (discard data high) 8391 */ 8392 if (write64bit) 8393 BUG_ON(addr & 0x7); 8394 else 8395 BUG_ON(addr & 0x3); 8396 amdgpu_ring_write(ring, lower_32_bits(addr)); 8397 amdgpu_ring_write(ring, upper_32_bits(addr)); 8398 amdgpu_ring_write(ring, lower_32_bits(seq)); 8399 amdgpu_ring_write(ring, upper_32_bits(seq)); 8400 amdgpu_ring_write(ring, ring->is_mes_queue ? 8401 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 8402 } 8403 8404 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8405 { 8406 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8407 uint32_t seq = ring->fence_drv.sync_seq; 8408 uint64_t addr = ring->fence_drv.gpu_addr; 8409 8410 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8411 upper_32_bits(addr), seq, 0xffffffff, 4); 8412 } 8413 8414 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8415 uint16_t pasid, uint32_t flush_type, 8416 bool all_hub, uint8_t dst_sel) 8417 { 8418 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8419 amdgpu_ring_write(ring, 8420 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8421 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8422 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8423 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8424 } 8425 8426 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8427 unsigned int vmid, uint64_t pd_addr) 8428 { 8429 if (ring->is_mes_queue) 8430 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 8431 else 8432 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8433 8434 /* compute doesn't have PFP */ 8435 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8436 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8437 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8438 amdgpu_ring_write(ring, 0x0); 8439 } 8440 } 8441 8442 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8443 u64 seq, unsigned int flags) 8444 { 8445 struct amdgpu_device *adev = ring->adev; 8446 8447 /* we only allocate 32bit for each seq wb address */ 8448 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8449 8450 /* write fence seq to the "addr" */ 8451 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8452 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8453 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8454 amdgpu_ring_write(ring, lower_32_bits(addr)); 8455 amdgpu_ring_write(ring, upper_32_bits(addr)); 8456 amdgpu_ring_write(ring, lower_32_bits(seq)); 8457 8458 if (flags & AMDGPU_FENCE_FLAG_INT) { 8459 /* set register to trigger INT */ 8460 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8461 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8462 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8463 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8464 amdgpu_ring_write(ring, 0); 8465 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8466 } 8467 } 8468 8469 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8470 { 8471 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8472 amdgpu_ring_write(ring, 0); 8473 } 8474 8475 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8476 uint32_t flags) 8477 { 8478 uint32_t dw2 = 0; 8479 8480 if (ring->adev->gfx.mcbp) 8481 gfx_v10_0_ring_emit_ce_meta(ring, 8482 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8483 8484 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8485 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8486 /* set load_global_config & load_global_uconfig */ 8487 dw2 |= 0x8001; 8488 /* set load_cs_sh_regs */ 8489 dw2 |= 0x01000000; 8490 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8491 dw2 |= 0x10002; 8492 8493 /* set load_ce_ram if preamble presented */ 8494 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8495 dw2 |= 0x10000000; 8496 } else { 8497 /* still load_ce_ram if this is the first time preamble presented 8498 * although there is no context switch happens. 8499 */ 8500 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8501 dw2 |= 0x10000000; 8502 } 8503 8504 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8505 amdgpu_ring_write(ring, dw2); 8506 amdgpu_ring_write(ring, 0); 8507 } 8508 8509 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8510 { 8511 unsigned int ret; 8512 8513 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8514 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8515 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8516 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8517 ret = ring->wptr & ring->buf_mask; 8518 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8519 8520 return ret; 8521 } 8522 8523 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset) 8524 { 8525 unsigned int cur; 8526 8527 BUG_ON(offset > ring->buf_mask); 8528 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8529 8530 cur = (ring->wptr - 1) & ring->buf_mask; 8531 if (likely(cur > offset)) 8532 ring->ring[offset] = cur - offset; 8533 else 8534 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8535 } 8536 8537 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8538 { 8539 int i, r = 0; 8540 struct amdgpu_device *adev = ring->adev; 8541 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8542 struct amdgpu_ring *kiq_ring = &kiq->ring; 8543 unsigned long flags; 8544 8545 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8546 return -EINVAL; 8547 8548 spin_lock_irqsave(&kiq->ring_lock, flags); 8549 8550 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8551 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8552 return -ENOMEM; 8553 } 8554 8555 /* assert preemption condition */ 8556 amdgpu_ring_set_preempt_cond_exec(ring, false); 8557 8558 /* assert IB preemption, emit the trailing fence */ 8559 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8560 ring->trail_fence_gpu_addr, 8561 ++ring->trail_seq); 8562 amdgpu_ring_commit(kiq_ring); 8563 8564 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8565 8566 /* poll the trailing fence */ 8567 for (i = 0; i < adev->usec_timeout; i++) { 8568 if (ring->trail_seq == 8569 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8570 break; 8571 udelay(1); 8572 } 8573 8574 if (i >= adev->usec_timeout) { 8575 r = -EINVAL; 8576 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8577 } 8578 8579 /* deassert preemption condition */ 8580 amdgpu_ring_set_preempt_cond_exec(ring, true); 8581 return r; 8582 } 8583 8584 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8585 { 8586 struct amdgpu_device *adev = ring->adev; 8587 struct v10_ce_ib_state ce_payload = {0}; 8588 uint64_t offset, ce_payload_gpu_addr; 8589 void *ce_payload_cpu_addr; 8590 int cnt; 8591 8592 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8593 8594 if (ring->is_mes_queue) { 8595 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8596 gfx[0].gfx_meta_data) + 8597 offsetof(struct v10_gfx_meta_data, ce_payload); 8598 ce_payload_gpu_addr = 8599 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8600 ce_payload_cpu_addr = 8601 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8602 } else { 8603 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8604 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8605 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8606 } 8607 8608 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8609 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8610 WRITE_DATA_DST_SEL(8) | 8611 WR_CONFIRM) | 8612 WRITE_DATA_CACHE_POLICY(0)); 8613 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8614 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8615 8616 if (resume) 8617 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8618 sizeof(ce_payload) >> 2); 8619 else 8620 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8621 sizeof(ce_payload) >> 2); 8622 } 8623 8624 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8625 { 8626 struct amdgpu_device *adev = ring->adev; 8627 struct v10_de_ib_state de_payload = {0}; 8628 uint64_t offset, gds_addr, de_payload_gpu_addr; 8629 void *de_payload_cpu_addr; 8630 int cnt; 8631 8632 if (ring->is_mes_queue) { 8633 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8634 gfx[0].gfx_meta_data) + 8635 offsetof(struct v10_gfx_meta_data, de_payload); 8636 de_payload_gpu_addr = 8637 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8638 de_payload_cpu_addr = 8639 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8640 8641 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8642 gfx[0].gds_backup) + 8643 offsetof(struct v10_gfx_meta_data, de_payload); 8644 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8645 } else { 8646 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8647 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8648 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8649 8650 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8651 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8652 PAGE_SIZE); 8653 } 8654 8655 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8656 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8657 8658 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8659 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8660 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8661 WRITE_DATA_DST_SEL(8) | 8662 WR_CONFIRM) | 8663 WRITE_DATA_CACHE_POLICY(0)); 8664 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8665 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8666 8667 if (resume) 8668 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8669 sizeof(de_payload) >> 2); 8670 else 8671 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8672 sizeof(de_payload) >> 2); 8673 } 8674 8675 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8676 bool secure) 8677 { 8678 uint32_t v = secure ? FRAME_TMZ : 0; 8679 8680 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8681 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8682 } 8683 8684 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8685 uint32_t reg_val_offs) 8686 { 8687 struct amdgpu_device *adev = ring->adev; 8688 8689 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8690 amdgpu_ring_write(ring, 0 | /* src: register*/ 8691 (5 << 8) | /* dst: memory */ 8692 (1 << 20)); /* write confirm */ 8693 amdgpu_ring_write(ring, reg); 8694 amdgpu_ring_write(ring, 0); 8695 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8696 reg_val_offs * 4)); 8697 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8698 reg_val_offs * 4)); 8699 } 8700 8701 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8702 uint32_t val) 8703 { 8704 uint32_t cmd = 0; 8705 8706 switch (ring->funcs->type) { 8707 case AMDGPU_RING_TYPE_GFX: 8708 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8709 break; 8710 case AMDGPU_RING_TYPE_KIQ: 8711 cmd = (1 << 16); /* no inc addr */ 8712 break; 8713 default: 8714 cmd = WR_CONFIRM; 8715 break; 8716 } 8717 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8718 amdgpu_ring_write(ring, cmd); 8719 amdgpu_ring_write(ring, reg); 8720 amdgpu_ring_write(ring, 0); 8721 amdgpu_ring_write(ring, val); 8722 } 8723 8724 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8725 uint32_t val, uint32_t mask) 8726 { 8727 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8728 } 8729 8730 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8731 uint32_t reg0, uint32_t reg1, 8732 uint32_t ref, uint32_t mask) 8733 { 8734 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8735 struct amdgpu_device *adev = ring->adev; 8736 bool fw_version_ok = false; 8737 8738 fw_version_ok = adev->gfx.cp_fw_write_wait; 8739 8740 if (fw_version_ok) 8741 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8742 ref, mask, 0x20); 8743 else 8744 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8745 ref, mask); 8746 } 8747 8748 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8749 unsigned int vmid) 8750 { 8751 struct amdgpu_device *adev = ring->adev; 8752 uint32_t value = 0; 8753 8754 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8755 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8756 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8757 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8758 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8759 } 8760 8761 static void 8762 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8763 uint32_t me, uint32_t pipe, 8764 enum amdgpu_interrupt_state state) 8765 { 8766 uint32_t cp_int_cntl, cp_int_cntl_reg; 8767 8768 if (!me) { 8769 switch (pipe) { 8770 case 0: 8771 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8772 break; 8773 case 1: 8774 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8775 break; 8776 default: 8777 DRM_DEBUG("invalid pipe %d\n", pipe); 8778 return; 8779 } 8780 } else { 8781 DRM_DEBUG("invalid me %d\n", me); 8782 return; 8783 } 8784 8785 switch (state) { 8786 case AMDGPU_IRQ_STATE_DISABLE: 8787 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8788 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8789 TIME_STAMP_INT_ENABLE, 0); 8790 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8791 break; 8792 case AMDGPU_IRQ_STATE_ENABLE: 8793 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8794 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8795 TIME_STAMP_INT_ENABLE, 1); 8796 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8797 break; 8798 default: 8799 break; 8800 } 8801 } 8802 8803 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8804 int me, int pipe, 8805 enum amdgpu_interrupt_state state) 8806 { 8807 u32 mec_int_cntl, mec_int_cntl_reg; 8808 8809 /* 8810 * amdgpu controls only the first MEC. That's why this function only 8811 * handles the setting of interrupts for this specific MEC. All other 8812 * pipes' interrupts are set by amdkfd. 8813 */ 8814 8815 if (me == 1) { 8816 switch (pipe) { 8817 case 0: 8818 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8819 break; 8820 case 1: 8821 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8822 break; 8823 case 2: 8824 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8825 break; 8826 case 3: 8827 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8828 break; 8829 default: 8830 DRM_DEBUG("invalid pipe %d\n", pipe); 8831 return; 8832 } 8833 } else { 8834 DRM_DEBUG("invalid me %d\n", me); 8835 return; 8836 } 8837 8838 switch (state) { 8839 case AMDGPU_IRQ_STATE_DISABLE: 8840 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8841 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8842 TIME_STAMP_INT_ENABLE, 0); 8843 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8844 break; 8845 case AMDGPU_IRQ_STATE_ENABLE: 8846 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8847 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8848 TIME_STAMP_INT_ENABLE, 1); 8849 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8850 break; 8851 default: 8852 break; 8853 } 8854 } 8855 8856 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8857 struct amdgpu_irq_src *src, 8858 unsigned int type, 8859 enum amdgpu_interrupt_state state) 8860 { 8861 switch (type) { 8862 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8863 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8864 break; 8865 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8866 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8867 break; 8868 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8869 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8870 break; 8871 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8872 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8873 break; 8874 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8875 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8876 break; 8877 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8878 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8879 break; 8880 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8881 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8882 break; 8883 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8884 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8885 break; 8886 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8887 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8888 break; 8889 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8890 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8891 break; 8892 default: 8893 break; 8894 } 8895 return 0; 8896 } 8897 8898 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8899 struct amdgpu_irq_src *source, 8900 struct amdgpu_iv_entry *entry) 8901 { 8902 int i; 8903 u8 me_id, pipe_id, queue_id; 8904 struct amdgpu_ring *ring; 8905 uint32_t mes_queue_id = entry->src_data[0]; 8906 8907 DRM_DEBUG("IH: CP EOP\n"); 8908 8909 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 8910 struct amdgpu_mes_queue *queue; 8911 8912 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 8913 8914 spin_lock(&adev->mes.queue_id_lock); 8915 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 8916 if (queue) { 8917 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 8918 amdgpu_fence_process(queue->ring); 8919 } 8920 spin_unlock(&adev->mes.queue_id_lock); 8921 } else { 8922 me_id = (entry->ring_id & 0x0c) >> 2; 8923 pipe_id = (entry->ring_id & 0x03) >> 0; 8924 queue_id = (entry->ring_id & 0x70) >> 4; 8925 8926 switch (me_id) { 8927 case 0: 8928 if (pipe_id == 0) 8929 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8930 else 8931 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8932 break; 8933 case 1: 8934 case 2: 8935 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8936 ring = &adev->gfx.compute_ring[i]; 8937 /* Per-queue interrupt is supported for MEC starting from VI. 8938 * The interrupt can only be enabled/disabled per pipe instead 8939 * of per queue. 8940 */ 8941 if ((ring->me == me_id) && 8942 (ring->pipe == pipe_id) && 8943 (ring->queue == queue_id)) 8944 amdgpu_fence_process(ring); 8945 } 8946 break; 8947 } 8948 } 8949 8950 return 0; 8951 } 8952 8953 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8954 struct amdgpu_irq_src *source, 8955 unsigned int type, 8956 enum amdgpu_interrupt_state state) 8957 { 8958 switch (state) { 8959 case AMDGPU_IRQ_STATE_DISABLE: 8960 case AMDGPU_IRQ_STATE_ENABLE: 8961 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8962 PRIV_REG_INT_ENABLE, 8963 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8964 break; 8965 default: 8966 break; 8967 } 8968 8969 return 0; 8970 } 8971 8972 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8973 struct amdgpu_irq_src *source, 8974 unsigned int type, 8975 enum amdgpu_interrupt_state state) 8976 { 8977 switch (state) { 8978 case AMDGPU_IRQ_STATE_DISABLE: 8979 case AMDGPU_IRQ_STATE_ENABLE: 8980 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8981 PRIV_INSTR_INT_ENABLE, 8982 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8983 break; 8984 default: 8985 break; 8986 } 8987 8988 return 0; 8989 } 8990 8991 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8992 struct amdgpu_iv_entry *entry) 8993 { 8994 u8 me_id, pipe_id, queue_id; 8995 struct amdgpu_ring *ring; 8996 int i; 8997 8998 me_id = (entry->ring_id & 0x0c) >> 2; 8999 pipe_id = (entry->ring_id & 0x03) >> 0; 9000 queue_id = (entry->ring_id & 0x70) >> 4; 9001 9002 switch (me_id) { 9003 case 0: 9004 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9005 ring = &adev->gfx.gfx_ring[i]; 9006 /* we only enabled 1 gfx queue per pipe for now */ 9007 if (ring->me == me_id && ring->pipe == pipe_id) 9008 drm_sched_fault(&ring->sched); 9009 } 9010 break; 9011 case 1: 9012 case 2: 9013 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9014 ring = &adev->gfx.compute_ring[i]; 9015 if (ring->me == me_id && ring->pipe == pipe_id && 9016 ring->queue == queue_id) 9017 drm_sched_fault(&ring->sched); 9018 } 9019 break; 9020 default: 9021 BUG(); 9022 } 9023 } 9024 9025 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9026 struct amdgpu_irq_src *source, 9027 struct amdgpu_iv_entry *entry) 9028 { 9029 DRM_ERROR("Illegal register access in command stream\n"); 9030 gfx_v10_0_handle_priv_fault(adev, entry); 9031 return 0; 9032 } 9033 9034 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9035 struct amdgpu_irq_src *source, 9036 struct amdgpu_iv_entry *entry) 9037 { 9038 DRM_ERROR("Illegal instruction in command stream\n"); 9039 gfx_v10_0_handle_priv_fault(adev, entry); 9040 return 0; 9041 } 9042 9043 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9044 struct amdgpu_irq_src *src, 9045 unsigned int type, 9046 enum amdgpu_interrupt_state state) 9047 { 9048 uint32_t tmp, target; 9049 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9050 9051 if (ring->me == 1) 9052 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9053 else 9054 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9055 target += ring->pipe; 9056 9057 switch (type) { 9058 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9059 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9060 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9061 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9062 GENERIC2_INT_ENABLE, 0); 9063 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9064 9065 tmp = RREG32_SOC15_IP(GC, target); 9066 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9067 GENERIC2_INT_ENABLE, 0); 9068 WREG32_SOC15_IP(GC, target, tmp); 9069 } else { 9070 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9071 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9072 GENERIC2_INT_ENABLE, 1); 9073 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9074 9075 tmp = RREG32_SOC15_IP(GC, target); 9076 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9077 GENERIC2_INT_ENABLE, 1); 9078 WREG32_SOC15_IP(GC, target, tmp); 9079 } 9080 break; 9081 default: 9082 BUG(); /* kiq only support GENERIC2_INT now */ 9083 break; 9084 } 9085 return 0; 9086 } 9087 9088 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9089 struct amdgpu_irq_src *source, 9090 struct amdgpu_iv_entry *entry) 9091 { 9092 u8 me_id, pipe_id, queue_id; 9093 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9094 9095 me_id = (entry->ring_id & 0x0c) >> 2; 9096 pipe_id = (entry->ring_id & 0x03) >> 0; 9097 queue_id = (entry->ring_id & 0x70) >> 4; 9098 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9099 me_id, pipe_id, queue_id); 9100 9101 amdgpu_fence_process(ring); 9102 return 0; 9103 } 9104 9105 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9106 { 9107 const unsigned int gcr_cntl = 9108 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9109 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9110 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9111 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9112 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9113 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9114 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9115 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9116 9117 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9118 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9119 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9120 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9121 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9122 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9123 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9124 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9125 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9126 } 9127 9128 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9129 .name = "gfx_v10_0", 9130 .early_init = gfx_v10_0_early_init, 9131 .late_init = gfx_v10_0_late_init, 9132 .sw_init = gfx_v10_0_sw_init, 9133 .sw_fini = gfx_v10_0_sw_fini, 9134 .hw_init = gfx_v10_0_hw_init, 9135 .hw_fini = gfx_v10_0_hw_fini, 9136 .suspend = gfx_v10_0_suspend, 9137 .resume = gfx_v10_0_resume, 9138 .is_idle = gfx_v10_0_is_idle, 9139 .wait_for_idle = gfx_v10_0_wait_for_idle, 9140 .soft_reset = gfx_v10_0_soft_reset, 9141 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9142 .set_powergating_state = gfx_v10_0_set_powergating_state, 9143 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9144 }; 9145 9146 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9147 .type = AMDGPU_RING_TYPE_GFX, 9148 .align_mask = 0xff, 9149 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9150 .support_64bit_ptrs = true, 9151 .secure_submission_supported = true, 9152 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9153 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9154 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9155 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9156 5 + /* COND_EXEC */ 9157 7 + /* PIPELINE_SYNC */ 9158 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9159 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9160 2 + /* VM_FLUSH */ 9161 8 + /* FENCE for VM_FLUSH */ 9162 20 + /* GDS switch */ 9163 4 + /* double SWITCH_BUFFER, 9164 * the first COND_EXEC jump to the place 9165 * just prior to this double SWITCH_BUFFER 9166 */ 9167 5 + /* COND_EXEC */ 9168 7 + /* HDP_flush */ 9169 4 + /* VGT_flush */ 9170 14 + /* CE_META */ 9171 31 + /* DE_META */ 9172 3 + /* CNTX_CTRL */ 9173 5 + /* HDP_INVL */ 9174 8 + 8 + /* FENCE x2 */ 9175 2 + /* SWITCH_BUFFER */ 9176 8, /* gfx_v10_0_emit_mem_sync */ 9177 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9178 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9179 .emit_fence = gfx_v10_0_ring_emit_fence, 9180 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9181 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9182 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9183 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9184 .test_ring = gfx_v10_0_ring_test_ring, 9185 .test_ib = gfx_v10_0_ring_test_ib, 9186 .insert_nop = amdgpu_ring_insert_nop, 9187 .pad_ib = amdgpu_ring_generic_pad_ib, 9188 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9189 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9190 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9191 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9192 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9193 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9194 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9195 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9196 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9197 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9198 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9199 }; 9200 9201 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9202 .type = AMDGPU_RING_TYPE_COMPUTE, 9203 .align_mask = 0xff, 9204 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9205 .support_64bit_ptrs = true, 9206 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9207 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9208 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9209 .emit_frame_size = 9210 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9211 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9212 5 + /* hdp invalidate */ 9213 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9214 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9215 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9216 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9217 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9218 8, /* gfx_v10_0_emit_mem_sync */ 9219 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9220 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9221 .emit_fence = gfx_v10_0_ring_emit_fence, 9222 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9223 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9224 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9225 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9226 .test_ring = gfx_v10_0_ring_test_ring, 9227 .test_ib = gfx_v10_0_ring_test_ib, 9228 .insert_nop = amdgpu_ring_insert_nop, 9229 .pad_ib = amdgpu_ring_generic_pad_ib, 9230 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9231 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9232 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9233 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9234 }; 9235 9236 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9237 .type = AMDGPU_RING_TYPE_KIQ, 9238 .align_mask = 0xff, 9239 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9240 .support_64bit_ptrs = true, 9241 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9242 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9243 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9244 .emit_frame_size = 9245 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9246 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9247 5 + /*hdp invalidate */ 9248 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9249 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9250 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9251 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9252 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9253 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9254 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9255 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9256 .test_ring = gfx_v10_0_ring_test_ring, 9257 .test_ib = gfx_v10_0_ring_test_ib, 9258 .insert_nop = amdgpu_ring_insert_nop, 9259 .pad_ib = amdgpu_ring_generic_pad_ib, 9260 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9261 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9262 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9263 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9264 }; 9265 9266 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9267 { 9268 int i; 9269 9270 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9271 9272 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9273 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9274 9275 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9276 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9277 } 9278 9279 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9280 .set = gfx_v10_0_set_eop_interrupt_state, 9281 .process = gfx_v10_0_eop_irq, 9282 }; 9283 9284 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9285 .set = gfx_v10_0_set_priv_reg_fault_state, 9286 .process = gfx_v10_0_priv_reg_irq, 9287 }; 9288 9289 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9290 .set = gfx_v10_0_set_priv_inst_fault_state, 9291 .process = gfx_v10_0_priv_inst_irq, 9292 }; 9293 9294 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9295 .set = gfx_v10_0_kiq_set_interrupt_state, 9296 .process = gfx_v10_0_kiq_irq, 9297 }; 9298 9299 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9300 { 9301 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9302 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9303 9304 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9305 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9306 9307 adev->gfx.priv_reg_irq.num_types = 1; 9308 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9309 9310 adev->gfx.priv_inst_irq.num_types = 1; 9311 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9312 } 9313 9314 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9315 { 9316 switch (adev->ip_versions[GC_HWIP][0]) { 9317 case IP_VERSION(10, 1, 10): 9318 case IP_VERSION(10, 1, 1): 9319 case IP_VERSION(10, 1, 3): 9320 case IP_VERSION(10, 1, 4): 9321 case IP_VERSION(10, 3, 2): 9322 case IP_VERSION(10, 3, 1): 9323 case IP_VERSION(10, 3, 4): 9324 case IP_VERSION(10, 3, 5): 9325 case IP_VERSION(10, 3, 6): 9326 case IP_VERSION(10, 3, 3): 9327 case IP_VERSION(10, 3, 7): 9328 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9329 break; 9330 case IP_VERSION(10, 1, 2): 9331 case IP_VERSION(10, 3, 0): 9332 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9333 break; 9334 default: 9335 break; 9336 } 9337 } 9338 9339 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9340 { 9341 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 9342 adev->gfx.config.max_sh_per_se * 9343 adev->gfx.config.max_shader_engines; 9344 9345 adev->gds.gds_size = 0x10000; 9346 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9347 adev->gds.gws_size = 64; 9348 adev->gds.oa_size = 16; 9349 } 9350 9351 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9352 { 9353 /* set gfx eng mqd */ 9354 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9355 sizeof(struct v10_gfx_mqd); 9356 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9357 gfx_v10_0_gfx_mqd_init; 9358 /* set compute eng mqd */ 9359 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9360 sizeof(struct v10_compute_mqd); 9361 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9362 gfx_v10_0_compute_mqd_init; 9363 } 9364 9365 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9366 u32 bitmap) 9367 { 9368 u32 data; 9369 9370 if (!bitmap) 9371 return; 9372 9373 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9374 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9375 9376 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9377 } 9378 9379 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9380 { 9381 u32 disabled_mask = 9382 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9383 u32 efuse_setting = 0; 9384 u32 vbios_setting = 0; 9385 9386 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9387 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9388 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9389 9390 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9391 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9392 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9393 9394 disabled_mask |= efuse_setting | vbios_setting; 9395 9396 return (~disabled_mask); 9397 } 9398 9399 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9400 { 9401 u32 wgp_idx, wgp_active_bitmap; 9402 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9403 9404 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9405 cu_active_bitmap = 0; 9406 9407 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9408 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9409 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9410 if (wgp_active_bitmap & (1 << wgp_idx)) 9411 cu_active_bitmap |= cu_bitmap_per_wgp; 9412 } 9413 9414 return cu_active_bitmap; 9415 } 9416 9417 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9418 struct amdgpu_cu_info *cu_info) 9419 { 9420 int i, j, k, counter, active_cu_number = 0; 9421 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9422 unsigned int disable_masks[4 * 2]; 9423 9424 if (!adev || !cu_info) 9425 return -EINVAL; 9426 9427 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9428 9429 mutex_lock(&adev->grbm_idx_mutex); 9430 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9431 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9432 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9433 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 9434 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 9435 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) || 9436 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) && 9437 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9438 continue; 9439 mask = 1; 9440 ao_bitmap = 0; 9441 counter = 0; 9442 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 9443 if (i < 4 && j < 2) 9444 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9445 adev, disable_masks[i * 2 + j]); 9446 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9447 cu_info->bitmap[0][i][j] = bitmap; 9448 9449 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9450 if (bitmap & mask) { 9451 if (counter < adev->gfx.config.max_cu_per_sh) 9452 ao_bitmap |= mask; 9453 counter++; 9454 } 9455 mask <<= 1; 9456 } 9457 active_cu_number += counter; 9458 if (i < 2 && j < 2) 9459 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9460 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9461 } 9462 } 9463 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 9464 mutex_unlock(&adev->grbm_idx_mutex); 9465 9466 cu_info->number = active_cu_number; 9467 cu_info->ao_cu_mask = ao_cu_mask; 9468 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9469 9470 return 0; 9471 } 9472 9473 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9474 { 9475 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9476 9477 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9478 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9479 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9480 9481 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9482 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9483 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9484 9485 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9486 adev->gfx.config.max_shader_engines); 9487 disabled_sa = efuse_setting | vbios_setting; 9488 disabled_sa &= max_sa_mask; 9489 9490 return disabled_sa; 9491 } 9492 9493 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9494 { 9495 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9496 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9497 9498 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9499 9500 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9501 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9502 max_shader_engines = adev->gfx.config.max_shader_engines; 9503 9504 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9505 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9506 disabled_sa_per_se &= max_sa_per_se_mask; 9507 if (disabled_sa_per_se == max_sa_per_se_mask) { 9508 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9509 break; 9510 } 9511 } 9512 } 9513 9514 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9515 { 9516 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9517 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9518 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9519 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9520 9521 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9522 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9523 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9524 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9525 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9526 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9527 9528 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9529 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9530 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9531 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9532 9533 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9534 9535 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9536 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9537 } 9538 9539 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 9540 .type = AMD_IP_BLOCK_TYPE_GFX, 9541 .major = 10, 9542 .minor = 0, 9543 .rev = 0, 9544 .funcs = &gfx_v10_0_ip_funcs, 9545 }; 9546