1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "smuio/smuio_11_0_0_offset.h" 39 #include "smuio/smuio_11_0_0_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "soc15_common.h" 47 #include "clearstate_gfx10.h" 48 #include "v10_structs.h" 49 #include "gfx_v10_0.h" 50 #include "nbio_v2_3.h" 51 52 /** 53 * Navi10 has two graphic rings to share each graphic pipe. 54 * 1. Primary ring 55 * 2. Async ring 56 */ 57 #define GFX10_NUM_GFX_RINGS_NV1X 1 58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 59 #define GFX10_MEC_HPD_SIZE 2048 60 61 #define F32_CE_PROGRAM_RAM_SIZE 65536 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 64 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 70 71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 73 74 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 76 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 101 102 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 103 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 104 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 105 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 106 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 107 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 108 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 109 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 110 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 111 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 112 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 113 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 114 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 115 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 116 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 117 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 118 119 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 120 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 121 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 122 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 123 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 124 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 125 #define mmCP_HYP_CE_UCODE_DATA 0x5819 126 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 127 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 128 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 129 #define mmCP_HYP_ME_UCODE_DATA 0x5817 130 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 131 132 #define mmCPG_PSP_DEBUG 0x5c10 133 #define mmCPG_PSP_DEBUG_BASE_IDX 1 134 #define mmCPC_PSP_DEBUG 0x5c11 135 #define mmCPC_PSP_DEBUG_BASE_IDX 1 136 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 137 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 138 139 //CC_GC_SA_UNIT_DISABLE 140 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 141 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 142 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 143 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 144 //GC_USER_SA_UNIT_DISABLE 145 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 146 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 147 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 148 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 149 //PA_SC_ENHANCE_3 150 #define mmPA_SC_ENHANCE_3 0x1085 151 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 152 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 153 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 154 155 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 156 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 157 158 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 159 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 160 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 161 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 162 163 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 164 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 165 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 166 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 167 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 168 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 169 170 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 171 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 172 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 173 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 174 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 175 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 176 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 177 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 178 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 179 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 180 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 181 182 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 183 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 184 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 185 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 186 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 187 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 188 189 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 190 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 191 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 192 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 193 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 194 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 195 196 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 197 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 198 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 199 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 200 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 201 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 202 203 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 204 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 205 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 206 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 207 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 208 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 209 210 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 211 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 212 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 213 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 214 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 215 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 216 217 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 218 { 219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 259 }; 260 261 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 262 { 263 /* Pending on emulation bring up */ 264 }; 265 266 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 267 { 268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1320 }; 1321 1322 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1323 { 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1362 }; 1363 1364 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1365 { 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 1406 }; 1407 1408 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 1409 { 1410 static void *scratch_reg0; 1411 static void *scratch_reg1; 1412 static void *spare_int; 1413 uint32_t i = 0; 1414 uint32_t retries = 50000; 1415 1416 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 1417 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 1418 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 1419 1420 if (amdgpu_sriov_runtime(adev)) { 1421 pr_err("shouldn't call rlcg write register during runtime\n"); 1422 return; 1423 } 1424 1425 writel(v, scratch_reg0); 1426 writel(offset | 0x80000000, scratch_reg1); 1427 writel(1, spare_int); 1428 for (i = 0; i < retries; i++) { 1429 u32 tmp; 1430 1431 tmp = readl(scratch_reg1); 1432 if (!(tmp & 0x80000000)) 1433 break; 1434 1435 udelay(10); 1436 } 1437 1438 if (i >= retries) 1439 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 1440 } 1441 1442 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1443 { 1444 /* Pending on emulation bring up */ 1445 }; 1446 1447 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1448 { 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2069 }; 2070 2071 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2072 { 2073 /* Pending on emulation bring up */ 2074 }; 2075 2076 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2077 { 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3130 }; 3131 3132 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3133 { 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3176 }; 3177 3178 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3179 { 3180 /* Pending on emulation bring up */ 3181 }; 3182 3183 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3184 { 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3226 3227 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3229 }; 3230 3231 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3232 { 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3256 3257 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3259 }; 3260 3261 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3262 { 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3298 }; 3299 3300 #define DEFAULT_SH_MEM_CONFIG \ 3301 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3302 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3303 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3304 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3305 3306 3307 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3308 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3309 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3310 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3311 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3312 struct amdgpu_cu_info *cu_info); 3313 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3314 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3315 u32 sh_num, u32 instance); 3316 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3317 3318 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3319 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3320 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3321 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3322 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3323 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3324 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3325 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3326 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3327 3328 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3329 { 3330 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3331 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3332 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3333 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3334 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3335 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3336 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3337 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3338 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3339 } 3340 3341 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3342 struct amdgpu_ring *ring) 3343 { 3344 struct amdgpu_device *adev = kiq_ring->adev; 3345 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3346 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3347 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3348 3349 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3350 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3351 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3352 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3353 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3354 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3355 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3356 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3357 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3358 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3359 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3360 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3361 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3362 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3363 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3364 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3365 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3366 } 3367 3368 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3369 struct amdgpu_ring *ring, 3370 enum amdgpu_unmap_queues_action action, 3371 u64 gpu_addr, u64 seq) 3372 { 3373 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3374 3375 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3376 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3377 PACKET3_UNMAP_QUEUES_ACTION(action) | 3378 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3379 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3380 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3381 amdgpu_ring_write(kiq_ring, 3382 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3383 3384 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3385 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3386 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3387 amdgpu_ring_write(kiq_ring, seq); 3388 } else { 3389 amdgpu_ring_write(kiq_ring, 0); 3390 amdgpu_ring_write(kiq_ring, 0); 3391 amdgpu_ring_write(kiq_ring, 0); 3392 } 3393 } 3394 3395 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3396 struct amdgpu_ring *ring, 3397 u64 addr, 3398 u64 seq) 3399 { 3400 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3401 3402 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3403 amdgpu_ring_write(kiq_ring, 3404 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3405 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3406 PACKET3_QUERY_STATUS_COMMAND(2)); 3407 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3408 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3409 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3410 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3411 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3412 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3413 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3414 } 3415 3416 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3417 uint16_t pasid, uint32_t flush_type, 3418 bool all_hub) 3419 { 3420 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3421 amdgpu_ring_write(kiq_ring, 3422 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3423 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3424 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3425 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3426 } 3427 3428 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3429 .kiq_set_resources = gfx10_kiq_set_resources, 3430 .kiq_map_queues = gfx10_kiq_map_queues, 3431 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3432 .kiq_query_status = gfx10_kiq_query_status, 3433 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3434 .set_resources_size = 8, 3435 .map_queues_size = 7, 3436 .unmap_queues_size = 6, 3437 .query_status_size = 7, 3438 .invalidate_tlbs_size = 2, 3439 }; 3440 3441 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3442 { 3443 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3444 } 3445 3446 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3447 { 3448 switch (adev->asic_type) { 3449 case CHIP_NAVI10: 3450 soc15_program_register_sequence(adev, 3451 golden_settings_gc_rlc_spm_10_0_nv10, 3452 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3453 break; 3454 case CHIP_NAVI14: 3455 soc15_program_register_sequence(adev, 3456 golden_settings_gc_rlc_spm_10_1_nv14, 3457 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3458 break; 3459 case CHIP_NAVI12: 3460 soc15_program_register_sequence(adev, 3461 golden_settings_gc_rlc_spm_10_1_2_nv12, 3462 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3463 break; 3464 default: 3465 break; 3466 } 3467 } 3468 3469 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3470 { 3471 switch (adev->asic_type) { 3472 case CHIP_NAVI10: 3473 soc15_program_register_sequence(adev, 3474 golden_settings_gc_10_1, 3475 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3476 soc15_program_register_sequence(adev, 3477 golden_settings_gc_10_0_nv10, 3478 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3479 break; 3480 case CHIP_NAVI14: 3481 soc15_program_register_sequence(adev, 3482 golden_settings_gc_10_1_1, 3483 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3484 soc15_program_register_sequence(adev, 3485 golden_settings_gc_10_1_nv14, 3486 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3487 break; 3488 case CHIP_NAVI12: 3489 soc15_program_register_sequence(adev, 3490 golden_settings_gc_10_1_2, 3491 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3492 soc15_program_register_sequence(adev, 3493 golden_settings_gc_10_1_2_nv12, 3494 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3495 break; 3496 case CHIP_SIENNA_CICHLID: 3497 soc15_program_register_sequence(adev, 3498 golden_settings_gc_10_3, 3499 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3500 soc15_program_register_sequence(adev, 3501 golden_settings_gc_10_3_sienna_cichlid, 3502 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3503 break; 3504 case CHIP_NAVY_FLOUNDER: 3505 soc15_program_register_sequence(adev, 3506 golden_settings_gc_10_3_2, 3507 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3508 break; 3509 case CHIP_VANGOGH: 3510 soc15_program_register_sequence(adev, 3511 golden_settings_gc_10_3_vangogh, 3512 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3513 break; 3514 case CHIP_DIMGREY_CAVEFISH: 3515 soc15_program_register_sequence(adev, 3516 golden_settings_gc_10_3_4, 3517 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3518 break; 3519 default: 3520 break; 3521 } 3522 gfx_v10_0_init_spm_golden_registers(adev); 3523 } 3524 3525 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3526 { 3527 adev->gfx.scratch.num_reg = 8; 3528 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3529 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3530 } 3531 3532 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3533 bool wc, uint32_t reg, uint32_t val) 3534 { 3535 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3536 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3537 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3538 amdgpu_ring_write(ring, reg); 3539 amdgpu_ring_write(ring, 0); 3540 amdgpu_ring_write(ring, val); 3541 } 3542 3543 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3544 int mem_space, int opt, uint32_t addr0, 3545 uint32_t addr1, uint32_t ref, uint32_t mask, 3546 uint32_t inv) 3547 { 3548 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3549 amdgpu_ring_write(ring, 3550 /* memory (1) or register (0) */ 3551 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3552 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3553 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3554 WAIT_REG_MEM_ENGINE(eng_sel))); 3555 3556 if (mem_space) 3557 BUG_ON(addr0 & 0x3); /* Dword align */ 3558 amdgpu_ring_write(ring, addr0); 3559 amdgpu_ring_write(ring, addr1); 3560 amdgpu_ring_write(ring, ref); 3561 amdgpu_ring_write(ring, mask); 3562 amdgpu_ring_write(ring, inv); /* poll interval */ 3563 } 3564 3565 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3566 { 3567 struct amdgpu_device *adev = ring->adev; 3568 uint32_t scratch; 3569 uint32_t tmp = 0; 3570 unsigned i; 3571 int r; 3572 3573 r = amdgpu_gfx_scratch_get(adev, &scratch); 3574 if (r) { 3575 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3576 return r; 3577 } 3578 3579 WREG32(scratch, 0xCAFEDEAD); 3580 3581 r = amdgpu_ring_alloc(ring, 3); 3582 if (r) { 3583 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3584 ring->idx, r); 3585 amdgpu_gfx_scratch_free(adev, scratch); 3586 return r; 3587 } 3588 3589 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3590 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3591 amdgpu_ring_write(ring, 0xDEADBEEF); 3592 amdgpu_ring_commit(ring); 3593 3594 for (i = 0; i < adev->usec_timeout; i++) { 3595 tmp = RREG32(scratch); 3596 if (tmp == 0xDEADBEEF) 3597 break; 3598 if (amdgpu_emu_mode == 1) 3599 msleep(1); 3600 else 3601 udelay(1); 3602 } 3603 3604 if (i >= adev->usec_timeout) 3605 r = -ETIMEDOUT; 3606 3607 amdgpu_gfx_scratch_free(adev, scratch); 3608 3609 return r; 3610 } 3611 3612 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3613 { 3614 struct amdgpu_device *adev = ring->adev; 3615 struct amdgpu_ib ib; 3616 struct dma_fence *f = NULL; 3617 unsigned index; 3618 uint64_t gpu_addr; 3619 uint32_t tmp; 3620 long r; 3621 3622 r = amdgpu_device_wb_get(adev, &index); 3623 if (r) 3624 return r; 3625 3626 gpu_addr = adev->wb.gpu_addr + (index * 4); 3627 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3628 memset(&ib, 0, sizeof(ib)); 3629 r = amdgpu_ib_get(adev, NULL, 16, 3630 AMDGPU_IB_POOL_DIRECT, &ib); 3631 if (r) 3632 goto err1; 3633 3634 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3635 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3636 ib.ptr[2] = lower_32_bits(gpu_addr); 3637 ib.ptr[3] = upper_32_bits(gpu_addr); 3638 ib.ptr[4] = 0xDEADBEEF; 3639 ib.length_dw = 5; 3640 3641 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3642 if (r) 3643 goto err2; 3644 3645 r = dma_fence_wait_timeout(f, false, timeout); 3646 if (r == 0) { 3647 r = -ETIMEDOUT; 3648 goto err2; 3649 } else if (r < 0) { 3650 goto err2; 3651 } 3652 3653 tmp = adev->wb.wb[index]; 3654 if (tmp == 0xDEADBEEF) 3655 r = 0; 3656 else 3657 r = -EINVAL; 3658 err2: 3659 amdgpu_ib_free(adev, &ib, NULL); 3660 dma_fence_put(f); 3661 err1: 3662 amdgpu_device_wb_free(adev, index); 3663 return r; 3664 } 3665 3666 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3667 { 3668 release_firmware(adev->gfx.pfp_fw); 3669 adev->gfx.pfp_fw = NULL; 3670 release_firmware(adev->gfx.me_fw); 3671 adev->gfx.me_fw = NULL; 3672 release_firmware(adev->gfx.ce_fw); 3673 adev->gfx.ce_fw = NULL; 3674 release_firmware(adev->gfx.rlc_fw); 3675 adev->gfx.rlc_fw = NULL; 3676 release_firmware(adev->gfx.mec_fw); 3677 adev->gfx.mec_fw = NULL; 3678 release_firmware(adev->gfx.mec2_fw); 3679 adev->gfx.mec2_fw = NULL; 3680 3681 kfree(adev->gfx.rlc.register_list_format); 3682 } 3683 3684 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3685 { 3686 adev->gfx.cp_fw_write_wait = false; 3687 3688 switch (adev->asic_type) { 3689 case CHIP_NAVI10: 3690 case CHIP_NAVI12: 3691 case CHIP_NAVI14: 3692 if ((adev->gfx.me_fw_version >= 0x00000046) && 3693 (adev->gfx.me_feature_version >= 27) && 3694 (adev->gfx.pfp_fw_version >= 0x00000068) && 3695 (adev->gfx.pfp_feature_version >= 27) && 3696 (adev->gfx.mec_fw_version >= 0x0000005b) && 3697 (adev->gfx.mec_feature_version >= 27)) 3698 adev->gfx.cp_fw_write_wait = true; 3699 break; 3700 case CHIP_SIENNA_CICHLID: 3701 case CHIP_NAVY_FLOUNDER: 3702 case CHIP_VANGOGH: 3703 case CHIP_DIMGREY_CAVEFISH: 3704 adev->gfx.cp_fw_write_wait = true; 3705 break; 3706 default: 3707 break; 3708 } 3709 3710 if (!adev->gfx.cp_fw_write_wait) 3711 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3712 } 3713 3714 3715 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3716 { 3717 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3718 3719 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 3720 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 3721 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 3722 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 3723 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 3724 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 3725 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 3726 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 3727 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 3728 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 3729 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 3730 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 3731 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 3732 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 3733 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 3734 } 3735 3736 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 3737 { 3738 const struct rlc_firmware_header_v2_2 *rlc_hdr; 3739 3740 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 3741 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 3742 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 3743 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 3744 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 3745 } 3746 3747 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3748 { 3749 bool ret = false; 3750 3751 switch (adev->pdev->revision) { 3752 case 0xc2: 3753 case 0xc3: 3754 ret = true; 3755 break; 3756 default: 3757 ret = false; 3758 break; 3759 } 3760 3761 return ret ; 3762 } 3763 3764 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3765 { 3766 switch (adev->asic_type) { 3767 case CHIP_NAVI10: 3768 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3769 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3770 break; 3771 case CHIP_VANGOGH: 3772 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3773 break; 3774 default: 3775 break; 3776 } 3777 } 3778 3779 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3780 { 3781 const char *chip_name; 3782 char fw_name[40]; 3783 char wks[10]; 3784 int err; 3785 struct amdgpu_firmware_info *info = NULL; 3786 const struct common_firmware_header *header = NULL; 3787 const struct gfx_firmware_header_v1_0 *cp_hdr; 3788 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3789 unsigned int *tmp = NULL; 3790 unsigned int i = 0; 3791 uint16_t version_major; 3792 uint16_t version_minor; 3793 3794 DRM_DEBUG("\n"); 3795 3796 memset(wks, 0, sizeof(wks)); 3797 switch (adev->asic_type) { 3798 case CHIP_NAVI10: 3799 chip_name = "navi10"; 3800 break; 3801 case CHIP_NAVI14: 3802 chip_name = "navi14"; 3803 if (!(adev->pdev->device == 0x7340 && 3804 adev->pdev->revision != 0x00)) 3805 snprintf(wks, sizeof(wks), "_wks"); 3806 break; 3807 case CHIP_NAVI12: 3808 chip_name = "navi12"; 3809 break; 3810 case CHIP_SIENNA_CICHLID: 3811 chip_name = "sienna_cichlid"; 3812 break; 3813 case CHIP_NAVY_FLOUNDER: 3814 chip_name = "navy_flounder"; 3815 break; 3816 case CHIP_VANGOGH: 3817 chip_name = "vangogh"; 3818 break; 3819 case CHIP_DIMGREY_CAVEFISH: 3820 chip_name = "dimgrey_cavefish"; 3821 break; 3822 default: 3823 BUG(); 3824 } 3825 3826 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 3827 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 3828 if (err) 3829 goto out; 3830 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 3831 if (err) 3832 goto out; 3833 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3834 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3835 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3836 3837 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 3838 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 3839 if (err) 3840 goto out; 3841 err = amdgpu_ucode_validate(adev->gfx.me_fw); 3842 if (err) 3843 goto out; 3844 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3845 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3846 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3847 3848 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 3849 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 3850 if (err) 3851 goto out; 3852 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 3853 if (err) 3854 goto out; 3855 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3856 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3857 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3858 3859 if (!amdgpu_sriov_vf(adev)) { 3860 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 3861 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 3862 if (err) 3863 goto out; 3864 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 3865 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3866 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 3867 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 3868 3869 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 3870 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 3871 adev->gfx.rlc.save_and_restore_offset = 3872 le32_to_cpu(rlc_hdr->save_and_restore_offset); 3873 adev->gfx.rlc.clear_state_descriptor_offset = 3874 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 3875 adev->gfx.rlc.avail_scratch_ram_locations = 3876 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 3877 adev->gfx.rlc.reg_restore_list_size = 3878 le32_to_cpu(rlc_hdr->reg_restore_list_size); 3879 adev->gfx.rlc.reg_list_format_start = 3880 le32_to_cpu(rlc_hdr->reg_list_format_start); 3881 adev->gfx.rlc.reg_list_format_separate_start = 3882 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 3883 adev->gfx.rlc.starting_offsets_start = 3884 le32_to_cpu(rlc_hdr->starting_offsets_start); 3885 adev->gfx.rlc.reg_list_format_size_bytes = 3886 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 3887 adev->gfx.rlc.reg_list_size_bytes = 3888 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 3889 adev->gfx.rlc.register_list_format = 3890 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 3891 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 3892 if (!adev->gfx.rlc.register_list_format) { 3893 err = -ENOMEM; 3894 goto out; 3895 } 3896 3897 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3898 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 3899 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 3900 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 3901 3902 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 3903 3904 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3905 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 3906 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 3907 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 3908 3909 if (version_major == 2) { 3910 if (version_minor >= 1) 3911 gfx_v10_0_init_rlc_ext_microcode(adev); 3912 if (version_minor == 2) 3913 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 3914 } 3915 } 3916 3917 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 3918 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 3919 if (err) 3920 goto out; 3921 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 3922 if (err) 3923 goto out; 3924 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3925 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3926 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3927 3928 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 3929 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 3930 if (!err) { 3931 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 3932 if (err) 3933 goto out; 3934 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 3935 adev->gfx.mec2_fw->data; 3936 adev->gfx.mec2_fw_version = 3937 le32_to_cpu(cp_hdr->header.ucode_version); 3938 adev->gfx.mec2_feature_version = 3939 le32_to_cpu(cp_hdr->ucode_feature_version); 3940 } else { 3941 err = 0; 3942 adev->gfx.mec2_fw = NULL; 3943 } 3944 3945 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 3946 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 3947 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 3948 info->fw = adev->gfx.pfp_fw; 3949 header = (const struct common_firmware_header *)info->fw->data; 3950 adev->firmware.fw_size += 3951 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3952 3953 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 3954 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 3955 info->fw = adev->gfx.me_fw; 3956 header = (const struct common_firmware_header *)info->fw->data; 3957 adev->firmware.fw_size += 3958 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3959 3960 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 3961 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 3962 info->fw = adev->gfx.ce_fw; 3963 header = (const struct common_firmware_header *)info->fw->data; 3964 adev->firmware.fw_size += 3965 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3966 3967 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 3968 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 3969 info->fw = adev->gfx.rlc_fw; 3970 if (info->fw) { 3971 header = (const struct common_firmware_header *)info->fw->data; 3972 adev->firmware.fw_size += 3973 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3974 } 3975 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 3976 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 3977 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 3978 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 3979 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 3980 info->fw = adev->gfx.rlc_fw; 3981 adev->firmware.fw_size += 3982 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 3983 3984 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 3985 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 3986 info->fw = adev->gfx.rlc_fw; 3987 adev->firmware.fw_size += 3988 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 3989 3990 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 3991 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 3992 info->fw = adev->gfx.rlc_fw; 3993 adev->firmware.fw_size += 3994 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 3995 3996 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 3997 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 3998 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 3999 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 4000 info->fw = adev->gfx.rlc_fw; 4001 adev->firmware.fw_size += 4002 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4003 4004 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4005 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4006 info->fw = adev->gfx.rlc_fw; 4007 adev->firmware.fw_size += 4008 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4009 } 4010 } 4011 4012 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4013 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4014 info->fw = adev->gfx.mec_fw; 4015 header = (const struct common_firmware_header *)info->fw->data; 4016 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4017 adev->firmware.fw_size += 4018 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4019 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4020 4021 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4022 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4023 info->fw = adev->gfx.mec_fw; 4024 adev->firmware.fw_size += 4025 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4026 4027 if (adev->gfx.mec2_fw) { 4028 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4029 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4030 info->fw = adev->gfx.mec2_fw; 4031 header = (const struct common_firmware_header *)info->fw->data; 4032 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4033 adev->firmware.fw_size += 4034 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4035 le32_to_cpu(cp_hdr->jt_size) * 4, 4036 PAGE_SIZE); 4037 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4038 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4039 info->fw = adev->gfx.mec2_fw; 4040 adev->firmware.fw_size += 4041 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4042 PAGE_SIZE); 4043 } 4044 } 4045 4046 gfx_v10_0_check_fw_write_wait(adev); 4047 out: 4048 if (err) { 4049 dev_err(adev->dev, 4050 "gfx10: Failed to load firmware \"%s\"\n", 4051 fw_name); 4052 release_firmware(adev->gfx.pfp_fw); 4053 adev->gfx.pfp_fw = NULL; 4054 release_firmware(adev->gfx.me_fw); 4055 adev->gfx.me_fw = NULL; 4056 release_firmware(adev->gfx.ce_fw); 4057 adev->gfx.ce_fw = NULL; 4058 release_firmware(adev->gfx.rlc_fw); 4059 adev->gfx.rlc_fw = NULL; 4060 release_firmware(adev->gfx.mec_fw); 4061 adev->gfx.mec_fw = NULL; 4062 release_firmware(adev->gfx.mec2_fw); 4063 adev->gfx.mec2_fw = NULL; 4064 } 4065 4066 gfx_v10_0_check_gfxoff_flag(adev); 4067 4068 return err; 4069 } 4070 4071 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4072 { 4073 u32 count = 0; 4074 const struct cs_section_def *sect = NULL; 4075 const struct cs_extent_def *ext = NULL; 4076 4077 /* begin clear state */ 4078 count += 2; 4079 /* context control state */ 4080 count += 3; 4081 4082 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4083 for (ext = sect->section; ext->extent != NULL; ++ext) { 4084 if (sect->id == SECT_CONTEXT) 4085 count += 2 + ext->reg_count; 4086 else 4087 return 0; 4088 } 4089 } 4090 4091 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4092 count += 3; 4093 /* end clear state */ 4094 count += 2; 4095 /* clear state */ 4096 count += 2; 4097 4098 return count; 4099 } 4100 4101 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4102 volatile u32 *buffer) 4103 { 4104 u32 count = 0, i; 4105 const struct cs_section_def *sect = NULL; 4106 const struct cs_extent_def *ext = NULL; 4107 int ctx_reg_offset; 4108 4109 if (adev->gfx.rlc.cs_data == NULL) 4110 return; 4111 if (buffer == NULL) 4112 return; 4113 4114 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4115 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4116 4117 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4118 buffer[count++] = cpu_to_le32(0x80000000); 4119 buffer[count++] = cpu_to_le32(0x80000000); 4120 4121 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4122 for (ext = sect->section; ext->extent != NULL; ++ext) { 4123 if (sect->id == SECT_CONTEXT) { 4124 buffer[count++] = 4125 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4126 buffer[count++] = cpu_to_le32(ext->reg_index - 4127 PACKET3_SET_CONTEXT_REG_START); 4128 for (i = 0; i < ext->reg_count; i++) 4129 buffer[count++] = cpu_to_le32(ext->extent[i]); 4130 } else { 4131 return; 4132 } 4133 } 4134 } 4135 4136 ctx_reg_offset = 4137 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4138 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4139 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4140 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4141 4142 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4143 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4144 4145 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4146 buffer[count++] = cpu_to_le32(0); 4147 } 4148 4149 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4150 { 4151 /* clear state block */ 4152 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4153 &adev->gfx.rlc.clear_state_gpu_addr, 4154 (void **)&adev->gfx.rlc.cs_ptr); 4155 4156 /* jump table block */ 4157 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4158 &adev->gfx.rlc.cp_table_gpu_addr, 4159 (void **)&adev->gfx.rlc.cp_table_ptr); 4160 } 4161 4162 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4163 { 4164 const struct cs_section_def *cs_data; 4165 int r; 4166 4167 adev->gfx.rlc.cs_data = gfx10_cs_data; 4168 4169 cs_data = adev->gfx.rlc.cs_data; 4170 4171 if (cs_data) { 4172 /* init clear state block */ 4173 r = amdgpu_gfx_rlc_init_csb(adev); 4174 if (r) 4175 return r; 4176 } 4177 4178 /* init spm vmid with 0xf */ 4179 if (adev->gfx.rlc.funcs->update_spm_vmid) 4180 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4181 4182 return 0; 4183 } 4184 4185 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4186 { 4187 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4188 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4189 } 4190 4191 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4192 { 4193 int r; 4194 4195 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4196 4197 amdgpu_gfx_graphics_queue_acquire(adev); 4198 4199 r = gfx_v10_0_init_microcode(adev); 4200 if (r) 4201 DRM_ERROR("Failed to load gfx firmware!\n"); 4202 4203 return r; 4204 } 4205 4206 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4207 { 4208 int r; 4209 u32 *hpd; 4210 const __le32 *fw_data = NULL; 4211 unsigned fw_size; 4212 u32 *fw = NULL; 4213 size_t mec_hpd_size; 4214 4215 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4216 4217 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4218 4219 /* take ownership of the relevant compute queues */ 4220 amdgpu_gfx_compute_queue_acquire(adev); 4221 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4222 4223 if (mec_hpd_size) { 4224 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4225 AMDGPU_GEM_DOMAIN_GTT, 4226 &adev->gfx.mec.hpd_eop_obj, 4227 &adev->gfx.mec.hpd_eop_gpu_addr, 4228 (void **)&hpd); 4229 if (r) { 4230 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4231 gfx_v10_0_mec_fini(adev); 4232 return r; 4233 } 4234 4235 memset(hpd, 0, mec_hpd_size); 4236 4237 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4238 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4239 } 4240 4241 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4242 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4243 4244 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4245 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4246 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4247 4248 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4249 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4250 &adev->gfx.mec.mec_fw_obj, 4251 &adev->gfx.mec.mec_fw_gpu_addr, 4252 (void **)&fw); 4253 if (r) { 4254 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4255 gfx_v10_0_mec_fini(adev); 4256 return r; 4257 } 4258 4259 memcpy(fw, fw_data, fw_size); 4260 4261 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4262 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4263 } 4264 4265 return 0; 4266 } 4267 4268 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4269 { 4270 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4271 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4272 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4273 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4274 } 4275 4276 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4277 uint32_t thread, uint32_t regno, 4278 uint32_t num, uint32_t *out) 4279 { 4280 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4281 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4282 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4283 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4284 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4285 while (num--) 4286 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4287 } 4288 4289 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4290 { 4291 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4292 * field when performing a select_se_sh so it should be 4293 * zero here */ 4294 WARN_ON(simd != 0); 4295 4296 /* type 2 wave data */ 4297 dst[(*no_fields)++] = 2; 4298 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4299 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4300 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4301 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4302 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4303 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4304 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4305 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4306 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4307 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4308 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4309 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4310 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4311 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4312 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4313 } 4314 4315 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4316 uint32_t wave, uint32_t start, 4317 uint32_t size, uint32_t *dst) 4318 { 4319 WARN_ON(simd != 0); 4320 4321 wave_read_regs( 4322 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4323 dst); 4324 } 4325 4326 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4327 uint32_t wave, uint32_t thread, 4328 uint32_t start, uint32_t size, 4329 uint32_t *dst) 4330 { 4331 wave_read_regs( 4332 adev, wave, thread, 4333 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4334 } 4335 4336 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4337 u32 me, u32 pipe, u32 q, u32 vm) 4338 { 4339 nv_grbm_select(adev, me, pipe, q, vm); 4340 } 4341 4342 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4343 bool enable) 4344 { 4345 uint32_t data, def; 4346 4347 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4348 4349 if (enable) 4350 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4351 else 4352 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4353 4354 if (data != def) 4355 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4356 } 4357 4358 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4359 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4360 .select_se_sh = &gfx_v10_0_select_se_sh, 4361 .read_wave_data = &gfx_v10_0_read_wave_data, 4362 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4363 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4364 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4365 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4366 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4367 }; 4368 4369 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4370 { 4371 u32 gb_addr_config; 4372 4373 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4374 4375 switch (adev->asic_type) { 4376 case CHIP_NAVI10: 4377 case CHIP_NAVI14: 4378 case CHIP_NAVI12: 4379 adev->gfx.config.max_hw_contexts = 8; 4380 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4381 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4382 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4383 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4384 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4385 break; 4386 case CHIP_SIENNA_CICHLID: 4387 case CHIP_NAVY_FLOUNDER: 4388 case CHIP_VANGOGH: 4389 case CHIP_DIMGREY_CAVEFISH: 4390 adev->gfx.config.max_hw_contexts = 8; 4391 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4392 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4393 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4394 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4395 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4396 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4397 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4398 break; 4399 default: 4400 BUG(); 4401 break; 4402 } 4403 4404 adev->gfx.config.gb_addr_config = gb_addr_config; 4405 4406 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4407 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4408 GB_ADDR_CONFIG, NUM_PIPES); 4409 4410 adev->gfx.config.max_tile_pipes = 4411 adev->gfx.config.gb_addr_config_fields.num_pipes; 4412 4413 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4414 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4415 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4416 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4417 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4418 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4419 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4420 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4421 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4422 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4423 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4424 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4425 } 4426 4427 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4428 int me, int pipe, int queue) 4429 { 4430 int r; 4431 struct amdgpu_ring *ring; 4432 unsigned int irq_type; 4433 4434 ring = &adev->gfx.gfx_ring[ring_id]; 4435 4436 ring->me = me; 4437 ring->pipe = pipe; 4438 ring->queue = queue; 4439 4440 ring->ring_obj = NULL; 4441 ring->use_doorbell = true; 4442 4443 if (!ring_id) 4444 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4445 else 4446 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4447 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4448 4449 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4450 r = amdgpu_ring_init(adev, ring, 1024, 4451 &adev->gfx.eop_irq, irq_type, 4452 AMDGPU_RING_PRIO_DEFAULT); 4453 if (r) 4454 return r; 4455 return 0; 4456 } 4457 4458 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4459 int mec, int pipe, int queue) 4460 { 4461 int r; 4462 unsigned irq_type; 4463 struct amdgpu_ring *ring; 4464 unsigned int hw_prio; 4465 4466 ring = &adev->gfx.compute_ring[ring_id]; 4467 4468 /* mec0 is me1 */ 4469 ring->me = mec + 1; 4470 ring->pipe = pipe; 4471 ring->queue = queue; 4472 4473 ring->ring_obj = NULL; 4474 ring->use_doorbell = true; 4475 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4476 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4477 + (ring_id * GFX10_MEC_HPD_SIZE); 4478 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4479 4480 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4481 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4482 + ring->pipe; 4483 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 4484 ring->queue) ? 4485 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4486 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4487 r = amdgpu_ring_init(adev, ring, 1024, 4488 &adev->gfx.eop_irq, irq_type, hw_prio); 4489 if (r) 4490 return r; 4491 4492 return 0; 4493 } 4494 4495 static int gfx_v10_0_sw_init(void *handle) 4496 { 4497 int i, j, k, r, ring_id = 0; 4498 struct amdgpu_kiq *kiq; 4499 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4500 4501 switch (adev->asic_type) { 4502 case CHIP_NAVI10: 4503 case CHIP_NAVI14: 4504 case CHIP_NAVI12: 4505 adev->gfx.me.num_me = 1; 4506 adev->gfx.me.num_pipe_per_me = 1; 4507 adev->gfx.me.num_queue_per_pipe = 1; 4508 adev->gfx.mec.num_mec = 2; 4509 adev->gfx.mec.num_pipe_per_mec = 4; 4510 adev->gfx.mec.num_queue_per_pipe = 8; 4511 break; 4512 case CHIP_SIENNA_CICHLID: 4513 case CHIP_NAVY_FLOUNDER: 4514 case CHIP_VANGOGH: 4515 case CHIP_DIMGREY_CAVEFISH: 4516 adev->gfx.me.num_me = 1; 4517 adev->gfx.me.num_pipe_per_me = 1; 4518 adev->gfx.me.num_queue_per_pipe = 1; 4519 adev->gfx.mec.num_mec = 2; 4520 adev->gfx.mec.num_pipe_per_mec = 4; 4521 adev->gfx.mec.num_queue_per_pipe = 4; 4522 break; 4523 default: 4524 adev->gfx.me.num_me = 1; 4525 adev->gfx.me.num_pipe_per_me = 1; 4526 adev->gfx.me.num_queue_per_pipe = 1; 4527 adev->gfx.mec.num_mec = 1; 4528 adev->gfx.mec.num_pipe_per_mec = 4; 4529 adev->gfx.mec.num_queue_per_pipe = 8; 4530 break; 4531 } 4532 4533 /* KIQ event */ 4534 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4535 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4536 &adev->gfx.kiq.irq); 4537 if (r) 4538 return r; 4539 4540 /* EOP Event */ 4541 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4542 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4543 &adev->gfx.eop_irq); 4544 if (r) 4545 return r; 4546 4547 /* Privileged reg */ 4548 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4549 &adev->gfx.priv_reg_irq); 4550 if (r) 4551 return r; 4552 4553 /* Privileged inst */ 4554 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4555 &adev->gfx.priv_inst_irq); 4556 if (r) 4557 return r; 4558 4559 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4560 4561 gfx_v10_0_scratch_init(adev); 4562 4563 r = gfx_v10_0_me_init(adev); 4564 if (r) 4565 return r; 4566 4567 r = gfx_v10_0_rlc_init(adev); 4568 if (r) { 4569 DRM_ERROR("Failed to init rlc BOs!\n"); 4570 return r; 4571 } 4572 4573 r = gfx_v10_0_mec_init(adev); 4574 if (r) { 4575 DRM_ERROR("Failed to init MEC BOs!\n"); 4576 return r; 4577 } 4578 4579 /* set up the gfx ring */ 4580 for (i = 0; i < adev->gfx.me.num_me; i++) { 4581 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4582 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4583 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4584 continue; 4585 4586 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4587 i, k, j); 4588 if (r) 4589 return r; 4590 ring_id++; 4591 } 4592 } 4593 } 4594 4595 ring_id = 0; 4596 /* set up the compute queues - allocate horizontally across pipes */ 4597 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4598 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4599 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4600 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4601 j)) 4602 continue; 4603 4604 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4605 i, k, j); 4606 if (r) 4607 return r; 4608 4609 ring_id++; 4610 } 4611 } 4612 } 4613 4614 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4615 if (r) { 4616 DRM_ERROR("Failed to init KIQ BOs!\n"); 4617 return r; 4618 } 4619 4620 kiq = &adev->gfx.kiq; 4621 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4622 if (r) 4623 return r; 4624 4625 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4626 if (r) 4627 return r; 4628 4629 /* allocate visible FB for rlc auto-loading fw */ 4630 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4631 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4632 if (r) 4633 return r; 4634 } 4635 4636 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4637 4638 gfx_v10_0_gpu_early_init(adev); 4639 4640 return 0; 4641 } 4642 4643 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4644 { 4645 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4646 &adev->gfx.pfp.pfp_fw_gpu_addr, 4647 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4648 } 4649 4650 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4651 { 4652 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4653 &adev->gfx.ce.ce_fw_gpu_addr, 4654 (void **)&adev->gfx.ce.ce_fw_ptr); 4655 } 4656 4657 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4658 { 4659 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4660 &adev->gfx.me.me_fw_gpu_addr, 4661 (void **)&adev->gfx.me.me_fw_ptr); 4662 } 4663 4664 static int gfx_v10_0_sw_fini(void *handle) 4665 { 4666 int i; 4667 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4668 4669 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4670 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4671 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4672 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4673 4674 amdgpu_gfx_mqd_sw_fini(adev); 4675 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4676 amdgpu_gfx_kiq_fini(adev); 4677 4678 gfx_v10_0_pfp_fini(adev); 4679 gfx_v10_0_ce_fini(adev); 4680 gfx_v10_0_me_fini(adev); 4681 gfx_v10_0_rlc_fini(adev); 4682 gfx_v10_0_mec_fini(adev); 4683 4684 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4685 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4686 4687 gfx_v10_0_free_microcode(adev); 4688 4689 return 0; 4690 } 4691 4692 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4693 u32 sh_num, u32 instance) 4694 { 4695 u32 data; 4696 4697 if (instance == 0xffffffff) 4698 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4699 INSTANCE_BROADCAST_WRITES, 1); 4700 else 4701 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4702 instance); 4703 4704 if (se_num == 0xffffffff) 4705 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4706 1); 4707 else 4708 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4709 4710 if (sh_num == 0xffffffff) 4711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4712 1); 4713 else 4714 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4715 4716 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4717 } 4718 4719 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4720 { 4721 u32 data, mask; 4722 4723 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4724 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4725 4726 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4727 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4728 4729 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4730 adev->gfx.config.max_sh_per_se); 4731 4732 return (~data) & mask; 4733 } 4734 4735 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4736 { 4737 int i, j; 4738 u32 data; 4739 u32 active_rbs = 0; 4740 u32 bitmap; 4741 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4742 adev->gfx.config.max_sh_per_se; 4743 4744 mutex_lock(&adev->grbm_idx_mutex); 4745 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4746 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4747 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4748 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 4749 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4750 continue; 4751 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4752 data = gfx_v10_0_get_rb_active_bitmap(adev); 4753 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4754 rb_bitmap_width_per_sh); 4755 } 4756 } 4757 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4758 mutex_unlock(&adev->grbm_idx_mutex); 4759 4760 adev->gfx.config.backend_enable_mask = active_rbs; 4761 adev->gfx.config.num_rbs = hweight32(active_rbs); 4762 } 4763 4764 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4765 { 4766 uint32_t num_sc; 4767 uint32_t enabled_rb_per_sh; 4768 uint32_t active_rb_bitmap; 4769 uint32_t num_rb_per_sc; 4770 uint32_t num_packer_per_sc; 4771 uint32_t pa_sc_tile_steering_override; 4772 4773 /* for ASICs that integrates GFX v10.3 4774 * pa_sc_tile_steering_override should be set to 0 */ 4775 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 4776 return 0; 4777 4778 /* init num_sc */ 4779 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4780 adev->gfx.config.num_sc_per_sh; 4781 /* init num_rb_per_sc */ 4782 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4783 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4784 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4785 /* init num_packer_per_sc */ 4786 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4787 4788 pa_sc_tile_steering_override = 0; 4789 pa_sc_tile_steering_override |= 4790 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4791 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4792 pa_sc_tile_steering_override |= 4793 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4794 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4795 pa_sc_tile_steering_override |= 4796 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4797 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4798 4799 return pa_sc_tile_steering_override; 4800 } 4801 4802 #define DEFAULT_SH_MEM_BASES (0x6000) 4803 4804 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4805 { 4806 int i; 4807 uint32_t sh_mem_bases; 4808 4809 /* 4810 * Configure apertures: 4811 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4812 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4813 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4814 */ 4815 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4816 4817 mutex_lock(&adev->srbm_mutex); 4818 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4819 nv_grbm_select(adev, 0, 0, 0, i); 4820 /* CP and shaders */ 4821 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4822 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4823 } 4824 nv_grbm_select(adev, 0, 0, 0, 0); 4825 mutex_unlock(&adev->srbm_mutex); 4826 4827 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4828 acccess. These should be enabled by FW for target VMIDs. */ 4829 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4830 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4831 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4832 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4833 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4834 } 4835 } 4836 4837 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4838 { 4839 int vmid; 4840 4841 /* 4842 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4843 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4844 * the driver can enable them for graphics. VMID0 should maintain 4845 * access so that HWS firmware can save/restore entries. 4846 */ 4847 for (vmid = 1; vmid < 16; vmid++) { 4848 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4849 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4850 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4851 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4852 } 4853 } 4854 4855 4856 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4857 { 4858 int i, j, k; 4859 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4860 u32 tmp, wgp_active_bitmap = 0; 4861 u32 gcrd_targets_disable_tcp = 0; 4862 u32 utcl_invreq_disable = 0; 4863 /* 4864 * GCRD_TARGETS_DISABLE field contains 4865 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4866 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4867 */ 4868 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4869 2 * max_wgp_per_sh + /* TCP */ 4870 max_wgp_per_sh + /* SQC */ 4871 4); /* GL1C */ 4872 /* 4873 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4874 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4875 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4876 */ 4877 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4878 2 * max_wgp_per_sh + /* TCP */ 4879 2 * max_wgp_per_sh + /* SQC */ 4880 4 + /* RMI */ 4881 1); /* SQG */ 4882 4883 if (adev->asic_type == CHIP_NAVI10 || 4884 adev->asic_type == CHIP_NAVI14 || 4885 adev->asic_type == CHIP_NAVI12) { 4886 mutex_lock(&adev->grbm_idx_mutex); 4887 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4888 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4889 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4890 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4891 /* 4892 * Set corresponding TCP bits for the inactive WGPs in 4893 * GCRD_SA_TARGETS_DISABLE 4894 */ 4895 gcrd_targets_disable_tcp = 0; 4896 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4897 utcl_invreq_disable = 0; 4898 4899 for (k = 0; k < max_wgp_per_sh; k++) { 4900 if (!(wgp_active_bitmap & (1 << k))) { 4901 gcrd_targets_disable_tcp |= 3 << (2 * k); 4902 utcl_invreq_disable |= (3 << (2 * k)) | 4903 (3 << (2 * (max_wgp_per_sh + k))); 4904 } 4905 } 4906 4907 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4908 /* only override TCP & SQC bits */ 4909 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 4910 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4911 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4912 4913 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4914 /* only override TCP bits */ 4915 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 4916 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4917 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4918 } 4919 } 4920 4921 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4922 mutex_unlock(&adev->grbm_idx_mutex); 4923 } 4924 } 4925 4926 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4927 { 4928 /* TCCs are global (not instanced). */ 4929 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4930 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4931 4932 adev->gfx.config.tcc_disabled_mask = 4933 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4934 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4935 } 4936 4937 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4938 { 4939 u32 tmp; 4940 int i; 4941 4942 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4943 4944 gfx_v10_0_setup_rb(adev); 4945 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4946 gfx_v10_0_get_tcc_info(adev); 4947 adev->gfx.config.pa_sc_tile_steering_override = 4948 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4949 4950 /* XXX SH_MEM regs */ 4951 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4952 mutex_lock(&adev->srbm_mutex); 4953 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 4954 nv_grbm_select(adev, 0, 0, 0, i); 4955 /* CP and shaders */ 4956 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4957 if (i != 0) { 4958 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4959 (adev->gmc.private_aperture_start >> 48)); 4960 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4961 (adev->gmc.shared_aperture_start >> 48)); 4962 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4963 } 4964 } 4965 nv_grbm_select(adev, 0, 0, 0, 0); 4966 4967 mutex_unlock(&adev->srbm_mutex); 4968 4969 gfx_v10_0_init_compute_vmid(adev); 4970 gfx_v10_0_init_gds_vmid(adev); 4971 4972 } 4973 4974 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 4975 bool enable) 4976 { 4977 u32 tmp; 4978 4979 if (amdgpu_sriov_vf(adev)) 4980 return; 4981 4982 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 4983 4984 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 4985 enable ? 1 : 0); 4986 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 4987 enable ? 1 : 0); 4988 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 4989 enable ? 1 : 0); 4990 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 4991 enable ? 1 : 0); 4992 4993 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 4994 } 4995 4996 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 4997 { 4998 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 4999 5000 /* csib */ 5001 if (adev->asic_type == CHIP_NAVI12) { 5002 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5003 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5004 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5005 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5006 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5007 } else { 5008 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5009 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5010 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5011 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5012 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5013 } 5014 return 0; 5015 } 5016 5017 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5018 { 5019 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5020 5021 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5022 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5023 } 5024 5025 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5026 { 5027 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5028 udelay(50); 5029 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5030 udelay(50); 5031 } 5032 5033 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5034 bool enable) 5035 { 5036 uint32_t rlc_pg_cntl; 5037 5038 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5039 5040 if (!enable) { 5041 /* RLC_PG_CNTL[23] = 0 (default) 5042 * RLC will wait for handshake acks with SMU 5043 * GFXOFF will be enabled 5044 * RLC_PG_CNTL[23] = 1 5045 * RLC will not issue any message to SMU 5046 * hence no handshake between SMU & RLC 5047 * GFXOFF will be disabled 5048 */ 5049 rlc_pg_cntl |= 0x800000; 5050 } else 5051 rlc_pg_cntl &= ~0x800000; 5052 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5053 } 5054 5055 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5056 { 5057 /* TODO: enable rlc & smu handshake until smu 5058 * and gfxoff feature works as expected */ 5059 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5060 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5061 5062 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5063 udelay(50); 5064 } 5065 5066 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5067 { 5068 uint32_t tmp; 5069 5070 /* enable Save Restore Machine */ 5071 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 5072 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5073 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5074 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 5075 } 5076 5077 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5078 { 5079 const struct rlc_firmware_header_v2_0 *hdr; 5080 const __le32 *fw_data; 5081 unsigned i, fw_size; 5082 5083 if (!adev->gfx.rlc_fw) 5084 return -EINVAL; 5085 5086 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5087 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5088 5089 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5090 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5091 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5092 5093 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5094 RLCG_UCODE_LOADING_START_ADDRESS); 5095 5096 for (i = 0; i < fw_size; i++) 5097 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5098 le32_to_cpup(fw_data++)); 5099 5100 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5101 5102 return 0; 5103 } 5104 5105 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5106 { 5107 int r; 5108 5109 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 5110 5111 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5112 if (r) 5113 return r; 5114 5115 gfx_v10_0_init_csb(adev); 5116 5117 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5118 gfx_v10_0_rlc_enable_srm(adev); 5119 } else { 5120 if (amdgpu_sriov_vf(adev)) { 5121 gfx_v10_0_init_csb(adev); 5122 return 0; 5123 } 5124 5125 adev->gfx.rlc.funcs->stop(adev); 5126 5127 /* disable CG */ 5128 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5129 5130 /* disable PG */ 5131 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5132 5133 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5134 /* legacy rlc firmware loading */ 5135 r = gfx_v10_0_rlc_load_microcode(adev); 5136 if (r) 5137 return r; 5138 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5139 /* rlc backdoor autoload firmware */ 5140 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5141 if (r) 5142 return r; 5143 } 5144 5145 gfx_v10_0_init_csb(adev); 5146 5147 adev->gfx.rlc.funcs->start(adev); 5148 5149 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5150 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5151 if (r) 5152 return r; 5153 } 5154 } 5155 return 0; 5156 } 5157 5158 static struct { 5159 FIRMWARE_ID id; 5160 unsigned int offset; 5161 unsigned int size; 5162 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5163 5164 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5165 { 5166 int ret; 5167 RLC_TABLE_OF_CONTENT *rlc_toc; 5168 5169 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 5170 AMDGPU_GEM_DOMAIN_GTT, 5171 &adev->gfx.rlc.rlc_toc_bo, 5172 &adev->gfx.rlc.rlc_toc_gpu_addr, 5173 (void **)&adev->gfx.rlc.rlc_toc_buf); 5174 if (ret) { 5175 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5176 return ret; 5177 } 5178 5179 /* Copy toc from psp sos fw to rlc toc buffer */ 5180 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 5181 5182 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5183 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5184 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5185 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5186 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5187 /* Offset needs 4KB alignment */ 5188 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5189 } 5190 5191 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5192 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5193 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5194 5195 rlc_toc++; 5196 } 5197 5198 return 0; 5199 } 5200 5201 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5202 { 5203 uint32_t total_size = 0; 5204 FIRMWARE_ID id; 5205 int ret; 5206 5207 ret = gfx_v10_0_parse_rlc_toc(adev); 5208 if (ret) { 5209 dev_err(adev->dev, "failed to parse rlc toc\n"); 5210 return 0; 5211 } 5212 5213 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5214 total_size += rlc_autoload_info[id].size; 5215 5216 /* In case the offset in rlc toc ucode is aligned */ 5217 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5218 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5219 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5220 5221 return total_size; 5222 } 5223 5224 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5225 { 5226 int r; 5227 uint32_t total_size; 5228 5229 total_size = gfx_v10_0_calc_toc_total_size(adev); 5230 5231 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5232 AMDGPU_GEM_DOMAIN_GTT, 5233 &adev->gfx.rlc.rlc_autoload_bo, 5234 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5235 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5236 if (r) { 5237 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5238 return r; 5239 } 5240 5241 return 0; 5242 } 5243 5244 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5245 { 5246 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5247 &adev->gfx.rlc.rlc_toc_gpu_addr, 5248 (void **)&adev->gfx.rlc.rlc_toc_buf); 5249 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5250 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5251 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5252 } 5253 5254 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5255 FIRMWARE_ID id, 5256 const void *fw_data, 5257 uint32_t fw_size) 5258 { 5259 uint32_t toc_offset; 5260 uint32_t toc_fw_size; 5261 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5262 5263 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5264 return; 5265 5266 toc_offset = rlc_autoload_info[id].offset; 5267 toc_fw_size = rlc_autoload_info[id].size; 5268 5269 if (fw_size == 0) 5270 fw_size = toc_fw_size; 5271 5272 if (fw_size > toc_fw_size) 5273 fw_size = toc_fw_size; 5274 5275 memcpy(ptr + toc_offset, fw_data, fw_size); 5276 5277 if (fw_size < toc_fw_size) 5278 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5279 } 5280 5281 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5282 { 5283 void *data; 5284 uint32_t size; 5285 5286 data = adev->gfx.rlc.rlc_toc_buf; 5287 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5288 5289 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5290 FIRMWARE_ID_RLC_TOC, 5291 data, size); 5292 } 5293 5294 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5295 { 5296 const __le32 *fw_data; 5297 uint32_t fw_size; 5298 const struct gfx_firmware_header_v1_0 *cp_hdr; 5299 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5300 5301 /* pfp ucode */ 5302 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5303 adev->gfx.pfp_fw->data; 5304 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5305 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5306 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5307 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5308 FIRMWARE_ID_CP_PFP, 5309 fw_data, fw_size); 5310 5311 /* ce ucode */ 5312 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5313 adev->gfx.ce_fw->data; 5314 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5315 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5316 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5317 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5318 FIRMWARE_ID_CP_CE, 5319 fw_data, fw_size); 5320 5321 /* me ucode */ 5322 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5323 adev->gfx.me_fw->data; 5324 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5325 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5326 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5327 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5328 FIRMWARE_ID_CP_ME, 5329 fw_data, fw_size); 5330 5331 /* rlc ucode */ 5332 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5333 adev->gfx.rlc_fw->data; 5334 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5335 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5336 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5337 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5338 FIRMWARE_ID_RLC_G_UCODE, 5339 fw_data, fw_size); 5340 5341 /* mec1 ucode */ 5342 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5343 adev->gfx.mec_fw->data; 5344 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5345 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5346 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5347 cp_hdr->jt_size * 4; 5348 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5349 FIRMWARE_ID_CP_MEC, 5350 fw_data, fw_size); 5351 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5352 } 5353 5354 /* Temporarily put sdma part here */ 5355 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5356 { 5357 const __le32 *fw_data; 5358 uint32_t fw_size; 5359 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5360 int i; 5361 5362 for (i = 0; i < adev->sdma.num_instances; i++) { 5363 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5364 adev->sdma.instance[i].fw->data; 5365 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5366 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5367 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5368 5369 if (i == 0) { 5370 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5371 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5372 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5373 FIRMWARE_ID_SDMA0_JT, 5374 (uint32_t *)fw_data + 5375 sdma_hdr->jt_offset, 5376 sdma_hdr->jt_size * 4); 5377 } else if (i == 1) { 5378 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5379 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5380 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5381 FIRMWARE_ID_SDMA1_JT, 5382 (uint32_t *)fw_data + 5383 sdma_hdr->jt_offset, 5384 sdma_hdr->jt_size * 4); 5385 } 5386 } 5387 } 5388 5389 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5390 { 5391 uint32_t rlc_g_offset, rlc_g_size, tmp; 5392 uint64_t gpu_addr; 5393 5394 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5395 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5396 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5397 5398 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5399 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5400 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5401 5402 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5403 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5404 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5405 5406 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5407 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5408 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5409 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5410 return -EINVAL; 5411 } 5412 5413 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5414 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5415 DRM_ERROR("RLC ROM should halt itself\n"); 5416 return -EINVAL; 5417 } 5418 5419 return 0; 5420 } 5421 5422 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5423 { 5424 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5425 uint32_t tmp; 5426 int i; 5427 uint64_t addr; 5428 5429 /* Trigger an invalidation of the L1 instruction caches */ 5430 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5431 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5432 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5433 5434 /* Wait for invalidation complete */ 5435 for (i = 0; i < usec_timeout; i++) { 5436 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5437 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5438 INVALIDATE_CACHE_COMPLETE)) 5439 break; 5440 udelay(1); 5441 } 5442 5443 if (i >= usec_timeout) { 5444 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5445 return -EINVAL; 5446 } 5447 5448 /* Program me ucode address into intruction cache address register */ 5449 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5450 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5451 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5452 lower_32_bits(addr) & 0xFFFFF000); 5453 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5454 upper_32_bits(addr)); 5455 5456 return 0; 5457 } 5458 5459 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5460 { 5461 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5462 uint32_t tmp; 5463 int i; 5464 uint64_t addr; 5465 5466 /* Trigger an invalidation of the L1 instruction caches */ 5467 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5468 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5469 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5470 5471 /* Wait for invalidation complete */ 5472 for (i = 0; i < usec_timeout; i++) { 5473 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5474 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5475 INVALIDATE_CACHE_COMPLETE)) 5476 break; 5477 udelay(1); 5478 } 5479 5480 if (i >= usec_timeout) { 5481 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5482 return -EINVAL; 5483 } 5484 5485 /* Program ce ucode address into intruction cache address register */ 5486 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5487 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5488 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5489 lower_32_bits(addr) & 0xFFFFF000); 5490 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5491 upper_32_bits(addr)); 5492 5493 return 0; 5494 } 5495 5496 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5497 { 5498 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5499 uint32_t tmp; 5500 int i; 5501 uint64_t addr; 5502 5503 /* Trigger an invalidation of the L1 instruction caches */ 5504 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5505 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5506 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5507 5508 /* Wait for invalidation complete */ 5509 for (i = 0; i < usec_timeout; i++) { 5510 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5511 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5512 INVALIDATE_CACHE_COMPLETE)) 5513 break; 5514 udelay(1); 5515 } 5516 5517 if (i >= usec_timeout) { 5518 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5519 return -EINVAL; 5520 } 5521 5522 /* Program pfp ucode address into intruction cache address register */ 5523 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5524 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5525 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5526 lower_32_bits(addr) & 0xFFFFF000); 5527 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5528 upper_32_bits(addr)); 5529 5530 return 0; 5531 } 5532 5533 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5534 { 5535 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5536 uint32_t tmp; 5537 int i; 5538 uint64_t addr; 5539 5540 /* Trigger an invalidation of the L1 instruction caches */ 5541 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5542 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5543 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5544 5545 /* Wait for invalidation complete */ 5546 for (i = 0; i < usec_timeout; i++) { 5547 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5548 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5549 INVALIDATE_CACHE_COMPLETE)) 5550 break; 5551 udelay(1); 5552 } 5553 5554 if (i >= usec_timeout) { 5555 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5556 return -EINVAL; 5557 } 5558 5559 /* Program mec1 ucode address into intruction cache address register */ 5560 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5561 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5562 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5563 lower_32_bits(addr) & 0xFFFFF000); 5564 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5565 upper_32_bits(addr)); 5566 5567 return 0; 5568 } 5569 5570 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5571 { 5572 uint32_t cp_status; 5573 uint32_t bootload_status; 5574 int i, r; 5575 5576 for (i = 0; i < adev->usec_timeout; i++) { 5577 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5578 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5579 if ((cp_status == 0) && 5580 (REG_GET_FIELD(bootload_status, 5581 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5582 break; 5583 } 5584 udelay(1); 5585 } 5586 5587 if (i >= adev->usec_timeout) { 5588 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5589 return -ETIMEDOUT; 5590 } 5591 5592 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5593 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5594 if (r) 5595 return r; 5596 5597 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5598 if (r) 5599 return r; 5600 5601 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5602 if (r) 5603 return r; 5604 5605 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5606 if (r) 5607 return r; 5608 } 5609 5610 return 0; 5611 } 5612 5613 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5614 { 5615 int i; 5616 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5617 5618 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5619 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5620 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5621 5622 if (adev->asic_type == CHIP_NAVI12) { 5623 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5624 } else { 5625 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5626 } 5627 5628 for (i = 0; i < adev->usec_timeout; i++) { 5629 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5630 break; 5631 udelay(1); 5632 } 5633 5634 if (i >= adev->usec_timeout) 5635 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5636 5637 return 0; 5638 } 5639 5640 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5641 { 5642 int r; 5643 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5644 const __le32 *fw_data; 5645 unsigned i, fw_size; 5646 uint32_t tmp; 5647 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5648 5649 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5650 adev->gfx.pfp_fw->data; 5651 5652 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5653 5654 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5655 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5656 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5657 5658 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5659 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5660 &adev->gfx.pfp.pfp_fw_obj, 5661 &adev->gfx.pfp.pfp_fw_gpu_addr, 5662 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5663 if (r) { 5664 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5665 gfx_v10_0_pfp_fini(adev); 5666 return r; 5667 } 5668 5669 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5670 5671 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5672 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5673 5674 /* Trigger an invalidation of the L1 instruction caches */ 5675 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5676 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5677 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5678 5679 /* Wait for invalidation complete */ 5680 for (i = 0; i < usec_timeout; i++) { 5681 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5682 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5683 INVALIDATE_CACHE_COMPLETE)) 5684 break; 5685 udelay(1); 5686 } 5687 5688 if (i >= usec_timeout) { 5689 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5690 return -EINVAL; 5691 } 5692 5693 if (amdgpu_emu_mode == 1) 5694 adev->nbio.funcs->hdp_flush(adev, NULL); 5695 5696 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5697 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5698 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5699 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5700 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5701 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5702 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5703 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5704 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5705 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5706 5707 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5708 5709 for (i = 0; i < pfp_hdr->jt_size; i++) 5710 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5711 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5712 5713 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5714 5715 return 0; 5716 } 5717 5718 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5719 { 5720 int r; 5721 const struct gfx_firmware_header_v1_0 *ce_hdr; 5722 const __le32 *fw_data; 5723 unsigned i, fw_size; 5724 uint32_t tmp; 5725 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5726 5727 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5728 adev->gfx.ce_fw->data; 5729 5730 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5731 5732 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5733 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5734 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5735 5736 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5737 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5738 &adev->gfx.ce.ce_fw_obj, 5739 &adev->gfx.ce.ce_fw_gpu_addr, 5740 (void **)&adev->gfx.ce.ce_fw_ptr); 5741 if (r) { 5742 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5743 gfx_v10_0_ce_fini(adev); 5744 return r; 5745 } 5746 5747 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5748 5749 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5750 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5751 5752 /* Trigger an invalidation of the L1 instruction caches */ 5753 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5754 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5755 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5756 5757 /* Wait for invalidation complete */ 5758 for (i = 0; i < usec_timeout; i++) { 5759 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5760 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5761 INVALIDATE_CACHE_COMPLETE)) 5762 break; 5763 udelay(1); 5764 } 5765 5766 if (i >= usec_timeout) { 5767 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5768 return -EINVAL; 5769 } 5770 5771 if (amdgpu_emu_mode == 1) 5772 adev->nbio.funcs->hdp_flush(adev, NULL); 5773 5774 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5775 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5776 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5777 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5778 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5779 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5780 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5781 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5782 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5783 5784 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5785 5786 for (i = 0; i < ce_hdr->jt_size; i++) 5787 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5788 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5789 5790 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5791 5792 return 0; 5793 } 5794 5795 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5796 { 5797 int r; 5798 const struct gfx_firmware_header_v1_0 *me_hdr; 5799 const __le32 *fw_data; 5800 unsigned i, fw_size; 5801 uint32_t tmp; 5802 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5803 5804 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5805 adev->gfx.me_fw->data; 5806 5807 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5808 5809 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5810 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5811 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5812 5813 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5814 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5815 &adev->gfx.me.me_fw_obj, 5816 &adev->gfx.me.me_fw_gpu_addr, 5817 (void **)&adev->gfx.me.me_fw_ptr); 5818 if (r) { 5819 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5820 gfx_v10_0_me_fini(adev); 5821 return r; 5822 } 5823 5824 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5825 5826 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5827 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5828 5829 /* Trigger an invalidation of the L1 instruction caches */ 5830 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5831 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5832 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5833 5834 /* Wait for invalidation complete */ 5835 for (i = 0; i < usec_timeout; i++) { 5836 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5837 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5838 INVALIDATE_CACHE_COMPLETE)) 5839 break; 5840 udelay(1); 5841 } 5842 5843 if (i >= usec_timeout) { 5844 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5845 return -EINVAL; 5846 } 5847 5848 if (amdgpu_emu_mode == 1) 5849 adev->nbio.funcs->hdp_flush(adev, NULL); 5850 5851 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5852 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5853 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5854 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5855 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5856 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5857 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5858 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5859 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5860 5861 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5862 5863 for (i = 0; i < me_hdr->jt_size; i++) 5864 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5865 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5866 5867 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5868 5869 return 0; 5870 } 5871 5872 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5873 { 5874 int r; 5875 5876 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5877 return -EINVAL; 5878 5879 gfx_v10_0_cp_gfx_enable(adev, false); 5880 5881 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5882 if (r) { 5883 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5884 return r; 5885 } 5886 5887 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5888 if (r) { 5889 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5890 return r; 5891 } 5892 5893 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5894 if (r) { 5895 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5896 return r; 5897 } 5898 5899 return 0; 5900 } 5901 5902 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5903 { 5904 struct amdgpu_ring *ring; 5905 const struct cs_section_def *sect = NULL; 5906 const struct cs_extent_def *ext = NULL; 5907 int r, i; 5908 int ctx_reg_offset; 5909 5910 /* init the CP */ 5911 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5912 adev->gfx.config.max_hw_contexts - 1); 5913 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5914 5915 gfx_v10_0_cp_gfx_enable(adev, true); 5916 5917 ring = &adev->gfx.gfx_ring[0]; 5918 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5919 if (r) { 5920 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5921 return r; 5922 } 5923 5924 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5925 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5926 5927 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5928 amdgpu_ring_write(ring, 0x80000000); 5929 amdgpu_ring_write(ring, 0x80000000); 5930 5931 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5932 for (ext = sect->section; ext->extent != NULL; ++ext) { 5933 if (sect->id == SECT_CONTEXT) { 5934 amdgpu_ring_write(ring, 5935 PACKET3(PACKET3_SET_CONTEXT_REG, 5936 ext->reg_count)); 5937 amdgpu_ring_write(ring, ext->reg_index - 5938 PACKET3_SET_CONTEXT_REG_START); 5939 for (i = 0; i < ext->reg_count; i++) 5940 amdgpu_ring_write(ring, ext->extent[i]); 5941 } 5942 } 5943 } 5944 5945 ctx_reg_offset = 5946 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5947 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5948 amdgpu_ring_write(ring, ctx_reg_offset); 5949 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5950 5951 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5952 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5953 5954 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5955 amdgpu_ring_write(ring, 0); 5956 5957 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 5958 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 5959 amdgpu_ring_write(ring, 0x8000); 5960 amdgpu_ring_write(ring, 0x8000); 5961 5962 amdgpu_ring_commit(ring); 5963 5964 /* submit cs packet to copy state 0 to next available state */ 5965 if (adev->gfx.num_gfx_rings > 1) { 5966 /* maximum supported gfx ring is 2 */ 5967 ring = &adev->gfx.gfx_ring[1]; 5968 r = amdgpu_ring_alloc(ring, 2); 5969 if (r) { 5970 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5971 return r; 5972 } 5973 5974 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5975 amdgpu_ring_write(ring, 0); 5976 5977 amdgpu_ring_commit(ring); 5978 } 5979 return 0; 5980 } 5981 5982 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 5983 CP_PIPE_ID pipe) 5984 { 5985 u32 tmp; 5986 5987 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 5988 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 5989 5990 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 5991 } 5992 5993 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 5994 struct amdgpu_ring *ring) 5995 { 5996 u32 tmp; 5997 5998 if (!amdgpu_async_gfx_ring) { 5999 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6000 if (ring->use_doorbell) { 6001 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6002 DOORBELL_OFFSET, ring->doorbell_index); 6003 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6004 DOORBELL_EN, 1); 6005 } else { 6006 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6007 DOORBELL_EN, 0); 6008 } 6009 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6010 } 6011 switch (adev->asic_type) { 6012 case CHIP_SIENNA_CICHLID: 6013 case CHIP_NAVY_FLOUNDER: 6014 case CHIP_VANGOGH: 6015 case CHIP_DIMGREY_CAVEFISH: 6016 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6017 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6018 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6019 6020 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6021 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6022 break; 6023 default: 6024 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6025 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6026 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6027 6028 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6029 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6030 break; 6031 } 6032 } 6033 6034 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6035 { 6036 struct amdgpu_ring *ring; 6037 u32 tmp; 6038 u32 rb_bufsz; 6039 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6040 u32 i; 6041 6042 /* Set the write pointer delay */ 6043 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6044 6045 /* set the RB to use vmid 0 */ 6046 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6047 6048 /* Init gfx ring 0 for pipe 0 */ 6049 mutex_lock(&adev->srbm_mutex); 6050 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6051 6052 /* Set ring buffer size */ 6053 ring = &adev->gfx.gfx_ring[0]; 6054 rb_bufsz = order_base_2(ring->ring_size / 8); 6055 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6056 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6057 #ifdef __BIG_ENDIAN 6058 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6059 #endif 6060 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6061 6062 /* Initialize the ring buffer's write pointers */ 6063 ring->wptr = 0; 6064 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6065 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6066 6067 /* set the wb address wether it's enabled or not */ 6068 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6069 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6070 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6071 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6072 6073 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6074 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6075 lower_32_bits(wptr_gpu_addr)); 6076 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6077 upper_32_bits(wptr_gpu_addr)); 6078 6079 mdelay(1); 6080 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6081 6082 rb_addr = ring->gpu_addr >> 8; 6083 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6084 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6085 6086 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6087 6088 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6089 mutex_unlock(&adev->srbm_mutex); 6090 6091 /* Init gfx ring 1 for pipe 1 */ 6092 if (adev->gfx.num_gfx_rings > 1) { 6093 mutex_lock(&adev->srbm_mutex); 6094 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6095 /* maximum supported gfx ring is 2 */ 6096 ring = &adev->gfx.gfx_ring[1]; 6097 rb_bufsz = order_base_2(ring->ring_size / 8); 6098 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6099 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6100 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6101 /* Initialize the ring buffer's write pointers */ 6102 ring->wptr = 0; 6103 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6104 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6105 /* Set the wb address wether it's enabled or not */ 6106 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6107 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6108 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6109 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6110 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6111 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6112 lower_32_bits(wptr_gpu_addr)); 6113 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6114 upper_32_bits(wptr_gpu_addr)); 6115 6116 mdelay(1); 6117 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6118 6119 rb_addr = ring->gpu_addr >> 8; 6120 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6121 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6122 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6123 6124 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6125 mutex_unlock(&adev->srbm_mutex); 6126 } 6127 /* Switch to pipe 0 */ 6128 mutex_lock(&adev->srbm_mutex); 6129 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6130 mutex_unlock(&adev->srbm_mutex); 6131 6132 /* start the ring */ 6133 gfx_v10_0_cp_gfx_start(adev); 6134 6135 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6136 ring = &adev->gfx.gfx_ring[i]; 6137 ring->sched.ready = true; 6138 } 6139 6140 return 0; 6141 } 6142 6143 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6144 { 6145 if (enable) { 6146 switch (adev->asic_type) { 6147 case CHIP_SIENNA_CICHLID: 6148 case CHIP_NAVY_FLOUNDER: 6149 case CHIP_VANGOGH: 6150 case CHIP_DIMGREY_CAVEFISH: 6151 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6152 break; 6153 default: 6154 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6155 break; 6156 } 6157 } else { 6158 switch (adev->asic_type) { 6159 case CHIP_SIENNA_CICHLID: 6160 case CHIP_NAVY_FLOUNDER: 6161 case CHIP_VANGOGH: 6162 case CHIP_DIMGREY_CAVEFISH: 6163 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6164 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6165 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6166 break; 6167 default: 6168 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6169 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6170 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6171 break; 6172 } 6173 adev->gfx.kiq.ring.sched.ready = false; 6174 } 6175 udelay(50); 6176 } 6177 6178 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6179 { 6180 const struct gfx_firmware_header_v1_0 *mec_hdr; 6181 const __le32 *fw_data; 6182 unsigned i; 6183 u32 tmp; 6184 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6185 6186 if (!adev->gfx.mec_fw) 6187 return -EINVAL; 6188 6189 gfx_v10_0_cp_compute_enable(adev, false); 6190 6191 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6192 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6193 6194 fw_data = (const __le32 *) 6195 (adev->gfx.mec_fw->data + 6196 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6197 6198 /* Trigger an invalidation of the L1 instruction caches */ 6199 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6200 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6201 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6202 6203 /* Wait for invalidation complete */ 6204 for (i = 0; i < usec_timeout; i++) { 6205 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6206 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6207 INVALIDATE_CACHE_COMPLETE)) 6208 break; 6209 udelay(1); 6210 } 6211 6212 if (i >= usec_timeout) { 6213 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6214 return -EINVAL; 6215 } 6216 6217 if (amdgpu_emu_mode == 1) 6218 adev->nbio.funcs->hdp_flush(adev, NULL); 6219 6220 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6221 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6222 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6223 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6224 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6225 6226 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6227 0xFFFFF000); 6228 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6229 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6230 6231 /* MEC1 */ 6232 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6233 6234 for (i = 0; i < mec_hdr->jt_size; i++) 6235 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6236 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6237 6238 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6239 6240 /* 6241 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6242 * different microcode than MEC1. 6243 */ 6244 6245 return 0; 6246 } 6247 6248 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6249 { 6250 uint32_t tmp; 6251 struct amdgpu_device *adev = ring->adev; 6252 6253 /* tell RLC which is KIQ queue */ 6254 switch (adev->asic_type) { 6255 case CHIP_SIENNA_CICHLID: 6256 case CHIP_NAVY_FLOUNDER: 6257 case CHIP_VANGOGH: 6258 case CHIP_DIMGREY_CAVEFISH: 6259 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6260 tmp &= 0xffffff00; 6261 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6262 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6263 tmp |= 0x80; 6264 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6265 break; 6266 default: 6267 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6268 tmp &= 0xffffff00; 6269 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6270 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6271 tmp |= 0x80; 6272 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6273 break; 6274 } 6275 } 6276 6277 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6278 { 6279 struct amdgpu_device *adev = ring->adev; 6280 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6281 uint64_t hqd_gpu_addr, wb_gpu_addr; 6282 uint32_t tmp; 6283 uint32_t rb_bufsz; 6284 6285 /* set up gfx hqd wptr */ 6286 mqd->cp_gfx_hqd_wptr = 0; 6287 mqd->cp_gfx_hqd_wptr_hi = 0; 6288 6289 /* set the pointer to the MQD */ 6290 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6291 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6292 6293 /* set up mqd control */ 6294 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6295 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6296 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6297 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6298 mqd->cp_gfx_mqd_control = tmp; 6299 6300 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6301 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6302 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6303 mqd->cp_gfx_hqd_vmid = 0; 6304 6305 /* set up default queue priority level 6306 * 0x0 = low priority, 0x1 = high priority */ 6307 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6308 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6309 mqd->cp_gfx_hqd_queue_priority = tmp; 6310 6311 /* set up time quantum */ 6312 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6313 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6314 mqd->cp_gfx_hqd_quantum = tmp; 6315 6316 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6317 hqd_gpu_addr = ring->gpu_addr >> 8; 6318 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6319 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6320 6321 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6322 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6323 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6324 mqd->cp_gfx_hqd_rptr_addr_hi = 6325 upper_32_bits(wb_gpu_addr) & 0xffff; 6326 6327 /* set up rb_wptr_poll addr */ 6328 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6329 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6330 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6331 6332 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6333 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6334 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6335 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6336 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6337 #ifdef __BIG_ENDIAN 6338 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6339 #endif 6340 mqd->cp_gfx_hqd_cntl = tmp; 6341 6342 /* set up cp_doorbell_control */ 6343 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6344 if (ring->use_doorbell) { 6345 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6346 DOORBELL_OFFSET, ring->doorbell_index); 6347 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6348 DOORBELL_EN, 1); 6349 } else 6350 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6351 DOORBELL_EN, 0); 6352 mqd->cp_rb_doorbell_control = tmp; 6353 6354 /*if there are 2 gfx rings, set the lower doorbell range of the first ring, 6355 *otherwise the range of the second ring will override the first ring */ 6356 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6357 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6358 6359 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6360 ring->wptr = 0; 6361 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6362 6363 /* active the queue */ 6364 mqd->cp_gfx_hqd_active = 1; 6365 6366 return 0; 6367 } 6368 6369 #ifdef BRING_UP_DEBUG 6370 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6371 { 6372 struct amdgpu_device *adev = ring->adev; 6373 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6374 6375 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6376 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6377 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6378 6379 /* set GFX_MQD_BASE */ 6380 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6381 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6382 6383 /* set GFX_MQD_CONTROL */ 6384 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6385 6386 /* set GFX_HQD_VMID to 0 */ 6387 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6388 6389 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6390 mqd->cp_gfx_hqd_queue_priority); 6391 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6392 6393 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6394 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6395 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6396 6397 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6398 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6399 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6400 6401 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6402 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6403 6404 /* set RB_WPTR_POLL_ADDR */ 6405 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6406 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6407 6408 /* set RB_DOORBELL_CONTROL */ 6409 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6410 6411 /* active the queue */ 6412 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6413 6414 return 0; 6415 } 6416 #endif 6417 6418 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6419 { 6420 struct amdgpu_device *adev = ring->adev; 6421 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6422 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6423 6424 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6425 memset((void *)mqd, 0, sizeof(*mqd)); 6426 mutex_lock(&adev->srbm_mutex); 6427 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6428 gfx_v10_0_gfx_mqd_init(ring); 6429 #ifdef BRING_UP_DEBUG 6430 gfx_v10_0_gfx_queue_init_register(ring); 6431 #endif 6432 nv_grbm_select(adev, 0, 0, 0, 0); 6433 mutex_unlock(&adev->srbm_mutex); 6434 if (adev->gfx.me.mqd_backup[mqd_idx]) 6435 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6436 } else if (amdgpu_in_reset(adev)) { 6437 /* reset mqd with the backup copy */ 6438 if (adev->gfx.me.mqd_backup[mqd_idx]) 6439 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6440 /* reset the ring */ 6441 ring->wptr = 0; 6442 adev->wb.wb[ring->wptr_offs] = 0; 6443 amdgpu_ring_clear_ring(ring); 6444 #ifdef BRING_UP_DEBUG 6445 mutex_lock(&adev->srbm_mutex); 6446 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6447 gfx_v10_0_gfx_queue_init_register(ring); 6448 nv_grbm_select(adev, 0, 0, 0, 0); 6449 mutex_unlock(&adev->srbm_mutex); 6450 #endif 6451 } else { 6452 amdgpu_ring_clear_ring(ring); 6453 } 6454 6455 return 0; 6456 } 6457 6458 #ifndef BRING_UP_DEBUG 6459 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6460 { 6461 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6462 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6463 int r, i; 6464 6465 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6466 return -EINVAL; 6467 6468 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6469 adev->gfx.num_gfx_rings); 6470 if (r) { 6471 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6472 return r; 6473 } 6474 6475 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6476 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6477 6478 return amdgpu_ring_test_helper(kiq_ring); 6479 } 6480 #endif 6481 6482 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6483 { 6484 int r, i; 6485 struct amdgpu_ring *ring; 6486 6487 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6488 ring = &adev->gfx.gfx_ring[i]; 6489 6490 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6491 if (unlikely(r != 0)) 6492 goto done; 6493 6494 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6495 if (!r) { 6496 r = gfx_v10_0_gfx_init_queue(ring); 6497 amdgpu_bo_kunmap(ring->mqd_obj); 6498 ring->mqd_ptr = NULL; 6499 } 6500 amdgpu_bo_unreserve(ring->mqd_obj); 6501 if (r) 6502 goto done; 6503 } 6504 #ifndef BRING_UP_DEBUG 6505 r = gfx_v10_0_kiq_enable_kgq(adev); 6506 if (r) 6507 goto done; 6508 #endif 6509 r = gfx_v10_0_cp_gfx_start(adev); 6510 if (r) 6511 goto done; 6512 6513 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6514 ring = &adev->gfx.gfx_ring[i]; 6515 ring->sched.ready = true; 6516 } 6517 done: 6518 return r; 6519 } 6520 6521 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6522 { 6523 struct amdgpu_device *adev = ring->adev; 6524 6525 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6526 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 6527 ring->queue)) { 6528 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6529 mqd->cp_hqd_queue_priority = 6530 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6531 } 6532 } 6533 } 6534 6535 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6536 { 6537 struct amdgpu_device *adev = ring->adev; 6538 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6539 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6540 uint32_t tmp; 6541 6542 mqd->header = 0xC0310800; 6543 mqd->compute_pipelinestat_enable = 0x00000001; 6544 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6545 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6546 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6547 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6548 mqd->compute_misc_reserved = 0x00000003; 6549 6550 eop_base_addr = ring->eop_gpu_addr >> 8; 6551 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6552 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6553 6554 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6555 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6556 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6557 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6558 6559 mqd->cp_hqd_eop_control = tmp; 6560 6561 /* enable doorbell? */ 6562 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6563 6564 if (ring->use_doorbell) { 6565 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6566 DOORBELL_OFFSET, ring->doorbell_index); 6567 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6568 DOORBELL_EN, 1); 6569 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6570 DOORBELL_SOURCE, 0); 6571 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6572 DOORBELL_HIT, 0); 6573 } else { 6574 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6575 DOORBELL_EN, 0); 6576 } 6577 6578 mqd->cp_hqd_pq_doorbell_control = tmp; 6579 6580 /* disable the queue if it's active */ 6581 ring->wptr = 0; 6582 mqd->cp_hqd_dequeue_request = 0; 6583 mqd->cp_hqd_pq_rptr = 0; 6584 mqd->cp_hqd_pq_wptr_lo = 0; 6585 mqd->cp_hqd_pq_wptr_hi = 0; 6586 6587 /* set the pointer to the MQD */ 6588 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6589 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6590 6591 /* set MQD vmid to 0 */ 6592 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6593 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6594 mqd->cp_mqd_control = tmp; 6595 6596 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6597 hqd_gpu_addr = ring->gpu_addr >> 8; 6598 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6599 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6600 6601 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6602 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6603 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6604 (order_base_2(ring->ring_size / 4) - 1)); 6605 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6606 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6607 #ifdef __BIG_ENDIAN 6608 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6609 #endif 6610 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6611 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6612 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6613 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6614 mqd->cp_hqd_pq_control = tmp; 6615 6616 /* set the wb address whether it's enabled or not */ 6617 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6618 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6619 mqd->cp_hqd_pq_rptr_report_addr_hi = 6620 upper_32_bits(wb_gpu_addr) & 0xffff; 6621 6622 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6623 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6624 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6625 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6626 6627 tmp = 0; 6628 /* enable the doorbell if requested */ 6629 if (ring->use_doorbell) { 6630 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6631 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6632 DOORBELL_OFFSET, ring->doorbell_index); 6633 6634 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6635 DOORBELL_EN, 1); 6636 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6637 DOORBELL_SOURCE, 0); 6638 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6639 DOORBELL_HIT, 0); 6640 } 6641 6642 mqd->cp_hqd_pq_doorbell_control = tmp; 6643 6644 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6645 ring->wptr = 0; 6646 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6647 6648 /* set the vmid for the queue */ 6649 mqd->cp_hqd_vmid = 0; 6650 6651 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6652 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6653 mqd->cp_hqd_persistent_state = tmp; 6654 6655 /* set MIN_IB_AVAIL_SIZE */ 6656 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6657 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6658 mqd->cp_hqd_ib_control = tmp; 6659 6660 /* set static priority for a compute queue/ring */ 6661 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6662 6663 /* map_queues packet doesn't need activate the queue, 6664 * so only kiq need set this field. 6665 */ 6666 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6667 mqd->cp_hqd_active = 1; 6668 6669 return 0; 6670 } 6671 6672 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6673 { 6674 struct amdgpu_device *adev = ring->adev; 6675 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6676 int j; 6677 6678 /* inactivate the queue */ 6679 if (amdgpu_sriov_vf(adev)) 6680 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6681 6682 /* disable wptr polling */ 6683 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6684 6685 /* write the EOP addr */ 6686 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6687 mqd->cp_hqd_eop_base_addr_lo); 6688 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6689 mqd->cp_hqd_eop_base_addr_hi); 6690 6691 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6692 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6693 mqd->cp_hqd_eop_control); 6694 6695 /* enable doorbell? */ 6696 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6697 mqd->cp_hqd_pq_doorbell_control); 6698 6699 /* disable the queue if it's active */ 6700 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6701 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6702 for (j = 0; j < adev->usec_timeout; j++) { 6703 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6704 break; 6705 udelay(1); 6706 } 6707 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6708 mqd->cp_hqd_dequeue_request); 6709 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6710 mqd->cp_hqd_pq_rptr); 6711 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6712 mqd->cp_hqd_pq_wptr_lo); 6713 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6714 mqd->cp_hqd_pq_wptr_hi); 6715 } 6716 6717 /* set the pointer to the MQD */ 6718 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6719 mqd->cp_mqd_base_addr_lo); 6720 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6721 mqd->cp_mqd_base_addr_hi); 6722 6723 /* set MQD vmid to 0 */ 6724 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6725 mqd->cp_mqd_control); 6726 6727 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6728 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6729 mqd->cp_hqd_pq_base_lo); 6730 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6731 mqd->cp_hqd_pq_base_hi); 6732 6733 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6734 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6735 mqd->cp_hqd_pq_control); 6736 6737 /* set the wb address whether it's enabled or not */ 6738 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6739 mqd->cp_hqd_pq_rptr_report_addr_lo); 6740 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6741 mqd->cp_hqd_pq_rptr_report_addr_hi); 6742 6743 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6744 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6745 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6746 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6747 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6748 6749 /* enable the doorbell if requested */ 6750 if (ring->use_doorbell) { 6751 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6752 (adev->doorbell_index.kiq * 2) << 2); 6753 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6754 (adev->doorbell_index.userqueue_end * 2) << 2); 6755 } 6756 6757 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6758 mqd->cp_hqd_pq_doorbell_control); 6759 6760 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6761 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6762 mqd->cp_hqd_pq_wptr_lo); 6763 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6764 mqd->cp_hqd_pq_wptr_hi); 6765 6766 /* set the vmid for the queue */ 6767 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6768 6769 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6770 mqd->cp_hqd_persistent_state); 6771 6772 /* activate the queue */ 6773 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6774 mqd->cp_hqd_active); 6775 6776 if (ring->use_doorbell) 6777 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6778 6779 return 0; 6780 } 6781 6782 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6783 { 6784 struct amdgpu_device *adev = ring->adev; 6785 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6786 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6787 6788 gfx_v10_0_kiq_setting(ring); 6789 6790 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6791 /* reset MQD to a clean status */ 6792 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6793 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6794 6795 /* reset ring buffer */ 6796 ring->wptr = 0; 6797 amdgpu_ring_clear_ring(ring); 6798 6799 mutex_lock(&adev->srbm_mutex); 6800 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6801 gfx_v10_0_kiq_init_register(ring); 6802 nv_grbm_select(adev, 0, 0, 0, 0); 6803 mutex_unlock(&adev->srbm_mutex); 6804 } else { 6805 memset((void *)mqd, 0, sizeof(*mqd)); 6806 mutex_lock(&adev->srbm_mutex); 6807 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6808 gfx_v10_0_compute_mqd_init(ring); 6809 gfx_v10_0_kiq_init_register(ring); 6810 nv_grbm_select(adev, 0, 0, 0, 0); 6811 mutex_unlock(&adev->srbm_mutex); 6812 6813 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6814 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6815 } 6816 6817 return 0; 6818 } 6819 6820 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6821 { 6822 struct amdgpu_device *adev = ring->adev; 6823 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6824 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6825 6826 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6827 memset((void *)mqd, 0, sizeof(*mqd)); 6828 mutex_lock(&adev->srbm_mutex); 6829 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6830 gfx_v10_0_compute_mqd_init(ring); 6831 nv_grbm_select(adev, 0, 0, 0, 0); 6832 mutex_unlock(&adev->srbm_mutex); 6833 6834 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6835 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6836 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6837 /* reset MQD to a clean status */ 6838 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6839 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6840 6841 /* reset ring buffer */ 6842 ring->wptr = 0; 6843 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 6844 amdgpu_ring_clear_ring(ring); 6845 } else { 6846 amdgpu_ring_clear_ring(ring); 6847 } 6848 6849 return 0; 6850 } 6851 6852 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6853 { 6854 struct amdgpu_ring *ring; 6855 int r; 6856 6857 ring = &adev->gfx.kiq.ring; 6858 6859 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6860 if (unlikely(r != 0)) 6861 return r; 6862 6863 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6864 if (unlikely(r != 0)) 6865 return r; 6866 6867 gfx_v10_0_kiq_init_queue(ring); 6868 amdgpu_bo_kunmap(ring->mqd_obj); 6869 ring->mqd_ptr = NULL; 6870 amdgpu_bo_unreserve(ring->mqd_obj); 6871 ring->sched.ready = true; 6872 return 0; 6873 } 6874 6875 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6876 { 6877 struct amdgpu_ring *ring = NULL; 6878 int r = 0, i; 6879 6880 gfx_v10_0_cp_compute_enable(adev, true); 6881 6882 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6883 ring = &adev->gfx.compute_ring[i]; 6884 6885 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6886 if (unlikely(r != 0)) 6887 goto done; 6888 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6889 if (!r) { 6890 r = gfx_v10_0_kcq_init_queue(ring); 6891 amdgpu_bo_kunmap(ring->mqd_obj); 6892 ring->mqd_ptr = NULL; 6893 } 6894 amdgpu_bo_unreserve(ring->mqd_obj); 6895 if (r) 6896 goto done; 6897 } 6898 6899 r = amdgpu_gfx_enable_kcq(adev); 6900 done: 6901 return r; 6902 } 6903 6904 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6905 { 6906 int r, i; 6907 struct amdgpu_ring *ring; 6908 6909 if (!(adev->flags & AMD_IS_APU)) 6910 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6911 6912 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6913 /* legacy firmware loading */ 6914 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6915 if (r) 6916 return r; 6917 6918 r = gfx_v10_0_cp_compute_load_microcode(adev); 6919 if (r) 6920 return r; 6921 } 6922 6923 r = gfx_v10_0_kiq_resume(adev); 6924 if (r) 6925 return r; 6926 6927 r = gfx_v10_0_kcq_resume(adev); 6928 if (r) 6929 return r; 6930 6931 if (!amdgpu_async_gfx_ring) { 6932 r = gfx_v10_0_cp_gfx_resume(adev); 6933 if (r) 6934 return r; 6935 } else { 6936 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6937 if (r) 6938 return r; 6939 } 6940 6941 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6942 ring = &adev->gfx.gfx_ring[i]; 6943 r = amdgpu_ring_test_helper(ring); 6944 if (r) 6945 return r; 6946 } 6947 6948 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6949 ring = &adev->gfx.compute_ring[i]; 6950 r = amdgpu_ring_test_helper(ring); 6951 if (r) 6952 return r; 6953 } 6954 6955 return 0; 6956 } 6957 6958 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6959 { 6960 gfx_v10_0_cp_gfx_enable(adev, enable); 6961 gfx_v10_0_cp_compute_enable(adev, enable); 6962 } 6963 6964 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6965 { 6966 uint32_t data, pattern = 0xDEADBEEF; 6967 6968 /* check if mmVGT_ESGS_RING_SIZE_UMD 6969 * has been remapped to mmVGT_ESGS_RING_SIZE */ 6970 switch (adev->asic_type) { 6971 case CHIP_SIENNA_CICHLID: 6972 case CHIP_NAVY_FLOUNDER: 6973 case CHIP_DIMGREY_CAVEFISH: 6974 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6975 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6976 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6977 6978 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6979 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 6980 return true; 6981 } else { 6982 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6983 return false; 6984 } 6985 break; 6986 case CHIP_VANGOGH: 6987 return true; 6988 default: 6989 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6990 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 6991 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6992 6993 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 6994 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6995 return true; 6996 } else { 6997 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 6998 return false; 6999 } 7000 break; 7001 } 7002 } 7003 7004 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7005 { 7006 uint32_t data; 7007 7008 /* initialize cam_index to 0 7009 * index will auto-inc after each data writting */ 7010 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7011 7012 switch (adev->asic_type) { 7013 case CHIP_SIENNA_CICHLID: 7014 case CHIP_NAVY_FLOUNDER: 7015 case CHIP_VANGOGH: 7016 case CHIP_DIMGREY_CAVEFISH: 7017 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7018 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7019 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7020 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7021 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7022 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7023 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7024 7025 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7026 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7027 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7028 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7029 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7030 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7031 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7032 7033 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7034 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7035 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7036 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7037 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7038 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7039 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7040 7041 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7042 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7043 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7044 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7045 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7046 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7047 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7048 7049 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7050 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7051 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7052 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7053 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7054 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7055 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7056 7057 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7058 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7059 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7060 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7061 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7062 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7063 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7064 7065 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7066 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7067 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7068 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7069 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7070 break; 7071 default: 7072 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7073 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7074 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7075 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7076 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7077 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7078 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7079 7080 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7081 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7082 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7083 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7084 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7085 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7086 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7087 7088 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7089 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7090 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7091 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7092 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7093 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7094 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7095 7096 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7097 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7098 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7099 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7100 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7101 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7102 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7103 7104 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7105 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7106 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7107 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7108 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7109 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7110 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7111 7112 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7113 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7114 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7115 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7116 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7117 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7118 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7119 7120 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7121 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7122 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7123 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7124 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7125 break; 7126 } 7127 7128 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7129 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7130 } 7131 7132 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7133 { 7134 uint32_t data; 7135 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7136 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7137 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7138 7139 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7140 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7141 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7142 } 7143 7144 static int gfx_v10_0_hw_init(void *handle) 7145 { 7146 int r; 7147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7148 7149 if (!amdgpu_emu_mode) 7150 gfx_v10_0_init_golden_registers(adev); 7151 7152 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7153 /** 7154 * For gfx 10, rlc firmware loading relies on smu firmware is 7155 * loaded firstly, so in direct type, it has to load smc ucode 7156 * here before rlc. 7157 */ 7158 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) { 7159 r = smu_load_microcode(&adev->smu); 7160 if (r) 7161 return r; 7162 7163 r = smu_check_fw_status(&adev->smu); 7164 if (r) { 7165 pr_err("SMC firmware status is not correct\n"); 7166 return r; 7167 } 7168 } 7169 gfx_v10_0_disable_gpa_mode(adev); 7170 } 7171 7172 /* if GRBM CAM not remapped, set up the remapping */ 7173 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7174 gfx_v10_0_setup_grbm_cam_remapping(adev); 7175 7176 gfx_v10_0_constants_init(adev); 7177 7178 r = gfx_v10_0_rlc_resume(adev); 7179 if (r) 7180 return r; 7181 7182 /* 7183 * init golden registers and rlc resume may override some registers, 7184 * reconfig them here 7185 */ 7186 gfx_v10_0_tcp_harvest(adev); 7187 7188 r = gfx_v10_0_cp_resume(adev); 7189 if (r) 7190 return r; 7191 7192 if (adev->asic_type == CHIP_SIENNA_CICHLID) 7193 gfx_v10_3_program_pbb_mode(adev); 7194 7195 return r; 7196 } 7197 7198 #ifndef BRING_UP_DEBUG 7199 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7200 { 7201 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7202 struct amdgpu_ring *kiq_ring = &kiq->ring; 7203 int i; 7204 7205 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7206 return -EINVAL; 7207 7208 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7209 adev->gfx.num_gfx_rings)) 7210 return -ENOMEM; 7211 7212 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7213 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7214 PREEMPT_QUEUES, 0, 0); 7215 7216 return amdgpu_ring_test_helper(kiq_ring); 7217 } 7218 #endif 7219 7220 static int gfx_v10_0_hw_fini(void *handle) 7221 { 7222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7223 int r; 7224 uint32_t tmp; 7225 7226 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7227 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7228 7229 if (!adev->in_pci_err_recovery) { 7230 #ifndef BRING_UP_DEBUG 7231 if (amdgpu_async_gfx_ring) { 7232 r = gfx_v10_0_kiq_disable_kgq(adev); 7233 if (r) 7234 DRM_ERROR("KGQ disable failed\n"); 7235 } 7236 #endif 7237 if (amdgpu_gfx_disable_kcq(adev)) 7238 DRM_ERROR("KCQ disable failed\n"); 7239 } 7240 7241 if (amdgpu_sriov_vf(adev)) { 7242 gfx_v10_0_cp_gfx_enable(adev, false); 7243 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7244 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7245 tmp &= 0xffffff00; 7246 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7247 7248 return 0; 7249 } 7250 gfx_v10_0_cp_enable(adev, false); 7251 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7252 7253 return 0; 7254 } 7255 7256 static int gfx_v10_0_suspend(void *handle) 7257 { 7258 return gfx_v10_0_hw_fini(handle); 7259 } 7260 7261 static int gfx_v10_0_resume(void *handle) 7262 { 7263 return gfx_v10_0_hw_init(handle); 7264 } 7265 7266 static bool gfx_v10_0_is_idle(void *handle) 7267 { 7268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7269 7270 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7271 GRBM_STATUS, GUI_ACTIVE)) 7272 return false; 7273 else 7274 return true; 7275 } 7276 7277 static int gfx_v10_0_wait_for_idle(void *handle) 7278 { 7279 unsigned i; 7280 u32 tmp; 7281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7282 7283 for (i = 0; i < adev->usec_timeout; i++) { 7284 /* read MC_STATUS */ 7285 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7286 GRBM_STATUS__GUI_ACTIVE_MASK; 7287 7288 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7289 return 0; 7290 udelay(1); 7291 } 7292 return -ETIMEDOUT; 7293 } 7294 7295 static int gfx_v10_0_soft_reset(void *handle) 7296 { 7297 u32 grbm_soft_reset = 0; 7298 u32 tmp; 7299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7300 7301 /* GRBM_STATUS */ 7302 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7303 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7304 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7305 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7306 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7307 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7308 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7309 GRBM_SOFT_RESET, SOFT_RESET_CP, 7310 1); 7311 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7312 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7313 1); 7314 } 7315 7316 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7317 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7318 GRBM_SOFT_RESET, SOFT_RESET_CP, 7319 1); 7320 } 7321 7322 /* GRBM_STATUS2 */ 7323 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7324 switch (adev->asic_type) { 7325 case CHIP_SIENNA_CICHLID: 7326 case CHIP_NAVY_FLOUNDER: 7327 case CHIP_VANGOGH: 7328 case CHIP_DIMGREY_CAVEFISH: 7329 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7330 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7331 GRBM_SOFT_RESET, 7332 SOFT_RESET_RLC, 7333 1); 7334 break; 7335 default: 7336 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7337 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7338 GRBM_SOFT_RESET, 7339 SOFT_RESET_RLC, 7340 1); 7341 break; 7342 } 7343 7344 if (grbm_soft_reset) { 7345 /* stop the rlc */ 7346 gfx_v10_0_rlc_stop(adev); 7347 7348 /* Disable GFX parsing/prefetching */ 7349 gfx_v10_0_cp_gfx_enable(adev, false); 7350 7351 /* Disable MEC parsing/prefetching */ 7352 gfx_v10_0_cp_compute_enable(adev, false); 7353 7354 if (grbm_soft_reset) { 7355 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7356 tmp |= grbm_soft_reset; 7357 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7358 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7359 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7360 7361 udelay(50); 7362 7363 tmp &= ~grbm_soft_reset; 7364 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7365 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7366 } 7367 7368 /* Wait a little for things to settle down */ 7369 udelay(50); 7370 } 7371 return 0; 7372 } 7373 7374 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7375 { 7376 uint64_t clock; 7377 7378 amdgpu_gfx_off_ctrl(adev, false); 7379 mutex_lock(&adev->gfx.gpu_clock_mutex); 7380 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 7381 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 7382 mutex_unlock(&adev->gfx.gpu_clock_mutex); 7383 amdgpu_gfx_off_ctrl(adev, true); 7384 return clock; 7385 } 7386 7387 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7388 uint32_t vmid, 7389 uint32_t gds_base, uint32_t gds_size, 7390 uint32_t gws_base, uint32_t gws_size, 7391 uint32_t oa_base, uint32_t oa_size) 7392 { 7393 struct amdgpu_device *adev = ring->adev; 7394 7395 /* GDS Base */ 7396 gfx_v10_0_write_data_to_reg(ring, 0, false, 7397 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7398 gds_base); 7399 7400 /* GDS Size */ 7401 gfx_v10_0_write_data_to_reg(ring, 0, false, 7402 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7403 gds_size); 7404 7405 /* GWS */ 7406 gfx_v10_0_write_data_to_reg(ring, 0, false, 7407 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7408 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7409 7410 /* OA */ 7411 gfx_v10_0_write_data_to_reg(ring, 0, false, 7412 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7413 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7414 } 7415 7416 static int gfx_v10_0_early_init(void *handle) 7417 { 7418 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7419 7420 switch (adev->asic_type) { 7421 case CHIP_NAVI10: 7422 case CHIP_NAVI14: 7423 case CHIP_NAVI12: 7424 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7425 break; 7426 case CHIP_SIENNA_CICHLID: 7427 case CHIP_NAVY_FLOUNDER: 7428 case CHIP_VANGOGH: 7429 case CHIP_DIMGREY_CAVEFISH: 7430 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7431 break; 7432 default: 7433 break; 7434 } 7435 7436 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7437 AMDGPU_MAX_COMPUTE_RINGS); 7438 7439 gfx_v10_0_set_kiq_pm4_funcs(adev); 7440 gfx_v10_0_set_ring_funcs(adev); 7441 gfx_v10_0_set_irq_funcs(adev); 7442 gfx_v10_0_set_gds_init(adev); 7443 gfx_v10_0_set_rlc_funcs(adev); 7444 7445 return 0; 7446 } 7447 7448 static int gfx_v10_0_late_init(void *handle) 7449 { 7450 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7451 int r; 7452 7453 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7454 if (r) 7455 return r; 7456 7457 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7458 if (r) 7459 return r; 7460 7461 return 0; 7462 } 7463 7464 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7465 { 7466 uint32_t rlc_cntl; 7467 7468 /* if RLC is not enabled, do nothing */ 7469 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7470 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7471 } 7472 7473 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7474 { 7475 uint32_t data; 7476 unsigned i; 7477 7478 data = RLC_SAFE_MODE__CMD_MASK; 7479 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7480 7481 switch (adev->asic_type) { 7482 case CHIP_SIENNA_CICHLID: 7483 case CHIP_NAVY_FLOUNDER: 7484 case CHIP_VANGOGH: 7485 case CHIP_DIMGREY_CAVEFISH: 7486 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7487 7488 /* wait for RLC_SAFE_MODE */ 7489 for (i = 0; i < adev->usec_timeout; i++) { 7490 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7491 RLC_SAFE_MODE, CMD)) 7492 break; 7493 udelay(1); 7494 } 7495 break; 7496 default: 7497 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7498 7499 /* wait for RLC_SAFE_MODE */ 7500 for (i = 0; i < adev->usec_timeout; i++) { 7501 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7502 RLC_SAFE_MODE, CMD)) 7503 break; 7504 udelay(1); 7505 } 7506 break; 7507 } 7508 } 7509 7510 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7511 { 7512 uint32_t data; 7513 7514 data = RLC_SAFE_MODE__CMD_MASK; 7515 switch (adev->asic_type) { 7516 case CHIP_SIENNA_CICHLID: 7517 case CHIP_NAVY_FLOUNDER: 7518 case CHIP_VANGOGH: 7519 case CHIP_DIMGREY_CAVEFISH: 7520 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7521 break; 7522 default: 7523 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7524 break; 7525 } 7526 } 7527 7528 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7529 bool enable) 7530 { 7531 uint32_t data, def; 7532 7533 /* It is disabled by HW by default */ 7534 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7535 /* 0 - Disable some blocks' MGCG */ 7536 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7537 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7538 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7539 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7540 7541 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7542 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7543 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7544 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7545 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7546 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7547 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7548 7549 if (def != data) 7550 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7551 7552 /* MGLS is a global flag to control all MGLS in GFX */ 7553 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7554 /* 2 - RLC memory Light sleep */ 7555 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7556 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7557 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7558 if (def != data) 7559 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7560 } 7561 /* 3 - CP memory Light sleep */ 7562 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7563 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7564 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7565 if (def != data) 7566 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7567 } 7568 } 7569 } else { 7570 /* 1 - MGCG_OVERRIDE */ 7571 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7572 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7573 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7574 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7575 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 7576 if (def != data) 7577 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7578 7579 /* 2 - disable MGLS in CP */ 7580 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7581 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7582 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7583 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7584 } 7585 7586 /* 3 - disable MGLS in RLC */ 7587 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7588 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7589 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7590 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7591 } 7592 7593 } 7594 } 7595 7596 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7597 bool enable) 7598 { 7599 uint32_t data, def; 7600 7601 /* Enable 3D CGCG/CGLS */ 7602 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 7603 /* write cmd to clear cgcg/cgls ov */ 7604 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7605 /* unset CGCG override */ 7606 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7607 /* update CGCG and CGLS override bits */ 7608 if (def != data) 7609 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7610 /* enable 3Dcgcg FSM(0x0000363f) */ 7611 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7612 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7613 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7614 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7615 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7616 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7617 if (def != data) 7618 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7619 7620 /* set IDLE_POLL_COUNT(0x00900100) */ 7621 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7622 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7623 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7624 if (def != data) 7625 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7626 } else { 7627 /* Disable CGCG/CGLS */ 7628 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7629 /* disable cgcg, cgls should be disabled */ 7630 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 7631 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 7632 /* disable cgcg and cgls in FSM */ 7633 if (def != data) 7634 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7635 } 7636 } 7637 7638 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7639 bool enable) 7640 { 7641 uint32_t def, data; 7642 7643 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 7644 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7645 /* unset CGCG override */ 7646 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7647 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7648 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7649 else 7650 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7651 /* update CGCG and CGLS override bits */ 7652 if (def != data) 7653 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7654 7655 /* enable cgcg FSM(0x0000363F) */ 7656 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7657 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7658 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7659 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7660 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7661 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7662 if (def != data) 7663 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7664 7665 /* set IDLE_POLL_COUNT(0x00900100) */ 7666 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7667 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7668 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7669 if (def != data) 7670 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7671 } else { 7672 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7673 /* reset CGCG/CGLS bits */ 7674 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 7675 /* disable cgcg and cgls in FSM */ 7676 if (def != data) 7677 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7678 } 7679 } 7680 7681 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7682 bool enable) 7683 { 7684 uint32_t def, data; 7685 7686 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) { 7687 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7688 /* unset FGCG override */ 7689 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7690 /* update FGCG override bits */ 7691 if (def != data) 7692 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7693 7694 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7695 /* unset RLC SRAM CLK GATER override */ 7696 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7697 /* update RLC SRAM CLK GATER override bits */ 7698 if (def != data) 7699 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7700 } else { 7701 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7702 /* reset FGCG bits */ 7703 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7704 /* disable FGCG*/ 7705 if (def != data) 7706 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7707 7708 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7709 /* reset RLC SRAM CLK GATER bits */ 7710 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7711 /* disable RLC SRAM CLK*/ 7712 if (def != data) 7713 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7714 } 7715 } 7716 7717 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7718 bool enable) 7719 { 7720 amdgpu_gfx_rlc_enter_safe_mode(adev); 7721 7722 if (enable) { 7723 /* enable FGCG firstly*/ 7724 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7725 /* CGCG/CGLS should be enabled after MGCG/MGLS 7726 * === MGCG + MGLS === 7727 */ 7728 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7729 /* === CGCG /CGLS for GFX 3D Only === */ 7730 gfx_v10_0_update_3d_clock_gating(adev, enable); 7731 /* === CGCG + CGLS === */ 7732 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7733 } else { 7734 /* CGCG/CGLS should be disabled before MGCG/MGLS 7735 * === CGCG + CGLS === 7736 */ 7737 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7738 /* === CGCG /CGLS for GFX 3D Only === */ 7739 gfx_v10_0_update_3d_clock_gating(adev, enable); 7740 /* === MGCG + MGLS === */ 7741 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7742 /* disable fgcg at last*/ 7743 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7744 } 7745 7746 if (adev->cg_flags & 7747 (AMD_CG_SUPPORT_GFX_MGCG | 7748 AMD_CG_SUPPORT_GFX_CGLS | 7749 AMD_CG_SUPPORT_GFX_CGCG | 7750 AMD_CG_SUPPORT_GFX_3D_CGCG | 7751 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7752 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7753 7754 amdgpu_gfx_rlc_exit_safe_mode(adev); 7755 7756 return 0; 7757 } 7758 7759 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 7760 { 7761 u32 reg, data; 7762 7763 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7764 if (amdgpu_sriov_is_pp_one_vf(adev)) 7765 data = RREG32_NO_KIQ(reg); 7766 else 7767 data = RREG32(reg); 7768 7769 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7770 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7771 7772 if (amdgpu_sriov_is_pp_one_vf(adev)) 7773 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7774 else 7775 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7776 } 7777 7778 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7779 uint32_t offset, 7780 struct soc15_reg_rlcg *entries, int arr_size) 7781 { 7782 int i; 7783 uint32_t reg; 7784 7785 if (!entries) 7786 return false; 7787 7788 for (i = 0; i < arr_size; i++) { 7789 const struct soc15_reg_rlcg *entry; 7790 7791 entry = &entries[i]; 7792 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7793 if (offset == reg) 7794 return true; 7795 } 7796 7797 return false; 7798 } 7799 7800 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7801 { 7802 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7803 } 7804 7805 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7806 { 7807 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7808 7809 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7810 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7811 else 7812 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7813 7814 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7815 } 7816 7817 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7818 { 7819 amdgpu_gfx_rlc_enter_safe_mode(adev); 7820 7821 gfx_v10_cntl_power_gating(adev, enable); 7822 7823 amdgpu_gfx_rlc_exit_safe_mode(adev); 7824 } 7825 7826 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 7827 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7828 .set_safe_mode = gfx_v10_0_set_safe_mode, 7829 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7830 .init = gfx_v10_0_rlc_init, 7831 .get_csb_size = gfx_v10_0_get_csb_size, 7832 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7833 .resume = gfx_v10_0_rlc_resume, 7834 .stop = gfx_v10_0_rlc_stop, 7835 .reset = gfx_v10_0_rlc_reset, 7836 .start = gfx_v10_0_rlc_start, 7837 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7838 }; 7839 7840 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 7841 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7842 .set_safe_mode = gfx_v10_0_set_safe_mode, 7843 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7844 .init = gfx_v10_0_rlc_init, 7845 .get_csb_size = gfx_v10_0_get_csb_size, 7846 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7847 .resume = gfx_v10_0_rlc_resume, 7848 .stop = gfx_v10_0_rlc_stop, 7849 .reset = gfx_v10_0_rlc_reset, 7850 .start = gfx_v10_0_rlc_start, 7851 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7852 .rlcg_wreg = gfx_v10_rlcg_wreg, 7853 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 7854 }; 7855 7856 static int gfx_v10_0_set_powergating_state(void *handle, 7857 enum amd_powergating_state state) 7858 { 7859 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7860 bool enable = (state == AMD_PG_STATE_GATE); 7861 7862 if (amdgpu_sriov_vf(adev)) 7863 return 0; 7864 7865 switch (adev->asic_type) { 7866 case CHIP_NAVI10: 7867 case CHIP_NAVI14: 7868 case CHIP_NAVI12: 7869 case CHIP_SIENNA_CICHLID: 7870 case CHIP_NAVY_FLOUNDER: 7871 case CHIP_DIMGREY_CAVEFISH: 7872 amdgpu_gfx_off_ctrl(adev, enable); 7873 break; 7874 case CHIP_VANGOGH: 7875 gfx_v10_cntl_pg(adev, enable); 7876 break; 7877 default: 7878 break; 7879 } 7880 return 0; 7881 } 7882 7883 static int gfx_v10_0_set_clockgating_state(void *handle, 7884 enum amd_clockgating_state state) 7885 { 7886 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7887 7888 if (amdgpu_sriov_vf(adev)) 7889 return 0; 7890 7891 switch (adev->asic_type) { 7892 case CHIP_NAVI10: 7893 case CHIP_NAVI14: 7894 case CHIP_NAVI12: 7895 case CHIP_SIENNA_CICHLID: 7896 case CHIP_NAVY_FLOUNDER: 7897 case CHIP_VANGOGH: 7898 case CHIP_DIMGREY_CAVEFISH: 7899 gfx_v10_0_update_gfx_clock_gating(adev, 7900 state == AMD_CG_STATE_GATE); 7901 break; 7902 default: 7903 break; 7904 } 7905 return 0; 7906 } 7907 7908 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 7909 { 7910 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7911 int data; 7912 7913 /* AMD_CG_SUPPORT_GFX_FGCG */ 7914 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7915 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 7916 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 7917 7918 /* AMD_CG_SUPPORT_GFX_MGCG */ 7919 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7920 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 7921 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 7922 7923 /* AMD_CG_SUPPORT_GFX_CGCG */ 7924 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 7925 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 7926 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 7927 7928 /* AMD_CG_SUPPORT_GFX_CGLS */ 7929 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 7930 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 7931 7932 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 7933 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 7934 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 7935 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 7936 7937 /* AMD_CG_SUPPORT_GFX_CP_LS */ 7938 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 7939 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 7940 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 7941 7942 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 7943 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 7944 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 7945 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 7946 7947 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 7948 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 7949 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 7950 } 7951 7952 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 7953 { 7954 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 7955 } 7956 7957 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 7958 { 7959 struct amdgpu_device *adev = ring->adev; 7960 u64 wptr; 7961 7962 /* XXX check if swapping is necessary on BE */ 7963 if (ring->use_doorbell) { 7964 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 7965 } else { 7966 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 7967 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 7968 } 7969 7970 return wptr; 7971 } 7972 7973 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 7974 { 7975 struct amdgpu_device *adev = ring->adev; 7976 7977 if (ring->use_doorbell) { 7978 /* XXX check if swapping is necessary on BE */ 7979 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 7980 WDOORBELL64(ring->doorbell_index, ring->wptr); 7981 } else { 7982 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 7983 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 7984 } 7985 } 7986 7987 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 7988 { 7989 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 7990 } 7991 7992 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 7993 { 7994 u64 wptr; 7995 7996 /* XXX check if swapping is necessary on BE */ 7997 if (ring->use_doorbell) 7998 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 7999 else 8000 BUG(); 8001 return wptr; 8002 } 8003 8004 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8005 { 8006 struct amdgpu_device *adev = ring->adev; 8007 8008 /* XXX check if swapping is necessary on BE */ 8009 if (ring->use_doorbell) { 8010 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8011 WDOORBELL64(ring->doorbell_index, ring->wptr); 8012 } else { 8013 BUG(); /* only DOORBELL method supported on gfx10 now */ 8014 } 8015 } 8016 8017 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8018 { 8019 struct amdgpu_device *adev = ring->adev; 8020 u32 ref_and_mask, reg_mem_engine; 8021 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8022 8023 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8024 switch (ring->me) { 8025 case 1: 8026 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8027 break; 8028 case 2: 8029 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8030 break; 8031 default: 8032 return; 8033 } 8034 reg_mem_engine = 0; 8035 } else { 8036 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8037 reg_mem_engine = 1; /* pfp */ 8038 } 8039 8040 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8041 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8042 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8043 ref_and_mask, ref_and_mask, 0x20); 8044 } 8045 8046 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8047 struct amdgpu_job *job, 8048 struct amdgpu_ib *ib, 8049 uint32_t flags) 8050 { 8051 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8052 u32 header, control = 0; 8053 8054 if (ib->flags & AMDGPU_IB_FLAG_CE) 8055 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8056 else 8057 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8058 8059 control |= ib->length_dw | (vmid << 24); 8060 8061 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8062 control |= INDIRECT_BUFFER_PRE_ENB(1); 8063 8064 if (flags & AMDGPU_IB_PREEMPTED) 8065 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8066 8067 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8068 gfx_v10_0_ring_emit_de_meta(ring, 8069 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8070 } 8071 8072 amdgpu_ring_write(ring, header); 8073 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8074 amdgpu_ring_write(ring, 8075 #ifdef __BIG_ENDIAN 8076 (2 << 0) | 8077 #endif 8078 lower_32_bits(ib->gpu_addr)); 8079 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8080 amdgpu_ring_write(ring, control); 8081 } 8082 8083 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8084 struct amdgpu_job *job, 8085 struct amdgpu_ib *ib, 8086 uint32_t flags) 8087 { 8088 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8089 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8090 8091 /* Currently, there is a high possibility to get wave ID mismatch 8092 * between ME and GDS, leading to a hw deadlock, because ME generates 8093 * different wave IDs than the GDS expects. This situation happens 8094 * randomly when at least 5 compute pipes use GDS ordered append. 8095 * The wave IDs generated by ME are also wrong after suspend/resume. 8096 * Those are probably bugs somewhere else in the kernel driver. 8097 * 8098 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8099 * GDS to 0 for this ring (me/pipe). 8100 */ 8101 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8102 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8103 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8104 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8105 } 8106 8107 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8108 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8109 amdgpu_ring_write(ring, 8110 #ifdef __BIG_ENDIAN 8111 (2 << 0) | 8112 #endif 8113 lower_32_bits(ib->gpu_addr)); 8114 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8115 amdgpu_ring_write(ring, control); 8116 } 8117 8118 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8119 u64 seq, unsigned flags) 8120 { 8121 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8122 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8123 8124 /* RELEASE_MEM - flush caches, send int */ 8125 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8126 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8127 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8128 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8129 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8130 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8131 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8132 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8133 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8134 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8135 8136 /* 8137 * the address should be Qword aligned if 64bit write, Dword 8138 * aligned if only send 32bit data low (discard data high) 8139 */ 8140 if (write64bit) 8141 BUG_ON(addr & 0x7); 8142 else 8143 BUG_ON(addr & 0x3); 8144 amdgpu_ring_write(ring, lower_32_bits(addr)); 8145 amdgpu_ring_write(ring, upper_32_bits(addr)); 8146 amdgpu_ring_write(ring, lower_32_bits(seq)); 8147 amdgpu_ring_write(ring, upper_32_bits(seq)); 8148 amdgpu_ring_write(ring, 0); 8149 } 8150 8151 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8152 { 8153 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8154 uint32_t seq = ring->fence_drv.sync_seq; 8155 uint64_t addr = ring->fence_drv.gpu_addr; 8156 8157 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8158 upper_32_bits(addr), seq, 0xffffffff, 4); 8159 } 8160 8161 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8162 unsigned vmid, uint64_t pd_addr) 8163 { 8164 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8165 8166 /* compute doesn't have PFP */ 8167 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8168 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8169 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8170 amdgpu_ring_write(ring, 0x0); 8171 } 8172 } 8173 8174 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8175 u64 seq, unsigned int flags) 8176 { 8177 struct amdgpu_device *adev = ring->adev; 8178 8179 /* we only allocate 32bit for each seq wb address */ 8180 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8181 8182 /* write fence seq to the "addr" */ 8183 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8184 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8185 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8186 amdgpu_ring_write(ring, lower_32_bits(addr)); 8187 amdgpu_ring_write(ring, upper_32_bits(addr)); 8188 amdgpu_ring_write(ring, lower_32_bits(seq)); 8189 8190 if (flags & AMDGPU_FENCE_FLAG_INT) { 8191 /* set register to trigger INT */ 8192 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8193 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8194 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8195 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8196 amdgpu_ring_write(ring, 0); 8197 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8198 } 8199 } 8200 8201 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8202 { 8203 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8204 amdgpu_ring_write(ring, 0); 8205 } 8206 8207 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8208 uint32_t flags) 8209 { 8210 uint32_t dw2 = 0; 8211 8212 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8213 gfx_v10_0_ring_emit_ce_meta(ring, 8214 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8215 8216 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8217 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8218 /* set load_global_config & load_global_uconfig */ 8219 dw2 |= 0x8001; 8220 /* set load_cs_sh_regs */ 8221 dw2 |= 0x01000000; 8222 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8223 dw2 |= 0x10002; 8224 8225 /* set load_ce_ram if preamble presented */ 8226 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8227 dw2 |= 0x10000000; 8228 } else { 8229 /* still load_ce_ram if this is the first time preamble presented 8230 * although there is no context switch happens. 8231 */ 8232 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8233 dw2 |= 0x10000000; 8234 } 8235 8236 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8237 amdgpu_ring_write(ring, dw2); 8238 amdgpu_ring_write(ring, 0); 8239 } 8240 8241 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8242 { 8243 unsigned ret; 8244 8245 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8246 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8247 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8248 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8249 ret = ring->wptr & ring->buf_mask; 8250 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8251 8252 return ret; 8253 } 8254 8255 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8256 { 8257 unsigned cur; 8258 BUG_ON(offset > ring->buf_mask); 8259 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8260 8261 cur = (ring->wptr - 1) & ring->buf_mask; 8262 if (likely(cur > offset)) 8263 ring->ring[offset] = cur - offset; 8264 else 8265 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8266 } 8267 8268 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8269 { 8270 int i, r = 0; 8271 struct amdgpu_device *adev = ring->adev; 8272 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8273 struct amdgpu_ring *kiq_ring = &kiq->ring; 8274 unsigned long flags; 8275 8276 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8277 return -EINVAL; 8278 8279 spin_lock_irqsave(&kiq->ring_lock, flags); 8280 8281 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8282 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8283 return -ENOMEM; 8284 } 8285 8286 /* assert preemption condition */ 8287 amdgpu_ring_set_preempt_cond_exec(ring, false); 8288 8289 /* assert IB preemption, emit the trailing fence */ 8290 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8291 ring->trail_fence_gpu_addr, 8292 ++ring->trail_seq); 8293 amdgpu_ring_commit(kiq_ring); 8294 8295 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8296 8297 /* poll the trailing fence */ 8298 for (i = 0; i < adev->usec_timeout; i++) { 8299 if (ring->trail_seq == 8300 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8301 break; 8302 udelay(1); 8303 } 8304 8305 if (i >= adev->usec_timeout) { 8306 r = -EINVAL; 8307 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8308 } 8309 8310 /* deassert preemption condition */ 8311 amdgpu_ring_set_preempt_cond_exec(ring, true); 8312 return r; 8313 } 8314 8315 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8316 { 8317 struct amdgpu_device *adev = ring->adev; 8318 struct v10_ce_ib_state ce_payload = {0}; 8319 uint64_t csa_addr; 8320 int cnt; 8321 8322 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8323 csa_addr = amdgpu_csa_vaddr(ring->adev); 8324 8325 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8326 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8327 WRITE_DATA_DST_SEL(8) | 8328 WR_CONFIRM) | 8329 WRITE_DATA_CACHE_POLICY(0)); 8330 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8331 offsetof(struct v10_gfx_meta_data, ce_payload))); 8332 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8333 offsetof(struct v10_gfx_meta_data, ce_payload))); 8334 8335 if (resume) 8336 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8337 offsetof(struct v10_gfx_meta_data, 8338 ce_payload), 8339 sizeof(ce_payload) >> 2); 8340 else 8341 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8342 sizeof(ce_payload) >> 2); 8343 } 8344 8345 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8346 { 8347 struct amdgpu_device *adev = ring->adev; 8348 struct v10_de_ib_state de_payload = {0}; 8349 uint64_t csa_addr, gds_addr; 8350 int cnt; 8351 8352 csa_addr = amdgpu_csa_vaddr(ring->adev); 8353 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8354 PAGE_SIZE); 8355 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8356 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8357 8358 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8359 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8360 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8361 WRITE_DATA_DST_SEL(8) | 8362 WR_CONFIRM) | 8363 WRITE_DATA_CACHE_POLICY(0)); 8364 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8365 offsetof(struct v10_gfx_meta_data, de_payload))); 8366 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8367 offsetof(struct v10_gfx_meta_data, de_payload))); 8368 8369 if (resume) 8370 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8371 offsetof(struct v10_gfx_meta_data, 8372 de_payload), 8373 sizeof(de_payload) >> 2); 8374 else 8375 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8376 sizeof(de_payload) >> 2); 8377 } 8378 8379 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8380 bool secure) 8381 { 8382 uint32_t v = secure ? FRAME_TMZ : 0; 8383 8384 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8385 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8386 } 8387 8388 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8389 uint32_t reg_val_offs) 8390 { 8391 struct amdgpu_device *adev = ring->adev; 8392 8393 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8394 amdgpu_ring_write(ring, 0 | /* src: register*/ 8395 (5 << 8) | /* dst: memory */ 8396 (1 << 20)); /* write confirm */ 8397 amdgpu_ring_write(ring, reg); 8398 amdgpu_ring_write(ring, 0); 8399 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8400 reg_val_offs * 4)); 8401 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8402 reg_val_offs * 4)); 8403 } 8404 8405 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8406 uint32_t val) 8407 { 8408 uint32_t cmd = 0; 8409 8410 switch (ring->funcs->type) { 8411 case AMDGPU_RING_TYPE_GFX: 8412 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8413 break; 8414 case AMDGPU_RING_TYPE_KIQ: 8415 cmd = (1 << 16); /* no inc addr */ 8416 break; 8417 default: 8418 cmd = WR_CONFIRM; 8419 break; 8420 } 8421 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8422 amdgpu_ring_write(ring, cmd); 8423 amdgpu_ring_write(ring, reg); 8424 amdgpu_ring_write(ring, 0); 8425 amdgpu_ring_write(ring, val); 8426 } 8427 8428 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8429 uint32_t val, uint32_t mask) 8430 { 8431 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8432 } 8433 8434 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8435 uint32_t reg0, uint32_t reg1, 8436 uint32_t ref, uint32_t mask) 8437 { 8438 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8439 struct amdgpu_device *adev = ring->adev; 8440 bool fw_version_ok = false; 8441 8442 fw_version_ok = adev->gfx.cp_fw_write_wait; 8443 8444 if (fw_version_ok) 8445 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8446 ref, mask, 0x20); 8447 else 8448 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8449 ref, mask); 8450 } 8451 8452 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8453 unsigned vmid) 8454 { 8455 struct amdgpu_device *adev = ring->adev; 8456 uint32_t value = 0; 8457 8458 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8459 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8460 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8461 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8462 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8463 } 8464 8465 static void 8466 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8467 uint32_t me, uint32_t pipe, 8468 enum amdgpu_interrupt_state state) 8469 { 8470 uint32_t cp_int_cntl, cp_int_cntl_reg; 8471 8472 if (!me) { 8473 switch (pipe) { 8474 case 0: 8475 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8476 break; 8477 case 1: 8478 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8479 break; 8480 default: 8481 DRM_DEBUG("invalid pipe %d\n", pipe); 8482 return; 8483 } 8484 } else { 8485 DRM_DEBUG("invalid me %d\n", me); 8486 return; 8487 } 8488 8489 switch (state) { 8490 case AMDGPU_IRQ_STATE_DISABLE: 8491 cp_int_cntl = RREG32(cp_int_cntl_reg); 8492 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8493 TIME_STAMP_INT_ENABLE, 0); 8494 WREG32(cp_int_cntl_reg, cp_int_cntl); 8495 break; 8496 case AMDGPU_IRQ_STATE_ENABLE: 8497 cp_int_cntl = RREG32(cp_int_cntl_reg); 8498 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8499 TIME_STAMP_INT_ENABLE, 1); 8500 WREG32(cp_int_cntl_reg, cp_int_cntl); 8501 break; 8502 default: 8503 break; 8504 } 8505 } 8506 8507 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8508 int me, int pipe, 8509 enum amdgpu_interrupt_state state) 8510 { 8511 u32 mec_int_cntl, mec_int_cntl_reg; 8512 8513 /* 8514 * amdgpu controls only the first MEC. That's why this function only 8515 * handles the setting of interrupts for this specific MEC. All other 8516 * pipes' interrupts are set by amdkfd. 8517 */ 8518 8519 if (me == 1) { 8520 switch (pipe) { 8521 case 0: 8522 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8523 break; 8524 case 1: 8525 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8526 break; 8527 case 2: 8528 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8529 break; 8530 case 3: 8531 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8532 break; 8533 default: 8534 DRM_DEBUG("invalid pipe %d\n", pipe); 8535 return; 8536 } 8537 } else { 8538 DRM_DEBUG("invalid me %d\n", me); 8539 return; 8540 } 8541 8542 switch (state) { 8543 case AMDGPU_IRQ_STATE_DISABLE: 8544 mec_int_cntl = RREG32(mec_int_cntl_reg); 8545 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8546 TIME_STAMP_INT_ENABLE, 0); 8547 WREG32(mec_int_cntl_reg, mec_int_cntl); 8548 break; 8549 case AMDGPU_IRQ_STATE_ENABLE: 8550 mec_int_cntl = RREG32(mec_int_cntl_reg); 8551 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8552 TIME_STAMP_INT_ENABLE, 1); 8553 WREG32(mec_int_cntl_reg, mec_int_cntl); 8554 break; 8555 default: 8556 break; 8557 } 8558 } 8559 8560 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8561 struct amdgpu_irq_src *src, 8562 unsigned type, 8563 enum amdgpu_interrupt_state state) 8564 { 8565 switch (type) { 8566 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8567 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8568 break; 8569 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8570 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8571 break; 8572 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8573 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8574 break; 8575 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8576 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8577 break; 8578 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8579 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8580 break; 8581 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8582 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8583 break; 8584 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8585 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8586 break; 8587 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8588 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8589 break; 8590 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8591 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8592 break; 8593 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8594 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8595 break; 8596 default: 8597 break; 8598 } 8599 return 0; 8600 } 8601 8602 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8603 struct amdgpu_irq_src *source, 8604 struct amdgpu_iv_entry *entry) 8605 { 8606 int i; 8607 u8 me_id, pipe_id, queue_id; 8608 struct amdgpu_ring *ring; 8609 8610 DRM_DEBUG("IH: CP EOP\n"); 8611 me_id = (entry->ring_id & 0x0c) >> 2; 8612 pipe_id = (entry->ring_id & 0x03) >> 0; 8613 queue_id = (entry->ring_id & 0x70) >> 4; 8614 8615 switch (me_id) { 8616 case 0: 8617 if (pipe_id == 0) 8618 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8619 else 8620 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8621 break; 8622 case 1: 8623 case 2: 8624 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8625 ring = &adev->gfx.compute_ring[i]; 8626 /* Per-queue interrupt is supported for MEC starting from VI. 8627 * The interrupt can only be enabled/disabled per pipe instead of per queue. 8628 */ 8629 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 8630 amdgpu_fence_process(ring); 8631 } 8632 break; 8633 } 8634 return 0; 8635 } 8636 8637 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8638 struct amdgpu_irq_src *source, 8639 unsigned type, 8640 enum amdgpu_interrupt_state state) 8641 { 8642 switch (state) { 8643 case AMDGPU_IRQ_STATE_DISABLE: 8644 case AMDGPU_IRQ_STATE_ENABLE: 8645 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8646 PRIV_REG_INT_ENABLE, 8647 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8648 break; 8649 default: 8650 break; 8651 } 8652 8653 return 0; 8654 } 8655 8656 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8657 struct amdgpu_irq_src *source, 8658 unsigned type, 8659 enum amdgpu_interrupt_state state) 8660 { 8661 switch (state) { 8662 case AMDGPU_IRQ_STATE_DISABLE: 8663 case AMDGPU_IRQ_STATE_ENABLE: 8664 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8665 PRIV_INSTR_INT_ENABLE, 8666 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8667 break; 8668 default: 8669 break; 8670 } 8671 8672 return 0; 8673 } 8674 8675 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8676 struct amdgpu_iv_entry *entry) 8677 { 8678 u8 me_id, pipe_id, queue_id; 8679 struct amdgpu_ring *ring; 8680 int i; 8681 8682 me_id = (entry->ring_id & 0x0c) >> 2; 8683 pipe_id = (entry->ring_id & 0x03) >> 0; 8684 queue_id = (entry->ring_id & 0x70) >> 4; 8685 8686 switch (me_id) { 8687 case 0: 8688 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 8689 ring = &adev->gfx.gfx_ring[i]; 8690 /* we only enabled 1 gfx queue per pipe for now */ 8691 if (ring->me == me_id && ring->pipe == pipe_id) 8692 drm_sched_fault(&ring->sched); 8693 } 8694 break; 8695 case 1: 8696 case 2: 8697 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8698 ring = &adev->gfx.compute_ring[i]; 8699 if (ring->me == me_id && ring->pipe == pipe_id && 8700 ring->queue == queue_id) 8701 drm_sched_fault(&ring->sched); 8702 } 8703 break; 8704 default: 8705 BUG(); 8706 } 8707 } 8708 8709 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 8710 struct amdgpu_irq_src *source, 8711 struct amdgpu_iv_entry *entry) 8712 { 8713 DRM_ERROR("Illegal register access in command stream\n"); 8714 gfx_v10_0_handle_priv_fault(adev, entry); 8715 return 0; 8716 } 8717 8718 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 8719 struct amdgpu_irq_src *source, 8720 struct amdgpu_iv_entry *entry) 8721 { 8722 DRM_ERROR("Illegal instruction in command stream\n"); 8723 gfx_v10_0_handle_priv_fault(adev, entry); 8724 return 0; 8725 } 8726 8727 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 8728 struct amdgpu_irq_src *src, 8729 unsigned int type, 8730 enum amdgpu_interrupt_state state) 8731 { 8732 uint32_t tmp, target; 8733 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8734 8735 if (ring->me == 1) 8736 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8737 else 8738 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 8739 target += ring->pipe; 8740 8741 switch (type) { 8742 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 8743 if (state == AMDGPU_IRQ_STATE_DISABLE) { 8744 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8745 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8746 GENERIC2_INT_ENABLE, 0); 8747 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8748 8749 tmp = RREG32(target); 8750 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8751 GENERIC2_INT_ENABLE, 0); 8752 WREG32(target, tmp); 8753 } else { 8754 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8755 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8756 GENERIC2_INT_ENABLE, 1); 8757 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8758 8759 tmp = RREG32(target); 8760 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8761 GENERIC2_INT_ENABLE, 1); 8762 WREG32(target, tmp); 8763 } 8764 break; 8765 default: 8766 BUG(); /* kiq only support GENERIC2_INT now */ 8767 break; 8768 } 8769 return 0; 8770 } 8771 8772 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 8773 struct amdgpu_irq_src *source, 8774 struct amdgpu_iv_entry *entry) 8775 { 8776 u8 me_id, pipe_id, queue_id; 8777 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8778 8779 me_id = (entry->ring_id & 0x0c) >> 2; 8780 pipe_id = (entry->ring_id & 0x03) >> 0; 8781 queue_id = (entry->ring_id & 0x70) >> 4; 8782 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 8783 me_id, pipe_id, queue_id); 8784 8785 amdgpu_fence_process(ring); 8786 return 0; 8787 } 8788 8789 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 8790 { 8791 const unsigned int gcr_cntl = 8792 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 8793 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 8794 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 8795 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 8796 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 8797 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 8798 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 8799 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 8800 8801 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 8802 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 8803 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 8804 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 8805 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 8806 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 8807 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 8808 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 8809 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 8810 } 8811 8812 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 8813 .name = "gfx_v10_0", 8814 .early_init = gfx_v10_0_early_init, 8815 .late_init = gfx_v10_0_late_init, 8816 .sw_init = gfx_v10_0_sw_init, 8817 .sw_fini = gfx_v10_0_sw_fini, 8818 .hw_init = gfx_v10_0_hw_init, 8819 .hw_fini = gfx_v10_0_hw_fini, 8820 .suspend = gfx_v10_0_suspend, 8821 .resume = gfx_v10_0_resume, 8822 .is_idle = gfx_v10_0_is_idle, 8823 .wait_for_idle = gfx_v10_0_wait_for_idle, 8824 .soft_reset = gfx_v10_0_soft_reset, 8825 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 8826 .set_powergating_state = gfx_v10_0_set_powergating_state, 8827 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 8828 }; 8829 8830 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 8831 .type = AMDGPU_RING_TYPE_GFX, 8832 .align_mask = 0xff, 8833 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8834 .support_64bit_ptrs = true, 8835 .vmhub = AMDGPU_GFXHUB_0, 8836 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 8837 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 8838 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 8839 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 8840 5 + /* COND_EXEC */ 8841 7 + /* PIPELINE_SYNC */ 8842 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8843 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8844 2 + /* VM_FLUSH */ 8845 8 + /* FENCE for VM_FLUSH */ 8846 20 + /* GDS switch */ 8847 4 + /* double SWITCH_BUFFER, 8848 * the first COND_EXEC jump to the place 8849 * just prior to this double SWITCH_BUFFER 8850 */ 8851 5 + /* COND_EXEC */ 8852 7 + /* HDP_flush */ 8853 4 + /* VGT_flush */ 8854 14 + /* CE_META */ 8855 31 + /* DE_META */ 8856 3 + /* CNTX_CTRL */ 8857 5 + /* HDP_INVL */ 8858 8 + 8 + /* FENCE x2 */ 8859 2 + /* SWITCH_BUFFER */ 8860 8, /* gfx_v10_0_emit_mem_sync */ 8861 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 8862 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 8863 .emit_fence = gfx_v10_0_ring_emit_fence, 8864 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8865 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8866 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8867 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8868 .test_ring = gfx_v10_0_ring_test_ring, 8869 .test_ib = gfx_v10_0_ring_test_ib, 8870 .insert_nop = amdgpu_ring_insert_nop, 8871 .pad_ib = amdgpu_ring_generic_pad_ib, 8872 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 8873 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 8874 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 8875 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 8876 .preempt_ib = gfx_v10_0_ring_preempt_ib, 8877 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 8878 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8879 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8880 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8881 .soft_recovery = gfx_v10_0_ring_soft_recovery, 8882 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8883 }; 8884 8885 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 8886 .type = AMDGPU_RING_TYPE_COMPUTE, 8887 .align_mask = 0xff, 8888 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8889 .support_64bit_ptrs = true, 8890 .vmhub = AMDGPU_GFXHUB_0, 8891 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8892 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8893 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8894 .emit_frame_size = 8895 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8896 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8897 5 + /* hdp invalidate */ 8898 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8899 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8900 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8901 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8902 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 8903 8, /* gfx_v10_0_emit_mem_sync */ 8904 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8905 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8906 .emit_fence = gfx_v10_0_ring_emit_fence, 8907 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8908 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8909 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8910 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8911 .test_ring = gfx_v10_0_ring_test_ring, 8912 .test_ib = gfx_v10_0_ring_test_ib, 8913 .insert_nop = amdgpu_ring_insert_nop, 8914 .pad_ib = amdgpu_ring_generic_pad_ib, 8915 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8916 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8917 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8918 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8919 }; 8920 8921 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 8922 .type = AMDGPU_RING_TYPE_KIQ, 8923 .align_mask = 0xff, 8924 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8925 .support_64bit_ptrs = true, 8926 .vmhub = AMDGPU_GFXHUB_0, 8927 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8928 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8929 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8930 .emit_frame_size = 8931 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8932 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8933 5 + /*hdp invalidate */ 8934 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8935 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8936 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8937 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8938 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 8939 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8940 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8941 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 8942 .test_ring = gfx_v10_0_ring_test_ring, 8943 .test_ib = gfx_v10_0_ring_test_ib, 8944 .insert_nop = amdgpu_ring_insert_nop, 8945 .pad_ib = amdgpu_ring_generic_pad_ib, 8946 .emit_rreg = gfx_v10_0_ring_emit_rreg, 8947 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8948 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8949 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8950 }; 8951 8952 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 8953 { 8954 int i; 8955 8956 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 8957 8958 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 8959 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 8960 8961 for (i = 0; i < adev->gfx.num_compute_rings; i++) 8962 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 8963 } 8964 8965 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 8966 .set = gfx_v10_0_set_eop_interrupt_state, 8967 .process = gfx_v10_0_eop_irq, 8968 }; 8969 8970 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 8971 .set = gfx_v10_0_set_priv_reg_fault_state, 8972 .process = gfx_v10_0_priv_reg_irq, 8973 }; 8974 8975 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 8976 .set = gfx_v10_0_set_priv_inst_fault_state, 8977 .process = gfx_v10_0_priv_inst_irq, 8978 }; 8979 8980 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 8981 .set = gfx_v10_0_kiq_set_interrupt_state, 8982 .process = gfx_v10_0_kiq_irq, 8983 }; 8984 8985 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 8986 { 8987 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 8988 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 8989 8990 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 8991 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 8992 8993 adev->gfx.priv_reg_irq.num_types = 1; 8994 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 8995 8996 adev->gfx.priv_inst_irq.num_types = 1; 8997 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 8998 } 8999 9000 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9001 { 9002 switch (adev->asic_type) { 9003 case CHIP_NAVI10: 9004 case CHIP_NAVI14: 9005 case CHIP_SIENNA_CICHLID: 9006 case CHIP_NAVY_FLOUNDER: 9007 case CHIP_VANGOGH: 9008 case CHIP_DIMGREY_CAVEFISH: 9009 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9010 break; 9011 case CHIP_NAVI12: 9012 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9013 break; 9014 default: 9015 break; 9016 } 9017 } 9018 9019 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9020 { 9021 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9022 adev->gfx.config.max_sh_per_se * 9023 adev->gfx.config.max_shader_engines; 9024 9025 adev->gds.gds_size = 0x10000; 9026 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9027 adev->gds.gws_size = 64; 9028 adev->gds.oa_size = 16; 9029 } 9030 9031 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9032 u32 bitmap) 9033 { 9034 u32 data; 9035 9036 if (!bitmap) 9037 return; 9038 9039 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9040 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9041 9042 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9043 } 9044 9045 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9046 { 9047 u32 data, wgp_bitmask; 9048 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9049 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9050 9051 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9052 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9053 9054 wgp_bitmask = 9055 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9056 9057 return (~data) & wgp_bitmask; 9058 } 9059 9060 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9061 { 9062 u32 wgp_idx, wgp_active_bitmap; 9063 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9064 9065 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9066 cu_active_bitmap = 0; 9067 9068 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9069 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9070 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9071 if (wgp_active_bitmap & (1 << wgp_idx)) 9072 cu_active_bitmap |= cu_bitmap_per_wgp; 9073 } 9074 9075 return cu_active_bitmap; 9076 } 9077 9078 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9079 struct amdgpu_cu_info *cu_info) 9080 { 9081 int i, j, k, counter, active_cu_number = 0; 9082 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9083 unsigned disable_masks[4 * 2]; 9084 9085 if (!adev || !cu_info) 9086 return -EINVAL; 9087 9088 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9089 9090 mutex_lock(&adev->grbm_idx_mutex); 9091 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9092 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9093 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9094 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 9095 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9096 continue; 9097 mask = 1; 9098 ao_bitmap = 0; 9099 counter = 0; 9100 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9101 if (i < 4 && j < 2) 9102 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9103 adev, disable_masks[i * 2 + j]); 9104 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9105 cu_info->bitmap[i][j] = bitmap; 9106 9107 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9108 if (bitmap & mask) { 9109 if (counter < adev->gfx.config.max_cu_per_sh) 9110 ao_bitmap |= mask; 9111 counter++; 9112 } 9113 mask <<= 1; 9114 } 9115 active_cu_number += counter; 9116 if (i < 2 && j < 2) 9117 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9118 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9119 } 9120 } 9121 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9122 mutex_unlock(&adev->grbm_idx_mutex); 9123 9124 cu_info->number = active_cu_number; 9125 cu_info->ao_cu_mask = ao_cu_mask; 9126 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9127 9128 return 0; 9129 } 9130 9131 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9132 { 9133 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9134 9135 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9136 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9137 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9138 9139 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9140 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9141 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9142 9143 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9144 adev->gfx.config.max_shader_engines); 9145 disabled_sa = efuse_setting | vbios_setting; 9146 disabled_sa &= max_sa_mask; 9147 9148 return disabled_sa; 9149 } 9150 9151 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9152 { 9153 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9154 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9155 9156 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9157 9158 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9159 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9160 max_shader_engines = adev->gfx.config.max_shader_engines; 9161 9162 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9163 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9164 disabled_sa_per_se &= max_sa_per_se_mask; 9165 if (disabled_sa_per_se == max_sa_per_se_mask) { 9166 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9167 break; 9168 } 9169 } 9170 } 9171 9172 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9173 { 9174 .type = AMD_IP_BLOCK_TYPE_GFX, 9175 .major = 10, 9176 .minor = 0, 9177 .rev = 0, 9178 .funcs = &gfx_v10_0_ip_funcs, 9179 }; 9180