1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_smu.h"
33 #include "nv.h"
34 #include "nvd.h"
35 
36 #include "gc/gc_10_1_0_offset.h"
37 #include "gc/gc_10_1_0_sh_mask.h"
38 #include "smuio/smuio_11_0_0_offset.h"
39 #include "smuio/smuio_11_0_0_sh_mask.h"
40 #include "navi10_enum.h"
41 #include "hdp/hdp_5_0_0_offset.h"
42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
43 
44 #include "soc15.h"
45 #include "soc15d.h"
46 #include "soc15_common.h"
47 #include "clearstate_gfx10.h"
48 #include "v10_structs.h"
49 #include "gfx_v10_0.h"
50 #include "nbio_v2_3.h"
51 
52 /**
53  * Navi10 has two graphic rings to share each graphic pipe.
54  * 1. Primary ring
55  * 2. Async ring
56  */
57 #define GFX10_NUM_GFX_RINGS_NV1X	1
58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1
59 #define GFX10_MEC_HPD_SIZE	2048
60 
61 #define F32_CE_PROGRAM_RAM_SIZE		65536
62 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
63 
64 #define mmCGTT_GS_NGG_CLK_CTRL	0x5087
65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
70 
71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
73 
74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
76 #define mmRLC_SAFE_MODE_Sienna_Cichlid			0x4ca0
77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX		1
78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid		0x4ca1
79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX	1
80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid			0x11ec
81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX		0
82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid		0x0fc1
83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid		0x0fc2
85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid			0x0fc3
87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid		0x0fc4
89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX	0
90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid		0x0fc5
91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX	0
92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid		0x0fc6
93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX	0
94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT	0x1a
95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK	0x04000000L
96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK	0x00000FFCL
97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT	0x2
98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK	0x00000FFCL
99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
101 
102 #define mmSPI_CONFIG_CNTL_1_Vangogh		 0x2441
103 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX	 1
104 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
105 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
106 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
107 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
108 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
109 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
110 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
111 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
112 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
113 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
114 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
115 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
116 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
117 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
118 
119 #define mmCP_HYP_PFP_UCODE_ADDR			0x5814
120 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1
121 #define mmCP_HYP_PFP_UCODE_DATA			0x5815
122 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX	1
123 #define mmCP_HYP_CE_UCODE_ADDR			0x5818
124 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX		1
125 #define mmCP_HYP_CE_UCODE_DATA			0x5819
126 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX		1
127 #define mmCP_HYP_ME_UCODE_ADDR			0x5816
128 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX		1
129 #define mmCP_HYP_ME_UCODE_DATA			0x5817
130 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX		1
131 
132 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
133 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
134 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
135 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
136 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
137 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
138 
139 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
140 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
141 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
142 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
143 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
144 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
145 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
146 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
147 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
148 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
149 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
150 
151 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
152 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
153 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
154 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
155 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
156 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
157 
158 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
159 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
160 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
161 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
162 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
163 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
164 
165 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
166 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
167 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
168 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
169 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
170 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
171 
172 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
173 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
174 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
175 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
176 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
177 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
178 
179 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
180 {
181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
221 };
222 
223 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
224 {
225 	/* Pending on emulation bring up */
226 };
227 
228 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
229 {
230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1282 };
1283 
1284 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1285 {
1286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1324 };
1325 
1326 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1327 {
1328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1368 };
1369 
1370 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1371 {
1372 	static void *scratch_reg0;
1373 	static void *scratch_reg1;
1374 	static void *scratch_reg2;
1375 	static void *scratch_reg3;
1376 	static void *spare_int;
1377 	static uint32_t grbm_cntl;
1378 	static uint32_t grbm_idx;
1379 	uint32_t i = 0;
1380 	uint32_t retries = 50000;
1381 
1382 	scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1383 	scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1384 	scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1385 	scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1386 	spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1387 
1388 	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1389 	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1390 
1391 	if (amdgpu_sriov_runtime(adev)) {
1392 		pr_err("shouldn't call rlcg write register during runtime\n");
1393 		return;
1394 	}
1395 
1396 	writel(v, scratch_reg0);
1397 	writel(offset | 0x80000000, scratch_reg1);
1398 	writel(1, spare_int);
1399 	for (i = 0; i < retries; i++) {
1400 		u32 tmp;
1401 
1402 		tmp = readl(scratch_reg1);
1403 		if (!(tmp & 0x80000000))
1404 			break;
1405 
1406 		udelay(10);
1407 	}
1408 
1409 	if (i >= retries)
1410 		pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1411 }
1412 
1413 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1414 {
1415 	/* Pending on emulation bring up */
1416 };
1417 
1418 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1419 {
1420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2040 };
2041 
2042 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2043 {
2044 	/* Pending on emulation bring up */
2045 };
2046 
2047 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2048 {
2049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3101 };
3102 
3103 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3104 {
3105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3141 };
3142 
3143 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3144 {
3145 	/* Pending on emulation bring up */
3146 };
3147 
3148 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3149 {
3150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
3188 };
3189 
3190 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3191 {
3192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3215 };
3216 
3217 #define DEFAULT_SH_MEM_CONFIG \
3218 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3219 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3220 	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3221 	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3222 
3223 
3224 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3225 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3226 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3227 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3228 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3229                                  struct amdgpu_cu_info *cu_info);
3230 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3231 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3232 				   u32 sh_num, u32 instance);
3233 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3234 
3235 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3236 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3237 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3238 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3239 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3240 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3241 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3242 
3243 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3244 {
3245 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3246 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3247 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
3248 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
3249 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
3250 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
3251 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
3252 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
3253 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
3254 }
3255 
3256 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3257 				 struct amdgpu_ring *ring)
3258 {
3259 	struct amdgpu_device *adev = kiq_ring->adev;
3260 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3261 	uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3262 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3263 
3264 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3265 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3266 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3267 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3268 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3269 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3270 			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3271 			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3272 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3273 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3274 			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3275 			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3276 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3277 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3278 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3279 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3280 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3281 }
3282 
3283 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3284 				   struct amdgpu_ring *ring,
3285 				   enum amdgpu_unmap_queues_action action,
3286 				   u64 gpu_addr, u64 seq)
3287 {
3288 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3289 
3290 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3291 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3292 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
3293 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3294 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3295 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3296 	amdgpu_ring_write(kiq_ring,
3297 		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3298 
3299 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
3300 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3301 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3302 		amdgpu_ring_write(kiq_ring, seq);
3303 	} else {
3304 		amdgpu_ring_write(kiq_ring, 0);
3305 		amdgpu_ring_write(kiq_ring, 0);
3306 		amdgpu_ring_write(kiq_ring, 0);
3307 	}
3308 }
3309 
3310 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3311 				   struct amdgpu_ring *ring,
3312 				   u64 addr,
3313 				   u64 seq)
3314 {
3315 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3316 
3317 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3318 	amdgpu_ring_write(kiq_ring,
3319 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3320 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3321 			  PACKET3_QUERY_STATUS_COMMAND(2));
3322 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3323 			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3324 			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3325 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3326 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3327 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3328 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3329 }
3330 
3331 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3332 				uint16_t pasid, uint32_t flush_type,
3333 				bool all_hub)
3334 {
3335 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3336 	amdgpu_ring_write(kiq_ring,
3337 			PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3338 			PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3339 			PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3340 			PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3341 }
3342 
3343 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3344 	.kiq_set_resources = gfx10_kiq_set_resources,
3345 	.kiq_map_queues = gfx10_kiq_map_queues,
3346 	.kiq_unmap_queues = gfx10_kiq_unmap_queues,
3347 	.kiq_query_status = gfx10_kiq_query_status,
3348 	.kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3349 	.set_resources_size = 8,
3350 	.map_queues_size = 7,
3351 	.unmap_queues_size = 6,
3352 	.query_status_size = 7,
3353 	.invalidate_tlbs_size = 2,
3354 };
3355 
3356 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3357 {
3358 	adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3359 }
3360 
3361 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3362 {
3363 	switch (adev->asic_type) {
3364 	case CHIP_NAVI10:
3365 		soc15_program_register_sequence(adev,
3366 						golden_settings_gc_rlc_spm_10_0_nv10,
3367 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3368 		break;
3369 	case CHIP_NAVI14:
3370 		soc15_program_register_sequence(adev,
3371 						golden_settings_gc_rlc_spm_10_1_nv14,
3372 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3373 		break;
3374 	case CHIP_NAVI12:
3375 		soc15_program_register_sequence(adev,
3376 						golden_settings_gc_rlc_spm_10_1_2_nv12,
3377 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3378 		break;
3379 	default:
3380 		break;
3381 	}
3382 }
3383 
3384 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3385 {
3386 	switch (adev->asic_type) {
3387 	case CHIP_NAVI10:
3388 		soc15_program_register_sequence(adev,
3389 						golden_settings_gc_10_1,
3390 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3391 		soc15_program_register_sequence(adev,
3392 						golden_settings_gc_10_0_nv10,
3393 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3394 		break;
3395 	case CHIP_NAVI14:
3396 		soc15_program_register_sequence(adev,
3397 						golden_settings_gc_10_1_1,
3398 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3399 		soc15_program_register_sequence(adev,
3400 						golden_settings_gc_10_1_nv14,
3401 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3402 		break;
3403 	case CHIP_NAVI12:
3404 		soc15_program_register_sequence(adev,
3405 						golden_settings_gc_10_1_2,
3406 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3407 		soc15_program_register_sequence(adev,
3408 						golden_settings_gc_10_1_2_nv12,
3409 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3410 		break;
3411 	case CHIP_SIENNA_CICHLID:
3412 		soc15_program_register_sequence(adev,
3413 						golden_settings_gc_10_3,
3414 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3415 		soc15_program_register_sequence(adev,
3416 						golden_settings_gc_10_3_sienna_cichlid,
3417 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3418 		break;
3419 	case CHIP_NAVY_FLOUNDER:
3420 		soc15_program_register_sequence(adev,
3421 						golden_settings_gc_10_3_2,
3422 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3423 		break;
3424 	case CHIP_VANGOGH:
3425 		soc15_program_register_sequence(adev,
3426 						golden_settings_gc_10_3_vangogh,
3427 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3428 		break;
3429 	default:
3430 		break;
3431 	}
3432 	gfx_v10_0_init_spm_golden_registers(adev);
3433 }
3434 
3435 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3436 {
3437 	adev->gfx.scratch.num_reg = 8;
3438 	adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3439 	adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3440 }
3441 
3442 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3443 				       bool wc, uint32_t reg, uint32_t val)
3444 {
3445 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3446 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3447 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3448 	amdgpu_ring_write(ring, reg);
3449 	amdgpu_ring_write(ring, 0);
3450 	amdgpu_ring_write(ring, val);
3451 }
3452 
3453 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3454 				  int mem_space, int opt, uint32_t addr0,
3455 				  uint32_t addr1, uint32_t ref, uint32_t mask,
3456 				  uint32_t inv)
3457 {
3458 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3459 	amdgpu_ring_write(ring,
3460 			  /* memory (1) or register (0) */
3461 			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3462 			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
3463 			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3464 			   WAIT_REG_MEM_ENGINE(eng_sel)));
3465 
3466 	if (mem_space)
3467 		BUG_ON(addr0 & 0x3); /* Dword align */
3468 	amdgpu_ring_write(ring, addr0);
3469 	amdgpu_ring_write(ring, addr1);
3470 	amdgpu_ring_write(ring, ref);
3471 	amdgpu_ring_write(ring, mask);
3472 	amdgpu_ring_write(ring, inv); /* poll interval */
3473 }
3474 
3475 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3476 {
3477 	struct amdgpu_device *adev = ring->adev;
3478 	uint32_t scratch;
3479 	uint32_t tmp = 0;
3480 	unsigned i;
3481 	int r;
3482 
3483 	r = amdgpu_gfx_scratch_get(adev, &scratch);
3484 	if (r) {
3485 		DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3486 		return r;
3487 	}
3488 
3489 	WREG32(scratch, 0xCAFEDEAD);
3490 
3491 	r = amdgpu_ring_alloc(ring, 3);
3492 	if (r) {
3493 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3494 			  ring->idx, r);
3495 		amdgpu_gfx_scratch_free(adev, scratch);
3496 		return r;
3497 	}
3498 
3499 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3500 	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3501 	amdgpu_ring_write(ring, 0xDEADBEEF);
3502 	amdgpu_ring_commit(ring);
3503 
3504 	for (i = 0; i < adev->usec_timeout; i++) {
3505 		tmp = RREG32(scratch);
3506 		if (tmp == 0xDEADBEEF)
3507 			break;
3508 		if (amdgpu_emu_mode == 1)
3509 			msleep(1);
3510 		else
3511 			udelay(1);
3512 	}
3513 
3514 	if (i >= adev->usec_timeout)
3515 		r = -ETIMEDOUT;
3516 
3517 	amdgpu_gfx_scratch_free(adev, scratch);
3518 
3519 	return r;
3520 }
3521 
3522 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3523 {
3524 	struct amdgpu_device *adev = ring->adev;
3525 	struct amdgpu_ib ib;
3526 	struct dma_fence *f = NULL;
3527 	unsigned index;
3528 	uint64_t gpu_addr;
3529 	uint32_t tmp;
3530 	long r;
3531 
3532 	r = amdgpu_device_wb_get(adev, &index);
3533 	if (r)
3534 		return r;
3535 
3536 	gpu_addr = adev->wb.gpu_addr + (index * 4);
3537 	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3538 	memset(&ib, 0, sizeof(ib));
3539 	r = amdgpu_ib_get(adev, NULL, 16,
3540 					AMDGPU_IB_POOL_DIRECT, &ib);
3541 	if (r)
3542 		goto err1;
3543 
3544 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3545 	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3546 	ib.ptr[2] = lower_32_bits(gpu_addr);
3547 	ib.ptr[3] = upper_32_bits(gpu_addr);
3548 	ib.ptr[4] = 0xDEADBEEF;
3549 	ib.length_dw = 5;
3550 
3551 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3552 	if (r)
3553 		goto err2;
3554 
3555 	r = dma_fence_wait_timeout(f, false, timeout);
3556 	if (r == 0) {
3557 		r = -ETIMEDOUT;
3558 		goto err2;
3559 	} else if (r < 0) {
3560 		goto err2;
3561 	}
3562 
3563 	tmp = adev->wb.wb[index];
3564 	if (tmp == 0xDEADBEEF)
3565 		r = 0;
3566 	else
3567 		r = -EINVAL;
3568 err2:
3569 	amdgpu_ib_free(adev, &ib, NULL);
3570 	dma_fence_put(f);
3571 err1:
3572 	amdgpu_device_wb_free(adev, index);
3573 	return r;
3574 }
3575 
3576 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3577 {
3578 	release_firmware(adev->gfx.pfp_fw);
3579 	adev->gfx.pfp_fw = NULL;
3580 	release_firmware(adev->gfx.me_fw);
3581 	adev->gfx.me_fw = NULL;
3582 	release_firmware(adev->gfx.ce_fw);
3583 	adev->gfx.ce_fw = NULL;
3584 	release_firmware(adev->gfx.rlc_fw);
3585 	adev->gfx.rlc_fw = NULL;
3586 	release_firmware(adev->gfx.mec_fw);
3587 	adev->gfx.mec_fw = NULL;
3588 	release_firmware(adev->gfx.mec2_fw);
3589 	adev->gfx.mec2_fw = NULL;
3590 
3591 	kfree(adev->gfx.rlc.register_list_format);
3592 }
3593 
3594 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3595 {
3596 	adev->gfx.cp_fw_write_wait = false;
3597 
3598 	switch (adev->asic_type) {
3599 	case CHIP_NAVI10:
3600 	case CHIP_NAVI12:
3601 	case CHIP_NAVI14:
3602 		if ((adev->gfx.me_fw_version >= 0x00000046) &&
3603 		    (adev->gfx.me_feature_version >= 27) &&
3604 		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
3605 		    (adev->gfx.pfp_feature_version >= 27) &&
3606 		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
3607 		    (adev->gfx.mec_feature_version >= 27))
3608 			adev->gfx.cp_fw_write_wait = true;
3609 		break;
3610 	case CHIP_SIENNA_CICHLID:
3611 	case CHIP_NAVY_FLOUNDER:
3612 	case CHIP_VANGOGH:
3613 		adev->gfx.cp_fw_write_wait = true;
3614 		break;
3615 	default:
3616 		break;
3617 	}
3618 
3619 	if (!adev->gfx.cp_fw_write_wait)
3620 		DRM_WARN_ONCE("CP firmware version too old, please update!");
3621 }
3622 
3623 
3624 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3625 {
3626 	const struct rlc_firmware_header_v2_1 *rlc_hdr;
3627 
3628 	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3629 	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3630 	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3631 	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3632 	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3633 	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3634 	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3635 	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3636 	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3637 	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3638 	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3639 	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3640 	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3641 	adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3642 			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3643 }
3644 
3645 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3646 {
3647 	bool ret = false;
3648 
3649 	switch (adev->pdev->revision) {
3650 	case 0xc2:
3651 	case 0xc3:
3652 		ret = true;
3653 		break;
3654 	default:
3655 		ret = false;
3656 		break;
3657 	}
3658 
3659 	return ret ;
3660 }
3661 
3662 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3663 {
3664 	switch (adev->asic_type) {
3665 	case CHIP_NAVI10:
3666 		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3667 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3668 		break;
3669 	case CHIP_NAVY_FLOUNDER:
3670 	case CHIP_VANGOGH:
3671 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3672 		break;
3673 	default:
3674 		break;
3675 	}
3676 }
3677 
3678 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3679 {
3680 	const char *chip_name;
3681 	char fw_name[40];
3682 	char wks[10];
3683 	int err;
3684 	struct amdgpu_firmware_info *info = NULL;
3685 	const struct common_firmware_header *header = NULL;
3686 	const struct gfx_firmware_header_v1_0 *cp_hdr;
3687 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
3688 	unsigned int *tmp = NULL;
3689 	unsigned int i = 0;
3690 	uint16_t version_major;
3691 	uint16_t version_minor;
3692 
3693 	DRM_DEBUG("\n");
3694 
3695 	memset(wks, 0, sizeof(wks));
3696 	switch (adev->asic_type) {
3697 	case CHIP_NAVI10:
3698 		chip_name = "navi10";
3699 		break;
3700 	case CHIP_NAVI14:
3701 		chip_name = "navi14";
3702 		if (!(adev->pdev->device == 0x7340 &&
3703 		      adev->pdev->revision != 0x00))
3704 			snprintf(wks, sizeof(wks), "_wks");
3705 		break;
3706 	case CHIP_NAVI12:
3707 		chip_name = "navi12";
3708 		break;
3709 	case CHIP_SIENNA_CICHLID:
3710 		chip_name = "sienna_cichlid";
3711 		break;
3712 	case CHIP_NAVY_FLOUNDER:
3713 		chip_name = "navy_flounder";
3714 		break;
3715 	case CHIP_VANGOGH:
3716 		chip_name = "vangogh";
3717 		break;
3718 	default:
3719 		BUG();
3720 	}
3721 
3722 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3723 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3724 	if (err)
3725 		goto out;
3726 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3727 	if (err)
3728 		goto out;
3729 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3730 	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3731 	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3732 
3733 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3734 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3735 	if (err)
3736 		goto out;
3737 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
3738 	if (err)
3739 		goto out;
3740 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3741 	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3742 	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3743 
3744 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3745 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3746 	if (err)
3747 		goto out;
3748 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3749 	if (err)
3750 		goto out;
3751 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3752 	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3753 	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3754 
3755 	if (!amdgpu_sriov_vf(adev)) {
3756 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3757 		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3758 		if (err)
3759 			goto out;
3760 		err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3761 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3762 		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3763 		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3764 		if (version_major == 2 && version_minor == 1)
3765 			adev->gfx.rlc.is_rlc_v2_1 = true;
3766 
3767 		adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3768 		adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3769 		adev->gfx.rlc.save_and_restore_offset =
3770 			le32_to_cpu(rlc_hdr->save_and_restore_offset);
3771 		adev->gfx.rlc.clear_state_descriptor_offset =
3772 			le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3773 		adev->gfx.rlc.avail_scratch_ram_locations =
3774 			le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3775 		adev->gfx.rlc.reg_restore_list_size =
3776 			le32_to_cpu(rlc_hdr->reg_restore_list_size);
3777 		adev->gfx.rlc.reg_list_format_start =
3778 			le32_to_cpu(rlc_hdr->reg_list_format_start);
3779 		adev->gfx.rlc.reg_list_format_separate_start =
3780 			le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3781 		adev->gfx.rlc.starting_offsets_start =
3782 			le32_to_cpu(rlc_hdr->starting_offsets_start);
3783 		adev->gfx.rlc.reg_list_format_size_bytes =
3784 			le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3785 		adev->gfx.rlc.reg_list_size_bytes =
3786 			le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3787 		adev->gfx.rlc.register_list_format =
3788 			kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3789 					adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3790 		if (!adev->gfx.rlc.register_list_format) {
3791 			err = -ENOMEM;
3792 			goto out;
3793 		}
3794 
3795 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3796 							   le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3797 		for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3798 			adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
3799 
3800 		adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3801 
3802 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3803 							   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3804 		for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3805 			adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3806 
3807 		if (adev->gfx.rlc.is_rlc_v2_1)
3808 			gfx_v10_0_init_rlc_ext_microcode(adev);
3809 	}
3810 
3811 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3812 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3813 	if (err)
3814 		goto out;
3815 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3816 	if (err)
3817 		goto out;
3818 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3819 	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3820 	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3821 
3822 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3823 	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3824 	if (!err) {
3825 		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3826 		if (err)
3827 			goto out;
3828 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3829 		adev->gfx.mec2_fw->data;
3830 		adev->gfx.mec2_fw_version =
3831 		le32_to_cpu(cp_hdr->header.ucode_version);
3832 		adev->gfx.mec2_feature_version =
3833 		le32_to_cpu(cp_hdr->ucode_feature_version);
3834 	} else {
3835 		err = 0;
3836 		adev->gfx.mec2_fw = NULL;
3837 	}
3838 
3839 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3840 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3841 		info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3842 		info->fw = adev->gfx.pfp_fw;
3843 		header = (const struct common_firmware_header *)info->fw->data;
3844 		adev->firmware.fw_size +=
3845 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3846 
3847 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3848 		info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3849 		info->fw = adev->gfx.me_fw;
3850 		header = (const struct common_firmware_header *)info->fw->data;
3851 		adev->firmware.fw_size +=
3852 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3853 
3854 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3855 		info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3856 		info->fw = adev->gfx.ce_fw;
3857 		header = (const struct common_firmware_header *)info->fw->data;
3858 		adev->firmware.fw_size +=
3859 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3860 
3861 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3862 		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3863 		info->fw = adev->gfx.rlc_fw;
3864 		if (info->fw) {
3865 			header = (const struct common_firmware_header *)info->fw->data;
3866 			adev->firmware.fw_size +=
3867 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3868 		}
3869 		if (adev->gfx.rlc.is_rlc_v2_1 &&
3870 		    adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3871 		    adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3872 		    adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3873 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3874 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3875 			info->fw = adev->gfx.rlc_fw;
3876 			adev->firmware.fw_size +=
3877 				ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3878 
3879 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3880 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3881 			info->fw = adev->gfx.rlc_fw;
3882 			adev->firmware.fw_size +=
3883 				ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3884 
3885 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3886 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3887 			info->fw = adev->gfx.rlc_fw;
3888 			adev->firmware.fw_size +=
3889 				ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3890 		}
3891 
3892 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3893 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3894 		info->fw = adev->gfx.mec_fw;
3895 		header = (const struct common_firmware_header *)info->fw->data;
3896 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3897 		adev->firmware.fw_size +=
3898 			ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3899 			      le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3900 
3901 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3902 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3903 		info->fw = adev->gfx.mec_fw;
3904 		adev->firmware.fw_size +=
3905 			ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3906 
3907 		if (adev->gfx.mec2_fw) {
3908 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3909 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3910 			info->fw = adev->gfx.mec2_fw;
3911 			header = (const struct common_firmware_header *)info->fw->data;
3912 			cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3913 			adev->firmware.fw_size +=
3914 				ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3915 				      le32_to_cpu(cp_hdr->jt_size) * 4,
3916 				      PAGE_SIZE);
3917 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3918 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3919 			info->fw = adev->gfx.mec2_fw;
3920 			adev->firmware.fw_size +=
3921 				ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3922 				      PAGE_SIZE);
3923 		}
3924 	}
3925 
3926 	gfx_v10_0_check_fw_write_wait(adev);
3927 out:
3928 	if (err) {
3929 		dev_err(adev->dev,
3930 			"gfx10: Failed to load firmware \"%s\"\n",
3931 			fw_name);
3932 		release_firmware(adev->gfx.pfp_fw);
3933 		adev->gfx.pfp_fw = NULL;
3934 		release_firmware(adev->gfx.me_fw);
3935 		adev->gfx.me_fw = NULL;
3936 		release_firmware(adev->gfx.ce_fw);
3937 		adev->gfx.ce_fw = NULL;
3938 		release_firmware(adev->gfx.rlc_fw);
3939 		adev->gfx.rlc_fw = NULL;
3940 		release_firmware(adev->gfx.mec_fw);
3941 		adev->gfx.mec_fw = NULL;
3942 		release_firmware(adev->gfx.mec2_fw);
3943 		adev->gfx.mec2_fw = NULL;
3944 	}
3945 
3946 	gfx_v10_0_check_gfxoff_flag(adev);
3947 
3948 	return err;
3949 }
3950 
3951 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3952 {
3953 	u32 count = 0;
3954 	const struct cs_section_def *sect = NULL;
3955 	const struct cs_extent_def *ext = NULL;
3956 
3957 	/* begin clear state */
3958 	count += 2;
3959 	/* context control state */
3960 	count += 3;
3961 
3962 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3963 		for (ext = sect->section; ext->extent != NULL; ++ext) {
3964 			if (sect->id == SECT_CONTEXT)
3965 				count += 2 + ext->reg_count;
3966 			else
3967 				return 0;
3968 		}
3969 	}
3970 
3971 	/* set PA_SC_TILE_STEERING_OVERRIDE */
3972 	count += 3;
3973 	/* end clear state */
3974 	count += 2;
3975 	/* clear state */
3976 	count += 2;
3977 
3978 	return count;
3979 }
3980 
3981 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3982 				    volatile u32 *buffer)
3983 {
3984 	u32 count = 0, i;
3985 	const struct cs_section_def *sect = NULL;
3986 	const struct cs_extent_def *ext = NULL;
3987 	int ctx_reg_offset;
3988 
3989 	if (adev->gfx.rlc.cs_data == NULL)
3990 		return;
3991 	if (buffer == NULL)
3992 		return;
3993 
3994 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3995 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3996 
3997 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3998 	buffer[count++] = cpu_to_le32(0x80000000);
3999 	buffer[count++] = cpu_to_le32(0x80000000);
4000 
4001 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4002 		for (ext = sect->section; ext->extent != NULL; ++ext) {
4003 			if (sect->id == SECT_CONTEXT) {
4004 				buffer[count++] =
4005 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4006 				buffer[count++] = cpu_to_le32(ext->reg_index -
4007 						PACKET3_SET_CONTEXT_REG_START);
4008 				for (i = 0; i < ext->reg_count; i++)
4009 					buffer[count++] = cpu_to_le32(ext->extent[i]);
4010 			} else {
4011 				return;
4012 			}
4013 		}
4014 	}
4015 
4016 	ctx_reg_offset =
4017 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4018 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4019 	buffer[count++] = cpu_to_le32(ctx_reg_offset);
4020 	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4021 
4022 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4023 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4024 
4025 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4026 	buffer[count++] = cpu_to_le32(0);
4027 }
4028 
4029 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4030 {
4031 	/* clear state block */
4032 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4033 			&adev->gfx.rlc.clear_state_gpu_addr,
4034 			(void **)&adev->gfx.rlc.cs_ptr);
4035 
4036 	/* jump table block */
4037 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4038 			&adev->gfx.rlc.cp_table_gpu_addr,
4039 			(void **)&adev->gfx.rlc.cp_table_ptr);
4040 }
4041 
4042 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4043 {
4044 	const struct cs_section_def *cs_data;
4045 	int r;
4046 
4047 	adev->gfx.rlc.cs_data = gfx10_cs_data;
4048 
4049 	cs_data = adev->gfx.rlc.cs_data;
4050 
4051 	if (cs_data) {
4052 		/* init clear state block */
4053 		r = amdgpu_gfx_rlc_init_csb(adev);
4054 		if (r)
4055 			return r;
4056 	}
4057 
4058 	/* init spm vmid with 0xf */
4059 	if (adev->gfx.rlc.funcs->update_spm_vmid)
4060 		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4061 
4062 	return 0;
4063 }
4064 
4065 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4066 {
4067 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4068 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4069 }
4070 
4071 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4072 {
4073 	int r;
4074 
4075 	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4076 
4077 	amdgpu_gfx_graphics_queue_acquire(adev);
4078 
4079 	r = gfx_v10_0_init_microcode(adev);
4080 	if (r)
4081 		DRM_ERROR("Failed to load gfx firmware!\n");
4082 
4083 	return r;
4084 }
4085 
4086 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4087 {
4088 	int r;
4089 	u32 *hpd;
4090 	const __le32 *fw_data = NULL;
4091 	unsigned fw_size;
4092 	u32 *fw = NULL;
4093 	size_t mec_hpd_size;
4094 
4095 	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4096 
4097 	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4098 
4099 	/* take ownership of the relevant compute queues */
4100 	amdgpu_gfx_compute_queue_acquire(adev);
4101 	mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4102 
4103 	if (mec_hpd_size) {
4104 		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4105 					      AMDGPU_GEM_DOMAIN_GTT,
4106 					      &adev->gfx.mec.hpd_eop_obj,
4107 					      &adev->gfx.mec.hpd_eop_gpu_addr,
4108 					      (void **)&hpd);
4109 		if (r) {
4110 			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4111 			gfx_v10_0_mec_fini(adev);
4112 			return r;
4113 		}
4114 
4115 		memset(hpd, 0, mec_hpd_size);
4116 
4117 		amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4118 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4119 	}
4120 
4121 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4122 		mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4123 
4124 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4125 			 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4126 		fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4127 
4128 		r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4129 					      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4130 					      &adev->gfx.mec.mec_fw_obj,
4131 					      &adev->gfx.mec.mec_fw_gpu_addr,
4132 					      (void **)&fw);
4133 		if (r) {
4134 			dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4135 			gfx_v10_0_mec_fini(adev);
4136 			return r;
4137 		}
4138 
4139 		memcpy(fw, fw_data, fw_size);
4140 
4141 		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4142 		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4143 	}
4144 
4145 	return 0;
4146 }
4147 
4148 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4149 {
4150 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4151 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4152 		(address << SQ_IND_INDEX__INDEX__SHIFT));
4153 	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4154 }
4155 
4156 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4157 			   uint32_t thread, uint32_t regno,
4158 			   uint32_t num, uint32_t *out)
4159 {
4160 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4161 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4162 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
4163 		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4164 		(SQ_IND_INDEX__AUTO_INCR_MASK));
4165 	while (num--)
4166 		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4167 }
4168 
4169 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4170 {
4171 	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4172 	 * field when performing a select_se_sh so it should be
4173 	 * zero here */
4174 	WARN_ON(simd != 0);
4175 
4176 	/* type 2 wave data */
4177 	dst[(*no_fields)++] = 2;
4178 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4179 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4180 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4181 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4182 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4183 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4184 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4185 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4186 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4187 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4188 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4189 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4190 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4191 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4192 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4193 }
4194 
4195 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4196 				     uint32_t wave, uint32_t start,
4197 				     uint32_t size, uint32_t *dst)
4198 {
4199 	WARN_ON(simd != 0);
4200 
4201 	wave_read_regs(
4202 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4203 		dst);
4204 }
4205 
4206 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4207 				      uint32_t wave, uint32_t thread,
4208 				      uint32_t start, uint32_t size,
4209 				      uint32_t *dst)
4210 {
4211 	wave_read_regs(
4212 		adev, wave, thread,
4213 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4214 }
4215 
4216 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4217 									  u32 me, u32 pipe, u32 q, u32 vm)
4218  {
4219        nv_grbm_select(adev, me, pipe, q, vm);
4220  }
4221 
4222 
4223 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4224 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4225 	.select_se_sh = &gfx_v10_0_select_se_sh,
4226 	.read_wave_data = &gfx_v10_0_read_wave_data,
4227 	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4228 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4229 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4230 	.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4231 };
4232 
4233 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4234 {
4235 	u32 gb_addr_config;
4236 
4237 	adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4238 
4239 	switch (adev->asic_type) {
4240 	case CHIP_NAVI10:
4241 	case CHIP_NAVI14:
4242 	case CHIP_NAVI12:
4243 		adev->gfx.config.max_hw_contexts = 8;
4244 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4245 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4246 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4247 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4248 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4249 		break;
4250 	case CHIP_SIENNA_CICHLID:
4251 	case CHIP_NAVY_FLOUNDER:
4252 	case CHIP_VANGOGH:
4253 		adev->gfx.config.max_hw_contexts = 8;
4254 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4255 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4256 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4257 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4258 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4259 		adev->gfx.config.gb_addr_config_fields.num_pkrs =
4260 			1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4261 		break;
4262 	default:
4263 		BUG();
4264 		break;
4265 	}
4266 
4267 	adev->gfx.config.gb_addr_config = gb_addr_config;
4268 
4269 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4270 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4271 				      GB_ADDR_CONFIG, NUM_PIPES);
4272 
4273 	adev->gfx.config.max_tile_pipes =
4274 		adev->gfx.config.gb_addr_config_fields.num_pipes;
4275 
4276 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4277 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4278 				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4279 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4280 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4281 				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
4282 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4283 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4284 				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4285 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4286 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4287 				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4288 }
4289 
4290 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4291 				   int me, int pipe, int queue)
4292 {
4293 	int r;
4294 	struct amdgpu_ring *ring;
4295 	unsigned int irq_type;
4296 
4297 	ring = &adev->gfx.gfx_ring[ring_id];
4298 
4299 	ring->me = me;
4300 	ring->pipe = pipe;
4301 	ring->queue = queue;
4302 
4303 	ring->ring_obj = NULL;
4304 	ring->use_doorbell = true;
4305 
4306 	if (!ring_id)
4307 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4308 	else
4309 		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4310 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4311 
4312 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4313 	r = amdgpu_ring_init(adev, ring, 1024,
4314 			     &adev->gfx.eop_irq, irq_type,
4315 			     AMDGPU_RING_PRIO_DEFAULT);
4316 	if (r)
4317 		return r;
4318 	return 0;
4319 }
4320 
4321 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4322 				       int mec, int pipe, int queue)
4323 {
4324 	int r;
4325 	unsigned irq_type;
4326 	struct amdgpu_ring *ring;
4327 	unsigned int hw_prio;
4328 
4329 	ring = &adev->gfx.compute_ring[ring_id];
4330 
4331 	/* mec0 is me1 */
4332 	ring->me = mec + 1;
4333 	ring->pipe = pipe;
4334 	ring->queue = queue;
4335 
4336 	ring->ring_obj = NULL;
4337 	ring->use_doorbell = true;
4338 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4339 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4340 				+ (ring_id * GFX10_MEC_HPD_SIZE);
4341 	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4342 
4343 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4344 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4345 		+ ring->pipe;
4346 	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4347 			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4348 	/* type-2 packets are deprecated on MEC, use type-3 instead */
4349 	r = amdgpu_ring_init(adev, ring, 1024,
4350 			     &adev->gfx.eop_irq, irq_type, hw_prio);
4351 	if (r)
4352 		return r;
4353 
4354 	return 0;
4355 }
4356 
4357 static int gfx_v10_0_sw_init(void *handle)
4358 {
4359 	int i, j, k, r, ring_id = 0;
4360 	struct amdgpu_kiq *kiq;
4361 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4362 
4363 	switch (adev->asic_type) {
4364 	case CHIP_NAVI10:
4365 	case CHIP_NAVI14:
4366 	case CHIP_NAVI12:
4367 		adev->gfx.me.num_me = 1;
4368 		adev->gfx.me.num_pipe_per_me = 1;
4369 		adev->gfx.me.num_queue_per_pipe = 1;
4370 		adev->gfx.mec.num_mec = 2;
4371 		adev->gfx.mec.num_pipe_per_mec = 4;
4372 		adev->gfx.mec.num_queue_per_pipe = 8;
4373 		break;
4374 	case CHIP_SIENNA_CICHLID:
4375 	case CHIP_NAVY_FLOUNDER:
4376 	case CHIP_VANGOGH:
4377 		adev->gfx.me.num_me = 1;
4378 		adev->gfx.me.num_pipe_per_me = 1;
4379 		adev->gfx.me.num_queue_per_pipe = 1;
4380 		adev->gfx.mec.num_mec = 2;
4381 		adev->gfx.mec.num_pipe_per_mec = 4;
4382 		adev->gfx.mec.num_queue_per_pipe = 4;
4383 		break;
4384 	default:
4385 		adev->gfx.me.num_me = 1;
4386 		adev->gfx.me.num_pipe_per_me = 1;
4387 		adev->gfx.me.num_queue_per_pipe = 1;
4388 		adev->gfx.mec.num_mec = 1;
4389 		adev->gfx.mec.num_pipe_per_mec = 4;
4390 		adev->gfx.mec.num_queue_per_pipe = 8;
4391 		break;
4392 	}
4393 
4394 	/* KIQ event */
4395 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4396 			      GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4397 			      &adev->gfx.kiq.irq);
4398 	if (r)
4399 		return r;
4400 
4401 	/* EOP Event */
4402 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4403 			      GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4404 			      &adev->gfx.eop_irq);
4405 	if (r)
4406 		return r;
4407 
4408 	/* Privileged reg */
4409 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4410 			      &adev->gfx.priv_reg_irq);
4411 	if (r)
4412 		return r;
4413 
4414 	/* Privileged inst */
4415 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4416 			      &adev->gfx.priv_inst_irq);
4417 	if (r)
4418 		return r;
4419 
4420 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4421 
4422 	gfx_v10_0_scratch_init(adev);
4423 
4424 	r = gfx_v10_0_me_init(adev);
4425 	if (r)
4426 		return r;
4427 
4428 	r = gfx_v10_0_rlc_init(adev);
4429 	if (r) {
4430 		DRM_ERROR("Failed to init rlc BOs!\n");
4431 		return r;
4432 	}
4433 
4434 	r = gfx_v10_0_mec_init(adev);
4435 	if (r) {
4436 		DRM_ERROR("Failed to init MEC BOs!\n");
4437 		return r;
4438 	}
4439 
4440 	/* set up the gfx ring */
4441 	for (i = 0; i < adev->gfx.me.num_me; i++) {
4442 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4443 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4444 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4445 					continue;
4446 
4447 				r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4448 							    i, k, j);
4449 				if (r)
4450 					return r;
4451 				ring_id++;
4452 			}
4453 		}
4454 	}
4455 
4456 	ring_id = 0;
4457 	/* set up the compute queues - allocate horizontally across pipes */
4458 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4459 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4460 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4461 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4462 								     j))
4463 					continue;
4464 
4465 				r = gfx_v10_0_compute_ring_init(adev, ring_id,
4466 								i, k, j);
4467 				if (r)
4468 					return r;
4469 
4470 				ring_id++;
4471 			}
4472 		}
4473 	}
4474 
4475 	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4476 	if (r) {
4477 		DRM_ERROR("Failed to init KIQ BOs!\n");
4478 		return r;
4479 	}
4480 
4481 	kiq = &adev->gfx.kiq;
4482 	r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4483 	if (r)
4484 		return r;
4485 
4486 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4487 	if (r)
4488 		return r;
4489 
4490 	/* allocate visible FB for rlc auto-loading fw */
4491 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4492 		r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4493 		if (r)
4494 			return r;
4495 	}
4496 
4497 	adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4498 
4499 	gfx_v10_0_gpu_early_init(adev);
4500 
4501 	return 0;
4502 }
4503 
4504 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4505 {
4506 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4507 			      &adev->gfx.pfp.pfp_fw_gpu_addr,
4508 			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
4509 }
4510 
4511 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4512 {
4513 	amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4514 			      &adev->gfx.ce.ce_fw_gpu_addr,
4515 			      (void **)&adev->gfx.ce.ce_fw_ptr);
4516 }
4517 
4518 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4519 {
4520 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4521 			      &adev->gfx.me.me_fw_gpu_addr,
4522 			      (void **)&adev->gfx.me.me_fw_ptr);
4523 }
4524 
4525 static int gfx_v10_0_sw_fini(void *handle)
4526 {
4527 	int i;
4528 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4529 
4530 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4531 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4532 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
4533 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4534 
4535 	amdgpu_gfx_mqd_sw_fini(adev);
4536 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4537 	amdgpu_gfx_kiq_fini(adev);
4538 
4539 	gfx_v10_0_pfp_fini(adev);
4540 	gfx_v10_0_ce_fini(adev);
4541 	gfx_v10_0_me_fini(adev);
4542 	gfx_v10_0_rlc_fini(adev);
4543 	gfx_v10_0_mec_fini(adev);
4544 
4545 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4546 		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4547 
4548 	gfx_v10_0_free_microcode(adev);
4549 
4550 	return 0;
4551 }
4552 
4553 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4554 				   u32 sh_num, u32 instance)
4555 {
4556 	u32 data;
4557 
4558 	if (instance == 0xffffffff)
4559 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4560 				     INSTANCE_BROADCAST_WRITES, 1);
4561 	else
4562 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4563 				     instance);
4564 
4565 	if (se_num == 0xffffffff)
4566 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4567 				     1);
4568 	else
4569 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4570 
4571 	if (sh_num == 0xffffffff)
4572 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4573 				     1);
4574 	else
4575 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4576 
4577 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4578 }
4579 
4580 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4581 {
4582 	u32 data, mask;
4583 
4584 	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4585 	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4586 
4587 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4588 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4589 
4590 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4591 					 adev->gfx.config.max_sh_per_se);
4592 
4593 	return (~data) & mask;
4594 }
4595 
4596 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4597 {
4598 	int i, j;
4599 	u32 data;
4600 	u32 active_rbs = 0;
4601 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4602 					adev->gfx.config.max_sh_per_se;
4603 
4604 	mutex_lock(&adev->grbm_idx_mutex);
4605 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4606 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4607 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4608 			data = gfx_v10_0_get_rb_active_bitmap(adev);
4609 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4610 					       rb_bitmap_width_per_sh);
4611 		}
4612 	}
4613 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4614 	mutex_unlock(&adev->grbm_idx_mutex);
4615 
4616 	adev->gfx.config.backend_enable_mask = active_rbs;
4617 	adev->gfx.config.num_rbs = hweight32(active_rbs);
4618 }
4619 
4620 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4621 {
4622 	uint32_t num_sc;
4623 	uint32_t enabled_rb_per_sh;
4624 	uint32_t active_rb_bitmap;
4625 	uint32_t num_rb_per_sc;
4626 	uint32_t num_packer_per_sc;
4627 	uint32_t pa_sc_tile_steering_override;
4628 
4629 	/* for ASICs that integrates GFX v10.3
4630 	 * pa_sc_tile_steering_override should be set to 0 */
4631 	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4632 	    adev->asic_type == CHIP_NAVY_FLOUNDER ||
4633 	    adev->asic_type == CHIP_VANGOGH)
4634 		return 0;
4635 
4636 	/* init num_sc */
4637 	num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4638 			adev->gfx.config.num_sc_per_sh;
4639 	/* init num_rb_per_sc */
4640 	active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4641 	enabled_rb_per_sh = hweight32(active_rb_bitmap);
4642 	num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4643 	/* init num_packer_per_sc */
4644 	num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4645 
4646 	pa_sc_tile_steering_override = 0;
4647 	pa_sc_tile_steering_override |=
4648 		(order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4649 		PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4650 	pa_sc_tile_steering_override |=
4651 		(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4652 		PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4653 	pa_sc_tile_steering_override |=
4654 		(order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4655 		PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4656 
4657 	return pa_sc_tile_steering_override;
4658 }
4659 
4660 #define DEFAULT_SH_MEM_BASES	(0x6000)
4661 
4662 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4663 {
4664 	int i;
4665 	uint32_t sh_mem_bases;
4666 
4667 	/*
4668 	 * Configure apertures:
4669 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4670 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4671 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4672 	 */
4673 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4674 
4675 	mutex_lock(&adev->srbm_mutex);
4676 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4677 		nv_grbm_select(adev, 0, 0, 0, i);
4678 		/* CP and shaders */
4679 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4680 		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4681 	}
4682 	nv_grbm_select(adev, 0, 0, 0, 0);
4683 	mutex_unlock(&adev->srbm_mutex);
4684 
4685 	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
4686 	   acccess. These should be enabled by FW for target VMIDs. */
4687 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4688 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4689 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4690 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4691 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4692 	}
4693 }
4694 
4695 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4696 {
4697 	int vmid;
4698 
4699 	/*
4700 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4701 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
4702 	 * the driver can enable them for graphics. VMID0 should maintain
4703 	 * access so that HWS firmware can save/restore entries.
4704 	 */
4705 	for (vmid = 1; vmid < 16; vmid++) {
4706 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4707 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4708 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4709 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4710 	}
4711 }
4712 
4713 
4714 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4715 {
4716 	int i, j, k;
4717 	int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4718 	u32 tmp, wgp_active_bitmap = 0;
4719 	u32 gcrd_targets_disable_tcp = 0;
4720 	u32 utcl_invreq_disable = 0;
4721 	/*
4722 	 * GCRD_TARGETS_DISABLE field contains
4723 	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4724 	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4725 	 */
4726 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4727 		2 * max_wgp_per_sh + /* TCP */
4728 		max_wgp_per_sh + /* SQC */
4729 		4); /* GL1C */
4730 	/*
4731 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
4732 	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4733 	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4734 	 */
4735 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4736 		2 * max_wgp_per_sh + /* TCP */
4737 		2 * max_wgp_per_sh + /* SQC */
4738 		4 + /* RMI */
4739 		1); /* SQG */
4740 
4741 	if (adev->asic_type == CHIP_NAVI10 ||
4742 	    adev->asic_type == CHIP_NAVI14 ||
4743 	    adev->asic_type == CHIP_NAVI12) {
4744 		mutex_lock(&adev->grbm_idx_mutex);
4745 		for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4746 			for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4747 				gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4748 				wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4749 				/*
4750 				 * Set corresponding TCP bits for the inactive WGPs in
4751 				 * GCRD_SA_TARGETS_DISABLE
4752 				 */
4753 				gcrd_targets_disable_tcp = 0;
4754 				/* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4755 				utcl_invreq_disable = 0;
4756 
4757 				for (k = 0; k < max_wgp_per_sh; k++) {
4758 					if (!(wgp_active_bitmap & (1 << k))) {
4759 						gcrd_targets_disable_tcp |= 3 << (2 * k);
4760 						utcl_invreq_disable |= (3 << (2 * k)) |
4761 							(3 << (2 * (max_wgp_per_sh + k)));
4762 					}
4763 				}
4764 
4765 				tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4766 				/* only override TCP & SQC bits */
4767 				tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4768 				tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4769 				WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4770 
4771 				tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4772 				/* only override TCP bits */
4773 				tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4774 				tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4775 				WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4776 			}
4777 		}
4778 
4779 		gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4780 		mutex_unlock(&adev->grbm_idx_mutex);
4781 	}
4782 }
4783 
4784 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4785 {
4786 	/* TCCs are global (not instanced). */
4787 	uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4788 			       RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4789 
4790 	adev->gfx.config.tcc_disabled_mask =
4791 		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4792 		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4793 }
4794 
4795 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4796 {
4797 	u32 tmp;
4798 	int i;
4799 
4800 	WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4801 
4802 	gfx_v10_0_setup_rb(adev);
4803 	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4804 	gfx_v10_0_get_tcc_info(adev);
4805 	adev->gfx.config.pa_sc_tile_steering_override =
4806 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4807 
4808 	/* XXX SH_MEM regs */
4809 	/* where to put LDS, scratch, GPUVM in FSA64 space */
4810 	mutex_lock(&adev->srbm_mutex);
4811 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4812 		nv_grbm_select(adev, 0, 0, 0, i);
4813 		/* CP and shaders */
4814 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4815 		if (i != 0) {
4816 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4817 				(adev->gmc.private_aperture_start >> 48));
4818 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4819 				(adev->gmc.shared_aperture_start >> 48));
4820 			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4821 		}
4822 	}
4823 	nv_grbm_select(adev, 0, 0, 0, 0);
4824 
4825 	mutex_unlock(&adev->srbm_mutex);
4826 
4827 	gfx_v10_0_init_compute_vmid(adev);
4828 	gfx_v10_0_init_gds_vmid(adev);
4829 
4830 }
4831 
4832 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4833 					       bool enable)
4834 {
4835 	u32 tmp;
4836 
4837 	if (amdgpu_sriov_vf(adev))
4838 		return;
4839 
4840 	tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4841 
4842 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4843 			    enable ? 1 : 0);
4844 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4845 			    enable ? 1 : 0);
4846 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4847 			    enable ? 1 : 0);
4848 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4849 			    enable ? 1 : 0);
4850 
4851 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4852 }
4853 
4854 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4855 {
4856 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4857 
4858 	/* csib */
4859 	if (adev->asic_type == CHIP_NAVI12) {
4860 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4861 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
4862 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4863 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4864 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4865 	} else {
4866 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
4867 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
4868 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
4869 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4870 		WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4871 	}
4872 	return 0;
4873 }
4874 
4875 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4876 {
4877 	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4878 
4879 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4880 	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4881 }
4882 
4883 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4884 {
4885 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4886 	udelay(50);
4887 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4888 	udelay(50);
4889 }
4890 
4891 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4892 					     bool enable)
4893 {
4894 	uint32_t rlc_pg_cntl;
4895 
4896 	rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4897 
4898 	if (!enable) {
4899 		/* RLC_PG_CNTL[23] = 0 (default)
4900 		 * RLC will wait for handshake acks with SMU
4901 		 * GFXOFF will be enabled
4902 		 * RLC_PG_CNTL[23] = 1
4903 		 * RLC will not issue any message to SMU
4904 		 * hence no handshake between SMU & RLC
4905 		 * GFXOFF will be disabled
4906 		 */
4907 		rlc_pg_cntl |= 0x800000;
4908 	} else
4909 		rlc_pg_cntl &= ~0x800000;
4910 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4911 }
4912 
4913 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4914 {
4915 	/* TODO: enable rlc & smu handshake until smu
4916 	 * and gfxoff feature works as expected */
4917 	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4918 		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4919 
4920 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4921 	udelay(50);
4922 }
4923 
4924 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4925 {
4926 	uint32_t tmp;
4927 
4928 	/* enable Save Restore Machine */
4929 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4930 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4931 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4932 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4933 }
4934 
4935 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4936 {
4937 	const struct rlc_firmware_header_v2_0 *hdr;
4938 	const __le32 *fw_data;
4939 	unsigned i, fw_size;
4940 
4941 	if (!adev->gfx.rlc_fw)
4942 		return -EINVAL;
4943 
4944 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4945 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
4946 
4947 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4948 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4949 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4950 
4951 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4952 		     RLCG_UCODE_LOADING_START_ADDRESS);
4953 
4954 	for (i = 0; i < fw_size; i++)
4955 		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4956 			     le32_to_cpup(fw_data++));
4957 
4958 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4959 
4960 	return 0;
4961 }
4962 
4963 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4964 {
4965 	int r;
4966 
4967 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4968 
4969 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4970 		if (r)
4971 			return r;
4972 
4973 		gfx_v10_0_init_csb(adev);
4974 
4975 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4976 			gfx_v10_0_rlc_enable_srm(adev);
4977 	} else {
4978 		if (amdgpu_sriov_vf(adev)) {
4979 			gfx_v10_0_init_csb(adev);
4980 			return 0;
4981 		}
4982 
4983 		adev->gfx.rlc.funcs->stop(adev);
4984 
4985 		/* disable CG */
4986 		WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4987 
4988 		/* disable PG */
4989 		WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4990 
4991 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4992 			/* legacy rlc firmware loading */
4993 			r = gfx_v10_0_rlc_load_microcode(adev);
4994 			if (r)
4995 				return r;
4996 		} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4997 			/* rlc backdoor autoload firmware */
4998 			r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4999 			if (r)
5000 				return r;
5001 		}
5002 
5003 		gfx_v10_0_init_csb(adev);
5004 
5005 		adev->gfx.rlc.funcs->start(adev);
5006 
5007 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5008 			r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5009 			if (r)
5010 				return r;
5011 		}
5012 	}
5013 	return 0;
5014 }
5015 
5016 static struct {
5017 	FIRMWARE_ID	id;
5018 	unsigned int	offset;
5019 	unsigned int	size;
5020 } rlc_autoload_info[FIRMWARE_ID_MAX];
5021 
5022 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5023 {
5024 	int ret;
5025 	RLC_TABLE_OF_CONTENT *rlc_toc;
5026 
5027 	ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5028 					AMDGPU_GEM_DOMAIN_GTT,
5029 					&adev->gfx.rlc.rlc_toc_bo,
5030 					&adev->gfx.rlc.rlc_toc_gpu_addr,
5031 					(void **)&adev->gfx.rlc.rlc_toc_buf);
5032 	if (ret) {
5033 		dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5034 		return ret;
5035 	}
5036 
5037 	/* Copy toc from psp sos fw to rlc toc buffer */
5038 	memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5039 
5040 	rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5041 	while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5042 		(rlc_toc->id < FIRMWARE_ID_MAX)) {
5043 		if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5044 		    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5045 			/* Offset needs 4KB alignment */
5046 			rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5047 		}
5048 
5049 		rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5050 		rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5051 		rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5052 
5053 		rlc_toc++;
5054 	}
5055 
5056 	return 0;
5057 }
5058 
5059 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5060 {
5061 	uint32_t total_size = 0;
5062 	FIRMWARE_ID id;
5063 	int ret;
5064 
5065 	ret = gfx_v10_0_parse_rlc_toc(adev);
5066 	if (ret) {
5067 		dev_err(adev->dev, "failed to parse rlc toc\n");
5068 		return 0;
5069 	}
5070 
5071 	for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5072 		total_size += rlc_autoload_info[id].size;
5073 
5074 	/* In case the offset in rlc toc ucode is aligned */
5075 	if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5076 		total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5077 				rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5078 
5079 	return total_size;
5080 }
5081 
5082 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5083 {
5084 	int r;
5085 	uint32_t total_size;
5086 
5087 	total_size = gfx_v10_0_calc_toc_total_size(adev);
5088 
5089 	r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5090 				      AMDGPU_GEM_DOMAIN_GTT,
5091 				      &adev->gfx.rlc.rlc_autoload_bo,
5092 				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5093 				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5094 	if (r) {
5095 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5096 		return r;
5097 	}
5098 
5099 	return 0;
5100 }
5101 
5102 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5103 {
5104 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5105 			      &adev->gfx.rlc.rlc_toc_gpu_addr,
5106 			      (void **)&adev->gfx.rlc.rlc_toc_buf);
5107 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5108 			      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5109 			      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5110 }
5111 
5112 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5113 						       FIRMWARE_ID id,
5114 						       const void *fw_data,
5115 						       uint32_t fw_size)
5116 {
5117 	uint32_t toc_offset;
5118 	uint32_t toc_fw_size;
5119 	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5120 
5121 	if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5122 		return;
5123 
5124 	toc_offset = rlc_autoload_info[id].offset;
5125 	toc_fw_size = rlc_autoload_info[id].size;
5126 
5127 	if (fw_size == 0)
5128 		fw_size = toc_fw_size;
5129 
5130 	if (fw_size > toc_fw_size)
5131 		fw_size = toc_fw_size;
5132 
5133 	memcpy(ptr + toc_offset, fw_data, fw_size);
5134 
5135 	if (fw_size < toc_fw_size)
5136 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5137 }
5138 
5139 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5140 {
5141 	void *data;
5142 	uint32_t size;
5143 
5144 	data = adev->gfx.rlc.rlc_toc_buf;
5145 	size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5146 
5147 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5148 						   FIRMWARE_ID_RLC_TOC,
5149 						   data, size);
5150 }
5151 
5152 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5153 {
5154 	const __le32 *fw_data;
5155 	uint32_t fw_size;
5156 	const struct gfx_firmware_header_v1_0 *cp_hdr;
5157 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
5158 
5159 	/* pfp ucode */
5160 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5161 		adev->gfx.pfp_fw->data;
5162 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5163 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5164 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5165 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5166 						   FIRMWARE_ID_CP_PFP,
5167 						   fw_data, fw_size);
5168 
5169 	/* ce ucode */
5170 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5171 		adev->gfx.ce_fw->data;
5172 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5173 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5174 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5175 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5176 						   FIRMWARE_ID_CP_CE,
5177 						   fw_data, fw_size);
5178 
5179 	/* me ucode */
5180 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5181 		adev->gfx.me_fw->data;
5182 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5183 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5184 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5185 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5186 						   FIRMWARE_ID_CP_ME,
5187 						   fw_data, fw_size);
5188 
5189 	/* rlc ucode */
5190 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5191 		adev->gfx.rlc_fw->data;
5192 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5193 		le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5194 	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5195 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5196 						   FIRMWARE_ID_RLC_G_UCODE,
5197 						   fw_data, fw_size);
5198 
5199 	/* mec1 ucode */
5200 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5201 		adev->gfx.mec_fw->data;
5202 	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5203 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5204 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5205 		cp_hdr->jt_size * 4;
5206 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5207 						   FIRMWARE_ID_CP_MEC,
5208 						   fw_data, fw_size);
5209 	/* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5210 }
5211 
5212 /* Temporarily put sdma part here */
5213 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5214 {
5215 	const __le32 *fw_data;
5216 	uint32_t fw_size;
5217 	const struct sdma_firmware_header_v1_0 *sdma_hdr;
5218 	int i;
5219 
5220 	for (i = 0; i < adev->sdma.num_instances; i++) {
5221 		sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5222 			adev->sdma.instance[i].fw->data;
5223 		fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5224 			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5225 		fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5226 
5227 		if (i == 0) {
5228 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5229 				FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5230 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5231 				FIRMWARE_ID_SDMA0_JT,
5232 				(uint32_t *)fw_data +
5233 				sdma_hdr->jt_offset,
5234 				sdma_hdr->jt_size * 4);
5235 		} else if (i == 1) {
5236 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5237 				FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5238 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5239 				FIRMWARE_ID_SDMA1_JT,
5240 				(uint32_t *)fw_data +
5241 				sdma_hdr->jt_offset,
5242 				sdma_hdr->jt_size * 4);
5243 		}
5244 	}
5245 }
5246 
5247 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5248 {
5249 	uint32_t rlc_g_offset, rlc_g_size, tmp;
5250 	uint64_t gpu_addr;
5251 
5252 	gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5253 	gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5254 	gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5255 
5256 	rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5257 	rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5258 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5259 
5260 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5261 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5262 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5263 
5264 	tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5265 	if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5266 		   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5267 		DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5268 		return -EINVAL;
5269 	}
5270 
5271 	tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5272 	if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5273 		DRM_ERROR("RLC ROM should halt itself\n");
5274 		return -EINVAL;
5275 	}
5276 
5277 	return 0;
5278 }
5279 
5280 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5281 {
5282 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5283 	uint32_t tmp;
5284 	int i;
5285 	uint64_t addr;
5286 
5287 	/* Trigger an invalidation of the L1 instruction caches */
5288 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5289 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5290 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5291 
5292 	/* Wait for invalidation complete */
5293 	for (i = 0; i < usec_timeout; i++) {
5294 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5295 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5296 			INVALIDATE_CACHE_COMPLETE))
5297 			break;
5298 		udelay(1);
5299 	}
5300 
5301 	if (i >= usec_timeout) {
5302 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5303 		return -EINVAL;
5304 	}
5305 
5306 	/* Program me ucode address into intruction cache address register */
5307 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5308 		rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5309 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5310 			lower_32_bits(addr) & 0xFFFFF000);
5311 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5312 			upper_32_bits(addr));
5313 
5314 	return 0;
5315 }
5316 
5317 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5318 {
5319 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5320 	uint32_t tmp;
5321 	int i;
5322 	uint64_t addr;
5323 
5324 	/* Trigger an invalidation of the L1 instruction caches */
5325 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5326 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5327 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5328 
5329 	/* Wait for invalidation complete */
5330 	for (i = 0; i < usec_timeout; i++) {
5331 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5332 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5333 			INVALIDATE_CACHE_COMPLETE))
5334 			break;
5335 		udelay(1);
5336 	}
5337 
5338 	if (i >= usec_timeout) {
5339 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5340 		return -EINVAL;
5341 	}
5342 
5343 	/* Program ce ucode address into intruction cache address register */
5344 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5345 		rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5346 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5347 			lower_32_bits(addr) & 0xFFFFF000);
5348 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5349 			upper_32_bits(addr));
5350 
5351 	return 0;
5352 }
5353 
5354 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5355 {
5356 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5357 	uint32_t tmp;
5358 	int i;
5359 	uint64_t addr;
5360 
5361 	/* Trigger an invalidation of the L1 instruction caches */
5362 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5363 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5364 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5365 
5366 	/* Wait for invalidation complete */
5367 	for (i = 0; i < usec_timeout; i++) {
5368 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5369 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5370 			INVALIDATE_CACHE_COMPLETE))
5371 			break;
5372 		udelay(1);
5373 	}
5374 
5375 	if (i >= usec_timeout) {
5376 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5377 		return -EINVAL;
5378 	}
5379 
5380 	/* Program pfp ucode address into intruction cache address register */
5381 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5382 		rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5383 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5384 			lower_32_bits(addr) & 0xFFFFF000);
5385 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5386 			upper_32_bits(addr));
5387 
5388 	return 0;
5389 }
5390 
5391 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5392 {
5393 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5394 	uint32_t tmp;
5395 	int i;
5396 	uint64_t addr;
5397 
5398 	/* Trigger an invalidation of the L1 instruction caches */
5399 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5400 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5401 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5402 
5403 	/* Wait for invalidation complete */
5404 	for (i = 0; i < usec_timeout; i++) {
5405 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5406 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5407 			INVALIDATE_CACHE_COMPLETE))
5408 			break;
5409 		udelay(1);
5410 	}
5411 
5412 	if (i >= usec_timeout) {
5413 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5414 		return -EINVAL;
5415 	}
5416 
5417 	/* Program mec1 ucode address into intruction cache address register */
5418 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5419 		rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5420 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5421 			lower_32_bits(addr) & 0xFFFFF000);
5422 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5423 			upper_32_bits(addr));
5424 
5425 	return 0;
5426 }
5427 
5428 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5429 {
5430 	uint32_t cp_status;
5431 	uint32_t bootload_status;
5432 	int i, r;
5433 
5434 	for (i = 0; i < adev->usec_timeout; i++) {
5435 		cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5436 		bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5437 		if ((cp_status == 0) &&
5438 		    (REG_GET_FIELD(bootload_status,
5439 			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5440 			break;
5441 		}
5442 		udelay(1);
5443 	}
5444 
5445 	if (i >= adev->usec_timeout) {
5446 		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5447 		return -ETIMEDOUT;
5448 	}
5449 
5450 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5451 		r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5452 		if (r)
5453 			return r;
5454 
5455 		r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5456 		if (r)
5457 			return r;
5458 
5459 		r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5460 		if (r)
5461 			return r;
5462 
5463 		r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5464 		if (r)
5465 			return r;
5466 	}
5467 
5468 	return 0;
5469 }
5470 
5471 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5472 {
5473 	int i;
5474 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5475 
5476 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5477 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5478 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5479 
5480 	if (adev->asic_type == CHIP_NAVI12) {
5481 		WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5482 	} else {
5483 		WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5484 	}
5485 
5486 	for (i = 0; i < adev->usec_timeout; i++) {
5487 		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5488 			break;
5489 		udelay(1);
5490 	}
5491 
5492 	if (i >= adev->usec_timeout)
5493 		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5494 
5495 	return 0;
5496 }
5497 
5498 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5499 {
5500 	int r;
5501 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
5502 	const __le32 *fw_data;
5503 	unsigned i, fw_size;
5504 	uint32_t tmp;
5505 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5506 
5507 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5508 		adev->gfx.pfp_fw->data;
5509 
5510 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5511 
5512 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5513 		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5514 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5515 
5516 	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5517 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5518 				      &adev->gfx.pfp.pfp_fw_obj,
5519 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
5520 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
5521 	if (r) {
5522 		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5523 		gfx_v10_0_pfp_fini(adev);
5524 		return r;
5525 	}
5526 
5527 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5528 
5529 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5530 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5531 
5532 	/* Trigger an invalidation of the L1 instruction caches */
5533 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5534 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5535 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5536 
5537 	/* Wait for invalidation complete */
5538 	for (i = 0; i < usec_timeout; i++) {
5539 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5540 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5541 			INVALIDATE_CACHE_COMPLETE))
5542 			break;
5543 		udelay(1);
5544 	}
5545 
5546 	if (i >= usec_timeout) {
5547 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5548 		return -EINVAL;
5549 	}
5550 
5551 	if (amdgpu_emu_mode == 1)
5552 		adev->nbio.funcs->hdp_flush(adev, NULL);
5553 
5554 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5555 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5556 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5557 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5558 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5559 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5560 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5561 		adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5562 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5563 		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5564 
5565 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5566 
5567 	for (i = 0; i < pfp_hdr->jt_size; i++)
5568 		WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5569 			     le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5570 
5571 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5572 
5573 	return 0;
5574 }
5575 
5576 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5577 {
5578 	int r;
5579 	const struct gfx_firmware_header_v1_0 *ce_hdr;
5580 	const __le32 *fw_data;
5581 	unsigned i, fw_size;
5582 	uint32_t tmp;
5583 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5584 
5585 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5586 		adev->gfx.ce_fw->data;
5587 
5588 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5589 
5590 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5591 		le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5592 	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5593 
5594 	r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5595 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5596 				      &adev->gfx.ce.ce_fw_obj,
5597 				      &adev->gfx.ce.ce_fw_gpu_addr,
5598 				      (void **)&adev->gfx.ce.ce_fw_ptr);
5599 	if (r) {
5600 		dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5601 		gfx_v10_0_ce_fini(adev);
5602 		return r;
5603 	}
5604 
5605 	memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5606 
5607 	amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5608 	amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5609 
5610 	/* Trigger an invalidation of the L1 instruction caches */
5611 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5612 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5613 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5614 
5615 	/* Wait for invalidation complete */
5616 	for (i = 0; i < usec_timeout; i++) {
5617 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5618 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5619 			INVALIDATE_CACHE_COMPLETE))
5620 			break;
5621 		udelay(1);
5622 	}
5623 
5624 	if (i >= usec_timeout) {
5625 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5626 		return -EINVAL;
5627 	}
5628 
5629 	if (amdgpu_emu_mode == 1)
5630 		adev->nbio.funcs->hdp_flush(adev, NULL);
5631 
5632 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5633 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5634 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5635 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5636 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5637 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5638 		adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5639 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5640 		upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5641 
5642 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5643 
5644 	for (i = 0; i < ce_hdr->jt_size; i++)
5645 		WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5646 			     le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5647 
5648 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5649 
5650 	return 0;
5651 }
5652 
5653 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5654 {
5655 	int r;
5656 	const struct gfx_firmware_header_v1_0 *me_hdr;
5657 	const __le32 *fw_data;
5658 	unsigned i, fw_size;
5659 	uint32_t tmp;
5660 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5661 
5662 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
5663 		adev->gfx.me_fw->data;
5664 
5665 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5666 
5667 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5668 		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5669 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5670 
5671 	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5672 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5673 				      &adev->gfx.me.me_fw_obj,
5674 				      &adev->gfx.me.me_fw_gpu_addr,
5675 				      (void **)&adev->gfx.me.me_fw_ptr);
5676 	if (r) {
5677 		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5678 		gfx_v10_0_me_fini(adev);
5679 		return r;
5680 	}
5681 
5682 	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5683 
5684 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5685 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5686 
5687 	/* Trigger an invalidation of the L1 instruction caches */
5688 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5689 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5690 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5691 
5692 	/* Wait for invalidation complete */
5693 	for (i = 0; i < usec_timeout; i++) {
5694 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5695 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5696 			INVALIDATE_CACHE_COMPLETE))
5697 			break;
5698 		udelay(1);
5699 	}
5700 
5701 	if (i >= usec_timeout) {
5702 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5703 		return -EINVAL;
5704 	}
5705 
5706 	if (amdgpu_emu_mode == 1)
5707 		adev->nbio.funcs->hdp_flush(adev, NULL);
5708 
5709 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5710 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5711 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5712 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5713 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5714 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5715 		adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5716 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5717 		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5718 
5719 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5720 
5721 	for (i = 0; i < me_hdr->jt_size; i++)
5722 		WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5723 			     le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5724 
5725 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5726 
5727 	return 0;
5728 }
5729 
5730 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5731 {
5732 	int r;
5733 
5734 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5735 		return -EINVAL;
5736 
5737 	gfx_v10_0_cp_gfx_enable(adev, false);
5738 
5739 	r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5740 	if (r) {
5741 		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5742 		return r;
5743 	}
5744 
5745 	r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5746 	if (r) {
5747 		dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5748 		return r;
5749 	}
5750 
5751 	r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5752 	if (r) {
5753 		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5754 		return r;
5755 	}
5756 
5757 	return 0;
5758 }
5759 
5760 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5761 {
5762 	struct amdgpu_ring *ring;
5763 	const struct cs_section_def *sect = NULL;
5764 	const struct cs_extent_def *ext = NULL;
5765 	int r, i;
5766 	int ctx_reg_offset;
5767 
5768 	/* init the CP */
5769 	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5770 		     adev->gfx.config.max_hw_contexts - 1);
5771 	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5772 
5773 	gfx_v10_0_cp_gfx_enable(adev, true);
5774 
5775 	ring = &adev->gfx.gfx_ring[0];
5776 	r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5777 	if (r) {
5778 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5779 		return r;
5780 	}
5781 
5782 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5783 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5784 
5785 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5786 	amdgpu_ring_write(ring, 0x80000000);
5787 	amdgpu_ring_write(ring, 0x80000000);
5788 
5789 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5790 		for (ext = sect->section; ext->extent != NULL; ++ext) {
5791 			if (sect->id == SECT_CONTEXT) {
5792 				amdgpu_ring_write(ring,
5793 						  PACKET3(PACKET3_SET_CONTEXT_REG,
5794 							  ext->reg_count));
5795 				amdgpu_ring_write(ring, ext->reg_index -
5796 						  PACKET3_SET_CONTEXT_REG_START);
5797 				for (i = 0; i < ext->reg_count; i++)
5798 					amdgpu_ring_write(ring, ext->extent[i]);
5799 			}
5800 		}
5801 	}
5802 
5803 	ctx_reg_offset =
5804 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5805 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5806 	amdgpu_ring_write(ring, ctx_reg_offset);
5807 	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5808 
5809 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5810 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5811 
5812 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5813 	amdgpu_ring_write(ring, 0);
5814 
5815 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5816 	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5817 	amdgpu_ring_write(ring, 0x8000);
5818 	amdgpu_ring_write(ring, 0x8000);
5819 
5820 	amdgpu_ring_commit(ring);
5821 
5822 	/* submit cs packet to copy state 0 to next available state */
5823 	if (adev->gfx.num_gfx_rings > 1) {
5824 		/* maximum supported gfx ring is 2 */
5825 		ring = &adev->gfx.gfx_ring[1];
5826 		r = amdgpu_ring_alloc(ring, 2);
5827 		if (r) {
5828 			DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5829 			return r;
5830 		}
5831 
5832 		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5833 		amdgpu_ring_write(ring, 0);
5834 
5835 		amdgpu_ring_commit(ring);
5836 	}
5837 	return 0;
5838 }
5839 
5840 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5841 					 CP_PIPE_ID pipe)
5842 {
5843 	u32 tmp;
5844 
5845 	tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5846 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5847 
5848 	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5849 }
5850 
5851 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5852 					  struct amdgpu_ring *ring)
5853 {
5854 	u32 tmp;
5855 
5856 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5857 	if (ring->use_doorbell) {
5858 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5859 				    DOORBELL_OFFSET, ring->doorbell_index);
5860 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5861 				    DOORBELL_EN, 1);
5862 	} else {
5863 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5864 				    DOORBELL_EN, 0);
5865 	}
5866 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5867 	switch (adev->asic_type) {
5868 	case CHIP_SIENNA_CICHLID:
5869 	case CHIP_NAVY_FLOUNDER:
5870 	case CHIP_VANGOGH:
5871 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5872 				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5873 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5874 
5875 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5876 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5877 		break;
5878 	default:
5879 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5880 				    DOORBELL_RANGE_LOWER, ring->doorbell_index);
5881 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5882 
5883 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5884 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5885 		break;
5886 	}
5887 }
5888 
5889 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5890 {
5891 	struct amdgpu_ring *ring;
5892 	u32 tmp;
5893 	u32 rb_bufsz;
5894 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
5895 	u32 i;
5896 
5897 	/* Set the write pointer delay */
5898 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5899 
5900 	/* set the RB to use vmid 0 */
5901 	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5902 
5903 	/* Init gfx ring 0 for pipe 0 */
5904 	mutex_lock(&adev->srbm_mutex);
5905 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5906 
5907 	/* Set ring buffer size */
5908 	ring = &adev->gfx.gfx_ring[0];
5909 	rb_bufsz = order_base_2(ring->ring_size / 8);
5910 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5911 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5912 #ifdef __BIG_ENDIAN
5913 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5914 #endif
5915 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5916 
5917 	/* Initialize the ring buffer's write pointers */
5918 	ring->wptr = 0;
5919 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5920 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5921 
5922 	/* set the wb address wether it's enabled or not */
5923 	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5924 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5925 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5926 		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5927 
5928 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5929 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5930 		     lower_32_bits(wptr_gpu_addr));
5931 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5932 		     upper_32_bits(wptr_gpu_addr));
5933 
5934 	mdelay(1);
5935 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5936 
5937 	rb_addr = ring->gpu_addr >> 8;
5938 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5939 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5940 
5941 	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5942 
5943 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5944 	mutex_unlock(&adev->srbm_mutex);
5945 
5946 	/* Init gfx ring 1 for pipe 1 */
5947 	if (adev->gfx.num_gfx_rings > 1) {
5948 		mutex_lock(&adev->srbm_mutex);
5949 		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5950 		/* maximum supported gfx ring is 2 */
5951 		ring = &adev->gfx.gfx_ring[1];
5952 		rb_bufsz = order_base_2(ring->ring_size / 8);
5953 		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5954 		tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5955 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5956 		/* Initialize the ring buffer's write pointers */
5957 		ring->wptr = 0;
5958 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5959 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5960 		/* Set the wb address wether it's enabled or not */
5961 		rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5962 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5963 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5964 			     CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5965 		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5966 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5967 			     lower_32_bits(wptr_gpu_addr));
5968 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5969 			     upper_32_bits(wptr_gpu_addr));
5970 
5971 		mdelay(1);
5972 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5973 
5974 		rb_addr = ring->gpu_addr >> 8;
5975 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5976 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5977 		WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5978 
5979 		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5980 		mutex_unlock(&adev->srbm_mutex);
5981 	}
5982 	/* Switch to pipe 0 */
5983 	mutex_lock(&adev->srbm_mutex);
5984 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5985 	mutex_unlock(&adev->srbm_mutex);
5986 
5987 	/* start the ring */
5988 	gfx_v10_0_cp_gfx_start(adev);
5989 
5990 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5991 		ring = &adev->gfx.gfx_ring[i];
5992 		ring->sched.ready = true;
5993 	}
5994 
5995 	return 0;
5996 }
5997 
5998 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5999 {
6000 	if (enable) {
6001 		switch (adev->asic_type) {
6002 		case CHIP_SIENNA_CICHLID:
6003 		case CHIP_NAVY_FLOUNDER:
6004 		case CHIP_VANGOGH:
6005 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6006 			break;
6007 		default:
6008 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6009 			break;
6010 		}
6011 	} else {
6012 		switch (adev->asic_type) {
6013 		case CHIP_SIENNA_CICHLID:
6014 		case CHIP_NAVY_FLOUNDER:
6015 		case CHIP_VANGOGH:
6016 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6017 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6018 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6019 			break;
6020 		default:
6021 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6022 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6023 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6024 			break;
6025 		}
6026 		adev->gfx.kiq.ring.sched.ready = false;
6027 	}
6028 	udelay(50);
6029 }
6030 
6031 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6032 {
6033 	const struct gfx_firmware_header_v1_0 *mec_hdr;
6034 	const __le32 *fw_data;
6035 	unsigned i;
6036 	u32 tmp;
6037 	u32 usec_timeout = 50000; /* Wait for 50 ms */
6038 
6039 	if (!adev->gfx.mec_fw)
6040 		return -EINVAL;
6041 
6042 	gfx_v10_0_cp_compute_enable(adev, false);
6043 
6044 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6045 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6046 
6047 	fw_data = (const __le32 *)
6048 		(adev->gfx.mec_fw->data +
6049 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6050 
6051 	/* Trigger an invalidation of the L1 instruction caches */
6052 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6053 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6054 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6055 
6056 	/* Wait for invalidation complete */
6057 	for (i = 0; i < usec_timeout; i++) {
6058 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6059 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6060 				       INVALIDATE_CACHE_COMPLETE))
6061 			break;
6062 		udelay(1);
6063 	}
6064 
6065 	if (i >= usec_timeout) {
6066 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6067 		return -EINVAL;
6068 	}
6069 
6070 	if (amdgpu_emu_mode == 1)
6071 		adev->nbio.funcs->hdp_flush(adev, NULL);
6072 
6073 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6074 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6075 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6076 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6077 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6078 
6079 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6080 		     0xFFFFF000);
6081 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6082 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6083 
6084 	/* MEC1 */
6085 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6086 
6087 	for (i = 0; i < mec_hdr->jt_size; i++)
6088 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6089 			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6090 
6091 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6092 
6093 	/*
6094 	 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6095 	 * different microcode than MEC1.
6096 	 */
6097 
6098 	return 0;
6099 }
6100 
6101 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6102 {
6103 	uint32_t tmp;
6104 	struct amdgpu_device *adev = ring->adev;
6105 
6106 	/* tell RLC which is KIQ queue */
6107 	switch (adev->asic_type) {
6108 	case CHIP_SIENNA_CICHLID:
6109 	case CHIP_NAVY_FLOUNDER:
6110 	case CHIP_VANGOGH:
6111 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6112 		tmp &= 0xffffff00;
6113 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6114 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6115 		tmp |= 0x80;
6116 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6117 		break;
6118 	default:
6119 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6120 		tmp &= 0xffffff00;
6121 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6122 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6123 		tmp |= 0x80;
6124 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6125 		break;
6126 	}
6127 }
6128 
6129 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6130 {
6131 	struct amdgpu_device *adev = ring->adev;
6132 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6133 	uint64_t hqd_gpu_addr, wb_gpu_addr;
6134 	uint32_t tmp;
6135 	uint32_t rb_bufsz;
6136 
6137 	/* set up gfx hqd wptr */
6138 	mqd->cp_gfx_hqd_wptr = 0;
6139 	mqd->cp_gfx_hqd_wptr_hi = 0;
6140 
6141 	/* set the pointer to the MQD */
6142 	mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6143 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6144 
6145 	/* set up mqd control */
6146 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6147 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6148 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6149 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6150 	mqd->cp_gfx_mqd_control = tmp;
6151 
6152 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6153 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6154 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6155 	mqd->cp_gfx_hqd_vmid = 0;
6156 
6157 	/* set up default queue priority level
6158 	 * 0x0 = low priority, 0x1 = high priority */
6159 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6160 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6161 	mqd->cp_gfx_hqd_queue_priority = tmp;
6162 
6163 	/* set up time quantum */
6164 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6165 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6166 	mqd->cp_gfx_hqd_quantum = tmp;
6167 
6168 	/* set up gfx hqd base. this is similar as CP_RB_BASE */
6169 	hqd_gpu_addr = ring->gpu_addr >> 8;
6170 	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6171 	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6172 
6173 	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6174 	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6175 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6176 	mqd->cp_gfx_hqd_rptr_addr_hi =
6177 		upper_32_bits(wb_gpu_addr) & 0xffff;
6178 
6179 	/* set up rb_wptr_poll addr */
6180 	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6181 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6182 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6183 
6184 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6185 	rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6186 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6187 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6188 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6189 #ifdef __BIG_ENDIAN
6190 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6191 #endif
6192 	mqd->cp_gfx_hqd_cntl = tmp;
6193 
6194 	/* set up cp_doorbell_control */
6195 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6196 	if (ring->use_doorbell) {
6197 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6198 				    DOORBELL_OFFSET, ring->doorbell_index);
6199 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6200 				    DOORBELL_EN, 1);
6201 	} else
6202 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6203 				    DOORBELL_EN, 0);
6204 	mqd->cp_rb_doorbell_control = tmp;
6205 
6206 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6207 	ring->wptr = 0;
6208 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6209 
6210 	/* active the queue */
6211 	mqd->cp_gfx_hqd_active = 1;
6212 
6213 	return 0;
6214 }
6215 
6216 #ifdef BRING_UP_DEBUG
6217 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6218 {
6219 	struct amdgpu_device *adev = ring->adev;
6220 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6221 
6222 	/* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6223 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6224 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6225 
6226 	/* set GFX_MQD_BASE */
6227 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6228 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6229 
6230 	/* set GFX_MQD_CONTROL */
6231 	WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6232 
6233 	/* set GFX_HQD_VMID to 0 */
6234 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6235 
6236 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6237 			mqd->cp_gfx_hqd_queue_priority);
6238 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6239 
6240 	/* set GFX_HQD_BASE, similar as CP_RB_BASE */
6241 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6242 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6243 
6244 	/* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6245 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6246 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6247 
6248 	/* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6249 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6250 
6251 	/* set RB_WPTR_POLL_ADDR */
6252 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6253 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6254 
6255 	/* set RB_DOORBELL_CONTROL */
6256 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6257 
6258 	/* active the queue */
6259 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6260 
6261 	return 0;
6262 }
6263 #endif
6264 
6265 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6266 {
6267 	struct amdgpu_device *adev = ring->adev;
6268 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6269 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6270 
6271 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6272 		memset((void *)mqd, 0, sizeof(*mqd));
6273 		mutex_lock(&adev->srbm_mutex);
6274 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6275 		gfx_v10_0_gfx_mqd_init(ring);
6276 #ifdef BRING_UP_DEBUG
6277 		gfx_v10_0_gfx_queue_init_register(ring);
6278 #endif
6279 		nv_grbm_select(adev, 0, 0, 0, 0);
6280 		mutex_unlock(&adev->srbm_mutex);
6281 		if (adev->gfx.me.mqd_backup[mqd_idx])
6282 			memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6283 	} else if (amdgpu_in_reset(adev)) {
6284 		/* reset mqd with the backup copy */
6285 		if (adev->gfx.me.mqd_backup[mqd_idx])
6286 			memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6287 		/* reset the ring */
6288 		ring->wptr = 0;
6289 		adev->wb.wb[ring->wptr_offs] = 0;
6290 		amdgpu_ring_clear_ring(ring);
6291 #ifdef BRING_UP_DEBUG
6292 		mutex_lock(&adev->srbm_mutex);
6293 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6294 		gfx_v10_0_gfx_queue_init_register(ring);
6295 		nv_grbm_select(adev, 0, 0, 0, 0);
6296 		mutex_unlock(&adev->srbm_mutex);
6297 #endif
6298 	} else {
6299 		amdgpu_ring_clear_ring(ring);
6300 	}
6301 
6302 	return 0;
6303 }
6304 
6305 #ifndef BRING_UP_DEBUG
6306 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6307 {
6308 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6309 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6310 	int r, i;
6311 
6312 	if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6313 		return -EINVAL;
6314 
6315 	r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6316 					adev->gfx.num_gfx_rings);
6317 	if (r) {
6318 		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6319 		return r;
6320 	}
6321 
6322 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6323 		kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6324 
6325 	return amdgpu_ring_test_helper(kiq_ring);
6326 }
6327 #endif
6328 
6329 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6330 {
6331 	int r, i;
6332 	struct amdgpu_ring *ring;
6333 
6334 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6335 		ring = &adev->gfx.gfx_ring[i];
6336 
6337 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
6338 		if (unlikely(r != 0))
6339 			goto done;
6340 
6341 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6342 		if (!r) {
6343 			r = gfx_v10_0_gfx_init_queue(ring);
6344 			amdgpu_bo_kunmap(ring->mqd_obj);
6345 			ring->mqd_ptr = NULL;
6346 		}
6347 		amdgpu_bo_unreserve(ring->mqd_obj);
6348 		if (r)
6349 			goto done;
6350 	}
6351 #ifndef BRING_UP_DEBUG
6352 	r = gfx_v10_0_kiq_enable_kgq(adev);
6353 	if (r)
6354 		goto done;
6355 #endif
6356 	r = gfx_v10_0_cp_gfx_start(adev);
6357 	if (r)
6358 		goto done;
6359 
6360 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6361 		ring = &adev->gfx.gfx_ring[i];
6362 		ring->sched.ready = true;
6363 	}
6364 done:
6365 	return r;
6366 }
6367 
6368 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6369 {
6370 	struct amdgpu_device *adev = ring->adev;
6371 
6372 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6373 		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6374 			mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6375 			mqd->cp_hqd_queue_priority =
6376 				AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6377 		}
6378 	}
6379 }
6380 
6381 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6382 {
6383 	struct amdgpu_device *adev = ring->adev;
6384 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6385 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6386 	uint32_t tmp;
6387 
6388 	mqd->header = 0xC0310800;
6389 	mqd->compute_pipelinestat_enable = 0x00000001;
6390 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6391 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6392 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6393 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6394 	mqd->compute_misc_reserved = 0x00000003;
6395 
6396 	eop_base_addr = ring->eop_gpu_addr >> 8;
6397 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6398 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6399 
6400 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6401 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6402 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6403 			(order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6404 
6405 	mqd->cp_hqd_eop_control = tmp;
6406 
6407 	/* enable doorbell? */
6408 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6409 
6410 	if (ring->use_doorbell) {
6411 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6412 				    DOORBELL_OFFSET, ring->doorbell_index);
6413 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6414 				    DOORBELL_EN, 1);
6415 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6416 				    DOORBELL_SOURCE, 0);
6417 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6418 				    DOORBELL_HIT, 0);
6419 	} else {
6420 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6421 				    DOORBELL_EN, 0);
6422 	}
6423 
6424 	mqd->cp_hqd_pq_doorbell_control = tmp;
6425 
6426 	/* disable the queue if it's active */
6427 	ring->wptr = 0;
6428 	mqd->cp_hqd_dequeue_request = 0;
6429 	mqd->cp_hqd_pq_rptr = 0;
6430 	mqd->cp_hqd_pq_wptr_lo = 0;
6431 	mqd->cp_hqd_pq_wptr_hi = 0;
6432 
6433 	/* set the pointer to the MQD */
6434 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6435 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6436 
6437 	/* set MQD vmid to 0 */
6438 	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6439 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6440 	mqd->cp_mqd_control = tmp;
6441 
6442 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6443 	hqd_gpu_addr = ring->gpu_addr >> 8;
6444 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6445 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6446 
6447 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6448 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6449 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6450 			    (order_base_2(ring->ring_size / 4) - 1));
6451 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6452 			    ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6453 #ifdef __BIG_ENDIAN
6454 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6455 #endif
6456 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6457 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6458 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6459 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6460 	mqd->cp_hqd_pq_control = tmp;
6461 
6462 	/* set the wb address whether it's enabled or not */
6463 	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6464 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6465 	mqd->cp_hqd_pq_rptr_report_addr_hi =
6466 		upper_32_bits(wb_gpu_addr) & 0xffff;
6467 
6468 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6469 	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6470 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6471 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6472 
6473 	tmp = 0;
6474 	/* enable the doorbell if requested */
6475 	if (ring->use_doorbell) {
6476 		tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6477 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6478 				DOORBELL_OFFSET, ring->doorbell_index);
6479 
6480 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6481 				    DOORBELL_EN, 1);
6482 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6483 				    DOORBELL_SOURCE, 0);
6484 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6485 				    DOORBELL_HIT, 0);
6486 	}
6487 
6488 	mqd->cp_hqd_pq_doorbell_control = tmp;
6489 
6490 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6491 	ring->wptr = 0;
6492 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6493 
6494 	/* set the vmid for the queue */
6495 	mqd->cp_hqd_vmid = 0;
6496 
6497 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6498 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6499 	mqd->cp_hqd_persistent_state = tmp;
6500 
6501 	/* set MIN_IB_AVAIL_SIZE */
6502 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6503 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6504 	mqd->cp_hqd_ib_control = tmp;
6505 
6506 	/* set static priority for a compute queue/ring */
6507 	gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6508 
6509 	/* map_queues packet doesn't need activate the queue,
6510 	 * so only kiq need set this field.
6511 	 */
6512 	if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6513 		mqd->cp_hqd_active = 1;
6514 
6515 	return 0;
6516 }
6517 
6518 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6519 {
6520 	struct amdgpu_device *adev = ring->adev;
6521 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6522 	int j;
6523 
6524 	/* inactivate the queue */
6525 	if (amdgpu_sriov_vf(adev))
6526 		WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6527 
6528 	/* disable wptr polling */
6529 	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6530 
6531 	/* write the EOP addr */
6532 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6533 	       mqd->cp_hqd_eop_base_addr_lo);
6534 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6535 	       mqd->cp_hqd_eop_base_addr_hi);
6536 
6537 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6538 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6539 	       mqd->cp_hqd_eop_control);
6540 
6541 	/* enable doorbell? */
6542 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6543 	       mqd->cp_hqd_pq_doorbell_control);
6544 
6545 	/* disable the queue if it's active */
6546 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6547 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6548 		for (j = 0; j < adev->usec_timeout; j++) {
6549 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6550 				break;
6551 			udelay(1);
6552 		}
6553 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6554 		       mqd->cp_hqd_dequeue_request);
6555 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6556 		       mqd->cp_hqd_pq_rptr);
6557 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6558 		       mqd->cp_hqd_pq_wptr_lo);
6559 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6560 		       mqd->cp_hqd_pq_wptr_hi);
6561 	}
6562 
6563 	/* set the pointer to the MQD */
6564 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6565 	       mqd->cp_mqd_base_addr_lo);
6566 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6567 	       mqd->cp_mqd_base_addr_hi);
6568 
6569 	/* set MQD vmid to 0 */
6570 	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6571 	       mqd->cp_mqd_control);
6572 
6573 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6574 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6575 	       mqd->cp_hqd_pq_base_lo);
6576 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6577 	       mqd->cp_hqd_pq_base_hi);
6578 
6579 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6580 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6581 	       mqd->cp_hqd_pq_control);
6582 
6583 	/* set the wb address whether it's enabled or not */
6584 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6585 		mqd->cp_hqd_pq_rptr_report_addr_lo);
6586 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6587 		mqd->cp_hqd_pq_rptr_report_addr_hi);
6588 
6589 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6590 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6591 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
6592 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6593 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
6594 
6595 	/* enable the doorbell if requested */
6596 	if (ring->use_doorbell) {
6597 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6598 			(adev->doorbell_index.kiq * 2) << 2);
6599 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6600 			(adev->doorbell_index.userqueue_end * 2) << 2);
6601 	}
6602 
6603 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6604 	       mqd->cp_hqd_pq_doorbell_control);
6605 
6606 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6607 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6608 	       mqd->cp_hqd_pq_wptr_lo);
6609 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6610 	       mqd->cp_hqd_pq_wptr_hi);
6611 
6612 	/* set the vmid for the queue */
6613 	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6614 
6615 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6616 	       mqd->cp_hqd_persistent_state);
6617 
6618 	/* activate the queue */
6619 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6620 	       mqd->cp_hqd_active);
6621 
6622 	if (ring->use_doorbell)
6623 		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6624 
6625 	return 0;
6626 }
6627 
6628 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6629 {
6630 	struct amdgpu_device *adev = ring->adev;
6631 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6632 	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6633 
6634 	gfx_v10_0_kiq_setting(ring);
6635 
6636 	if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6637 		/* reset MQD to a clean status */
6638 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6639 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6640 
6641 		/* reset ring buffer */
6642 		ring->wptr = 0;
6643 		amdgpu_ring_clear_ring(ring);
6644 
6645 		mutex_lock(&adev->srbm_mutex);
6646 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6647 		gfx_v10_0_kiq_init_register(ring);
6648 		nv_grbm_select(adev, 0, 0, 0, 0);
6649 		mutex_unlock(&adev->srbm_mutex);
6650 	} else {
6651 		memset((void *)mqd, 0, sizeof(*mqd));
6652 		mutex_lock(&adev->srbm_mutex);
6653 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6654 		gfx_v10_0_compute_mqd_init(ring);
6655 		gfx_v10_0_kiq_init_register(ring);
6656 		nv_grbm_select(adev, 0, 0, 0, 0);
6657 		mutex_unlock(&adev->srbm_mutex);
6658 
6659 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6660 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6661 	}
6662 
6663 	return 0;
6664 }
6665 
6666 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6667 {
6668 	struct amdgpu_device *adev = ring->adev;
6669 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6670 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
6671 
6672 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6673 		memset((void *)mqd, 0, sizeof(*mqd));
6674 		mutex_lock(&adev->srbm_mutex);
6675 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6676 		gfx_v10_0_compute_mqd_init(ring);
6677 		nv_grbm_select(adev, 0, 0, 0, 0);
6678 		mutex_unlock(&adev->srbm_mutex);
6679 
6680 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6681 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6682 	} else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6683 		/* reset MQD to a clean status */
6684 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6685 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6686 
6687 		/* reset ring buffer */
6688 		ring->wptr = 0;
6689 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6690 		amdgpu_ring_clear_ring(ring);
6691 	} else {
6692 		amdgpu_ring_clear_ring(ring);
6693 	}
6694 
6695 	return 0;
6696 }
6697 
6698 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6699 {
6700 	struct amdgpu_ring *ring;
6701 	int r;
6702 
6703 	ring = &adev->gfx.kiq.ring;
6704 
6705 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
6706 	if (unlikely(r != 0))
6707 		return r;
6708 
6709 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6710 	if (unlikely(r != 0))
6711 		return r;
6712 
6713 	gfx_v10_0_kiq_init_queue(ring);
6714 	amdgpu_bo_kunmap(ring->mqd_obj);
6715 	ring->mqd_ptr = NULL;
6716 	amdgpu_bo_unreserve(ring->mqd_obj);
6717 	ring->sched.ready = true;
6718 	return 0;
6719 }
6720 
6721 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6722 {
6723 	struct amdgpu_ring *ring = NULL;
6724 	int r = 0, i;
6725 
6726 	gfx_v10_0_cp_compute_enable(adev, true);
6727 
6728 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6729 		ring = &adev->gfx.compute_ring[i];
6730 
6731 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
6732 		if (unlikely(r != 0))
6733 			goto done;
6734 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6735 		if (!r) {
6736 			r = gfx_v10_0_kcq_init_queue(ring);
6737 			amdgpu_bo_kunmap(ring->mqd_obj);
6738 			ring->mqd_ptr = NULL;
6739 		}
6740 		amdgpu_bo_unreserve(ring->mqd_obj);
6741 		if (r)
6742 			goto done;
6743 	}
6744 
6745 	r = amdgpu_gfx_enable_kcq(adev);
6746 done:
6747 	return r;
6748 }
6749 
6750 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6751 {
6752 	int r, i;
6753 	struct amdgpu_ring *ring;
6754 
6755 	if (!(adev->flags & AMD_IS_APU))
6756 		gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6757 
6758 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6759 		/* legacy firmware loading */
6760 		r = gfx_v10_0_cp_gfx_load_microcode(adev);
6761 		if (r)
6762 			return r;
6763 
6764 		r = gfx_v10_0_cp_compute_load_microcode(adev);
6765 		if (r)
6766 			return r;
6767 	}
6768 
6769 	r = gfx_v10_0_kiq_resume(adev);
6770 	if (r)
6771 		return r;
6772 
6773 	r = gfx_v10_0_kcq_resume(adev);
6774 	if (r)
6775 		return r;
6776 
6777 	if (!amdgpu_async_gfx_ring) {
6778 		r = gfx_v10_0_cp_gfx_resume(adev);
6779 		if (r)
6780 			return r;
6781 	} else {
6782 		r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6783 		if (r)
6784 			return r;
6785 	}
6786 
6787 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6788 		ring = &adev->gfx.gfx_ring[i];
6789 		r = amdgpu_ring_test_helper(ring);
6790 		if (r)
6791 			return r;
6792 	}
6793 
6794 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6795 		ring = &adev->gfx.compute_ring[i];
6796 		r = amdgpu_ring_test_helper(ring);
6797 		if (r)
6798 			return r;
6799 	}
6800 
6801 	return 0;
6802 }
6803 
6804 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6805 {
6806 	gfx_v10_0_cp_gfx_enable(adev, enable);
6807 	gfx_v10_0_cp_compute_enable(adev, enable);
6808 }
6809 
6810 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6811 {
6812 	uint32_t data, pattern = 0xDEADBEEF;
6813 
6814 	/* check if mmVGT_ESGS_RING_SIZE_UMD
6815 	 * has been remapped to mmVGT_ESGS_RING_SIZE */
6816 	switch (adev->asic_type) {
6817 	case CHIP_SIENNA_CICHLID:
6818 	case CHIP_NAVY_FLOUNDER:
6819 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6820 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6821 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6822 
6823 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6824 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6825 			return true;
6826 		} else {
6827 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6828 			return false;
6829 		}
6830 		break;
6831 	case CHIP_VANGOGH:
6832 		return true;
6833 	default:
6834 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6835 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6836 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6837 
6838 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6839 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6840 			return true;
6841 		} else {
6842 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6843 			return false;
6844 		}
6845 		break;
6846 	}
6847 }
6848 
6849 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6850 {
6851 	uint32_t data;
6852 
6853 	/* initialize cam_index to 0
6854 	 * index will auto-inc after each data writting */
6855 	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6856 
6857 	switch (adev->asic_type) {
6858 	case CHIP_SIENNA_CICHLID:
6859 	case CHIP_NAVY_FLOUNDER:
6860 	case CHIP_VANGOGH:
6861 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6862 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6863 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6864 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6865 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6866 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6867 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6868 
6869 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6870 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6871 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6872 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6873 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6874 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6875 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6876 
6877 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6878 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6879 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6880 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6881 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6882 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6883 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6884 
6885 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6886 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6887 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6888 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6889 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6890 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6891 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6892 
6893 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6894 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6895 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6896 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6897 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6898 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6899 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6900 
6901 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6902 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6903 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6904 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6905 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6906 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6907 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6908 
6909 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6910 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6911 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6912 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6913 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6914 		break;
6915 	default:
6916 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6917 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6918 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6919 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6920 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6921 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6922 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6923 
6924 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6925 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6926 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6927 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6928 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6929 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6930 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6931 
6932 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6933 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6934 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6935 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6936 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6937 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6938 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6939 
6940 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6941 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6942 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6943 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6944 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6945 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6946 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6947 
6948 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6949 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6950 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6951 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6952 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6953 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6954 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6955 
6956 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6957 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6958 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6959 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6960 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6961 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6962 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6963 
6964 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6965 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6966 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6967 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6968 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6969 		break;
6970 	}
6971 
6972 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6973 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6974 }
6975 
6976 static int gfx_v10_0_hw_init(void *handle)
6977 {
6978 	int r;
6979 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6980 
6981 	if (!amdgpu_emu_mode)
6982 		gfx_v10_0_init_golden_registers(adev);
6983 
6984 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6985 		/**
6986 		 * For gfx 10, rlc firmware loading relies on smu firmware is
6987 		 * loaded firstly, so in direct type, it has to load smc ucode
6988 		 * here before rlc.
6989 		 */
6990 		if (adev->smu.ppt_funcs != NULL) {
6991 			r = smu_load_microcode(&adev->smu);
6992 			if (r)
6993 				return r;
6994 
6995 			r = smu_check_fw_status(&adev->smu);
6996 			if (r) {
6997 				pr_err("SMC firmware status is not correct\n");
6998 				return r;
6999 			}
7000 		}
7001 	}
7002 
7003 	/* if GRBM CAM not remapped, set up the remapping */
7004 	if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7005 		gfx_v10_0_setup_grbm_cam_remapping(adev);
7006 
7007 	gfx_v10_0_constants_init(adev);
7008 
7009 	r = gfx_v10_0_rlc_resume(adev);
7010 	if (r)
7011 		return r;
7012 
7013 	/*
7014 	 * init golden registers and rlc resume may override some registers,
7015 	 * reconfig them here
7016 	 */
7017 	gfx_v10_0_tcp_harvest(adev);
7018 
7019 	r = gfx_v10_0_cp_resume(adev);
7020 	if (r)
7021 		return r;
7022 
7023 	return r;
7024 }
7025 
7026 #ifndef BRING_UP_DEBUG
7027 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7028 {
7029 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7030 	struct amdgpu_ring *kiq_ring = &kiq->ring;
7031 	int i;
7032 
7033 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7034 		return -EINVAL;
7035 
7036 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7037 					adev->gfx.num_gfx_rings))
7038 		return -ENOMEM;
7039 
7040 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7041 		kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7042 					   PREEMPT_QUEUES, 0, 0);
7043 
7044 	return amdgpu_ring_test_helper(kiq_ring);
7045 }
7046 #endif
7047 
7048 static int gfx_v10_0_hw_fini(void *handle)
7049 {
7050 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7051 	int r;
7052 	uint32_t tmp;
7053 
7054 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7055 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7056 
7057 	if (!adev->in_pci_err_recovery) {
7058 #ifndef BRING_UP_DEBUG
7059 		if (amdgpu_async_gfx_ring) {
7060 			r = gfx_v10_0_kiq_disable_kgq(adev);
7061 			if (r)
7062 				DRM_ERROR("KGQ disable failed\n");
7063 		}
7064 #endif
7065 		if (amdgpu_gfx_disable_kcq(adev))
7066 			DRM_ERROR("KCQ disable failed\n");
7067 	}
7068 
7069 	if (amdgpu_sriov_vf(adev)) {
7070 		gfx_v10_0_cp_gfx_enable(adev, false);
7071 		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7072 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7073 		tmp &= 0xffffff00;
7074 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7075 
7076 		return 0;
7077 	}
7078 	gfx_v10_0_cp_enable(adev, false);
7079 	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7080 
7081 	return 0;
7082 }
7083 
7084 static int gfx_v10_0_suspend(void *handle)
7085 {
7086 	return gfx_v10_0_hw_fini(handle);
7087 }
7088 
7089 static int gfx_v10_0_resume(void *handle)
7090 {
7091 	return gfx_v10_0_hw_init(handle);
7092 }
7093 
7094 static bool gfx_v10_0_is_idle(void *handle)
7095 {
7096 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7097 
7098 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7099 				GRBM_STATUS, GUI_ACTIVE))
7100 		return false;
7101 	else
7102 		return true;
7103 }
7104 
7105 static int gfx_v10_0_wait_for_idle(void *handle)
7106 {
7107 	unsigned i;
7108 	u32 tmp;
7109 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7110 
7111 	for (i = 0; i < adev->usec_timeout; i++) {
7112 		/* read MC_STATUS */
7113 		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7114 			GRBM_STATUS__GUI_ACTIVE_MASK;
7115 
7116 		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7117 			return 0;
7118 		udelay(1);
7119 	}
7120 	return -ETIMEDOUT;
7121 }
7122 
7123 static int gfx_v10_0_soft_reset(void *handle)
7124 {
7125 	u32 grbm_soft_reset = 0;
7126 	u32 tmp;
7127 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7128 
7129 	/* GRBM_STATUS */
7130 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7131 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7132 		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7133 		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7134 		   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7135 		   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7136 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7137 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7138 						1);
7139 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7140 						GRBM_SOFT_RESET, SOFT_RESET_GFX,
7141 						1);
7142 	}
7143 
7144 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7145 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7146 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7147 						1);
7148 	}
7149 
7150 	/* GRBM_STATUS2 */
7151 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7152 	switch (adev->asic_type) {
7153 	case CHIP_SIENNA_CICHLID:
7154 	case CHIP_NAVY_FLOUNDER:
7155 	case CHIP_VANGOGH:
7156 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7157 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7158 							GRBM_SOFT_RESET,
7159 							SOFT_RESET_RLC,
7160 							1);
7161 		break;
7162 	default:
7163 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7164 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7165 							GRBM_SOFT_RESET,
7166 							SOFT_RESET_RLC,
7167 							1);
7168 		break;
7169 	}
7170 
7171 	if (grbm_soft_reset) {
7172 		/* stop the rlc */
7173 		gfx_v10_0_rlc_stop(adev);
7174 
7175 		/* Disable GFX parsing/prefetching */
7176 		gfx_v10_0_cp_gfx_enable(adev, false);
7177 
7178 		/* Disable MEC parsing/prefetching */
7179 		gfx_v10_0_cp_compute_enable(adev, false);
7180 
7181 		if (grbm_soft_reset) {
7182 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7183 			tmp |= grbm_soft_reset;
7184 			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7185 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7186 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7187 
7188 			udelay(50);
7189 
7190 			tmp &= ~grbm_soft_reset;
7191 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7192 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7193 		}
7194 
7195 		/* Wait a little for things to settle down */
7196 		udelay(50);
7197 	}
7198 	return 0;
7199 }
7200 
7201 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7202 {
7203 	uint64_t clock;
7204 
7205 	amdgpu_gfx_off_ctrl(adev, false);
7206 	mutex_lock(&adev->gfx.gpu_clock_mutex);
7207 	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7208 		((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7209 	mutex_unlock(&adev->gfx.gpu_clock_mutex);
7210 	amdgpu_gfx_off_ctrl(adev, true);
7211 	return clock;
7212 }
7213 
7214 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7215 					   uint32_t vmid,
7216 					   uint32_t gds_base, uint32_t gds_size,
7217 					   uint32_t gws_base, uint32_t gws_size,
7218 					   uint32_t oa_base, uint32_t oa_size)
7219 {
7220 	struct amdgpu_device *adev = ring->adev;
7221 
7222 	/* GDS Base */
7223 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7224 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7225 				    gds_base);
7226 
7227 	/* GDS Size */
7228 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7229 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7230 				    gds_size);
7231 
7232 	/* GWS */
7233 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7234 				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7235 				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7236 
7237 	/* OA */
7238 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7239 				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7240 				    (1 << (oa_size + oa_base)) - (1 << oa_base));
7241 }
7242 
7243 static int gfx_v10_0_early_init(void *handle)
7244 {
7245 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7246 
7247 	switch (adev->asic_type) {
7248 	case CHIP_NAVI10:
7249 	case CHIP_NAVI14:
7250 	case CHIP_NAVI12:
7251 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7252 		break;
7253 	case CHIP_SIENNA_CICHLID:
7254 	case CHIP_NAVY_FLOUNDER:
7255 	case CHIP_VANGOGH:
7256 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7257 		break;
7258 	default:
7259 		break;
7260 	}
7261 
7262 	adev->gfx.num_compute_rings = amdgpu_num_kcq;
7263 
7264 	gfx_v10_0_set_kiq_pm4_funcs(adev);
7265 	gfx_v10_0_set_ring_funcs(adev);
7266 	gfx_v10_0_set_irq_funcs(adev);
7267 	gfx_v10_0_set_gds_init(adev);
7268 	gfx_v10_0_set_rlc_funcs(adev);
7269 
7270 	return 0;
7271 }
7272 
7273 static int gfx_v10_0_late_init(void *handle)
7274 {
7275 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7276 	int r;
7277 
7278 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7279 	if (r)
7280 		return r;
7281 
7282 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7283 	if (r)
7284 		return r;
7285 
7286 	return 0;
7287 }
7288 
7289 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7290 {
7291 	uint32_t rlc_cntl;
7292 
7293 	/* if RLC is not enabled, do nothing */
7294 	rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7295 	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7296 }
7297 
7298 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7299 {
7300 	uint32_t data;
7301 	unsigned i;
7302 
7303 	data = RLC_SAFE_MODE__CMD_MASK;
7304 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7305 
7306 	switch (adev->asic_type) {
7307 	case CHIP_SIENNA_CICHLID:
7308 	case CHIP_NAVY_FLOUNDER:
7309 	case CHIP_VANGOGH:
7310 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7311 
7312 		/* wait for RLC_SAFE_MODE */
7313 		for (i = 0; i < adev->usec_timeout; i++) {
7314 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7315 					   RLC_SAFE_MODE, CMD))
7316 				break;
7317 			udelay(1);
7318 		}
7319 		break;
7320 	default:
7321 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7322 
7323 		/* wait for RLC_SAFE_MODE */
7324 		for (i = 0; i < adev->usec_timeout; i++) {
7325 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7326 					   RLC_SAFE_MODE, CMD))
7327 				break;
7328 			udelay(1);
7329 		}
7330 		break;
7331 	}
7332 }
7333 
7334 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7335 {
7336 	uint32_t data;
7337 
7338 	data = RLC_SAFE_MODE__CMD_MASK;
7339 	switch (adev->asic_type) {
7340 	case CHIP_SIENNA_CICHLID:
7341 	case CHIP_NAVY_FLOUNDER:
7342 	case CHIP_VANGOGH:
7343 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7344 		break;
7345 	default:
7346 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7347 		break;
7348 	}
7349 }
7350 
7351 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7352 						      bool enable)
7353 {
7354 	uint32_t data, def;
7355 
7356 	/* It is disabled by HW by default */
7357 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7358 		/* 0 - Disable some blocks' MGCG */
7359 		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7360 		WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7361 		WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7362 		WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7363 
7364 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
7365 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7366 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7367 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7368 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7369 			  RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7370 
7371 		if (def != data)
7372 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7373 
7374 		/* MGLS is a global flag to control all MGLS in GFX */
7375 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7376 			/* 2 - RLC memory Light sleep */
7377 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7378 				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7379 				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7380 				if (def != data)
7381 					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7382 			}
7383 			/* 3 - CP memory Light sleep */
7384 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7385 				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7386 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7387 				if (def != data)
7388 					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7389 			}
7390 		}
7391 	} else {
7392 		/* 1 - MGCG_OVERRIDE */
7393 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7394 		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7395 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7396 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7397 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7398 		if (def != data)
7399 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7400 
7401 		/* 2 - disable MGLS in CP */
7402 		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7403 		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7404 			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7405 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7406 		}
7407 
7408 		/* 3 - disable MGLS in RLC */
7409 		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7410 		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7411 			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7412 			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7413 		}
7414 
7415 	}
7416 }
7417 
7418 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7419 					   bool enable)
7420 {
7421 	uint32_t data, def;
7422 
7423 	/* Enable 3D CGCG/CGLS */
7424 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7425 		/* write cmd to clear cgcg/cgls ov */
7426 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7427 		/* unset CGCG override */
7428 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7429 		/* update CGCG and CGLS override bits */
7430 		if (def != data)
7431 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7432 		/* enable 3Dcgcg FSM(0x0000363f) */
7433 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7434 		data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7435 			RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7436 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7437 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7438 				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7439 		if (def != data)
7440 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7441 
7442 		/* set IDLE_POLL_COUNT(0x00900100) */
7443 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7444 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7445 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7446 		if (def != data)
7447 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7448 	} else {
7449 		/* Disable CGCG/CGLS */
7450 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7451 		/* disable cgcg, cgls should be disabled */
7452 		data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7453 			  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7454 		/* disable cgcg and cgls in FSM */
7455 		if (def != data)
7456 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7457 	}
7458 }
7459 
7460 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7461 						      bool enable)
7462 {
7463 	uint32_t def, data;
7464 
7465 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7466 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7467 		/* unset CGCG override */
7468 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7469 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7470 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7471 		else
7472 			data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7473 		/* update CGCG and CGLS override bits */
7474 		if (def != data)
7475 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7476 
7477 		/* enable cgcg FSM(0x0000363F) */
7478 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7479 		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7480 			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7481 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7482 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7483 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7484 		if (def != data)
7485 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7486 
7487 		/* set IDLE_POLL_COUNT(0x00900100) */
7488 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7489 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7490 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7491 		if (def != data)
7492 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7493 	} else {
7494 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7495 		/* reset CGCG/CGLS bits */
7496 		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7497 		/* disable cgcg and cgls in FSM */
7498 		if (def != data)
7499 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7500 	}
7501 }
7502 
7503 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7504 					    bool enable)
7505 {
7506 	amdgpu_gfx_rlc_enter_safe_mode(adev);
7507 
7508 	if (enable) {
7509 		/* CGCG/CGLS should be enabled after MGCG/MGLS
7510 		 * ===  MGCG + MGLS ===
7511 		 */
7512 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7513 		/* ===  CGCG /CGLS for GFX 3D Only === */
7514 		gfx_v10_0_update_3d_clock_gating(adev, enable);
7515 		/* ===  CGCG + CGLS === */
7516 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7517 	} else {
7518 		/* CGCG/CGLS should be disabled before MGCG/MGLS
7519 		 * ===  CGCG + CGLS ===
7520 		 */
7521 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7522 		/* ===  CGCG /CGLS for GFX 3D Only === */
7523 		gfx_v10_0_update_3d_clock_gating(adev, enable);
7524 		/* ===  MGCG + MGLS === */
7525 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7526 	}
7527 
7528 	if (adev->cg_flags &
7529 	    (AMD_CG_SUPPORT_GFX_MGCG |
7530 	     AMD_CG_SUPPORT_GFX_CGLS |
7531 	     AMD_CG_SUPPORT_GFX_CGCG |
7532 	     AMD_CG_SUPPORT_GFX_3D_CGCG |
7533 	     AMD_CG_SUPPORT_GFX_3D_CGLS))
7534 		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7535 
7536 	amdgpu_gfx_rlc_exit_safe_mode(adev);
7537 
7538 	return 0;
7539 }
7540 
7541 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7542 {
7543 	u32 reg, data;
7544 
7545 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7546 	if (amdgpu_sriov_is_pp_one_vf(adev))
7547 		data = RREG32_NO_KIQ(reg);
7548 	else
7549 		data = RREG32(reg);
7550 
7551 	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7552 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7553 
7554 	if (amdgpu_sriov_is_pp_one_vf(adev))
7555 		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7556 	else
7557 		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7558 }
7559 
7560 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7561 					uint32_t offset,
7562 					struct soc15_reg_rlcg *entries, int arr_size)
7563 {
7564 	int i;
7565 	uint32_t reg;
7566 
7567 	if (!entries)
7568 		return false;
7569 
7570 	for (i = 0; i < arr_size; i++) {
7571 		const struct soc15_reg_rlcg *entry;
7572 
7573 		entry = &entries[i];
7574 		reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7575 		if (offset == reg)
7576 			return true;
7577 	}
7578 
7579 	return false;
7580 }
7581 
7582 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7583 {
7584 	return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7585 }
7586 
7587 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7588 {
7589 	u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7590 
7591 	if (enable && (adev->cg_flags & AMD_PG_SUPPORT_GFX_PG))
7592 		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7593 	else
7594 		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7595 
7596 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7597 }
7598 
7599 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
7600 {
7601 	amdgpu_gfx_rlc_enter_safe_mode(adev);
7602 
7603 	gfx_v10_cntl_power_gating(adev, enable);
7604 
7605 	amdgpu_gfx_rlc_exit_safe_mode(adev);
7606 }
7607 
7608 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7609 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7610 	.set_safe_mode = gfx_v10_0_set_safe_mode,
7611 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
7612 	.init = gfx_v10_0_rlc_init,
7613 	.get_csb_size = gfx_v10_0_get_csb_size,
7614 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
7615 	.resume = gfx_v10_0_rlc_resume,
7616 	.stop = gfx_v10_0_rlc_stop,
7617 	.reset = gfx_v10_0_rlc_reset,
7618 	.start = gfx_v10_0_rlc_start,
7619 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
7620 };
7621 
7622 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7623 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7624 	.set_safe_mode = gfx_v10_0_set_safe_mode,
7625 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
7626 	.init = gfx_v10_0_rlc_init,
7627 	.get_csb_size = gfx_v10_0_get_csb_size,
7628 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
7629 	.resume = gfx_v10_0_rlc_resume,
7630 	.stop = gfx_v10_0_rlc_stop,
7631 	.reset = gfx_v10_0_rlc_reset,
7632 	.start = gfx_v10_0_rlc_start,
7633 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
7634 	.rlcg_wreg = gfx_v10_rlcg_wreg,
7635 	.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7636 };
7637 
7638 static int gfx_v10_0_set_powergating_state(void *handle,
7639 					  enum amd_powergating_state state)
7640 {
7641 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7642 	bool enable = (state == AMD_PG_STATE_GATE);
7643 
7644 	if (amdgpu_sriov_vf(adev))
7645 		return 0;
7646 
7647 	switch (adev->asic_type) {
7648 	case CHIP_NAVI10:
7649 	case CHIP_NAVI14:
7650 	case CHIP_NAVI12:
7651 	case CHIP_SIENNA_CICHLID:
7652 	case CHIP_NAVY_FLOUNDER:
7653 		amdgpu_gfx_off_ctrl(adev, enable);
7654 		break;
7655 	case CHIP_VANGOGH:
7656 		gfx_v10_cntl_pg(adev, enable);
7657 		break;
7658 	default:
7659 		break;
7660 	}
7661 	return 0;
7662 }
7663 
7664 static int gfx_v10_0_set_clockgating_state(void *handle,
7665 					  enum amd_clockgating_state state)
7666 {
7667 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7668 
7669 	if (amdgpu_sriov_vf(adev))
7670 		return 0;
7671 
7672 	switch (adev->asic_type) {
7673 	case CHIP_NAVI10:
7674 	case CHIP_NAVI14:
7675 	case CHIP_NAVI12:
7676 	case CHIP_SIENNA_CICHLID:
7677 	case CHIP_NAVY_FLOUNDER:
7678 	case CHIP_VANGOGH:
7679 		gfx_v10_0_update_gfx_clock_gating(adev,
7680 						 state == AMD_CG_STATE_GATE);
7681 		break;
7682 	default:
7683 		break;
7684 	}
7685 	return 0;
7686 }
7687 
7688 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7689 {
7690 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7691 	int data;
7692 
7693 	/* AMD_CG_SUPPORT_GFX_MGCG */
7694 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7695 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7696 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
7697 
7698 	/* AMD_CG_SUPPORT_GFX_CGCG */
7699 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7700 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7701 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
7702 
7703 	/* AMD_CG_SUPPORT_GFX_CGLS */
7704 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7705 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
7706 
7707 	/* AMD_CG_SUPPORT_GFX_RLC_LS */
7708 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7709 	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7710 		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7711 
7712 	/* AMD_CG_SUPPORT_GFX_CP_LS */
7713 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7714 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7715 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7716 
7717 	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
7718 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7719 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7720 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7721 
7722 	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
7723 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7724 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7725 }
7726 
7727 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7728 {
7729 	return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7730 }
7731 
7732 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7733 {
7734 	struct amdgpu_device *adev = ring->adev;
7735 	u64 wptr;
7736 
7737 	/* XXX check if swapping is necessary on BE */
7738 	if (ring->use_doorbell) {
7739 		wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7740 	} else {
7741 		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7742 		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7743 	}
7744 
7745 	return wptr;
7746 }
7747 
7748 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7749 {
7750 	struct amdgpu_device *adev = ring->adev;
7751 
7752 	if (ring->use_doorbell) {
7753 		/* XXX check if swapping is necessary on BE */
7754 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7755 		WDOORBELL64(ring->doorbell_index, ring->wptr);
7756 	} else {
7757 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7758 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7759 	}
7760 }
7761 
7762 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7763 {
7764 	return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7765 }
7766 
7767 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7768 {
7769 	u64 wptr;
7770 
7771 	/* XXX check if swapping is necessary on BE */
7772 	if (ring->use_doorbell)
7773 		wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7774 	else
7775 		BUG();
7776 	return wptr;
7777 }
7778 
7779 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7780 {
7781 	struct amdgpu_device *adev = ring->adev;
7782 
7783 	/* XXX check if swapping is necessary on BE */
7784 	if (ring->use_doorbell) {
7785 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7786 		WDOORBELL64(ring->doorbell_index, ring->wptr);
7787 	} else {
7788 		BUG(); /* only DOORBELL method supported on gfx10 now */
7789 	}
7790 }
7791 
7792 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7793 {
7794 	struct amdgpu_device *adev = ring->adev;
7795 	u32 ref_and_mask, reg_mem_engine;
7796 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7797 
7798 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7799 		switch (ring->me) {
7800 		case 1:
7801 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7802 			break;
7803 		case 2:
7804 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7805 			break;
7806 		default:
7807 			return;
7808 		}
7809 		reg_mem_engine = 0;
7810 	} else {
7811 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7812 		reg_mem_engine = 1; /* pfp */
7813 	}
7814 
7815 	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7816 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7817 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7818 			       ref_and_mask, ref_and_mask, 0x20);
7819 }
7820 
7821 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7822 				       struct amdgpu_job *job,
7823 				       struct amdgpu_ib *ib,
7824 				       uint32_t flags)
7825 {
7826 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7827 	u32 header, control = 0;
7828 
7829 	if (ib->flags & AMDGPU_IB_FLAG_CE)
7830 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7831 	else
7832 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7833 
7834 	control |= ib->length_dw | (vmid << 24);
7835 
7836 	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7837 		control |= INDIRECT_BUFFER_PRE_ENB(1);
7838 
7839 		if (flags & AMDGPU_IB_PREEMPTED)
7840 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
7841 
7842 		if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7843 			gfx_v10_0_ring_emit_de_meta(ring,
7844 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7845 	}
7846 
7847 	amdgpu_ring_write(ring, header);
7848 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7849 	amdgpu_ring_write(ring,
7850 #ifdef __BIG_ENDIAN
7851 		(2 << 0) |
7852 #endif
7853 		lower_32_bits(ib->gpu_addr));
7854 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7855 	amdgpu_ring_write(ring, control);
7856 }
7857 
7858 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7859 					   struct amdgpu_job *job,
7860 					   struct amdgpu_ib *ib,
7861 					   uint32_t flags)
7862 {
7863 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7864 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7865 
7866 	/* Currently, there is a high possibility to get wave ID mismatch
7867 	 * between ME and GDS, leading to a hw deadlock, because ME generates
7868 	 * different wave IDs than the GDS expects. This situation happens
7869 	 * randomly when at least 5 compute pipes use GDS ordered append.
7870 	 * The wave IDs generated by ME are also wrong after suspend/resume.
7871 	 * Those are probably bugs somewhere else in the kernel driver.
7872 	 *
7873 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7874 	 * GDS to 0 for this ring (me/pipe).
7875 	 */
7876 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7877 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7878 		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7879 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7880 	}
7881 
7882 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7883 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7884 	amdgpu_ring_write(ring,
7885 #ifdef __BIG_ENDIAN
7886 				(2 << 0) |
7887 #endif
7888 				lower_32_bits(ib->gpu_addr));
7889 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7890 	amdgpu_ring_write(ring, control);
7891 }
7892 
7893 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7894 				     u64 seq, unsigned flags)
7895 {
7896 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7897 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7898 
7899 	/* RELEASE_MEM - flush caches, send int */
7900 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7901 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7902 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
7903 				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7904 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
7905 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7906 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7907 				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7908 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7909 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7910 
7911 	/*
7912 	 * the address should be Qword aligned if 64bit write, Dword
7913 	 * aligned if only send 32bit data low (discard data high)
7914 	 */
7915 	if (write64bit)
7916 		BUG_ON(addr & 0x7);
7917 	else
7918 		BUG_ON(addr & 0x3);
7919 	amdgpu_ring_write(ring, lower_32_bits(addr));
7920 	amdgpu_ring_write(ring, upper_32_bits(addr));
7921 	amdgpu_ring_write(ring, lower_32_bits(seq));
7922 	amdgpu_ring_write(ring, upper_32_bits(seq));
7923 	amdgpu_ring_write(ring, 0);
7924 }
7925 
7926 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7927 {
7928 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7929 	uint32_t seq = ring->fence_drv.sync_seq;
7930 	uint64_t addr = ring->fence_drv.gpu_addr;
7931 
7932 	gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7933 			       upper_32_bits(addr), seq, 0xffffffff, 4);
7934 }
7935 
7936 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7937 					 unsigned vmid, uint64_t pd_addr)
7938 {
7939 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7940 
7941 	/* compute doesn't have PFP */
7942 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7943 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
7944 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7945 		amdgpu_ring_write(ring, 0x0);
7946 	}
7947 }
7948 
7949 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7950 					  u64 seq, unsigned int flags)
7951 {
7952 	struct amdgpu_device *adev = ring->adev;
7953 
7954 	/* we only allocate 32bit for each seq wb address */
7955 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7956 
7957 	/* write fence seq to the "addr" */
7958 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7959 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7960 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7961 	amdgpu_ring_write(ring, lower_32_bits(addr));
7962 	amdgpu_ring_write(ring, upper_32_bits(addr));
7963 	amdgpu_ring_write(ring, lower_32_bits(seq));
7964 
7965 	if (flags & AMDGPU_FENCE_FLAG_INT) {
7966 		/* set register to trigger INT */
7967 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7968 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7969 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7970 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7971 		amdgpu_ring_write(ring, 0);
7972 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7973 	}
7974 }
7975 
7976 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7977 {
7978 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7979 	amdgpu_ring_write(ring, 0);
7980 }
7981 
7982 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7983 					 uint32_t flags)
7984 {
7985 	uint32_t dw2 = 0;
7986 
7987 	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7988 		gfx_v10_0_ring_emit_ce_meta(ring,
7989 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7990 
7991 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7992 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7993 		/* set load_global_config & load_global_uconfig */
7994 		dw2 |= 0x8001;
7995 		/* set load_cs_sh_regs */
7996 		dw2 |= 0x01000000;
7997 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
7998 		dw2 |= 0x10002;
7999 
8000 		/* set load_ce_ram if preamble presented */
8001 		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8002 			dw2 |= 0x10000000;
8003 	} else {
8004 		/* still load_ce_ram if this is the first time preamble presented
8005 		 * although there is no context switch happens.
8006 		 */
8007 		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8008 			dw2 |= 0x10000000;
8009 	}
8010 
8011 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8012 	amdgpu_ring_write(ring, dw2);
8013 	amdgpu_ring_write(ring, 0);
8014 }
8015 
8016 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8017 {
8018 	unsigned ret;
8019 
8020 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8021 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8022 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8023 	amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8024 	ret = ring->wptr & ring->buf_mask;
8025 	amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8026 
8027 	return ret;
8028 }
8029 
8030 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8031 {
8032 	unsigned cur;
8033 	BUG_ON(offset > ring->buf_mask);
8034 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
8035 
8036 	cur = (ring->wptr - 1) & ring->buf_mask;
8037 	if (likely(cur > offset))
8038 		ring->ring[offset] = cur - offset;
8039 	else
8040 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8041 }
8042 
8043 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8044 {
8045 	int i, r = 0;
8046 	struct amdgpu_device *adev = ring->adev;
8047 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8048 	struct amdgpu_ring *kiq_ring = &kiq->ring;
8049 	unsigned long flags;
8050 
8051 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8052 		return -EINVAL;
8053 
8054 	spin_lock_irqsave(&kiq->ring_lock, flags);
8055 
8056 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8057 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
8058 		return -ENOMEM;
8059 	}
8060 
8061 	/* assert preemption condition */
8062 	amdgpu_ring_set_preempt_cond_exec(ring, false);
8063 
8064 	/* assert IB preemption, emit the trailing fence */
8065 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8066 				   ring->trail_fence_gpu_addr,
8067 				   ++ring->trail_seq);
8068 	amdgpu_ring_commit(kiq_ring);
8069 
8070 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
8071 
8072 	/* poll the trailing fence */
8073 	for (i = 0; i < adev->usec_timeout; i++) {
8074 		if (ring->trail_seq ==
8075 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8076 			break;
8077 		udelay(1);
8078 	}
8079 
8080 	if (i >= adev->usec_timeout) {
8081 		r = -EINVAL;
8082 		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8083 	}
8084 
8085 	/* deassert preemption condition */
8086 	amdgpu_ring_set_preempt_cond_exec(ring, true);
8087 	return r;
8088 }
8089 
8090 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8091 {
8092 	struct amdgpu_device *adev = ring->adev;
8093 	struct v10_ce_ib_state ce_payload = {0};
8094 	uint64_t csa_addr;
8095 	int cnt;
8096 
8097 	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8098 	csa_addr = amdgpu_csa_vaddr(ring->adev);
8099 
8100 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8101 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8102 				 WRITE_DATA_DST_SEL(8) |
8103 				 WR_CONFIRM) |
8104 				 WRITE_DATA_CACHE_POLICY(0));
8105 	amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8106 			      offsetof(struct v10_gfx_meta_data, ce_payload)));
8107 	amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8108 			      offsetof(struct v10_gfx_meta_data, ce_payload)));
8109 
8110 	if (resume)
8111 		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8112 					   offsetof(struct v10_gfx_meta_data,
8113 						    ce_payload),
8114 					   sizeof(ce_payload) >> 2);
8115 	else
8116 		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8117 					   sizeof(ce_payload) >> 2);
8118 }
8119 
8120 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8121 {
8122 	struct amdgpu_device *adev = ring->adev;
8123 	struct v10_de_ib_state de_payload = {0};
8124 	uint64_t csa_addr, gds_addr;
8125 	int cnt;
8126 
8127 	csa_addr = amdgpu_csa_vaddr(ring->adev);
8128 	gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8129 			 PAGE_SIZE);
8130 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8131 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8132 
8133 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8134 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8135 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8136 				 WRITE_DATA_DST_SEL(8) |
8137 				 WR_CONFIRM) |
8138 				 WRITE_DATA_CACHE_POLICY(0));
8139 	amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8140 			      offsetof(struct v10_gfx_meta_data, de_payload)));
8141 	amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8142 			      offsetof(struct v10_gfx_meta_data, de_payload)));
8143 
8144 	if (resume)
8145 		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8146 					   offsetof(struct v10_gfx_meta_data,
8147 						    de_payload),
8148 					   sizeof(de_payload) >> 2);
8149 	else
8150 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8151 					   sizeof(de_payload) >> 2);
8152 }
8153 
8154 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8155 				    bool secure)
8156 {
8157 	uint32_t v = secure ? FRAME_TMZ : 0;
8158 
8159 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8160 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8161 }
8162 
8163 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8164 				     uint32_t reg_val_offs)
8165 {
8166 	struct amdgpu_device *adev = ring->adev;
8167 
8168 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8169 	amdgpu_ring_write(ring, 0 |	/* src: register*/
8170 				(5 << 8) |	/* dst: memory */
8171 				(1 << 20));	/* write confirm */
8172 	amdgpu_ring_write(ring, reg);
8173 	amdgpu_ring_write(ring, 0);
8174 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8175 				reg_val_offs * 4));
8176 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8177 				reg_val_offs * 4));
8178 }
8179 
8180 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8181 				   uint32_t val)
8182 {
8183 	uint32_t cmd = 0;
8184 
8185 	switch (ring->funcs->type) {
8186 	case AMDGPU_RING_TYPE_GFX:
8187 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8188 		break;
8189 	case AMDGPU_RING_TYPE_KIQ:
8190 		cmd = (1 << 16); /* no inc addr */
8191 		break;
8192 	default:
8193 		cmd = WR_CONFIRM;
8194 		break;
8195 	}
8196 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8197 	amdgpu_ring_write(ring, cmd);
8198 	amdgpu_ring_write(ring, reg);
8199 	amdgpu_ring_write(ring, 0);
8200 	amdgpu_ring_write(ring, val);
8201 }
8202 
8203 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8204 					uint32_t val, uint32_t mask)
8205 {
8206 	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8207 }
8208 
8209 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8210 						   uint32_t reg0, uint32_t reg1,
8211 						   uint32_t ref, uint32_t mask)
8212 {
8213 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8214 	struct amdgpu_device *adev = ring->adev;
8215 	bool fw_version_ok = false;
8216 
8217 	fw_version_ok = adev->gfx.cp_fw_write_wait;
8218 
8219 	if (fw_version_ok)
8220 		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8221 				       ref, mask, 0x20);
8222 	else
8223 		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8224 							   ref, mask);
8225 }
8226 
8227 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8228 					 unsigned vmid)
8229 {
8230 	struct amdgpu_device *adev = ring->adev;
8231 	uint32_t value = 0;
8232 
8233 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8234 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8235 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8236 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8237 	WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8238 }
8239 
8240 static void
8241 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8242 				      uint32_t me, uint32_t pipe,
8243 				      enum amdgpu_interrupt_state state)
8244 {
8245 	uint32_t cp_int_cntl, cp_int_cntl_reg;
8246 
8247 	if (!me) {
8248 		switch (pipe) {
8249 		case 0:
8250 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8251 			break;
8252 		case 1:
8253 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8254 			break;
8255 		default:
8256 			DRM_DEBUG("invalid pipe %d\n", pipe);
8257 			return;
8258 		}
8259 	} else {
8260 		DRM_DEBUG("invalid me %d\n", me);
8261 		return;
8262 	}
8263 
8264 	switch (state) {
8265 	case AMDGPU_IRQ_STATE_DISABLE:
8266 		cp_int_cntl = RREG32(cp_int_cntl_reg);
8267 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8268 					    TIME_STAMP_INT_ENABLE, 0);
8269 		WREG32(cp_int_cntl_reg, cp_int_cntl);
8270 		break;
8271 	case AMDGPU_IRQ_STATE_ENABLE:
8272 		cp_int_cntl = RREG32(cp_int_cntl_reg);
8273 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8274 					    TIME_STAMP_INT_ENABLE, 1);
8275 		WREG32(cp_int_cntl_reg, cp_int_cntl);
8276 		break;
8277 	default:
8278 		break;
8279 	}
8280 }
8281 
8282 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8283 						     int me, int pipe,
8284 						     enum amdgpu_interrupt_state state)
8285 {
8286 	u32 mec_int_cntl, mec_int_cntl_reg;
8287 
8288 	/*
8289 	 * amdgpu controls only the first MEC. That's why this function only
8290 	 * handles the setting of interrupts for this specific MEC. All other
8291 	 * pipes' interrupts are set by amdkfd.
8292 	 */
8293 
8294 	if (me == 1) {
8295 		switch (pipe) {
8296 		case 0:
8297 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8298 			break;
8299 		case 1:
8300 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8301 			break;
8302 		case 2:
8303 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8304 			break;
8305 		case 3:
8306 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8307 			break;
8308 		default:
8309 			DRM_DEBUG("invalid pipe %d\n", pipe);
8310 			return;
8311 		}
8312 	} else {
8313 		DRM_DEBUG("invalid me %d\n", me);
8314 		return;
8315 	}
8316 
8317 	switch (state) {
8318 	case AMDGPU_IRQ_STATE_DISABLE:
8319 		mec_int_cntl = RREG32(mec_int_cntl_reg);
8320 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8321 					     TIME_STAMP_INT_ENABLE, 0);
8322 		WREG32(mec_int_cntl_reg, mec_int_cntl);
8323 		break;
8324 	case AMDGPU_IRQ_STATE_ENABLE:
8325 		mec_int_cntl = RREG32(mec_int_cntl_reg);
8326 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8327 					     TIME_STAMP_INT_ENABLE, 1);
8328 		WREG32(mec_int_cntl_reg, mec_int_cntl);
8329 		break;
8330 	default:
8331 		break;
8332 	}
8333 }
8334 
8335 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8336 					    struct amdgpu_irq_src *src,
8337 					    unsigned type,
8338 					    enum amdgpu_interrupt_state state)
8339 {
8340 	switch (type) {
8341 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8342 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8343 		break;
8344 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8345 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8346 		break;
8347 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8348 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8349 		break;
8350 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8351 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8352 		break;
8353 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8354 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8355 		break;
8356 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8357 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8358 		break;
8359 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8360 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8361 		break;
8362 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8363 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8364 		break;
8365 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8366 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8367 		break;
8368 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8369 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8370 		break;
8371 	default:
8372 		break;
8373 	}
8374 	return 0;
8375 }
8376 
8377 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8378 			     struct amdgpu_irq_src *source,
8379 			     struct amdgpu_iv_entry *entry)
8380 {
8381 	int i;
8382 	u8 me_id, pipe_id, queue_id;
8383 	struct amdgpu_ring *ring;
8384 
8385 	DRM_DEBUG("IH: CP EOP\n");
8386 	me_id = (entry->ring_id & 0x0c) >> 2;
8387 	pipe_id = (entry->ring_id & 0x03) >> 0;
8388 	queue_id = (entry->ring_id & 0x70) >> 4;
8389 
8390 	switch (me_id) {
8391 	case 0:
8392 		if (pipe_id == 0)
8393 			amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8394 		else
8395 			amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8396 		break;
8397 	case 1:
8398 	case 2:
8399 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8400 			ring = &adev->gfx.compute_ring[i];
8401 			/* Per-queue interrupt is supported for MEC starting from VI.
8402 			  * The interrupt can only be enabled/disabled per pipe instead of per queue.
8403 			  */
8404 			if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8405 				amdgpu_fence_process(ring);
8406 		}
8407 		break;
8408 	}
8409 	return 0;
8410 }
8411 
8412 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8413 					      struct amdgpu_irq_src *source,
8414 					      unsigned type,
8415 					      enum amdgpu_interrupt_state state)
8416 {
8417 	switch (state) {
8418 	case AMDGPU_IRQ_STATE_DISABLE:
8419 	case AMDGPU_IRQ_STATE_ENABLE:
8420 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8421 			       PRIV_REG_INT_ENABLE,
8422 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8423 		break;
8424 	default:
8425 		break;
8426 	}
8427 
8428 	return 0;
8429 }
8430 
8431 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8432 					       struct amdgpu_irq_src *source,
8433 					       unsigned type,
8434 					       enum amdgpu_interrupt_state state)
8435 {
8436 	switch (state) {
8437 	case AMDGPU_IRQ_STATE_DISABLE:
8438 	case AMDGPU_IRQ_STATE_ENABLE:
8439 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8440 			       PRIV_INSTR_INT_ENABLE,
8441 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8442 	default:
8443 		break;
8444 	}
8445 
8446 	return 0;
8447 }
8448 
8449 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8450 					struct amdgpu_iv_entry *entry)
8451 {
8452 	u8 me_id, pipe_id, queue_id;
8453 	struct amdgpu_ring *ring;
8454 	int i;
8455 
8456 	me_id = (entry->ring_id & 0x0c) >> 2;
8457 	pipe_id = (entry->ring_id & 0x03) >> 0;
8458 	queue_id = (entry->ring_id & 0x70) >> 4;
8459 
8460 	switch (me_id) {
8461 	case 0:
8462 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8463 			ring = &adev->gfx.gfx_ring[i];
8464 			/* we only enabled 1 gfx queue per pipe for now */
8465 			if (ring->me == me_id && ring->pipe == pipe_id)
8466 				drm_sched_fault(&ring->sched);
8467 		}
8468 		break;
8469 	case 1:
8470 	case 2:
8471 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8472 			ring = &adev->gfx.compute_ring[i];
8473 			if (ring->me == me_id && ring->pipe == pipe_id &&
8474 			    ring->queue == queue_id)
8475 				drm_sched_fault(&ring->sched);
8476 		}
8477 		break;
8478 	default:
8479 		BUG();
8480 	}
8481 }
8482 
8483 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8484 				  struct amdgpu_irq_src *source,
8485 				  struct amdgpu_iv_entry *entry)
8486 {
8487 	DRM_ERROR("Illegal register access in command stream\n");
8488 	gfx_v10_0_handle_priv_fault(adev, entry);
8489 	return 0;
8490 }
8491 
8492 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8493 				   struct amdgpu_irq_src *source,
8494 				   struct amdgpu_iv_entry *entry)
8495 {
8496 	DRM_ERROR("Illegal instruction in command stream\n");
8497 	gfx_v10_0_handle_priv_fault(adev, entry);
8498 	return 0;
8499 }
8500 
8501 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8502 					     struct amdgpu_irq_src *src,
8503 					     unsigned int type,
8504 					     enum amdgpu_interrupt_state state)
8505 {
8506 	uint32_t tmp, target;
8507 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8508 
8509 	if (ring->me == 1)
8510 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8511 	else
8512 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8513 	target += ring->pipe;
8514 
8515 	switch (type) {
8516 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8517 		if (state == AMDGPU_IRQ_STATE_DISABLE) {
8518 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8519 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8520 					    GENERIC2_INT_ENABLE, 0);
8521 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8522 
8523 			tmp = RREG32(target);
8524 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8525 					    GENERIC2_INT_ENABLE, 0);
8526 			WREG32(target, tmp);
8527 		} else {
8528 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8529 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8530 					    GENERIC2_INT_ENABLE, 1);
8531 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8532 
8533 			tmp = RREG32(target);
8534 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8535 					    GENERIC2_INT_ENABLE, 1);
8536 			WREG32(target, tmp);
8537 		}
8538 		break;
8539 	default:
8540 		BUG(); /* kiq only support GENERIC2_INT now */
8541 		break;
8542 	}
8543 	return 0;
8544 }
8545 
8546 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8547 			     struct amdgpu_irq_src *source,
8548 			     struct amdgpu_iv_entry *entry)
8549 {
8550 	u8 me_id, pipe_id, queue_id;
8551 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8552 
8553 	me_id = (entry->ring_id & 0x0c) >> 2;
8554 	pipe_id = (entry->ring_id & 0x03) >> 0;
8555 	queue_id = (entry->ring_id & 0x70) >> 4;
8556 	DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8557 		   me_id, pipe_id, queue_id);
8558 
8559 	amdgpu_fence_process(ring);
8560 	return 0;
8561 }
8562 
8563 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8564 {
8565 	const unsigned int gcr_cntl =
8566 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8567 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8568 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8569 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8570 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8571 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8572 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8573 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8574 
8575 	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8576 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8577 	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8578 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8579 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8580 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8581 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8582 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8583 	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8584 }
8585 
8586 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8587 	.name = "gfx_v10_0",
8588 	.early_init = gfx_v10_0_early_init,
8589 	.late_init = gfx_v10_0_late_init,
8590 	.sw_init = gfx_v10_0_sw_init,
8591 	.sw_fini = gfx_v10_0_sw_fini,
8592 	.hw_init = gfx_v10_0_hw_init,
8593 	.hw_fini = gfx_v10_0_hw_fini,
8594 	.suspend = gfx_v10_0_suspend,
8595 	.resume = gfx_v10_0_resume,
8596 	.is_idle = gfx_v10_0_is_idle,
8597 	.wait_for_idle = gfx_v10_0_wait_for_idle,
8598 	.soft_reset = gfx_v10_0_soft_reset,
8599 	.set_clockgating_state = gfx_v10_0_set_clockgating_state,
8600 	.set_powergating_state = gfx_v10_0_set_powergating_state,
8601 	.get_clockgating_state = gfx_v10_0_get_clockgating_state,
8602 };
8603 
8604 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8605 	.type = AMDGPU_RING_TYPE_GFX,
8606 	.align_mask = 0xff,
8607 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
8608 	.support_64bit_ptrs = true,
8609 	.vmhub = AMDGPU_GFXHUB_0,
8610 	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8611 	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8612 	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8613 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
8614 		5 + /* COND_EXEC */
8615 		7 + /* PIPELINE_SYNC */
8616 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8617 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8618 		2 + /* VM_FLUSH */
8619 		8 + /* FENCE for VM_FLUSH */
8620 		20 + /* GDS switch */
8621 		4 + /* double SWITCH_BUFFER,
8622 		     * the first COND_EXEC jump to the place
8623 		     * just prior to this double SWITCH_BUFFER
8624 		     */
8625 		5 + /* COND_EXEC */
8626 		7 + /* HDP_flush */
8627 		4 + /* VGT_flush */
8628 		14 + /*	CE_META */
8629 		31 + /*	DE_META */
8630 		3 + /* CNTX_CTRL */
8631 		5 + /* HDP_INVL */
8632 		8 + 8 + /* FENCE x2 */
8633 		2 + /* SWITCH_BUFFER */
8634 		8, /* gfx_v10_0_emit_mem_sync */
8635 	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
8636 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8637 	.emit_fence = gfx_v10_0_ring_emit_fence,
8638 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8639 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8640 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8641 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8642 	.test_ring = gfx_v10_0_ring_test_ring,
8643 	.test_ib = gfx_v10_0_ring_test_ib,
8644 	.insert_nop = amdgpu_ring_insert_nop,
8645 	.pad_ib = amdgpu_ring_generic_pad_ib,
8646 	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8647 	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8648 	.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8649 	.patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8650 	.preempt_ib = gfx_v10_0_ring_preempt_ib,
8651 	.emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8652 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
8653 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8654 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8655 	.soft_recovery = gfx_v10_0_ring_soft_recovery,
8656 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
8657 };
8658 
8659 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8660 	.type = AMDGPU_RING_TYPE_COMPUTE,
8661 	.align_mask = 0xff,
8662 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
8663 	.support_64bit_ptrs = true,
8664 	.vmhub = AMDGPU_GFXHUB_0,
8665 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
8666 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
8667 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
8668 	.emit_frame_size =
8669 		20 + /* gfx_v10_0_ring_emit_gds_switch */
8670 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
8671 		5 + /* hdp invalidate */
8672 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8673 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8674 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8675 		2 + /* gfx_v10_0_ring_emit_vm_flush */
8676 		8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8677 		8, /* gfx_v10_0_emit_mem_sync */
8678 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
8679 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
8680 	.emit_fence = gfx_v10_0_ring_emit_fence,
8681 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8682 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8683 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8684 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8685 	.test_ring = gfx_v10_0_ring_test_ring,
8686 	.test_ib = gfx_v10_0_ring_test_ib,
8687 	.insert_nop = amdgpu_ring_insert_nop,
8688 	.pad_ib = amdgpu_ring_generic_pad_ib,
8689 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
8690 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8691 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8692 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
8693 };
8694 
8695 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8696 	.type = AMDGPU_RING_TYPE_KIQ,
8697 	.align_mask = 0xff,
8698 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
8699 	.support_64bit_ptrs = true,
8700 	.vmhub = AMDGPU_GFXHUB_0,
8701 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
8702 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
8703 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
8704 	.emit_frame_size =
8705 		20 + /* gfx_v10_0_ring_emit_gds_switch */
8706 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
8707 		5 + /*hdp invalidate */
8708 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8709 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8710 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8711 		2 + /* gfx_v10_0_ring_emit_vm_flush */
8712 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8713 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
8714 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
8715 	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8716 	.test_ring = gfx_v10_0_ring_test_ring,
8717 	.test_ib = gfx_v10_0_ring_test_ib,
8718 	.insert_nop = amdgpu_ring_insert_nop,
8719 	.pad_ib = amdgpu_ring_generic_pad_ib,
8720 	.emit_rreg = gfx_v10_0_ring_emit_rreg,
8721 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
8722 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8723 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8724 };
8725 
8726 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8727 {
8728 	int i;
8729 
8730 	adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8731 
8732 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8733 		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8734 
8735 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
8736 		adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8737 }
8738 
8739 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8740 	.set = gfx_v10_0_set_eop_interrupt_state,
8741 	.process = gfx_v10_0_eop_irq,
8742 };
8743 
8744 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8745 	.set = gfx_v10_0_set_priv_reg_fault_state,
8746 	.process = gfx_v10_0_priv_reg_irq,
8747 };
8748 
8749 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8750 	.set = gfx_v10_0_set_priv_inst_fault_state,
8751 	.process = gfx_v10_0_priv_inst_irq,
8752 };
8753 
8754 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8755 	.set = gfx_v10_0_kiq_set_interrupt_state,
8756 	.process = gfx_v10_0_kiq_irq,
8757 };
8758 
8759 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8760 {
8761 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8762 	adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8763 
8764 	adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8765 	adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8766 
8767 	adev->gfx.priv_reg_irq.num_types = 1;
8768 	adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8769 
8770 	adev->gfx.priv_inst_irq.num_types = 1;
8771 	adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8772 }
8773 
8774 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8775 {
8776 	switch (adev->asic_type) {
8777 	case CHIP_NAVI10:
8778 	case CHIP_NAVI14:
8779 	case CHIP_SIENNA_CICHLID:
8780 	case CHIP_NAVY_FLOUNDER:
8781 	case CHIP_VANGOGH:
8782 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8783 		break;
8784 	case CHIP_NAVI12:
8785 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8786 		break;
8787 	default:
8788 		break;
8789 	}
8790 }
8791 
8792 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8793 {
8794 	unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8795 			    adev->gfx.config.max_sh_per_se *
8796 			    adev->gfx.config.max_shader_engines;
8797 
8798 	adev->gds.gds_size = 0x10000;
8799 	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8800 	adev->gds.gws_size = 64;
8801 	adev->gds.oa_size = 16;
8802 }
8803 
8804 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8805 							  u32 bitmap)
8806 {
8807 	u32 data;
8808 
8809 	if (!bitmap)
8810 		return;
8811 
8812 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8813 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8814 
8815 	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8816 }
8817 
8818 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8819 {
8820 	u32 data, wgp_bitmask;
8821 	data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8822 	data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8823 
8824 	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8825 	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8826 
8827 	wgp_bitmask =
8828 		amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8829 
8830 	return (~data) & wgp_bitmask;
8831 }
8832 
8833 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8834 {
8835 	u32 wgp_idx, wgp_active_bitmap;
8836 	u32 cu_bitmap_per_wgp, cu_active_bitmap;
8837 
8838 	wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8839 	cu_active_bitmap = 0;
8840 
8841 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8842 		/* if there is one WGP enabled, it means 2 CUs will be enabled */
8843 		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8844 		if (wgp_active_bitmap & (1 << wgp_idx))
8845 			cu_active_bitmap |= cu_bitmap_per_wgp;
8846 	}
8847 
8848 	return cu_active_bitmap;
8849 }
8850 
8851 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8852 				 struct amdgpu_cu_info *cu_info)
8853 {
8854 	int i, j, k, counter, active_cu_number = 0;
8855 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8856 	unsigned disable_masks[4 * 2];
8857 
8858 	if (!adev || !cu_info)
8859 		return -EINVAL;
8860 
8861 	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8862 
8863 	mutex_lock(&adev->grbm_idx_mutex);
8864 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8865 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8866 			mask = 1;
8867 			ao_bitmap = 0;
8868 			counter = 0;
8869 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8870 			if (i < 4 && j < 2)
8871 				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8872 					adev, disable_masks[i * 2 + j]);
8873 			bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8874 			cu_info->bitmap[i][j] = bitmap;
8875 
8876 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8877 				if (bitmap & mask) {
8878 					if (counter < adev->gfx.config.max_cu_per_sh)
8879 						ao_bitmap |= mask;
8880 					counter++;
8881 				}
8882 				mask <<= 1;
8883 			}
8884 			active_cu_number += counter;
8885 			if (i < 2 && j < 2)
8886 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8887 			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8888 		}
8889 	}
8890 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8891 	mutex_unlock(&adev->grbm_idx_mutex);
8892 
8893 	cu_info->number = active_cu_number;
8894 	cu_info->ao_cu_mask = ao_cu_mask;
8895 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8896 
8897 	return 0;
8898 }
8899 
8900 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8901 {
8902 	.type = AMD_IP_BLOCK_TYPE_GFX,
8903 	.major = 10,
8904 	.minor = 0,
8905 	.rev = 0,
8906 	.funcs = &gfx_v10_0_ip_funcs,
8907 };
8908