1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "smuio/smuio_11_0_0_offset.h" 39 #include "smuio/smuio_11_0_0_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "soc15_common.h" 47 #include "clearstate_gfx10.h" 48 #include "v10_structs.h" 49 #include "gfx_v10_0.h" 50 #include "nbio_v2_3.h" 51 52 /** 53 * Navi10 has two graphic rings to share each graphic pipe. 54 * 1. Primary ring 55 * 2. Async ring 56 */ 57 #define GFX10_NUM_GFX_RINGS_NV1X 1 58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 59 #define GFX10_MEC_HPD_SIZE 2048 60 61 #define F32_CE_PROGRAM_RAM_SIZE 65536 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 64 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 70 71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 73 74 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 76 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 101 102 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 103 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 104 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 105 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 106 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 107 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 108 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 109 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 110 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 111 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 112 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 113 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 114 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 115 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 116 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 117 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 118 119 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 120 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 121 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 122 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 123 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 124 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 125 #define mmCP_HYP_CE_UCODE_DATA 0x5819 126 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 127 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 128 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 129 #define mmCP_HYP_ME_UCODE_DATA 0x5817 130 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 131 132 #define mmCPG_PSP_DEBUG 0x5c10 133 #define mmCPG_PSP_DEBUG_BASE_IDX 1 134 #define mmCPC_PSP_DEBUG 0x5c11 135 #define mmCPC_PSP_DEBUG_BASE_IDX 1 136 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 137 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 138 139 //CC_GC_SA_UNIT_DISABLE 140 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 141 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 142 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 143 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 144 //GC_USER_SA_UNIT_DISABLE 145 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 146 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 147 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 148 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 149 //PA_SC_ENHANCE_3 150 #define mmPA_SC_ENHANCE_3 0x1085 151 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 152 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 153 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 154 155 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 156 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 157 158 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 159 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 160 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 161 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 162 163 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 164 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 165 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 166 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 167 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 168 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 169 170 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 171 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 172 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 173 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 174 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 175 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 176 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 177 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 178 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 179 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 180 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 181 182 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 183 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 184 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 185 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 186 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 187 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 188 189 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 190 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 191 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 192 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 193 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 194 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 195 196 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 197 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 198 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 199 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 200 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 201 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 202 203 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 204 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 205 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 206 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 207 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 208 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 209 210 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 211 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 212 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 213 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 214 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 215 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 216 217 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 218 { 219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 259 }; 260 261 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 262 { 263 /* Pending on emulation bring up */ 264 }; 265 266 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 267 { 268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1320 }; 1321 1322 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1323 { 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1362 }; 1363 1364 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1365 { 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 1406 }; 1407 1408 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 1409 { 1410 static void *scratch_reg0; 1411 static void *scratch_reg1; 1412 static void *scratch_reg2; 1413 static void *scratch_reg3; 1414 static void *spare_int; 1415 static uint32_t grbm_cntl; 1416 static uint32_t grbm_idx; 1417 uint32_t i = 0; 1418 uint32_t retries = 50000; 1419 1420 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 1421 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 1422 scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4; 1423 scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4; 1424 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 1425 1426 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 1427 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; 1428 1429 if (amdgpu_sriov_runtime(adev)) { 1430 pr_err("shouldn't call rlcg write register during runtime\n"); 1431 return; 1432 } 1433 1434 writel(v, scratch_reg0); 1435 writel(offset | 0x80000000, scratch_reg1); 1436 writel(1, spare_int); 1437 for (i = 0; i < retries; i++) { 1438 u32 tmp; 1439 1440 tmp = readl(scratch_reg1); 1441 if (!(tmp & 0x80000000)) 1442 break; 1443 1444 udelay(10); 1445 } 1446 1447 if (i >= retries) 1448 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 1449 } 1450 1451 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1452 { 1453 /* Pending on emulation bring up */ 1454 }; 1455 1456 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1457 { 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2078 }; 2079 2080 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2081 { 2082 /* Pending on emulation bring up */ 2083 }; 2084 2085 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2086 { 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3139 }; 3140 3141 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3142 { 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3185 }; 3186 3187 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3188 { 3189 /* Pending on emulation bring up */ 3190 }; 3191 3192 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3193 { 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3235 3236 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3238 }; 3239 3240 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3241 { 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3265 }; 3266 3267 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3268 { 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3303 }; 3304 3305 #define DEFAULT_SH_MEM_CONFIG \ 3306 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3307 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3308 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3309 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3310 3311 3312 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3313 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3314 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3315 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3316 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3317 struct amdgpu_cu_info *cu_info); 3318 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3319 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3320 u32 sh_num, u32 instance); 3321 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3322 3323 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3324 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3325 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3326 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3327 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3328 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3329 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3330 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3331 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3332 3333 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3334 { 3335 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3336 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3337 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3338 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3339 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3340 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3341 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3342 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3343 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3344 } 3345 3346 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3347 struct amdgpu_ring *ring) 3348 { 3349 struct amdgpu_device *adev = kiq_ring->adev; 3350 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3351 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3352 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3353 3354 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3355 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3356 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3357 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3358 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3359 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3360 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3361 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3362 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3363 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3364 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3365 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3366 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3367 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3368 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3369 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3370 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3371 } 3372 3373 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3374 struct amdgpu_ring *ring, 3375 enum amdgpu_unmap_queues_action action, 3376 u64 gpu_addr, u64 seq) 3377 { 3378 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3379 3380 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3381 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3382 PACKET3_UNMAP_QUEUES_ACTION(action) | 3383 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3384 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3385 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3386 amdgpu_ring_write(kiq_ring, 3387 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3388 3389 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3390 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3391 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3392 amdgpu_ring_write(kiq_ring, seq); 3393 } else { 3394 amdgpu_ring_write(kiq_ring, 0); 3395 amdgpu_ring_write(kiq_ring, 0); 3396 amdgpu_ring_write(kiq_ring, 0); 3397 } 3398 } 3399 3400 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3401 struct amdgpu_ring *ring, 3402 u64 addr, 3403 u64 seq) 3404 { 3405 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3406 3407 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3408 amdgpu_ring_write(kiq_ring, 3409 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3410 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3411 PACKET3_QUERY_STATUS_COMMAND(2)); 3412 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3413 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3414 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3415 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3416 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3417 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3418 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3419 } 3420 3421 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3422 uint16_t pasid, uint32_t flush_type, 3423 bool all_hub) 3424 { 3425 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 3426 amdgpu_ring_write(kiq_ring, 3427 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 3428 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 3429 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 3430 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 3431 } 3432 3433 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3434 .kiq_set_resources = gfx10_kiq_set_resources, 3435 .kiq_map_queues = gfx10_kiq_map_queues, 3436 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3437 .kiq_query_status = gfx10_kiq_query_status, 3438 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3439 .set_resources_size = 8, 3440 .map_queues_size = 7, 3441 .unmap_queues_size = 6, 3442 .query_status_size = 7, 3443 .invalidate_tlbs_size = 2, 3444 }; 3445 3446 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3447 { 3448 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3449 } 3450 3451 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3452 { 3453 switch (adev->asic_type) { 3454 case CHIP_NAVI10: 3455 soc15_program_register_sequence(adev, 3456 golden_settings_gc_rlc_spm_10_0_nv10, 3457 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3458 break; 3459 case CHIP_NAVI14: 3460 soc15_program_register_sequence(adev, 3461 golden_settings_gc_rlc_spm_10_1_nv14, 3462 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3463 break; 3464 case CHIP_NAVI12: 3465 soc15_program_register_sequence(adev, 3466 golden_settings_gc_rlc_spm_10_1_2_nv12, 3467 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3468 break; 3469 default: 3470 break; 3471 } 3472 } 3473 3474 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3475 { 3476 switch (adev->asic_type) { 3477 case CHIP_NAVI10: 3478 soc15_program_register_sequence(adev, 3479 golden_settings_gc_10_1, 3480 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3481 soc15_program_register_sequence(adev, 3482 golden_settings_gc_10_0_nv10, 3483 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3484 break; 3485 case CHIP_NAVI14: 3486 soc15_program_register_sequence(adev, 3487 golden_settings_gc_10_1_1, 3488 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3489 soc15_program_register_sequence(adev, 3490 golden_settings_gc_10_1_nv14, 3491 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3492 break; 3493 case CHIP_NAVI12: 3494 soc15_program_register_sequence(adev, 3495 golden_settings_gc_10_1_2, 3496 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3497 soc15_program_register_sequence(adev, 3498 golden_settings_gc_10_1_2_nv12, 3499 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3500 break; 3501 case CHIP_SIENNA_CICHLID: 3502 soc15_program_register_sequence(adev, 3503 golden_settings_gc_10_3, 3504 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3505 soc15_program_register_sequence(adev, 3506 golden_settings_gc_10_3_sienna_cichlid, 3507 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3508 break; 3509 case CHIP_NAVY_FLOUNDER: 3510 soc15_program_register_sequence(adev, 3511 golden_settings_gc_10_3_2, 3512 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3513 break; 3514 case CHIP_VANGOGH: 3515 soc15_program_register_sequence(adev, 3516 golden_settings_gc_10_3_vangogh, 3517 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3518 break; 3519 case CHIP_DIMGREY_CAVEFISH: 3520 soc15_program_register_sequence(adev, 3521 golden_settings_gc_10_3_4, 3522 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3523 break; 3524 default: 3525 break; 3526 } 3527 gfx_v10_0_init_spm_golden_registers(adev); 3528 } 3529 3530 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 3531 { 3532 adev->gfx.scratch.num_reg = 8; 3533 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3534 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 3535 } 3536 3537 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3538 bool wc, uint32_t reg, uint32_t val) 3539 { 3540 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3541 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3542 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3543 amdgpu_ring_write(ring, reg); 3544 amdgpu_ring_write(ring, 0); 3545 amdgpu_ring_write(ring, val); 3546 } 3547 3548 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3549 int mem_space, int opt, uint32_t addr0, 3550 uint32_t addr1, uint32_t ref, uint32_t mask, 3551 uint32_t inv) 3552 { 3553 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3554 amdgpu_ring_write(ring, 3555 /* memory (1) or register (0) */ 3556 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3557 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3558 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3559 WAIT_REG_MEM_ENGINE(eng_sel))); 3560 3561 if (mem_space) 3562 BUG_ON(addr0 & 0x3); /* Dword align */ 3563 amdgpu_ring_write(ring, addr0); 3564 amdgpu_ring_write(ring, addr1); 3565 amdgpu_ring_write(ring, ref); 3566 amdgpu_ring_write(ring, mask); 3567 amdgpu_ring_write(ring, inv); /* poll interval */ 3568 } 3569 3570 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3571 { 3572 struct amdgpu_device *adev = ring->adev; 3573 uint32_t scratch; 3574 uint32_t tmp = 0; 3575 unsigned i; 3576 int r; 3577 3578 r = amdgpu_gfx_scratch_get(adev, &scratch); 3579 if (r) { 3580 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 3581 return r; 3582 } 3583 3584 WREG32(scratch, 0xCAFEDEAD); 3585 3586 r = amdgpu_ring_alloc(ring, 3); 3587 if (r) { 3588 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3589 ring->idx, r); 3590 amdgpu_gfx_scratch_free(adev, scratch); 3591 return r; 3592 } 3593 3594 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3595 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3596 amdgpu_ring_write(ring, 0xDEADBEEF); 3597 amdgpu_ring_commit(ring); 3598 3599 for (i = 0; i < adev->usec_timeout; i++) { 3600 tmp = RREG32(scratch); 3601 if (tmp == 0xDEADBEEF) 3602 break; 3603 if (amdgpu_emu_mode == 1) 3604 msleep(1); 3605 else 3606 udelay(1); 3607 } 3608 3609 if (i >= adev->usec_timeout) 3610 r = -ETIMEDOUT; 3611 3612 amdgpu_gfx_scratch_free(adev, scratch); 3613 3614 return r; 3615 } 3616 3617 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3618 { 3619 struct amdgpu_device *adev = ring->adev; 3620 struct amdgpu_ib ib; 3621 struct dma_fence *f = NULL; 3622 unsigned index; 3623 uint64_t gpu_addr; 3624 uint32_t tmp; 3625 long r; 3626 3627 r = amdgpu_device_wb_get(adev, &index); 3628 if (r) 3629 return r; 3630 3631 gpu_addr = adev->wb.gpu_addr + (index * 4); 3632 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3633 memset(&ib, 0, sizeof(ib)); 3634 r = amdgpu_ib_get(adev, NULL, 16, 3635 AMDGPU_IB_POOL_DIRECT, &ib); 3636 if (r) 3637 goto err1; 3638 3639 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3640 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3641 ib.ptr[2] = lower_32_bits(gpu_addr); 3642 ib.ptr[3] = upper_32_bits(gpu_addr); 3643 ib.ptr[4] = 0xDEADBEEF; 3644 ib.length_dw = 5; 3645 3646 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3647 if (r) 3648 goto err2; 3649 3650 r = dma_fence_wait_timeout(f, false, timeout); 3651 if (r == 0) { 3652 r = -ETIMEDOUT; 3653 goto err2; 3654 } else if (r < 0) { 3655 goto err2; 3656 } 3657 3658 tmp = adev->wb.wb[index]; 3659 if (tmp == 0xDEADBEEF) 3660 r = 0; 3661 else 3662 r = -EINVAL; 3663 err2: 3664 amdgpu_ib_free(adev, &ib, NULL); 3665 dma_fence_put(f); 3666 err1: 3667 amdgpu_device_wb_free(adev, index); 3668 return r; 3669 } 3670 3671 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3672 { 3673 release_firmware(adev->gfx.pfp_fw); 3674 adev->gfx.pfp_fw = NULL; 3675 release_firmware(adev->gfx.me_fw); 3676 adev->gfx.me_fw = NULL; 3677 release_firmware(adev->gfx.ce_fw); 3678 adev->gfx.ce_fw = NULL; 3679 release_firmware(adev->gfx.rlc_fw); 3680 adev->gfx.rlc_fw = NULL; 3681 release_firmware(adev->gfx.mec_fw); 3682 adev->gfx.mec_fw = NULL; 3683 release_firmware(adev->gfx.mec2_fw); 3684 adev->gfx.mec2_fw = NULL; 3685 3686 kfree(adev->gfx.rlc.register_list_format); 3687 } 3688 3689 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3690 { 3691 adev->gfx.cp_fw_write_wait = false; 3692 3693 switch (adev->asic_type) { 3694 case CHIP_NAVI10: 3695 case CHIP_NAVI12: 3696 case CHIP_NAVI14: 3697 if ((adev->gfx.me_fw_version >= 0x00000046) && 3698 (adev->gfx.me_feature_version >= 27) && 3699 (adev->gfx.pfp_fw_version >= 0x00000068) && 3700 (adev->gfx.pfp_feature_version >= 27) && 3701 (adev->gfx.mec_fw_version >= 0x0000005b) && 3702 (adev->gfx.mec_feature_version >= 27)) 3703 adev->gfx.cp_fw_write_wait = true; 3704 break; 3705 case CHIP_SIENNA_CICHLID: 3706 case CHIP_NAVY_FLOUNDER: 3707 case CHIP_VANGOGH: 3708 case CHIP_DIMGREY_CAVEFISH: 3709 adev->gfx.cp_fw_write_wait = true; 3710 break; 3711 default: 3712 break; 3713 } 3714 3715 if (!adev->gfx.cp_fw_write_wait) 3716 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3717 } 3718 3719 3720 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 3721 { 3722 const struct rlc_firmware_header_v2_1 *rlc_hdr; 3723 3724 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 3725 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 3726 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 3727 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 3728 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 3729 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 3730 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 3731 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 3732 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 3733 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 3734 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 3735 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 3736 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 3737 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 3738 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 3739 } 3740 3741 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) 3742 { 3743 const struct rlc_firmware_header_v2_2 *rlc_hdr; 3744 3745 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 3746 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); 3747 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); 3748 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); 3749 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); 3750 } 3751 3752 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3753 { 3754 bool ret = false; 3755 3756 switch (adev->pdev->revision) { 3757 case 0xc2: 3758 case 0xc3: 3759 ret = true; 3760 break; 3761 default: 3762 ret = false; 3763 break; 3764 } 3765 3766 return ret ; 3767 } 3768 3769 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3770 { 3771 switch (adev->asic_type) { 3772 case CHIP_NAVI10: 3773 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3774 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3775 break; 3776 case CHIP_VANGOGH: 3777 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3778 break; 3779 default: 3780 break; 3781 } 3782 } 3783 3784 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3785 { 3786 const char *chip_name; 3787 char fw_name[40]; 3788 char wks[10]; 3789 int err; 3790 struct amdgpu_firmware_info *info = NULL; 3791 const struct common_firmware_header *header = NULL; 3792 const struct gfx_firmware_header_v1_0 *cp_hdr; 3793 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3794 unsigned int *tmp = NULL; 3795 unsigned int i = 0; 3796 uint16_t version_major; 3797 uint16_t version_minor; 3798 3799 DRM_DEBUG("\n"); 3800 3801 memset(wks, 0, sizeof(wks)); 3802 switch (adev->asic_type) { 3803 case CHIP_NAVI10: 3804 chip_name = "navi10"; 3805 break; 3806 case CHIP_NAVI14: 3807 chip_name = "navi14"; 3808 if (!(adev->pdev->device == 0x7340 && 3809 adev->pdev->revision != 0x00)) 3810 snprintf(wks, sizeof(wks), "_wks"); 3811 break; 3812 case CHIP_NAVI12: 3813 chip_name = "navi12"; 3814 break; 3815 case CHIP_SIENNA_CICHLID: 3816 chip_name = "sienna_cichlid"; 3817 break; 3818 case CHIP_NAVY_FLOUNDER: 3819 chip_name = "navy_flounder"; 3820 break; 3821 case CHIP_VANGOGH: 3822 chip_name = "vangogh"; 3823 break; 3824 case CHIP_DIMGREY_CAVEFISH: 3825 chip_name = "dimgrey_cavefish"; 3826 break; 3827 default: 3828 BUG(); 3829 } 3830 3831 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 3832 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 3833 if (err) 3834 goto out; 3835 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 3836 if (err) 3837 goto out; 3838 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3839 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3840 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3841 3842 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 3843 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 3844 if (err) 3845 goto out; 3846 err = amdgpu_ucode_validate(adev->gfx.me_fw); 3847 if (err) 3848 goto out; 3849 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3850 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3851 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3852 3853 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 3854 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 3855 if (err) 3856 goto out; 3857 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 3858 if (err) 3859 goto out; 3860 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3861 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3862 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3863 3864 if (!amdgpu_sriov_vf(adev)) { 3865 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 3866 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 3867 if (err) 3868 goto out; 3869 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 3870 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3871 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 3872 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 3873 3874 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 3875 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 3876 adev->gfx.rlc.save_and_restore_offset = 3877 le32_to_cpu(rlc_hdr->save_and_restore_offset); 3878 adev->gfx.rlc.clear_state_descriptor_offset = 3879 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 3880 adev->gfx.rlc.avail_scratch_ram_locations = 3881 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 3882 adev->gfx.rlc.reg_restore_list_size = 3883 le32_to_cpu(rlc_hdr->reg_restore_list_size); 3884 adev->gfx.rlc.reg_list_format_start = 3885 le32_to_cpu(rlc_hdr->reg_list_format_start); 3886 adev->gfx.rlc.reg_list_format_separate_start = 3887 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 3888 adev->gfx.rlc.starting_offsets_start = 3889 le32_to_cpu(rlc_hdr->starting_offsets_start); 3890 adev->gfx.rlc.reg_list_format_size_bytes = 3891 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 3892 adev->gfx.rlc.reg_list_size_bytes = 3893 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 3894 adev->gfx.rlc.register_list_format = 3895 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 3896 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 3897 if (!adev->gfx.rlc.register_list_format) { 3898 err = -ENOMEM; 3899 goto out; 3900 } 3901 3902 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3903 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 3904 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 3905 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 3906 3907 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 3908 3909 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 3910 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 3911 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 3912 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 3913 3914 if (version_major == 2) { 3915 if (version_minor >= 1) 3916 gfx_v10_0_init_rlc_ext_microcode(adev); 3917 if (version_minor == 2) 3918 gfx_v10_0_init_rlc_iram_dram_microcode(adev); 3919 } 3920 } 3921 3922 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 3923 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 3924 if (err) 3925 goto out; 3926 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 3927 if (err) 3928 goto out; 3929 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3930 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 3931 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 3932 3933 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 3934 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 3935 if (!err) { 3936 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 3937 if (err) 3938 goto out; 3939 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 3940 adev->gfx.mec2_fw->data; 3941 adev->gfx.mec2_fw_version = 3942 le32_to_cpu(cp_hdr->header.ucode_version); 3943 adev->gfx.mec2_feature_version = 3944 le32_to_cpu(cp_hdr->ucode_feature_version); 3945 } else { 3946 err = 0; 3947 adev->gfx.mec2_fw = NULL; 3948 } 3949 3950 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 3951 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 3952 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 3953 info->fw = adev->gfx.pfp_fw; 3954 header = (const struct common_firmware_header *)info->fw->data; 3955 adev->firmware.fw_size += 3956 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3957 3958 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 3959 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 3960 info->fw = adev->gfx.me_fw; 3961 header = (const struct common_firmware_header *)info->fw->data; 3962 adev->firmware.fw_size += 3963 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3964 3965 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 3966 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 3967 info->fw = adev->gfx.ce_fw; 3968 header = (const struct common_firmware_header *)info->fw->data; 3969 adev->firmware.fw_size += 3970 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3971 3972 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 3973 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 3974 info->fw = adev->gfx.rlc_fw; 3975 if (info->fw) { 3976 header = (const struct common_firmware_header *)info->fw->data; 3977 adev->firmware.fw_size += 3978 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 3979 } 3980 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes && 3981 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 3982 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 3983 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 3984 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 3985 info->fw = adev->gfx.rlc_fw; 3986 adev->firmware.fw_size += 3987 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 3988 3989 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 3990 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 3991 info->fw = adev->gfx.rlc_fw; 3992 adev->firmware.fw_size += 3993 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 3994 3995 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 3996 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 3997 info->fw = adev->gfx.rlc_fw; 3998 adev->firmware.fw_size += 3999 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 4000 4001 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes && 4002 adev->gfx.rlc.rlc_dram_ucode_size_bytes) { 4003 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; 4004 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM; 4005 info->fw = adev->gfx.rlc_fw; 4006 adev->firmware.fw_size += 4007 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); 4008 4009 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; 4010 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM; 4011 info->fw = adev->gfx.rlc_fw; 4012 adev->firmware.fw_size += 4013 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); 4014 } 4015 } 4016 4017 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 4018 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 4019 info->fw = adev->gfx.mec_fw; 4020 header = (const struct common_firmware_header *)info->fw->data; 4021 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4022 adev->firmware.fw_size += 4023 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4024 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4025 4026 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 4027 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 4028 info->fw = adev->gfx.mec_fw; 4029 adev->firmware.fw_size += 4030 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 4031 4032 if (adev->gfx.mec2_fw) { 4033 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 4034 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 4035 info->fw = adev->gfx.mec2_fw; 4036 header = (const struct common_firmware_header *)info->fw->data; 4037 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 4038 adev->firmware.fw_size += 4039 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 4040 le32_to_cpu(cp_hdr->jt_size) * 4, 4041 PAGE_SIZE); 4042 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 4043 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 4044 info->fw = adev->gfx.mec2_fw; 4045 adev->firmware.fw_size += 4046 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 4047 PAGE_SIZE); 4048 } 4049 } 4050 4051 gfx_v10_0_check_fw_write_wait(adev); 4052 out: 4053 if (err) { 4054 dev_err(adev->dev, 4055 "gfx10: Failed to load firmware \"%s\"\n", 4056 fw_name); 4057 release_firmware(adev->gfx.pfp_fw); 4058 adev->gfx.pfp_fw = NULL; 4059 release_firmware(adev->gfx.me_fw); 4060 adev->gfx.me_fw = NULL; 4061 release_firmware(adev->gfx.ce_fw); 4062 adev->gfx.ce_fw = NULL; 4063 release_firmware(adev->gfx.rlc_fw); 4064 adev->gfx.rlc_fw = NULL; 4065 release_firmware(adev->gfx.mec_fw); 4066 adev->gfx.mec_fw = NULL; 4067 release_firmware(adev->gfx.mec2_fw); 4068 adev->gfx.mec2_fw = NULL; 4069 } 4070 4071 gfx_v10_0_check_gfxoff_flag(adev); 4072 4073 return err; 4074 } 4075 4076 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4077 { 4078 u32 count = 0; 4079 const struct cs_section_def *sect = NULL; 4080 const struct cs_extent_def *ext = NULL; 4081 4082 /* begin clear state */ 4083 count += 2; 4084 /* context control state */ 4085 count += 3; 4086 4087 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4088 for (ext = sect->section; ext->extent != NULL; ++ext) { 4089 if (sect->id == SECT_CONTEXT) 4090 count += 2 + ext->reg_count; 4091 else 4092 return 0; 4093 } 4094 } 4095 4096 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4097 count += 3; 4098 /* end clear state */ 4099 count += 2; 4100 /* clear state */ 4101 count += 2; 4102 4103 return count; 4104 } 4105 4106 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4107 volatile u32 *buffer) 4108 { 4109 u32 count = 0, i; 4110 const struct cs_section_def *sect = NULL; 4111 const struct cs_extent_def *ext = NULL; 4112 int ctx_reg_offset; 4113 4114 if (adev->gfx.rlc.cs_data == NULL) 4115 return; 4116 if (buffer == NULL) 4117 return; 4118 4119 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4120 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4121 4122 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4123 buffer[count++] = cpu_to_le32(0x80000000); 4124 buffer[count++] = cpu_to_le32(0x80000000); 4125 4126 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4127 for (ext = sect->section; ext->extent != NULL; ++ext) { 4128 if (sect->id == SECT_CONTEXT) { 4129 buffer[count++] = 4130 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4131 buffer[count++] = cpu_to_le32(ext->reg_index - 4132 PACKET3_SET_CONTEXT_REG_START); 4133 for (i = 0; i < ext->reg_count; i++) 4134 buffer[count++] = cpu_to_le32(ext->extent[i]); 4135 } else { 4136 return; 4137 } 4138 } 4139 } 4140 4141 ctx_reg_offset = 4142 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4143 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4144 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4145 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4146 4147 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4148 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4149 4150 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4151 buffer[count++] = cpu_to_le32(0); 4152 } 4153 4154 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4155 { 4156 /* clear state block */ 4157 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4158 &adev->gfx.rlc.clear_state_gpu_addr, 4159 (void **)&adev->gfx.rlc.cs_ptr); 4160 4161 /* jump table block */ 4162 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4163 &adev->gfx.rlc.cp_table_gpu_addr, 4164 (void **)&adev->gfx.rlc.cp_table_ptr); 4165 } 4166 4167 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4168 { 4169 const struct cs_section_def *cs_data; 4170 int r; 4171 4172 adev->gfx.rlc.cs_data = gfx10_cs_data; 4173 4174 cs_data = adev->gfx.rlc.cs_data; 4175 4176 if (cs_data) { 4177 /* init clear state block */ 4178 r = amdgpu_gfx_rlc_init_csb(adev); 4179 if (r) 4180 return r; 4181 } 4182 4183 /* init spm vmid with 0xf */ 4184 if (adev->gfx.rlc.funcs->update_spm_vmid) 4185 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4186 4187 return 0; 4188 } 4189 4190 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4191 { 4192 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4193 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4194 } 4195 4196 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4197 { 4198 int r; 4199 4200 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4201 4202 amdgpu_gfx_graphics_queue_acquire(adev); 4203 4204 r = gfx_v10_0_init_microcode(adev); 4205 if (r) 4206 DRM_ERROR("Failed to load gfx firmware!\n"); 4207 4208 return r; 4209 } 4210 4211 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4212 { 4213 int r; 4214 u32 *hpd; 4215 const __le32 *fw_data = NULL; 4216 unsigned fw_size; 4217 u32 *fw = NULL; 4218 size_t mec_hpd_size; 4219 4220 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4221 4222 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4223 4224 /* take ownership of the relevant compute queues */ 4225 amdgpu_gfx_compute_queue_acquire(adev); 4226 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4227 4228 if (mec_hpd_size) { 4229 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4230 AMDGPU_GEM_DOMAIN_GTT, 4231 &adev->gfx.mec.hpd_eop_obj, 4232 &adev->gfx.mec.hpd_eop_gpu_addr, 4233 (void **)&hpd); 4234 if (r) { 4235 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4236 gfx_v10_0_mec_fini(adev); 4237 return r; 4238 } 4239 4240 memset(hpd, 0, mec_hpd_size); 4241 4242 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4243 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4244 } 4245 4246 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4247 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4248 4249 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4250 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4251 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4252 4253 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4254 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4255 &adev->gfx.mec.mec_fw_obj, 4256 &adev->gfx.mec.mec_fw_gpu_addr, 4257 (void **)&fw); 4258 if (r) { 4259 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4260 gfx_v10_0_mec_fini(adev); 4261 return r; 4262 } 4263 4264 memcpy(fw, fw_data, fw_size); 4265 4266 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4267 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4268 } 4269 4270 return 0; 4271 } 4272 4273 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4274 { 4275 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4276 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4277 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4278 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4279 } 4280 4281 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4282 uint32_t thread, uint32_t regno, 4283 uint32_t num, uint32_t *out) 4284 { 4285 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4286 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4287 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4288 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4289 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4290 while (num--) 4291 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4292 } 4293 4294 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4295 { 4296 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4297 * field when performing a select_se_sh so it should be 4298 * zero here */ 4299 WARN_ON(simd != 0); 4300 4301 /* type 2 wave data */ 4302 dst[(*no_fields)++] = 2; 4303 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4304 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4305 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4306 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4307 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4308 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4309 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4310 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4311 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4312 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4313 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4314 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4315 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4316 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4317 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4318 } 4319 4320 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4321 uint32_t wave, uint32_t start, 4322 uint32_t size, uint32_t *dst) 4323 { 4324 WARN_ON(simd != 0); 4325 4326 wave_read_regs( 4327 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4328 dst); 4329 } 4330 4331 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4332 uint32_t wave, uint32_t thread, 4333 uint32_t start, uint32_t size, 4334 uint32_t *dst) 4335 { 4336 wave_read_regs( 4337 adev, wave, thread, 4338 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4339 } 4340 4341 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4342 u32 me, u32 pipe, u32 q, u32 vm) 4343 { 4344 nv_grbm_select(adev, me, pipe, q, vm); 4345 } 4346 4347 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4348 bool enable) 4349 { 4350 uint32_t data, def; 4351 4352 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4353 4354 if (enable) 4355 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4356 else 4357 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4358 4359 if (data != def) 4360 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4361 } 4362 4363 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4364 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4365 .select_se_sh = &gfx_v10_0_select_se_sh, 4366 .read_wave_data = &gfx_v10_0_read_wave_data, 4367 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4368 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4369 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4370 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4371 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4372 }; 4373 4374 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4375 { 4376 u32 gb_addr_config; 4377 4378 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 4379 4380 switch (adev->asic_type) { 4381 case CHIP_NAVI10: 4382 case CHIP_NAVI14: 4383 case CHIP_NAVI12: 4384 adev->gfx.config.max_hw_contexts = 8; 4385 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4386 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4387 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4388 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4389 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4390 break; 4391 case CHIP_SIENNA_CICHLID: 4392 case CHIP_NAVY_FLOUNDER: 4393 case CHIP_VANGOGH: 4394 case CHIP_DIMGREY_CAVEFISH: 4395 adev->gfx.config.max_hw_contexts = 8; 4396 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4397 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4398 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4399 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4400 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4401 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4402 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4403 break; 4404 default: 4405 BUG(); 4406 break; 4407 } 4408 4409 adev->gfx.config.gb_addr_config = gb_addr_config; 4410 4411 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4412 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4413 GB_ADDR_CONFIG, NUM_PIPES); 4414 4415 adev->gfx.config.max_tile_pipes = 4416 adev->gfx.config.gb_addr_config_fields.num_pipes; 4417 4418 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4419 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4420 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4421 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4422 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4423 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4424 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4425 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4426 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4427 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4428 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4429 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4430 } 4431 4432 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4433 int me, int pipe, int queue) 4434 { 4435 int r; 4436 struct amdgpu_ring *ring; 4437 unsigned int irq_type; 4438 4439 ring = &adev->gfx.gfx_ring[ring_id]; 4440 4441 ring->me = me; 4442 ring->pipe = pipe; 4443 ring->queue = queue; 4444 4445 ring->ring_obj = NULL; 4446 ring->use_doorbell = true; 4447 4448 if (!ring_id) 4449 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4450 else 4451 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4452 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4453 4454 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4455 r = amdgpu_ring_init(adev, ring, 1024, 4456 &adev->gfx.eop_irq, irq_type, 4457 AMDGPU_RING_PRIO_DEFAULT); 4458 if (r) 4459 return r; 4460 return 0; 4461 } 4462 4463 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4464 int mec, int pipe, int queue) 4465 { 4466 int r; 4467 unsigned irq_type; 4468 struct amdgpu_ring *ring; 4469 unsigned int hw_prio; 4470 4471 ring = &adev->gfx.compute_ring[ring_id]; 4472 4473 /* mec0 is me1 */ 4474 ring->me = mec + 1; 4475 ring->pipe = pipe; 4476 ring->queue = queue; 4477 4478 ring->ring_obj = NULL; 4479 ring->use_doorbell = true; 4480 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4481 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4482 + (ring_id * GFX10_MEC_HPD_SIZE); 4483 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4484 4485 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4486 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4487 + ring->pipe; 4488 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 4489 ring->queue) ? 4490 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4491 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4492 r = amdgpu_ring_init(adev, ring, 1024, 4493 &adev->gfx.eop_irq, irq_type, hw_prio); 4494 if (r) 4495 return r; 4496 4497 return 0; 4498 } 4499 4500 static int gfx_v10_0_sw_init(void *handle) 4501 { 4502 int i, j, k, r, ring_id = 0; 4503 struct amdgpu_kiq *kiq; 4504 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4505 4506 switch (adev->asic_type) { 4507 case CHIP_NAVI10: 4508 case CHIP_NAVI14: 4509 case CHIP_NAVI12: 4510 adev->gfx.me.num_me = 1; 4511 adev->gfx.me.num_pipe_per_me = 1; 4512 adev->gfx.me.num_queue_per_pipe = 1; 4513 adev->gfx.mec.num_mec = 2; 4514 adev->gfx.mec.num_pipe_per_mec = 4; 4515 adev->gfx.mec.num_queue_per_pipe = 8; 4516 break; 4517 case CHIP_SIENNA_CICHLID: 4518 case CHIP_NAVY_FLOUNDER: 4519 case CHIP_VANGOGH: 4520 case CHIP_DIMGREY_CAVEFISH: 4521 adev->gfx.me.num_me = 1; 4522 adev->gfx.me.num_pipe_per_me = 1; 4523 adev->gfx.me.num_queue_per_pipe = 1; 4524 adev->gfx.mec.num_mec = 2; 4525 adev->gfx.mec.num_pipe_per_mec = 4; 4526 adev->gfx.mec.num_queue_per_pipe = 4; 4527 break; 4528 default: 4529 adev->gfx.me.num_me = 1; 4530 adev->gfx.me.num_pipe_per_me = 1; 4531 adev->gfx.me.num_queue_per_pipe = 1; 4532 adev->gfx.mec.num_mec = 1; 4533 adev->gfx.mec.num_pipe_per_mec = 4; 4534 adev->gfx.mec.num_queue_per_pipe = 8; 4535 break; 4536 } 4537 4538 /* KIQ event */ 4539 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4540 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4541 &adev->gfx.kiq.irq); 4542 if (r) 4543 return r; 4544 4545 /* EOP Event */ 4546 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4547 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4548 &adev->gfx.eop_irq); 4549 if (r) 4550 return r; 4551 4552 /* Privileged reg */ 4553 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4554 &adev->gfx.priv_reg_irq); 4555 if (r) 4556 return r; 4557 4558 /* Privileged inst */ 4559 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4560 &adev->gfx.priv_inst_irq); 4561 if (r) 4562 return r; 4563 4564 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4565 4566 gfx_v10_0_scratch_init(adev); 4567 4568 r = gfx_v10_0_me_init(adev); 4569 if (r) 4570 return r; 4571 4572 r = gfx_v10_0_rlc_init(adev); 4573 if (r) { 4574 DRM_ERROR("Failed to init rlc BOs!\n"); 4575 return r; 4576 } 4577 4578 r = gfx_v10_0_mec_init(adev); 4579 if (r) { 4580 DRM_ERROR("Failed to init MEC BOs!\n"); 4581 return r; 4582 } 4583 4584 /* set up the gfx ring */ 4585 for (i = 0; i < adev->gfx.me.num_me; i++) { 4586 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4587 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4588 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4589 continue; 4590 4591 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4592 i, k, j); 4593 if (r) 4594 return r; 4595 ring_id++; 4596 } 4597 } 4598 } 4599 4600 ring_id = 0; 4601 /* set up the compute queues - allocate horizontally across pipes */ 4602 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4603 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4604 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4605 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4606 j)) 4607 continue; 4608 4609 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4610 i, k, j); 4611 if (r) 4612 return r; 4613 4614 ring_id++; 4615 } 4616 } 4617 } 4618 4619 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4620 if (r) { 4621 DRM_ERROR("Failed to init KIQ BOs!\n"); 4622 return r; 4623 } 4624 4625 kiq = &adev->gfx.kiq; 4626 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4627 if (r) 4628 return r; 4629 4630 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4631 if (r) 4632 return r; 4633 4634 /* allocate visible FB for rlc auto-loading fw */ 4635 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4636 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4637 if (r) 4638 return r; 4639 } 4640 4641 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4642 4643 gfx_v10_0_gpu_early_init(adev); 4644 4645 return 0; 4646 } 4647 4648 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4649 { 4650 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4651 &adev->gfx.pfp.pfp_fw_gpu_addr, 4652 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4653 } 4654 4655 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4656 { 4657 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4658 &adev->gfx.ce.ce_fw_gpu_addr, 4659 (void **)&adev->gfx.ce.ce_fw_ptr); 4660 } 4661 4662 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4663 { 4664 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4665 &adev->gfx.me.me_fw_gpu_addr, 4666 (void **)&adev->gfx.me.me_fw_ptr); 4667 } 4668 4669 static int gfx_v10_0_sw_fini(void *handle) 4670 { 4671 int i; 4672 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4673 4674 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4675 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4676 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4677 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4678 4679 amdgpu_gfx_mqd_sw_fini(adev); 4680 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4681 amdgpu_gfx_kiq_fini(adev); 4682 4683 gfx_v10_0_pfp_fini(adev); 4684 gfx_v10_0_ce_fini(adev); 4685 gfx_v10_0_me_fini(adev); 4686 gfx_v10_0_rlc_fini(adev); 4687 gfx_v10_0_mec_fini(adev); 4688 4689 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4690 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4691 4692 gfx_v10_0_free_microcode(adev); 4693 4694 return 0; 4695 } 4696 4697 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4698 u32 sh_num, u32 instance) 4699 { 4700 u32 data; 4701 4702 if (instance == 0xffffffff) 4703 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4704 INSTANCE_BROADCAST_WRITES, 1); 4705 else 4706 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4707 instance); 4708 4709 if (se_num == 0xffffffff) 4710 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4711 1); 4712 else 4713 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4714 4715 if (sh_num == 0xffffffff) 4716 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4717 1); 4718 else 4719 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4720 4721 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4722 } 4723 4724 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4725 { 4726 u32 data, mask; 4727 4728 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4729 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4730 4731 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4732 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4733 4734 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4735 adev->gfx.config.max_sh_per_se); 4736 4737 return (~data) & mask; 4738 } 4739 4740 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4741 { 4742 int i, j; 4743 u32 data; 4744 u32 active_rbs = 0; 4745 u32 bitmap; 4746 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4747 adev->gfx.config.max_sh_per_se; 4748 4749 mutex_lock(&adev->grbm_idx_mutex); 4750 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4751 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4752 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4753 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 4754 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4755 continue; 4756 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4757 data = gfx_v10_0_get_rb_active_bitmap(adev); 4758 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4759 rb_bitmap_width_per_sh); 4760 } 4761 } 4762 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4763 mutex_unlock(&adev->grbm_idx_mutex); 4764 4765 adev->gfx.config.backend_enable_mask = active_rbs; 4766 adev->gfx.config.num_rbs = hweight32(active_rbs); 4767 } 4768 4769 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4770 { 4771 uint32_t num_sc; 4772 uint32_t enabled_rb_per_sh; 4773 uint32_t active_rb_bitmap; 4774 uint32_t num_rb_per_sc; 4775 uint32_t num_packer_per_sc; 4776 uint32_t pa_sc_tile_steering_override; 4777 4778 /* for ASICs that integrates GFX v10.3 4779 * pa_sc_tile_steering_override should be set to 0 */ 4780 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 4781 return 0; 4782 4783 /* init num_sc */ 4784 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4785 adev->gfx.config.num_sc_per_sh; 4786 /* init num_rb_per_sc */ 4787 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4788 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4789 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4790 /* init num_packer_per_sc */ 4791 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4792 4793 pa_sc_tile_steering_override = 0; 4794 pa_sc_tile_steering_override |= 4795 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4796 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4797 pa_sc_tile_steering_override |= 4798 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4799 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4800 pa_sc_tile_steering_override |= 4801 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4802 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4803 4804 return pa_sc_tile_steering_override; 4805 } 4806 4807 #define DEFAULT_SH_MEM_BASES (0x6000) 4808 4809 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4810 { 4811 int i; 4812 uint32_t sh_mem_bases; 4813 4814 /* 4815 * Configure apertures: 4816 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4817 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4818 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4819 */ 4820 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4821 4822 mutex_lock(&adev->srbm_mutex); 4823 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4824 nv_grbm_select(adev, 0, 0, 0, i); 4825 /* CP and shaders */ 4826 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4827 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4828 } 4829 nv_grbm_select(adev, 0, 0, 0, 0); 4830 mutex_unlock(&adev->srbm_mutex); 4831 4832 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4833 acccess. These should be enabled by FW for target VMIDs. */ 4834 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4835 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4836 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4837 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4838 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4839 } 4840 } 4841 4842 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4843 { 4844 int vmid; 4845 4846 /* 4847 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4848 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4849 * the driver can enable them for graphics. VMID0 should maintain 4850 * access so that HWS firmware can save/restore entries. 4851 */ 4852 for (vmid = 1; vmid < 16; vmid++) { 4853 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4854 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4855 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4856 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4857 } 4858 } 4859 4860 4861 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4862 { 4863 int i, j, k; 4864 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4865 u32 tmp, wgp_active_bitmap = 0; 4866 u32 gcrd_targets_disable_tcp = 0; 4867 u32 utcl_invreq_disable = 0; 4868 /* 4869 * GCRD_TARGETS_DISABLE field contains 4870 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4871 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4872 */ 4873 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4874 2 * max_wgp_per_sh + /* TCP */ 4875 max_wgp_per_sh + /* SQC */ 4876 4); /* GL1C */ 4877 /* 4878 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4879 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4880 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4881 */ 4882 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4883 2 * max_wgp_per_sh + /* TCP */ 4884 2 * max_wgp_per_sh + /* SQC */ 4885 4 + /* RMI */ 4886 1); /* SQG */ 4887 4888 if (adev->asic_type == CHIP_NAVI10 || 4889 adev->asic_type == CHIP_NAVI14 || 4890 adev->asic_type == CHIP_NAVI12) { 4891 mutex_lock(&adev->grbm_idx_mutex); 4892 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4893 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4894 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4895 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4896 /* 4897 * Set corresponding TCP bits for the inactive WGPs in 4898 * GCRD_SA_TARGETS_DISABLE 4899 */ 4900 gcrd_targets_disable_tcp = 0; 4901 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4902 utcl_invreq_disable = 0; 4903 4904 for (k = 0; k < max_wgp_per_sh; k++) { 4905 if (!(wgp_active_bitmap & (1 << k))) { 4906 gcrd_targets_disable_tcp |= 3 << (2 * k); 4907 utcl_invreq_disable |= (3 << (2 * k)) | 4908 (3 << (2 * (max_wgp_per_sh + k))); 4909 } 4910 } 4911 4912 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4913 /* only override TCP & SQC bits */ 4914 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 4915 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4916 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4917 4918 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4919 /* only override TCP bits */ 4920 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 4921 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4922 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4923 } 4924 } 4925 4926 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4927 mutex_unlock(&adev->grbm_idx_mutex); 4928 } 4929 } 4930 4931 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4932 { 4933 /* TCCs are global (not instanced). */ 4934 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4935 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4936 4937 adev->gfx.config.tcc_disabled_mask = 4938 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4939 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4940 } 4941 4942 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4943 { 4944 u32 tmp; 4945 int i; 4946 4947 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4948 4949 gfx_v10_0_setup_rb(adev); 4950 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4951 gfx_v10_0_get_tcc_info(adev); 4952 adev->gfx.config.pa_sc_tile_steering_override = 4953 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4954 4955 /* XXX SH_MEM regs */ 4956 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4957 mutex_lock(&adev->srbm_mutex); 4958 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 4959 nv_grbm_select(adev, 0, 0, 0, i); 4960 /* CP and shaders */ 4961 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4962 if (i != 0) { 4963 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4964 (adev->gmc.private_aperture_start >> 48)); 4965 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4966 (adev->gmc.shared_aperture_start >> 48)); 4967 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4968 } 4969 } 4970 nv_grbm_select(adev, 0, 0, 0, 0); 4971 4972 mutex_unlock(&adev->srbm_mutex); 4973 4974 gfx_v10_0_init_compute_vmid(adev); 4975 gfx_v10_0_init_gds_vmid(adev); 4976 4977 } 4978 4979 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 4980 bool enable) 4981 { 4982 u32 tmp; 4983 4984 if (amdgpu_sriov_vf(adev)) 4985 return; 4986 4987 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 4988 4989 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 4990 enable ? 1 : 0); 4991 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 4992 enable ? 1 : 0); 4993 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 4994 enable ? 1 : 0); 4995 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 4996 enable ? 1 : 0); 4997 4998 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 4999 } 5000 5001 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5002 { 5003 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5004 5005 /* csib */ 5006 if (adev->asic_type == CHIP_NAVI12) { 5007 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5008 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5009 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5010 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5011 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5012 } else { 5013 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5014 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5015 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5016 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5017 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5018 } 5019 return 0; 5020 } 5021 5022 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5023 { 5024 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5025 5026 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5027 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5028 } 5029 5030 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5031 { 5032 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5033 udelay(50); 5034 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5035 udelay(50); 5036 } 5037 5038 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5039 bool enable) 5040 { 5041 uint32_t rlc_pg_cntl; 5042 5043 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5044 5045 if (!enable) { 5046 /* RLC_PG_CNTL[23] = 0 (default) 5047 * RLC will wait for handshake acks with SMU 5048 * GFXOFF will be enabled 5049 * RLC_PG_CNTL[23] = 1 5050 * RLC will not issue any message to SMU 5051 * hence no handshake between SMU & RLC 5052 * GFXOFF will be disabled 5053 */ 5054 rlc_pg_cntl |= 0x800000; 5055 } else 5056 rlc_pg_cntl &= ~0x800000; 5057 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5058 } 5059 5060 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5061 { 5062 /* TODO: enable rlc & smu handshake until smu 5063 * and gfxoff feature works as expected */ 5064 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5065 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5066 5067 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5068 udelay(50); 5069 } 5070 5071 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5072 { 5073 uint32_t tmp; 5074 5075 /* enable Save Restore Machine */ 5076 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 5077 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5078 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5079 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 5080 } 5081 5082 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5083 { 5084 const struct rlc_firmware_header_v2_0 *hdr; 5085 const __le32 *fw_data; 5086 unsigned i, fw_size; 5087 5088 if (!adev->gfx.rlc_fw) 5089 return -EINVAL; 5090 5091 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5092 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5093 5094 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5095 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5096 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5097 5098 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5099 RLCG_UCODE_LOADING_START_ADDRESS); 5100 5101 for (i = 0; i < fw_size; i++) 5102 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5103 le32_to_cpup(fw_data++)); 5104 5105 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5106 5107 return 0; 5108 } 5109 5110 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5111 { 5112 int r; 5113 5114 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 5115 5116 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5117 if (r) 5118 return r; 5119 5120 gfx_v10_0_init_csb(adev); 5121 5122 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5123 gfx_v10_0_rlc_enable_srm(adev); 5124 } else { 5125 if (amdgpu_sriov_vf(adev)) { 5126 gfx_v10_0_init_csb(adev); 5127 return 0; 5128 } 5129 5130 adev->gfx.rlc.funcs->stop(adev); 5131 5132 /* disable CG */ 5133 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5134 5135 /* disable PG */ 5136 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5137 5138 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5139 /* legacy rlc firmware loading */ 5140 r = gfx_v10_0_rlc_load_microcode(adev); 5141 if (r) 5142 return r; 5143 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5144 /* rlc backdoor autoload firmware */ 5145 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5146 if (r) 5147 return r; 5148 } 5149 5150 gfx_v10_0_init_csb(adev); 5151 5152 adev->gfx.rlc.funcs->start(adev); 5153 5154 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5155 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5156 if (r) 5157 return r; 5158 } 5159 } 5160 return 0; 5161 } 5162 5163 static struct { 5164 FIRMWARE_ID id; 5165 unsigned int offset; 5166 unsigned int size; 5167 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5168 5169 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5170 { 5171 int ret; 5172 RLC_TABLE_OF_CONTENT *rlc_toc; 5173 5174 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 5175 AMDGPU_GEM_DOMAIN_GTT, 5176 &adev->gfx.rlc.rlc_toc_bo, 5177 &adev->gfx.rlc.rlc_toc_gpu_addr, 5178 (void **)&adev->gfx.rlc.rlc_toc_buf); 5179 if (ret) { 5180 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5181 return ret; 5182 } 5183 5184 /* Copy toc from psp sos fw to rlc toc buffer */ 5185 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 5186 5187 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5188 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5189 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5190 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5191 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5192 /* Offset needs 4KB alignment */ 5193 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5194 } 5195 5196 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5197 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5198 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5199 5200 rlc_toc++; 5201 } 5202 5203 return 0; 5204 } 5205 5206 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5207 { 5208 uint32_t total_size = 0; 5209 FIRMWARE_ID id; 5210 int ret; 5211 5212 ret = gfx_v10_0_parse_rlc_toc(adev); 5213 if (ret) { 5214 dev_err(adev->dev, "failed to parse rlc toc\n"); 5215 return 0; 5216 } 5217 5218 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5219 total_size += rlc_autoload_info[id].size; 5220 5221 /* In case the offset in rlc toc ucode is aligned */ 5222 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5223 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5224 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5225 5226 return total_size; 5227 } 5228 5229 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5230 { 5231 int r; 5232 uint32_t total_size; 5233 5234 total_size = gfx_v10_0_calc_toc_total_size(adev); 5235 5236 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5237 AMDGPU_GEM_DOMAIN_GTT, 5238 &adev->gfx.rlc.rlc_autoload_bo, 5239 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5240 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5241 if (r) { 5242 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5243 return r; 5244 } 5245 5246 return 0; 5247 } 5248 5249 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5250 { 5251 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5252 &adev->gfx.rlc.rlc_toc_gpu_addr, 5253 (void **)&adev->gfx.rlc.rlc_toc_buf); 5254 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5255 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5256 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5257 } 5258 5259 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5260 FIRMWARE_ID id, 5261 const void *fw_data, 5262 uint32_t fw_size) 5263 { 5264 uint32_t toc_offset; 5265 uint32_t toc_fw_size; 5266 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5267 5268 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5269 return; 5270 5271 toc_offset = rlc_autoload_info[id].offset; 5272 toc_fw_size = rlc_autoload_info[id].size; 5273 5274 if (fw_size == 0) 5275 fw_size = toc_fw_size; 5276 5277 if (fw_size > toc_fw_size) 5278 fw_size = toc_fw_size; 5279 5280 memcpy(ptr + toc_offset, fw_data, fw_size); 5281 5282 if (fw_size < toc_fw_size) 5283 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5284 } 5285 5286 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5287 { 5288 void *data; 5289 uint32_t size; 5290 5291 data = adev->gfx.rlc.rlc_toc_buf; 5292 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5293 5294 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5295 FIRMWARE_ID_RLC_TOC, 5296 data, size); 5297 } 5298 5299 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5300 { 5301 const __le32 *fw_data; 5302 uint32_t fw_size; 5303 const struct gfx_firmware_header_v1_0 *cp_hdr; 5304 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5305 5306 /* pfp ucode */ 5307 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5308 adev->gfx.pfp_fw->data; 5309 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5310 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5311 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5312 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5313 FIRMWARE_ID_CP_PFP, 5314 fw_data, fw_size); 5315 5316 /* ce ucode */ 5317 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5318 adev->gfx.ce_fw->data; 5319 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5320 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5321 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5322 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5323 FIRMWARE_ID_CP_CE, 5324 fw_data, fw_size); 5325 5326 /* me ucode */ 5327 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5328 adev->gfx.me_fw->data; 5329 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5330 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5331 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5332 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5333 FIRMWARE_ID_CP_ME, 5334 fw_data, fw_size); 5335 5336 /* rlc ucode */ 5337 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5338 adev->gfx.rlc_fw->data; 5339 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5340 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5341 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5342 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5343 FIRMWARE_ID_RLC_G_UCODE, 5344 fw_data, fw_size); 5345 5346 /* mec1 ucode */ 5347 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5348 adev->gfx.mec_fw->data; 5349 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5350 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5351 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5352 cp_hdr->jt_size * 4; 5353 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5354 FIRMWARE_ID_CP_MEC, 5355 fw_data, fw_size); 5356 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5357 } 5358 5359 /* Temporarily put sdma part here */ 5360 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5361 { 5362 const __le32 *fw_data; 5363 uint32_t fw_size; 5364 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5365 int i; 5366 5367 for (i = 0; i < adev->sdma.num_instances; i++) { 5368 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5369 adev->sdma.instance[i].fw->data; 5370 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5371 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5372 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5373 5374 if (i == 0) { 5375 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5376 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5377 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5378 FIRMWARE_ID_SDMA0_JT, 5379 (uint32_t *)fw_data + 5380 sdma_hdr->jt_offset, 5381 sdma_hdr->jt_size * 4); 5382 } else if (i == 1) { 5383 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5384 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5385 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5386 FIRMWARE_ID_SDMA1_JT, 5387 (uint32_t *)fw_data + 5388 sdma_hdr->jt_offset, 5389 sdma_hdr->jt_size * 4); 5390 } 5391 } 5392 } 5393 5394 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5395 { 5396 uint32_t rlc_g_offset, rlc_g_size, tmp; 5397 uint64_t gpu_addr; 5398 5399 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5400 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5401 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5402 5403 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5404 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5405 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5406 5407 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5408 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5409 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5410 5411 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5412 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5413 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5414 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5415 return -EINVAL; 5416 } 5417 5418 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5419 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5420 DRM_ERROR("RLC ROM should halt itself\n"); 5421 return -EINVAL; 5422 } 5423 5424 return 0; 5425 } 5426 5427 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5428 { 5429 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5430 uint32_t tmp; 5431 int i; 5432 uint64_t addr; 5433 5434 /* Trigger an invalidation of the L1 instruction caches */ 5435 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5436 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5437 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5438 5439 /* Wait for invalidation complete */ 5440 for (i = 0; i < usec_timeout; i++) { 5441 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5442 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5443 INVALIDATE_CACHE_COMPLETE)) 5444 break; 5445 udelay(1); 5446 } 5447 5448 if (i >= usec_timeout) { 5449 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5450 return -EINVAL; 5451 } 5452 5453 /* Program me ucode address into intruction cache address register */ 5454 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5455 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5456 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5457 lower_32_bits(addr) & 0xFFFFF000); 5458 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5459 upper_32_bits(addr)); 5460 5461 return 0; 5462 } 5463 5464 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5465 { 5466 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5467 uint32_t tmp; 5468 int i; 5469 uint64_t addr; 5470 5471 /* Trigger an invalidation of the L1 instruction caches */ 5472 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5473 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5474 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5475 5476 /* Wait for invalidation complete */ 5477 for (i = 0; i < usec_timeout; i++) { 5478 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5479 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5480 INVALIDATE_CACHE_COMPLETE)) 5481 break; 5482 udelay(1); 5483 } 5484 5485 if (i >= usec_timeout) { 5486 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5487 return -EINVAL; 5488 } 5489 5490 /* Program ce ucode address into intruction cache address register */ 5491 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5492 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5493 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5494 lower_32_bits(addr) & 0xFFFFF000); 5495 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5496 upper_32_bits(addr)); 5497 5498 return 0; 5499 } 5500 5501 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5502 { 5503 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5504 uint32_t tmp; 5505 int i; 5506 uint64_t addr; 5507 5508 /* Trigger an invalidation of the L1 instruction caches */ 5509 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5510 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5511 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5512 5513 /* Wait for invalidation complete */ 5514 for (i = 0; i < usec_timeout; i++) { 5515 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5516 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5517 INVALIDATE_CACHE_COMPLETE)) 5518 break; 5519 udelay(1); 5520 } 5521 5522 if (i >= usec_timeout) { 5523 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5524 return -EINVAL; 5525 } 5526 5527 /* Program pfp ucode address into intruction cache address register */ 5528 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5529 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5530 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5531 lower_32_bits(addr) & 0xFFFFF000); 5532 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5533 upper_32_bits(addr)); 5534 5535 return 0; 5536 } 5537 5538 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5539 { 5540 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5541 uint32_t tmp; 5542 int i; 5543 uint64_t addr; 5544 5545 /* Trigger an invalidation of the L1 instruction caches */ 5546 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5547 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5548 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5549 5550 /* Wait for invalidation complete */ 5551 for (i = 0; i < usec_timeout; i++) { 5552 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5553 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5554 INVALIDATE_CACHE_COMPLETE)) 5555 break; 5556 udelay(1); 5557 } 5558 5559 if (i >= usec_timeout) { 5560 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5561 return -EINVAL; 5562 } 5563 5564 /* Program mec1 ucode address into intruction cache address register */ 5565 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5566 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5567 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5568 lower_32_bits(addr) & 0xFFFFF000); 5569 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5570 upper_32_bits(addr)); 5571 5572 return 0; 5573 } 5574 5575 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5576 { 5577 uint32_t cp_status; 5578 uint32_t bootload_status; 5579 int i, r; 5580 5581 for (i = 0; i < adev->usec_timeout; i++) { 5582 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5583 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5584 if ((cp_status == 0) && 5585 (REG_GET_FIELD(bootload_status, 5586 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5587 break; 5588 } 5589 udelay(1); 5590 } 5591 5592 if (i >= adev->usec_timeout) { 5593 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5594 return -ETIMEDOUT; 5595 } 5596 5597 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5598 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5599 if (r) 5600 return r; 5601 5602 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5603 if (r) 5604 return r; 5605 5606 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5607 if (r) 5608 return r; 5609 5610 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5611 if (r) 5612 return r; 5613 } 5614 5615 return 0; 5616 } 5617 5618 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5619 { 5620 int i; 5621 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5622 5623 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5624 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5625 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5626 5627 if (adev->asic_type == CHIP_NAVI12) { 5628 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5629 } else { 5630 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5631 } 5632 5633 for (i = 0; i < adev->usec_timeout; i++) { 5634 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5635 break; 5636 udelay(1); 5637 } 5638 5639 if (i >= adev->usec_timeout) 5640 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5641 5642 return 0; 5643 } 5644 5645 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5646 { 5647 int r; 5648 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5649 const __le32 *fw_data; 5650 unsigned i, fw_size; 5651 uint32_t tmp; 5652 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5653 5654 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5655 adev->gfx.pfp_fw->data; 5656 5657 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5658 5659 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5660 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5661 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5662 5663 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5664 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5665 &adev->gfx.pfp.pfp_fw_obj, 5666 &adev->gfx.pfp.pfp_fw_gpu_addr, 5667 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5668 if (r) { 5669 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5670 gfx_v10_0_pfp_fini(adev); 5671 return r; 5672 } 5673 5674 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5675 5676 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5677 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5678 5679 /* Trigger an invalidation of the L1 instruction caches */ 5680 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5681 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5682 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5683 5684 /* Wait for invalidation complete */ 5685 for (i = 0; i < usec_timeout; i++) { 5686 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5687 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5688 INVALIDATE_CACHE_COMPLETE)) 5689 break; 5690 udelay(1); 5691 } 5692 5693 if (i >= usec_timeout) { 5694 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5695 return -EINVAL; 5696 } 5697 5698 if (amdgpu_emu_mode == 1) 5699 adev->nbio.funcs->hdp_flush(adev, NULL); 5700 5701 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5702 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5703 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5704 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5705 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5706 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5707 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5708 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5709 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5710 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5711 5712 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5713 5714 for (i = 0; i < pfp_hdr->jt_size; i++) 5715 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5716 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5717 5718 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5719 5720 return 0; 5721 } 5722 5723 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5724 { 5725 int r; 5726 const struct gfx_firmware_header_v1_0 *ce_hdr; 5727 const __le32 *fw_data; 5728 unsigned i, fw_size; 5729 uint32_t tmp; 5730 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5731 5732 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5733 adev->gfx.ce_fw->data; 5734 5735 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5736 5737 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5738 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5739 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5740 5741 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5742 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5743 &adev->gfx.ce.ce_fw_obj, 5744 &adev->gfx.ce.ce_fw_gpu_addr, 5745 (void **)&adev->gfx.ce.ce_fw_ptr); 5746 if (r) { 5747 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5748 gfx_v10_0_ce_fini(adev); 5749 return r; 5750 } 5751 5752 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5753 5754 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5755 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5756 5757 /* Trigger an invalidation of the L1 instruction caches */ 5758 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5759 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5760 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5761 5762 /* Wait for invalidation complete */ 5763 for (i = 0; i < usec_timeout; i++) { 5764 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5765 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5766 INVALIDATE_CACHE_COMPLETE)) 5767 break; 5768 udelay(1); 5769 } 5770 5771 if (i >= usec_timeout) { 5772 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5773 return -EINVAL; 5774 } 5775 5776 if (amdgpu_emu_mode == 1) 5777 adev->nbio.funcs->hdp_flush(adev, NULL); 5778 5779 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5780 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5781 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5782 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5783 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5784 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5785 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5786 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5787 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5788 5789 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5790 5791 for (i = 0; i < ce_hdr->jt_size; i++) 5792 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5793 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5794 5795 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5796 5797 return 0; 5798 } 5799 5800 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5801 { 5802 int r; 5803 const struct gfx_firmware_header_v1_0 *me_hdr; 5804 const __le32 *fw_data; 5805 unsigned i, fw_size; 5806 uint32_t tmp; 5807 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5808 5809 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5810 adev->gfx.me_fw->data; 5811 5812 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5813 5814 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5815 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5816 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5817 5818 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5819 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5820 &adev->gfx.me.me_fw_obj, 5821 &adev->gfx.me.me_fw_gpu_addr, 5822 (void **)&adev->gfx.me.me_fw_ptr); 5823 if (r) { 5824 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5825 gfx_v10_0_me_fini(adev); 5826 return r; 5827 } 5828 5829 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5830 5831 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5832 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5833 5834 /* Trigger an invalidation of the L1 instruction caches */ 5835 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5836 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5837 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5838 5839 /* Wait for invalidation complete */ 5840 for (i = 0; i < usec_timeout; i++) { 5841 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5842 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5843 INVALIDATE_CACHE_COMPLETE)) 5844 break; 5845 udelay(1); 5846 } 5847 5848 if (i >= usec_timeout) { 5849 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5850 return -EINVAL; 5851 } 5852 5853 if (amdgpu_emu_mode == 1) 5854 adev->nbio.funcs->hdp_flush(adev, NULL); 5855 5856 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5857 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5858 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5859 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5860 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5861 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5862 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5863 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5864 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5865 5866 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5867 5868 for (i = 0; i < me_hdr->jt_size; i++) 5869 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5870 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5871 5872 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5873 5874 return 0; 5875 } 5876 5877 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5878 { 5879 int r; 5880 5881 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5882 return -EINVAL; 5883 5884 gfx_v10_0_cp_gfx_enable(adev, false); 5885 5886 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5887 if (r) { 5888 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5889 return r; 5890 } 5891 5892 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5893 if (r) { 5894 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5895 return r; 5896 } 5897 5898 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5899 if (r) { 5900 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5901 return r; 5902 } 5903 5904 return 0; 5905 } 5906 5907 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5908 { 5909 struct amdgpu_ring *ring; 5910 const struct cs_section_def *sect = NULL; 5911 const struct cs_extent_def *ext = NULL; 5912 int r, i; 5913 int ctx_reg_offset; 5914 5915 /* init the CP */ 5916 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5917 adev->gfx.config.max_hw_contexts - 1); 5918 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5919 5920 gfx_v10_0_cp_gfx_enable(adev, true); 5921 5922 ring = &adev->gfx.gfx_ring[0]; 5923 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5924 if (r) { 5925 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5926 return r; 5927 } 5928 5929 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5930 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5931 5932 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5933 amdgpu_ring_write(ring, 0x80000000); 5934 amdgpu_ring_write(ring, 0x80000000); 5935 5936 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5937 for (ext = sect->section; ext->extent != NULL; ++ext) { 5938 if (sect->id == SECT_CONTEXT) { 5939 amdgpu_ring_write(ring, 5940 PACKET3(PACKET3_SET_CONTEXT_REG, 5941 ext->reg_count)); 5942 amdgpu_ring_write(ring, ext->reg_index - 5943 PACKET3_SET_CONTEXT_REG_START); 5944 for (i = 0; i < ext->reg_count; i++) 5945 amdgpu_ring_write(ring, ext->extent[i]); 5946 } 5947 } 5948 } 5949 5950 ctx_reg_offset = 5951 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5952 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5953 amdgpu_ring_write(ring, ctx_reg_offset); 5954 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5955 5956 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5957 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5958 5959 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5960 amdgpu_ring_write(ring, 0); 5961 5962 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 5963 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 5964 amdgpu_ring_write(ring, 0x8000); 5965 amdgpu_ring_write(ring, 0x8000); 5966 5967 amdgpu_ring_commit(ring); 5968 5969 /* submit cs packet to copy state 0 to next available state */ 5970 if (adev->gfx.num_gfx_rings > 1) { 5971 /* maximum supported gfx ring is 2 */ 5972 ring = &adev->gfx.gfx_ring[1]; 5973 r = amdgpu_ring_alloc(ring, 2); 5974 if (r) { 5975 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5976 return r; 5977 } 5978 5979 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 5980 amdgpu_ring_write(ring, 0); 5981 5982 amdgpu_ring_commit(ring); 5983 } 5984 return 0; 5985 } 5986 5987 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 5988 CP_PIPE_ID pipe) 5989 { 5990 u32 tmp; 5991 5992 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 5993 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 5994 5995 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 5996 } 5997 5998 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 5999 struct amdgpu_ring *ring) 6000 { 6001 u32 tmp; 6002 6003 if (!amdgpu_async_gfx_ring) { 6004 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6005 if (ring->use_doorbell) { 6006 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6007 DOORBELL_OFFSET, ring->doorbell_index); 6008 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6009 DOORBELL_EN, 1); 6010 } else { 6011 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6012 DOORBELL_EN, 0); 6013 } 6014 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6015 } 6016 switch (adev->asic_type) { 6017 case CHIP_SIENNA_CICHLID: 6018 case CHIP_NAVY_FLOUNDER: 6019 case CHIP_VANGOGH: 6020 case CHIP_DIMGREY_CAVEFISH: 6021 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6022 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6023 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6024 6025 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6026 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6027 break; 6028 default: 6029 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6030 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6031 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6032 6033 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6034 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6035 break; 6036 } 6037 } 6038 6039 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6040 { 6041 struct amdgpu_ring *ring; 6042 u32 tmp; 6043 u32 rb_bufsz; 6044 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6045 u32 i; 6046 6047 /* Set the write pointer delay */ 6048 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6049 6050 /* set the RB to use vmid 0 */ 6051 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6052 6053 /* Init gfx ring 0 for pipe 0 */ 6054 mutex_lock(&adev->srbm_mutex); 6055 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6056 6057 /* Set ring buffer size */ 6058 ring = &adev->gfx.gfx_ring[0]; 6059 rb_bufsz = order_base_2(ring->ring_size / 8); 6060 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6061 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6062 #ifdef __BIG_ENDIAN 6063 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6064 #endif 6065 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6066 6067 /* Initialize the ring buffer's write pointers */ 6068 ring->wptr = 0; 6069 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6070 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6071 6072 /* set the wb address wether it's enabled or not */ 6073 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6074 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6075 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6076 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6077 6078 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6079 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6080 lower_32_bits(wptr_gpu_addr)); 6081 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6082 upper_32_bits(wptr_gpu_addr)); 6083 6084 mdelay(1); 6085 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6086 6087 rb_addr = ring->gpu_addr >> 8; 6088 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6089 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6090 6091 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6092 6093 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6094 mutex_unlock(&adev->srbm_mutex); 6095 6096 /* Init gfx ring 1 for pipe 1 */ 6097 if (adev->gfx.num_gfx_rings > 1) { 6098 mutex_lock(&adev->srbm_mutex); 6099 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6100 /* maximum supported gfx ring is 2 */ 6101 ring = &adev->gfx.gfx_ring[1]; 6102 rb_bufsz = order_base_2(ring->ring_size / 8); 6103 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6104 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6105 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6106 /* Initialize the ring buffer's write pointers */ 6107 ring->wptr = 0; 6108 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6109 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6110 /* Set the wb address wether it's enabled or not */ 6111 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6112 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6113 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6114 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6115 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6116 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6117 lower_32_bits(wptr_gpu_addr)); 6118 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6119 upper_32_bits(wptr_gpu_addr)); 6120 6121 mdelay(1); 6122 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6123 6124 rb_addr = ring->gpu_addr >> 8; 6125 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6126 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6127 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6128 6129 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6130 mutex_unlock(&adev->srbm_mutex); 6131 } 6132 /* Switch to pipe 0 */ 6133 mutex_lock(&adev->srbm_mutex); 6134 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6135 mutex_unlock(&adev->srbm_mutex); 6136 6137 /* start the ring */ 6138 gfx_v10_0_cp_gfx_start(adev); 6139 6140 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6141 ring = &adev->gfx.gfx_ring[i]; 6142 ring->sched.ready = true; 6143 } 6144 6145 return 0; 6146 } 6147 6148 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6149 { 6150 if (enable) { 6151 switch (adev->asic_type) { 6152 case CHIP_SIENNA_CICHLID: 6153 case CHIP_NAVY_FLOUNDER: 6154 case CHIP_VANGOGH: 6155 case CHIP_DIMGREY_CAVEFISH: 6156 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6157 break; 6158 default: 6159 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6160 break; 6161 } 6162 } else { 6163 switch (adev->asic_type) { 6164 case CHIP_SIENNA_CICHLID: 6165 case CHIP_NAVY_FLOUNDER: 6166 case CHIP_VANGOGH: 6167 case CHIP_DIMGREY_CAVEFISH: 6168 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6169 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6170 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6171 break; 6172 default: 6173 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6174 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6175 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6176 break; 6177 } 6178 adev->gfx.kiq.ring.sched.ready = false; 6179 } 6180 udelay(50); 6181 } 6182 6183 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6184 { 6185 const struct gfx_firmware_header_v1_0 *mec_hdr; 6186 const __le32 *fw_data; 6187 unsigned i; 6188 u32 tmp; 6189 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6190 6191 if (!adev->gfx.mec_fw) 6192 return -EINVAL; 6193 6194 gfx_v10_0_cp_compute_enable(adev, false); 6195 6196 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6197 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6198 6199 fw_data = (const __le32 *) 6200 (adev->gfx.mec_fw->data + 6201 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6202 6203 /* Trigger an invalidation of the L1 instruction caches */ 6204 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6205 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6206 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6207 6208 /* Wait for invalidation complete */ 6209 for (i = 0; i < usec_timeout; i++) { 6210 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6211 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6212 INVALIDATE_CACHE_COMPLETE)) 6213 break; 6214 udelay(1); 6215 } 6216 6217 if (i >= usec_timeout) { 6218 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6219 return -EINVAL; 6220 } 6221 6222 if (amdgpu_emu_mode == 1) 6223 adev->nbio.funcs->hdp_flush(adev, NULL); 6224 6225 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6226 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6227 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6228 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6229 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6230 6231 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6232 0xFFFFF000); 6233 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6234 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6235 6236 /* MEC1 */ 6237 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6238 6239 for (i = 0; i < mec_hdr->jt_size; i++) 6240 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6241 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6242 6243 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6244 6245 /* 6246 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6247 * different microcode than MEC1. 6248 */ 6249 6250 return 0; 6251 } 6252 6253 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6254 { 6255 uint32_t tmp; 6256 struct amdgpu_device *adev = ring->adev; 6257 6258 /* tell RLC which is KIQ queue */ 6259 switch (adev->asic_type) { 6260 case CHIP_SIENNA_CICHLID: 6261 case CHIP_NAVY_FLOUNDER: 6262 case CHIP_VANGOGH: 6263 case CHIP_DIMGREY_CAVEFISH: 6264 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6265 tmp &= 0xffffff00; 6266 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6267 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6268 tmp |= 0x80; 6269 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6270 break; 6271 default: 6272 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6273 tmp &= 0xffffff00; 6274 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6275 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6276 tmp |= 0x80; 6277 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6278 break; 6279 } 6280 } 6281 6282 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 6283 { 6284 struct amdgpu_device *adev = ring->adev; 6285 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6286 uint64_t hqd_gpu_addr, wb_gpu_addr; 6287 uint32_t tmp; 6288 uint32_t rb_bufsz; 6289 6290 /* set up gfx hqd wptr */ 6291 mqd->cp_gfx_hqd_wptr = 0; 6292 mqd->cp_gfx_hqd_wptr_hi = 0; 6293 6294 /* set the pointer to the MQD */ 6295 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 6296 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6297 6298 /* set up mqd control */ 6299 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6300 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6301 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6302 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6303 mqd->cp_gfx_mqd_control = tmp; 6304 6305 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6306 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6307 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6308 mqd->cp_gfx_hqd_vmid = 0; 6309 6310 /* set up default queue priority level 6311 * 0x0 = low priority, 0x1 = high priority */ 6312 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6313 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 6314 mqd->cp_gfx_hqd_queue_priority = tmp; 6315 6316 /* set up time quantum */ 6317 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6318 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6319 mqd->cp_gfx_hqd_quantum = tmp; 6320 6321 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6322 hqd_gpu_addr = ring->gpu_addr >> 8; 6323 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6324 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6325 6326 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6327 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6328 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6329 mqd->cp_gfx_hqd_rptr_addr_hi = 6330 upper_32_bits(wb_gpu_addr) & 0xffff; 6331 6332 /* set up rb_wptr_poll addr */ 6333 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6334 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6335 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6336 6337 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6338 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 6339 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6340 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6341 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6342 #ifdef __BIG_ENDIAN 6343 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6344 #endif 6345 mqd->cp_gfx_hqd_cntl = tmp; 6346 6347 /* set up cp_doorbell_control */ 6348 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6349 if (ring->use_doorbell) { 6350 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6351 DOORBELL_OFFSET, ring->doorbell_index); 6352 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6353 DOORBELL_EN, 1); 6354 } else 6355 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6356 DOORBELL_EN, 0); 6357 mqd->cp_rb_doorbell_control = tmp; 6358 6359 /* set doorbell range */ 6360 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6361 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6362 ring->wptr = 0; 6363 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6364 6365 /* active the queue */ 6366 mqd->cp_gfx_hqd_active = 1; 6367 6368 return 0; 6369 } 6370 6371 #ifdef BRING_UP_DEBUG 6372 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6373 { 6374 struct amdgpu_device *adev = ring->adev; 6375 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6376 6377 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6378 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6379 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6380 6381 /* set GFX_MQD_BASE */ 6382 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6383 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6384 6385 /* set GFX_MQD_CONTROL */ 6386 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6387 6388 /* set GFX_HQD_VMID to 0 */ 6389 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6390 6391 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6392 mqd->cp_gfx_hqd_queue_priority); 6393 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6394 6395 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6396 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6397 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6398 6399 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6400 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6401 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6402 6403 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6404 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6405 6406 /* set RB_WPTR_POLL_ADDR */ 6407 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6408 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6409 6410 /* set RB_DOORBELL_CONTROL */ 6411 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6412 6413 /* active the queue */ 6414 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6415 6416 return 0; 6417 } 6418 #endif 6419 6420 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6421 { 6422 struct amdgpu_device *adev = ring->adev; 6423 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6424 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6425 6426 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6427 memset((void *)mqd, 0, sizeof(*mqd)); 6428 mutex_lock(&adev->srbm_mutex); 6429 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6430 gfx_v10_0_gfx_mqd_init(ring); 6431 #ifdef BRING_UP_DEBUG 6432 gfx_v10_0_gfx_queue_init_register(ring); 6433 #endif 6434 nv_grbm_select(adev, 0, 0, 0, 0); 6435 mutex_unlock(&adev->srbm_mutex); 6436 if (adev->gfx.me.mqd_backup[mqd_idx]) 6437 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6438 } else if (amdgpu_in_reset(adev)) { 6439 /* reset mqd with the backup copy */ 6440 if (adev->gfx.me.mqd_backup[mqd_idx]) 6441 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6442 /* reset the ring */ 6443 ring->wptr = 0; 6444 adev->wb.wb[ring->wptr_offs] = 0; 6445 amdgpu_ring_clear_ring(ring); 6446 #ifdef BRING_UP_DEBUG 6447 mutex_lock(&adev->srbm_mutex); 6448 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6449 gfx_v10_0_gfx_queue_init_register(ring); 6450 nv_grbm_select(adev, 0, 0, 0, 0); 6451 mutex_unlock(&adev->srbm_mutex); 6452 #endif 6453 } else { 6454 amdgpu_ring_clear_ring(ring); 6455 } 6456 6457 return 0; 6458 } 6459 6460 #ifndef BRING_UP_DEBUG 6461 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6462 { 6463 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6464 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6465 int r, i; 6466 6467 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6468 return -EINVAL; 6469 6470 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6471 adev->gfx.num_gfx_rings); 6472 if (r) { 6473 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6474 return r; 6475 } 6476 6477 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6478 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6479 6480 return amdgpu_ring_test_helper(kiq_ring); 6481 } 6482 #endif 6483 6484 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6485 { 6486 int r, i; 6487 struct amdgpu_ring *ring; 6488 6489 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6490 ring = &adev->gfx.gfx_ring[i]; 6491 6492 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6493 if (unlikely(r != 0)) 6494 goto done; 6495 6496 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6497 if (!r) { 6498 r = gfx_v10_0_gfx_init_queue(ring); 6499 amdgpu_bo_kunmap(ring->mqd_obj); 6500 ring->mqd_ptr = NULL; 6501 } 6502 amdgpu_bo_unreserve(ring->mqd_obj); 6503 if (r) 6504 goto done; 6505 } 6506 #ifndef BRING_UP_DEBUG 6507 r = gfx_v10_0_kiq_enable_kgq(adev); 6508 if (r) 6509 goto done; 6510 #endif 6511 r = gfx_v10_0_cp_gfx_start(adev); 6512 if (r) 6513 goto done; 6514 6515 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6516 ring = &adev->gfx.gfx_ring[i]; 6517 ring->sched.ready = true; 6518 } 6519 done: 6520 return r; 6521 } 6522 6523 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 6524 { 6525 struct amdgpu_device *adev = ring->adev; 6526 6527 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 6528 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, 6529 ring->queue)) { 6530 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 6531 mqd->cp_hqd_queue_priority = 6532 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 6533 } 6534 } 6535 } 6536 6537 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 6538 { 6539 struct amdgpu_device *adev = ring->adev; 6540 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6541 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6542 uint32_t tmp; 6543 6544 mqd->header = 0xC0310800; 6545 mqd->compute_pipelinestat_enable = 0x00000001; 6546 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6547 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6548 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6549 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6550 mqd->compute_misc_reserved = 0x00000003; 6551 6552 eop_base_addr = ring->eop_gpu_addr >> 8; 6553 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6554 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6555 6556 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6557 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6558 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6559 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6560 6561 mqd->cp_hqd_eop_control = tmp; 6562 6563 /* enable doorbell? */ 6564 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6565 6566 if (ring->use_doorbell) { 6567 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6568 DOORBELL_OFFSET, ring->doorbell_index); 6569 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6570 DOORBELL_EN, 1); 6571 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6572 DOORBELL_SOURCE, 0); 6573 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6574 DOORBELL_HIT, 0); 6575 } else { 6576 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6577 DOORBELL_EN, 0); 6578 } 6579 6580 mqd->cp_hqd_pq_doorbell_control = tmp; 6581 6582 /* disable the queue if it's active */ 6583 ring->wptr = 0; 6584 mqd->cp_hqd_dequeue_request = 0; 6585 mqd->cp_hqd_pq_rptr = 0; 6586 mqd->cp_hqd_pq_wptr_lo = 0; 6587 mqd->cp_hqd_pq_wptr_hi = 0; 6588 6589 /* set the pointer to the MQD */ 6590 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 6591 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 6592 6593 /* set MQD vmid to 0 */ 6594 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6595 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6596 mqd->cp_mqd_control = tmp; 6597 6598 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6599 hqd_gpu_addr = ring->gpu_addr >> 8; 6600 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6601 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6602 6603 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6604 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6605 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6606 (order_base_2(ring->ring_size / 4) - 1)); 6607 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6608 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 6609 #ifdef __BIG_ENDIAN 6610 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6611 #endif 6612 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6613 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6614 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6615 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6616 mqd->cp_hqd_pq_control = tmp; 6617 6618 /* set the wb address whether it's enabled or not */ 6619 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 6620 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6621 mqd->cp_hqd_pq_rptr_report_addr_hi = 6622 upper_32_bits(wb_gpu_addr) & 0xffff; 6623 6624 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6625 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 6626 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6627 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6628 6629 tmp = 0; 6630 /* enable the doorbell if requested */ 6631 if (ring->use_doorbell) { 6632 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6633 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6634 DOORBELL_OFFSET, ring->doorbell_index); 6635 6636 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6637 DOORBELL_EN, 1); 6638 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6639 DOORBELL_SOURCE, 0); 6640 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6641 DOORBELL_HIT, 0); 6642 } 6643 6644 mqd->cp_hqd_pq_doorbell_control = tmp; 6645 6646 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6647 ring->wptr = 0; 6648 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6649 6650 /* set the vmid for the queue */ 6651 mqd->cp_hqd_vmid = 0; 6652 6653 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6654 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6655 mqd->cp_hqd_persistent_state = tmp; 6656 6657 /* set MIN_IB_AVAIL_SIZE */ 6658 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6659 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6660 mqd->cp_hqd_ib_control = tmp; 6661 6662 /* set static priority for a compute queue/ring */ 6663 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 6664 6665 /* map_queues packet doesn't need activate the queue, 6666 * so only kiq need set this field. 6667 */ 6668 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 6669 mqd->cp_hqd_active = 1; 6670 6671 return 0; 6672 } 6673 6674 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6675 { 6676 struct amdgpu_device *adev = ring->adev; 6677 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6678 int j; 6679 6680 /* inactivate the queue */ 6681 if (amdgpu_sriov_vf(adev)) 6682 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6683 6684 /* disable wptr polling */ 6685 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6686 6687 /* write the EOP addr */ 6688 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6689 mqd->cp_hqd_eop_base_addr_lo); 6690 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6691 mqd->cp_hqd_eop_base_addr_hi); 6692 6693 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6694 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6695 mqd->cp_hqd_eop_control); 6696 6697 /* enable doorbell? */ 6698 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6699 mqd->cp_hqd_pq_doorbell_control); 6700 6701 /* disable the queue if it's active */ 6702 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6703 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6704 for (j = 0; j < adev->usec_timeout; j++) { 6705 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6706 break; 6707 udelay(1); 6708 } 6709 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6710 mqd->cp_hqd_dequeue_request); 6711 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6712 mqd->cp_hqd_pq_rptr); 6713 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6714 mqd->cp_hqd_pq_wptr_lo); 6715 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6716 mqd->cp_hqd_pq_wptr_hi); 6717 } 6718 6719 /* set the pointer to the MQD */ 6720 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6721 mqd->cp_mqd_base_addr_lo); 6722 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6723 mqd->cp_mqd_base_addr_hi); 6724 6725 /* set MQD vmid to 0 */ 6726 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6727 mqd->cp_mqd_control); 6728 6729 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6730 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6731 mqd->cp_hqd_pq_base_lo); 6732 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6733 mqd->cp_hqd_pq_base_hi); 6734 6735 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6736 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6737 mqd->cp_hqd_pq_control); 6738 6739 /* set the wb address whether it's enabled or not */ 6740 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6741 mqd->cp_hqd_pq_rptr_report_addr_lo); 6742 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6743 mqd->cp_hqd_pq_rptr_report_addr_hi); 6744 6745 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6746 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6747 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6748 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6749 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6750 6751 /* enable the doorbell if requested */ 6752 if (ring->use_doorbell) { 6753 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6754 (adev->doorbell_index.kiq * 2) << 2); 6755 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6756 (adev->doorbell_index.userqueue_end * 2) << 2); 6757 } 6758 6759 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6760 mqd->cp_hqd_pq_doorbell_control); 6761 6762 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6763 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6764 mqd->cp_hqd_pq_wptr_lo); 6765 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6766 mqd->cp_hqd_pq_wptr_hi); 6767 6768 /* set the vmid for the queue */ 6769 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6770 6771 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6772 mqd->cp_hqd_persistent_state); 6773 6774 /* activate the queue */ 6775 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6776 mqd->cp_hqd_active); 6777 6778 if (ring->use_doorbell) 6779 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6780 6781 return 0; 6782 } 6783 6784 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6785 { 6786 struct amdgpu_device *adev = ring->adev; 6787 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6788 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6789 6790 gfx_v10_0_kiq_setting(ring); 6791 6792 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6793 /* reset MQD to a clean status */ 6794 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6795 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6796 6797 /* reset ring buffer */ 6798 ring->wptr = 0; 6799 amdgpu_ring_clear_ring(ring); 6800 6801 mutex_lock(&adev->srbm_mutex); 6802 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6803 gfx_v10_0_kiq_init_register(ring); 6804 nv_grbm_select(adev, 0, 0, 0, 0); 6805 mutex_unlock(&adev->srbm_mutex); 6806 } else { 6807 memset((void *)mqd, 0, sizeof(*mqd)); 6808 mutex_lock(&adev->srbm_mutex); 6809 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6810 gfx_v10_0_compute_mqd_init(ring); 6811 gfx_v10_0_kiq_init_register(ring); 6812 nv_grbm_select(adev, 0, 0, 0, 0); 6813 mutex_unlock(&adev->srbm_mutex); 6814 6815 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6816 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6817 } 6818 6819 return 0; 6820 } 6821 6822 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6823 { 6824 struct amdgpu_device *adev = ring->adev; 6825 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6826 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6827 6828 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6829 memset((void *)mqd, 0, sizeof(*mqd)); 6830 mutex_lock(&adev->srbm_mutex); 6831 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6832 gfx_v10_0_compute_mqd_init(ring); 6833 nv_grbm_select(adev, 0, 0, 0, 0); 6834 mutex_unlock(&adev->srbm_mutex); 6835 6836 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6837 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6838 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6839 /* reset MQD to a clean status */ 6840 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6841 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6842 6843 /* reset ring buffer */ 6844 ring->wptr = 0; 6845 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 6846 amdgpu_ring_clear_ring(ring); 6847 } else { 6848 amdgpu_ring_clear_ring(ring); 6849 } 6850 6851 return 0; 6852 } 6853 6854 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6855 { 6856 struct amdgpu_ring *ring; 6857 int r; 6858 6859 ring = &adev->gfx.kiq.ring; 6860 6861 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6862 if (unlikely(r != 0)) 6863 return r; 6864 6865 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6866 if (unlikely(r != 0)) 6867 return r; 6868 6869 gfx_v10_0_kiq_init_queue(ring); 6870 amdgpu_bo_kunmap(ring->mqd_obj); 6871 ring->mqd_ptr = NULL; 6872 amdgpu_bo_unreserve(ring->mqd_obj); 6873 ring->sched.ready = true; 6874 return 0; 6875 } 6876 6877 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6878 { 6879 struct amdgpu_ring *ring = NULL; 6880 int r = 0, i; 6881 6882 gfx_v10_0_cp_compute_enable(adev, true); 6883 6884 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6885 ring = &adev->gfx.compute_ring[i]; 6886 6887 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6888 if (unlikely(r != 0)) 6889 goto done; 6890 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6891 if (!r) { 6892 r = gfx_v10_0_kcq_init_queue(ring); 6893 amdgpu_bo_kunmap(ring->mqd_obj); 6894 ring->mqd_ptr = NULL; 6895 } 6896 amdgpu_bo_unreserve(ring->mqd_obj); 6897 if (r) 6898 goto done; 6899 } 6900 6901 r = amdgpu_gfx_enable_kcq(adev); 6902 done: 6903 return r; 6904 } 6905 6906 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6907 { 6908 int r, i; 6909 struct amdgpu_ring *ring; 6910 6911 if (!(adev->flags & AMD_IS_APU)) 6912 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6913 6914 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6915 /* legacy firmware loading */ 6916 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6917 if (r) 6918 return r; 6919 6920 r = gfx_v10_0_cp_compute_load_microcode(adev); 6921 if (r) 6922 return r; 6923 } 6924 6925 r = gfx_v10_0_kiq_resume(adev); 6926 if (r) 6927 return r; 6928 6929 r = gfx_v10_0_kcq_resume(adev); 6930 if (r) 6931 return r; 6932 6933 if (!amdgpu_async_gfx_ring) { 6934 r = gfx_v10_0_cp_gfx_resume(adev); 6935 if (r) 6936 return r; 6937 } else { 6938 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6939 if (r) 6940 return r; 6941 } 6942 6943 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6944 ring = &adev->gfx.gfx_ring[i]; 6945 r = amdgpu_ring_test_helper(ring); 6946 if (r) 6947 return r; 6948 } 6949 6950 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6951 ring = &adev->gfx.compute_ring[i]; 6952 r = amdgpu_ring_test_helper(ring); 6953 if (r) 6954 return r; 6955 } 6956 6957 return 0; 6958 } 6959 6960 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6961 { 6962 gfx_v10_0_cp_gfx_enable(adev, enable); 6963 gfx_v10_0_cp_compute_enable(adev, enable); 6964 } 6965 6966 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6967 { 6968 uint32_t data, pattern = 0xDEADBEEF; 6969 6970 /* check if mmVGT_ESGS_RING_SIZE_UMD 6971 * has been remapped to mmVGT_ESGS_RING_SIZE */ 6972 switch (adev->asic_type) { 6973 case CHIP_SIENNA_CICHLID: 6974 case CHIP_NAVY_FLOUNDER: 6975 case CHIP_DIMGREY_CAVEFISH: 6976 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6977 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6978 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6979 6980 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6981 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 6982 return true; 6983 } else { 6984 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6985 return false; 6986 } 6987 break; 6988 case CHIP_VANGOGH: 6989 return true; 6990 default: 6991 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6992 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 6993 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6994 6995 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 6996 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6997 return true; 6998 } else { 6999 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7000 return false; 7001 } 7002 break; 7003 } 7004 } 7005 7006 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7007 { 7008 uint32_t data; 7009 7010 /* initialize cam_index to 0 7011 * index will auto-inc after each data writting */ 7012 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7013 7014 switch (adev->asic_type) { 7015 case CHIP_SIENNA_CICHLID: 7016 case CHIP_NAVY_FLOUNDER: 7017 case CHIP_VANGOGH: 7018 case CHIP_DIMGREY_CAVEFISH: 7019 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7020 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7021 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7022 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7023 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7024 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7025 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7026 7027 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7028 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7029 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7030 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7031 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7032 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7033 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7034 7035 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7036 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7037 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7038 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7039 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7040 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7041 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7042 7043 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7044 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7045 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7046 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7047 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7048 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7049 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7050 7051 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7052 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7053 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7054 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7055 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7056 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7057 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7058 7059 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7060 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7061 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7062 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7063 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7064 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7065 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7066 7067 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7068 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7069 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7070 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7071 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7072 break; 7073 default: 7074 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7075 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7076 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7077 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7078 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7079 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7080 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7081 7082 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7083 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7084 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7085 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7086 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7087 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7088 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7089 7090 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7091 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7092 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7093 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7094 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7095 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7096 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7097 7098 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7099 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7100 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7101 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7102 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7103 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7104 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7105 7106 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7107 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7108 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7109 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7110 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7111 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7112 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7113 7114 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7115 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7116 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7117 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7118 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7119 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7120 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7121 7122 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7123 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7124 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7125 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7126 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7127 break; 7128 } 7129 7130 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7131 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7132 } 7133 7134 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7135 { 7136 uint32_t data; 7137 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7138 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7139 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7140 7141 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7142 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7143 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7144 } 7145 7146 static int gfx_v10_0_hw_init(void *handle) 7147 { 7148 int r; 7149 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7150 7151 if (!amdgpu_emu_mode) 7152 gfx_v10_0_init_golden_registers(adev); 7153 7154 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7155 /** 7156 * For gfx 10, rlc firmware loading relies on smu firmware is 7157 * loaded firstly, so in direct type, it has to load smc ucode 7158 * here before rlc. 7159 */ 7160 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) { 7161 r = smu_load_microcode(&adev->smu); 7162 if (r) 7163 return r; 7164 7165 r = smu_check_fw_status(&adev->smu); 7166 if (r) { 7167 pr_err("SMC firmware status is not correct\n"); 7168 return r; 7169 } 7170 } 7171 gfx_v10_0_disable_gpa_mode(adev); 7172 } 7173 7174 /* if GRBM CAM not remapped, set up the remapping */ 7175 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7176 gfx_v10_0_setup_grbm_cam_remapping(adev); 7177 7178 gfx_v10_0_constants_init(adev); 7179 7180 r = gfx_v10_0_rlc_resume(adev); 7181 if (r) 7182 return r; 7183 7184 /* 7185 * init golden registers and rlc resume may override some registers, 7186 * reconfig them here 7187 */ 7188 gfx_v10_0_tcp_harvest(adev); 7189 7190 r = gfx_v10_0_cp_resume(adev); 7191 if (r) 7192 return r; 7193 7194 if (adev->asic_type == CHIP_SIENNA_CICHLID) 7195 gfx_v10_3_program_pbb_mode(adev); 7196 7197 return r; 7198 } 7199 7200 #ifndef BRING_UP_DEBUG 7201 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7202 { 7203 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7204 struct amdgpu_ring *kiq_ring = &kiq->ring; 7205 int i; 7206 7207 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7208 return -EINVAL; 7209 7210 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7211 adev->gfx.num_gfx_rings)) 7212 return -ENOMEM; 7213 7214 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7215 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7216 PREEMPT_QUEUES, 0, 0); 7217 7218 return amdgpu_ring_test_helper(kiq_ring); 7219 } 7220 #endif 7221 7222 static int gfx_v10_0_hw_fini(void *handle) 7223 { 7224 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7225 int r; 7226 uint32_t tmp; 7227 7228 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7229 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7230 7231 if (!adev->in_pci_err_recovery) { 7232 #ifndef BRING_UP_DEBUG 7233 if (amdgpu_async_gfx_ring) { 7234 r = gfx_v10_0_kiq_disable_kgq(adev); 7235 if (r) 7236 DRM_ERROR("KGQ disable failed\n"); 7237 } 7238 #endif 7239 if (amdgpu_gfx_disable_kcq(adev)) 7240 DRM_ERROR("KCQ disable failed\n"); 7241 } 7242 7243 if (amdgpu_sriov_vf(adev)) { 7244 gfx_v10_0_cp_gfx_enable(adev, false); 7245 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7246 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7247 tmp &= 0xffffff00; 7248 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7249 7250 return 0; 7251 } 7252 gfx_v10_0_cp_enable(adev, false); 7253 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7254 7255 return 0; 7256 } 7257 7258 static int gfx_v10_0_suspend(void *handle) 7259 { 7260 return gfx_v10_0_hw_fini(handle); 7261 } 7262 7263 static int gfx_v10_0_resume(void *handle) 7264 { 7265 return gfx_v10_0_hw_init(handle); 7266 } 7267 7268 static bool gfx_v10_0_is_idle(void *handle) 7269 { 7270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7271 7272 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7273 GRBM_STATUS, GUI_ACTIVE)) 7274 return false; 7275 else 7276 return true; 7277 } 7278 7279 static int gfx_v10_0_wait_for_idle(void *handle) 7280 { 7281 unsigned i; 7282 u32 tmp; 7283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7284 7285 for (i = 0; i < adev->usec_timeout; i++) { 7286 /* read MC_STATUS */ 7287 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7288 GRBM_STATUS__GUI_ACTIVE_MASK; 7289 7290 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7291 return 0; 7292 udelay(1); 7293 } 7294 return -ETIMEDOUT; 7295 } 7296 7297 static int gfx_v10_0_soft_reset(void *handle) 7298 { 7299 u32 grbm_soft_reset = 0; 7300 u32 tmp; 7301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7302 7303 /* GRBM_STATUS */ 7304 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7305 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7306 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7307 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7308 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7309 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7310 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7311 GRBM_SOFT_RESET, SOFT_RESET_CP, 7312 1); 7313 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7314 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7315 1); 7316 } 7317 7318 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7319 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7320 GRBM_SOFT_RESET, SOFT_RESET_CP, 7321 1); 7322 } 7323 7324 /* GRBM_STATUS2 */ 7325 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7326 switch (adev->asic_type) { 7327 case CHIP_SIENNA_CICHLID: 7328 case CHIP_NAVY_FLOUNDER: 7329 case CHIP_VANGOGH: 7330 case CHIP_DIMGREY_CAVEFISH: 7331 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7332 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7333 GRBM_SOFT_RESET, 7334 SOFT_RESET_RLC, 7335 1); 7336 break; 7337 default: 7338 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7339 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7340 GRBM_SOFT_RESET, 7341 SOFT_RESET_RLC, 7342 1); 7343 break; 7344 } 7345 7346 if (grbm_soft_reset) { 7347 /* stop the rlc */ 7348 gfx_v10_0_rlc_stop(adev); 7349 7350 /* Disable GFX parsing/prefetching */ 7351 gfx_v10_0_cp_gfx_enable(adev, false); 7352 7353 /* Disable MEC parsing/prefetching */ 7354 gfx_v10_0_cp_compute_enable(adev, false); 7355 7356 if (grbm_soft_reset) { 7357 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7358 tmp |= grbm_soft_reset; 7359 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7360 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7361 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7362 7363 udelay(50); 7364 7365 tmp &= ~grbm_soft_reset; 7366 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7367 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7368 } 7369 7370 /* Wait a little for things to settle down */ 7371 udelay(50); 7372 } 7373 return 0; 7374 } 7375 7376 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7377 { 7378 uint64_t clock; 7379 7380 amdgpu_gfx_off_ctrl(adev, false); 7381 mutex_lock(&adev->gfx.gpu_clock_mutex); 7382 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 7383 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 7384 mutex_unlock(&adev->gfx.gpu_clock_mutex); 7385 amdgpu_gfx_off_ctrl(adev, true); 7386 return clock; 7387 } 7388 7389 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7390 uint32_t vmid, 7391 uint32_t gds_base, uint32_t gds_size, 7392 uint32_t gws_base, uint32_t gws_size, 7393 uint32_t oa_base, uint32_t oa_size) 7394 { 7395 struct amdgpu_device *adev = ring->adev; 7396 7397 /* GDS Base */ 7398 gfx_v10_0_write_data_to_reg(ring, 0, false, 7399 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7400 gds_base); 7401 7402 /* GDS Size */ 7403 gfx_v10_0_write_data_to_reg(ring, 0, false, 7404 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7405 gds_size); 7406 7407 /* GWS */ 7408 gfx_v10_0_write_data_to_reg(ring, 0, false, 7409 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7410 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7411 7412 /* OA */ 7413 gfx_v10_0_write_data_to_reg(ring, 0, false, 7414 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7415 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7416 } 7417 7418 static int gfx_v10_0_early_init(void *handle) 7419 { 7420 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7421 7422 switch (adev->asic_type) { 7423 case CHIP_NAVI10: 7424 case CHIP_NAVI14: 7425 case CHIP_NAVI12: 7426 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7427 break; 7428 case CHIP_SIENNA_CICHLID: 7429 case CHIP_NAVY_FLOUNDER: 7430 case CHIP_VANGOGH: 7431 case CHIP_DIMGREY_CAVEFISH: 7432 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7433 break; 7434 default: 7435 break; 7436 } 7437 7438 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7439 AMDGPU_MAX_COMPUTE_RINGS); 7440 7441 gfx_v10_0_set_kiq_pm4_funcs(adev); 7442 gfx_v10_0_set_ring_funcs(adev); 7443 gfx_v10_0_set_irq_funcs(adev); 7444 gfx_v10_0_set_gds_init(adev); 7445 gfx_v10_0_set_rlc_funcs(adev); 7446 7447 return 0; 7448 } 7449 7450 static int gfx_v10_0_late_init(void *handle) 7451 { 7452 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7453 int r; 7454 7455 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7456 if (r) 7457 return r; 7458 7459 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7460 if (r) 7461 return r; 7462 7463 return 0; 7464 } 7465 7466 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7467 { 7468 uint32_t rlc_cntl; 7469 7470 /* if RLC is not enabled, do nothing */ 7471 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7472 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7473 } 7474 7475 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7476 { 7477 uint32_t data; 7478 unsigned i; 7479 7480 data = RLC_SAFE_MODE__CMD_MASK; 7481 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7482 7483 switch (adev->asic_type) { 7484 case CHIP_SIENNA_CICHLID: 7485 case CHIP_NAVY_FLOUNDER: 7486 case CHIP_VANGOGH: 7487 case CHIP_DIMGREY_CAVEFISH: 7488 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7489 7490 /* wait for RLC_SAFE_MODE */ 7491 for (i = 0; i < adev->usec_timeout; i++) { 7492 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7493 RLC_SAFE_MODE, CMD)) 7494 break; 7495 udelay(1); 7496 } 7497 break; 7498 default: 7499 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7500 7501 /* wait for RLC_SAFE_MODE */ 7502 for (i = 0; i < adev->usec_timeout; i++) { 7503 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7504 RLC_SAFE_MODE, CMD)) 7505 break; 7506 udelay(1); 7507 } 7508 break; 7509 } 7510 } 7511 7512 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7513 { 7514 uint32_t data; 7515 7516 data = RLC_SAFE_MODE__CMD_MASK; 7517 switch (adev->asic_type) { 7518 case CHIP_SIENNA_CICHLID: 7519 case CHIP_NAVY_FLOUNDER: 7520 case CHIP_VANGOGH: 7521 case CHIP_DIMGREY_CAVEFISH: 7522 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7523 break; 7524 default: 7525 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7526 break; 7527 } 7528 } 7529 7530 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7531 bool enable) 7532 { 7533 uint32_t data, def; 7534 7535 /* It is disabled by HW by default */ 7536 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7537 /* 0 - Disable some blocks' MGCG */ 7538 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7539 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7540 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7541 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7542 7543 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7544 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7545 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7546 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7547 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7548 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7549 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7550 7551 if (def != data) 7552 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7553 7554 /* MGLS is a global flag to control all MGLS in GFX */ 7555 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7556 /* 2 - RLC memory Light sleep */ 7557 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7558 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7559 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7560 if (def != data) 7561 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7562 } 7563 /* 3 - CP memory Light sleep */ 7564 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7565 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7566 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7567 if (def != data) 7568 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7569 } 7570 } 7571 } else { 7572 /* 1 - MGCG_OVERRIDE */ 7573 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7574 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7575 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7576 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7577 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 7578 if (def != data) 7579 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7580 7581 /* 2 - disable MGLS in CP */ 7582 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7583 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7584 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7585 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7586 } 7587 7588 /* 3 - disable MGLS in RLC */ 7589 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7590 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7591 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7592 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7593 } 7594 7595 } 7596 } 7597 7598 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7599 bool enable) 7600 { 7601 uint32_t data, def; 7602 7603 /* Enable 3D CGCG/CGLS */ 7604 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 7605 /* write cmd to clear cgcg/cgls ov */ 7606 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7607 /* unset CGCG override */ 7608 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7609 /* update CGCG and CGLS override bits */ 7610 if (def != data) 7611 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7612 /* enable 3Dcgcg FSM(0x0000363f) */ 7613 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7614 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7615 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7616 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7617 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7618 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7619 if (def != data) 7620 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7621 7622 /* set IDLE_POLL_COUNT(0x00900100) */ 7623 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7624 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7625 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7626 if (def != data) 7627 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7628 } else { 7629 /* Disable CGCG/CGLS */ 7630 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7631 /* disable cgcg, cgls should be disabled */ 7632 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 7633 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 7634 /* disable cgcg and cgls in FSM */ 7635 if (def != data) 7636 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7637 } 7638 } 7639 7640 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7641 bool enable) 7642 { 7643 uint32_t def, data; 7644 7645 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 7646 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7647 /* unset CGCG override */ 7648 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7649 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7650 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7651 else 7652 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7653 /* update CGCG and CGLS override bits */ 7654 if (def != data) 7655 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7656 7657 /* enable cgcg FSM(0x0000363F) */ 7658 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7659 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7660 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7661 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7662 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7663 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7664 if (def != data) 7665 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7666 7667 /* set IDLE_POLL_COUNT(0x00900100) */ 7668 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7669 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7670 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7671 if (def != data) 7672 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7673 } else { 7674 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7675 /* reset CGCG/CGLS bits */ 7676 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 7677 /* disable cgcg and cgls in FSM */ 7678 if (def != data) 7679 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7680 } 7681 } 7682 7683 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7684 bool enable) 7685 { 7686 uint32_t def, data; 7687 7688 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) { 7689 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7690 /* unset FGCG override */ 7691 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7692 /* update FGCG override bits */ 7693 if (def != data) 7694 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7695 7696 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7697 /* unset RLC SRAM CLK GATER override */ 7698 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7699 /* update RLC SRAM CLK GATER override bits */ 7700 if (def != data) 7701 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7702 } else { 7703 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7704 /* reset FGCG bits */ 7705 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7706 /* disable FGCG*/ 7707 if (def != data) 7708 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7709 7710 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7711 /* reset RLC SRAM CLK GATER bits */ 7712 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7713 /* disable RLC SRAM CLK*/ 7714 if (def != data) 7715 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7716 } 7717 } 7718 7719 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7720 bool enable) 7721 { 7722 amdgpu_gfx_rlc_enter_safe_mode(adev); 7723 7724 if (enable) { 7725 /* enable FGCG firstly*/ 7726 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7727 /* CGCG/CGLS should be enabled after MGCG/MGLS 7728 * === MGCG + MGLS === 7729 */ 7730 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7731 /* === CGCG /CGLS for GFX 3D Only === */ 7732 gfx_v10_0_update_3d_clock_gating(adev, enable); 7733 /* === CGCG + CGLS === */ 7734 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7735 } else { 7736 /* CGCG/CGLS should be disabled before MGCG/MGLS 7737 * === CGCG + CGLS === 7738 */ 7739 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7740 /* === CGCG /CGLS for GFX 3D Only === */ 7741 gfx_v10_0_update_3d_clock_gating(adev, enable); 7742 /* === MGCG + MGLS === */ 7743 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7744 /* disable fgcg at last*/ 7745 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7746 } 7747 7748 if (adev->cg_flags & 7749 (AMD_CG_SUPPORT_GFX_MGCG | 7750 AMD_CG_SUPPORT_GFX_CGLS | 7751 AMD_CG_SUPPORT_GFX_CGCG | 7752 AMD_CG_SUPPORT_GFX_3D_CGCG | 7753 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7754 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7755 7756 amdgpu_gfx_rlc_exit_safe_mode(adev); 7757 7758 return 0; 7759 } 7760 7761 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 7762 { 7763 u32 reg, data; 7764 7765 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7766 if (amdgpu_sriov_is_pp_one_vf(adev)) 7767 data = RREG32_NO_KIQ(reg); 7768 else 7769 data = RREG32(reg); 7770 7771 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7772 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7773 7774 if (amdgpu_sriov_is_pp_one_vf(adev)) 7775 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7776 else 7777 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7778 } 7779 7780 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7781 uint32_t offset, 7782 struct soc15_reg_rlcg *entries, int arr_size) 7783 { 7784 int i; 7785 uint32_t reg; 7786 7787 if (!entries) 7788 return false; 7789 7790 for (i = 0; i < arr_size; i++) { 7791 const struct soc15_reg_rlcg *entry; 7792 7793 entry = &entries[i]; 7794 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7795 if (offset == reg) 7796 return true; 7797 } 7798 7799 return false; 7800 } 7801 7802 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7803 { 7804 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7805 } 7806 7807 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7808 { 7809 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7810 7811 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7812 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7813 else 7814 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7815 7816 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7817 } 7818 7819 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7820 { 7821 amdgpu_gfx_rlc_enter_safe_mode(adev); 7822 7823 gfx_v10_cntl_power_gating(adev, enable); 7824 7825 amdgpu_gfx_rlc_exit_safe_mode(adev); 7826 } 7827 7828 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 7829 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7830 .set_safe_mode = gfx_v10_0_set_safe_mode, 7831 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7832 .init = gfx_v10_0_rlc_init, 7833 .get_csb_size = gfx_v10_0_get_csb_size, 7834 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7835 .resume = gfx_v10_0_rlc_resume, 7836 .stop = gfx_v10_0_rlc_stop, 7837 .reset = gfx_v10_0_rlc_reset, 7838 .start = gfx_v10_0_rlc_start, 7839 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7840 }; 7841 7842 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 7843 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7844 .set_safe_mode = gfx_v10_0_set_safe_mode, 7845 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 7846 .init = gfx_v10_0_rlc_init, 7847 .get_csb_size = gfx_v10_0_get_csb_size, 7848 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 7849 .resume = gfx_v10_0_rlc_resume, 7850 .stop = gfx_v10_0_rlc_stop, 7851 .reset = gfx_v10_0_rlc_reset, 7852 .start = gfx_v10_0_rlc_start, 7853 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 7854 .rlcg_wreg = gfx_v10_rlcg_wreg, 7855 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 7856 }; 7857 7858 static int gfx_v10_0_set_powergating_state(void *handle, 7859 enum amd_powergating_state state) 7860 { 7861 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7862 bool enable = (state == AMD_PG_STATE_GATE); 7863 7864 if (amdgpu_sriov_vf(adev)) 7865 return 0; 7866 7867 switch (adev->asic_type) { 7868 case CHIP_NAVI10: 7869 case CHIP_NAVI14: 7870 case CHIP_NAVI12: 7871 case CHIP_SIENNA_CICHLID: 7872 case CHIP_NAVY_FLOUNDER: 7873 case CHIP_DIMGREY_CAVEFISH: 7874 amdgpu_gfx_off_ctrl(adev, enable); 7875 break; 7876 case CHIP_VANGOGH: 7877 gfx_v10_cntl_pg(adev, enable); 7878 break; 7879 default: 7880 break; 7881 } 7882 return 0; 7883 } 7884 7885 static int gfx_v10_0_set_clockgating_state(void *handle, 7886 enum amd_clockgating_state state) 7887 { 7888 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7889 7890 if (amdgpu_sriov_vf(adev)) 7891 return 0; 7892 7893 switch (adev->asic_type) { 7894 case CHIP_NAVI10: 7895 case CHIP_NAVI14: 7896 case CHIP_NAVI12: 7897 case CHIP_SIENNA_CICHLID: 7898 case CHIP_NAVY_FLOUNDER: 7899 case CHIP_VANGOGH: 7900 case CHIP_DIMGREY_CAVEFISH: 7901 gfx_v10_0_update_gfx_clock_gating(adev, 7902 state == AMD_CG_STATE_GATE); 7903 break; 7904 default: 7905 break; 7906 } 7907 return 0; 7908 } 7909 7910 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 7911 { 7912 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7913 int data; 7914 7915 /* AMD_CG_SUPPORT_GFX_FGCG */ 7916 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7917 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 7918 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 7919 7920 /* AMD_CG_SUPPORT_GFX_MGCG */ 7921 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 7922 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 7923 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 7924 7925 /* AMD_CG_SUPPORT_GFX_CGCG */ 7926 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 7927 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 7928 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 7929 7930 /* AMD_CG_SUPPORT_GFX_CGLS */ 7931 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 7932 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 7933 7934 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 7935 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 7936 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 7937 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 7938 7939 /* AMD_CG_SUPPORT_GFX_CP_LS */ 7940 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 7941 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 7942 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 7943 7944 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 7945 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 7946 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 7947 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 7948 7949 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 7950 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 7951 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 7952 } 7953 7954 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 7955 { 7956 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 7957 } 7958 7959 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 7960 { 7961 struct amdgpu_device *adev = ring->adev; 7962 u64 wptr; 7963 7964 /* XXX check if swapping is necessary on BE */ 7965 if (ring->use_doorbell) { 7966 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 7967 } else { 7968 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 7969 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 7970 } 7971 7972 return wptr; 7973 } 7974 7975 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 7976 { 7977 struct amdgpu_device *adev = ring->adev; 7978 7979 if (ring->use_doorbell) { 7980 /* XXX check if swapping is necessary on BE */ 7981 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 7982 WDOORBELL64(ring->doorbell_index, ring->wptr); 7983 } else { 7984 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 7985 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 7986 } 7987 } 7988 7989 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 7990 { 7991 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 7992 } 7993 7994 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 7995 { 7996 u64 wptr; 7997 7998 /* XXX check if swapping is necessary on BE */ 7999 if (ring->use_doorbell) 8000 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 8001 else 8002 BUG(); 8003 return wptr; 8004 } 8005 8006 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8007 { 8008 struct amdgpu_device *adev = ring->adev; 8009 8010 /* XXX check if swapping is necessary on BE */ 8011 if (ring->use_doorbell) { 8012 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 8013 WDOORBELL64(ring->doorbell_index, ring->wptr); 8014 } else { 8015 BUG(); /* only DOORBELL method supported on gfx10 now */ 8016 } 8017 } 8018 8019 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8020 { 8021 struct amdgpu_device *adev = ring->adev; 8022 u32 ref_and_mask, reg_mem_engine; 8023 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8024 8025 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8026 switch (ring->me) { 8027 case 1: 8028 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8029 break; 8030 case 2: 8031 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8032 break; 8033 default: 8034 return; 8035 } 8036 reg_mem_engine = 0; 8037 } else { 8038 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8039 reg_mem_engine = 1; /* pfp */ 8040 } 8041 8042 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8043 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8044 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8045 ref_and_mask, ref_and_mask, 0x20); 8046 } 8047 8048 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8049 struct amdgpu_job *job, 8050 struct amdgpu_ib *ib, 8051 uint32_t flags) 8052 { 8053 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8054 u32 header, control = 0; 8055 8056 if (ib->flags & AMDGPU_IB_FLAG_CE) 8057 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8058 else 8059 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8060 8061 control |= ib->length_dw | (vmid << 24); 8062 8063 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8064 control |= INDIRECT_BUFFER_PRE_ENB(1); 8065 8066 if (flags & AMDGPU_IB_PREEMPTED) 8067 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8068 8069 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8070 gfx_v10_0_ring_emit_de_meta(ring, 8071 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8072 } 8073 8074 amdgpu_ring_write(ring, header); 8075 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8076 amdgpu_ring_write(ring, 8077 #ifdef __BIG_ENDIAN 8078 (2 << 0) | 8079 #endif 8080 lower_32_bits(ib->gpu_addr)); 8081 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8082 amdgpu_ring_write(ring, control); 8083 } 8084 8085 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8086 struct amdgpu_job *job, 8087 struct amdgpu_ib *ib, 8088 uint32_t flags) 8089 { 8090 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8091 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8092 8093 /* Currently, there is a high possibility to get wave ID mismatch 8094 * between ME and GDS, leading to a hw deadlock, because ME generates 8095 * different wave IDs than the GDS expects. This situation happens 8096 * randomly when at least 5 compute pipes use GDS ordered append. 8097 * The wave IDs generated by ME are also wrong after suspend/resume. 8098 * Those are probably bugs somewhere else in the kernel driver. 8099 * 8100 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8101 * GDS to 0 for this ring (me/pipe). 8102 */ 8103 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8104 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8105 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8106 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8107 } 8108 8109 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8110 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8111 amdgpu_ring_write(ring, 8112 #ifdef __BIG_ENDIAN 8113 (2 << 0) | 8114 #endif 8115 lower_32_bits(ib->gpu_addr)); 8116 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8117 amdgpu_ring_write(ring, control); 8118 } 8119 8120 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8121 u64 seq, unsigned flags) 8122 { 8123 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8124 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8125 8126 /* RELEASE_MEM - flush caches, send int */ 8127 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8128 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8129 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8130 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8131 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8132 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8133 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8134 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8135 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8136 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8137 8138 /* 8139 * the address should be Qword aligned if 64bit write, Dword 8140 * aligned if only send 32bit data low (discard data high) 8141 */ 8142 if (write64bit) 8143 BUG_ON(addr & 0x7); 8144 else 8145 BUG_ON(addr & 0x3); 8146 amdgpu_ring_write(ring, lower_32_bits(addr)); 8147 amdgpu_ring_write(ring, upper_32_bits(addr)); 8148 amdgpu_ring_write(ring, lower_32_bits(seq)); 8149 amdgpu_ring_write(ring, upper_32_bits(seq)); 8150 amdgpu_ring_write(ring, 0); 8151 } 8152 8153 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8154 { 8155 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8156 uint32_t seq = ring->fence_drv.sync_seq; 8157 uint64_t addr = ring->fence_drv.gpu_addr; 8158 8159 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8160 upper_32_bits(addr), seq, 0xffffffff, 4); 8161 } 8162 8163 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8164 unsigned vmid, uint64_t pd_addr) 8165 { 8166 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8167 8168 /* compute doesn't have PFP */ 8169 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8170 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8171 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8172 amdgpu_ring_write(ring, 0x0); 8173 } 8174 } 8175 8176 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8177 u64 seq, unsigned int flags) 8178 { 8179 struct amdgpu_device *adev = ring->adev; 8180 8181 /* we only allocate 32bit for each seq wb address */ 8182 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8183 8184 /* write fence seq to the "addr" */ 8185 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8186 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8187 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8188 amdgpu_ring_write(ring, lower_32_bits(addr)); 8189 amdgpu_ring_write(ring, upper_32_bits(addr)); 8190 amdgpu_ring_write(ring, lower_32_bits(seq)); 8191 8192 if (flags & AMDGPU_FENCE_FLAG_INT) { 8193 /* set register to trigger INT */ 8194 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8195 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8196 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8197 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8198 amdgpu_ring_write(ring, 0); 8199 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8200 } 8201 } 8202 8203 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8204 { 8205 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8206 amdgpu_ring_write(ring, 0); 8207 } 8208 8209 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8210 uint32_t flags) 8211 { 8212 uint32_t dw2 = 0; 8213 8214 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 8215 gfx_v10_0_ring_emit_ce_meta(ring, 8216 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8217 8218 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8219 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8220 /* set load_global_config & load_global_uconfig */ 8221 dw2 |= 0x8001; 8222 /* set load_cs_sh_regs */ 8223 dw2 |= 0x01000000; 8224 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8225 dw2 |= 0x10002; 8226 8227 /* set load_ce_ram if preamble presented */ 8228 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8229 dw2 |= 0x10000000; 8230 } else { 8231 /* still load_ce_ram if this is the first time preamble presented 8232 * although there is no context switch happens. 8233 */ 8234 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8235 dw2 |= 0x10000000; 8236 } 8237 8238 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8239 amdgpu_ring_write(ring, dw2); 8240 amdgpu_ring_write(ring, 0); 8241 } 8242 8243 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8244 { 8245 unsigned ret; 8246 8247 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8248 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8249 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8250 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8251 ret = ring->wptr & ring->buf_mask; 8252 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8253 8254 return ret; 8255 } 8256 8257 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8258 { 8259 unsigned cur; 8260 BUG_ON(offset > ring->buf_mask); 8261 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8262 8263 cur = (ring->wptr - 1) & ring->buf_mask; 8264 if (likely(cur > offset)) 8265 ring->ring[offset] = cur - offset; 8266 else 8267 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8268 } 8269 8270 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8271 { 8272 int i, r = 0; 8273 struct amdgpu_device *adev = ring->adev; 8274 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8275 struct amdgpu_ring *kiq_ring = &kiq->ring; 8276 unsigned long flags; 8277 8278 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8279 return -EINVAL; 8280 8281 spin_lock_irqsave(&kiq->ring_lock, flags); 8282 8283 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8284 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8285 return -ENOMEM; 8286 } 8287 8288 /* assert preemption condition */ 8289 amdgpu_ring_set_preempt_cond_exec(ring, false); 8290 8291 /* assert IB preemption, emit the trailing fence */ 8292 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8293 ring->trail_fence_gpu_addr, 8294 ++ring->trail_seq); 8295 amdgpu_ring_commit(kiq_ring); 8296 8297 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8298 8299 /* poll the trailing fence */ 8300 for (i = 0; i < adev->usec_timeout; i++) { 8301 if (ring->trail_seq == 8302 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8303 break; 8304 udelay(1); 8305 } 8306 8307 if (i >= adev->usec_timeout) { 8308 r = -EINVAL; 8309 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8310 } 8311 8312 /* deassert preemption condition */ 8313 amdgpu_ring_set_preempt_cond_exec(ring, true); 8314 return r; 8315 } 8316 8317 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8318 { 8319 struct amdgpu_device *adev = ring->adev; 8320 struct v10_ce_ib_state ce_payload = {0}; 8321 uint64_t csa_addr; 8322 int cnt; 8323 8324 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8325 csa_addr = amdgpu_csa_vaddr(ring->adev); 8326 8327 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8328 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8329 WRITE_DATA_DST_SEL(8) | 8330 WR_CONFIRM) | 8331 WRITE_DATA_CACHE_POLICY(0)); 8332 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8333 offsetof(struct v10_gfx_meta_data, ce_payload))); 8334 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8335 offsetof(struct v10_gfx_meta_data, ce_payload))); 8336 8337 if (resume) 8338 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8339 offsetof(struct v10_gfx_meta_data, 8340 ce_payload), 8341 sizeof(ce_payload) >> 2); 8342 else 8343 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8344 sizeof(ce_payload) >> 2); 8345 } 8346 8347 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8348 { 8349 struct amdgpu_device *adev = ring->adev; 8350 struct v10_de_ib_state de_payload = {0}; 8351 uint64_t csa_addr, gds_addr; 8352 int cnt; 8353 8354 csa_addr = amdgpu_csa_vaddr(ring->adev); 8355 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 8356 PAGE_SIZE); 8357 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8358 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8359 8360 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8361 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8362 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8363 WRITE_DATA_DST_SEL(8) | 8364 WR_CONFIRM) | 8365 WRITE_DATA_CACHE_POLICY(0)); 8366 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 8367 offsetof(struct v10_gfx_meta_data, de_payload))); 8368 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 8369 offsetof(struct v10_gfx_meta_data, de_payload))); 8370 8371 if (resume) 8372 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 8373 offsetof(struct v10_gfx_meta_data, 8374 de_payload), 8375 sizeof(de_payload) >> 2); 8376 else 8377 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8378 sizeof(de_payload) >> 2); 8379 } 8380 8381 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8382 bool secure) 8383 { 8384 uint32_t v = secure ? FRAME_TMZ : 0; 8385 8386 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8387 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8388 } 8389 8390 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8391 uint32_t reg_val_offs) 8392 { 8393 struct amdgpu_device *adev = ring->adev; 8394 8395 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8396 amdgpu_ring_write(ring, 0 | /* src: register*/ 8397 (5 << 8) | /* dst: memory */ 8398 (1 << 20)); /* write confirm */ 8399 amdgpu_ring_write(ring, reg); 8400 amdgpu_ring_write(ring, 0); 8401 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8402 reg_val_offs * 4)); 8403 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8404 reg_val_offs * 4)); 8405 } 8406 8407 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8408 uint32_t val) 8409 { 8410 uint32_t cmd = 0; 8411 8412 switch (ring->funcs->type) { 8413 case AMDGPU_RING_TYPE_GFX: 8414 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8415 break; 8416 case AMDGPU_RING_TYPE_KIQ: 8417 cmd = (1 << 16); /* no inc addr */ 8418 break; 8419 default: 8420 cmd = WR_CONFIRM; 8421 break; 8422 } 8423 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8424 amdgpu_ring_write(ring, cmd); 8425 amdgpu_ring_write(ring, reg); 8426 amdgpu_ring_write(ring, 0); 8427 amdgpu_ring_write(ring, val); 8428 } 8429 8430 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8431 uint32_t val, uint32_t mask) 8432 { 8433 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8434 } 8435 8436 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8437 uint32_t reg0, uint32_t reg1, 8438 uint32_t ref, uint32_t mask) 8439 { 8440 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8441 struct amdgpu_device *adev = ring->adev; 8442 bool fw_version_ok = false; 8443 8444 fw_version_ok = adev->gfx.cp_fw_write_wait; 8445 8446 if (fw_version_ok) 8447 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8448 ref, mask, 0x20); 8449 else 8450 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8451 ref, mask); 8452 } 8453 8454 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8455 unsigned vmid) 8456 { 8457 struct amdgpu_device *adev = ring->adev; 8458 uint32_t value = 0; 8459 8460 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8461 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8462 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8463 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8464 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8465 } 8466 8467 static void 8468 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8469 uint32_t me, uint32_t pipe, 8470 enum amdgpu_interrupt_state state) 8471 { 8472 uint32_t cp_int_cntl, cp_int_cntl_reg; 8473 8474 if (!me) { 8475 switch (pipe) { 8476 case 0: 8477 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8478 break; 8479 case 1: 8480 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8481 break; 8482 default: 8483 DRM_DEBUG("invalid pipe %d\n", pipe); 8484 return; 8485 } 8486 } else { 8487 DRM_DEBUG("invalid me %d\n", me); 8488 return; 8489 } 8490 8491 switch (state) { 8492 case AMDGPU_IRQ_STATE_DISABLE: 8493 cp_int_cntl = RREG32(cp_int_cntl_reg); 8494 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8495 TIME_STAMP_INT_ENABLE, 0); 8496 WREG32(cp_int_cntl_reg, cp_int_cntl); 8497 break; 8498 case AMDGPU_IRQ_STATE_ENABLE: 8499 cp_int_cntl = RREG32(cp_int_cntl_reg); 8500 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8501 TIME_STAMP_INT_ENABLE, 1); 8502 WREG32(cp_int_cntl_reg, cp_int_cntl); 8503 break; 8504 default: 8505 break; 8506 } 8507 } 8508 8509 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8510 int me, int pipe, 8511 enum amdgpu_interrupt_state state) 8512 { 8513 u32 mec_int_cntl, mec_int_cntl_reg; 8514 8515 /* 8516 * amdgpu controls only the first MEC. That's why this function only 8517 * handles the setting of interrupts for this specific MEC. All other 8518 * pipes' interrupts are set by amdkfd. 8519 */ 8520 8521 if (me == 1) { 8522 switch (pipe) { 8523 case 0: 8524 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8525 break; 8526 case 1: 8527 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8528 break; 8529 case 2: 8530 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8531 break; 8532 case 3: 8533 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8534 break; 8535 default: 8536 DRM_DEBUG("invalid pipe %d\n", pipe); 8537 return; 8538 } 8539 } else { 8540 DRM_DEBUG("invalid me %d\n", me); 8541 return; 8542 } 8543 8544 switch (state) { 8545 case AMDGPU_IRQ_STATE_DISABLE: 8546 mec_int_cntl = RREG32(mec_int_cntl_reg); 8547 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8548 TIME_STAMP_INT_ENABLE, 0); 8549 WREG32(mec_int_cntl_reg, mec_int_cntl); 8550 break; 8551 case AMDGPU_IRQ_STATE_ENABLE: 8552 mec_int_cntl = RREG32(mec_int_cntl_reg); 8553 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8554 TIME_STAMP_INT_ENABLE, 1); 8555 WREG32(mec_int_cntl_reg, mec_int_cntl); 8556 break; 8557 default: 8558 break; 8559 } 8560 } 8561 8562 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8563 struct amdgpu_irq_src *src, 8564 unsigned type, 8565 enum amdgpu_interrupt_state state) 8566 { 8567 switch (type) { 8568 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8569 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8570 break; 8571 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8572 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8573 break; 8574 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8575 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8576 break; 8577 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8578 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8579 break; 8580 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8581 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8582 break; 8583 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8584 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8585 break; 8586 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8587 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8588 break; 8589 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8590 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8591 break; 8592 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8593 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8594 break; 8595 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8596 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8597 break; 8598 default: 8599 break; 8600 } 8601 return 0; 8602 } 8603 8604 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8605 struct amdgpu_irq_src *source, 8606 struct amdgpu_iv_entry *entry) 8607 { 8608 int i; 8609 u8 me_id, pipe_id, queue_id; 8610 struct amdgpu_ring *ring; 8611 8612 DRM_DEBUG("IH: CP EOP\n"); 8613 me_id = (entry->ring_id & 0x0c) >> 2; 8614 pipe_id = (entry->ring_id & 0x03) >> 0; 8615 queue_id = (entry->ring_id & 0x70) >> 4; 8616 8617 switch (me_id) { 8618 case 0: 8619 if (pipe_id == 0) 8620 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8621 else 8622 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8623 break; 8624 case 1: 8625 case 2: 8626 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8627 ring = &adev->gfx.compute_ring[i]; 8628 /* Per-queue interrupt is supported for MEC starting from VI. 8629 * The interrupt can only be enabled/disabled per pipe instead of per queue. 8630 */ 8631 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 8632 amdgpu_fence_process(ring); 8633 } 8634 break; 8635 } 8636 return 0; 8637 } 8638 8639 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8640 struct amdgpu_irq_src *source, 8641 unsigned type, 8642 enum amdgpu_interrupt_state state) 8643 { 8644 switch (state) { 8645 case AMDGPU_IRQ_STATE_DISABLE: 8646 case AMDGPU_IRQ_STATE_ENABLE: 8647 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8648 PRIV_REG_INT_ENABLE, 8649 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8650 break; 8651 default: 8652 break; 8653 } 8654 8655 return 0; 8656 } 8657 8658 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8659 struct amdgpu_irq_src *source, 8660 unsigned type, 8661 enum amdgpu_interrupt_state state) 8662 { 8663 switch (state) { 8664 case AMDGPU_IRQ_STATE_DISABLE: 8665 case AMDGPU_IRQ_STATE_ENABLE: 8666 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8667 PRIV_INSTR_INT_ENABLE, 8668 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8669 break; 8670 default: 8671 break; 8672 } 8673 8674 return 0; 8675 } 8676 8677 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8678 struct amdgpu_iv_entry *entry) 8679 { 8680 u8 me_id, pipe_id, queue_id; 8681 struct amdgpu_ring *ring; 8682 int i; 8683 8684 me_id = (entry->ring_id & 0x0c) >> 2; 8685 pipe_id = (entry->ring_id & 0x03) >> 0; 8686 queue_id = (entry->ring_id & 0x70) >> 4; 8687 8688 switch (me_id) { 8689 case 0: 8690 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 8691 ring = &adev->gfx.gfx_ring[i]; 8692 /* we only enabled 1 gfx queue per pipe for now */ 8693 if (ring->me == me_id && ring->pipe == pipe_id) 8694 drm_sched_fault(&ring->sched); 8695 } 8696 break; 8697 case 1: 8698 case 2: 8699 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8700 ring = &adev->gfx.compute_ring[i]; 8701 if (ring->me == me_id && ring->pipe == pipe_id && 8702 ring->queue == queue_id) 8703 drm_sched_fault(&ring->sched); 8704 } 8705 break; 8706 default: 8707 BUG(); 8708 } 8709 } 8710 8711 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 8712 struct amdgpu_irq_src *source, 8713 struct amdgpu_iv_entry *entry) 8714 { 8715 DRM_ERROR("Illegal register access in command stream\n"); 8716 gfx_v10_0_handle_priv_fault(adev, entry); 8717 return 0; 8718 } 8719 8720 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 8721 struct amdgpu_irq_src *source, 8722 struct amdgpu_iv_entry *entry) 8723 { 8724 DRM_ERROR("Illegal instruction in command stream\n"); 8725 gfx_v10_0_handle_priv_fault(adev, entry); 8726 return 0; 8727 } 8728 8729 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 8730 struct amdgpu_irq_src *src, 8731 unsigned int type, 8732 enum amdgpu_interrupt_state state) 8733 { 8734 uint32_t tmp, target; 8735 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8736 8737 if (ring->me == 1) 8738 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8739 else 8740 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 8741 target += ring->pipe; 8742 8743 switch (type) { 8744 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 8745 if (state == AMDGPU_IRQ_STATE_DISABLE) { 8746 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8747 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8748 GENERIC2_INT_ENABLE, 0); 8749 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8750 8751 tmp = RREG32(target); 8752 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8753 GENERIC2_INT_ENABLE, 0); 8754 WREG32(target, tmp); 8755 } else { 8756 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 8757 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 8758 GENERIC2_INT_ENABLE, 1); 8759 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 8760 8761 tmp = RREG32(target); 8762 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 8763 GENERIC2_INT_ENABLE, 1); 8764 WREG32(target, tmp); 8765 } 8766 break; 8767 default: 8768 BUG(); /* kiq only support GENERIC2_INT now */ 8769 break; 8770 } 8771 return 0; 8772 } 8773 8774 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 8775 struct amdgpu_irq_src *source, 8776 struct amdgpu_iv_entry *entry) 8777 { 8778 u8 me_id, pipe_id, queue_id; 8779 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 8780 8781 me_id = (entry->ring_id & 0x0c) >> 2; 8782 pipe_id = (entry->ring_id & 0x03) >> 0; 8783 queue_id = (entry->ring_id & 0x70) >> 4; 8784 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 8785 me_id, pipe_id, queue_id); 8786 8787 amdgpu_fence_process(ring); 8788 return 0; 8789 } 8790 8791 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 8792 { 8793 const unsigned int gcr_cntl = 8794 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 8795 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 8796 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 8797 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 8798 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 8799 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 8800 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 8801 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 8802 8803 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 8804 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 8805 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 8806 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 8807 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 8808 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 8809 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 8810 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 8811 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 8812 } 8813 8814 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 8815 .name = "gfx_v10_0", 8816 .early_init = gfx_v10_0_early_init, 8817 .late_init = gfx_v10_0_late_init, 8818 .sw_init = gfx_v10_0_sw_init, 8819 .sw_fini = gfx_v10_0_sw_fini, 8820 .hw_init = gfx_v10_0_hw_init, 8821 .hw_fini = gfx_v10_0_hw_fini, 8822 .suspend = gfx_v10_0_suspend, 8823 .resume = gfx_v10_0_resume, 8824 .is_idle = gfx_v10_0_is_idle, 8825 .wait_for_idle = gfx_v10_0_wait_for_idle, 8826 .soft_reset = gfx_v10_0_soft_reset, 8827 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 8828 .set_powergating_state = gfx_v10_0_set_powergating_state, 8829 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 8830 }; 8831 8832 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 8833 .type = AMDGPU_RING_TYPE_GFX, 8834 .align_mask = 0xff, 8835 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8836 .support_64bit_ptrs = true, 8837 .vmhub = AMDGPU_GFXHUB_0, 8838 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 8839 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 8840 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 8841 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 8842 5 + /* COND_EXEC */ 8843 7 + /* PIPELINE_SYNC */ 8844 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8845 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8846 2 + /* VM_FLUSH */ 8847 8 + /* FENCE for VM_FLUSH */ 8848 20 + /* GDS switch */ 8849 4 + /* double SWITCH_BUFFER, 8850 * the first COND_EXEC jump to the place 8851 * just prior to this double SWITCH_BUFFER 8852 */ 8853 5 + /* COND_EXEC */ 8854 7 + /* HDP_flush */ 8855 4 + /* VGT_flush */ 8856 14 + /* CE_META */ 8857 31 + /* DE_META */ 8858 3 + /* CNTX_CTRL */ 8859 5 + /* HDP_INVL */ 8860 8 + 8 + /* FENCE x2 */ 8861 2 + /* SWITCH_BUFFER */ 8862 8, /* gfx_v10_0_emit_mem_sync */ 8863 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 8864 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 8865 .emit_fence = gfx_v10_0_ring_emit_fence, 8866 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8867 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8868 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8869 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8870 .test_ring = gfx_v10_0_ring_test_ring, 8871 .test_ib = gfx_v10_0_ring_test_ib, 8872 .insert_nop = amdgpu_ring_insert_nop, 8873 .pad_ib = amdgpu_ring_generic_pad_ib, 8874 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 8875 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 8876 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 8877 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 8878 .preempt_ib = gfx_v10_0_ring_preempt_ib, 8879 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 8880 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8881 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8882 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8883 .soft_recovery = gfx_v10_0_ring_soft_recovery, 8884 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8885 }; 8886 8887 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 8888 .type = AMDGPU_RING_TYPE_COMPUTE, 8889 .align_mask = 0xff, 8890 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8891 .support_64bit_ptrs = true, 8892 .vmhub = AMDGPU_GFXHUB_0, 8893 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8894 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8895 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8896 .emit_frame_size = 8897 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8898 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8899 5 + /* hdp invalidate */ 8900 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8901 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8902 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8903 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8904 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 8905 8, /* gfx_v10_0_emit_mem_sync */ 8906 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8907 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8908 .emit_fence = gfx_v10_0_ring_emit_fence, 8909 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 8910 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 8911 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 8912 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 8913 .test_ring = gfx_v10_0_ring_test_ring, 8914 .test_ib = gfx_v10_0_ring_test_ib, 8915 .insert_nop = amdgpu_ring_insert_nop, 8916 .pad_ib = amdgpu_ring_generic_pad_ib, 8917 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8918 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8919 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8920 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 8921 }; 8922 8923 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 8924 .type = AMDGPU_RING_TYPE_KIQ, 8925 .align_mask = 0xff, 8926 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 8927 .support_64bit_ptrs = true, 8928 .vmhub = AMDGPU_GFXHUB_0, 8929 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 8930 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 8931 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 8932 .emit_frame_size = 8933 20 + /* gfx_v10_0_ring_emit_gds_switch */ 8934 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 8935 5 + /*hdp invalidate */ 8936 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 8937 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 8938 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8939 2 + /* gfx_v10_0_ring_emit_vm_flush */ 8940 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 8941 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 8942 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 8943 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 8944 .test_ring = gfx_v10_0_ring_test_ring, 8945 .test_ib = gfx_v10_0_ring_test_ib, 8946 .insert_nop = amdgpu_ring_insert_nop, 8947 .pad_ib = amdgpu_ring_generic_pad_ib, 8948 .emit_rreg = gfx_v10_0_ring_emit_rreg, 8949 .emit_wreg = gfx_v10_0_ring_emit_wreg, 8950 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 8951 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 8952 }; 8953 8954 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 8955 { 8956 int i; 8957 8958 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 8959 8960 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 8961 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 8962 8963 for (i = 0; i < adev->gfx.num_compute_rings; i++) 8964 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 8965 } 8966 8967 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 8968 .set = gfx_v10_0_set_eop_interrupt_state, 8969 .process = gfx_v10_0_eop_irq, 8970 }; 8971 8972 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 8973 .set = gfx_v10_0_set_priv_reg_fault_state, 8974 .process = gfx_v10_0_priv_reg_irq, 8975 }; 8976 8977 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 8978 .set = gfx_v10_0_set_priv_inst_fault_state, 8979 .process = gfx_v10_0_priv_inst_irq, 8980 }; 8981 8982 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 8983 .set = gfx_v10_0_kiq_set_interrupt_state, 8984 .process = gfx_v10_0_kiq_irq, 8985 }; 8986 8987 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 8988 { 8989 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 8990 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 8991 8992 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 8993 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 8994 8995 adev->gfx.priv_reg_irq.num_types = 1; 8996 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 8997 8998 adev->gfx.priv_inst_irq.num_types = 1; 8999 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9000 } 9001 9002 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9003 { 9004 switch (adev->asic_type) { 9005 case CHIP_NAVI10: 9006 case CHIP_NAVI14: 9007 case CHIP_SIENNA_CICHLID: 9008 case CHIP_NAVY_FLOUNDER: 9009 case CHIP_VANGOGH: 9010 case CHIP_DIMGREY_CAVEFISH: 9011 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9012 break; 9013 case CHIP_NAVI12: 9014 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9015 break; 9016 default: 9017 break; 9018 } 9019 } 9020 9021 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9022 { 9023 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9024 adev->gfx.config.max_sh_per_se * 9025 adev->gfx.config.max_shader_engines; 9026 9027 adev->gds.gds_size = 0x10000; 9028 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9029 adev->gds.gws_size = 64; 9030 adev->gds.oa_size = 16; 9031 } 9032 9033 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9034 u32 bitmap) 9035 { 9036 u32 data; 9037 9038 if (!bitmap) 9039 return; 9040 9041 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9042 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9043 9044 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9045 } 9046 9047 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9048 { 9049 u32 data, wgp_bitmask; 9050 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9051 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9052 9053 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9054 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9055 9056 wgp_bitmask = 9057 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9058 9059 return (~data) & wgp_bitmask; 9060 } 9061 9062 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9063 { 9064 u32 wgp_idx, wgp_active_bitmap; 9065 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9066 9067 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9068 cu_active_bitmap = 0; 9069 9070 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9071 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9072 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9073 if (wgp_active_bitmap & (1 << wgp_idx)) 9074 cu_active_bitmap |= cu_bitmap_per_wgp; 9075 } 9076 9077 return cu_active_bitmap; 9078 } 9079 9080 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9081 struct amdgpu_cu_info *cu_info) 9082 { 9083 int i, j, k, counter, active_cu_number = 0; 9084 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9085 unsigned disable_masks[4 * 2]; 9086 9087 if (!adev || !cu_info) 9088 return -EINVAL; 9089 9090 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9091 9092 mutex_lock(&adev->grbm_idx_mutex); 9093 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9094 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9095 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9096 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 9097 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9098 continue; 9099 mask = 1; 9100 ao_bitmap = 0; 9101 counter = 0; 9102 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9103 if (i < 4 && j < 2) 9104 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9105 adev, disable_masks[i * 2 + j]); 9106 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9107 cu_info->bitmap[i][j] = bitmap; 9108 9109 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9110 if (bitmap & mask) { 9111 if (counter < adev->gfx.config.max_cu_per_sh) 9112 ao_bitmap |= mask; 9113 counter++; 9114 } 9115 mask <<= 1; 9116 } 9117 active_cu_number += counter; 9118 if (i < 2 && j < 2) 9119 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9120 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9121 } 9122 } 9123 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9124 mutex_unlock(&adev->grbm_idx_mutex); 9125 9126 cu_info->number = active_cu_number; 9127 cu_info->ao_cu_mask = ao_cu_mask; 9128 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9129 9130 return 0; 9131 } 9132 9133 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9134 { 9135 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9136 9137 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9138 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9139 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9140 9141 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9142 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9143 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9144 9145 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9146 adev->gfx.config.max_shader_engines); 9147 disabled_sa = efuse_setting | vbios_setting; 9148 disabled_sa &= max_sa_mask; 9149 9150 return disabled_sa; 9151 } 9152 9153 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9154 { 9155 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9156 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9157 9158 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9159 9160 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9161 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9162 max_shader_engines = adev->gfx.config.max_shader_engines; 9163 9164 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9165 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9166 disabled_sa_per_se &= max_sa_per_se_mask; 9167 if (disabled_sa_per_se == max_sa_per_se_mask) { 9168 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9169 break; 9170 } 9171 } 9172 } 9173 9174 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9175 { 9176 .type = AMD_IP_BLOCK_TYPE_GFX, 9177 .major = 10, 9178 .minor = 0, 9179 .rev = 0, 9180 .funcs = &gfx_v10_0_ip_funcs, 9181 }; 9182