1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "navi10_enum.h" 39 #include "hdp/hdp_5_0_0_offset.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15_common.h" 44 #include "clearstate_gfx10.h" 45 #include "v10_structs.h" 46 #include "gfx_v10_0.h" 47 #include "nbio_v2_3.h" 48 49 /** 50 * Navi10 has two graphic rings to share each graphic pipe. 51 * 1. Primary ring 52 * 2. Async ring 53 * 54 * In bring-up phase, it just used primary ring so set gfx ring number as 1 at 55 * first. 56 */ 57 #define GFX10_NUM_GFX_RINGS 2 58 #define GFX10_MEC_HPD_SIZE 2048 59 60 #define F32_CE_PROGRAM_RAM_SIZE 65536 61 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 62 63 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 68 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 72 73 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 74 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 75 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 76 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 77 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 78 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 79 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 80 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 81 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 82 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 83 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 84 85 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 86 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 87 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 88 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 89 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 90 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 91 92 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 93 { 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 131 }; 132 133 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 134 { 135 /* Pending on emulation bring up */ 136 }; 137 138 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 139 { 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 175 }; 176 177 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 178 { 179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 219 }; 220 221 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 222 { 223 /* Pending on emulation bring up */ 224 }; 225 226 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 227 { 228 /* Pending on emulation bring up */ 229 }; 230 231 #define DEFAULT_SH_MEM_CONFIG \ 232 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 233 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 234 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 235 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 236 237 238 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 239 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 240 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 241 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 242 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 243 struct amdgpu_cu_info *cu_info); 244 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 245 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 246 u32 sh_num, u32 instance); 247 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 248 249 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 250 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 251 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 252 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 253 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 254 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 255 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start); 256 257 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 258 { 259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 260 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 261 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 262 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 263 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 264 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 265 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 266 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 267 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 268 } 269 270 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 271 struct amdgpu_ring *ring) 272 { 273 struct amdgpu_device *adev = kiq_ring->adev; 274 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 275 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 276 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 277 278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 279 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 280 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 281 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 282 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 283 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 284 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 285 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 286 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 287 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 288 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 289 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 290 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 291 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 292 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 293 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 294 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 295 } 296 297 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 298 struct amdgpu_ring *ring, 299 enum amdgpu_unmap_queues_action action, 300 u64 gpu_addr, u64 seq) 301 { 302 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 303 304 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 305 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 306 PACKET3_UNMAP_QUEUES_ACTION(action) | 307 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 308 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 309 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 310 amdgpu_ring_write(kiq_ring, 311 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 312 313 if (action == PREEMPT_QUEUES_NO_UNMAP) { 314 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 315 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 316 amdgpu_ring_write(kiq_ring, seq); 317 } else { 318 amdgpu_ring_write(kiq_ring, 0); 319 amdgpu_ring_write(kiq_ring, 0); 320 amdgpu_ring_write(kiq_ring, 0); 321 } 322 } 323 324 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 325 struct amdgpu_ring *ring, 326 u64 addr, 327 u64 seq) 328 { 329 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 330 331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 332 amdgpu_ring_write(kiq_ring, 333 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 334 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 335 PACKET3_QUERY_STATUS_COMMAND(2)); 336 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 337 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 338 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 339 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 340 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 341 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 342 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 343 } 344 345 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 346 .kiq_set_resources = gfx10_kiq_set_resources, 347 .kiq_map_queues = gfx10_kiq_map_queues, 348 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 349 .kiq_query_status = gfx10_kiq_query_status, 350 .set_resources_size = 8, 351 .map_queues_size = 7, 352 .unmap_queues_size = 6, 353 .query_status_size = 7, 354 }; 355 356 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 357 { 358 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 359 } 360 361 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 362 { 363 switch (adev->asic_type) { 364 case CHIP_NAVI10: 365 soc15_program_register_sequence(adev, 366 golden_settings_gc_10_1, 367 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 368 soc15_program_register_sequence(adev, 369 golden_settings_gc_10_0_nv10, 370 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 371 break; 372 case CHIP_NAVI14: 373 soc15_program_register_sequence(adev, 374 golden_settings_gc_10_1_1, 375 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 376 soc15_program_register_sequence(adev, 377 golden_settings_gc_10_1_nv14, 378 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 379 break; 380 case CHIP_NAVI12: 381 soc15_program_register_sequence(adev, 382 golden_settings_gc_10_1_2, 383 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 384 soc15_program_register_sequence(adev, 385 golden_settings_gc_10_1_2_nv12, 386 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 387 break; 388 default: 389 break; 390 } 391 } 392 393 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 394 { 395 adev->gfx.scratch.num_reg = 8; 396 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 397 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 398 } 399 400 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 401 bool wc, uint32_t reg, uint32_t val) 402 { 403 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 404 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 405 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 406 amdgpu_ring_write(ring, reg); 407 amdgpu_ring_write(ring, 0); 408 amdgpu_ring_write(ring, val); 409 } 410 411 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 412 int mem_space, int opt, uint32_t addr0, 413 uint32_t addr1, uint32_t ref, uint32_t mask, 414 uint32_t inv) 415 { 416 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 417 amdgpu_ring_write(ring, 418 /* memory (1) or register (0) */ 419 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 420 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 421 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 422 WAIT_REG_MEM_ENGINE(eng_sel))); 423 424 if (mem_space) 425 BUG_ON(addr0 & 0x3); /* Dword align */ 426 amdgpu_ring_write(ring, addr0); 427 amdgpu_ring_write(ring, addr1); 428 amdgpu_ring_write(ring, ref); 429 amdgpu_ring_write(ring, mask); 430 amdgpu_ring_write(ring, inv); /* poll interval */ 431 } 432 433 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 434 { 435 struct amdgpu_device *adev = ring->adev; 436 uint32_t scratch; 437 uint32_t tmp = 0; 438 unsigned i; 439 int r; 440 441 r = amdgpu_gfx_scratch_get(adev, &scratch); 442 if (r) { 443 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 444 return r; 445 } 446 447 WREG32(scratch, 0xCAFEDEAD); 448 449 r = amdgpu_ring_alloc(ring, 3); 450 if (r) { 451 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 452 ring->idx, r); 453 amdgpu_gfx_scratch_free(adev, scratch); 454 return r; 455 } 456 457 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 458 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 459 amdgpu_ring_write(ring, 0xDEADBEEF); 460 amdgpu_ring_commit(ring); 461 462 for (i = 0; i < adev->usec_timeout; i++) { 463 tmp = RREG32(scratch); 464 if (tmp == 0xDEADBEEF) 465 break; 466 if (amdgpu_emu_mode == 1) 467 msleep(1); 468 else 469 udelay(1); 470 } 471 if (i < adev->usec_timeout) { 472 if (amdgpu_emu_mode == 1) 473 DRM_INFO("ring test on %d succeeded in %d msecs\n", 474 ring->idx, i); 475 else 476 DRM_INFO("ring test on %d succeeded in %d usecs\n", 477 ring->idx, i); 478 } else { 479 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 480 ring->idx, scratch, tmp); 481 r = -EINVAL; 482 } 483 amdgpu_gfx_scratch_free(adev, scratch); 484 485 return r; 486 } 487 488 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 489 { 490 struct amdgpu_device *adev = ring->adev; 491 struct amdgpu_ib ib; 492 struct dma_fence *f = NULL; 493 uint32_t scratch; 494 uint32_t tmp = 0; 495 long r; 496 497 r = amdgpu_gfx_scratch_get(adev, &scratch); 498 if (r) { 499 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 500 return r; 501 } 502 503 WREG32(scratch, 0xCAFEDEAD); 504 505 memset(&ib, 0, sizeof(ib)); 506 r = amdgpu_ib_get(adev, NULL, 256, &ib); 507 if (r) { 508 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 509 goto err1; 510 } 511 512 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 513 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 514 ib.ptr[2] = 0xDEADBEEF; 515 ib.length_dw = 3; 516 517 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 518 if (r) 519 goto err2; 520 521 r = dma_fence_wait_timeout(f, false, timeout); 522 if (r == 0) { 523 DRM_ERROR("amdgpu: IB test timed out.\n"); 524 r = -ETIMEDOUT; 525 goto err2; 526 } else if (r < 0) { 527 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 528 goto err2; 529 } 530 531 tmp = RREG32(scratch); 532 if (tmp == 0xDEADBEEF) { 533 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 534 r = 0; 535 } else { 536 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 537 scratch, tmp); 538 r = -EINVAL; 539 } 540 err2: 541 amdgpu_ib_free(adev, &ib, NULL); 542 dma_fence_put(f); 543 err1: 544 amdgpu_gfx_scratch_free(adev, scratch); 545 546 return r; 547 } 548 549 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 550 { 551 release_firmware(adev->gfx.pfp_fw); 552 adev->gfx.pfp_fw = NULL; 553 release_firmware(adev->gfx.me_fw); 554 adev->gfx.me_fw = NULL; 555 release_firmware(adev->gfx.ce_fw); 556 adev->gfx.ce_fw = NULL; 557 release_firmware(adev->gfx.rlc_fw); 558 adev->gfx.rlc_fw = NULL; 559 release_firmware(adev->gfx.mec_fw); 560 adev->gfx.mec_fw = NULL; 561 release_firmware(adev->gfx.mec2_fw); 562 adev->gfx.mec2_fw = NULL; 563 564 kfree(adev->gfx.rlc.register_list_format); 565 } 566 567 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 568 { 569 adev->gfx.cp_fw_write_wait = false; 570 571 switch (adev->asic_type) { 572 case CHIP_NAVI10: 573 case CHIP_NAVI12: 574 case CHIP_NAVI14: 575 if ((adev->gfx.me_fw_version >= 0x00000046) && 576 (adev->gfx.me_feature_version >= 27) && 577 (adev->gfx.pfp_fw_version >= 0x00000068) && 578 (adev->gfx.pfp_feature_version >= 27) && 579 (adev->gfx.mec_fw_version >= 0x0000005b) && 580 (adev->gfx.mec_feature_version >= 27)) 581 adev->gfx.cp_fw_write_wait = true; 582 break; 583 default: 584 break; 585 } 586 587 if (adev->gfx.cp_fw_write_wait == false) 588 DRM_WARN_ONCE("Warning: check cp_fw_version and update it to realize \ 589 GRBM requires 1-cycle delay in cp firmware\n"); 590 } 591 592 593 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 594 { 595 const struct rlc_firmware_header_v2_1 *rlc_hdr; 596 597 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 598 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 599 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 600 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 601 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 602 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 603 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 604 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 605 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 606 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 607 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 608 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 609 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 610 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 611 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 612 } 613 614 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 615 { 616 switch (adev->asic_type) { 617 case CHIP_NAVI10: 618 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 619 break; 620 default: 621 break; 622 } 623 } 624 625 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 626 { 627 const char *chip_name; 628 char fw_name[40]; 629 char wks[10]; 630 int err; 631 struct amdgpu_firmware_info *info = NULL; 632 const struct common_firmware_header *header = NULL; 633 const struct gfx_firmware_header_v1_0 *cp_hdr; 634 const struct rlc_firmware_header_v2_0 *rlc_hdr; 635 unsigned int *tmp = NULL; 636 unsigned int i = 0; 637 uint16_t version_major; 638 uint16_t version_minor; 639 640 DRM_DEBUG("\n"); 641 642 memset(wks, 0, sizeof(wks)); 643 switch (adev->asic_type) { 644 case CHIP_NAVI10: 645 chip_name = "navi10"; 646 break; 647 case CHIP_NAVI14: 648 chip_name = "navi14"; 649 if (!(adev->pdev->device == 0x7340 && 650 adev->pdev->revision != 0x00)) 651 snprintf(wks, sizeof(wks), "_wks"); 652 break; 653 case CHIP_NAVI12: 654 chip_name = "navi12"; 655 break; 656 default: 657 BUG(); 658 } 659 660 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 661 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 662 if (err) 663 goto out; 664 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 665 if (err) 666 goto out; 667 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 668 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 669 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 670 671 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 672 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 673 if (err) 674 goto out; 675 err = amdgpu_ucode_validate(adev->gfx.me_fw); 676 if (err) 677 goto out; 678 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 679 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 680 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 681 682 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 683 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 684 if (err) 685 goto out; 686 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 687 if (err) 688 goto out; 689 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 690 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 691 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 692 693 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 694 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 695 if (err) 696 goto out; 697 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 698 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 699 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 700 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 701 if (version_major == 2 && version_minor == 1) 702 adev->gfx.rlc.is_rlc_v2_1 = true; 703 704 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 705 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 706 adev->gfx.rlc.save_and_restore_offset = 707 le32_to_cpu(rlc_hdr->save_and_restore_offset); 708 adev->gfx.rlc.clear_state_descriptor_offset = 709 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 710 adev->gfx.rlc.avail_scratch_ram_locations = 711 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 712 adev->gfx.rlc.reg_restore_list_size = 713 le32_to_cpu(rlc_hdr->reg_restore_list_size); 714 adev->gfx.rlc.reg_list_format_start = 715 le32_to_cpu(rlc_hdr->reg_list_format_start); 716 adev->gfx.rlc.reg_list_format_separate_start = 717 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 718 adev->gfx.rlc.starting_offsets_start = 719 le32_to_cpu(rlc_hdr->starting_offsets_start); 720 adev->gfx.rlc.reg_list_format_size_bytes = 721 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 722 adev->gfx.rlc.reg_list_size_bytes = 723 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 724 adev->gfx.rlc.register_list_format = 725 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 726 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 727 if (!adev->gfx.rlc.register_list_format) { 728 err = -ENOMEM; 729 goto out; 730 } 731 732 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 733 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 734 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 735 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 736 737 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 738 739 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 740 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 741 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 742 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 743 744 if (adev->gfx.rlc.is_rlc_v2_1) 745 gfx_v10_0_init_rlc_ext_microcode(adev); 746 747 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 748 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 749 if (err) 750 goto out; 751 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 752 if (err) 753 goto out; 754 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 755 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 756 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 757 758 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 759 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 760 if (!err) { 761 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 762 if (err) 763 goto out; 764 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 765 adev->gfx.mec2_fw->data; 766 adev->gfx.mec2_fw_version = 767 le32_to_cpu(cp_hdr->header.ucode_version); 768 adev->gfx.mec2_feature_version = 769 le32_to_cpu(cp_hdr->ucode_feature_version); 770 } else { 771 err = 0; 772 adev->gfx.mec2_fw = NULL; 773 } 774 775 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 776 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 777 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 778 info->fw = adev->gfx.pfp_fw; 779 header = (const struct common_firmware_header *)info->fw->data; 780 adev->firmware.fw_size += 781 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 782 783 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 784 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 785 info->fw = adev->gfx.me_fw; 786 header = (const struct common_firmware_header *)info->fw->data; 787 adev->firmware.fw_size += 788 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 789 790 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 791 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 792 info->fw = adev->gfx.ce_fw; 793 header = (const struct common_firmware_header *)info->fw->data; 794 adev->firmware.fw_size += 795 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 796 797 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 798 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 799 info->fw = adev->gfx.rlc_fw; 800 header = (const struct common_firmware_header *)info->fw->data; 801 adev->firmware.fw_size += 802 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 803 804 if (adev->gfx.rlc.is_rlc_v2_1 && 805 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 806 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 807 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 808 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 809 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 810 info->fw = adev->gfx.rlc_fw; 811 adev->firmware.fw_size += 812 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 813 814 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 815 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 816 info->fw = adev->gfx.rlc_fw; 817 adev->firmware.fw_size += 818 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 819 820 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 821 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 822 info->fw = adev->gfx.rlc_fw; 823 adev->firmware.fw_size += 824 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 825 } 826 827 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 828 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 829 info->fw = adev->gfx.mec_fw; 830 header = (const struct common_firmware_header *)info->fw->data; 831 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 832 adev->firmware.fw_size += 833 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 834 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 835 836 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 837 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 838 info->fw = adev->gfx.mec_fw; 839 adev->firmware.fw_size += 840 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 841 842 if (adev->gfx.mec2_fw) { 843 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 844 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 845 info->fw = adev->gfx.mec2_fw; 846 header = (const struct common_firmware_header *)info->fw->data; 847 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 848 adev->firmware.fw_size += 849 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 850 le32_to_cpu(cp_hdr->jt_size) * 4, 851 PAGE_SIZE); 852 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 853 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 854 info->fw = adev->gfx.mec2_fw; 855 adev->firmware.fw_size += 856 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 857 PAGE_SIZE); 858 } 859 } 860 861 gfx_v10_0_check_fw_write_wait(adev); 862 out: 863 if (err) { 864 dev_err(adev->dev, 865 "gfx10: Failed to load firmware \"%s\"\n", 866 fw_name); 867 release_firmware(adev->gfx.pfp_fw); 868 adev->gfx.pfp_fw = NULL; 869 release_firmware(adev->gfx.me_fw); 870 adev->gfx.me_fw = NULL; 871 release_firmware(adev->gfx.ce_fw); 872 adev->gfx.ce_fw = NULL; 873 release_firmware(adev->gfx.rlc_fw); 874 adev->gfx.rlc_fw = NULL; 875 release_firmware(adev->gfx.mec_fw); 876 adev->gfx.mec_fw = NULL; 877 release_firmware(adev->gfx.mec2_fw); 878 adev->gfx.mec2_fw = NULL; 879 } 880 881 gfx_v10_0_check_gfxoff_flag(adev); 882 883 return err; 884 } 885 886 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 887 { 888 u32 count = 0; 889 const struct cs_section_def *sect = NULL; 890 const struct cs_extent_def *ext = NULL; 891 892 /* begin clear state */ 893 count += 2; 894 /* context control state */ 895 count += 3; 896 897 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 898 for (ext = sect->section; ext->extent != NULL; ++ext) { 899 if (sect->id == SECT_CONTEXT) 900 count += 2 + ext->reg_count; 901 else 902 return 0; 903 } 904 } 905 906 /* set PA_SC_TILE_STEERING_OVERRIDE */ 907 count += 3; 908 /* end clear state */ 909 count += 2; 910 /* clear state */ 911 count += 2; 912 913 return count; 914 } 915 916 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 917 volatile u32 *buffer) 918 { 919 u32 count = 0, i; 920 const struct cs_section_def *sect = NULL; 921 const struct cs_extent_def *ext = NULL; 922 int ctx_reg_offset; 923 924 if (adev->gfx.rlc.cs_data == NULL) 925 return; 926 if (buffer == NULL) 927 return; 928 929 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 930 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 931 932 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 933 buffer[count++] = cpu_to_le32(0x80000000); 934 buffer[count++] = cpu_to_le32(0x80000000); 935 936 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 937 for (ext = sect->section; ext->extent != NULL; ++ext) { 938 if (sect->id == SECT_CONTEXT) { 939 buffer[count++] = 940 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 941 buffer[count++] = cpu_to_le32(ext->reg_index - 942 PACKET3_SET_CONTEXT_REG_START); 943 for (i = 0; i < ext->reg_count; i++) 944 buffer[count++] = cpu_to_le32(ext->extent[i]); 945 } else { 946 return; 947 } 948 } 949 } 950 951 ctx_reg_offset = 952 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 953 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 954 buffer[count++] = cpu_to_le32(ctx_reg_offset); 955 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 956 957 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 958 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 959 960 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 961 buffer[count++] = cpu_to_le32(0); 962 } 963 964 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 965 { 966 /* clear state block */ 967 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 968 &adev->gfx.rlc.clear_state_gpu_addr, 969 (void **)&adev->gfx.rlc.cs_ptr); 970 971 /* jump table block */ 972 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 973 &adev->gfx.rlc.cp_table_gpu_addr, 974 (void **)&adev->gfx.rlc.cp_table_ptr); 975 } 976 977 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 978 { 979 const struct cs_section_def *cs_data; 980 int r; 981 982 adev->gfx.rlc.cs_data = gfx10_cs_data; 983 984 cs_data = adev->gfx.rlc.cs_data; 985 986 if (cs_data) { 987 /* init clear state block */ 988 r = amdgpu_gfx_rlc_init_csb(adev); 989 if (r) 990 return r; 991 } 992 993 return 0; 994 } 995 996 static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev) 997 { 998 int r; 999 1000 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 1001 if (unlikely(r != 0)) 1002 return r; 1003 1004 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, 1005 AMDGPU_GEM_DOMAIN_VRAM); 1006 if (!r) 1007 adev->gfx.rlc.clear_state_gpu_addr = 1008 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); 1009 1010 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1011 1012 return r; 1013 } 1014 1015 static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev) 1016 { 1017 int r; 1018 1019 if (!adev->gfx.rlc.clear_state_obj) 1020 return; 1021 1022 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); 1023 if (likely(r == 0)) { 1024 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 1025 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1026 } 1027 } 1028 1029 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 1030 { 1031 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1032 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1033 } 1034 1035 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 1036 { 1037 int r; 1038 1039 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 1040 1041 amdgpu_gfx_graphics_queue_acquire(adev); 1042 1043 r = gfx_v10_0_init_microcode(adev); 1044 if (r) 1045 DRM_ERROR("Failed to load gfx firmware!\n"); 1046 1047 return r; 1048 } 1049 1050 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 1051 { 1052 int r; 1053 u32 *hpd; 1054 const __le32 *fw_data = NULL; 1055 unsigned fw_size; 1056 u32 *fw = NULL; 1057 size_t mec_hpd_size; 1058 1059 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 1060 1061 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1062 1063 /* take ownership of the relevant compute queues */ 1064 amdgpu_gfx_compute_queue_acquire(adev); 1065 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 1066 1067 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1068 AMDGPU_GEM_DOMAIN_GTT, 1069 &adev->gfx.mec.hpd_eop_obj, 1070 &adev->gfx.mec.hpd_eop_gpu_addr, 1071 (void **)&hpd); 1072 if (r) { 1073 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1074 gfx_v10_0_mec_fini(adev); 1075 return r; 1076 } 1077 1078 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 1079 1080 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1081 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1082 1083 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1084 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1085 1086 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1087 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1088 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1089 1090 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1091 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1092 &adev->gfx.mec.mec_fw_obj, 1093 &adev->gfx.mec.mec_fw_gpu_addr, 1094 (void **)&fw); 1095 if (r) { 1096 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 1097 gfx_v10_0_mec_fini(adev); 1098 return r; 1099 } 1100 1101 memcpy(fw, fw_data, fw_size); 1102 1103 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1104 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1105 } 1106 1107 return 0; 1108 } 1109 1110 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1111 { 1112 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1113 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1114 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1115 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1116 } 1117 1118 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1119 uint32_t thread, uint32_t regno, 1120 uint32_t num, uint32_t *out) 1121 { 1122 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1123 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1124 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1125 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1126 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1127 while (num--) 1128 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1129 } 1130 1131 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1132 { 1133 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 1134 * field when performing a select_se_sh so it should be 1135 * zero here */ 1136 WARN_ON(simd != 0); 1137 1138 /* type 2 wave data */ 1139 dst[(*no_fields)++] = 2; 1140 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1141 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1142 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1143 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1144 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1145 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1146 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1147 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 1148 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1149 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1150 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1151 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1152 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1153 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1154 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1155 } 1156 1157 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1158 uint32_t wave, uint32_t start, 1159 uint32_t size, uint32_t *dst) 1160 { 1161 WARN_ON(simd != 0); 1162 1163 wave_read_regs( 1164 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1165 dst); 1166 } 1167 1168 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1169 uint32_t wave, uint32_t thread, 1170 uint32_t start, uint32_t size, 1171 uint32_t *dst) 1172 { 1173 wave_read_regs( 1174 adev, wave, thread, 1175 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1176 } 1177 1178 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 1179 u32 me, u32 pipe, u32 q, u32 vm) 1180 { 1181 nv_grbm_select(adev, me, pipe, q, vm); 1182 } 1183 1184 1185 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 1186 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 1187 .select_se_sh = &gfx_v10_0_select_se_sh, 1188 .read_wave_data = &gfx_v10_0_read_wave_data, 1189 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 1190 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 1191 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 1192 }; 1193 1194 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 1195 { 1196 u32 gb_addr_config; 1197 1198 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 1199 1200 switch (adev->asic_type) { 1201 case CHIP_NAVI10: 1202 case CHIP_NAVI14: 1203 case CHIP_NAVI12: 1204 adev->gfx.config.max_hw_contexts = 8; 1205 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1206 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1207 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1208 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1209 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1210 break; 1211 default: 1212 BUG(); 1213 break; 1214 } 1215 1216 adev->gfx.config.gb_addr_config = gb_addr_config; 1217 1218 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1219 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1220 GB_ADDR_CONFIG, NUM_PIPES); 1221 1222 adev->gfx.config.max_tile_pipes = 1223 adev->gfx.config.gb_addr_config_fields.num_pipes; 1224 1225 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1226 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1227 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 1228 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1229 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1230 GB_ADDR_CONFIG, NUM_RB_PER_SE); 1231 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1232 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1233 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 1234 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1235 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1236 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 1237 } 1238 1239 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1240 int me, int pipe, int queue) 1241 { 1242 int r; 1243 struct amdgpu_ring *ring; 1244 unsigned int irq_type; 1245 1246 ring = &adev->gfx.gfx_ring[ring_id]; 1247 1248 ring->me = me; 1249 ring->pipe = pipe; 1250 ring->queue = queue; 1251 1252 ring->ring_obj = NULL; 1253 ring->use_doorbell = true; 1254 1255 if (!ring_id) 1256 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1257 else 1258 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1259 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1260 1261 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1262 r = amdgpu_ring_init(adev, ring, 1024, 1263 &adev->gfx.eop_irq, irq_type); 1264 if (r) 1265 return r; 1266 return 0; 1267 } 1268 1269 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1270 int mec, int pipe, int queue) 1271 { 1272 int r; 1273 unsigned irq_type; 1274 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1275 1276 ring = &adev->gfx.compute_ring[ring_id]; 1277 1278 /* mec0 is me1 */ 1279 ring->me = mec + 1; 1280 ring->pipe = pipe; 1281 ring->queue = queue; 1282 1283 ring->ring_obj = NULL; 1284 ring->use_doorbell = true; 1285 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1286 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1287 + (ring_id * GFX10_MEC_HPD_SIZE); 1288 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1289 1290 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1291 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1292 + ring->pipe; 1293 1294 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1295 r = amdgpu_ring_init(adev, ring, 1024, 1296 &adev->gfx.eop_irq, irq_type); 1297 if (r) 1298 return r; 1299 1300 return 0; 1301 } 1302 1303 static int gfx_v10_0_sw_init(void *handle) 1304 { 1305 int i, j, k, r, ring_id = 0; 1306 struct amdgpu_kiq *kiq; 1307 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1308 1309 switch (adev->asic_type) { 1310 case CHIP_NAVI10: 1311 case CHIP_NAVI14: 1312 case CHIP_NAVI12: 1313 adev->gfx.me.num_me = 1; 1314 adev->gfx.me.num_pipe_per_me = 2; 1315 adev->gfx.me.num_queue_per_pipe = 1; 1316 adev->gfx.mec.num_mec = 2; 1317 adev->gfx.mec.num_pipe_per_mec = 4; 1318 adev->gfx.mec.num_queue_per_pipe = 8; 1319 break; 1320 default: 1321 adev->gfx.me.num_me = 1; 1322 adev->gfx.me.num_pipe_per_me = 1; 1323 adev->gfx.me.num_queue_per_pipe = 1; 1324 adev->gfx.mec.num_mec = 1; 1325 adev->gfx.mec.num_pipe_per_mec = 4; 1326 adev->gfx.mec.num_queue_per_pipe = 8; 1327 break; 1328 } 1329 1330 /* KIQ event */ 1331 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1332 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 1333 &adev->gfx.kiq.irq); 1334 if (r) 1335 return r; 1336 1337 /* EOP Event */ 1338 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1339 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 1340 &adev->gfx.eop_irq); 1341 if (r) 1342 return r; 1343 1344 /* Privileged reg */ 1345 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 1346 &adev->gfx.priv_reg_irq); 1347 if (r) 1348 return r; 1349 1350 /* Privileged inst */ 1351 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 1352 &adev->gfx.priv_inst_irq); 1353 if (r) 1354 return r; 1355 1356 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1357 1358 gfx_v10_0_scratch_init(adev); 1359 1360 r = gfx_v10_0_me_init(adev); 1361 if (r) 1362 return r; 1363 1364 r = gfx_v10_0_rlc_init(adev); 1365 if (r) { 1366 DRM_ERROR("Failed to init rlc BOs!\n"); 1367 return r; 1368 } 1369 1370 r = gfx_v10_0_mec_init(adev); 1371 if (r) { 1372 DRM_ERROR("Failed to init MEC BOs!\n"); 1373 return r; 1374 } 1375 1376 /* set up the gfx ring */ 1377 for (i = 0; i < adev->gfx.me.num_me; i++) { 1378 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1379 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1380 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1381 continue; 1382 1383 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 1384 i, k, j); 1385 if (r) 1386 return r; 1387 ring_id++; 1388 } 1389 } 1390 } 1391 1392 ring_id = 0; 1393 /* set up the compute queues - allocate horizontally across pipes */ 1394 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1395 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1396 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1397 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1398 j)) 1399 continue; 1400 1401 r = gfx_v10_0_compute_ring_init(adev, ring_id, 1402 i, k, j); 1403 if (r) 1404 return r; 1405 1406 ring_id++; 1407 } 1408 } 1409 } 1410 1411 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 1412 if (r) { 1413 DRM_ERROR("Failed to init KIQ BOs!\n"); 1414 return r; 1415 } 1416 1417 kiq = &adev->gfx.kiq; 1418 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1419 if (r) 1420 return r; 1421 1422 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 1423 if (r) 1424 return r; 1425 1426 /* allocate visible FB for rlc auto-loading fw */ 1427 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1428 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 1429 if (r) 1430 return r; 1431 } 1432 1433 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 1434 1435 gfx_v10_0_gpu_early_init(adev); 1436 1437 return 0; 1438 } 1439 1440 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 1441 { 1442 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1443 &adev->gfx.pfp.pfp_fw_gpu_addr, 1444 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1445 } 1446 1447 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 1448 { 1449 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 1450 &adev->gfx.ce.ce_fw_gpu_addr, 1451 (void **)&adev->gfx.ce.ce_fw_ptr); 1452 } 1453 1454 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 1455 { 1456 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1457 &adev->gfx.me.me_fw_gpu_addr, 1458 (void **)&adev->gfx.me.me_fw_ptr); 1459 } 1460 1461 static int gfx_v10_0_sw_fini(void *handle) 1462 { 1463 int i; 1464 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1465 1466 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1467 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1468 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1469 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1470 1471 amdgpu_gfx_mqd_sw_fini(adev); 1472 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1473 amdgpu_gfx_kiq_fini(adev); 1474 1475 gfx_v10_0_pfp_fini(adev); 1476 gfx_v10_0_ce_fini(adev); 1477 gfx_v10_0_me_fini(adev); 1478 gfx_v10_0_rlc_fini(adev); 1479 gfx_v10_0_mec_fini(adev); 1480 1481 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1482 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 1483 1484 gfx_v10_0_free_microcode(adev); 1485 1486 return 0; 1487 } 1488 1489 1490 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev) 1491 { 1492 /* TODO */ 1493 } 1494 1495 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1496 u32 sh_num, u32 instance) 1497 { 1498 u32 data; 1499 1500 if (instance == 0xffffffff) 1501 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1502 INSTANCE_BROADCAST_WRITES, 1); 1503 else 1504 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1505 instance); 1506 1507 if (se_num == 0xffffffff) 1508 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1509 1); 1510 else 1511 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1512 1513 if (sh_num == 0xffffffff) 1514 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1515 1); 1516 else 1517 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1518 1519 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1520 } 1521 1522 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1523 { 1524 u32 data, mask; 1525 1526 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1527 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1528 1529 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1530 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1531 1532 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1533 adev->gfx.config.max_sh_per_se); 1534 1535 return (~data) & mask; 1536 } 1537 1538 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 1539 { 1540 int i, j; 1541 u32 data; 1542 u32 active_rbs = 0; 1543 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1544 adev->gfx.config.max_sh_per_se; 1545 1546 mutex_lock(&adev->grbm_idx_mutex); 1547 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1548 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1549 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1550 data = gfx_v10_0_get_rb_active_bitmap(adev); 1551 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1552 rb_bitmap_width_per_sh); 1553 } 1554 } 1555 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1556 mutex_unlock(&adev->grbm_idx_mutex); 1557 1558 adev->gfx.config.backend_enable_mask = active_rbs; 1559 adev->gfx.config.num_rbs = hweight32(active_rbs); 1560 } 1561 1562 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 1563 { 1564 uint32_t num_sc; 1565 uint32_t enabled_rb_per_sh; 1566 uint32_t active_rb_bitmap; 1567 uint32_t num_rb_per_sc; 1568 uint32_t num_packer_per_sc; 1569 uint32_t pa_sc_tile_steering_override; 1570 1571 /* init num_sc */ 1572 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 1573 adev->gfx.config.num_sc_per_sh; 1574 /* init num_rb_per_sc */ 1575 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 1576 enabled_rb_per_sh = hweight32(active_rb_bitmap); 1577 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 1578 /* init num_packer_per_sc */ 1579 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 1580 1581 pa_sc_tile_steering_override = 0; 1582 pa_sc_tile_steering_override |= 1583 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 1584 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 1585 pa_sc_tile_steering_override |= 1586 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 1587 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 1588 pa_sc_tile_steering_override |= 1589 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 1590 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 1591 1592 return pa_sc_tile_steering_override; 1593 } 1594 1595 #define DEFAULT_SH_MEM_BASES (0x6000) 1596 #define FIRST_COMPUTE_VMID (8) 1597 #define LAST_COMPUTE_VMID (16) 1598 1599 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 1600 { 1601 int i; 1602 uint32_t sh_mem_bases; 1603 1604 /* 1605 * Configure apertures: 1606 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1607 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1608 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1609 */ 1610 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1611 1612 mutex_lock(&adev->srbm_mutex); 1613 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1614 nv_grbm_select(adev, 0, 0, 0, i); 1615 /* CP and shaders */ 1616 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1617 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1618 } 1619 nv_grbm_select(adev, 0, 0, 0, 0); 1620 mutex_unlock(&adev->srbm_mutex); 1621 1622 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1623 acccess. These should be enabled by FW for target VMIDs. */ 1624 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1625 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 1626 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 1627 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 1628 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 1629 } 1630 } 1631 1632 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 1633 { 1634 int vmid; 1635 1636 /* 1637 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1638 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1639 * the driver can enable them for graphics. VMID0 should maintain 1640 * access so that HWS firmware can save/restore entries. 1641 */ 1642 for (vmid = 1; vmid < 16; vmid++) { 1643 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 1644 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 1645 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 1646 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 1647 } 1648 } 1649 1650 1651 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 1652 { 1653 int i, j, k; 1654 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 1655 u32 tmp, wgp_active_bitmap = 0; 1656 u32 gcrd_targets_disable_tcp = 0; 1657 u32 utcl_invreq_disable = 0; 1658 /* 1659 * GCRD_TARGETS_DISABLE field contains 1660 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 1661 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 1662 */ 1663 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 1664 2 * max_wgp_per_sh + /* TCP */ 1665 max_wgp_per_sh + /* SQC */ 1666 4); /* GL1C */ 1667 /* 1668 * UTCL1_UTCL0_INVREQ_DISABLE field contains 1669 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 1670 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 1671 */ 1672 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 1673 2 * max_wgp_per_sh + /* TCP */ 1674 2 * max_wgp_per_sh + /* SQC */ 1675 4 + /* RMI */ 1676 1); /* SQG */ 1677 1678 if (adev->asic_type == CHIP_NAVI10 || 1679 adev->asic_type == CHIP_NAVI14 || 1680 adev->asic_type == CHIP_NAVI12) { 1681 mutex_lock(&adev->grbm_idx_mutex); 1682 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1683 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1684 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1685 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 1686 /* 1687 * Set corresponding TCP bits for the inactive WGPs in 1688 * GCRD_SA_TARGETS_DISABLE 1689 */ 1690 gcrd_targets_disable_tcp = 0; 1691 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 1692 utcl_invreq_disable = 0; 1693 1694 for (k = 0; k < max_wgp_per_sh; k++) { 1695 if (!(wgp_active_bitmap & (1 << k))) { 1696 gcrd_targets_disable_tcp |= 3 << (2 * k); 1697 utcl_invreq_disable |= (3 << (2 * k)) | 1698 (3 << (2 * (max_wgp_per_sh + k))); 1699 } 1700 } 1701 1702 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 1703 /* only override TCP & SQC bits */ 1704 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 1705 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 1706 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 1707 1708 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 1709 /* only override TCP bits */ 1710 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 1711 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 1712 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 1713 } 1714 } 1715 1716 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1717 mutex_unlock(&adev->grbm_idx_mutex); 1718 } 1719 } 1720 1721 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 1722 { 1723 /* TCCs are global (not instanced). */ 1724 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 1725 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 1726 1727 adev->gfx.config.tcc_disabled_mask = 1728 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1729 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1730 } 1731 1732 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 1733 { 1734 u32 tmp; 1735 int i; 1736 1737 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1738 1739 gfx_v10_0_tiling_mode_table_init(adev); 1740 1741 gfx_v10_0_setup_rb(adev); 1742 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 1743 gfx_v10_0_get_tcc_info(adev); 1744 adev->gfx.config.pa_sc_tile_steering_override = 1745 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 1746 1747 /* XXX SH_MEM regs */ 1748 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1749 mutex_lock(&adev->srbm_mutex); 1750 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1751 nv_grbm_select(adev, 0, 0, 0, i); 1752 /* CP and shaders */ 1753 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1754 if (i != 0) { 1755 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1756 (adev->gmc.private_aperture_start >> 48)); 1757 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1758 (adev->gmc.shared_aperture_start >> 48)); 1759 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1760 } 1761 } 1762 nv_grbm_select(adev, 0, 0, 0, 0); 1763 1764 mutex_unlock(&adev->srbm_mutex); 1765 1766 gfx_v10_0_init_compute_vmid(adev); 1767 gfx_v10_0_init_gds_vmid(adev); 1768 1769 } 1770 1771 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1772 bool enable) 1773 { 1774 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1775 1776 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1777 enable ? 1 : 0); 1778 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1779 enable ? 1 : 0); 1780 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1781 enable ? 1 : 0); 1782 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1783 enable ? 1 : 0); 1784 1785 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1786 } 1787 1788 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 1789 { 1790 int r; 1791 1792 if (adev->in_gpu_reset) { 1793 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 1794 if (r) 1795 return r; 1796 1797 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, 1798 (void **)&adev->gfx.rlc.cs_ptr); 1799 if (!r) { 1800 adev->gfx.rlc.funcs->get_csb_buffer(adev, 1801 adev->gfx.rlc.cs_ptr); 1802 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 1803 } 1804 1805 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1806 if (r) 1807 return r; 1808 } 1809 1810 /* csib */ 1811 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 1812 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1813 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 1814 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1815 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1816 1817 return 0; 1818 } 1819 1820 static int gfx_v10_0_init_pg(struct amdgpu_device *adev) 1821 { 1822 int i; 1823 int r; 1824 1825 r = gfx_v10_0_init_csb(adev); 1826 if (r) 1827 return r; 1828 1829 for (i = 0; i < adev->num_vmhubs; i++) 1830 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 1831 1832 /* TODO: init power gating */ 1833 return 0; 1834 } 1835 1836 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 1837 { 1838 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 1839 1840 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1841 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 1842 } 1843 1844 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 1845 { 1846 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1847 udelay(50); 1848 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1849 udelay(50); 1850 } 1851 1852 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1853 bool enable) 1854 { 1855 uint32_t rlc_pg_cntl; 1856 1857 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 1858 1859 if (!enable) { 1860 /* RLC_PG_CNTL[23] = 0 (default) 1861 * RLC will wait for handshake acks with SMU 1862 * GFXOFF will be enabled 1863 * RLC_PG_CNTL[23] = 1 1864 * RLC will not issue any message to SMU 1865 * hence no handshake between SMU & RLC 1866 * GFXOFF will be disabled 1867 */ 1868 rlc_pg_cntl |= 0x800000; 1869 } else 1870 rlc_pg_cntl &= ~0x800000; 1871 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 1872 } 1873 1874 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 1875 { 1876 /* TODO: enable rlc & smu handshake until smu 1877 * and gfxoff feature works as expected */ 1878 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1879 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 1880 1881 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1882 udelay(50); 1883 } 1884 1885 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 1886 { 1887 uint32_t tmp; 1888 1889 /* enable Save Restore Machine */ 1890 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1891 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1892 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1893 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1894 } 1895 1896 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 1897 { 1898 const struct rlc_firmware_header_v2_0 *hdr; 1899 const __le32 *fw_data; 1900 unsigned i, fw_size; 1901 1902 if (!adev->gfx.rlc_fw) 1903 return -EINVAL; 1904 1905 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1906 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1907 1908 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1909 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1910 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1911 1912 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 1913 RLCG_UCODE_LOADING_START_ADDRESS); 1914 1915 for (i = 0; i < fw_size; i++) 1916 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 1917 le32_to_cpup(fw_data++)); 1918 1919 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1920 1921 return 0; 1922 } 1923 1924 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 1925 { 1926 int r; 1927 1928 if (amdgpu_sriov_vf(adev)) 1929 return 0; 1930 1931 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1932 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1933 if (r) 1934 return r; 1935 1936 r = gfx_v10_0_init_pg(adev); 1937 if (r) 1938 return r; 1939 1940 /* enable RLC SRM */ 1941 gfx_v10_0_rlc_enable_srm(adev); 1942 1943 } else { 1944 adev->gfx.rlc.funcs->stop(adev); 1945 1946 /* disable CG */ 1947 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 1948 1949 /* disable PG */ 1950 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 1951 1952 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1953 /* legacy rlc firmware loading */ 1954 r = gfx_v10_0_rlc_load_microcode(adev); 1955 if (r) 1956 return r; 1957 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1958 /* rlc backdoor autoload firmware */ 1959 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 1960 if (r) 1961 return r; 1962 } 1963 1964 r = gfx_v10_0_init_pg(adev); 1965 if (r) 1966 return r; 1967 1968 adev->gfx.rlc.funcs->start(adev); 1969 1970 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1971 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1972 if (r) 1973 return r; 1974 } 1975 } 1976 return 0; 1977 } 1978 1979 static struct { 1980 FIRMWARE_ID id; 1981 unsigned int offset; 1982 unsigned int size; 1983 } rlc_autoload_info[FIRMWARE_ID_MAX]; 1984 1985 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 1986 { 1987 int ret; 1988 RLC_TABLE_OF_CONTENT *rlc_toc; 1989 1990 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 1991 AMDGPU_GEM_DOMAIN_GTT, 1992 &adev->gfx.rlc.rlc_toc_bo, 1993 &adev->gfx.rlc.rlc_toc_gpu_addr, 1994 (void **)&adev->gfx.rlc.rlc_toc_buf); 1995 if (ret) { 1996 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 1997 return ret; 1998 } 1999 2000 /* Copy toc from psp sos fw to rlc toc buffer */ 2001 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 2002 2003 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 2004 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 2005 (rlc_toc->id < FIRMWARE_ID_MAX)) { 2006 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 2007 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 2008 /* Offset needs 4KB alignment */ 2009 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 2010 } 2011 2012 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 2013 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 2014 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 2015 2016 rlc_toc++; 2017 }; 2018 2019 return 0; 2020 } 2021 2022 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 2023 { 2024 uint32_t total_size = 0; 2025 FIRMWARE_ID id; 2026 int ret; 2027 2028 ret = gfx_v10_0_parse_rlc_toc(adev); 2029 if (ret) { 2030 dev_err(adev->dev, "failed to parse rlc toc\n"); 2031 return 0; 2032 } 2033 2034 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 2035 total_size += rlc_autoload_info[id].size; 2036 2037 /* In case the offset in rlc toc ucode is aligned */ 2038 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 2039 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 2040 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 2041 2042 return total_size; 2043 } 2044 2045 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 2046 { 2047 int r; 2048 uint32_t total_size; 2049 2050 total_size = gfx_v10_0_calc_toc_total_size(adev); 2051 2052 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 2053 AMDGPU_GEM_DOMAIN_GTT, 2054 &adev->gfx.rlc.rlc_autoload_bo, 2055 &adev->gfx.rlc.rlc_autoload_gpu_addr, 2056 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 2057 if (r) { 2058 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 2059 return r; 2060 } 2061 2062 return 0; 2063 } 2064 2065 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 2066 { 2067 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 2068 &adev->gfx.rlc.rlc_toc_gpu_addr, 2069 (void **)&adev->gfx.rlc.rlc_toc_buf); 2070 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 2071 &adev->gfx.rlc.rlc_autoload_gpu_addr, 2072 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 2073 } 2074 2075 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 2076 FIRMWARE_ID id, 2077 const void *fw_data, 2078 uint32_t fw_size) 2079 { 2080 uint32_t toc_offset; 2081 uint32_t toc_fw_size; 2082 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 2083 2084 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 2085 return; 2086 2087 toc_offset = rlc_autoload_info[id].offset; 2088 toc_fw_size = rlc_autoload_info[id].size; 2089 2090 if (fw_size == 0) 2091 fw_size = toc_fw_size; 2092 2093 if (fw_size > toc_fw_size) 2094 fw_size = toc_fw_size; 2095 2096 memcpy(ptr + toc_offset, fw_data, fw_size); 2097 2098 if (fw_size < toc_fw_size) 2099 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 2100 } 2101 2102 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 2103 { 2104 void *data; 2105 uint32_t size; 2106 2107 data = adev->gfx.rlc.rlc_toc_buf; 2108 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 2109 2110 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2111 FIRMWARE_ID_RLC_TOC, 2112 data, size); 2113 } 2114 2115 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 2116 { 2117 const __le32 *fw_data; 2118 uint32_t fw_size; 2119 const struct gfx_firmware_header_v1_0 *cp_hdr; 2120 const struct rlc_firmware_header_v2_0 *rlc_hdr; 2121 2122 /* pfp ucode */ 2123 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2124 adev->gfx.pfp_fw->data; 2125 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2126 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2127 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2128 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2129 FIRMWARE_ID_CP_PFP, 2130 fw_data, fw_size); 2131 2132 /* ce ucode */ 2133 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2134 adev->gfx.ce_fw->data; 2135 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2136 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2137 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2138 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2139 FIRMWARE_ID_CP_CE, 2140 fw_data, fw_size); 2141 2142 /* me ucode */ 2143 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2144 adev->gfx.me_fw->data; 2145 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2146 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2147 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2148 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2149 FIRMWARE_ID_CP_ME, 2150 fw_data, fw_size); 2151 2152 /* rlc ucode */ 2153 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 2154 adev->gfx.rlc_fw->data; 2155 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2156 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 2157 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 2158 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2159 FIRMWARE_ID_RLC_G_UCODE, 2160 fw_data, fw_size); 2161 2162 /* mec1 ucode */ 2163 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2164 adev->gfx.mec_fw->data; 2165 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2166 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2167 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 2168 cp_hdr->jt_size * 4; 2169 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2170 FIRMWARE_ID_CP_MEC, 2171 fw_data, fw_size); 2172 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 2173 } 2174 2175 /* Temporarily put sdma part here */ 2176 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 2177 { 2178 const __le32 *fw_data; 2179 uint32_t fw_size; 2180 const struct sdma_firmware_header_v1_0 *sdma_hdr; 2181 int i; 2182 2183 for (i = 0; i < adev->sdma.num_instances; i++) { 2184 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 2185 adev->sdma.instance[i].fw->data; 2186 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 2187 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 2188 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 2189 2190 if (i == 0) { 2191 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2192 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 2193 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2194 FIRMWARE_ID_SDMA0_JT, 2195 (uint32_t *)fw_data + 2196 sdma_hdr->jt_offset, 2197 sdma_hdr->jt_size * 4); 2198 } else if (i == 1) { 2199 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2200 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 2201 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2202 FIRMWARE_ID_SDMA1_JT, 2203 (uint32_t *)fw_data + 2204 sdma_hdr->jt_offset, 2205 sdma_hdr->jt_size * 4); 2206 } 2207 } 2208 } 2209 2210 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 2211 { 2212 uint32_t rlc_g_offset, rlc_g_size, tmp; 2213 uint64_t gpu_addr; 2214 2215 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 2216 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 2217 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 2218 2219 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 2220 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 2221 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 2222 2223 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 2224 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 2225 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 2226 2227 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 2228 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 2229 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 2230 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 2231 return -EINVAL; 2232 } 2233 2234 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 2235 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2236 DRM_ERROR("RLC ROM should halt itself\n"); 2237 return -EINVAL; 2238 } 2239 2240 return 0; 2241 } 2242 2243 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 2244 { 2245 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2246 uint32_t tmp; 2247 int i; 2248 uint64_t addr; 2249 2250 /* Trigger an invalidation of the L1 instruction caches */ 2251 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2252 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2253 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2254 2255 /* Wait for invalidation complete */ 2256 for (i = 0; i < usec_timeout; i++) { 2257 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2258 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2259 INVALIDATE_CACHE_COMPLETE)) 2260 break; 2261 udelay(1); 2262 } 2263 2264 if (i >= usec_timeout) { 2265 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2266 return -EINVAL; 2267 } 2268 2269 /* Program me ucode address into intruction cache address register */ 2270 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2271 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 2272 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2273 lower_32_bits(addr) & 0xFFFFF000); 2274 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2275 upper_32_bits(addr)); 2276 2277 return 0; 2278 } 2279 2280 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 2281 { 2282 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2283 uint32_t tmp; 2284 int i; 2285 uint64_t addr; 2286 2287 /* Trigger an invalidation of the L1 instruction caches */ 2288 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2289 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2290 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2291 2292 /* Wait for invalidation complete */ 2293 for (i = 0; i < usec_timeout; i++) { 2294 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2295 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2296 INVALIDATE_CACHE_COMPLETE)) 2297 break; 2298 udelay(1); 2299 } 2300 2301 if (i >= usec_timeout) { 2302 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2303 return -EINVAL; 2304 } 2305 2306 /* Program ce ucode address into intruction cache address register */ 2307 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2308 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 2309 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2310 lower_32_bits(addr) & 0xFFFFF000); 2311 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2312 upper_32_bits(addr)); 2313 2314 return 0; 2315 } 2316 2317 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 2318 { 2319 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2320 uint32_t tmp; 2321 int i; 2322 uint64_t addr; 2323 2324 /* Trigger an invalidation of the L1 instruction caches */ 2325 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2326 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2327 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2328 2329 /* Wait for invalidation complete */ 2330 for (i = 0; i < usec_timeout; i++) { 2331 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2332 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2333 INVALIDATE_CACHE_COMPLETE)) 2334 break; 2335 udelay(1); 2336 } 2337 2338 if (i >= usec_timeout) { 2339 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2340 return -EINVAL; 2341 } 2342 2343 /* Program pfp ucode address into intruction cache address register */ 2344 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2345 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 2346 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2347 lower_32_bits(addr) & 0xFFFFF000); 2348 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2349 upper_32_bits(addr)); 2350 2351 return 0; 2352 } 2353 2354 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 2355 { 2356 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2357 uint32_t tmp; 2358 int i; 2359 uint64_t addr; 2360 2361 /* Trigger an invalidation of the L1 instruction caches */ 2362 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2363 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2364 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2365 2366 /* Wait for invalidation complete */ 2367 for (i = 0; i < usec_timeout; i++) { 2368 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2369 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2370 INVALIDATE_CACHE_COMPLETE)) 2371 break; 2372 udelay(1); 2373 } 2374 2375 if (i >= usec_timeout) { 2376 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2377 return -EINVAL; 2378 } 2379 2380 /* Program mec1 ucode address into intruction cache address register */ 2381 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2382 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 2383 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2384 lower_32_bits(addr) & 0xFFFFF000); 2385 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2386 upper_32_bits(addr)); 2387 2388 return 0; 2389 } 2390 2391 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2392 { 2393 uint32_t cp_status; 2394 uint32_t bootload_status; 2395 int i, r; 2396 2397 for (i = 0; i < adev->usec_timeout; i++) { 2398 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 2399 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 2400 if ((cp_status == 0) && 2401 (REG_GET_FIELD(bootload_status, 2402 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2403 break; 2404 } 2405 udelay(1); 2406 } 2407 2408 if (i >= adev->usec_timeout) { 2409 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2410 return -ETIMEDOUT; 2411 } 2412 2413 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2414 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 2415 if (r) 2416 return r; 2417 2418 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 2419 if (r) 2420 return r; 2421 2422 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 2423 if (r) 2424 return r; 2425 2426 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 2427 if (r) 2428 return r; 2429 } 2430 2431 return 0; 2432 } 2433 2434 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2435 { 2436 int i; 2437 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2438 2439 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2440 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2441 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2442 if (!enable) { 2443 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2444 adev->gfx.gfx_ring[i].sched.ready = false; 2445 } 2446 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2447 2448 for (i = 0; i < adev->usec_timeout; i++) { 2449 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 2450 break; 2451 udelay(1); 2452 } 2453 2454 if (i >= adev->usec_timeout) 2455 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2456 2457 return 0; 2458 } 2459 2460 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2461 { 2462 int r; 2463 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2464 const __le32 *fw_data; 2465 unsigned i, fw_size; 2466 uint32_t tmp; 2467 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2468 2469 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2470 adev->gfx.pfp_fw->data; 2471 2472 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2473 2474 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2475 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2476 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2477 2478 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2479 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2480 &adev->gfx.pfp.pfp_fw_obj, 2481 &adev->gfx.pfp.pfp_fw_gpu_addr, 2482 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2483 if (r) { 2484 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2485 gfx_v10_0_pfp_fini(adev); 2486 return r; 2487 } 2488 2489 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2490 2491 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2492 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2493 2494 /* Trigger an invalidation of the L1 instruction caches */ 2495 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2496 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2497 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2498 2499 /* Wait for invalidation complete */ 2500 for (i = 0; i < usec_timeout; i++) { 2501 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2502 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2503 INVALIDATE_CACHE_COMPLETE)) 2504 break; 2505 udelay(1); 2506 } 2507 2508 if (i >= usec_timeout) { 2509 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2510 return -EINVAL; 2511 } 2512 2513 if (amdgpu_emu_mode == 1) 2514 adev->nbio.funcs->hdp_flush(adev, NULL); 2515 2516 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 2517 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2518 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2519 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2520 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2521 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 2522 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2523 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 2524 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2525 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2526 2527 return 0; 2528 } 2529 2530 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 2531 { 2532 int r; 2533 const struct gfx_firmware_header_v1_0 *ce_hdr; 2534 const __le32 *fw_data; 2535 unsigned i, fw_size; 2536 uint32_t tmp; 2537 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2538 2539 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2540 adev->gfx.ce_fw->data; 2541 2542 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2543 2544 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2545 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2546 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 2547 2548 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 2549 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2550 &adev->gfx.ce.ce_fw_obj, 2551 &adev->gfx.ce.ce_fw_gpu_addr, 2552 (void **)&adev->gfx.ce.ce_fw_ptr); 2553 if (r) { 2554 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 2555 gfx_v10_0_ce_fini(adev); 2556 return r; 2557 } 2558 2559 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 2560 2561 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 2562 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 2563 2564 /* Trigger an invalidation of the L1 instruction caches */ 2565 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2566 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2567 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2568 2569 /* Wait for invalidation complete */ 2570 for (i = 0; i < usec_timeout; i++) { 2571 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2572 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2573 INVALIDATE_CACHE_COMPLETE)) 2574 break; 2575 udelay(1); 2576 } 2577 2578 if (i >= usec_timeout) { 2579 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2580 return -EINVAL; 2581 } 2582 2583 if (amdgpu_emu_mode == 1) 2584 adev->nbio.funcs->hdp_flush(adev, NULL); 2585 2586 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 2587 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 2588 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 2589 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 2590 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2591 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2592 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 2593 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2594 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 2595 2596 return 0; 2597 } 2598 2599 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2600 { 2601 int r; 2602 const struct gfx_firmware_header_v1_0 *me_hdr; 2603 const __le32 *fw_data; 2604 unsigned i, fw_size; 2605 uint32_t tmp; 2606 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2607 2608 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2609 adev->gfx.me_fw->data; 2610 2611 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2612 2613 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2614 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2615 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2616 2617 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2618 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2619 &adev->gfx.me.me_fw_obj, 2620 &adev->gfx.me.me_fw_gpu_addr, 2621 (void **)&adev->gfx.me.me_fw_ptr); 2622 if (r) { 2623 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2624 gfx_v10_0_me_fini(adev); 2625 return r; 2626 } 2627 2628 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2629 2630 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2631 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2632 2633 /* Trigger an invalidation of the L1 instruction caches */ 2634 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2635 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2636 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2637 2638 /* Wait for invalidation complete */ 2639 for (i = 0; i < usec_timeout; i++) { 2640 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2641 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2642 INVALIDATE_CACHE_COMPLETE)) 2643 break; 2644 udelay(1); 2645 } 2646 2647 if (i >= usec_timeout) { 2648 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2649 return -EINVAL; 2650 } 2651 2652 if (amdgpu_emu_mode == 1) 2653 adev->nbio.funcs->hdp_flush(adev, NULL); 2654 2655 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 2656 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2657 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2658 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2659 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2660 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2661 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 2662 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2663 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2664 2665 return 0; 2666 } 2667 2668 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2669 { 2670 int r; 2671 2672 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2673 return -EINVAL; 2674 2675 gfx_v10_0_cp_gfx_enable(adev, false); 2676 2677 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 2678 if (r) { 2679 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2680 return r; 2681 } 2682 2683 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 2684 if (r) { 2685 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 2686 return r; 2687 } 2688 2689 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 2690 if (r) { 2691 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2692 return r; 2693 } 2694 2695 return 0; 2696 } 2697 2698 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 2699 { 2700 struct amdgpu_ring *ring; 2701 const struct cs_section_def *sect = NULL; 2702 const struct cs_extent_def *ext = NULL; 2703 int r, i; 2704 int ctx_reg_offset; 2705 2706 /* init the CP */ 2707 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 2708 adev->gfx.config.max_hw_contexts - 1); 2709 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2710 2711 gfx_v10_0_cp_gfx_enable(adev, true); 2712 2713 ring = &adev->gfx.gfx_ring[0]; 2714 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 2715 if (r) { 2716 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2717 return r; 2718 } 2719 2720 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2721 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2722 2723 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2724 amdgpu_ring_write(ring, 0x80000000); 2725 amdgpu_ring_write(ring, 0x80000000); 2726 2727 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 2728 for (ext = sect->section; ext->extent != NULL; ++ext) { 2729 if (sect->id == SECT_CONTEXT) { 2730 amdgpu_ring_write(ring, 2731 PACKET3(PACKET3_SET_CONTEXT_REG, 2732 ext->reg_count)); 2733 amdgpu_ring_write(ring, ext->reg_index - 2734 PACKET3_SET_CONTEXT_REG_START); 2735 for (i = 0; i < ext->reg_count; i++) 2736 amdgpu_ring_write(ring, ext->extent[i]); 2737 } 2738 } 2739 } 2740 2741 ctx_reg_offset = 2742 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 2743 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2744 amdgpu_ring_write(ring, ctx_reg_offset); 2745 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 2746 2747 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2748 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2749 2750 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2751 amdgpu_ring_write(ring, 0); 2752 2753 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2754 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2755 amdgpu_ring_write(ring, 0x8000); 2756 amdgpu_ring_write(ring, 0x8000); 2757 2758 amdgpu_ring_commit(ring); 2759 2760 /* submit cs packet to copy state 0 to next available state */ 2761 ring = &adev->gfx.gfx_ring[1]; 2762 r = amdgpu_ring_alloc(ring, 2); 2763 if (r) { 2764 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2765 return r; 2766 } 2767 2768 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2769 amdgpu_ring_write(ring, 0); 2770 2771 amdgpu_ring_commit(ring); 2772 2773 return 0; 2774 } 2775 2776 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2777 CP_PIPE_ID pipe) 2778 { 2779 u32 tmp; 2780 2781 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 2782 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2783 2784 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 2785 } 2786 2787 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2788 struct amdgpu_ring *ring) 2789 { 2790 u32 tmp; 2791 2792 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2793 if (ring->use_doorbell) { 2794 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2795 DOORBELL_OFFSET, ring->doorbell_index); 2796 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2797 DOORBELL_EN, 1); 2798 } else { 2799 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2800 DOORBELL_EN, 0); 2801 } 2802 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2803 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2804 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2805 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2806 2807 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2808 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2809 } 2810 2811 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 2812 { 2813 struct amdgpu_ring *ring; 2814 u32 tmp; 2815 u32 rb_bufsz; 2816 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2817 u32 i; 2818 2819 /* Set the write pointer delay */ 2820 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2821 2822 /* set the RB to use vmid 0 */ 2823 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2824 2825 /* Init gfx ring 0 for pipe 0 */ 2826 mutex_lock(&adev->srbm_mutex); 2827 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2828 mutex_unlock(&adev->srbm_mutex); 2829 /* Set ring buffer size */ 2830 ring = &adev->gfx.gfx_ring[0]; 2831 rb_bufsz = order_base_2(ring->ring_size / 8); 2832 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2833 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2834 #ifdef __BIG_ENDIAN 2835 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2836 #endif 2837 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2838 2839 /* Initialize the ring buffer's write pointers */ 2840 ring->wptr = 0; 2841 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2842 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2843 2844 /* set the wb address wether it's enabled or not */ 2845 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2846 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2847 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2848 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2849 2850 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2851 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2852 lower_32_bits(wptr_gpu_addr)); 2853 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2854 upper_32_bits(wptr_gpu_addr)); 2855 2856 mdelay(1); 2857 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2858 2859 rb_addr = ring->gpu_addr >> 8; 2860 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2861 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2862 2863 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 2864 2865 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2866 2867 /* Init gfx ring 1 for pipe 1 */ 2868 mutex_lock(&adev->srbm_mutex); 2869 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 2870 mutex_unlock(&adev->srbm_mutex); 2871 ring = &adev->gfx.gfx_ring[1]; 2872 rb_bufsz = order_base_2(ring->ring_size / 8); 2873 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 2874 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 2875 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2876 /* Initialize the ring buffer's write pointers */ 2877 ring->wptr = 0; 2878 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2879 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 2880 /* Set the wb address wether it's enabled or not */ 2881 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2882 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2883 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2884 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2885 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2886 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2887 lower_32_bits(wptr_gpu_addr)); 2888 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2889 upper_32_bits(wptr_gpu_addr)); 2890 2891 mdelay(1); 2892 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2893 2894 rb_addr = ring->gpu_addr >> 8; 2895 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 2896 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 2897 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 2898 2899 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2900 2901 /* Switch to pipe 0 */ 2902 mutex_lock(&adev->srbm_mutex); 2903 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2904 mutex_unlock(&adev->srbm_mutex); 2905 2906 /* start the ring */ 2907 gfx_v10_0_cp_gfx_start(adev); 2908 2909 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2910 ring = &adev->gfx.gfx_ring[i]; 2911 ring->sched.ready = true; 2912 } 2913 2914 return 0; 2915 } 2916 2917 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2918 { 2919 int i; 2920 2921 if (enable) { 2922 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2923 } else { 2924 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2925 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 2926 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2927 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2928 adev->gfx.compute_ring[i].sched.ready = false; 2929 adev->gfx.kiq.ring.sched.ready = false; 2930 } 2931 udelay(50); 2932 } 2933 2934 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2935 { 2936 const struct gfx_firmware_header_v1_0 *mec_hdr; 2937 const __le32 *fw_data; 2938 unsigned i; 2939 u32 tmp; 2940 u32 usec_timeout = 50000; /* Wait for 50 ms */ 2941 2942 if (!adev->gfx.mec_fw) 2943 return -EINVAL; 2944 2945 gfx_v10_0_cp_compute_enable(adev, false); 2946 2947 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2948 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2949 2950 fw_data = (const __le32 *) 2951 (adev->gfx.mec_fw->data + 2952 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2953 2954 /* Trigger an invalidation of the L1 instruction caches */ 2955 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2956 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2957 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2958 2959 /* Wait for invalidation complete */ 2960 for (i = 0; i < usec_timeout; i++) { 2961 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2962 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2963 INVALIDATE_CACHE_COMPLETE)) 2964 break; 2965 udelay(1); 2966 } 2967 2968 if (i >= usec_timeout) { 2969 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2970 return -EINVAL; 2971 } 2972 2973 if (amdgpu_emu_mode == 1) 2974 adev->nbio.funcs->hdp_flush(adev, NULL); 2975 2976 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 2977 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2978 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2979 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2980 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2981 2982 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 2983 0xFFFFF000); 2984 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2985 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2986 2987 /* MEC1 */ 2988 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 2989 2990 for (i = 0; i < mec_hdr->jt_size; i++) 2991 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2992 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2993 2994 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 2995 2996 /* 2997 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 2998 * different microcode than MEC1. 2999 */ 3000 3001 return 0; 3002 } 3003 3004 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 3005 { 3006 uint32_t tmp; 3007 struct amdgpu_device *adev = ring->adev; 3008 3009 /* tell RLC which is KIQ queue */ 3010 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3011 tmp &= 0xffffff00; 3012 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3013 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3014 tmp |= 0x80; 3015 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3016 } 3017 3018 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 3019 { 3020 struct amdgpu_device *adev = ring->adev; 3021 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3022 uint64_t hqd_gpu_addr, wb_gpu_addr; 3023 uint32_t tmp; 3024 uint32_t rb_bufsz; 3025 3026 /* set up gfx hqd wptr */ 3027 mqd->cp_gfx_hqd_wptr = 0; 3028 mqd->cp_gfx_hqd_wptr_hi = 0; 3029 3030 /* set the pointer to the MQD */ 3031 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 3032 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3033 3034 /* set up mqd control */ 3035 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 3036 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3037 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3038 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3039 mqd->cp_gfx_mqd_control = tmp; 3040 3041 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3042 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 3043 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3044 mqd->cp_gfx_hqd_vmid = 0; 3045 3046 /* set up default queue priority level 3047 * 0x0 = low priority, 0x1 = high priority */ 3048 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 3049 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3050 mqd->cp_gfx_hqd_queue_priority = tmp; 3051 3052 /* set up time quantum */ 3053 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 3054 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3055 mqd->cp_gfx_hqd_quantum = tmp; 3056 3057 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3058 hqd_gpu_addr = ring->gpu_addr >> 8; 3059 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3060 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3061 3062 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3063 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3064 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3065 mqd->cp_gfx_hqd_rptr_addr_hi = 3066 upper_32_bits(wb_gpu_addr) & 0xffff; 3067 3068 /* set up rb_wptr_poll addr */ 3069 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3070 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3071 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3072 3073 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3074 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 3075 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 3076 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3077 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3078 #ifdef __BIG_ENDIAN 3079 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3080 #endif 3081 mqd->cp_gfx_hqd_cntl = tmp; 3082 3083 /* set up cp_doorbell_control */ 3084 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3085 if (ring->use_doorbell) { 3086 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3087 DOORBELL_OFFSET, ring->doorbell_index); 3088 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3089 DOORBELL_EN, 1); 3090 } else 3091 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3092 DOORBELL_EN, 0); 3093 mqd->cp_rb_doorbell_control = tmp; 3094 3095 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3096 ring->wptr = 0; 3097 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 3098 3099 /* active the queue */ 3100 mqd->cp_gfx_hqd_active = 1; 3101 3102 return 0; 3103 } 3104 3105 #ifdef BRING_UP_DEBUG 3106 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3107 { 3108 struct amdgpu_device *adev = ring->adev; 3109 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3110 3111 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3112 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3113 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3114 3115 /* set GFX_MQD_BASE */ 3116 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3117 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3118 3119 /* set GFX_MQD_CONTROL */ 3120 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3121 3122 /* set GFX_HQD_VMID to 0 */ 3123 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3124 3125 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 3126 mqd->cp_gfx_hqd_queue_priority); 3127 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3128 3129 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3130 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3131 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3132 3133 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3134 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3135 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3136 3137 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3138 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3139 3140 /* set RB_WPTR_POLL_ADDR */ 3141 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3142 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3143 3144 /* set RB_DOORBELL_CONTROL */ 3145 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3146 3147 /* active the queue */ 3148 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3149 3150 return 0; 3151 } 3152 #endif 3153 3154 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 3155 { 3156 struct amdgpu_device *adev = ring->adev; 3157 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3158 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3159 3160 if (!adev->in_gpu_reset && !adev->in_suspend) { 3161 memset((void *)mqd, 0, sizeof(*mqd)); 3162 mutex_lock(&adev->srbm_mutex); 3163 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3164 gfx_v10_0_gfx_mqd_init(ring); 3165 #ifdef BRING_UP_DEBUG 3166 gfx_v10_0_gfx_queue_init_register(ring); 3167 #endif 3168 nv_grbm_select(adev, 0, 0, 0, 0); 3169 mutex_unlock(&adev->srbm_mutex); 3170 if (adev->gfx.me.mqd_backup[mqd_idx]) 3171 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3172 } else if (adev->in_gpu_reset) { 3173 /* reset mqd with the backup copy */ 3174 if (adev->gfx.me.mqd_backup[mqd_idx]) 3175 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3176 /* reset the ring */ 3177 ring->wptr = 0; 3178 adev->wb.wb[ring->wptr_offs] = 0; 3179 amdgpu_ring_clear_ring(ring); 3180 #ifdef BRING_UP_DEBUG 3181 mutex_lock(&adev->srbm_mutex); 3182 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3183 gfx_v10_0_gfx_queue_init_register(ring); 3184 nv_grbm_select(adev, 0, 0, 0, 0); 3185 mutex_unlock(&adev->srbm_mutex); 3186 #endif 3187 } else { 3188 amdgpu_ring_clear_ring(ring); 3189 } 3190 3191 return 0; 3192 } 3193 3194 #ifndef BRING_UP_DEBUG 3195 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 3196 { 3197 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3198 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3199 int r, i; 3200 3201 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3202 return -EINVAL; 3203 3204 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3205 adev->gfx.num_gfx_rings); 3206 if (r) { 3207 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3208 return r; 3209 } 3210 3211 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3212 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3213 3214 r = amdgpu_ring_test_ring(kiq_ring); 3215 if (r) { 3216 DRM_ERROR("kfq enable failed\n"); 3217 kiq_ring->sched.ready = false; 3218 } 3219 return r; 3220 } 3221 #endif 3222 3223 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3224 { 3225 int r, i; 3226 struct amdgpu_ring *ring; 3227 3228 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3229 ring = &adev->gfx.gfx_ring[i]; 3230 3231 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3232 if (unlikely(r != 0)) 3233 goto done; 3234 3235 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3236 if (!r) { 3237 r = gfx_v10_0_gfx_init_queue(ring); 3238 amdgpu_bo_kunmap(ring->mqd_obj); 3239 ring->mqd_ptr = NULL; 3240 } 3241 amdgpu_bo_unreserve(ring->mqd_obj); 3242 if (r) 3243 goto done; 3244 } 3245 #ifndef BRING_UP_DEBUG 3246 r = gfx_v10_0_kiq_enable_kgq(adev); 3247 if (r) 3248 goto done; 3249 #endif 3250 r = gfx_v10_0_cp_gfx_start(adev); 3251 if (r) 3252 goto done; 3253 3254 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3255 ring = &adev->gfx.gfx_ring[i]; 3256 ring->sched.ready = true; 3257 } 3258 done: 3259 return r; 3260 } 3261 3262 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 3263 { 3264 struct amdgpu_device *adev = ring->adev; 3265 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3266 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3267 uint32_t tmp; 3268 3269 mqd->header = 0xC0310800; 3270 mqd->compute_pipelinestat_enable = 0x00000001; 3271 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3272 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3273 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3274 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3275 mqd->compute_misc_reserved = 0x00000003; 3276 3277 eop_base_addr = ring->eop_gpu_addr >> 8; 3278 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3279 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3280 3281 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3282 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3283 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3284 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 3285 3286 mqd->cp_hqd_eop_control = tmp; 3287 3288 /* enable doorbell? */ 3289 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3290 3291 if (ring->use_doorbell) { 3292 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3293 DOORBELL_OFFSET, ring->doorbell_index); 3294 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3295 DOORBELL_EN, 1); 3296 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3297 DOORBELL_SOURCE, 0); 3298 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3299 DOORBELL_HIT, 0); 3300 } else { 3301 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3302 DOORBELL_EN, 0); 3303 } 3304 3305 mqd->cp_hqd_pq_doorbell_control = tmp; 3306 3307 /* disable the queue if it's active */ 3308 ring->wptr = 0; 3309 mqd->cp_hqd_dequeue_request = 0; 3310 mqd->cp_hqd_pq_rptr = 0; 3311 mqd->cp_hqd_pq_wptr_lo = 0; 3312 mqd->cp_hqd_pq_wptr_hi = 0; 3313 3314 /* set the pointer to the MQD */ 3315 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3316 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3317 3318 /* set MQD vmid to 0 */ 3319 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3320 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3321 mqd->cp_mqd_control = tmp; 3322 3323 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3324 hqd_gpu_addr = ring->gpu_addr >> 8; 3325 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3326 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3327 3328 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3329 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3330 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3331 (order_base_2(ring->ring_size / 4) - 1)); 3332 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3333 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3334 #ifdef __BIG_ENDIAN 3335 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3336 #endif 3337 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3338 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3339 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3340 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3341 mqd->cp_hqd_pq_control = tmp; 3342 3343 /* set the wb address whether it's enabled or not */ 3344 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3345 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3346 mqd->cp_hqd_pq_rptr_report_addr_hi = 3347 upper_32_bits(wb_gpu_addr) & 0xffff; 3348 3349 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3350 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3351 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3352 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3353 3354 tmp = 0; 3355 /* enable the doorbell if requested */ 3356 if (ring->use_doorbell) { 3357 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3358 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3359 DOORBELL_OFFSET, ring->doorbell_index); 3360 3361 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3362 DOORBELL_EN, 1); 3363 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3364 DOORBELL_SOURCE, 0); 3365 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3366 DOORBELL_HIT, 0); 3367 } 3368 3369 mqd->cp_hqd_pq_doorbell_control = tmp; 3370 3371 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3372 ring->wptr = 0; 3373 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3374 3375 /* set the vmid for the queue */ 3376 mqd->cp_hqd_vmid = 0; 3377 3378 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3379 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3380 mqd->cp_hqd_persistent_state = tmp; 3381 3382 /* set MIN_IB_AVAIL_SIZE */ 3383 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3384 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3385 mqd->cp_hqd_ib_control = tmp; 3386 3387 /* activate the queue */ 3388 mqd->cp_hqd_active = 1; 3389 3390 return 0; 3391 } 3392 3393 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 3394 { 3395 struct amdgpu_device *adev = ring->adev; 3396 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3397 int j; 3398 3399 /* disable wptr polling */ 3400 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3401 3402 /* write the EOP addr */ 3403 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3404 mqd->cp_hqd_eop_base_addr_lo); 3405 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3406 mqd->cp_hqd_eop_base_addr_hi); 3407 3408 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3409 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 3410 mqd->cp_hqd_eop_control); 3411 3412 /* enable doorbell? */ 3413 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3414 mqd->cp_hqd_pq_doorbell_control); 3415 3416 /* disable the queue if it's active */ 3417 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3418 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3419 for (j = 0; j < adev->usec_timeout; j++) { 3420 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3421 break; 3422 udelay(1); 3423 } 3424 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3425 mqd->cp_hqd_dequeue_request); 3426 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 3427 mqd->cp_hqd_pq_rptr); 3428 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3429 mqd->cp_hqd_pq_wptr_lo); 3430 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3431 mqd->cp_hqd_pq_wptr_hi); 3432 } 3433 3434 /* set the pointer to the MQD */ 3435 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 3436 mqd->cp_mqd_base_addr_lo); 3437 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3438 mqd->cp_mqd_base_addr_hi); 3439 3440 /* set MQD vmid to 0 */ 3441 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 3442 mqd->cp_mqd_control); 3443 3444 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3445 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 3446 mqd->cp_hqd_pq_base_lo); 3447 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 3448 mqd->cp_hqd_pq_base_hi); 3449 3450 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3451 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 3452 mqd->cp_hqd_pq_control); 3453 3454 /* set the wb address whether it's enabled or not */ 3455 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3456 mqd->cp_hqd_pq_rptr_report_addr_lo); 3457 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3458 mqd->cp_hqd_pq_rptr_report_addr_hi); 3459 3460 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3461 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3462 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3463 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3464 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3465 3466 /* enable the doorbell if requested */ 3467 if (ring->use_doorbell) { 3468 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3469 (adev->doorbell_index.kiq * 2) << 2); 3470 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3471 (adev->doorbell_index.userqueue_end * 2) << 2); 3472 } 3473 3474 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3475 mqd->cp_hqd_pq_doorbell_control); 3476 3477 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3478 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3479 mqd->cp_hqd_pq_wptr_lo); 3480 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3481 mqd->cp_hqd_pq_wptr_hi); 3482 3483 /* set the vmid for the queue */ 3484 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3485 3486 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3487 mqd->cp_hqd_persistent_state); 3488 3489 /* activate the queue */ 3490 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 3491 mqd->cp_hqd_active); 3492 3493 if (ring->use_doorbell) 3494 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3495 3496 return 0; 3497 } 3498 3499 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 3500 { 3501 struct amdgpu_device *adev = ring->adev; 3502 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3503 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3504 3505 gfx_v10_0_kiq_setting(ring); 3506 3507 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3508 /* reset MQD to a clean status */ 3509 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3510 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3511 3512 /* reset ring buffer */ 3513 ring->wptr = 0; 3514 amdgpu_ring_clear_ring(ring); 3515 3516 mutex_lock(&adev->srbm_mutex); 3517 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3518 gfx_v10_0_kiq_init_register(ring); 3519 nv_grbm_select(adev, 0, 0, 0, 0); 3520 mutex_unlock(&adev->srbm_mutex); 3521 } else { 3522 memset((void *)mqd, 0, sizeof(*mqd)); 3523 mutex_lock(&adev->srbm_mutex); 3524 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3525 gfx_v10_0_compute_mqd_init(ring); 3526 gfx_v10_0_kiq_init_register(ring); 3527 nv_grbm_select(adev, 0, 0, 0, 0); 3528 mutex_unlock(&adev->srbm_mutex); 3529 3530 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3531 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3532 } 3533 3534 return 0; 3535 } 3536 3537 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 3538 { 3539 struct amdgpu_device *adev = ring->adev; 3540 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3541 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3542 3543 if (!adev->in_gpu_reset && !adev->in_suspend) { 3544 memset((void *)mqd, 0, sizeof(*mqd)); 3545 mutex_lock(&adev->srbm_mutex); 3546 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3547 gfx_v10_0_compute_mqd_init(ring); 3548 nv_grbm_select(adev, 0, 0, 0, 0); 3549 mutex_unlock(&adev->srbm_mutex); 3550 3551 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3552 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3553 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3554 /* reset MQD to a clean status */ 3555 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3556 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3557 3558 /* reset ring buffer */ 3559 ring->wptr = 0; 3560 amdgpu_ring_clear_ring(ring); 3561 } else { 3562 amdgpu_ring_clear_ring(ring); 3563 } 3564 3565 return 0; 3566 } 3567 3568 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 3569 { 3570 struct amdgpu_ring *ring; 3571 int r; 3572 3573 ring = &adev->gfx.kiq.ring; 3574 3575 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3576 if (unlikely(r != 0)) 3577 return r; 3578 3579 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3580 if (unlikely(r != 0)) 3581 return r; 3582 3583 gfx_v10_0_kiq_init_queue(ring); 3584 amdgpu_bo_kunmap(ring->mqd_obj); 3585 ring->mqd_ptr = NULL; 3586 amdgpu_bo_unreserve(ring->mqd_obj); 3587 ring->sched.ready = true; 3588 return 0; 3589 } 3590 3591 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 3592 { 3593 struct amdgpu_ring *ring = NULL; 3594 int r = 0, i; 3595 3596 gfx_v10_0_cp_compute_enable(adev, true); 3597 3598 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3599 ring = &adev->gfx.compute_ring[i]; 3600 3601 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3602 if (unlikely(r != 0)) 3603 goto done; 3604 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3605 if (!r) { 3606 r = gfx_v10_0_kcq_init_queue(ring); 3607 amdgpu_bo_kunmap(ring->mqd_obj); 3608 ring->mqd_ptr = NULL; 3609 } 3610 amdgpu_bo_unreserve(ring->mqd_obj); 3611 if (r) 3612 goto done; 3613 } 3614 3615 r = amdgpu_gfx_enable_kcq(adev); 3616 done: 3617 return r; 3618 } 3619 3620 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 3621 { 3622 int r, i; 3623 struct amdgpu_ring *ring; 3624 3625 if (!(adev->flags & AMD_IS_APU)) 3626 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3627 3628 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3629 /* legacy firmware loading */ 3630 r = gfx_v10_0_cp_gfx_load_microcode(adev); 3631 if (r) 3632 return r; 3633 3634 r = gfx_v10_0_cp_compute_load_microcode(adev); 3635 if (r) 3636 return r; 3637 } 3638 3639 r = gfx_v10_0_kiq_resume(adev); 3640 if (r) 3641 return r; 3642 3643 r = gfx_v10_0_kcq_resume(adev); 3644 if (r) 3645 return r; 3646 3647 if (!amdgpu_async_gfx_ring) { 3648 r = gfx_v10_0_cp_gfx_resume(adev); 3649 if (r) 3650 return r; 3651 } else { 3652 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 3653 if (r) 3654 return r; 3655 } 3656 3657 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3658 ring = &adev->gfx.gfx_ring[i]; 3659 DRM_INFO("gfx %d ring me %d pipe %d q %d\n", 3660 i, ring->me, ring->pipe, ring->queue); 3661 r = amdgpu_ring_test_ring(ring); 3662 if (r) { 3663 ring->sched.ready = false; 3664 return r; 3665 } 3666 } 3667 3668 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3669 ring = &adev->gfx.compute_ring[i]; 3670 ring->sched.ready = true; 3671 DRM_INFO("compute ring %d mec %d pipe %d q %d\n", 3672 i, ring->me, ring->pipe, ring->queue); 3673 r = amdgpu_ring_test_ring(ring); 3674 if (r) 3675 ring->sched.ready = false; 3676 } 3677 3678 return 0; 3679 } 3680 3681 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 3682 { 3683 gfx_v10_0_cp_gfx_enable(adev, enable); 3684 gfx_v10_0_cp_compute_enable(adev, enable); 3685 } 3686 3687 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 3688 { 3689 uint32_t data, pattern = 0xDEADBEEF; 3690 3691 /* check if mmVGT_ESGS_RING_SIZE_UMD 3692 * has been remapped to mmVGT_ESGS_RING_SIZE */ 3693 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 3694 3695 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 3696 3697 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 3698 3699 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 3700 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 3701 return true; 3702 } else { 3703 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 3704 return false; 3705 } 3706 } 3707 3708 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 3709 { 3710 uint32_t data; 3711 3712 /* initialize cam_index to 0 3713 * index will auto-inc after each data writting */ 3714 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 3715 3716 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 3717 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 3718 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3719 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 3720 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3721 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3722 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3723 3724 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 3725 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 3726 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3727 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 3728 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3729 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3730 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3731 3732 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 3733 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 3734 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3735 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 3736 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3737 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3738 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3739 3740 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 3741 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 3742 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3743 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 3744 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3745 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3746 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3747 3748 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 3749 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 3750 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3751 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 3752 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3753 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3754 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3755 3756 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 3757 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 3758 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3759 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 3760 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3761 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3762 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3763 3764 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 3765 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 3766 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3767 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 3768 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3769 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3770 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3771 } 3772 3773 static int gfx_v10_0_hw_init(void *handle) 3774 { 3775 int r; 3776 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3777 3778 r = gfx_v10_0_csb_vram_pin(adev); 3779 if (r) 3780 return r; 3781 3782 if (!amdgpu_emu_mode) 3783 gfx_v10_0_init_golden_registers(adev); 3784 3785 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3786 /** 3787 * For gfx 10, rlc firmware loading relies on smu firmware is 3788 * loaded firstly, so in direct type, it has to load smc ucode 3789 * here before rlc. 3790 */ 3791 r = smu_load_microcode(&adev->smu); 3792 if (r) 3793 return r; 3794 3795 r = smu_check_fw_status(&adev->smu); 3796 if (r) { 3797 pr_err("SMC firmware status is not correct\n"); 3798 return r; 3799 } 3800 } 3801 3802 /* if GRBM CAM not remapped, set up the remapping */ 3803 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 3804 gfx_v10_0_setup_grbm_cam_remapping(adev); 3805 3806 gfx_v10_0_constants_init(adev); 3807 3808 r = gfx_v10_0_rlc_resume(adev); 3809 if (r) 3810 return r; 3811 3812 /* 3813 * init golden registers and rlc resume may override some registers, 3814 * reconfig them here 3815 */ 3816 gfx_v10_0_tcp_harvest(adev); 3817 3818 r = gfx_v10_0_cp_resume(adev); 3819 if (r) 3820 return r; 3821 3822 return r; 3823 } 3824 3825 #ifndef BRING_UP_DEBUG 3826 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 3827 { 3828 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3829 struct amdgpu_ring *kiq_ring = &kiq->ring; 3830 int i; 3831 3832 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3833 return -EINVAL; 3834 3835 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 3836 adev->gfx.num_gfx_rings)) 3837 return -ENOMEM; 3838 3839 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3840 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 3841 PREEMPT_QUEUES, 0, 0); 3842 3843 return amdgpu_ring_test_ring(kiq_ring); 3844 } 3845 #endif 3846 3847 static int gfx_v10_0_hw_fini(void *handle) 3848 { 3849 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3850 int r; 3851 3852 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3853 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3854 #ifndef BRING_UP_DEBUG 3855 if (amdgpu_async_gfx_ring) { 3856 r = gfx_v10_0_kiq_disable_kgq(adev); 3857 if (r) 3858 DRM_ERROR("KGQ disable failed\n"); 3859 } 3860 #endif 3861 if (amdgpu_gfx_disable_kcq(adev)) 3862 DRM_ERROR("KCQ disable failed\n"); 3863 if (amdgpu_sriov_vf(adev)) { 3864 pr_debug("For SRIOV client, shouldn't do anything.\n"); 3865 return 0; 3866 } 3867 gfx_v10_0_cp_enable(adev, false); 3868 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3869 gfx_v10_0_csb_vram_unpin(adev); 3870 3871 return 0; 3872 } 3873 3874 static int gfx_v10_0_suspend(void *handle) 3875 { 3876 return gfx_v10_0_hw_fini(handle); 3877 } 3878 3879 static int gfx_v10_0_resume(void *handle) 3880 { 3881 return gfx_v10_0_hw_init(handle); 3882 } 3883 3884 static bool gfx_v10_0_is_idle(void *handle) 3885 { 3886 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3887 3888 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3889 GRBM_STATUS, GUI_ACTIVE)) 3890 return false; 3891 else 3892 return true; 3893 } 3894 3895 static int gfx_v10_0_wait_for_idle(void *handle) 3896 { 3897 unsigned i; 3898 u32 tmp; 3899 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3900 3901 for (i = 0; i < adev->usec_timeout; i++) { 3902 /* read MC_STATUS */ 3903 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 3904 GRBM_STATUS__GUI_ACTIVE_MASK; 3905 3906 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3907 return 0; 3908 udelay(1); 3909 } 3910 return -ETIMEDOUT; 3911 } 3912 3913 static int gfx_v10_0_soft_reset(void *handle) 3914 { 3915 u32 grbm_soft_reset = 0; 3916 u32 tmp; 3917 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3918 3919 /* GRBM_STATUS */ 3920 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3921 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3922 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3923 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 3924 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 3925 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK 3926 | GRBM_STATUS__BCI_BUSY_MASK)) { 3927 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3928 GRBM_SOFT_RESET, SOFT_RESET_CP, 3929 1); 3930 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3931 GRBM_SOFT_RESET, SOFT_RESET_GFX, 3932 1); 3933 } 3934 3935 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3936 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3937 GRBM_SOFT_RESET, SOFT_RESET_CP, 3938 1); 3939 } 3940 3941 /* GRBM_STATUS2 */ 3942 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3943 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3944 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3945 GRBM_SOFT_RESET, SOFT_RESET_RLC, 3946 1); 3947 3948 if (grbm_soft_reset) { 3949 /* stop the rlc */ 3950 gfx_v10_0_rlc_stop(adev); 3951 3952 /* Disable GFX parsing/prefetching */ 3953 gfx_v10_0_cp_gfx_enable(adev, false); 3954 3955 /* Disable MEC parsing/prefetching */ 3956 gfx_v10_0_cp_compute_enable(adev, false); 3957 3958 if (grbm_soft_reset) { 3959 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3960 tmp |= grbm_soft_reset; 3961 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3962 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3963 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3964 3965 udelay(50); 3966 3967 tmp &= ~grbm_soft_reset; 3968 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3969 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3970 } 3971 3972 /* Wait a little for things to settle down */ 3973 udelay(50); 3974 } 3975 return 0; 3976 } 3977 3978 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3979 { 3980 uint64_t clock; 3981 3982 mutex_lock(&adev->gfx.gpu_clock_mutex); 3983 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3984 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3985 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3986 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3987 return clock; 3988 } 3989 3990 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3991 uint32_t vmid, 3992 uint32_t gds_base, uint32_t gds_size, 3993 uint32_t gws_base, uint32_t gws_size, 3994 uint32_t oa_base, uint32_t oa_size) 3995 { 3996 struct amdgpu_device *adev = ring->adev; 3997 3998 /* GDS Base */ 3999 gfx_v10_0_write_data_to_reg(ring, 0, false, 4000 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4001 gds_base); 4002 4003 /* GDS Size */ 4004 gfx_v10_0_write_data_to_reg(ring, 0, false, 4005 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4006 gds_size); 4007 4008 /* GWS */ 4009 gfx_v10_0_write_data_to_reg(ring, 0, false, 4010 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4011 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4012 4013 /* OA */ 4014 gfx_v10_0_write_data_to_reg(ring, 0, false, 4015 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4016 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4017 } 4018 4019 static int gfx_v10_0_early_init(void *handle) 4020 { 4021 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4022 4023 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS; 4024 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 4025 4026 gfx_v10_0_set_kiq_pm4_funcs(adev); 4027 gfx_v10_0_set_ring_funcs(adev); 4028 gfx_v10_0_set_irq_funcs(adev); 4029 gfx_v10_0_set_gds_init(adev); 4030 gfx_v10_0_set_rlc_funcs(adev); 4031 4032 return 0; 4033 } 4034 4035 static int gfx_v10_0_late_init(void *handle) 4036 { 4037 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4038 int r; 4039 4040 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4041 if (r) 4042 return r; 4043 4044 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4045 if (r) 4046 return r; 4047 4048 return 0; 4049 } 4050 4051 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 4052 { 4053 uint32_t rlc_cntl; 4054 4055 /* if RLC is not enabled, do nothing */ 4056 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4057 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4058 } 4059 4060 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 4061 { 4062 uint32_t data; 4063 unsigned i; 4064 4065 data = RLC_SAFE_MODE__CMD_MASK; 4066 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4067 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4068 4069 /* wait for RLC_SAFE_MODE */ 4070 for (i = 0; i < adev->usec_timeout; i++) { 4071 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4072 break; 4073 udelay(1); 4074 } 4075 } 4076 4077 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 4078 { 4079 uint32_t data; 4080 4081 data = RLC_SAFE_MODE__CMD_MASK; 4082 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4083 } 4084 4085 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4086 bool enable) 4087 { 4088 uint32_t data, def; 4089 4090 /* It is disabled by HW by default */ 4091 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4092 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4093 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4094 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4095 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4096 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4097 4098 /* only for Vega10 & Raven1 */ 4099 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4100 4101 if (def != data) 4102 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4103 4104 /* MGLS is a global flag to control all MGLS in GFX */ 4105 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4106 /* 2 - RLC memory Light sleep */ 4107 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4108 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4109 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4110 if (def != data) 4111 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4112 } 4113 /* 3 - CP memory Light sleep */ 4114 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4115 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4116 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4117 if (def != data) 4118 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4119 } 4120 } 4121 } else { 4122 /* 1 - MGCG_OVERRIDE */ 4123 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4124 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4125 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4126 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4127 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4128 if (def != data) 4129 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4130 4131 /* 2 - disable MGLS in RLC */ 4132 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4133 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4134 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4135 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4136 } 4137 4138 /* 3 - disable MGLS in CP */ 4139 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4140 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4141 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4142 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4143 } 4144 } 4145 } 4146 4147 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 4148 bool enable) 4149 { 4150 uint32_t data, def; 4151 4152 /* Enable 3D CGCG/CGLS */ 4153 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 4154 /* write cmd to clear cgcg/cgls ov */ 4155 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4156 /* unset CGCG override */ 4157 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4158 /* update CGCG and CGLS override bits */ 4159 if (def != data) 4160 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4161 /* enable 3Dcgcg FSM(0x0000363f) */ 4162 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4163 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4164 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4165 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4166 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4167 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4168 if (def != data) 4169 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4170 4171 /* set IDLE_POLL_COUNT(0x00900100) */ 4172 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4173 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4174 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4175 if (def != data) 4176 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4177 } else { 4178 /* Disable CGCG/CGLS */ 4179 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4180 /* disable cgcg, cgls should be disabled */ 4181 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4182 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4183 /* disable cgcg and cgls in FSM */ 4184 if (def != data) 4185 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4186 } 4187 } 4188 4189 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4190 bool enable) 4191 { 4192 uint32_t def, data; 4193 4194 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4195 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4196 /* unset CGCG override */ 4197 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4198 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4199 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4200 else 4201 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4202 /* update CGCG and CGLS override bits */ 4203 if (def != data) 4204 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4205 4206 /* enable cgcg FSM(0x0000363F) */ 4207 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4208 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4209 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4210 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4211 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4212 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4213 if (def != data) 4214 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4215 4216 /* set IDLE_POLL_COUNT(0x00900100) */ 4217 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4218 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4219 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4220 if (def != data) 4221 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4222 } else { 4223 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4224 /* reset CGCG/CGLS bits */ 4225 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4226 /* disable cgcg and cgls in FSM */ 4227 if (def != data) 4228 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4229 } 4230 } 4231 4232 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4233 bool enable) 4234 { 4235 amdgpu_gfx_rlc_enter_safe_mode(adev); 4236 4237 if (enable) { 4238 /* CGCG/CGLS should be enabled after MGCG/MGLS 4239 * === MGCG + MGLS === 4240 */ 4241 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4242 /* === CGCG /CGLS for GFX 3D Only === */ 4243 gfx_v10_0_update_3d_clock_gating(adev, enable); 4244 /* === CGCG + CGLS === */ 4245 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4246 } else { 4247 /* CGCG/CGLS should be disabled before MGCG/MGLS 4248 * === CGCG + CGLS === 4249 */ 4250 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4251 /* === CGCG /CGLS for GFX 3D Only === */ 4252 gfx_v10_0_update_3d_clock_gating(adev, enable); 4253 /* === MGCG + MGLS === */ 4254 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4255 } 4256 4257 if (adev->cg_flags & 4258 (AMD_CG_SUPPORT_GFX_MGCG | 4259 AMD_CG_SUPPORT_GFX_CGLS | 4260 AMD_CG_SUPPORT_GFX_CGCG | 4261 AMD_CG_SUPPORT_GFX_CGLS | 4262 AMD_CG_SUPPORT_GFX_3D_CGCG | 4263 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4264 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 4265 4266 amdgpu_gfx_rlc_exit_safe_mode(adev); 4267 4268 return 0; 4269 } 4270 4271 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 4272 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 4273 .set_safe_mode = gfx_v10_0_set_safe_mode, 4274 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 4275 .init = gfx_v10_0_rlc_init, 4276 .get_csb_size = gfx_v10_0_get_csb_size, 4277 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 4278 .resume = gfx_v10_0_rlc_resume, 4279 .stop = gfx_v10_0_rlc_stop, 4280 .reset = gfx_v10_0_rlc_reset, 4281 .start = gfx_v10_0_rlc_start 4282 }; 4283 4284 static int gfx_v10_0_set_powergating_state(void *handle, 4285 enum amd_powergating_state state) 4286 { 4287 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4288 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 4289 switch (adev->asic_type) { 4290 case CHIP_NAVI10: 4291 case CHIP_NAVI14: 4292 if (!enable) { 4293 amdgpu_gfx_off_ctrl(adev, false); 4294 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 4295 } else 4296 amdgpu_gfx_off_ctrl(adev, true); 4297 break; 4298 default: 4299 break; 4300 } 4301 return 0; 4302 } 4303 4304 static int gfx_v10_0_set_clockgating_state(void *handle, 4305 enum amd_clockgating_state state) 4306 { 4307 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4308 4309 switch (adev->asic_type) { 4310 case CHIP_NAVI10: 4311 case CHIP_NAVI14: 4312 case CHIP_NAVI12: 4313 gfx_v10_0_update_gfx_clock_gating(adev, 4314 state == AMD_CG_STATE_GATE ? true : false); 4315 break; 4316 default: 4317 break; 4318 } 4319 return 0; 4320 } 4321 4322 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 4323 { 4324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4325 int data; 4326 4327 /* AMD_CG_SUPPORT_GFX_MGCG */ 4328 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4329 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4330 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4331 4332 /* AMD_CG_SUPPORT_GFX_CGCG */ 4333 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4334 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4335 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4336 4337 /* AMD_CG_SUPPORT_GFX_CGLS */ 4338 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4339 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4340 4341 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 4342 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4343 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 4344 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 4345 4346 /* AMD_CG_SUPPORT_GFX_CP_LS */ 4347 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4348 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 4349 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 4350 4351 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4352 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4353 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4354 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4355 4356 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4357 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4358 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4359 } 4360 4361 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4362 { 4363 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 4364 } 4365 4366 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4367 { 4368 struct amdgpu_device *adev = ring->adev; 4369 u64 wptr; 4370 4371 /* XXX check if swapping is necessary on BE */ 4372 if (ring->use_doorbell) { 4373 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 4374 } else { 4375 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 4376 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 4377 } 4378 4379 return wptr; 4380 } 4381 4382 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4383 { 4384 struct amdgpu_device *adev = ring->adev; 4385 4386 if (ring->use_doorbell) { 4387 /* XXX check if swapping is necessary on BE */ 4388 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4389 WDOORBELL64(ring->doorbell_index, ring->wptr); 4390 } else { 4391 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4392 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 4393 } 4394 } 4395 4396 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4397 { 4398 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 4399 } 4400 4401 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4402 { 4403 u64 wptr; 4404 4405 /* XXX check if swapping is necessary on BE */ 4406 if (ring->use_doorbell) 4407 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 4408 else 4409 BUG(); 4410 return wptr; 4411 } 4412 4413 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4414 { 4415 struct amdgpu_device *adev = ring->adev; 4416 4417 /* XXX check if swapping is necessary on BE */ 4418 if (ring->use_doorbell) { 4419 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4420 WDOORBELL64(ring->doorbell_index, ring->wptr); 4421 } else { 4422 BUG(); /* only DOORBELL method supported on gfx10 now */ 4423 } 4424 } 4425 4426 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4427 { 4428 struct amdgpu_device *adev = ring->adev; 4429 u32 ref_and_mask, reg_mem_engine; 4430 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4431 4432 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4433 switch (ring->me) { 4434 case 1: 4435 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4436 break; 4437 case 2: 4438 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4439 break; 4440 default: 4441 return; 4442 } 4443 reg_mem_engine = 0; 4444 } else { 4445 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4446 reg_mem_engine = 1; /* pfp */ 4447 } 4448 4449 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4450 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4451 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4452 ref_and_mask, ref_and_mask, 0x20); 4453 } 4454 4455 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4456 struct amdgpu_job *job, 4457 struct amdgpu_ib *ib, 4458 uint32_t flags) 4459 { 4460 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4461 u32 header, control = 0; 4462 4463 if (ib->flags & AMDGPU_IB_FLAG_CE) 4464 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 4465 else 4466 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4467 4468 control |= ib->length_dw | (vmid << 24); 4469 4470 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 4471 control |= INDIRECT_BUFFER_PRE_ENB(1); 4472 4473 if (flags & AMDGPU_IB_PREEMPTED) 4474 control |= INDIRECT_BUFFER_PRE_RESUME(1); 4475 4476 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 4477 gfx_v10_0_ring_emit_de_meta(ring, 4478 flags & AMDGPU_IB_PREEMPTED ? true : false); 4479 } 4480 4481 amdgpu_ring_write(ring, header); 4482 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4483 amdgpu_ring_write(ring, 4484 #ifdef __BIG_ENDIAN 4485 (2 << 0) | 4486 #endif 4487 lower_32_bits(ib->gpu_addr)); 4488 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4489 amdgpu_ring_write(ring, control); 4490 } 4491 4492 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4493 struct amdgpu_job *job, 4494 struct amdgpu_ib *ib, 4495 uint32_t flags) 4496 { 4497 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4498 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4499 4500 /* Currently, there is a high possibility to get wave ID mismatch 4501 * between ME and GDS, leading to a hw deadlock, because ME generates 4502 * different wave IDs than the GDS expects. This situation happens 4503 * randomly when at least 5 compute pipes use GDS ordered append. 4504 * The wave IDs generated by ME are also wrong after suspend/resume. 4505 * Those are probably bugs somewhere else in the kernel driver. 4506 * 4507 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 4508 * GDS to 0 for this ring (me/pipe). 4509 */ 4510 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 4511 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4512 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 4513 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 4514 } 4515 4516 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4517 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4518 amdgpu_ring_write(ring, 4519 #ifdef __BIG_ENDIAN 4520 (2 << 0) | 4521 #endif 4522 lower_32_bits(ib->gpu_addr)); 4523 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4524 amdgpu_ring_write(ring, control); 4525 } 4526 4527 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4528 u64 seq, unsigned flags) 4529 { 4530 struct amdgpu_device *adev = ring->adev; 4531 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4532 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4533 4534 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 4535 if (adev->pdev->device == 0x50) 4536 int_sel = false; 4537 4538 /* RELEASE_MEM - flush caches, send int */ 4539 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4540 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4541 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4542 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 4543 PACKET3_RELEASE_MEM_GCR_GLM_WB | 4544 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4545 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4546 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4547 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4548 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4549 4550 /* 4551 * the address should be Qword aligned if 64bit write, Dword 4552 * aligned if only send 32bit data low (discard data high) 4553 */ 4554 if (write64bit) 4555 BUG_ON(addr & 0x7); 4556 else 4557 BUG_ON(addr & 0x3); 4558 amdgpu_ring_write(ring, lower_32_bits(addr)); 4559 amdgpu_ring_write(ring, upper_32_bits(addr)); 4560 amdgpu_ring_write(ring, lower_32_bits(seq)); 4561 amdgpu_ring_write(ring, upper_32_bits(seq)); 4562 amdgpu_ring_write(ring, 0); 4563 } 4564 4565 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4566 { 4567 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4568 uint32_t seq = ring->fence_drv.sync_seq; 4569 uint64_t addr = ring->fence_drv.gpu_addr; 4570 4571 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4572 upper_32_bits(addr), seq, 0xffffffff, 4); 4573 } 4574 4575 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4576 unsigned vmid, uint64_t pd_addr) 4577 { 4578 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4579 4580 /* compute doesn't have PFP */ 4581 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4582 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4583 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4584 amdgpu_ring_write(ring, 0x0); 4585 } 4586 } 4587 4588 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4589 u64 seq, unsigned int flags) 4590 { 4591 struct amdgpu_device *adev = ring->adev; 4592 4593 /* we only allocate 32bit for each seq wb address */ 4594 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4595 4596 /* write fence seq to the "addr" */ 4597 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4598 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4599 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4600 amdgpu_ring_write(ring, lower_32_bits(addr)); 4601 amdgpu_ring_write(ring, upper_32_bits(addr)); 4602 amdgpu_ring_write(ring, lower_32_bits(seq)); 4603 4604 if (flags & AMDGPU_FENCE_FLAG_INT) { 4605 /* set register to trigger INT */ 4606 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4607 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4608 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4609 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 4610 amdgpu_ring_write(ring, 0); 4611 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4612 } 4613 } 4614 4615 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 4616 { 4617 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4618 amdgpu_ring_write(ring, 0); 4619 } 4620 4621 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 4622 { 4623 uint32_t dw2 = 0; 4624 4625 if (amdgpu_mcbp) 4626 gfx_v10_0_ring_emit_ce_meta(ring, 4627 flags & AMDGPU_IB_PREEMPTED ? true : false); 4628 4629 gfx_v10_0_ring_emit_tmz(ring, true); 4630 4631 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4632 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4633 /* set load_global_config & load_global_uconfig */ 4634 dw2 |= 0x8001; 4635 /* set load_cs_sh_regs */ 4636 dw2 |= 0x01000000; 4637 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4638 dw2 |= 0x10002; 4639 4640 /* set load_ce_ram if preamble presented */ 4641 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 4642 dw2 |= 0x10000000; 4643 } else { 4644 /* still load_ce_ram if this is the first time preamble presented 4645 * although there is no context switch happens. 4646 */ 4647 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 4648 dw2 |= 0x10000000; 4649 } 4650 4651 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4652 amdgpu_ring_write(ring, dw2); 4653 amdgpu_ring_write(ring, 0); 4654 } 4655 4656 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 4657 { 4658 unsigned ret; 4659 4660 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4661 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 4662 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 4663 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 4664 ret = ring->wptr & ring->buf_mask; 4665 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 4666 4667 return ret; 4668 } 4669 4670 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 4671 { 4672 unsigned cur; 4673 BUG_ON(offset > ring->buf_mask); 4674 BUG_ON(ring->ring[offset] != 0x55aa55aa); 4675 4676 cur = (ring->wptr - 1) & ring->buf_mask; 4677 if (likely(cur > offset)) 4678 ring->ring[offset] = cur - offset; 4679 else 4680 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 4681 } 4682 4683 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 4684 { 4685 int i, r = 0; 4686 struct amdgpu_device *adev = ring->adev; 4687 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4688 struct amdgpu_ring *kiq_ring = &kiq->ring; 4689 4690 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4691 return -EINVAL; 4692 4693 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) 4694 return -ENOMEM; 4695 4696 /* assert preemption condition */ 4697 amdgpu_ring_set_preempt_cond_exec(ring, false); 4698 4699 /* assert IB preemption, emit the trailing fence */ 4700 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4701 ring->trail_fence_gpu_addr, 4702 ++ring->trail_seq); 4703 amdgpu_ring_commit(kiq_ring); 4704 4705 /* poll the trailing fence */ 4706 for (i = 0; i < adev->usec_timeout; i++) { 4707 if (ring->trail_seq == 4708 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4709 break; 4710 udelay(1); 4711 } 4712 4713 if (i >= adev->usec_timeout) { 4714 r = -EINVAL; 4715 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4716 } 4717 4718 /* deassert preemption condition */ 4719 amdgpu_ring_set_preempt_cond_exec(ring, true); 4720 return r; 4721 } 4722 4723 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 4724 { 4725 struct amdgpu_device *adev = ring->adev; 4726 struct v10_ce_ib_state ce_payload = {0}; 4727 uint64_t csa_addr; 4728 int cnt; 4729 4730 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 4731 csa_addr = amdgpu_csa_vaddr(ring->adev); 4732 4733 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4734 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 4735 WRITE_DATA_DST_SEL(8) | 4736 WR_CONFIRM) | 4737 WRITE_DATA_CACHE_POLICY(0)); 4738 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4739 offsetof(struct v10_gfx_meta_data, ce_payload))); 4740 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4741 offsetof(struct v10_gfx_meta_data, ce_payload))); 4742 4743 if (resume) 4744 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4745 offsetof(struct v10_gfx_meta_data, 4746 ce_payload), 4747 sizeof(ce_payload) >> 2); 4748 else 4749 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 4750 sizeof(ce_payload) >> 2); 4751 } 4752 4753 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 4754 { 4755 struct amdgpu_device *adev = ring->adev; 4756 struct v10_de_ib_state de_payload = {0}; 4757 uint64_t csa_addr, gds_addr; 4758 int cnt; 4759 4760 csa_addr = amdgpu_csa_vaddr(ring->adev); 4761 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 4762 PAGE_SIZE); 4763 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 4764 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 4765 4766 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 4767 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4768 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 4769 WRITE_DATA_DST_SEL(8) | 4770 WR_CONFIRM) | 4771 WRITE_DATA_CACHE_POLICY(0)); 4772 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4773 offsetof(struct v10_gfx_meta_data, de_payload))); 4774 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4775 offsetof(struct v10_gfx_meta_data, de_payload))); 4776 4777 if (resume) 4778 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4779 offsetof(struct v10_gfx_meta_data, 4780 de_payload), 4781 sizeof(de_payload) >> 2); 4782 else 4783 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 4784 sizeof(de_payload) >> 2); 4785 } 4786 4787 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 4788 { 4789 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4790 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 4791 } 4792 4793 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 4794 { 4795 struct amdgpu_device *adev = ring->adev; 4796 4797 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4798 amdgpu_ring_write(ring, 0 | /* src: register*/ 4799 (5 << 8) | /* dst: memory */ 4800 (1 << 20)); /* write confirm */ 4801 amdgpu_ring_write(ring, reg); 4802 amdgpu_ring_write(ring, 0); 4803 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4804 adev->virt.reg_val_offs * 4)); 4805 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4806 adev->virt.reg_val_offs * 4)); 4807 } 4808 4809 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 4810 uint32_t val) 4811 { 4812 uint32_t cmd = 0; 4813 4814 switch (ring->funcs->type) { 4815 case AMDGPU_RING_TYPE_GFX: 4816 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4817 break; 4818 case AMDGPU_RING_TYPE_KIQ: 4819 cmd = (1 << 16); /* no inc addr */ 4820 break; 4821 default: 4822 cmd = WR_CONFIRM; 4823 break; 4824 } 4825 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4826 amdgpu_ring_write(ring, cmd); 4827 amdgpu_ring_write(ring, reg); 4828 amdgpu_ring_write(ring, 0); 4829 amdgpu_ring_write(ring, val); 4830 } 4831 4832 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4833 uint32_t val, uint32_t mask) 4834 { 4835 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4836 } 4837 4838 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4839 uint32_t reg0, uint32_t reg1, 4840 uint32_t ref, uint32_t mask) 4841 { 4842 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4843 struct amdgpu_device *adev = ring->adev; 4844 bool fw_version_ok = false; 4845 4846 fw_version_ok = adev->gfx.cp_fw_write_wait; 4847 4848 if (fw_version_ok) 4849 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4850 ref, mask, 0x20); 4851 else 4852 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 4853 ref, mask); 4854 } 4855 4856 static void 4857 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4858 uint32_t me, uint32_t pipe, 4859 enum amdgpu_interrupt_state state) 4860 { 4861 uint32_t cp_int_cntl, cp_int_cntl_reg; 4862 4863 if (!me) { 4864 switch (pipe) { 4865 case 0: 4866 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 4867 break; 4868 case 1: 4869 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 4870 break; 4871 default: 4872 DRM_DEBUG("invalid pipe %d\n", pipe); 4873 return; 4874 } 4875 } else { 4876 DRM_DEBUG("invalid me %d\n", me); 4877 return; 4878 } 4879 4880 switch (state) { 4881 case AMDGPU_IRQ_STATE_DISABLE: 4882 cp_int_cntl = RREG32(cp_int_cntl_reg); 4883 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4884 TIME_STAMP_INT_ENABLE, 0); 4885 WREG32(cp_int_cntl_reg, cp_int_cntl); 4886 break; 4887 case AMDGPU_IRQ_STATE_ENABLE: 4888 cp_int_cntl = RREG32(cp_int_cntl_reg); 4889 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4890 TIME_STAMP_INT_ENABLE, 1); 4891 WREG32(cp_int_cntl_reg, cp_int_cntl); 4892 break; 4893 default: 4894 break; 4895 } 4896 } 4897 4898 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4899 int me, int pipe, 4900 enum amdgpu_interrupt_state state) 4901 { 4902 u32 mec_int_cntl, mec_int_cntl_reg; 4903 4904 /* 4905 * amdgpu controls only the first MEC. That's why this function only 4906 * handles the setting of interrupts for this specific MEC. All other 4907 * pipes' interrupts are set by amdkfd. 4908 */ 4909 4910 if (me == 1) { 4911 switch (pipe) { 4912 case 0: 4913 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4914 break; 4915 case 1: 4916 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 4917 break; 4918 case 2: 4919 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 4920 break; 4921 case 3: 4922 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 4923 break; 4924 default: 4925 DRM_DEBUG("invalid pipe %d\n", pipe); 4926 return; 4927 } 4928 } else { 4929 DRM_DEBUG("invalid me %d\n", me); 4930 return; 4931 } 4932 4933 switch (state) { 4934 case AMDGPU_IRQ_STATE_DISABLE: 4935 mec_int_cntl = RREG32(mec_int_cntl_reg); 4936 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4937 TIME_STAMP_INT_ENABLE, 0); 4938 WREG32(mec_int_cntl_reg, mec_int_cntl); 4939 break; 4940 case AMDGPU_IRQ_STATE_ENABLE: 4941 mec_int_cntl = RREG32(mec_int_cntl_reg); 4942 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4943 TIME_STAMP_INT_ENABLE, 1); 4944 WREG32(mec_int_cntl_reg, mec_int_cntl); 4945 break; 4946 default: 4947 break; 4948 } 4949 } 4950 4951 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4952 struct amdgpu_irq_src *src, 4953 unsigned type, 4954 enum amdgpu_interrupt_state state) 4955 { 4956 switch (type) { 4957 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4958 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4959 break; 4960 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4961 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4962 break; 4963 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4964 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4965 break; 4966 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4967 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4968 break; 4969 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4970 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4971 break; 4972 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4973 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4974 break; 4975 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4976 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4977 break; 4978 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4979 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4980 break; 4981 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4982 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4983 break; 4984 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4985 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4986 break; 4987 default: 4988 break; 4989 } 4990 return 0; 4991 } 4992 4993 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 4994 struct amdgpu_irq_src *source, 4995 struct amdgpu_iv_entry *entry) 4996 { 4997 int i; 4998 u8 me_id, pipe_id, queue_id; 4999 struct amdgpu_ring *ring; 5000 5001 DRM_DEBUG("IH: CP EOP\n"); 5002 me_id = (entry->ring_id & 0x0c) >> 2; 5003 pipe_id = (entry->ring_id & 0x03) >> 0; 5004 queue_id = (entry->ring_id & 0x70) >> 4; 5005 5006 switch (me_id) { 5007 case 0: 5008 if (pipe_id == 0) 5009 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5010 else 5011 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5012 break; 5013 case 1: 5014 case 2: 5015 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5016 ring = &adev->gfx.compute_ring[i]; 5017 /* Per-queue interrupt is supported for MEC starting from VI. 5018 * The interrupt can only be enabled/disabled per pipe instead of per queue. 5019 */ 5020 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 5021 amdgpu_fence_process(ring); 5022 } 5023 break; 5024 } 5025 return 0; 5026 } 5027 5028 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5029 struct amdgpu_irq_src *source, 5030 unsigned type, 5031 enum amdgpu_interrupt_state state) 5032 { 5033 switch (state) { 5034 case AMDGPU_IRQ_STATE_DISABLE: 5035 case AMDGPU_IRQ_STATE_ENABLE: 5036 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5037 PRIV_REG_INT_ENABLE, 5038 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5039 break; 5040 default: 5041 break; 5042 } 5043 5044 return 0; 5045 } 5046 5047 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5048 struct amdgpu_irq_src *source, 5049 unsigned type, 5050 enum amdgpu_interrupt_state state) 5051 { 5052 switch (state) { 5053 case AMDGPU_IRQ_STATE_DISABLE: 5054 case AMDGPU_IRQ_STATE_ENABLE: 5055 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5056 PRIV_INSTR_INT_ENABLE, 5057 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5058 default: 5059 break; 5060 } 5061 5062 return 0; 5063 } 5064 5065 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 5066 struct amdgpu_iv_entry *entry) 5067 { 5068 u8 me_id, pipe_id, queue_id; 5069 struct amdgpu_ring *ring; 5070 int i; 5071 5072 me_id = (entry->ring_id & 0x0c) >> 2; 5073 pipe_id = (entry->ring_id & 0x03) >> 0; 5074 queue_id = (entry->ring_id & 0x70) >> 4; 5075 5076 switch (me_id) { 5077 case 0: 5078 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5079 ring = &adev->gfx.gfx_ring[i]; 5080 /* we only enabled 1 gfx queue per pipe for now */ 5081 if (ring->me == me_id && ring->pipe == pipe_id) 5082 drm_sched_fault(&ring->sched); 5083 } 5084 break; 5085 case 1: 5086 case 2: 5087 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5088 ring = &adev->gfx.compute_ring[i]; 5089 if (ring->me == me_id && ring->pipe == pipe_id && 5090 ring->queue == queue_id) 5091 drm_sched_fault(&ring->sched); 5092 } 5093 break; 5094 default: 5095 BUG(); 5096 } 5097 } 5098 5099 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 5100 struct amdgpu_irq_src *source, 5101 struct amdgpu_iv_entry *entry) 5102 { 5103 DRM_ERROR("Illegal register access in command stream\n"); 5104 gfx_v10_0_handle_priv_fault(adev, entry); 5105 return 0; 5106 } 5107 5108 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 5109 struct amdgpu_irq_src *source, 5110 struct amdgpu_iv_entry *entry) 5111 { 5112 DRM_ERROR("Illegal instruction in command stream\n"); 5113 gfx_v10_0_handle_priv_fault(adev, entry); 5114 return 0; 5115 } 5116 5117 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 5118 struct amdgpu_irq_src *src, 5119 unsigned int type, 5120 enum amdgpu_interrupt_state state) 5121 { 5122 uint32_t tmp, target; 5123 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5124 5125 if (ring->me == 1) 5126 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5127 else 5128 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 5129 target += ring->pipe; 5130 5131 switch (type) { 5132 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 5133 if (state == AMDGPU_IRQ_STATE_DISABLE) { 5134 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5135 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5136 GENERIC2_INT_ENABLE, 0); 5137 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5138 5139 tmp = RREG32(target); 5140 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 5141 GENERIC2_INT_ENABLE, 0); 5142 WREG32(target, tmp); 5143 } else { 5144 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5145 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5146 GENERIC2_INT_ENABLE, 1); 5147 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5148 5149 tmp = RREG32(target); 5150 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 5151 GENERIC2_INT_ENABLE, 1); 5152 WREG32(target, tmp); 5153 } 5154 break; 5155 default: 5156 BUG(); /* kiq only support GENERIC2_INT now */ 5157 break; 5158 } 5159 return 0; 5160 } 5161 5162 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 5163 struct amdgpu_irq_src *source, 5164 struct amdgpu_iv_entry *entry) 5165 { 5166 u8 me_id, pipe_id, queue_id; 5167 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5168 5169 me_id = (entry->ring_id & 0x0c) >> 2; 5170 pipe_id = (entry->ring_id & 0x03) >> 0; 5171 queue_id = (entry->ring_id & 0x70) >> 4; 5172 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 5173 me_id, pipe_id, queue_id); 5174 5175 amdgpu_fence_process(ring); 5176 return 0; 5177 } 5178 5179 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 5180 .name = "gfx_v10_0", 5181 .early_init = gfx_v10_0_early_init, 5182 .late_init = gfx_v10_0_late_init, 5183 .sw_init = gfx_v10_0_sw_init, 5184 .sw_fini = gfx_v10_0_sw_fini, 5185 .hw_init = gfx_v10_0_hw_init, 5186 .hw_fini = gfx_v10_0_hw_fini, 5187 .suspend = gfx_v10_0_suspend, 5188 .resume = gfx_v10_0_resume, 5189 .is_idle = gfx_v10_0_is_idle, 5190 .wait_for_idle = gfx_v10_0_wait_for_idle, 5191 .soft_reset = gfx_v10_0_soft_reset, 5192 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 5193 .set_powergating_state = gfx_v10_0_set_powergating_state, 5194 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 5195 }; 5196 5197 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 5198 .type = AMDGPU_RING_TYPE_GFX, 5199 .align_mask = 0xff, 5200 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5201 .support_64bit_ptrs = true, 5202 .vmhub = AMDGPU_GFXHUB_0, 5203 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 5204 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 5205 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 5206 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5207 5 + /* COND_EXEC */ 5208 7 + /* PIPELINE_SYNC */ 5209 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5210 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5211 2 + /* VM_FLUSH */ 5212 8 + /* FENCE for VM_FLUSH */ 5213 20 + /* GDS switch */ 5214 4 + /* double SWITCH_BUFFER, 5215 * the first COND_EXEC jump to the place 5216 * just prior to this double SWITCH_BUFFER 5217 */ 5218 5 + /* COND_EXEC */ 5219 7 + /* HDP_flush */ 5220 4 + /* VGT_flush */ 5221 14 + /* CE_META */ 5222 31 + /* DE_META */ 5223 3 + /* CNTX_CTRL */ 5224 5 + /* HDP_INVL */ 5225 8 + 8 + /* FENCE x2 */ 5226 2, /* SWITCH_BUFFER */ 5227 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 5228 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 5229 .emit_fence = gfx_v10_0_ring_emit_fence, 5230 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5231 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5232 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5233 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5234 .test_ring = gfx_v10_0_ring_test_ring, 5235 .test_ib = gfx_v10_0_ring_test_ib, 5236 .insert_nop = amdgpu_ring_insert_nop, 5237 .pad_ib = amdgpu_ring_generic_pad_ib, 5238 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 5239 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 5240 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 5241 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 5242 .preempt_ib = gfx_v10_0_ring_preempt_ib, 5243 .emit_tmz = gfx_v10_0_ring_emit_tmz, 5244 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5245 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5246 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5247 }; 5248 5249 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 5250 .type = AMDGPU_RING_TYPE_COMPUTE, 5251 .align_mask = 0xff, 5252 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5253 .support_64bit_ptrs = true, 5254 .vmhub = AMDGPU_GFXHUB_0, 5255 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5256 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5257 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5258 .emit_frame_size = 5259 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5260 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5261 5 + /* hdp invalidate */ 5262 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5263 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5264 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5265 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5266 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 5267 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5268 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5269 .emit_fence = gfx_v10_0_ring_emit_fence, 5270 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5271 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5272 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5273 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5274 .test_ring = gfx_v10_0_ring_test_ring, 5275 .test_ib = gfx_v10_0_ring_test_ib, 5276 .insert_nop = amdgpu_ring_insert_nop, 5277 .pad_ib = amdgpu_ring_generic_pad_ib, 5278 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5279 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5280 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5281 }; 5282 5283 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 5284 .type = AMDGPU_RING_TYPE_KIQ, 5285 .align_mask = 0xff, 5286 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5287 .support_64bit_ptrs = true, 5288 .vmhub = AMDGPU_GFXHUB_0, 5289 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5290 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5291 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5292 .emit_frame_size = 5293 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5294 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5295 5 + /*hdp invalidate */ 5296 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5297 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5298 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5299 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5300 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5301 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5302 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5303 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 5304 .test_ring = gfx_v10_0_ring_test_ring, 5305 .test_ib = gfx_v10_0_ring_test_ib, 5306 .insert_nop = amdgpu_ring_insert_nop, 5307 .pad_ib = amdgpu_ring_generic_pad_ib, 5308 .emit_rreg = gfx_v10_0_ring_emit_rreg, 5309 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5310 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5311 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5312 }; 5313 5314 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 5315 { 5316 int i; 5317 5318 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 5319 5320 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5321 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 5322 5323 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5324 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 5325 } 5326 5327 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 5328 .set = gfx_v10_0_set_eop_interrupt_state, 5329 .process = gfx_v10_0_eop_irq, 5330 }; 5331 5332 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 5333 .set = gfx_v10_0_set_priv_reg_fault_state, 5334 .process = gfx_v10_0_priv_reg_irq, 5335 }; 5336 5337 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 5338 .set = gfx_v10_0_set_priv_inst_fault_state, 5339 .process = gfx_v10_0_priv_inst_irq, 5340 }; 5341 5342 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 5343 .set = gfx_v10_0_kiq_set_interrupt_state, 5344 .process = gfx_v10_0_kiq_irq, 5345 }; 5346 5347 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 5348 { 5349 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5350 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 5351 5352 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 5353 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 5354 5355 adev->gfx.priv_reg_irq.num_types = 1; 5356 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 5357 5358 adev->gfx.priv_inst_irq.num_types = 1; 5359 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 5360 } 5361 5362 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 5363 { 5364 switch (adev->asic_type) { 5365 case CHIP_NAVI10: 5366 case CHIP_NAVI14: 5367 case CHIP_NAVI12: 5368 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 5369 break; 5370 default: 5371 break; 5372 } 5373 } 5374 5375 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 5376 { 5377 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 5378 adev->gfx.config.max_sh_per_se * 5379 adev->gfx.config.max_shader_engines; 5380 5381 adev->gds.gds_size = 0x10000; 5382 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 5383 adev->gds.gws_size = 64; 5384 adev->gds.oa_size = 16; 5385 } 5386 5387 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5388 u32 bitmap) 5389 { 5390 u32 data; 5391 5392 if (!bitmap) 5393 return; 5394 5395 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5396 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5397 5398 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 5399 } 5400 5401 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5402 { 5403 u32 data, wgp_bitmask; 5404 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 5405 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 5406 5407 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5408 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5409 5410 wgp_bitmask = 5411 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5412 5413 return (~data) & wgp_bitmask; 5414 } 5415 5416 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5417 { 5418 u32 wgp_idx, wgp_active_bitmap; 5419 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5420 5421 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5422 cu_active_bitmap = 0; 5423 5424 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5425 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5426 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5427 if (wgp_active_bitmap & (1 << wgp_idx)) 5428 cu_active_bitmap |= cu_bitmap_per_wgp; 5429 } 5430 5431 return cu_active_bitmap; 5432 } 5433 5434 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 5435 struct amdgpu_cu_info *cu_info) 5436 { 5437 int i, j, k, counter, active_cu_number = 0; 5438 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5439 unsigned disable_masks[4 * 2]; 5440 5441 if (!adev || !cu_info) 5442 return -EINVAL; 5443 5444 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5445 5446 mutex_lock(&adev->grbm_idx_mutex); 5447 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5448 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5449 mask = 1; 5450 ao_bitmap = 0; 5451 counter = 0; 5452 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5453 if (i < 4 && j < 2) 5454 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 5455 adev, disable_masks[i * 2 + j]); 5456 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 5457 cu_info->bitmap[i][j] = bitmap; 5458 5459 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5460 if (bitmap & mask) { 5461 if (counter < adev->gfx.config.max_cu_per_sh) 5462 ao_bitmap |= mask; 5463 counter++; 5464 } 5465 mask <<= 1; 5466 } 5467 active_cu_number += counter; 5468 if (i < 2 && j < 2) 5469 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5470 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5471 } 5472 } 5473 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5474 mutex_unlock(&adev->grbm_idx_mutex); 5475 5476 cu_info->number = active_cu_number; 5477 cu_info->ao_cu_mask = ao_cu_mask; 5478 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5479 5480 return 0; 5481 } 5482 5483 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 5484 { 5485 .type = AMD_IP_BLOCK_TYPE_GFX, 5486 .major = 10, 5487 .minor = 0, 5488 .rev = 0, 5489 .funcs = &gfx_v10_0_ip_funcs, 5490 }; 5491