1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 114 115 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 121 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 125 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 127 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 129 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 131 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 134 135 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 137 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 139 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 141 #define mmCP_HYP_CE_UCODE_DATA 0x5819 142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 143 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 145 #define mmCP_HYP_ME_UCODE_DATA 0x5817 146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 147 148 #define mmCPG_PSP_DEBUG 0x5c10 149 #define mmCPG_PSP_DEBUG_BASE_IDX 1 150 #define mmCPC_PSP_DEBUG 0x5c11 151 #define mmCPC_PSP_DEBUG_BASE_IDX 1 152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 154 155 //CC_GC_SA_UNIT_DISABLE 156 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 160 //GC_USER_SA_UNIT_DISABLE 161 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //PA_SC_ENHANCE_3 166 #define mmPA_SC_ENHANCE_3 0x1085 167 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 170 171 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 173 174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 178 179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 181 182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 184 185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 187 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 191 192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 203 204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 206 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 210 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 217 218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 224 225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 231 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 238 239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 245 246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 252 253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 259 260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 266 267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 273 274 static const struct soc15_reg_golden golden_settings_gc_10_1[] = { 275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 315 }; 316 317 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = { 318 /* Pending on emulation bring up */ 319 }; 320 321 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = { 322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1374 }; 1375 1376 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = { 1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1415 }; 1416 1417 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = { 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1460 }; 1461 1462 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = { 1463 /* Pending on emulation bring up */ 1464 }; 1465 1466 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = { 1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2087 }; 2088 2089 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = { 2090 /* Pending on emulation bring up */ 2091 }; 2092 2093 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = { 2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3146 }; 3147 3148 static const struct soc15_reg_golden golden_settings_gc_10_3[] = { 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3192 }; 3193 3194 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = { 3195 /* Pending on emulation bring up */ 3196 }; 3197 3198 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = { 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3240 3241 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3243 }; 3244 3245 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = { 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3270 3271 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3273 }; 3274 3275 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = { 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3296 }; 3297 3298 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = { 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3335 }; 3336 3337 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3370 }; 3371 3372 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3407 }; 3408 3409 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = { 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3432 }; 3433 3434 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3457 }; 3458 3459 #define DEFAULT_SH_MEM_CONFIG \ 3460 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3461 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3462 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3463 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3464 3465 /* TODO: pending on golden setting value of gb address config */ 3466 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3467 3468 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3469 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3470 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3471 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3472 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3473 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3474 struct amdgpu_cu_info *cu_info); 3475 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3476 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3477 u32 sh_num, u32 instance, int xcc_id); 3478 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3479 3480 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3481 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3482 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3483 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3484 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3485 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3486 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3487 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3488 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3489 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3490 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3491 uint16_t pasid, uint32_t flush_type, 3492 bool all_hub, uint8_t dst_sel); 3493 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 3494 unsigned int vmid); 3495 3496 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3497 { 3498 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3499 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3500 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3501 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3502 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3503 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3504 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3505 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3506 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3507 } 3508 3509 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3510 struct amdgpu_ring *ring) 3511 { 3512 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3513 uint64_t wptr_addr = ring->wptr_gpu_addr; 3514 uint32_t eng_sel = 0; 3515 3516 switch (ring->funcs->type) { 3517 case AMDGPU_RING_TYPE_COMPUTE: 3518 eng_sel = 0; 3519 break; 3520 case AMDGPU_RING_TYPE_GFX: 3521 eng_sel = 4; 3522 break; 3523 case AMDGPU_RING_TYPE_MES: 3524 eng_sel = 5; 3525 break; 3526 default: 3527 WARN_ON(1); 3528 } 3529 3530 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3531 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3532 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3533 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3534 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3535 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3536 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3537 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3538 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3539 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3540 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3541 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3542 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3543 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3544 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3545 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3546 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3547 } 3548 3549 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3550 struct amdgpu_ring *ring, 3551 enum amdgpu_unmap_queues_action action, 3552 u64 gpu_addr, u64 seq) 3553 { 3554 struct amdgpu_device *adev = kiq_ring->adev; 3555 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3556 3557 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 3558 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 3559 return; 3560 } 3561 3562 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3563 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3564 PACKET3_UNMAP_QUEUES_ACTION(action) | 3565 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3566 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3567 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3568 amdgpu_ring_write(kiq_ring, 3569 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3570 3571 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3572 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3573 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3574 amdgpu_ring_write(kiq_ring, seq); 3575 } else { 3576 amdgpu_ring_write(kiq_ring, 0); 3577 amdgpu_ring_write(kiq_ring, 0); 3578 amdgpu_ring_write(kiq_ring, 0); 3579 } 3580 } 3581 3582 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3583 struct amdgpu_ring *ring, 3584 u64 addr, 3585 u64 seq) 3586 { 3587 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3588 3589 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3590 amdgpu_ring_write(kiq_ring, 3591 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3592 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3593 PACKET3_QUERY_STATUS_COMMAND(2)); 3594 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3595 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3596 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3597 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3598 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3599 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3600 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3601 } 3602 3603 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3604 uint16_t pasid, uint32_t flush_type, 3605 bool all_hub) 3606 { 3607 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3608 } 3609 3610 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3611 .kiq_set_resources = gfx10_kiq_set_resources, 3612 .kiq_map_queues = gfx10_kiq_map_queues, 3613 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3614 .kiq_query_status = gfx10_kiq_query_status, 3615 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3616 .set_resources_size = 8, 3617 .map_queues_size = 7, 3618 .unmap_queues_size = 6, 3619 .query_status_size = 7, 3620 .invalidate_tlbs_size = 2, 3621 }; 3622 3623 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3624 { 3625 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs; 3626 } 3627 3628 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3629 { 3630 switch (adev->ip_versions[GC_HWIP][0]) { 3631 case IP_VERSION(10, 1, 10): 3632 soc15_program_register_sequence(adev, 3633 golden_settings_gc_rlc_spm_10_0_nv10, 3634 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3635 break; 3636 case IP_VERSION(10, 1, 1): 3637 soc15_program_register_sequence(adev, 3638 golden_settings_gc_rlc_spm_10_1_nv14, 3639 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3640 break; 3641 case IP_VERSION(10, 1, 2): 3642 soc15_program_register_sequence(adev, 3643 golden_settings_gc_rlc_spm_10_1_2_nv12, 3644 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3645 break; 3646 default: 3647 break; 3648 } 3649 } 3650 3651 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3652 { 3653 switch (adev->ip_versions[GC_HWIP][0]) { 3654 case IP_VERSION(10, 1, 10): 3655 soc15_program_register_sequence(adev, 3656 golden_settings_gc_10_1, 3657 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3658 soc15_program_register_sequence(adev, 3659 golden_settings_gc_10_0_nv10, 3660 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3661 break; 3662 case IP_VERSION(10, 1, 1): 3663 soc15_program_register_sequence(adev, 3664 golden_settings_gc_10_1_1, 3665 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3666 soc15_program_register_sequence(adev, 3667 golden_settings_gc_10_1_nv14, 3668 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3669 break; 3670 case IP_VERSION(10, 1, 2): 3671 soc15_program_register_sequence(adev, 3672 golden_settings_gc_10_1_2, 3673 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3674 soc15_program_register_sequence(adev, 3675 golden_settings_gc_10_1_2_nv12, 3676 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3677 break; 3678 case IP_VERSION(10, 3, 0): 3679 soc15_program_register_sequence(adev, 3680 golden_settings_gc_10_3, 3681 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3682 soc15_program_register_sequence(adev, 3683 golden_settings_gc_10_3_sienna_cichlid, 3684 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3685 break; 3686 case IP_VERSION(10, 3, 2): 3687 soc15_program_register_sequence(adev, 3688 golden_settings_gc_10_3_2, 3689 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3690 break; 3691 case IP_VERSION(10, 3, 1): 3692 soc15_program_register_sequence(adev, 3693 golden_settings_gc_10_3_vangogh, 3694 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3695 break; 3696 case IP_VERSION(10, 3, 3): 3697 soc15_program_register_sequence(adev, 3698 golden_settings_gc_10_3_3, 3699 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3700 break; 3701 case IP_VERSION(10, 3, 4): 3702 soc15_program_register_sequence(adev, 3703 golden_settings_gc_10_3_4, 3704 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3705 break; 3706 case IP_VERSION(10, 3, 5): 3707 soc15_program_register_sequence(adev, 3708 golden_settings_gc_10_3_5, 3709 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3710 break; 3711 case IP_VERSION(10, 1, 3): 3712 case IP_VERSION(10, 1, 4): 3713 soc15_program_register_sequence(adev, 3714 golden_settings_gc_10_0_cyan_skillfish, 3715 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3716 break; 3717 case IP_VERSION(10, 3, 6): 3718 soc15_program_register_sequence(adev, 3719 golden_settings_gc_10_3_6, 3720 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3721 break; 3722 case IP_VERSION(10, 3, 7): 3723 soc15_program_register_sequence(adev, 3724 golden_settings_gc_10_3_7, 3725 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3726 break; 3727 default: 3728 break; 3729 } 3730 gfx_v10_0_init_spm_golden_registers(adev); 3731 } 3732 3733 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3734 bool wc, uint32_t reg, uint32_t val) 3735 { 3736 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3737 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3738 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3739 amdgpu_ring_write(ring, reg); 3740 amdgpu_ring_write(ring, 0); 3741 amdgpu_ring_write(ring, val); 3742 } 3743 3744 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3745 int mem_space, int opt, uint32_t addr0, 3746 uint32_t addr1, uint32_t ref, uint32_t mask, 3747 uint32_t inv) 3748 { 3749 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3750 amdgpu_ring_write(ring, 3751 /* memory (1) or register (0) */ 3752 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3753 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3754 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3755 WAIT_REG_MEM_ENGINE(eng_sel))); 3756 3757 if (mem_space) 3758 BUG_ON(addr0 & 0x3); /* Dword align */ 3759 amdgpu_ring_write(ring, addr0); 3760 amdgpu_ring_write(ring, addr1); 3761 amdgpu_ring_write(ring, ref); 3762 amdgpu_ring_write(ring, mask); 3763 amdgpu_ring_write(ring, inv); /* poll interval */ 3764 } 3765 3766 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3767 { 3768 struct amdgpu_device *adev = ring->adev; 3769 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3770 uint32_t tmp = 0; 3771 unsigned int i; 3772 int r; 3773 3774 WREG32(scratch, 0xCAFEDEAD); 3775 r = amdgpu_ring_alloc(ring, 3); 3776 if (r) { 3777 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3778 ring->idx, r); 3779 return r; 3780 } 3781 3782 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3783 amdgpu_ring_write(ring, scratch - 3784 PACKET3_SET_UCONFIG_REG_START); 3785 amdgpu_ring_write(ring, 0xDEADBEEF); 3786 amdgpu_ring_commit(ring); 3787 3788 for (i = 0; i < adev->usec_timeout; i++) { 3789 tmp = RREG32(scratch); 3790 if (tmp == 0xDEADBEEF) 3791 break; 3792 if (amdgpu_emu_mode == 1) 3793 msleep(1); 3794 else 3795 udelay(1); 3796 } 3797 3798 if (i >= adev->usec_timeout) 3799 r = -ETIMEDOUT; 3800 3801 return r; 3802 } 3803 3804 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3805 { 3806 struct amdgpu_device *adev = ring->adev; 3807 struct amdgpu_ib ib; 3808 struct dma_fence *f = NULL; 3809 unsigned int index; 3810 uint64_t gpu_addr; 3811 volatile uint32_t *cpu_ptr; 3812 long r; 3813 3814 memset(&ib, 0, sizeof(ib)); 3815 3816 if (ring->is_mes_queue) { 3817 uint32_t padding, offset; 3818 3819 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 3820 padding = amdgpu_mes_ctx_get_offs(ring, 3821 AMDGPU_MES_CTX_PADDING_OFFS); 3822 3823 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 3824 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 3825 3826 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 3827 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 3828 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 3829 } else { 3830 r = amdgpu_device_wb_get(adev, &index); 3831 if (r) 3832 return r; 3833 3834 gpu_addr = adev->wb.gpu_addr + (index * 4); 3835 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3836 cpu_ptr = &adev->wb.wb[index]; 3837 3838 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 3839 if (r) { 3840 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 3841 goto err1; 3842 } 3843 } 3844 3845 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3846 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3847 ib.ptr[2] = lower_32_bits(gpu_addr); 3848 ib.ptr[3] = upper_32_bits(gpu_addr); 3849 ib.ptr[4] = 0xDEADBEEF; 3850 ib.length_dw = 5; 3851 3852 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3853 if (r) 3854 goto err2; 3855 3856 r = dma_fence_wait_timeout(f, false, timeout); 3857 if (r == 0) { 3858 r = -ETIMEDOUT; 3859 goto err2; 3860 } else if (r < 0) { 3861 goto err2; 3862 } 3863 3864 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 3865 r = 0; 3866 else 3867 r = -EINVAL; 3868 err2: 3869 if (!ring->is_mes_queue) 3870 amdgpu_ib_free(adev, &ib, NULL); 3871 dma_fence_put(f); 3872 err1: 3873 if (!ring->is_mes_queue) 3874 amdgpu_device_wb_free(adev, index); 3875 return r; 3876 } 3877 3878 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3879 { 3880 amdgpu_ucode_release(&adev->gfx.pfp_fw); 3881 amdgpu_ucode_release(&adev->gfx.me_fw); 3882 amdgpu_ucode_release(&adev->gfx.ce_fw); 3883 amdgpu_ucode_release(&adev->gfx.rlc_fw); 3884 amdgpu_ucode_release(&adev->gfx.mec_fw); 3885 amdgpu_ucode_release(&adev->gfx.mec2_fw); 3886 3887 kfree(adev->gfx.rlc.register_list_format); 3888 } 3889 3890 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3891 { 3892 adev->gfx.cp_fw_write_wait = false; 3893 3894 switch (adev->ip_versions[GC_HWIP][0]) { 3895 case IP_VERSION(10, 1, 10): 3896 case IP_VERSION(10, 1, 2): 3897 case IP_VERSION(10, 1, 1): 3898 case IP_VERSION(10, 1, 3): 3899 case IP_VERSION(10, 1, 4): 3900 if ((adev->gfx.me_fw_version >= 0x00000046) && 3901 (adev->gfx.me_feature_version >= 27) && 3902 (adev->gfx.pfp_fw_version >= 0x00000068) && 3903 (adev->gfx.pfp_feature_version >= 27) && 3904 (adev->gfx.mec_fw_version >= 0x0000005b) && 3905 (adev->gfx.mec_feature_version >= 27)) 3906 adev->gfx.cp_fw_write_wait = true; 3907 break; 3908 case IP_VERSION(10, 3, 0): 3909 case IP_VERSION(10, 3, 2): 3910 case IP_VERSION(10, 3, 1): 3911 case IP_VERSION(10, 3, 4): 3912 case IP_VERSION(10, 3, 5): 3913 case IP_VERSION(10, 3, 6): 3914 case IP_VERSION(10, 3, 3): 3915 case IP_VERSION(10, 3, 7): 3916 adev->gfx.cp_fw_write_wait = true; 3917 break; 3918 default: 3919 break; 3920 } 3921 3922 if (!adev->gfx.cp_fw_write_wait) 3923 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3924 } 3925 3926 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3927 { 3928 bool ret = false; 3929 3930 switch (adev->pdev->revision) { 3931 case 0xc2: 3932 case 0xc3: 3933 ret = true; 3934 break; 3935 default: 3936 ret = false; 3937 break; 3938 } 3939 3940 return ret; 3941 } 3942 3943 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3944 { 3945 switch (adev->ip_versions[GC_HWIP][0]) { 3946 case IP_VERSION(10, 1, 10): 3947 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3948 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3949 break; 3950 default: 3951 break; 3952 } 3953 } 3954 3955 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3956 { 3957 char fw_name[40]; 3958 char ucode_prefix[30]; 3959 const char *wks = ""; 3960 int err; 3961 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3962 uint16_t version_major; 3963 uint16_t version_minor; 3964 3965 DRM_DEBUG("\n"); 3966 3967 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) && 3968 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00))) 3969 wks = "_wks"; 3970 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 3971 3972 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks); 3973 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 3974 if (err) 3975 goto out; 3976 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 3977 3978 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks); 3979 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 3980 if (err) 3981 goto out; 3982 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 3983 3984 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks); 3985 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 3986 if (err) 3987 goto out; 3988 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 3989 3990 if (!amdgpu_sriov_vf(adev)) { 3991 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); 3992 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 3993 if (err) 3994 goto out; 3995 3996 /* don't validate this firmware. There are apparently firmwares 3997 * in the wild with incorrect size in the header 3998 */ 3999 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4000 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4001 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4002 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4003 if (err) 4004 goto out; 4005 } 4006 4007 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks); 4008 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 4009 if (err) 4010 goto out; 4011 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4012 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4013 4014 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks); 4015 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 4016 if (!err) { 4017 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4018 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4019 } else { 4020 err = 0; 4021 adev->gfx.mec2_fw = NULL; 4022 } 4023 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4024 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4025 4026 gfx_v10_0_check_fw_write_wait(adev); 4027 out: 4028 if (err) { 4029 amdgpu_ucode_release(&adev->gfx.pfp_fw); 4030 amdgpu_ucode_release(&adev->gfx.me_fw); 4031 amdgpu_ucode_release(&adev->gfx.ce_fw); 4032 amdgpu_ucode_release(&adev->gfx.rlc_fw); 4033 amdgpu_ucode_release(&adev->gfx.mec_fw); 4034 amdgpu_ucode_release(&adev->gfx.mec2_fw); 4035 } 4036 4037 gfx_v10_0_check_gfxoff_flag(adev); 4038 4039 return err; 4040 } 4041 4042 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4043 { 4044 u32 count = 0; 4045 const struct cs_section_def *sect = NULL; 4046 const struct cs_extent_def *ext = NULL; 4047 4048 /* begin clear state */ 4049 count += 2; 4050 /* context control state */ 4051 count += 3; 4052 4053 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4054 for (ext = sect->section; ext->extent != NULL; ++ext) { 4055 if (sect->id == SECT_CONTEXT) 4056 count += 2 + ext->reg_count; 4057 else 4058 return 0; 4059 } 4060 } 4061 4062 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4063 count += 3; 4064 /* end clear state */ 4065 count += 2; 4066 /* clear state */ 4067 count += 2; 4068 4069 return count; 4070 } 4071 4072 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4073 volatile u32 *buffer) 4074 { 4075 u32 count = 0, i; 4076 const struct cs_section_def *sect = NULL; 4077 const struct cs_extent_def *ext = NULL; 4078 int ctx_reg_offset; 4079 4080 if (adev->gfx.rlc.cs_data == NULL) 4081 return; 4082 if (buffer == NULL) 4083 return; 4084 4085 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4086 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4087 4088 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4089 buffer[count++] = cpu_to_le32(0x80000000); 4090 buffer[count++] = cpu_to_le32(0x80000000); 4091 4092 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4093 for (ext = sect->section; ext->extent != NULL; ++ext) { 4094 if (sect->id == SECT_CONTEXT) { 4095 buffer[count++] = 4096 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4097 buffer[count++] = cpu_to_le32(ext->reg_index - 4098 PACKET3_SET_CONTEXT_REG_START); 4099 for (i = 0; i < ext->reg_count; i++) 4100 buffer[count++] = cpu_to_le32(ext->extent[i]); 4101 } else { 4102 return; 4103 } 4104 } 4105 } 4106 4107 ctx_reg_offset = 4108 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4109 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4110 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4111 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4112 4113 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4114 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4115 4116 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4117 buffer[count++] = cpu_to_le32(0); 4118 } 4119 4120 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4121 { 4122 /* clear state block */ 4123 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4124 &adev->gfx.rlc.clear_state_gpu_addr, 4125 (void **)&adev->gfx.rlc.cs_ptr); 4126 4127 /* jump table block */ 4128 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4129 &adev->gfx.rlc.cp_table_gpu_addr, 4130 (void **)&adev->gfx.rlc.cp_table_ptr); 4131 } 4132 4133 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4134 { 4135 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4136 4137 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; 4138 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4139 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4140 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4141 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4142 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4143 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4144 switch (adev->ip_versions[GC_HWIP][0]) { 4145 case IP_VERSION(10, 3, 0): 4146 reg_access_ctrl->spare_int = 4147 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4148 break; 4149 default: 4150 reg_access_ctrl->spare_int = 4151 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4152 break; 4153 } 4154 adev->gfx.rlc.rlcg_reg_access_supported = true; 4155 } 4156 4157 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4158 { 4159 const struct cs_section_def *cs_data; 4160 int r; 4161 4162 adev->gfx.rlc.cs_data = gfx10_cs_data; 4163 4164 cs_data = adev->gfx.rlc.cs_data; 4165 4166 if (cs_data) { 4167 /* init clear state block */ 4168 r = amdgpu_gfx_rlc_init_csb(adev); 4169 if (r) 4170 return r; 4171 } 4172 4173 return 0; 4174 } 4175 4176 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4177 { 4178 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4179 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4180 } 4181 4182 static void gfx_v10_0_me_init(struct amdgpu_device *adev) 4183 { 4184 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4185 4186 amdgpu_gfx_graphics_queue_acquire(adev); 4187 } 4188 4189 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4190 { 4191 int r; 4192 u32 *hpd; 4193 const __le32 *fw_data = NULL; 4194 unsigned int fw_size; 4195 u32 *fw = NULL; 4196 size_t mec_hpd_size; 4197 4198 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4199 4200 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4201 4202 /* take ownership of the relevant compute queues */ 4203 amdgpu_gfx_compute_queue_acquire(adev); 4204 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4205 4206 if (mec_hpd_size) { 4207 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4208 AMDGPU_GEM_DOMAIN_GTT, 4209 &adev->gfx.mec.hpd_eop_obj, 4210 &adev->gfx.mec.hpd_eop_gpu_addr, 4211 (void **)&hpd); 4212 if (r) { 4213 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4214 gfx_v10_0_mec_fini(adev); 4215 return r; 4216 } 4217 4218 memset(hpd, 0, mec_hpd_size); 4219 4220 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4221 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4222 } 4223 4224 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4225 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4226 4227 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4228 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4229 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4230 4231 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4232 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4233 &adev->gfx.mec.mec_fw_obj, 4234 &adev->gfx.mec.mec_fw_gpu_addr, 4235 (void **)&fw); 4236 if (r) { 4237 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4238 gfx_v10_0_mec_fini(adev); 4239 return r; 4240 } 4241 4242 memcpy(fw, fw_data, fw_size); 4243 4244 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4245 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4246 } 4247 4248 return 0; 4249 } 4250 4251 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4252 { 4253 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4254 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4255 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4256 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4257 } 4258 4259 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4260 uint32_t thread, uint32_t regno, 4261 uint32_t num, uint32_t *out) 4262 { 4263 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4264 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4265 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4266 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4267 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4268 while (num--) 4269 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4270 } 4271 4272 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4273 { 4274 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4275 * field when performing a select_se_sh so it should be 4276 * zero here 4277 */ 4278 WARN_ON(simd != 0); 4279 4280 /* type 2 wave data */ 4281 dst[(*no_fields)++] = 2; 4282 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4283 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4284 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4285 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4286 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4287 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4288 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4289 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4290 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4291 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4292 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4293 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4294 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4295 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4296 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4297 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4298 } 4299 4300 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4301 uint32_t wave, uint32_t start, 4302 uint32_t size, uint32_t *dst) 4303 { 4304 WARN_ON(simd != 0); 4305 4306 wave_read_regs( 4307 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4308 dst); 4309 } 4310 4311 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4312 uint32_t wave, uint32_t thread, 4313 uint32_t start, uint32_t size, 4314 uint32_t *dst) 4315 { 4316 wave_read_regs( 4317 adev, wave, thread, 4318 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4319 } 4320 4321 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4322 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4323 { 4324 nv_grbm_select(adev, me, pipe, q, vm); 4325 } 4326 4327 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4328 bool enable) 4329 { 4330 uint32_t data, def; 4331 4332 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4333 4334 if (enable) 4335 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4336 else 4337 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4338 4339 if (data != def) 4340 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4341 } 4342 4343 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4344 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4345 .select_se_sh = &gfx_v10_0_select_se_sh, 4346 .read_wave_data = &gfx_v10_0_read_wave_data, 4347 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4348 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4349 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4350 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4351 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4352 }; 4353 4354 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4355 { 4356 u32 gb_addr_config; 4357 4358 switch (adev->ip_versions[GC_HWIP][0]) { 4359 case IP_VERSION(10, 1, 10): 4360 case IP_VERSION(10, 1, 1): 4361 case IP_VERSION(10, 1, 2): 4362 adev->gfx.config.max_hw_contexts = 8; 4363 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4364 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4365 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4366 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4367 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4368 break; 4369 case IP_VERSION(10, 3, 0): 4370 case IP_VERSION(10, 3, 2): 4371 case IP_VERSION(10, 3, 1): 4372 case IP_VERSION(10, 3, 4): 4373 case IP_VERSION(10, 3, 5): 4374 case IP_VERSION(10, 3, 6): 4375 case IP_VERSION(10, 3, 3): 4376 case IP_VERSION(10, 3, 7): 4377 adev->gfx.config.max_hw_contexts = 8; 4378 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4379 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4380 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4381 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4382 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4383 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4384 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4385 break; 4386 case IP_VERSION(10, 1, 3): 4387 case IP_VERSION(10, 1, 4): 4388 adev->gfx.config.max_hw_contexts = 8; 4389 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4390 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4391 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4392 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4393 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4394 break; 4395 default: 4396 BUG(); 4397 break; 4398 } 4399 4400 adev->gfx.config.gb_addr_config = gb_addr_config; 4401 4402 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4403 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4404 GB_ADDR_CONFIG, NUM_PIPES); 4405 4406 adev->gfx.config.max_tile_pipes = 4407 adev->gfx.config.gb_addr_config_fields.num_pipes; 4408 4409 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4410 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4411 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4412 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4413 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4414 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4415 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4416 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4417 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4418 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4419 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4420 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4421 } 4422 4423 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4424 int me, int pipe, int queue) 4425 { 4426 struct amdgpu_ring *ring; 4427 unsigned int irq_type; 4428 unsigned int hw_prio; 4429 4430 ring = &adev->gfx.gfx_ring[ring_id]; 4431 4432 ring->me = me; 4433 ring->pipe = pipe; 4434 ring->queue = queue; 4435 4436 ring->ring_obj = NULL; 4437 ring->use_doorbell = true; 4438 4439 if (!ring_id) 4440 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4441 else 4442 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4443 ring->vm_hub = AMDGPU_GFXHUB(0); 4444 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4445 4446 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4447 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4448 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4449 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4450 hw_prio, NULL); 4451 } 4452 4453 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4454 int mec, int pipe, int queue) 4455 { 4456 unsigned int irq_type; 4457 struct amdgpu_ring *ring; 4458 unsigned int hw_prio; 4459 4460 ring = &adev->gfx.compute_ring[ring_id]; 4461 4462 /* mec0 is me1 */ 4463 ring->me = mec + 1; 4464 ring->pipe = pipe; 4465 ring->queue = queue; 4466 4467 ring->ring_obj = NULL; 4468 ring->use_doorbell = true; 4469 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4470 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4471 + (ring_id * GFX10_MEC_HPD_SIZE); 4472 ring->vm_hub = AMDGPU_GFXHUB(0); 4473 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4474 4475 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4476 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4477 + ring->pipe; 4478 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4479 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4480 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4481 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4482 hw_prio, NULL); 4483 } 4484 4485 static int gfx_v10_0_sw_init(void *handle) 4486 { 4487 int i, j, k, r, ring_id = 0; 4488 struct amdgpu_kiq *kiq; 4489 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4490 4491 switch (adev->ip_versions[GC_HWIP][0]) { 4492 case IP_VERSION(10, 1, 10): 4493 case IP_VERSION(10, 1, 1): 4494 case IP_VERSION(10, 1, 2): 4495 case IP_VERSION(10, 1, 3): 4496 case IP_VERSION(10, 1, 4): 4497 adev->gfx.me.num_me = 1; 4498 adev->gfx.me.num_pipe_per_me = 1; 4499 adev->gfx.me.num_queue_per_pipe = 1; 4500 adev->gfx.mec.num_mec = 2; 4501 adev->gfx.mec.num_pipe_per_mec = 4; 4502 adev->gfx.mec.num_queue_per_pipe = 8; 4503 break; 4504 case IP_VERSION(10, 3, 0): 4505 case IP_VERSION(10, 3, 2): 4506 case IP_VERSION(10, 3, 1): 4507 case IP_VERSION(10, 3, 4): 4508 case IP_VERSION(10, 3, 5): 4509 case IP_VERSION(10, 3, 6): 4510 case IP_VERSION(10, 3, 3): 4511 case IP_VERSION(10, 3, 7): 4512 adev->gfx.me.num_me = 1; 4513 adev->gfx.me.num_pipe_per_me = 1; 4514 adev->gfx.me.num_queue_per_pipe = 1; 4515 adev->gfx.mec.num_mec = 2; 4516 adev->gfx.mec.num_pipe_per_mec = 4; 4517 adev->gfx.mec.num_queue_per_pipe = 4; 4518 break; 4519 default: 4520 adev->gfx.me.num_me = 1; 4521 adev->gfx.me.num_pipe_per_me = 1; 4522 adev->gfx.me.num_queue_per_pipe = 1; 4523 adev->gfx.mec.num_mec = 1; 4524 adev->gfx.mec.num_pipe_per_mec = 4; 4525 adev->gfx.mec.num_queue_per_pipe = 8; 4526 break; 4527 } 4528 4529 /* KIQ event */ 4530 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4531 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4532 &adev->gfx.kiq[0].irq); 4533 if (r) 4534 return r; 4535 4536 /* EOP Event */ 4537 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4538 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4539 &adev->gfx.eop_irq); 4540 if (r) 4541 return r; 4542 4543 /* Privileged reg */ 4544 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4545 &adev->gfx.priv_reg_irq); 4546 if (r) 4547 return r; 4548 4549 /* Privileged inst */ 4550 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4551 &adev->gfx.priv_inst_irq); 4552 if (r) 4553 return r; 4554 4555 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4556 4557 gfx_v10_0_me_init(adev); 4558 4559 if (adev->gfx.rlc.funcs) { 4560 if (adev->gfx.rlc.funcs->init) { 4561 r = adev->gfx.rlc.funcs->init(adev); 4562 if (r) { 4563 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4564 return r; 4565 } 4566 } 4567 } 4568 4569 r = gfx_v10_0_mec_init(adev); 4570 if (r) { 4571 DRM_ERROR("Failed to init MEC BOs!\n"); 4572 return r; 4573 } 4574 4575 /* set up the gfx ring */ 4576 for (i = 0; i < adev->gfx.me.num_me; i++) { 4577 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4578 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4579 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4580 continue; 4581 4582 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4583 i, k, j); 4584 if (r) 4585 return r; 4586 ring_id++; 4587 } 4588 } 4589 } 4590 4591 ring_id = 0; 4592 /* set up the compute queues - allocate horizontally across pipes */ 4593 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4594 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4595 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4596 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4597 k, j)) 4598 continue; 4599 4600 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4601 i, k, j); 4602 if (r) 4603 return r; 4604 4605 ring_id++; 4606 } 4607 } 4608 } 4609 4610 if (!adev->enable_mes_kiq) { 4611 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0); 4612 if (r) { 4613 DRM_ERROR("Failed to init KIQ BOs!\n"); 4614 return r; 4615 } 4616 4617 kiq = &adev->gfx.kiq[0]; 4618 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 4619 if (r) 4620 return r; 4621 } 4622 4623 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0); 4624 if (r) 4625 return r; 4626 4627 /* allocate visible FB for rlc auto-loading fw */ 4628 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4629 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4630 if (r) 4631 return r; 4632 } 4633 4634 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4635 4636 gfx_v10_0_gpu_early_init(adev); 4637 4638 return 0; 4639 } 4640 4641 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4642 { 4643 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4644 &adev->gfx.pfp.pfp_fw_gpu_addr, 4645 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4646 } 4647 4648 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4649 { 4650 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4651 &adev->gfx.ce.ce_fw_gpu_addr, 4652 (void **)&adev->gfx.ce.ce_fw_ptr); 4653 } 4654 4655 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4656 { 4657 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4658 &adev->gfx.me.me_fw_gpu_addr, 4659 (void **)&adev->gfx.me.me_fw_ptr); 4660 } 4661 4662 static int gfx_v10_0_sw_fini(void *handle) 4663 { 4664 int i; 4665 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4666 4667 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4668 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4669 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4670 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4671 4672 amdgpu_gfx_mqd_sw_fini(adev, 0); 4673 4674 if (!adev->enable_mes_kiq) { 4675 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 4676 amdgpu_gfx_kiq_fini(adev, 0); 4677 } 4678 4679 gfx_v10_0_pfp_fini(adev); 4680 gfx_v10_0_ce_fini(adev); 4681 gfx_v10_0_me_fini(adev); 4682 gfx_v10_0_rlc_fini(adev); 4683 gfx_v10_0_mec_fini(adev); 4684 4685 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4686 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4687 4688 gfx_v10_0_free_microcode(adev); 4689 4690 return 0; 4691 } 4692 4693 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4694 u32 sh_num, u32 instance, int xcc_id) 4695 { 4696 u32 data; 4697 4698 if (instance == 0xffffffff) 4699 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4700 INSTANCE_BROADCAST_WRITES, 1); 4701 else 4702 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4703 instance); 4704 4705 if (se_num == 0xffffffff) 4706 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4707 1); 4708 else 4709 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4710 4711 if (sh_num == 0xffffffff) 4712 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4713 1); 4714 else 4715 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4716 4717 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4718 } 4719 4720 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4721 { 4722 u32 data, mask; 4723 4724 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4725 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4726 4727 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4728 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4729 4730 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4731 adev->gfx.config.max_sh_per_se); 4732 4733 return (~data) & mask; 4734 } 4735 4736 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4737 { 4738 int i, j; 4739 u32 data; 4740 u32 active_rbs = 0; 4741 u32 bitmap; 4742 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4743 adev->gfx.config.max_sh_per_se; 4744 4745 mutex_lock(&adev->grbm_idx_mutex); 4746 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4747 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4748 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4749 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 4750 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 4751 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) && 4752 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4753 continue; 4754 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4755 data = gfx_v10_0_get_rb_active_bitmap(adev); 4756 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4757 rb_bitmap_width_per_sh); 4758 } 4759 } 4760 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4761 mutex_unlock(&adev->grbm_idx_mutex); 4762 4763 adev->gfx.config.backend_enable_mask = active_rbs; 4764 adev->gfx.config.num_rbs = hweight32(active_rbs); 4765 } 4766 4767 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4768 { 4769 uint32_t num_sc; 4770 uint32_t enabled_rb_per_sh; 4771 uint32_t active_rb_bitmap; 4772 uint32_t num_rb_per_sc; 4773 uint32_t num_packer_per_sc; 4774 uint32_t pa_sc_tile_steering_override; 4775 4776 /* for ASICs that integrates GFX v10.3 4777 * pa_sc_tile_steering_override should be set to 0 4778 */ 4779 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 4780 return 0; 4781 4782 /* init num_sc */ 4783 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4784 adev->gfx.config.num_sc_per_sh; 4785 /* init num_rb_per_sc */ 4786 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4787 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4788 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4789 /* init num_packer_per_sc */ 4790 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4791 4792 pa_sc_tile_steering_override = 0; 4793 pa_sc_tile_steering_override |= 4794 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4795 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4796 pa_sc_tile_steering_override |= 4797 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4798 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4799 pa_sc_tile_steering_override |= 4800 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4801 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4802 4803 return pa_sc_tile_steering_override; 4804 } 4805 4806 #define DEFAULT_SH_MEM_BASES (0x6000) 4807 4808 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, 4809 uint32_t first_vmid, 4810 uint32_t last_vmid) 4811 { 4812 uint32_t data; 4813 uint32_t trap_config_vmid_mask = 0; 4814 int i; 4815 4816 /* Calculate trap config vmid mask */ 4817 for (i = first_vmid; i < last_vmid; i++) 4818 trap_config_vmid_mask |= (1 << i); 4819 4820 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, 4821 VMID_SEL, trap_config_vmid_mask); 4822 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, 4823 TRAP_EN, 1); 4824 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); 4825 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); 4826 4827 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); 4828 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); 4829 } 4830 4831 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4832 { 4833 int i; 4834 uint32_t sh_mem_bases; 4835 4836 /* 4837 * Configure apertures: 4838 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4839 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4840 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4841 */ 4842 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4843 4844 mutex_lock(&adev->srbm_mutex); 4845 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4846 nv_grbm_select(adev, 0, 0, 0, i); 4847 /* CP and shaders */ 4848 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4849 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4850 } 4851 nv_grbm_select(adev, 0, 0, 0, 0); 4852 mutex_unlock(&adev->srbm_mutex); 4853 4854 /* 4855 * Initialize all compute VMIDs to have no GDS, GWS, or OA 4856 * access. These should be enabled by FW for target VMIDs. 4857 */ 4858 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4859 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4860 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4861 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4862 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4863 } 4864 4865 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, 4866 AMDGPU_NUM_VMID); 4867 } 4868 4869 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4870 { 4871 int vmid; 4872 4873 /* 4874 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4875 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4876 * the driver can enable them for graphics. VMID0 should maintain 4877 * access so that HWS firmware can save/restore entries. 4878 */ 4879 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4880 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4881 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4882 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4883 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4884 } 4885 } 4886 4887 4888 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4889 { 4890 int i, j, k; 4891 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4892 u32 tmp, wgp_active_bitmap = 0; 4893 u32 gcrd_targets_disable_tcp = 0; 4894 u32 utcl_invreq_disable = 0; 4895 /* 4896 * GCRD_TARGETS_DISABLE field contains 4897 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4898 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4899 */ 4900 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4901 2 * max_wgp_per_sh + /* TCP */ 4902 max_wgp_per_sh + /* SQC */ 4903 4); /* GL1C */ 4904 /* 4905 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4906 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4907 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4908 */ 4909 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4910 2 * max_wgp_per_sh + /* TCP */ 4911 2 * max_wgp_per_sh + /* SQC */ 4912 4 + /* RMI */ 4913 1); /* SQG */ 4914 4915 mutex_lock(&adev->grbm_idx_mutex); 4916 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4917 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4918 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4919 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4920 /* 4921 * Set corresponding TCP bits for the inactive WGPs in 4922 * GCRD_SA_TARGETS_DISABLE 4923 */ 4924 gcrd_targets_disable_tcp = 0; 4925 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4926 utcl_invreq_disable = 0; 4927 4928 for (k = 0; k < max_wgp_per_sh; k++) { 4929 if (!(wgp_active_bitmap & (1 << k))) { 4930 gcrd_targets_disable_tcp |= 3 << (2 * k); 4931 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 4932 utcl_invreq_disable |= (3 << (2 * k)) | 4933 (3 << (2 * (max_wgp_per_sh + k))); 4934 } 4935 } 4936 4937 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 4938 /* only override TCP & SQC bits */ 4939 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 4940 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 4941 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 4942 4943 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 4944 /* only override TCP & SQC bits */ 4945 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 4946 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 4947 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 4948 } 4949 } 4950 4951 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4952 mutex_unlock(&adev->grbm_idx_mutex); 4953 } 4954 4955 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4956 { 4957 /* TCCs are global (not instanced). */ 4958 uint32_t tcc_disable; 4959 4960 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 4961 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 4962 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 4963 } else { 4964 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4965 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4966 } 4967 4968 adev->gfx.config.tcc_disabled_mask = 4969 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 4970 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 4971 } 4972 4973 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 4974 { 4975 u32 tmp; 4976 int i; 4977 4978 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 4979 4980 gfx_v10_0_setup_rb(adev); 4981 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 4982 gfx_v10_0_get_tcc_info(adev); 4983 adev->gfx.config.pa_sc_tile_steering_override = 4984 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 4985 4986 /* XXX SH_MEM regs */ 4987 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4988 mutex_lock(&adev->srbm_mutex); 4989 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 4990 nv_grbm_select(adev, 0, 0, 0, i); 4991 /* CP and shaders */ 4992 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4993 if (i != 0) { 4994 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 4995 (adev->gmc.private_aperture_start >> 48)); 4996 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 4997 (adev->gmc.shared_aperture_start >> 48)); 4998 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 4999 } 5000 } 5001 nv_grbm_select(adev, 0, 0, 0, 0); 5002 5003 mutex_unlock(&adev->srbm_mutex); 5004 5005 gfx_v10_0_init_compute_vmid(adev); 5006 gfx_v10_0_init_gds_vmid(adev); 5007 5008 } 5009 5010 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5011 bool enable) 5012 { 5013 u32 tmp; 5014 5015 if (amdgpu_sriov_vf(adev)) 5016 return; 5017 5018 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5019 5020 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5021 enable ? 1 : 0); 5022 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5023 enable ? 1 : 0); 5024 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5025 enable ? 1 : 0); 5026 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5027 enable ? 1 : 0); 5028 5029 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5030 } 5031 5032 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5033 { 5034 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5035 5036 /* csib */ 5037 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5038 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5039 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5040 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5041 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5042 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5043 } else { 5044 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5045 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5046 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5047 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5048 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5049 } 5050 return 0; 5051 } 5052 5053 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5054 { 5055 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5056 5057 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5058 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5059 } 5060 5061 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5062 { 5063 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5064 udelay(50); 5065 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5066 udelay(50); 5067 } 5068 5069 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5070 bool enable) 5071 { 5072 uint32_t rlc_pg_cntl; 5073 5074 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5075 5076 if (!enable) { 5077 /* RLC_PG_CNTL[23] = 0 (default) 5078 * RLC will wait for handshake acks with SMU 5079 * GFXOFF will be enabled 5080 * RLC_PG_CNTL[23] = 1 5081 * RLC will not issue any message to SMU 5082 * hence no handshake between SMU & RLC 5083 * GFXOFF will be disabled 5084 */ 5085 rlc_pg_cntl |= 0x800000; 5086 } else 5087 rlc_pg_cntl &= ~0x800000; 5088 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5089 } 5090 5091 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5092 { 5093 /* 5094 * TODO: enable rlc & smu handshake until smu 5095 * and gfxoff feature works as expected 5096 */ 5097 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5098 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5099 5100 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5101 udelay(50); 5102 } 5103 5104 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5105 { 5106 uint32_t tmp; 5107 5108 /* enable Save Restore Machine */ 5109 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5110 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5111 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5112 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5113 } 5114 5115 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5116 { 5117 const struct rlc_firmware_header_v2_0 *hdr; 5118 const __le32 *fw_data; 5119 unsigned int i, fw_size; 5120 5121 if (!adev->gfx.rlc_fw) 5122 return -EINVAL; 5123 5124 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5125 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5126 5127 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5128 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5129 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5130 5131 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5132 RLCG_UCODE_LOADING_START_ADDRESS); 5133 5134 for (i = 0; i < fw_size; i++) 5135 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5136 le32_to_cpup(fw_data++)); 5137 5138 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5139 5140 return 0; 5141 } 5142 5143 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5144 { 5145 int r; 5146 5147 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5148 adev->psp.autoload_supported) { 5149 5150 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5151 if (r) 5152 return r; 5153 5154 gfx_v10_0_init_csb(adev); 5155 5156 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5157 5158 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5159 gfx_v10_0_rlc_enable_srm(adev); 5160 } else { 5161 if (amdgpu_sriov_vf(adev)) { 5162 gfx_v10_0_init_csb(adev); 5163 return 0; 5164 } 5165 5166 adev->gfx.rlc.funcs->stop(adev); 5167 5168 /* disable CG */ 5169 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5170 5171 /* disable PG */ 5172 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5173 5174 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5175 /* legacy rlc firmware loading */ 5176 r = gfx_v10_0_rlc_load_microcode(adev); 5177 if (r) 5178 return r; 5179 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5180 /* rlc backdoor autoload firmware */ 5181 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5182 if (r) 5183 return r; 5184 } 5185 5186 gfx_v10_0_init_csb(adev); 5187 5188 gfx_v10_0_update_spm_vmid_internal(adev, 0xf); 5189 5190 adev->gfx.rlc.funcs->start(adev); 5191 5192 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5193 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5194 if (r) 5195 return r; 5196 } 5197 } 5198 5199 return 0; 5200 } 5201 5202 static struct { 5203 FIRMWARE_ID id; 5204 unsigned int offset; 5205 unsigned int size; 5206 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5207 5208 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5209 { 5210 int ret; 5211 RLC_TABLE_OF_CONTENT *rlc_toc; 5212 5213 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5214 AMDGPU_GEM_DOMAIN_GTT, 5215 &adev->gfx.rlc.rlc_toc_bo, 5216 &adev->gfx.rlc.rlc_toc_gpu_addr, 5217 (void **)&adev->gfx.rlc.rlc_toc_buf); 5218 if (ret) { 5219 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5220 return ret; 5221 } 5222 5223 /* Copy toc from psp sos fw to rlc toc buffer */ 5224 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5225 5226 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5227 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5228 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5229 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5230 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5231 /* Offset needs 4KB alignment */ 5232 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5233 } 5234 5235 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5236 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5237 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5238 5239 rlc_toc++; 5240 } 5241 5242 return 0; 5243 } 5244 5245 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5246 { 5247 uint32_t total_size = 0; 5248 FIRMWARE_ID id; 5249 int ret; 5250 5251 ret = gfx_v10_0_parse_rlc_toc(adev); 5252 if (ret) { 5253 dev_err(adev->dev, "failed to parse rlc toc\n"); 5254 return 0; 5255 } 5256 5257 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5258 total_size += rlc_autoload_info[id].size; 5259 5260 /* In case the offset in rlc toc ucode is aligned */ 5261 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5262 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5263 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5264 5265 return total_size; 5266 } 5267 5268 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5269 { 5270 int r; 5271 uint32_t total_size; 5272 5273 total_size = gfx_v10_0_calc_toc_total_size(adev); 5274 5275 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5276 AMDGPU_GEM_DOMAIN_GTT, 5277 &adev->gfx.rlc.rlc_autoload_bo, 5278 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5279 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5280 if (r) { 5281 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5282 return r; 5283 } 5284 5285 return 0; 5286 } 5287 5288 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5289 { 5290 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5291 &adev->gfx.rlc.rlc_toc_gpu_addr, 5292 (void **)&adev->gfx.rlc.rlc_toc_buf); 5293 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5294 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5295 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5296 } 5297 5298 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5299 FIRMWARE_ID id, 5300 const void *fw_data, 5301 uint32_t fw_size) 5302 { 5303 uint32_t toc_offset; 5304 uint32_t toc_fw_size; 5305 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5306 5307 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5308 return; 5309 5310 toc_offset = rlc_autoload_info[id].offset; 5311 toc_fw_size = rlc_autoload_info[id].size; 5312 5313 if (fw_size == 0) 5314 fw_size = toc_fw_size; 5315 5316 if (fw_size > toc_fw_size) 5317 fw_size = toc_fw_size; 5318 5319 memcpy(ptr + toc_offset, fw_data, fw_size); 5320 5321 if (fw_size < toc_fw_size) 5322 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5323 } 5324 5325 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5326 { 5327 void *data; 5328 uint32_t size; 5329 5330 data = adev->gfx.rlc.rlc_toc_buf; 5331 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5332 5333 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5334 FIRMWARE_ID_RLC_TOC, 5335 data, size); 5336 } 5337 5338 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5339 { 5340 const __le32 *fw_data; 5341 uint32_t fw_size; 5342 const struct gfx_firmware_header_v1_0 *cp_hdr; 5343 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5344 5345 /* pfp ucode */ 5346 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5347 adev->gfx.pfp_fw->data; 5348 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5349 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5350 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5351 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5352 FIRMWARE_ID_CP_PFP, 5353 fw_data, fw_size); 5354 5355 /* ce ucode */ 5356 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5357 adev->gfx.ce_fw->data; 5358 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5359 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5360 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5361 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5362 FIRMWARE_ID_CP_CE, 5363 fw_data, fw_size); 5364 5365 /* me ucode */ 5366 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5367 adev->gfx.me_fw->data; 5368 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5369 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5370 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5371 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5372 FIRMWARE_ID_CP_ME, 5373 fw_data, fw_size); 5374 5375 /* rlc ucode */ 5376 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5377 adev->gfx.rlc_fw->data; 5378 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5379 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5380 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5381 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5382 FIRMWARE_ID_RLC_G_UCODE, 5383 fw_data, fw_size); 5384 5385 /* mec1 ucode */ 5386 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5387 adev->gfx.mec_fw->data; 5388 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5389 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5390 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5391 cp_hdr->jt_size * 4; 5392 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5393 FIRMWARE_ID_CP_MEC, 5394 fw_data, fw_size); 5395 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5396 } 5397 5398 /* Temporarily put sdma part here */ 5399 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5400 { 5401 const __le32 *fw_data; 5402 uint32_t fw_size; 5403 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5404 int i; 5405 5406 for (i = 0; i < adev->sdma.num_instances; i++) { 5407 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5408 adev->sdma.instance[i].fw->data; 5409 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5410 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5411 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5412 5413 if (i == 0) { 5414 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5415 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5416 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5417 FIRMWARE_ID_SDMA0_JT, 5418 (uint32_t *)fw_data + 5419 sdma_hdr->jt_offset, 5420 sdma_hdr->jt_size * 4); 5421 } else if (i == 1) { 5422 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5423 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5424 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5425 FIRMWARE_ID_SDMA1_JT, 5426 (uint32_t *)fw_data + 5427 sdma_hdr->jt_offset, 5428 sdma_hdr->jt_size * 4); 5429 } 5430 } 5431 } 5432 5433 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5434 { 5435 uint32_t rlc_g_offset, rlc_g_size, tmp; 5436 uint64_t gpu_addr; 5437 5438 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5439 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5440 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5441 5442 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5443 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5444 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5445 5446 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5447 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5448 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5449 5450 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5451 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5452 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5453 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5454 return -EINVAL; 5455 } 5456 5457 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5458 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5459 DRM_ERROR("RLC ROM should halt itself\n"); 5460 return -EINVAL; 5461 } 5462 5463 return 0; 5464 } 5465 5466 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5467 { 5468 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5469 uint32_t tmp; 5470 int i; 5471 uint64_t addr; 5472 5473 /* Trigger an invalidation of the L1 instruction caches */ 5474 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5475 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5476 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5477 5478 /* Wait for invalidation complete */ 5479 for (i = 0; i < usec_timeout; i++) { 5480 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5481 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5482 INVALIDATE_CACHE_COMPLETE)) 5483 break; 5484 udelay(1); 5485 } 5486 5487 if (i >= usec_timeout) { 5488 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5489 return -EINVAL; 5490 } 5491 5492 /* Program me ucode address into intruction cache address register */ 5493 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5494 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5495 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5496 lower_32_bits(addr) & 0xFFFFF000); 5497 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5498 upper_32_bits(addr)); 5499 5500 return 0; 5501 } 5502 5503 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5504 { 5505 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5506 uint32_t tmp; 5507 int i; 5508 uint64_t addr; 5509 5510 /* Trigger an invalidation of the L1 instruction caches */ 5511 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5512 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5513 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5514 5515 /* Wait for invalidation complete */ 5516 for (i = 0; i < usec_timeout; i++) { 5517 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5518 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5519 INVALIDATE_CACHE_COMPLETE)) 5520 break; 5521 udelay(1); 5522 } 5523 5524 if (i >= usec_timeout) { 5525 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5526 return -EINVAL; 5527 } 5528 5529 /* Program ce ucode address into intruction cache address register */ 5530 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5531 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5532 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5533 lower_32_bits(addr) & 0xFFFFF000); 5534 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5535 upper_32_bits(addr)); 5536 5537 return 0; 5538 } 5539 5540 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5541 { 5542 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5543 uint32_t tmp; 5544 int i; 5545 uint64_t addr; 5546 5547 /* Trigger an invalidation of the L1 instruction caches */ 5548 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5549 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5550 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5551 5552 /* Wait for invalidation complete */ 5553 for (i = 0; i < usec_timeout; i++) { 5554 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5555 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5556 INVALIDATE_CACHE_COMPLETE)) 5557 break; 5558 udelay(1); 5559 } 5560 5561 if (i >= usec_timeout) { 5562 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5563 return -EINVAL; 5564 } 5565 5566 /* Program pfp ucode address into intruction cache address register */ 5567 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5568 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5569 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5570 lower_32_bits(addr) & 0xFFFFF000); 5571 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5572 upper_32_bits(addr)); 5573 5574 return 0; 5575 } 5576 5577 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5578 { 5579 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5580 uint32_t tmp; 5581 int i; 5582 uint64_t addr; 5583 5584 /* Trigger an invalidation of the L1 instruction caches */ 5585 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5586 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5587 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5588 5589 /* Wait for invalidation complete */ 5590 for (i = 0; i < usec_timeout; i++) { 5591 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5592 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5593 INVALIDATE_CACHE_COMPLETE)) 5594 break; 5595 udelay(1); 5596 } 5597 5598 if (i >= usec_timeout) { 5599 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5600 return -EINVAL; 5601 } 5602 5603 /* Program mec1 ucode address into intruction cache address register */ 5604 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5605 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5606 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5607 lower_32_bits(addr) & 0xFFFFF000); 5608 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5609 upper_32_bits(addr)); 5610 5611 return 0; 5612 } 5613 5614 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5615 { 5616 uint32_t cp_status; 5617 uint32_t bootload_status; 5618 int i, r; 5619 5620 for (i = 0; i < adev->usec_timeout; i++) { 5621 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5622 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5623 if ((cp_status == 0) && 5624 (REG_GET_FIELD(bootload_status, 5625 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5626 break; 5627 } 5628 udelay(1); 5629 } 5630 5631 if (i >= adev->usec_timeout) { 5632 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5633 return -ETIMEDOUT; 5634 } 5635 5636 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5637 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5638 if (r) 5639 return r; 5640 5641 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5642 if (r) 5643 return r; 5644 5645 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5646 if (r) 5647 return r; 5648 5649 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5650 if (r) 5651 return r; 5652 } 5653 5654 return 0; 5655 } 5656 5657 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5658 { 5659 int i; 5660 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5661 5662 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5663 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5664 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5665 5666 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 5667 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5668 else 5669 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5670 5671 if (adev->job_hang && !enable) 5672 return 0; 5673 5674 for (i = 0; i < adev->usec_timeout; i++) { 5675 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5676 break; 5677 udelay(1); 5678 } 5679 5680 if (i >= adev->usec_timeout) 5681 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5682 5683 return 0; 5684 } 5685 5686 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5687 { 5688 int r; 5689 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5690 const __le32 *fw_data; 5691 unsigned int i, fw_size; 5692 uint32_t tmp; 5693 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5694 5695 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5696 adev->gfx.pfp_fw->data; 5697 5698 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5699 5700 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5701 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5702 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5703 5704 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5705 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5706 &adev->gfx.pfp.pfp_fw_obj, 5707 &adev->gfx.pfp.pfp_fw_gpu_addr, 5708 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5709 if (r) { 5710 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5711 gfx_v10_0_pfp_fini(adev); 5712 return r; 5713 } 5714 5715 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5716 5717 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5718 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5719 5720 /* Trigger an invalidation of the L1 instruction caches */ 5721 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5722 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5723 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5724 5725 /* Wait for invalidation complete */ 5726 for (i = 0; i < usec_timeout; i++) { 5727 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5728 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5729 INVALIDATE_CACHE_COMPLETE)) 5730 break; 5731 udelay(1); 5732 } 5733 5734 if (i >= usec_timeout) { 5735 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5736 return -EINVAL; 5737 } 5738 5739 if (amdgpu_emu_mode == 1) 5740 adev->hdp.funcs->flush_hdp(adev, NULL); 5741 5742 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5743 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5744 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5745 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5746 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5747 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5748 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5749 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5750 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5751 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5752 5753 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5754 5755 for (i = 0; i < pfp_hdr->jt_size; i++) 5756 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5757 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5758 5759 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5760 5761 return 0; 5762 } 5763 5764 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5765 { 5766 int r; 5767 const struct gfx_firmware_header_v1_0 *ce_hdr; 5768 const __le32 *fw_data; 5769 unsigned int i, fw_size; 5770 uint32_t tmp; 5771 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5772 5773 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5774 adev->gfx.ce_fw->data; 5775 5776 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5777 5778 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5779 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5780 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5781 5782 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5783 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5784 &adev->gfx.ce.ce_fw_obj, 5785 &adev->gfx.ce.ce_fw_gpu_addr, 5786 (void **)&adev->gfx.ce.ce_fw_ptr); 5787 if (r) { 5788 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5789 gfx_v10_0_ce_fini(adev); 5790 return r; 5791 } 5792 5793 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5794 5795 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5796 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5797 5798 /* Trigger an invalidation of the L1 instruction caches */ 5799 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5800 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5801 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5802 5803 /* Wait for invalidation complete */ 5804 for (i = 0; i < usec_timeout; i++) { 5805 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5806 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5807 INVALIDATE_CACHE_COMPLETE)) 5808 break; 5809 udelay(1); 5810 } 5811 5812 if (i >= usec_timeout) { 5813 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5814 return -EINVAL; 5815 } 5816 5817 if (amdgpu_emu_mode == 1) 5818 adev->hdp.funcs->flush_hdp(adev, NULL); 5819 5820 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5821 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5822 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5823 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5824 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5825 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5826 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5827 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5828 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5829 5830 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5831 5832 for (i = 0; i < ce_hdr->jt_size; i++) 5833 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5834 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5835 5836 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5837 5838 return 0; 5839 } 5840 5841 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5842 { 5843 int r; 5844 const struct gfx_firmware_header_v1_0 *me_hdr; 5845 const __le32 *fw_data; 5846 unsigned int i, fw_size; 5847 uint32_t tmp; 5848 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5849 5850 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5851 adev->gfx.me_fw->data; 5852 5853 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5854 5855 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5856 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5857 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5858 5859 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5860 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5861 &adev->gfx.me.me_fw_obj, 5862 &adev->gfx.me.me_fw_gpu_addr, 5863 (void **)&adev->gfx.me.me_fw_ptr); 5864 if (r) { 5865 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5866 gfx_v10_0_me_fini(adev); 5867 return r; 5868 } 5869 5870 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5871 5872 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5873 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5874 5875 /* Trigger an invalidation of the L1 instruction caches */ 5876 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5877 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5878 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5879 5880 /* Wait for invalidation complete */ 5881 for (i = 0; i < usec_timeout; i++) { 5882 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5883 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5884 INVALIDATE_CACHE_COMPLETE)) 5885 break; 5886 udelay(1); 5887 } 5888 5889 if (i >= usec_timeout) { 5890 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5891 return -EINVAL; 5892 } 5893 5894 if (amdgpu_emu_mode == 1) 5895 adev->hdp.funcs->flush_hdp(adev, NULL); 5896 5897 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5898 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5899 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5900 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5901 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5902 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5903 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5904 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5905 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5906 5907 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5908 5909 for (i = 0; i < me_hdr->jt_size; i++) 5910 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5911 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5912 5913 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5914 5915 return 0; 5916 } 5917 5918 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5919 { 5920 int r; 5921 5922 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5923 return -EINVAL; 5924 5925 gfx_v10_0_cp_gfx_enable(adev, false); 5926 5927 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5928 if (r) { 5929 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5930 return r; 5931 } 5932 5933 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5934 if (r) { 5935 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5936 return r; 5937 } 5938 5939 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 5940 if (r) { 5941 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 5942 return r; 5943 } 5944 5945 return 0; 5946 } 5947 5948 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 5949 { 5950 struct amdgpu_ring *ring; 5951 const struct cs_section_def *sect = NULL; 5952 const struct cs_extent_def *ext = NULL; 5953 int r, i; 5954 int ctx_reg_offset; 5955 5956 /* init the CP */ 5957 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 5958 adev->gfx.config.max_hw_contexts - 1); 5959 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 5960 5961 gfx_v10_0_cp_gfx_enable(adev, true); 5962 5963 ring = &adev->gfx.gfx_ring[0]; 5964 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 5965 if (r) { 5966 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 5967 return r; 5968 } 5969 5970 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5971 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 5972 5973 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5974 amdgpu_ring_write(ring, 0x80000000); 5975 amdgpu_ring_write(ring, 0x80000000); 5976 5977 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 5978 for (ext = sect->section; ext->extent != NULL; ++ext) { 5979 if (sect->id == SECT_CONTEXT) { 5980 amdgpu_ring_write(ring, 5981 PACKET3(PACKET3_SET_CONTEXT_REG, 5982 ext->reg_count)); 5983 amdgpu_ring_write(ring, ext->reg_index - 5984 PACKET3_SET_CONTEXT_REG_START); 5985 for (i = 0; i < ext->reg_count; i++) 5986 amdgpu_ring_write(ring, ext->extent[i]); 5987 } 5988 } 5989 } 5990 5991 ctx_reg_offset = 5992 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 5993 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 5994 amdgpu_ring_write(ring, ctx_reg_offset); 5995 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 5996 5997 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 5998 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 5999 6000 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6001 amdgpu_ring_write(ring, 0); 6002 6003 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6004 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6005 amdgpu_ring_write(ring, 0x8000); 6006 amdgpu_ring_write(ring, 0x8000); 6007 6008 amdgpu_ring_commit(ring); 6009 6010 /* submit cs packet to copy state 0 to next available state */ 6011 if (adev->gfx.num_gfx_rings > 1) { 6012 /* maximum supported gfx ring is 2 */ 6013 ring = &adev->gfx.gfx_ring[1]; 6014 r = amdgpu_ring_alloc(ring, 2); 6015 if (r) { 6016 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6017 return r; 6018 } 6019 6020 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6021 amdgpu_ring_write(ring, 0); 6022 6023 amdgpu_ring_commit(ring); 6024 } 6025 return 0; 6026 } 6027 6028 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6029 CP_PIPE_ID pipe) 6030 { 6031 u32 tmp; 6032 6033 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6034 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6035 6036 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6037 } 6038 6039 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6040 struct amdgpu_ring *ring) 6041 { 6042 u32 tmp; 6043 6044 if (!amdgpu_async_gfx_ring) { 6045 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6046 if (ring->use_doorbell) { 6047 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6048 DOORBELL_OFFSET, ring->doorbell_index); 6049 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6050 DOORBELL_EN, 1); 6051 } else { 6052 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6053 DOORBELL_EN, 0); 6054 } 6055 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6056 } 6057 switch (adev->ip_versions[GC_HWIP][0]) { 6058 case IP_VERSION(10, 3, 0): 6059 case IP_VERSION(10, 3, 2): 6060 case IP_VERSION(10, 3, 1): 6061 case IP_VERSION(10, 3, 4): 6062 case IP_VERSION(10, 3, 5): 6063 case IP_VERSION(10, 3, 6): 6064 case IP_VERSION(10, 3, 3): 6065 case IP_VERSION(10, 3, 7): 6066 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6067 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6068 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6069 6070 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6071 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6072 break; 6073 default: 6074 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6075 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6076 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6077 6078 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6079 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6080 break; 6081 } 6082 } 6083 6084 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6085 { 6086 struct amdgpu_ring *ring; 6087 u32 tmp; 6088 u32 rb_bufsz; 6089 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6090 6091 /* Set the write pointer delay */ 6092 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6093 6094 /* set the RB to use vmid 0 */ 6095 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6096 6097 /* Init gfx ring 0 for pipe 0 */ 6098 mutex_lock(&adev->srbm_mutex); 6099 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6100 6101 /* Set ring buffer size */ 6102 ring = &adev->gfx.gfx_ring[0]; 6103 rb_bufsz = order_base_2(ring->ring_size / 8); 6104 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6105 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6106 #ifdef __BIG_ENDIAN 6107 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6108 #endif 6109 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6110 6111 /* Initialize the ring buffer's write pointers */ 6112 ring->wptr = 0; 6113 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6114 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6115 6116 /* set the wb address wether it's enabled or not */ 6117 rptr_addr = ring->rptr_gpu_addr; 6118 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6119 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6120 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6121 6122 wptr_gpu_addr = ring->wptr_gpu_addr; 6123 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6124 lower_32_bits(wptr_gpu_addr)); 6125 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6126 upper_32_bits(wptr_gpu_addr)); 6127 6128 mdelay(1); 6129 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6130 6131 rb_addr = ring->gpu_addr >> 8; 6132 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6133 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6134 6135 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6136 6137 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6138 mutex_unlock(&adev->srbm_mutex); 6139 6140 /* Init gfx ring 1 for pipe 1 */ 6141 if (adev->gfx.num_gfx_rings > 1) { 6142 mutex_lock(&adev->srbm_mutex); 6143 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6144 /* maximum supported gfx ring is 2 */ 6145 ring = &adev->gfx.gfx_ring[1]; 6146 rb_bufsz = order_base_2(ring->ring_size / 8); 6147 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6148 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6149 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6150 /* Initialize the ring buffer's write pointers */ 6151 ring->wptr = 0; 6152 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6153 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6154 /* Set the wb address wether it's enabled or not */ 6155 rptr_addr = ring->rptr_gpu_addr; 6156 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6157 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6158 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6159 wptr_gpu_addr = ring->wptr_gpu_addr; 6160 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6161 lower_32_bits(wptr_gpu_addr)); 6162 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6163 upper_32_bits(wptr_gpu_addr)); 6164 6165 mdelay(1); 6166 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6167 6168 rb_addr = ring->gpu_addr >> 8; 6169 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6170 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6171 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6172 6173 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6174 mutex_unlock(&adev->srbm_mutex); 6175 } 6176 /* Switch to pipe 0 */ 6177 mutex_lock(&adev->srbm_mutex); 6178 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6179 mutex_unlock(&adev->srbm_mutex); 6180 6181 /* start the ring */ 6182 gfx_v10_0_cp_gfx_start(adev); 6183 6184 return 0; 6185 } 6186 6187 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6188 { 6189 if (enable) { 6190 switch (adev->ip_versions[GC_HWIP][0]) { 6191 case IP_VERSION(10, 3, 0): 6192 case IP_VERSION(10, 3, 2): 6193 case IP_VERSION(10, 3, 1): 6194 case IP_VERSION(10, 3, 4): 6195 case IP_VERSION(10, 3, 5): 6196 case IP_VERSION(10, 3, 6): 6197 case IP_VERSION(10, 3, 3): 6198 case IP_VERSION(10, 3, 7): 6199 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6200 break; 6201 default: 6202 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6203 break; 6204 } 6205 } else { 6206 switch (adev->ip_versions[GC_HWIP][0]) { 6207 case IP_VERSION(10, 3, 0): 6208 case IP_VERSION(10, 3, 2): 6209 case IP_VERSION(10, 3, 1): 6210 case IP_VERSION(10, 3, 4): 6211 case IP_VERSION(10, 3, 5): 6212 case IP_VERSION(10, 3, 6): 6213 case IP_VERSION(10, 3, 3): 6214 case IP_VERSION(10, 3, 7): 6215 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6216 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6217 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6218 break; 6219 default: 6220 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6221 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6222 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6223 break; 6224 } 6225 adev->gfx.kiq[0].ring.sched.ready = false; 6226 } 6227 udelay(50); 6228 } 6229 6230 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6231 { 6232 const struct gfx_firmware_header_v1_0 *mec_hdr; 6233 const __le32 *fw_data; 6234 unsigned int i; 6235 u32 tmp; 6236 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6237 6238 if (!adev->gfx.mec_fw) 6239 return -EINVAL; 6240 6241 gfx_v10_0_cp_compute_enable(adev, false); 6242 6243 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6244 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6245 6246 fw_data = (const __le32 *) 6247 (adev->gfx.mec_fw->data + 6248 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6249 6250 /* Trigger an invalidation of the L1 instruction caches */ 6251 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6252 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6253 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6254 6255 /* Wait for invalidation complete */ 6256 for (i = 0; i < usec_timeout; i++) { 6257 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6258 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6259 INVALIDATE_CACHE_COMPLETE)) 6260 break; 6261 udelay(1); 6262 } 6263 6264 if (i >= usec_timeout) { 6265 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6266 return -EINVAL; 6267 } 6268 6269 if (amdgpu_emu_mode == 1) 6270 adev->hdp.funcs->flush_hdp(adev, NULL); 6271 6272 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6273 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6274 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6275 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6276 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6277 6278 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6279 0xFFFFF000); 6280 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6281 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6282 6283 /* MEC1 */ 6284 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6285 6286 for (i = 0; i < mec_hdr->jt_size; i++) 6287 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6288 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6289 6290 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6291 6292 /* 6293 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6294 * different microcode than MEC1. 6295 */ 6296 6297 return 0; 6298 } 6299 6300 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6301 { 6302 uint32_t tmp; 6303 struct amdgpu_device *adev = ring->adev; 6304 6305 /* tell RLC which is KIQ queue */ 6306 switch (adev->ip_versions[GC_HWIP][0]) { 6307 case IP_VERSION(10, 3, 0): 6308 case IP_VERSION(10, 3, 2): 6309 case IP_VERSION(10, 3, 1): 6310 case IP_VERSION(10, 3, 4): 6311 case IP_VERSION(10, 3, 5): 6312 case IP_VERSION(10, 3, 6): 6313 case IP_VERSION(10, 3, 3): 6314 case IP_VERSION(10, 3, 7): 6315 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6316 tmp &= 0xffffff00; 6317 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6318 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6319 tmp |= 0x80; 6320 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6321 break; 6322 default: 6323 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6324 tmp &= 0xffffff00; 6325 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6326 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6327 tmp |= 0x80; 6328 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6329 break; 6330 } 6331 } 6332 6333 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6334 struct v10_gfx_mqd *mqd, 6335 struct amdgpu_mqd_prop *prop) 6336 { 6337 bool priority = 0; 6338 u32 tmp; 6339 6340 /* set up default queue priority level 6341 * 0x0 = low priority, 0x1 = high priority 6342 */ 6343 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6344 priority = 1; 6345 6346 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6347 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6348 mqd->cp_gfx_hqd_queue_priority = tmp; 6349 } 6350 6351 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6352 struct amdgpu_mqd_prop *prop) 6353 { 6354 struct v10_gfx_mqd *mqd = m; 6355 uint64_t hqd_gpu_addr, wb_gpu_addr; 6356 uint32_t tmp; 6357 uint32_t rb_bufsz; 6358 6359 /* set up gfx hqd wptr */ 6360 mqd->cp_gfx_hqd_wptr = 0; 6361 mqd->cp_gfx_hqd_wptr_hi = 0; 6362 6363 /* set the pointer to the MQD */ 6364 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6365 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6366 6367 /* set up mqd control */ 6368 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6369 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6370 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6371 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6372 mqd->cp_gfx_mqd_control = tmp; 6373 6374 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6375 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6376 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6377 mqd->cp_gfx_hqd_vmid = 0; 6378 6379 /* set up gfx queue priority */ 6380 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6381 6382 /* set up time quantum */ 6383 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6384 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6385 mqd->cp_gfx_hqd_quantum = tmp; 6386 6387 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6388 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6389 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6390 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6391 6392 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6393 wb_gpu_addr = prop->rptr_gpu_addr; 6394 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6395 mqd->cp_gfx_hqd_rptr_addr_hi = 6396 upper_32_bits(wb_gpu_addr) & 0xffff; 6397 6398 /* set up rb_wptr_poll addr */ 6399 wb_gpu_addr = prop->wptr_gpu_addr; 6400 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6401 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6402 6403 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6404 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6405 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6406 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6407 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6408 #ifdef __BIG_ENDIAN 6409 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6410 #endif 6411 mqd->cp_gfx_hqd_cntl = tmp; 6412 6413 /* set up cp_doorbell_control */ 6414 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6415 if (prop->use_doorbell) { 6416 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6417 DOORBELL_OFFSET, prop->doorbell_index); 6418 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6419 DOORBELL_EN, 1); 6420 } else 6421 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6422 DOORBELL_EN, 0); 6423 mqd->cp_rb_doorbell_control = tmp; 6424 6425 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6426 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6427 6428 /* active the queue */ 6429 mqd->cp_gfx_hqd_active = 1; 6430 6431 return 0; 6432 } 6433 6434 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6435 { 6436 struct amdgpu_device *adev = ring->adev; 6437 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6438 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6439 6440 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6441 memset((void *)mqd, 0, sizeof(*mqd)); 6442 mutex_lock(&adev->srbm_mutex); 6443 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6444 amdgpu_ring_init_mqd(ring); 6445 6446 /* 6447 * if there are 2 gfx rings, set the lower doorbell 6448 * range of the first ring, otherwise the range of 6449 * the second ring will override the first ring 6450 */ 6451 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6452 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6453 6454 nv_grbm_select(adev, 0, 0, 0, 0); 6455 mutex_unlock(&adev->srbm_mutex); 6456 if (adev->gfx.me.mqd_backup[mqd_idx]) 6457 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6458 } else { 6459 /* restore mqd with the backup copy */ 6460 if (adev->gfx.me.mqd_backup[mqd_idx]) 6461 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6462 /* reset the ring */ 6463 ring->wptr = 0; 6464 *ring->wptr_cpu_addr = 0; 6465 amdgpu_ring_clear_ring(ring); 6466 } 6467 6468 return 0; 6469 } 6470 6471 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6472 { 6473 int r, i; 6474 struct amdgpu_ring *ring; 6475 6476 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6477 ring = &adev->gfx.gfx_ring[i]; 6478 6479 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6480 if (unlikely(r != 0)) 6481 return r; 6482 6483 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6484 if (!r) { 6485 r = gfx_v10_0_gfx_init_queue(ring); 6486 amdgpu_bo_kunmap(ring->mqd_obj); 6487 ring->mqd_ptr = NULL; 6488 } 6489 amdgpu_bo_unreserve(ring->mqd_obj); 6490 if (r) 6491 return r; 6492 } 6493 6494 r = amdgpu_gfx_enable_kgq(adev, 0); 6495 if (r) 6496 return r; 6497 6498 return gfx_v10_0_cp_gfx_start(adev); 6499 } 6500 6501 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6502 struct amdgpu_mqd_prop *prop) 6503 { 6504 struct v10_compute_mqd *mqd = m; 6505 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6506 uint32_t tmp; 6507 6508 mqd->header = 0xC0310800; 6509 mqd->compute_pipelinestat_enable = 0x00000001; 6510 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6511 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6512 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6513 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6514 mqd->compute_misc_reserved = 0x00000003; 6515 6516 eop_base_addr = prop->eop_gpu_addr >> 8; 6517 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6518 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6519 6520 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6521 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6522 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6523 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6524 6525 mqd->cp_hqd_eop_control = tmp; 6526 6527 /* enable doorbell? */ 6528 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6529 6530 if (prop->use_doorbell) { 6531 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6532 DOORBELL_OFFSET, prop->doorbell_index); 6533 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6534 DOORBELL_EN, 1); 6535 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6536 DOORBELL_SOURCE, 0); 6537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6538 DOORBELL_HIT, 0); 6539 } else { 6540 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6541 DOORBELL_EN, 0); 6542 } 6543 6544 mqd->cp_hqd_pq_doorbell_control = tmp; 6545 6546 /* disable the queue if it's active */ 6547 mqd->cp_hqd_dequeue_request = 0; 6548 mqd->cp_hqd_pq_rptr = 0; 6549 mqd->cp_hqd_pq_wptr_lo = 0; 6550 mqd->cp_hqd_pq_wptr_hi = 0; 6551 6552 /* set the pointer to the MQD */ 6553 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6554 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6555 6556 /* set MQD vmid to 0 */ 6557 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6558 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6559 mqd->cp_mqd_control = tmp; 6560 6561 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6562 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6563 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6564 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6565 6566 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6567 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6568 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6569 (order_base_2(prop->queue_size / 4) - 1)); 6570 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6571 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6572 #ifdef __BIG_ENDIAN 6573 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6574 #endif 6575 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 6576 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6577 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6578 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6579 mqd->cp_hqd_pq_control = tmp; 6580 6581 /* set the wb address whether it's enabled or not */ 6582 wb_gpu_addr = prop->rptr_gpu_addr; 6583 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6584 mqd->cp_hqd_pq_rptr_report_addr_hi = 6585 upper_32_bits(wb_gpu_addr) & 0xffff; 6586 6587 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6588 wb_gpu_addr = prop->wptr_gpu_addr; 6589 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6590 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6591 6592 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6593 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6594 6595 /* set the vmid for the queue */ 6596 mqd->cp_hqd_vmid = 0; 6597 6598 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6599 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6600 mqd->cp_hqd_persistent_state = tmp; 6601 6602 /* set MIN_IB_AVAIL_SIZE */ 6603 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6604 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6605 mqd->cp_hqd_ib_control = tmp; 6606 6607 /* set static priority for a compute queue/ring */ 6608 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6609 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6610 6611 mqd->cp_hqd_active = prop->hqd_active; 6612 6613 return 0; 6614 } 6615 6616 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6617 { 6618 struct amdgpu_device *adev = ring->adev; 6619 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6620 int j; 6621 6622 /* inactivate the queue */ 6623 if (amdgpu_sriov_vf(adev)) 6624 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6625 6626 /* disable wptr polling */ 6627 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6628 6629 /* disable the queue if it's active */ 6630 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6631 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6632 for (j = 0; j < adev->usec_timeout; j++) { 6633 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6634 break; 6635 udelay(1); 6636 } 6637 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6638 mqd->cp_hqd_dequeue_request); 6639 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6640 mqd->cp_hqd_pq_rptr); 6641 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6642 mqd->cp_hqd_pq_wptr_lo); 6643 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6644 mqd->cp_hqd_pq_wptr_hi); 6645 } 6646 6647 /* disable doorbells */ 6648 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6649 6650 /* write the EOP addr */ 6651 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6652 mqd->cp_hqd_eop_base_addr_lo); 6653 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6654 mqd->cp_hqd_eop_base_addr_hi); 6655 6656 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6657 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6658 mqd->cp_hqd_eop_control); 6659 6660 /* set the pointer to the MQD */ 6661 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6662 mqd->cp_mqd_base_addr_lo); 6663 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6664 mqd->cp_mqd_base_addr_hi); 6665 6666 /* set MQD vmid to 0 */ 6667 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6668 mqd->cp_mqd_control); 6669 6670 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6671 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6672 mqd->cp_hqd_pq_base_lo); 6673 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6674 mqd->cp_hqd_pq_base_hi); 6675 6676 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6677 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6678 mqd->cp_hqd_pq_control); 6679 6680 /* set the wb address whether it's enabled or not */ 6681 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6682 mqd->cp_hqd_pq_rptr_report_addr_lo); 6683 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6684 mqd->cp_hqd_pq_rptr_report_addr_hi); 6685 6686 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6687 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6688 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6689 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6690 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6691 6692 /* enable the doorbell if requested */ 6693 if (ring->use_doorbell) { 6694 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6695 (adev->doorbell_index.kiq * 2) << 2); 6696 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6697 (adev->doorbell_index.userqueue_end * 2) << 2); 6698 } 6699 6700 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6701 mqd->cp_hqd_pq_doorbell_control); 6702 6703 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6704 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6705 mqd->cp_hqd_pq_wptr_lo); 6706 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6707 mqd->cp_hqd_pq_wptr_hi); 6708 6709 /* set the vmid for the queue */ 6710 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6711 6712 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6713 mqd->cp_hqd_persistent_state); 6714 6715 /* activate the queue */ 6716 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6717 mqd->cp_hqd_active); 6718 6719 if (ring->use_doorbell) 6720 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6721 6722 return 0; 6723 } 6724 6725 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6726 { 6727 struct amdgpu_device *adev = ring->adev; 6728 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6729 6730 gfx_v10_0_kiq_setting(ring); 6731 6732 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6733 /* reset MQD to a clean status */ 6734 if (adev->gfx.kiq[0].mqd_backup) 6735 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); 6736 6737 /* reset ring buffer */ 6738 ring->wptr = 0; 6739 amdgpu_ring_clear_ring(ring); 6740 6741 mutex_lock(&adev->srbm_mutex); 6742 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6743 gfx_v10_0_kiq_init_register(ring); 6744 nv_grbm_select(adev, 0, 0, 0, 0); 6745 mutex_unlock(&adev->srbm_mutex); 6746 } else { 6747 memset((void *)mqd, 0, sizeof(*mqd)); 6748 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 6749 amdgpu_ring_clear_ring(ring); 6750 mutex_lock(&adev->srbm_mutex); 6751 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6752 amdgpu_ring_init_mqd(ring); 6753 gfx_v10_0_kiq_init_register(ring); 6754 nv_grbm_select(adev, 0, 0, 0, 0); 6755 mutex_unlock(&adev->srbm_mutex); 6756 6757 if (adev->gfx.kiq[0].mqd_backup) 6758 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); 6759 } 6760 6761 return 0; 6762 } 6763 6764 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6765 { 6766 struct amdgpu_device *adev = ring->adev; 6767 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6768 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6769 6770 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6771 memset((void *)mqd, 0, sizeof(*mqd)); 6772 mutex_lock(&adev->srbm_mutex); 6773 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6774 amdgpu_ring_init_mqd(ring); 6775 nv_grbm_select(adev, 0, 0, 0, 0); 6776 mutex_unlock(&adev->srbm_mutex); 6777 6778 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6779 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6780 } else { 6781 /* restore MQD to a clean status */ 6782 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6783 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6784 /* reset ring buffer */ 6785 ring->wptr = 0; 6786 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6787 amdgpu_ring_clear_ring(ring); 6788 } 6789 6790 return 0; 6791 } 6792 6793 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6794 { 6795 struct amdgpu_ring *ring; 6796 int r; 6797 6798 ring = &adev->gfx.kiq[0].ring; 6799 6800 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6801 if (unlikely(r != 0)) 6802 return r; 6803 6804 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6805 if (unlikely(r != 0)) { 6806 amdgpu_bo_unreserve(ring->mqd_obj); 6807 return r; 6808 } 6809 6810 gfx_v10_0_kiq_init_queue(ring); 6811 amdgpu_bo_kunmap(ring->mqd_obj); 6812 ring->mqd_ptr = NULL; 6813 amdgpu_bo_unreserve(ring->mqd_obj); 6814 return 0; 6815 } 6816 6817 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6818 { 6819 struct amdgpu_ring *ring = NULL; 6820 int r = 0, i; 6821 6822 gfx_v10_0_cp_compute_enable(adev, true); 6823 6824 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6825 ring = &adev->gfx.compute_ring[i]; 6826 6827 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6828 if (unlikely(r != 0)) 6829 goto done; 6830 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6831 if (!r) { 6832 r = gfx_v10_0_kcq_init_queue(ring); 6833 amdgpu_bo_kunmap(ring->mqd_obj); 6834 ring->mqd_ptr = NULL; 6835 } 6836 amdgpu_bo_unreserve(ring->mqd_obj); 6837 if (r) 6838 goto done; 6839 } 6840 6841 r = amdgpu_gfx_enable_kcq(adev, 0); 6842 done: 6843 return r; 6844 } 6845 6846 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 6847 { 6848 int r, i; 6849 struct amdgpu_ring *ring; 6850 6851 if (!(adev->flags & AMD_IS_APU)) 6852 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 6853 6854 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 6855 /* legacy firmware loading */ 6856 r = gfx_v10_0_cp_gfx_load_microcode(adev); 6857 if (r) 6858 return r; 6859 6860 r = gfx_v10_0_cp_compute_load_microcode(adev); 6861 if (r) 6862 return r; 6863 } 6864 6865 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 6866 r = amdgpu_mes_kiq_hw_init(adev); 6867 else 6868 r = gfx_v10_0_kiq_resume(adev); 6869 if (r) 6870 return r; 6871 6872 r = gfx_v10_0_kcq_resume(adev); 6873 if (r) 6874 return r; 6875 6876 if (!amdgpu_async_gfx_ring) { 6877 r = gfx_v10_0_cp_gfx_resume(adev); 6878 if (r) 6879 return r; 6880 } else { 6881 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 6882 if (r) 6883 return r; 6884 } 6885 6886 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6887 ring = &adev->gfx.gfx_ring[i]; 6888 r = amdgpu_ring_test_helper(ring); 6889 if (r) 6890 return r; 6891 } 6892 6893 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6894 ring = &adev->gfx.compute_ring[i]; 6895 r = amdgpu_ring_test_helper(ring); 6896 if (r) 6897 return r; 6898 } 6899 6900 return 0; 6901 } 6902 6903 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 6904 { 6905 gfx_v10_0_cp_gfx_enable(adev, enable); 6906 gfx_v10_0_cp_compute_enable(adev, enable); 6907 } 6908 6909 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 6910 { 6911 uint32_t data, pattern = 0xDEADBEEF; 6912 6913 /* 6914 * check if mmVGT_ESGS_RING_SIZE_UMD 6915 * has been remapped to mmVGT_ESGS_RING_SIZE 6916 */ 6917 switch (adev->ip_versions[GC_HWIP][0]) { 6918 case IP_VERSION(10, 3, 0): 6919 case IP_VERSION(10, 3, 2): 6920 case IP_VERSION(10, 3, 4): 6921 case IP_VERSION(10, 3, 5): 6922 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 6923 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 6924 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6925 6926 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 6927 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6928 return true; 6929 } 6930 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 6931 break; 6932 case IP_VERSION(10, 3, 1): 6933 case IP_VERSION(10, 3, 3): 6934 case IP_VERSION(10, 3, 6): 6935 case IP_VERSION(10, 3, 7): 6936 return true; 6937 default: 6938 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 6939 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 6940 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 6941 6942 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 6943 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 6944 return true; 6945 } 6946 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 6947 break; 6948 } 6949 6950 return false; 6951 } 6952 6953 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 6954 { 6955 uint32_t data; 6956 6957 if (amdgpu_sriov_vf(adev)) 6958 return; 6959 6960 /* 6961 * Initialize cam_index to 0 6962 * index will auto-inc after each data writing 6963 */ 6964 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 6965 6966 switch (adev->ip_versions[GC_HWIP][0]) { 6967 case IP_VERSION(10, 3, 0): 6968 case IP_VERSION(10, 3, 2): 6969 case IP_VERSION(10, 3, 1): 6970 case IP_VERSION(10, 3, 4): 6971 case IP_VERSION(10, 3, 5): 6972 case IP_VERSION(10, 3, 6): 6973 case IP_VERSION(10, 3, 3): 6974 case IP_VERSION(10, 3, 7): 6975 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 6976 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 6977 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6978 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 6979 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6980 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6981 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 6982 6983 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 6984 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 6985 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6986 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 6987 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6988 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6989 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 6990 6991 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 6992 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 6993 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 6994 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 6995 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 6996 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 6997 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 6998 6999 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7000 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7001 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7002 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7003 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7004 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7005 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7006 7007 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7008 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7009 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7010 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7011 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7012 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7013 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7014 7015 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7016 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7017 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7018 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7019 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7020 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7021 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7022 7023 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7024 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7025 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7026 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7027 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7028 break; 7029 default: 7030 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7031 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7032 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7033 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7034 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7035 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7036 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7037 7038 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7039 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7040 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7041 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7042 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7043 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7044 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7045 7046 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7047 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7048 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7049 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7050 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7051 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7052 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7053 7054 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7055 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7056 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7057 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7058 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7059 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7060 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7061 7062 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7063 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7064 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7065 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7066 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7067 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7068 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7069 7070 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7071 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7072 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7073 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7074 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7075 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7076 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7077 7078 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7079 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7080 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7081 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7082 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7083 break; 7084 } 7085 7086 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7087 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7088 } 7089 7090 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7091 { 7092 uint32_t data; 7093 7094 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7095 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7096 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7097 7098 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7099 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7100 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7101 } 7102 7103 static int gfx_v10_0_hw_init(void *handle) 7104 { 7105 int r; 7106 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7107 7108 if (!amdgpu_emu_mode) 7109 gfx_v10_0_init_golden_registers(adev); 7110 7111 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7112 /** 7113 * For gfx 10, rlc firmware loading relies on smu firmware is 7114 * loaded firstly, so in direct type, it has to load smc ucode 7115 * here before rlc. 7116 */ 7117 if (!(adev->flags & AMD_IS_APU)) { 7118 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7119 if (r) 7120 return r; 7121 } 7122 gfx_v10_0_disable_gpa_mode(adev); 7123 } 7124 7125 /* if GRBM CAM not remapped, set up the remapping */ 7126 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7127 gfx_v10_0_setup_grbm_cam_remapping(adev); 7128 7129 gfx_v10_0_constants_init(adev); 7130 7131 r = gfx_v10_0_rlc_resume(adev); 7132 if (r) 7133 return r; 7134 7135 /* 7136 * init golden registers and rlc resume may override some registers, 7137 * reconfig them here 7138 */ 7139 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) || 7140 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) || 7141 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 7142 gfx_v10_0_tcp_harvest(adev); 7143 7144 r = gfx_v10_0_cp_resume(adev); 7145 if (r) 7146 return r; 7147 7148 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 7149 gfx_v10_3_program_pbb_mode(adev); 7150 7151 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 7152 gfx_v10_3_set_power_brake_sequence(adev); 7153 7154 return r; 7155 } 7156 7157 static int gfx_v10_0_hw_fini(void *handle) 7158 { 7159 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7160 7161 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7162 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7163 7164 if (!adev->no_hw_access) { 7165 if (amdgpu_async_gfx_ring) { 7166 if (amdgpu_gfx_disable_kgq(adev, 0)) 7167 DRM_ERROR("KGQ disable failed\n"); 7168 } 7169 7170 if (amdgpu_gfx_disable_kcq(adev, 0)) 7171 DRM_ERROR("KCQ disable failed\n"); 7172 } 7173 7174 if (amdgpu_sriov_vf(adev)) { 7175 gfx_v10_0_cp_gfx_enable(adev, false); 7176 /* Remove the steps of clearing KIQ position. 7177 * It causes GFX hang when another Win guest is rendering. 7178 */ 7179 return 0; 7180 } 7181 gfx_v10_0_cp_enable(adev, false); 7182 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7183 7184 return 0; 7185 } 7186 7187 static int gfx_v10_0_suspend(void *handle) 7188 { 7189 return gfx_v10_0_hw_fini(handle); 7190 } 7191 7192 static int gfx_v10_0_resume(void *handle) 7193 { 7194 return gfx_v10_0_hw_init(handle); 7195 } 7196 7197 static bool gfx_v10_0_is_idle(void *handle) 7198 { 7199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7200 7201 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7202 GRBM_STATUS, GUI_ACTIVE)) 7203 return false; 7204 else 7205 return true; 7206 } 7207 7208 static int gfx_v10_0_wait_for_idle(void *handle) 7209 { 7210 unsigned int i; 7211 u32 tmp; 7212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7213 7214 for (i = 0; i < adev->usec_timeout; i++) { 7215 /* read MC_STATUS */ 7216 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7217 GRBM_STATUS__GUI_ACTIVE_MASK; 7218 7219 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7220 return 0; 7221 udelay(1); 7222 } 7223 return -ETIMEDOUT; 7224 } 7225 7226 static int gfx_v10_0_soft_reset(void *handle) 7227 { 7228 u32 grbm_soft_reset = 0; 7229 u32 tmp; 7230 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7231 7232 /* GRBM_STATUS */ 7233 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7234 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7235 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7236 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7237 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7238 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7239 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7240 GRBM_SOFT_RESET, SOFT_RESET_CP, 7241 1); 7242 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7243 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7244 1); 7245 } 7246 7247 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7248 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7249 GRBM_SOFT_RESET, SOFT_RESET_CP, 7250 1); 7251 } 7252 7253 /* GRBM_STATUS2 */ 7254 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7255 switch (adev->ip_versions[GC_HWIP][0]) { 7256 case IP_VERSION(10, 3, 0): 7257 case IP_VERSION(10, 3, 2): 7258 case IP_VERSION(10, 3, 1): 7259 case IP_VERSION(10, 3, 4): 7260 case IP_VERSION(10, 3, 5): 7261 case IP_VERSION(10, 3, 6): 7262 case IP_VERSION(10, 3, 3): 7263 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7264 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7265 GRBM_SOFT_RESET, 7266 SOFT_RESET_RLC, 7267 1); 7268 break; 7269 default: 7270 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7271 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7272 GRBM_SOFT_RESET, 7273 SOFT_RESET_RLC, 7274 1); 7275 break; 7276 } 7277 7278 if (grbm_soft_reset) { 7279 /* stop the rlc */ 7280 gfx_v10_0_rlc_stop(adev); 7281 7282 /* Disable GFX parsing/prefetching */ 7283 gfx_v10_0_cp_gfx_enable(adev, false); 7284 7285 /* Disable MEC parsing/prefetching */ 7286 gfx_v10_0_cp_compute_enable(adev, false); 7287 7288 if (grbm_soft_reset) { 7289 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7290 tmp |= grbm_soft_reset; 7291 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7292 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7293 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7294 7295 udelay(50); 7296 7297 tmp &= ~grbm_soft_reset; 7298 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7299 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7300 } 7301 7302 /* Wait a little for things to settle down */ 7303 udelay(50); 7304 } 7305 return 0; 7306 } 7307 7308 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7309 { 7310 uint64_t clock, clock_lo, clock_hi, hi_check; 7311 7312 switch (adev->ip_versions[GC_HWIP][0]) { 7313 case IP_VERSION(10, 3, 1): 7314 case IP_VERSION(10, 3, 3): 7315 case IP_VERSION(10, 3, 7): 7316 preempt_disable(); 7317 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7318 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7319 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7320 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7321 * roughly every 42 seconds. 7322 */ 7323 if (hi_check != clock_hi) { 7324 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7325 clock_hi = hi_check; 7326 } 7327 preempt_enable(); 7328 clock = clock_lo | (clock_hi << 32ULL); 7329 break; 7330 case IP_VERSION(10, 3, 6): 7331 preempt_disable(); 7332 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7333 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7334 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7335 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7336 * roughly every 42 seconds. 7337 */ 7338 if (hi_check != clock_hi) { 7339 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7340 clock_hi = hi_check; 7341 } 7342 preempt_enable(); 7343 clock = clock_lo | (clock_hi << 32ULL); 7344 break; 7345 default: 7346 preempt_disable(); 7347 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7348 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7349 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7350 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7351 * roughly every 42 seconds. 7352 */ 7353 if (hi_check != clock_hi) { 7354 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7355 clock_hi = hi_check; 7356 } 7357 preempt_enable(); 7358 clock = clock_lo | (clock_hi << 32ULL); 7359 break; 7360 } 7361 return clock; 7362 } 7363 7364 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7365 uint32_t vmid, 7366 uint32_t gds_base, uint32_t gds_size, 7367 uint32_t gws_base, uint32_t gws_size, 7368 uint32_t oa_base, uint32_t oa_size) 7369 { 7370 struct amdgpu_device *adev = ring->adev; 7371 7372 /* GDS Base */ 7373 gfx_v10_0_write_data_to_reg(ring, 0, false, 7374 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7375 gds_base); 7376 7377 /* GDS Size */ 7378 gfx_v10_0_write_data_to_reg(ring, 0, false, 7379 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7380 gds_size); 7381 7382 /* GWS */ 7383 gfx_v10_0_write_data_to_reg(ring, 0, false, 7384 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7385 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7386 7387 /* OA */ 7388 gfx_v10_0_write_data_to_reg(ring, 0, false, 7389 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7390 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7391 } 7392 7393 static int gfx_v10_0_early_init(void *handle) 7394 { 7395 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7396 7397 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7398 7399 switch (adev->ip_versions[GC_HWIP][0]) { 7400 case IP_VERSION(10, 1, 10): 7401 case IP_VERSION(10, 1, 1): 7402 case IP_VERSION(10, 1, 2): 7403 case IP_VERSION(10, 1, 3): 7404 case IP_VERSION(10, 1, 4): 7405 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7406 break; 7407 case IP_VERSION(10, 3, 0): 7408 case IP_VERSION(10, 3, 2): 7409 case IP_VERSION(10, 3, 1): 7410 case IP_VERSION(10, 3, 4): 7411 case IP_VERSION(10, 3, 5): 7412 case IP_VERSION(10, 3, 6): 7413 case IP_VERSION(10, 3, 3): 7414 case IP_VERSION(10, 3, 7): 7415 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7416 break; 7417 default: 7418 break; 7419 } 7420 7421 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7422 AMDGPU_MAX_COMPUTE_RINGS); 7423 7424 gfx_v10_0_set_kiq_pm4_funcs(adev); 7425 gfx_v10_0_set_ring_funcs(adev); 7426 gfx_v10_0_set_irq_funcs(adev); 7427 gfx_v10_0_set_gds_init(adev); 7428 gfx_v10_0_set_rlc_funcs(adev); 7429 gfx_v10_0_set_mqd_funcs(adev); 7430 7431 /* init rlcg reg access ctrl */ 7432 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7433 7434 return gfx_v10_0_init_microcode(adev); 7435 } 7436 7437 static int gfx_v10_0_late_init(void *handle) 7438 { 7439 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7440 int r; 7441 7442 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7443 if (r) 7444 return r; 7445 7446 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7447 if (r) 7448 return r; 7449 7450 return 0; 7451 } 7452 7453 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7454 { 7455 uint32_t rlc_cntl; 7456 7457 /* if RLC is not enabled, do nothing */ 7458 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7459 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7460 } 7461 7462 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 7463 { 7464 uint32_t data; 7465 unsigned int i; 7466 7467 data = RLC_SAFE_MODE__CMD_MASK; 7468 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7469 7470 switch (adev->ip_versions[GC_HWIP][0]) { 7471 case IP_VERSION(10, 3, 0): 7472 case IP_VERSION(10, 3, 2): 7473 case IP_VERSION(10, 3, 1): 7474 case IP_VERSION(10, 3, 4): 7475 case IP_VERSION(10, 3, 5): 7476 case IP_VERSION(10, 3, 6): 7477 case IP_VERSION(10, 3, 3): 7478 case IP_VERSION(10, 3, 7): 7479 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7480 7481 /* wait for RLC_SAFE_MODE */ 7482 for (i = 0; i < adev->usec_timeout; i++) { 7483 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7484 RLC_SAFE_MODE, CMD)) 7485 break; 7486 udelay(1); 7487 } 7488 break; 7489 default: 7490 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7491 7492 /* wait for RLC_SAFE_MODE */ 7493 for (i = 0; i < adev->usec_timeout; i++) { 7494 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7495 RLC_SAFE_MODE, CMD)) 7496 break; 7497 udelay(1); 7498 } 7499 break; 7500 } 7501 } 7502 7503 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 7504 { 7505 uint32_t data; 7506 7507 data = RLC_SAFE_MODE__CMD_MASK; 7508 switch (adev->ip_versions[GC_HWIP][0]) { 7509 case IP_VERSION(10, 3, 0): 7510 case IP_VERSION(10, 3, 2): 7511 case IP_VERSION(10, 3, 1): 7512 case IP_VERSION(10, 3, 4): 7513 case IP_VERSION(10, 3, 5): 7514 case IP_VERSION(10, 3, 6): 7515 case IP_VERSION(10, 3, 3): 7516 case IP_VERSION(10, 3, 7): 7517 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7518 break; 7519 default: 7520 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7521 break; 7522 } 7523 } 7524 7525 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7526 bool enable) 7527 { 7528 uint32_t data, def; 7529 7530 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7531 return; 7532 7533 /* It is disabled by HW by default */ 7534 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7535 /* 0 - Disable some blocks' MGCG */ 7536 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7537 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7538 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7539 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7540 7541 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7542 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7543 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7544 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7545 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7546 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7547 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7548 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7549 7550 if (def != data) 7551 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7552 7553 /* MGLS is a global flag to control all MGLS in GFX */ 7554 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7555 /* 2 - RLC memory Light sleep */ 7556 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7557 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7558 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7559 if (def != data) 7560 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7561 } 7562 /* 3 - CP memory Light sleep */ 7563 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7564 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7565 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7566 if (def != data) 7567 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7568 } 7569 } 7570 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7571 /* 1 - MGCG_OVERRIDE */ 7572 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7573 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7574 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7575 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7576 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7577 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7578 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7579 if (def != data) 7580 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7581 7582 /* 2 - disable MGLS in CP */ 7583 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7584 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7585 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7586 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7587 } 7588 7589 /* 3 - disable MGLS in RLC */ 7590 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7591 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7592 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7593 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7594 } 7595 7596 } 7597 } 7598 7599 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7600 bool enable) 7601 { 7602 uint32_t data, def; 7603 7604 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7605 return; 7606 7607 /* Enable 3D CGCG/CGLS */ 7608 if (enable) { 7609 /* write cmd to clear cgcg/cgls ov */ 7610 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7611 7612 /* unset CGCG override */ 7613 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7614 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7615 7616 /* update CGCG and CGLS override bits */ 7617 if (def != data) 7618 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7619 7620 /* enable 3Dcgcg FSM(0x0000363f) */ 7621 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7622 data = 0; 7623 7624 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7625 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7626 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7627 7628 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7629 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7630 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7631 7632 if (def != data) 7633 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7634 7635 /* set IDLE_POLL_COUNT(0x00900100) */ 7636 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7637 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7638 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7639 if (def != data) 7640 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7641 } else { 7642 /* Disable CGCG/CGLS */ 7643 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7644 7645 /* disable cgcg, cgls should be disabled */ 7646 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7647 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7648 7649 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7650 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7651 7652 /* disable cgcg and cgls in FSM */ 7653 if (def != data) 7654 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7655 } 7656 } 7657 7658 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7659 bool enable) 7660 { 7661 uint32_t def, data; 7662 7663 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7664 return; 7665 7666 if (enable) { 7667 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7668 7669 /* unset CGCG override */ 7670 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7671 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7672 7673 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7674 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7675 7676 /* update CGCG and CGLS override bits */ 7677 if (def != data) 7678 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7679 7680 /* enable cgcg FSM(0x0000363F) */ 7681 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7682 data = 0; 7683 7684 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7685 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7686 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7687 7688 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7689 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7690 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7691 7692 if (def != data) 7693 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7694 7695 /* set IDLE_POLL_COUNT(0x00900100) */ 7696 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7697 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7698 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7699 if (def != data) 7700 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7701 } else { 7702 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7703 7704 /* reset CGCG/CGLS bits */ 7705 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7706 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7707 7708 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7709 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7710 7711 /* disable cgcg and cgls in FSM */ 7712 if (def != data) 7713 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7714 } 7715 } 7716 7717 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7718 bool enable) 7719 { 7720 uint32_t def, data; 7721 7722 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 7723 return; 7724 7725 if (enable) { 7726 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7727 /* unset FGCG override */ 7728 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7729 /* update FGCG override bits */ 7730 if (def != data) 7731 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7732 7733 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7734 /* unset RLC SRAM CLK GATER override */ 7735 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7736 /* update RLC SRAM CLK GATER override bits */ 7737 if (def != data) 7738 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7739 } else { 7740 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7741 /* reset FGCG bits */ 7742 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7743 /* disable FGCG*/ 7744 if (def != data) 7745 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7746 7747 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7748 /* reset RLC SRAM CLK GATER bits */ 7749 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7750 /* disable RLC SRAM CLK*/ 7751 if (def != data) 7752 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7753 } 7754 } 7755 7756 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 7757 { 7758 uint32_t reg_data = 0; 7759 uint32_t reg_idx = 0; 7760 uint32_t i; 7761 7762 const uint32_t tcp_ctrl_regs[] = { 7763 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7764 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7765 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7766 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7767 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7768 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7769 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7770 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7771 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7772 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7773 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 7774 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 7775 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7776 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7777 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7778 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7779 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7780 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7781 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7782 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7783 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7784 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7785 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 7786 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 7787 }; 7788 7789 const uint32_t tcp_ctrl_regs_nv12[] = { 7790 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7791 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7792 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7793 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7794 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7795 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7796 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7797 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7798 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7799 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7800 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7801 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7802 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7803 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7804 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7805 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7806 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7807 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7808 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7809 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7810 }; 7811 7812 const uint32_t sm_ctlr_regs[] = { 7813 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 7814 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 7815 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 7816 mmCGTS_SA1_QUAD1_SM_CTRL_REG 7817 }; 7818 7819 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 7820 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 7821 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7822 tcp_ctrl_regs_nv12[i]; 7823 reg_data = RREG32(reg_idx); 7824 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7825 WREG32(reg_idx, reg_data); 7826 } 7827 } else { 7828 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 7829 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 7830 tcp_ctrl_regs[i]; 7831 reg_data = RREG32(reg_idx); 7832 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 7833 WREG32(reg_idx, reg_data); 7834 } 7835 } 7836 7837 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 7838 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 7839 sm_ctlr_regs[i]; 7840 reg_data = RREG32(reg_idx); 7841 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 7842 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 7843 WREG32(reg_idx, reg_data); 7844 } 7845 } 7846 7847 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 7848 bool enable) 7849 { 7850 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 7851 7852 if (enable) { 7853 /* enable FGCG firstly*/ 7854 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7855 /* CGCG/CGLS should be enabled after MGCG/MGLS 7856 * === MGCG + MGLS === 7857 */ 7858 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7859 /* === CGCG /CGLS for GFX 3D Only === */ 7860 gfx_v10_0_update_3d_clock_gating(adev, enable); 7861 /* === CGCG + CGLS === */ 7862 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7863 7864 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) || 7865 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) || 7866 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))) 7867 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 7868 } else { 7869 /* CGCG/CGLS should be disabled before MGCG/MGLS 7870 * === CGCG + CGLS === 7871 */ 7872 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 7873 /* === CGCG /CGLS for GFX 3D Only === */ 7874 gfx_v10_0_update_3d_clock_gating(adev, enable); 7875 /* === MGCG + MGLS === */ 7876 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 7877 /* disable fgcg at last*/ 7878 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 7879 } 7880 7881 if (adev->cg_flags & 7882 (AMD_CG_SUPPORT_GFX_MGCG | 7883 AMD_CG_SUPPORT_GFX_CGLS | 7884 AMD_CG_SUPPORT_GFX_CGCG | 7885 AMD_CG_SUPPORT_GFX_3D_CGCG | 7886 AMD_CG_SUPPORT_GFX_3D_CGLS)) 7887 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 7888 7889 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 7890 7891 return 0; 7892 } 7893 7894 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, 7895 unsigned int vmid) 7896 { 7897 u32 reg, data; 7898 7899 /* not for *_SOC15 */ 7900 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 7901 if (amdgpu_sriov_is_pp_one_vf(adev)) 7902 data = RREG32_NO_KIQ(reg); 7903 else 7904 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 7905 7906 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 7907 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 7908 7909 if (amdgpu_sriov_is_pp_one_vf(adev)) 7910 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 7911 else 7912 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 7913 } 7914 7915 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid) 7916 { 7917 amdgpu_gfx_off_ctrl(adev, false); 7918 7919 gfx_v10_0_update_spm_vmid_internal(adev, vmid); 7920 7921 amdgpu_gfx_off_ctrl(adev, true); 7922 } 7923 7924 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 7925 uint32_t offset, 7926 struct soc15_reg_rlcg *entries, int arr_size) 7927 { 7928 int i; 7929 uint32_t reg; 7930 7931 if (!entries) 7932 return false; 7933 7934 for (i = 0; i < arr_size; i++) { 7935 const struct soc15_reg_rlcg *entry; 7936 7937 entry = &entries[i]; 7938 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 7939 if (offset == reg) 7940 return true; 7941 } 7942 7943 return false; 7944 } 7945 7946 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 7947 { 7948 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 7949 } 7950 7951 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 7952 { 7953 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 7954 7955 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 7956 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7957 else 7958 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 7959 7960 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 7961 7962 /* 7963 * CGPG enablement required and the register to program the hysteresis value 7964 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 7965 * in refclk count. Note that RLC FW is modified to take 16 bits from 7966 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 7967 * 7968 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 7969 * of CGPG enablement starting point. 7970 * Power/performance team will optimize it and might give a new value later. 7971 */ 7972 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 7973 switch (adev->ip_versions[GC_HWIP][0]) { 7974 case IP_VERSION(10, 3, 1): 7975 case IP_VERSION(10, 3, 3): 7976 case IP_VERSION(10, 3, 6): 7977 case IP_VERSION(10, 3, 7): 7978 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 7979 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 7980 break; 7981 default: 7982 break; 7983 } 7984 } 7985 } 7986 7987 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 7988 { 7989 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 7990 7991 gfx_v10_cntl_power_gating(adev, enable); 7992 7993 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 7994 } 7995 7996 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 7997 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 7998 .set_safe_mode = gfx_v10_0_set_safe_mode, 7999 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8000 .init = gfx_v10_0_rlc_init, 8001 .get_csb_size = gfx_v10_0_get_csb_size, 8002 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8003 .resume = gfx_v10_0_rlc_resume, 8004 .stop = gfx_v10_0_rlc_stop, 8005 .reset = gfx_v10_0_rlc_reset, 8006 .start = gfx_v10_0_rlc_start, 8007 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8008 }; 8009 8010 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8011 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8012 .set_safe_mode = gfx_v10_0_set_safe_mode, 8013 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8014 .init = gfx_v10_0_rlc_init, 8015 .get_csb_size = gfx_v10_0_get_csb_size, 8016 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8017 .resume = gfx_v10_0_rlc_resume, 8018 .stop = gfx_v10_0_rlc_stop, 8019 .reset = gfx_v10_0_rlc_reset, 8020 .start = gfx_v10_0_rlc_start, 8021 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8022 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8023 }; 8024 8025 static int gfx_v10_0_set_powergating_state(void *handle, 8026 enum amd_powergating_state state) 8027 { 8028 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8029 bool enable = (state == AMD_PG_STATE_GATE); 8030 8031 if (amdgpu_sriov_vf(adev)) 8032 return 0; 8033 8034 switch (adev->ip_versions[GC_HWIP][0]) { 8035 case IP_VERSION(10, 1, 10): 8036 case IP_VERSION(10, 1, 1): 8037 case IP_VERSION(10, 1, 2): 8038 case IP_VERSION(10, 3, 0): 8039 case IP_VERSION(10, 3, 2): 8040 case IP_VERSION(10, 3, 4): 8041 case IP_VERSION(10, 3, 5): 8042 amdgpu_gfx_off_ctrl(adev, enable); 8043 break; 8044 case IP_VERSION(10, 3, 1): 8045 case IP_VERSION(10, 3, 3): 8046 case IP_VERSION(10, 3, 6): 8047 case IP_VERSION(10, 3, 7): 8048 if (!enable) 8049 amdgpu_gfx_off_ctrl(adev, false); 8050 8051 gfx_v10_cntl_pg(adev, enable); 8052 8053 if (enable) 8054 amdgpu_gfx_off_ctrl(adev, true); 8055 8056 break; 8057 default: 8058 break; 8059 } 8060 return 0; 8061 } 8062 8063 static int gfx_v10_0_set_clockgating_state(void *handle, 8064 enum amd_clockgating_state state) 8065 { 8066 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8067 8068 if (amdgpu_sriov_vf(adev)) 8069 return 0; 8070 8071 switch (adev->ip_versions[GC_HWIP][0]) { 8072 case IP_VERSION(10, 1, 10): 8073 case IP_VERSION(10, 1, 1): 8074 case IP_VERSION(10, 1, 2): 8075 case IP_VERSION(10, 3, 0): 8076 case IP_VERSION(10, 3, 2): 8077 case IP_VERSION(10, 3, 1): 8078 case IP_VERSION(10, 3, 4): 8079 case IP_VERSION(10, 3, 5): 8080 case IP_VERSION(10, 3, 6): 8081 case IP_VERSION(10, 3, 3): 8082 case IP_VERSION(10, 3, 7): 8083 gfx_v10_0_update_gfx_clock_gating(adev, 8084 state == AMD_CG_STATE_GATE); 8085 break; 8086 default: 8087 break; 8088 } 8089 return 0; 8090 } 8091 8092 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8093 { 8094 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8095 int data; 8096 8097 /* AMD_CG_SUPPORT_GFX_FGCG */ 8098 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8099 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8100 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8101 8102 /* AMD_CG_SUPPORT_GFX_MGCG */ 8103 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8104 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8105 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8106 8107 /* AMD_CG_SUPPORT_GFX_CGCG */ 8108 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8109 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8110 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8111 8112 /* AMD_CG_SUPPORT_GFX_CGLS */ 8113 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8114 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8115 8116 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8117 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8118 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8119 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8120 8121 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8122 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8123 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8124 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8125 8126 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8127 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8128 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8129 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8130 8131 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8132 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8133 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8134 } 8135 8136 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8137 { 8138 /* gfx10 is 32bit rptr*/ 8139 return *(uint32_t *)ring->rptr_cpu_addr; 8140 } 8141 8142 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8143 { 8144 struct amdgpu_device *adev = ring->adev; 8145 u64 wptr; 8146 8147 /* XXX check if swapping is necessary on BE */ 8148 if (ring->use_doorbell) { 8149 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8150 } else { 8151 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8152 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8153 } 8154 8155 return wptr; 8156 } 8157 8158 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8159 { 8160 struct amdgpu_device *adev = ring->adev; 8161 uint32_t *wptr_saved; 8162 uint32_t *is_queue_unmap; 8163 uint64_t aggregated_db_index; 8164 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 8165 uint64_t wptr_tmp; 8166 8167 if (ring->is_mes_queue) { 8168 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8169 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8170 sizeof(uint32_t)); 8171 aggregated_db_index = 8172 amdgpu_mes_get_aggregated_doorbell_index(adev, 8173 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8174 8175 wptr_tmp = ring->wptr & ring->buf_mask; 8176 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8177 *wptr_saved = wptr_tmp; 8178 /* assume doorbell always being used by mes mapped queue */ 8179 if (*is_queue_unmap) { 8180 WDOORBELL64(aggregated_db_index, wptr_tmp); 8181 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8182 } else { 8183 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8184 8185 if (*is_queue_unmap) 8186 WDOORBELL64(aggregated_db_index, wptr_tmp); 8187 } 8188 } else { 8189 if (ring->use_doorbell) { 8190 /* XXX check if swapping is necessary on BE */ 8191 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8192 ring->wptr); 8193 WDOORBELL64(ring->doorbell_index, ring->wptr); 8194 } else { 8195 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8196 lower_32_bits(ring->wptr)); 8197 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8198 upper_32_bits(ring->wptr)); 8199 } 8200 } 8201 } 8202 8203 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8204 { 8205 /* gfx10 hardware is 32bit rptr */ 8206 return *(uint32_t *)ring->rptr_cpu_addr; 8207 } 8208 8209 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8210 { 8211 u64 wptr; 8212 8213 /* XXX check if swapping is necessary on BE */ 8214 if (ring->use_doorbell) 8215 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8216 else 8217 BUG(); 8218 return wptr; 8219 } 8220 8221 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8222 { 8223 struct amdgpu_device *adev = ring->adev; 8224 uint32_t *wptr_saved; 8225 uint32_t *is_queue_unmap; 8226 uint64_t aggregated_db_index; 8227 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 8228 uint64_t wptr_tmp; 8229 8230 if (ring->is_mes_queue) { 8231 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8232 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8233 sizeof(uint32_t)); 8234 aggregated_db_index = 8235 amdgpu_mes_get_aggregated_doorbell_index(adev, 8236 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8237 8238 wptr_tmp = ring->wptr & ring->buf_mask; 8239 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8240 *wptr_saved = wptr_tmp; 8241 /* assume doorbell always used by mes mapped queue */ 8242 if (*is_queue_unmap) { 8243 WDOORBELL64(aggregated_db_index, wptr_tmp); 8244 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8245 } else { 8246 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8247 8248 if (*is_queue_unmap) 8249 WDOORBELL64(aggregated_db_index, wptr_tmp); 8250 } 8251 } else { 8252 /* XXX check if swapping is necessary on BE */ 8253 if (ring->use_doorbell) { 8254 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8255 ring->wptr); 8256 WDOORBELL64(ring->doorbell_index, ring->wptr); 8257 } else { 8258 BUG(); /* only DOORBELL method supported on gfx10 now */ 8259 } 8260 } 8261 } 8262 8263 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8264 { 8265 struct amdgpu_device *adev = ring->adev; 8266 u32 ref_and_mask, reg_mem_engine; 8267 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8268 8269 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8270 switch (ring->me) { 8271 case 1: 8272 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8273 break; 8274 case 2: 8275 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8276 break; 8277 default: 8278 return; 8279 } 8280 reg_mem_engine = 0; 8281 } else { 8282 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8283 reg_mem_engine = 1; /* pfp */ 8284 } 8285 8286 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8287 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8288 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8289 ref_and_mask, ref_and_mask, 0x20); 8290 } 8291 8292 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8293 struct amdgpu_job *job, 8294 struct amdgpu_ib *ib, 8295 uint32_t flags) 8296 { 8297 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8298 u32 header, control = 0; 8299 8300 if (ib->flags & AMDGPU_IB_FLAG_CE) 8301 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8302 else 8303 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8304 8305 control |= ib->length_dw | (vmid << 24); 8306 8307 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8308 control |= INDIRECT_BUFFER_PRE_ENB(1); 8309 8310 if (flags & AMDGPU_IB_PREEMPTED) 8311 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8312 8313 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8314 gfx_v10_0_ring_emit_de_meta(ring, 8315 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8316 } 8317 8318 if (ring->is_mes_queue) 8319 /* inherit vmid from mqd */ 8320 control |= 0x400000; 8321 8322 amdgpu_ring_write(ring, header); 8323 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8324 amdgpu_ring_write(ring, 8325 #ifdef __BIG_ENDIAN 8326 (2 << 0) | 8327 #endif 8328 lower_32_bits(ib->gpu_addr)); 8329 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8330 amdgpu_ring_write(ring, control); 8331 } 8332 8333 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8334 struct amdgpu_job *job, 8335 struct amdgpu_ib *ib, 8336 uint32_t flags) 8337 { 8338 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 8339 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8340 8341 if (ring->is_mes_queue) 8342 /* inherit vmid from mqd */ 8343 control |= 0x40000000; 8344 8345 /* Currently, there is a high possibility to get wave ID mismatch 8346 * between ME and GDS, leading to a hw deadlock, because ME generates 8347 * different wave IDs than the GDS expects. This situation happens 8348 * randomly when at least 5 compute pipes use GDS ordered append. 8349 * The wave IDs generated by ME are also wrong after suspend/resume. 8350 * Those are probably bugs somewhere else in the kernel driver. 8351 * 8352 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8353 * GDS to 0 for this ring (me/pipe). 8354 */ 8355 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8356 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8357 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8358 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8359 } 8360 8361 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8362 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8363 amdgpu_ring_write(ring, 8364 #ifdef __BIG_ENDIAN 8365 (2 << 0) | 8366 #endif 8367 lower_32_bits(ib->gpu_addr)); 8368 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8369 amdgpu_ring_write(ring, control); 8370 } 8371 8372 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8373 u64 seq, unsigned int flags) 8374 { 8375 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8376 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8377 8378 /* RELEASE_MEM - flush caches, send int */ 8379 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8380 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8381 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8382 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8383 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8384 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8385 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8386 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8387 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8388 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8389 8390 /* 8391 * the address should be Qword aligned if 64bit write, Dword 8392 * aligned if only send 32bit data low (discard data high) 8393 */ 8394 if (write64bit) 8395 BUG_ON(addr & 0x7); 8396 else 8397 BUG_ON(addr & 0x3); 8398 amdgpu_ring_write(ring, lower_32_bits(addr)); 8399 amdgpu_ring_write(ring, upper_32_bits(addr)); 8400 amdgpu_ring_write(ring, lower_32_bits(seq)); 8401 amdgpu_ring_write(ring, upper_32_bits(seq)); 8402 amdgpu_ring_write(ring, ring->is_mes_queue ? 8403 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 8404 } 8405 8406 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8407 { 8408 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8409 uint32_t seq = ring->fence_drv.sync_seq; 8410 uint64_t addr = ring->fence_drv.gpu_addr; 8411 8412 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8413 upper_32_bits(addr), seq, 0xffffffff, 4); 8414 } 8415 8416 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8417 uint16_t pasid, uint32_t flush_type, 8418 bool all_hub, uint8_t dst_sel) 8419 { 8420 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8421 amdgpu_ring_write(ring, 8422 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8423 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8424 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8425 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8426 } 8427 8428 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8429 unsigned int vmid, uint64_t pd_addr) 8430 { 8431 if (ring->is_mes_queue) 8432 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 8433 else 8434 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8435 8436 /* compute doesn't have PFP */ 8437 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8438 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8439 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8440 amdgpu_ring_write(ring, 0x0); 8441 } 8442 } 8443 8444 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8445 u64 seq, unsigned int flags) 8446 { 8447 struct amdgpu_device *adev = ring->adev; 8448 8449 /* we only allocate 32bit for each seq wb address */ 8450 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8451 8452 /* write fence seq to the "addr" */ 8453 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8454 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8455 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8456 amdgpu_ring_write(ring, lower_32_bits(addr)); 8457 amdgpu_ring_write(ring, upper_32_bits(addr)); 8458 amdgpu_ring_write(ring, lower_32_bits(seq)); 8459 8460 if (flags & AMDGPU_FENCE_FLAG_INT) { 8461 /* set register to trigger INT */ 8462 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8463 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8464 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8465 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8466 amdgpu_ring_write(ring, 0); 8467 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8468 } 8469 } 8470 8471 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8472 { 8473 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8474 amdgpu_ring_write(ring, 0); 8475 } 8476 8477 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8478 uint32_t flags) 8479 { 8480 uint32_t dw2 = 0; 8481 8482 if (ring->adev->gfx.mcbp) 8483 gfx_v10_0_ring_emit_ce_meta(ring, 8484 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8485 8486 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8487 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8488 /* set load_global_config & load_global_uconfig */ 8489 dw2 |= 0x8001; 8490 /* set load_cs_sh_regs */ 8491 dw2 |= 0x01000000; 8492 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8493 dw2 |= 0x10002; 8494 8495 /* set load_ce_ram if preamble presented */ 8496 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8497 dw2 |= 0x10000000; 8498 } else { 8499 /* still load_ce_ram if this is the first time preamble presented 8500 * although there is no context switch happens. 8501 */ 8502 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8503 dw2 |= 0x10000000; 8504 } 8505 8506 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8507 amdgpu_ring_write(ring, dw2); 8508 amdgpu_ring_write(ring, 0); 8509 } 8510 8511 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8512 { 8513 unsigned int ret; 8514 8515 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8516 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8517 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8518 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8519 ret = ring->wptr & ring->buf_mask; 8520 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8521 8522 return ret; 8523 } 8524 8525 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset) 8526 { 8527 unsigned int cur; 8528 8529 BUG_ON(offset > ring->buf_mask); 8530 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8531 8532 cur = (ring->wptr - 1) & ring->buf_mask; 8533 if (likely(cur > offset)) 8534 ring->ring[offset] = cur - offset; 8535 else 8536 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8537 } 8538 8539 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8540 { 8541 int i, r = 0; 8542 struct amdgpu_device *adev = ring->adev; 8543 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 8544 struct amdgpu_ring *kiq_ring = &kiq->ring; 8545 unsigned long flags; 8546 8547 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8548 return -EINVAL; 8549 8550 spin_lock_irqsave(&kiq->ring_lock, flags); 8551 8552 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8553 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8554 return -ENOMEM; 8555 } 8556 8557 /* assert preemption condition */ 8558 amdgpu_ring_set_preempt_cond_exec(ring, false); 8559 8560 /* assert IB preemption, emit the trailing fence */ 8561 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8562 ring->trail_fence_gpu_addr, 8563 ++ring->trail_seq); 8564 amdgpu_ring_commit(kiq_ring); 8565 8566 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8567 8568 /* poll the trailing fence */ 8569 for (i = 0; i < adev->usec_timeout; i++) { 8570 if (ring->trail_seq == 8571 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8572 break; 8573 udelay(1); 8574 } 8575 8576 if (i >= adev->usec_timeout) { 8577 r = -EINVAL; 8578 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8579 } 8580 8581 /* deassert preemption condition */ 8582 amdgpu_ring_set_preempt_cond_exec(ring, true); 8583 return r; 8584 } 8585 8586 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8587 { 8588 struct amdgpu_device *adev = ring->adev; 8589 struct v10_ce_ib_state ce_payload = {0}; 8590 uint64_t offset, ce_payload_gpu_addr; 8591 void *ce_payload_cpu_addr; 8592 int cnt; 8593 8594 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8595 8596 if (ring->is_mes_queue) { 8597 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8598 gfx[0].gfx_meta_data) + 8599 offsetof(struct v10_gfx_meta_data, ce_payload); 8600 ce_payload_gpu_addr = 8601 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8602 ce_payload_cpu_addr = 8603 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8604 } else { 8605 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8606 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8607 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8608 } 8609 8610 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8611 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8612 WRITE_DATA_DST_SEL(8) | 8613 WR_CONFIRM) | 8614 WRITE_DATA_CACHE_POLICY(0)); 8615 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8616 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8617 8618 if (resume) 8619 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8620 sizeof(ce_payload) >> 2); 8621 else 8622 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8623 sizeof(ce_payload) >> 2); 8624 } 8625 8626 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8627 { 8628 struct amdgpu_device *adev = ring->adev; 8629 struct v10_de_ib_state de_payload = {0}; 8630 uint64_t offset, gds_addr, de_payload_gpu_addr; 8631 void *de_payload_cpu_addr; 8632 int cnt; 8633 8634 if (ring->is_mes_queue) { 8635 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8636 gfx[0].gfx_meta_data) + 8637 offsetof(struct v10_gfx_meta_data, de_payload); 8638 de_payload_gpu_addr = 8639 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8640 de_payload_cpu_addr = 8641 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8642 8643 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8644 gfx[0].gds_backup) + 8645 offsetof(struct v10_gfx_meta_data, de_payload); 8646 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8647 } else { 8648 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8649 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8650 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8651 8652 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8653 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8654 PAGE_SIZE); 8655 } 8656 8657 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8658 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8659 8660 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8661 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8662 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8663 WRITE_DATA_DST_SEL(8) | 8664 WR_CONFIRM) | 8665 WRITE_DATA_CACHE_POLICY(0)); 8666 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8667 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8668 8669 if (resume) 8670 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8671 sizeof(de_payload) >> 2); 8672 else 8673 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8674 sizeof(de_payload) >> 2); 8675 } 8676 8677 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8678 bool secure) 8679 { 8680 uint32_t v = secure ? FRAME_TMZ : 0; 8681 8682 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8683 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8684 } 8685 8686 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8687 uint32_t reg_val_offs) 8688 { 8689 struct amdgpu_device *adev = ring->adev; 8690 8691 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8692 amdgpu_ring_write(ring, 0 | /* src: register*/ 8693 (5 << 8) | /* dst: memory */ 8694 (1 << 20)); /* write confirm */ 8695 amdgpu_ring_write(ring, reg); 8696 amdgpu_ring_write(ring, 0); 8697 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8698 reg_val_offs * 4)); 8699 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8700 reg_val_offs * 4)); 8701 } 8702 8703 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8704 uint32_t val) 8705 { 8706 uint32_t cmd = 0; 8707 8708 switch (ring->funcs->type) { 8709 case AMDGPU_RING_TYPE_GFX: 8710 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8711 break; 8712 case AMDGPU_RING_TYPE_KIQ: 8713 cmd = (1 << 16); /* no inc addr */ 8714 break; 8715 default: 8716 cmd = WR_CONFIRM; 8717 break; 8718 } 8719 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8720 amdgpu_ring_write(ring, cmd); 8721 amdgpu_ring_write(ring, reg); 8722 amdgpu_ring_write(ring, 0); 8723 amdgpu_ring_write(ring, val); 8724 } 8725 8726 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8727 uint32_t val, uint32_t mask) 8728 { 8729 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8730 } 8731 8732 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8733 uint32_t reg0, uint32_t reg1, 8734 uint32_t ref, uint32_t mask) 8735 { 8736 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8737 struct amdgpu_device *adev = ring->adev; 8738 bool fw_version_ok = false; 8739 8740 fw_version_ok = adev->gfx.cp_fw_write_wait; 8741 8742 if (fw_version_ok) 8743 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8744 ref, mask, 0x20); 8745 else 8746 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8747 ref, mask); 8748 } 8749 8750 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8751 unsigned int vmid) 8752 { 8753 struct amdgpu_device *adev = ring->adev; 8754 uint32_t value = 0; 8755 8756 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8757 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8758 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8759 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8760 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8761 } 8762 8763 static void 8764 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8765 uint32_t me, uint32_t pipe, 8766 enum amdgpu_interrupt_state state) 8767 { 8768 uint32_t cp_int_cntl, cp_int_cntl_reg; 8769 8770 if (!me) { 8771 switch (pipe) { 8772 case 0: 8773 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8774 break; 8775 case 1: 8776 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8777 break; 8778 default: 8779 DRM_DEBUG("invalid pipe %d\n", pipe); 8780 return; 8781 } 8782 } else { 8783 DRM_DEBUG("invalid me %d\n", me); 8784 return; 8785 } 8786 8787 switch (state) { 8788 case AMDGPU_IRQ_STATE_DISABLE: 8789 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8790 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8791 TIME_STAMP_INT_ENABLE, 0); 8792 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8793 break; 8794 case AMDGPU_IRQ_STATE_ENABLE: 8795 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8796 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8797 TIME_STAMP_INT_ENABLE, 1); 8798 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8799 break; 8800 default: 8801 break; 8802 } 8803 } 8804 8805 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8806 int me, int pipe, 8807 enum amdgpu_interrupt_state state) 8808 { 8809 u32 mec_int_cntl, mec_int_cntl_reg; 8810 8811 /* 8812 * amdgpu controls only the first MEC. That's why this function only 8813 * handles the setting of interrupts for this specific MEC. All other 8814 * pipes' interrupts are set by amdkfd. 8815 */ 8816 8817 if (me == 1) { 8818 switch (pipe) { 8819 case 0: 8820 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 8821 break; 8822 case 1: 8823 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 8824 break; 8825 case 2: 8826 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 8827 break; 8828 case 3: 8829 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 8830 break; 8831 default: 8832 DRM_DEBUG("invalid pipe %d\n", pipe); 8833 return; 8834 } 8835 } else { 8836 DRM_DEBUG("invalid me %d\n", me); 8837 return; 8838 } 8839 8840 switch (state) { 8841 case AMDGPU_IRQ_STATE_DISABLE: 8842 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8843 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8844 TIME_STAMP_INT_ENABLE, 0); 8845 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8846 break; 8847 case AMDGPU_IRQ_STATE_ENABLE: 8848 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8849 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 8850 TIME_STAMP_INT_ENABLE, 1); 8851 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 8852 break; 8853 default: 8854 break; 8855 } 8856 } 8857 8858 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 8859 struct amdgpu_irq_src *src, 8860 unsigned int type, 8861 enum amdgpu_interrupt_state state) 8862 { 8863 switch (type) { 8864 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 8865 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 8866 break; 8867 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 8868 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 8869 break; 8870 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 8871 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 8872 break; 8873 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 8874 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 8875 break; 8876 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 8877 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 8878 break; 8879 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 8880 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 8881 break; 8882 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 8883 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 8884 break; 8885 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 8886 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 8887 break; 8888 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 8889 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 8890 break; 8891 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 8892 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 8893 break; 8894 default: 8895 break; 8896 } 8897 return 0; 8898 } 8899 8900 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 8901 struct amdgpu_irq_src *source, 8902 struct amdgpu_iv_entry *entry) 8903 { 8904 int i; 8905 u8 me_id, pipe_id, queue_id; 8906 struct amdgpu_ring *ring; 8907 uint32_t mes_queue_id = entry->src_data[0]; 8908 8909 DRM_DEBUG("IH: CP EOP\n"); 8910 8911 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 8912 struct amdgpu_mes_queue *queue; 8913 8914 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 8915 8916 spin_lock(&adev->mes.queue_id_lock); 8917 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 8918 if (queue) { 8919 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 8920 amdgpu_fence_process(queue->ring); 8921 } 8922 spin_unlock(&adev->mes.queue_id_lock); 8923 } else { 8924 me_id = (entry->ring_id & 0x0c) >> 2; 8925 pipe_id = (entry->ring_id & 0x03) >> 0; 8926 queue_id = (entry->ring_id & 0x70) >> 4; 8927 8928 switch (me_id) { 8929 case 0: 8930 if (pipe_id == 0) 8931 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 8932 else 8933 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 8934 break; 8935 case 1: 8936 case 2: 8937 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 8938 ring = &adev->gfx.compute_ring[i]; 8939 /* Per-queue interrupt is supported for MEC starting from VI. 8940 * The interrupt can only be enabled/disabled per pipe instead 8941 * of per queue. 8942 */ 8943 if ((ring->me == me_id) && 8944 (ring->pipe == pipe_id) && 8945 (ring->queue == queue_id)) 8946 amdgpu_fence_process(ring); 8947 } 8948 break; 8949 } 8950 } 8951 8952 return 0; 8953 } 8954 8955 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 8956 struct amdgpu_irq_src *source, 8957 unsigned int type, 8958 enum amdgpu_interrupt_state state) 8959 { 8960 switch (state) { 8961 case AMDGPU_IRQ_STATE_DISABLE: 8962 case AMDGPU_IRQ_STATE_ENABLE: 8963 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8964 PRIV_REG_INT_ENABLE, 8965 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8966 break; 8967 default: 8968 break; 8969 } 8970 8971 return 0; 8972 } 8973 8974 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 8975 struct amdgpu_irq_src *source, 8976 unsigned int type, 8977 enum amdgpu_interrupt_state state) 8978 { 8979 switch (state) { 8980 case AMDGPU_IRQ_STATE_DISABLE: 8981 case AMDGPU_IRQ_STATE_ENABLE: 8982 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 8983 PRIV_INSTR_INT_ENABLE, 8984 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 8985 break; 8986 default: 8987 break; 8988 } 8989 8990 return 0; 8991 } 8992 8993 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 8994 struct amdgpu_iv_entry *entry) 8995 { 8996 u8 me_id, pipe_id, queue_id; 8997 struct amdgpu_ring *ring; 8998 int i; 8999 9000 me_id = (entry->ring_id & 0x0c) >> 2; 9001 pipe_id = (entry->ring_id & 0x03) >> 0; 9002 queue_id = (entry->ring_id & 0x70) >> 4; 9003 9004 switch (me_id) { 9005 case 0: 9006 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9007 ring = &adev->gfx.gfx_ring[i]; 9008 /* we only enabled 1 gfx queue per pipe for now */ 9009 if (ring->me == me_id && ring->pipe == pipe_id) 9010 drm_sched_fault(&ring->sched); 9011 } 9012 break; 9013 case 1: 9014 case 2: 9015 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9016 ring = &adev->gfx.compute_ring[i]; 9017 if (ring->me == me_id && ring->pipe == pipe_id && 9018 ring->queue == queue_id) 9019 drm_sched_fault(&ring->sched); 9020 } 9021 break; 9022 default: 9023 BUG(); 9024 } 9025 } 9026 9027 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9028 struct amdgpu_irq_src *source, 9029 struct amdgpu_iv_entry *entry) 9030 { 9031 DRM_ERROR("Illegal register access in command stream\n"); 9032 gfx_v10_0_handle_priv_fault(adev, entry); 9033 return 0; 9034 } 9035 9036 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9037 struct amdgpu_irq_src *source, 9038 struct amdgpu_iv_entry *entry) 9039 { 9040 DRM_ERROR("Illegal instruction in command stream\n"); 9041 gfx_v10_0_handle_priv_fault(adev, entry); 9042 return 0; 9043 } 9044 9045 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9046 struct amdgpu_irq_src *src, 9047 unsigned int type, 9048 enum amdgpu_interrupt_state state) 9049 { 9050 uint32_t tmp, target; 9051 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9052 9053 if (ring->me == 1) 9054 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9055 else 9056 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9057 target += ring->pipe; 9058 9059 switch (type) { 9060 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9061 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9062 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9063 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9064 GENERIC2_INT_ENABLE, 0); 9065 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9066 9067 tmp = RREG32_SOC15_IP(GC, target); 9068 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9069 GENERIC2_INT_ENABLE, 0); 9070 WREG32_SOC15_IP(GC, target, tmp); 9071 } else { 9072 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9073 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9074 GENERIC2_INT_ENABLE, 1); 9075 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9076 9077 tmp = RREG32_SOC15_IP(GC, target); 9078 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9079 GENERIC2_INT_ENABLE, 1); 9080 WREG32_SOC15_IP(GC, target, tmp); 9081 } 9082 break; 9083 default: 9084 BUG(); /* kiq only support GENERIC2_INT now */ 9085 break; 9086 } 9087 return 0; 9088 } 9089 9090 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9091 struct amdgpu_irq_src *source, 9092 struct amdgpu_iv_entry *entry) 9093 { 9094 u8 me_id, pipe_id, queue_id; 9095 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring); 9096 9097 me_id = (entry->ring_id & 0x0c) >> 2; 9098 pipe_id = (entry->ring_id & 0x03) >> 0; 9099 queue_id = (entry->ring_id & 0x70) >> 4; 9100 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9101 me_id, pipe_id, queue_id); 9102 9103 amdgpu_fence_process(ring); 9104 return 0; 9105 } 9106 9107 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9108 { 9109 const unsigned int gcr_cntl = 9110 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9111 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9112 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9113 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9114 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9115 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9116 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9117 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9118 9119 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9120 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9121 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9122 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9123 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9124 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9125 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9126 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9127 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9128 } 9129 9130 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9131 .name = "gfx_v10_0", 9132 .early_init = gfx_v10_0_early_init, 9133 .late_init = gfx_v10_0_late_init, 9134 .sw_init = gfx_v10_0_sw_init, 9135 .sw_fini = gfx_v10_0_sw_fini, 9136 .hw_init = gfx_v10_0_hw_init, 9137 .hw_fini = gfx_v10_0_hw_fini, 9138 .suspend = gfx_v10_0_suspend, 9139 .resume = gfx_v10_0_resume, 9140 .is_idle = gfx_v10_0_is_idle, 9141 .wait_for_idle = gfx_v10_0_wait_for_idle, 9142 .soft_reset = gfx_v10_0_soft_reset, 9143 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9144 .set_powergating_state = gfx_v10_0_set_powergating_state, 9145 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9146 }; 9147 9148 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9149 .type = AMDGPU_RING_TYPE_GFX, 9150 .align_mask = 0xff, 9151 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9152 .support_64bit_ptrs = true, 9153 .secure_submission_supported = true, 9154 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9155 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9156 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9157 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9158 5 + /* COND_EXEC */ 9159 7 + /* PIPELINE_SYNC */ 9160 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9161 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9162 2 + /* VM_FLUSH */ 9163 8 + /* FENCE for VM_FLUSH */ 9164 20 + /* GDS switch */ 9165 4 + /* double SWITCH_BUFFER, 9166 * the first COND_EXEC jump to the place 9167 * just prior to this double SWITCH_BUFFER 9168 */ 9169 5 + /* COND_EXEC */ 9170 7 + /* HDP_flush */ 9171 4 + /* VGT_flush */ 9172 14 + /* CE_META */ 9173 31 + /* DE_META */ 9174 3 + /* CNTX_CTRL */ 9175 5 + /* HDP_INVL */ 9176 8 + 8 + /* FENCE x2 */ 9177 2 + /* SWITCH_BUFFER */ 9178 8, /* gfx_v10_0_emit_mem_sync */ 9179 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9180 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9181 .emit_fence = gfx_v10_0_ring_emit_fence, 9182 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9183 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9184 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9185 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9186 .test_ring = gfx_v10_0_ring_test_ring, 9187 .test_ib = gfx_v10_0_ring_test_ib, 9188 .insert_nop = amdgpu_ring_insert_nop, 9189 .pad_ib = amdgpu_ring_generic_pad_ib, 9190 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9191 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9192 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9193 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9194 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9195 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9196 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9197 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9198 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9199 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9200 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9201 }; 9202 9203 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9204 .type = AMDGPU_RING_TYPE_COMPUTE, 9205 .align_mask = 0xff, 9206 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9207 .support_64bit_ptrs = true, 9208 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9209 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9210 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9211 .emit_frame_size = 9212 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9213 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9214 5 + /* hdp invalidate */ 9215 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9216 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9217 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9218 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9219 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9220 8, /* gfx_v10_0_emit_mem_sync */ 9221 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9222 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9223 .emit_fence = gfx_v10_0_ring_emit_fence, 9224 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9225 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9226 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9227 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9228 .test_ring = gfx_v10_0_ring_test_ring, 9229 .test_ib = gfx_v10_0_ring_test_ib, 9230 .insert_nop = amdgpu_ring_insert_nop, 9231 .pad_ib = amdgpu_ring_generic_pad_ib, 9232 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9233 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9234 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9235 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9236 }; 9237 9238 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9239 .type = AMDGPU_RING_TYPE_KIQ, 9240 .align_mask = 0xff, 9241 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9242 .support_64bit_ptrs = true, 9243 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9244 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9245 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9246 .emit_frame_size = 9247 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9248 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9249 5 + /*hdp invalidate */ 9250 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9251 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9252 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9253 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9254 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9255 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9256 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9257 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9258 .test_ring = gfx_v10_0_ring_test_ring, 9259 .test_ib = gfx_v10_0_ring_test_ib, 9260 .insert_nop = amdgpu_ring_insert_nop, 9261 .pad_ib = amdgpu_ring_generic_pad_ib, 9262 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9263 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9264 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9265 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9266 }; 9267 9268 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9269 { 9270 int i; 9271 9272 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9273 9274 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9275 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9276 9277 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9278 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9279 } 9280 9281 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9282 .set = gfx_v10_0_set_eop_interrupt_state, 9283 .process = gfx_v10_0_eop_irq, 9284 }; 9285 9286 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9287 .set = gfx_v10_0_set_priv_reg_fault_state, 9288 .process = gfx_v10_0_priv_reg_irq, 9289 }; 9290 9291 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9292 .set = gfx_v10_0_set_priv_inst_fault_state, 9293 .process = gfx_v10_0_priv_inst_irq, 9294 }; 9295 9296 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9297 .set = gfx_v10_0_kiq_set_interrupt_state, 9298 .process = gfx_v10_0_kiq_irq, 9299 }; 9300 9301 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9302 { 9303 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9304 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9305 9306 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9307 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9308 9309 adev->gfx.priv_reg_irq.num_types = 1; 9310 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9311 9312 adev->gfx.priv_inst_irq.num_types = 1; 9313 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9314 } 9315 9316 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9317 { 9318 switch (adev->ip_versions[GC_HWIP][0]) { 9319 case IP_VERSION(10, 1, 10): 9320 case IP_VERSION(10, 1, 1): 9321 case IP_VERSION(10, 1, 3): 9322 case IP_VERSION(10, 1, 4): 9323 case IP_VERSION(10, 3, 2): 9324 case IP_VERSION(10, 3, 1): 9325 case IP_VERSION(10, 3, 4): 9326 case IP_VERSION(10, 3, 5): 9327 case IP_VERSION(10, 3, 6): 9328 case IP_VERSION(10, 3, 3): 9329 case IP_VERSION(10, 3, 7): 9330 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9331 break; 9332 case IP_VERSION(10, 1, 2): 9333 case IP_VERSION(10, 3, 0): 9334 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9335 break; 9336 default: 9337 break; 9338 } 9339 } 9340 9341 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9342 { 9343 unsigned int total_cu = adev->gfx.config.max_cu_per_sh * 9344 adev->gfx.config.max_sh_per_se * 9345 adev->gfx.config.max_shader_engines; 9346 9347 adev->gds.gds_size = 0x10000; 9348 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9349 adev->gds.gws_size = 64; 9350 adev->gds.oa_size = 16; 9351 } 9352 9353 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9354 { 9355 /* set gfx eng mqd */ 9356 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9357 sizeof(struct v10_gfx_mqd); 9358 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9359 gfx_v10_0_gfx_mqd_init; 9360 /* set compute eng mqd */ 9361 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9362 sizeof(struct v10_compute_mqd); 9363 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9364 gfx_v10_0_compute_mqd_init; 9365 } 9366 9367 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9368 u32 bitmap) 9369 { 9370 u32 data; 9371 9372 if (!bitmap) 9373 return; 9374 9375 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9376 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9377 9378 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9379 } 9380 9381 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9382 { 9383 u32 disabled_mask = 9384 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9385 u32 efuse_setting = 0; 9386 u32 vbios_setting = 0; 9387 9388 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9389 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9390 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9391 9392 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9393 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9394 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9395 9396 disabled_mask |= efuse_setting | vbios_setting; 9397 9398 return (~disabled_mask); 9399 } 9400 9401 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9402 { 9403 u32 wgp_idx, wgp_active_bitmap; 9404 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9405 9406 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9407 cu_active_bitmap = 0; 9408 9409 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9410 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9411 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9412 if (wgp_active_bitmap & (1 << wgp_idx)) 9413 cu_active_bitmap |= cu_bitmap_per_wgp; 9414 } 9415 9416 return cu_active_bitmap; 9417 } 9418 9419 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9420 struct amdgpu_cu_info *cu_info) 9421 { 9422 int i, j, k, counter, active_cu_number = 0; 9423 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9424 unsigned int disable_masks[4 * 2]; 9425 9426 if (!adev || !cu_info) 9427 return -EINVAL; 9428 9429 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9430 9431 mutex_lock(&adev->grbm_idx_mutex); 9432 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9433 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9434 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9435 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 9436 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 9437 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) || 9438 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) && 9439 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9440 continue; 9441 mask = 1; 9442 ao_bitmap = 0; 9443 counter = 0; 9444 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 9445 if (i < 4 && j < 2) 9446 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9447 adev, disable_masks[i * 2 + j]); 9448 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9449 cu_info->bitmap[0][i][j] = bitmap; 9450 9451 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9452 if (bitmap & mask) { 9453 if (counter < adev->gfx.config.max_cu_per_sh) 9454 ao_bitmap |= mask; 9455 counter++; 9456 } 9457 mask <<= 1; 9458 } 9459 active_cu_number += counter; 9460 if (i < 2 && j < 2) 9461 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9462 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9463 } 9464 } 9465 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 9466 mutex_unlock(&adev->grbm_idx_mutex); 9467 9468 cu_info->number = active_cu_number; 9469 cu_info->ao_cu_mask = ao_cu_mask; 9470 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9471 9472 return 0; 9473 } 9474 9475 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9476 { 9477 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9478 9479 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9480 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9481 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9482 9483 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9484 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9485 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9486 9487 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9488 adev->gfx.config.max_shader_engines); 9489 disabled_sa = efuse_setting | vbios_setting; 9490 disabled_sa &= max_sa_mask; 9491 9492 return disabled_sa; 9493 } 9494 9495 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9496 { 9497 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9498 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9499 9500 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9501 9502 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9503 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9504 max_shader_engines = adev->gfx.config.max_shader_engines; 9505 9506 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9507 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9508 disabled_sa_per_se &= max_sa_per_se_mask; 9509 if (disabled_sa_per_se == max_sa_per_se_mask) { 9510 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9511 break; 9512 } 9513 } 9514 } 9515 9516 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9517 { 9518 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9519 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9520 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9521 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9522 9523 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9524 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9525 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9526 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9527 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9528 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9529 9530 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9531 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9532 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9533 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9534 9535 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9536 9537 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9538 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9539 } 9540 9541 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = { 9542 .type = AMD_IP_BLOCK_TYPE_GFX, 9543 .major = 10, 9544 .minor = 0, 9545 .rev = 0, 9546 .funcs = &gfx_v10_0_ip_funcs, 9547 }; 9548